From 1b6b1201a28428de604f82b22ec0e8dfdb6c2eaa Mon Sep 17 00:00:00 2001 From: aschi54 Date: Mon, 27 Dec 2010 13:20:36 +0000 Subject: [PATCH 001/127] --- FPGA_Quartus_13.1/Coldari1.qsf | 44 + FPGA_Quartus_13.1/DSP/DSP.vhd | 79 + FPGA_Quartus_13.1/DSP/DSP.vhd.bak | 79 + FPGA_Quartus_13.1/DSP/dsp56k.zip | Bin 0 -> 39208 bytes FPGA_Quartus_13.1/DSP/src/adgen_stage.vhd | 216 + FPGA_Quartus_13.1/DSP/src/constants_pkg.vhd | 62 + FPGA_Quartus_13.1/DSP/src/decode_stage.vhd | 1221 ++ FPGA_Quartus_13.1/DSP/src/exec_stage_alu.vhd | 603 + .../DSP/src/exec_stage_bit_modify.vhd | 79 + .../DSP/src/exec_stage_branch.vhd | 117 + .../DSP/src/exec_stage_cc_flag_calc.vhd | 75 + .../DSP/src/exec_stage_cr_mod.vhd | 72 + .../DSP/src/exec_stage_loops.vhd | 200 + FPGA_Quartus_13.1/DSP/src/fetch_stage.vhd | 60 + FPGA_Quartus_13.1/DSP/src/mem_control.vhd | 1519 +++ .../DSP/src/memory_management.vhd | 206 + FPGA_Quartus_13.1/DSP/src/parameter_pkg.vhd | 10 + FPGA_Quartus_13.1/DSP/src/pipeline.vhd | 968 ++ FPGA_Quartus_13.1/DSP/src/reg_file.vhd | 679 + FPGA_Quartus_13.1/DSP/src/types_pkg.vhd | 167 + .../FalconIO_SDCard_IDE_CF.vhd | 971 ++ .../FalconIO_SDCard_IDE_CF.vhd.bak | 971 ++ .../FalconIO_SDCard_IDE_CF_pgk.vhd | 406 + .../FalconIO_SDCard_IDE_CF_pgk.vhd.bak | 406 + .../WF5380/wf5380_control.vhd | 631 + .../WF5380/wf5380_pkg.vhd | 139 + .../WF5380/wf5380_registers.vhd | 265 + .../WF5380/wf5380_soc_top.vhd | 300 + .../WF5380/wf5380_top.vhd | 275 + .../WF_FDC1772_IP/wf1772ip_am_detector.vhd | 253 + .../WF_FDC1772_IP/wf1772ip_control.vhd | 1463 +++ .../WF_FDC1772_IP/wf1772ip_crc_logic.vhd | 162 + .../WF_FDC1772_IP/wf1772ip_digital_pll.vhd | 426 + .../WF_FDC1772_IP/wf1772ip_pkg.vhd | 232 + .../WF_FDC1772_IP/wf1772ip_registers.vhd | 264 + .../WF_FDC1772_IP/wf1772ip_top.vhd | 154 + .../WF_FDC1772_IP/wf1772ip_top_soc.vhd | 333 + .../WF_FDC1772_IP/wf1772ip_transceiver.vhd | 517 + .../WF_MFP68901_IP/wf68901ip_gpio.vhd | 141 + .../WF_MFP68901_IP/wf68901ip_interrupts.vhd | 391 + .../WF_MFP68901_IP/wf68901ip_pkg.vhd | 263 + .../WF_MFP68901_IP/wf68901ip_timers.vhd | 533 + .../WF_MFP68901_IP/wf68901ip_top.vhd | 213 + .../WF_MFP68901_IP/wf68901ip_top_soc.vhd | 309 + .../WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd | 191 + .../WF_MFP68901_IP/wf68901ip_usart_rx.vhd | 590 + .../WF_MFP68901_IP/wf68901ip_usart_top.vhd | 238 + .../WF_MFP68901_IP/wf68901ip_usart_tx.vhd | 387 + .../WF_SDC_IF/sd-card-interface.vhd | 228 + .../WF_SDC_IF/sd-card-interface_soc.vhd | 240 + .../WF_SDC_IF/sd-card-interface_soc.vhd.bak | 239 + .../WF_SND2149_IP/wf2149ip_pkg.vhd | 84 + .../WF_SND2149_IP/wf2149ip_top.vhd | 170 + .../WF_SND2149_IP/wf2149ip_top_soc.vhd | 229 + .../WF_SND2149_IP/wf2149ip_wave.vhd | 533 + .../WF_UART6850_IP/wf6850ip_ctrl_status.vhd | 244 + .../wf6850ip_ctrl_status.vhd.bak | 244 + .../WF_UART6850_IP/wf6850ip_receive.vhd | 415 + .../WF_UART6850_IP/wf6850ip_receive.vhd.bak | 415 + .../WF_UART6850_IP/wf6850ip_top.vhd | 135 + .../WF_UART6850_IP/wf6850ip_top_soc.vhd | 255 + .../WF_UART6850_IP/wf6850ip_top_soc.vhd.bak | 252 + .../WF_UART6850_IP/wf6850ip_transmit.vhd | 339 + .../WF_UART6850_IP/wf6850ip_transmit.vhd.bak | 339 + .../FalconIO_SDCard_IDE_CF/dcfifo0.bsf | 95 + .../FalconIO_SDCard_IDE_CF/dcfifo0.cmp | 28 + .../FalconIO_SDCard_IDE_CF/dcfifo0.qip | 5 + .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd | 202 + .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak | 202 + .../FalconIO_SDCard_IDE_CF/dcfifo1.bsf | 95 + .../FalconIO_SDCard_IDE_CF/dcfifo1.cmp | 28 + .../FalconIO_SDCard_IDE_CF/dcfifo1.qip | 5 + .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd | 202 + .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak | 202 + .../Interrupt_Handler/interrupt_handler.tdf | 478 + .../interrupt_handler.tdf.bak | 478 + FPGA_Quartus_13.1/UNUSED | 27 + FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 75 + .../Video/BLITTER/BLITTER.vhd.bak | 75 + FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 659 + FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak | 660 + .../Video/DDR_CTR_BLITTER.tdf.bak | 352 + FPGA_Quartus_13.1/Video/UNUSED | 267 + .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 675 + .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak | 675 + FPGA_Quartus_13.1/Video/Video.bdf | 10651 ++++++++++++++++ FPGA_Quartus_13.1/Video/altddio_bidir0.bsf | 99 + FPGA_Quartus_13.1/Video/altddio_bidir0.cmp | 29 + FPGA_Quartus_13.1/Video/altddio_bidir0.inc | 30 + FPGA_Quartus_13.1/Video/altddio_bidir0.ppf | 16 + FPGA_Quartus_13.1/Video/altddio_bidir0.qip | 7 + FPGA_Quartus_13.1/Video/altddio_bidir0.vhd | 172 + FPGA_Quartus_13.1/Video/altddio_out0.bsf | 64 + FPGA_Quartus_13.1/Video/altddio_out0.cmp | 24 + FPGA_Quartus_13.1/Video/altddio_out0.inc | 25 + FPGA_Quartus_13.1/Video/altddio_out0.ppf | 11 + FPGA_Quartus_13.1/Video/altddio_out0.qip | 7 + FPGA_Quartus_13.1/Video/altddio_out0.vhd | 136 + FPGA_Quartus_13.1/Video/altddio_out1.bsf | 64 + FPGA_Quartus_13.1/Video/altddio_out1.cmp | 24 + FPGA_Quartus_13.1/Video/altddio_out1.inc | 25 + FPGA_Quartus_13.1/Video/altddio_out1.ppf | 11 + FPGA_Quartus_13.1/Video/altddio_out1.qip | 7 + FPGA_Quartus_13.1/Video/altddio_out1.vhd | 146 + FPGA_Quartus_13.1/Video/altddio_out2.bsf | 64 + FPGA_Quartus_13.1/Video/altddio_out2.cmp | 24 + FPGA_Quartus_13.1/Video/altddio_out2.inc | 25 + FPGA_Quartus_13.1/Video/altddio_out2.ppf | 11 + FPGA_Quartus_13.1/Video/altddio_out2.qip | 7 + FPGA_Quartus_13.1/Video/altddio_out2.vhd | 136 + FPGA_Quartus_13.1/Video/altdpram0.bsf | 173 + FPGA_Quartus_13.1/Video/altdpram0.cmp | 30 + FPGA_Quartus_13.1/Video/altdpram0.inc | 31 + FPGA_Quartus_13.1/Video/altdpram0.qip | 6 + FPGA_Quartus_13.1/Video/altdpram0.vhd | 273 + FPGA_Quartus_13.1/Video/altdpram0_wave0.jpg | Bin 0 -> 125146 bytes FPGA_Quartus_13.1/Video/altdpram0_wave1.jpg | Bin 0 -> 171723 bytes .../Video/altdpram0_waveforms.html | 16 + FPGA_Quartus_13.1/Video/altdpram1.bsf | 173 + FPGA_Quartus_13.1/Video/altdpram1.cmp | 30 + FPGA_Quartus_13.1/Video/altdpram1.inc | 31 + FPGA_Quartus_13.1/Video/altdpram1.qip | 6 + FPGA_Quartus_13.1/Video/altdpram1.vhd | 273 + FPGA_Quartus_13.1/Video/altdpram1_wave0.jpg | Bin 0 -> 151954 bytes FPGA_Quartus_13.1/Video/altdpram1_wave1.jpg | Bin 0 -> 203609 bytes .../Video/altdpram1_waveforms.html | 16 + FPGA_Quartus_13.1/Video/altdpram2.bsf | 173 + FPGA_Quartus_13.1/Video/altdpram2.cmp | 30 + FPGA_Quartus_13.1/Video/altdpram2.inc | 31 + FPGA_Quartus_13.1/Video/altdpram2.qip | 6 + FPGA_Quartus_13.1/Video/altdpram2.vhd | 273 + FPGA_Quartus_13.1/Video/altdpram2_wave0.jpg | Bin 0 -> 152433 bytes FPGA_Quartus_13.1/Video/altdpram2_wave1.jpg | Bin 0 -> 204342 bytes .../Video/altdpram2_waveforms.html | 16 + FPGA_Quartus_13.1/Video/lpm_bustri0.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri0.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri0.inc | 24 + FPGA_Quartus_13.1/Video/lpm_bustri0.qip | 6 + FPGA_Quartus_13.1/Video/lpm_bustri0.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri1.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri1.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri1.qip | 5 + FPGA_Quartus_13.1/Video/lpm_bustri1.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri2.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri2.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri2.qip | 5 + FPGA_Quartus_13.1/Video/lpm_bustri2.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri3.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri3.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri3.qip | 5 + FPGA_Quartus_13.1/Video/lpm_bustri3.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri4.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri4.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri4.qip | 5 + FPGA_Quartus_13.1/Video/lpm_bustri4.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri5.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri5.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri5.inc | 24 + FPGA_Quartus_13.1/Video/lpm_bustri5.qip | 6 + FPGA_Quartus_13.1/Video/lpm_bustri5.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri6.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri6.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri6.qip | 5 + FPGA_Quartus_13.1/Video/lpm_bustri6.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_bustri7.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_bustri7.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_bustri7.qip | 5 + FPGA_Quartus_13.1/Video/lpm_bustri7.vhd | 107 + FPGA_Quartus_13.1/Video/lpm_compare1.bsf | 54 + FPGA_Quartus_13.1/Video/lpm_compare1.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_compare1.inc | 24 + FPGA_Quartus_13.1/Video/lpm_compare1.qip | 6 + FPGA_Quartus_13.1/Video/lpm_compare1.vhd | 127 + .../Video/lpm_compare1_wave0.jpg | Bin 0 -> 30655 bytes .../Video/lpm_compare1_waveforms.html | 13 + FPGA_Quartus_13.1/Video/lpm_constant0.bsf | 42 + FPGA_Quartus_13.1/Video/lpm_constant0.cmp | 21 + FPGA_Quartus_13.1/Video/lpm_constant0.qip | 5 + FPGA_Quartus_13.1/Video/lpm_constant0.vhd | 108 + FPGA_Quartus_13.1/Video/lpm_constant1.bsf | 42 + FPGA_Quartus_13.1/Video/lpm_constant1.cmp | 21 + FPGA_Quartus_13.1/Video/lpm_constant1.inc | 23 + FPGA_Quartus_13.1/Video/lpm_constant1.qip | 6 + FPGA_Quartus_13.1/Video/lpm_constant1.vhd | 108 + FPGA_Quartus_13.1/Video/lpm_constant2.bsf | 42 + FPGA_Quartus_13.1/Video/lpm_constant2.cmp | 21 + FPGA_Quartus_13.1/Video/lpm_constant2.qip | 5 + FPGA_Quartus_13.1/Video/lpm_constant2.vhd | 108 + FPGA_Quartus_13.1/Video/lpm_constant3.bsf | 42 + FPGA_Quartus_13.1/Video/lpm_constant3.cmp | 21 + FPGA_Quartus_13.1/Video/lpm_constant3.qip | 5 + FPGA_Quartus_13.1/Video/lpm_constant3.vhd | 108 + FPGA_Quartus_13.1/Video/lpm_constant4.bsf | 42 + FPGA_Quartus_13.1/Video/lpm_constant4.cmp | 21 + FPGA_Quartus_13.1/Video/lpm_constant4.inc | 23 + FPGA_Quartus_13.1/Video/lpm_constant4.qip | 6 + FPGA_Quartus_13.1/Video/lpm_constant4.vhd | 108 + FPGA_Quartus_13.1/Video/lpm_ff0.bsf | 63 + FPGA_Quartus_13.1/Video/lpm_ff0.cmp | 24 + FPGA_Quartus_13.1/Video/lpm_ff0.qip | 5 + FPGA_Quartus_13.1/Video/lpm_ff0.vhd | 127 + FPGA_Quartus_13.1/Video/lpm_ff1.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_ff1.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_ff1.qip | 5 + FPGA_Quartus_13.1/Video/lpm_ff1.vhd | 122 + FPGA_Quartus_13.1/Video/lpm_ff2.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_ff2.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_ff2.qip | 5 + FPGA_Quartus_13.1/Video/lpm_ff2.vhd | 122 + FPGA_Quartus_13.1/Video/lpm_ff3.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_ff3.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_ff3.qip | 5 + FPGA_Quartus_13.1/Video/lpm_ff3.vhd | 122 + FPGA_Quartus_13.1/Video/lpm_ff4.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_ff4.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_ff4.inc | 24 + FPGA_Quartus_13.1/Video/lpm_ff4.qip | 6 + FPGA_Quartus_13.1/Video/lpm_ff4.vhd | 122 + FPGA_Quartus_13.1/Video/lpm_ff5.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_ff5.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_ff5.inc | 24 + FPGA_Quartus_13.1/Video/lpm_ff5.qip | 6 + FPGA_Quartus_13.1/Video/lpm_ff5.vhd | 122 + FPGA_Quartus_13.1/Video/lpm_ff6.bsf | 63 + FPGA_Quartus_13.1/Video/lpm_ff6.cmp | 24 + FPGA_Quartus_13.1/Video/lpm_ff6.inc | 25 + FPGA_Quartus_13.1/Video/lpm_ff6.qip | 6 + FPGA_Quartus_13.1/Video/lpm_ff6.vhd | 127 + FPGA_Quartus_13.1/Video/lpm_fifoDZ.bsf | 79 + FPGA_Quartus_13.1/Video/lpm_fifoDZ.cmp | 26 + FPGA_Quartus_13.1/Video/lpm_fifoDZ.qip | 5 + FPGA_Quartus_13.1/Video/lpm_fifoDZ.vhd | 178 + FPGA_Quartus_13.1/Video/lpm_fifoDZ_wave0.jpg | Bin 0 -> 86257 bytes .../Video/lpm_fifoDZ_waveforms.html | 13 + FPGA_Quartus_13.1/Video/lpm_fifo_dc0.bsf | 102 + FPGA_Quartus_13.1/Video/lpm_fifo_dc0.cmp | 29 + FPGA_Quartus_13.1/Video/lpm_fifo_dc0.inc | 30 + FPGA_Quartus_13.1/Video/lpm_fifo_dc0.qip | 6 + FPGA_Quartus_13.1/Video/lpm_fifo_dc0.vhd | 203 + .../Video/lpm_fifo_dc0_wave0.jpg | Bin 0 -> 121926 bytes .../Video/lpm_fifo_dc0_waveforms.html | 13 + FPGA_Quartus_13.1/Video/lpm_latch1.bsf | 53 + FPGA_Quartus_13.1/Video/lpm_latch1.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_latch1.qip | 5 + FPGA_Quartus_13.1/Video/lpm_latch1.vhd | 110 + FPGA_Quartus_13.1/Video/lpm_mux0.bsf | 83 + FPGA_Quartus_13.1/Video/lpm_mux0.cmp | 27 + FPGA_Quartus_13.1/Video/lpm_mux0.inc | 28 + FPGA_Quartus_13.1/Video/lpm_mux0.qip | 6 + FPGA_Quartus_13.1/Video/lpm_mux0.vhd | 251 + FPGA_Quartus_13.1/Video/lpm_mux1.bsf | 111 + FPGA_Quartus_13.1/Video/lpm_mux1.cmp | 31 + FPGA_Quartus_13.1/Video/lpm_mux1.inc | 32 + FPGA_Quartus_13.1/Video/lpm_mux1.qip | 6 + FPGA_Quartus_13.1/Video/lpm_mux1.vhd | 271 + FPGA_Quartus_13.1/Video/lpm_mux2.bsf | 167 + FPGA_Quartus_13.1/Video/lpm_mux2.cmp | 39 + FPGA_Quartus_13.1/Video/lpm_mux2.inc | 40 + FPGA_Quartus_13.1/Video/lpm_mux2.qip | 6 + FPGA_Quartus_13.1/Video/lpm_mux2.vhd | 311 + FPGA_Quartus_13.1/Video/lpm_mux3.bsf | 60 + FPGA_Quartus_13.1/Video/lpm_mux3.cmp | 24 + FPGA_Quartus_13.1/Video/lpm_mux3.qip | 5 + FPGA_Quartus_13.1/Video/lpm_mux3.vhd | 115 + FPGA_Quartus_13.1/Video/lpm_mux4.bsf | 60 + FPGA_Quartus_13.1/Video/lpm_mux4.cmp | 24 + FPGA_Quartus_13.1/Video/lpm_mux4.qip | 5 + FPGA_Quartus_13.1/Video/lpm_mux4.vhd | 125 + FPGA_Quartus_13.1/Video/lpm_mux5.bsf | 74 + FPGA_Quartus_13.1/Video/lpm_mux5.cmp | 26 + FPGA_Quartus_13.1/Video/lpm_mux5.inc | 27 + FPGA_Quartus_13.1/Video/lpm_mux5.qip | 6 + FPGA_Quartus_13.1/Video/lpm_mux5.vhd | 373 + FPGA_Quartus_13.1/Video/lpm_mux6.bsf | 111 + FPGA_Quartus_13.1/Video/lpm_mux6.cmp | 31 + FPGA_Quartus_13.1/Video/lpm_mux6.inc | 32 + FPGA_Quartus_13.1/Video/lpm_mux6.qip | 6 + FPGA_Quartus_13.1/Video/lpm_mux6.vhd | 335 + FPGA_Quartus_13.1/Video/lpm_muxDZ.bsf | 76 + FPGA_Quartus_13.1/Video/lpm_muxDZ.cmp | 26 + FPGA_Quartus_13.1/Video/lpm_muxDZ.qip | 5 + FPGA_Quartus_13.1/Video/lpm_muxDZ.vhd | 377 + FPGA_Quartus_13.1/Video/lpm_muxDZ2.bsf | 60 + FPGA_Quartus_13.1/Video/lpm_muxDZ2.cmp | 24 + FPGA_Quartus_13.1/Video/lpm_muxDZ2.qip | 5 + FPGA_Quartus_13.1/Video/lpm_muxDZ2.vhd | 115 + FPGA_Quartus_13.1/Video/lpm_muxVDM.bsf | 158 + FPGA_Quartus_13.1/Video/lpm_muxVDM.cmp | 38 + FPGA_Quartus_13.1/Video/lpm_muxVDM.qip | 5 + FPGA_Quartus_13.1/Video/lpm_muxVDM.vhd | 2225 ++++ FPGA_Quartus_13.1/Video/lpm_shiftreg0.bsf | 70 + FPGA_Quartus_13.1/Video/lpm_shiftreg0.cmp | 25 + FPGA_Quartus_13.1/Video/lpm_shiftreg0.inc | 26 + FPGA_Quartus_13.1/Video/lpm_shiftreg0.qip | 6 + FPGA_Quartus_13.1/Video/lpm_shiftreg0.vhd | 135 + FPGA_Quartus_13.1/Video/lpm_shiftreg1.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_shiftreg1.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_shiftreg1.qip | 5 + FPGA_Quartus_13.1/Video/lpm_shiftreg1.vhd | 125 + FPGA_Quartus_13.1/Video/lpm_shiftreg2.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_shiftreg2.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_shiftreg2.qip | 5 + FPGA_Quartus_13.1/Video/lpm_shiftreg2.vhd | 125 + FPGA_Quartus_13.1/Video/lpm_shiftreg3.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_shiftreg3.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_shiftreg3.inc | 24 + FPGA_Quartus_13.1/Video/lpm_shiftreg3.qip | 6 + FPGA_Quartus_13.1/Video/lpm_shiftreg3.vhd | 125 + FPGA_Quartus_13.1/Video/lpm_shiftreg4.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_shiftreg4.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_shiftreg4.inc | 24 + FPGA_Quartus_13.1/Video/lpm_shiftreg4.qip | 6 + FPGA_Quartus_13.1/Video/lpm_shiftreg4.vhd | 125 + FPGA_Quartus_13.1/Video/lpm_shiftreg5.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_shiftreg5.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_shiftreg5.inc | 24 + FPGA_Quartus_13.1/Video/lpm_shiftreg5.qip | 6 + FPGA_Quartus_13.1/Video/lpm_shiftreg5.vhd | 125 + FPGA_Quartus_13.1/Video/lpm_shiftreg6.bsf | 56 + FPGA_Quartus_13.1/Video/lpm_shiftreg6.cmp | 23 + FPGA_Quartus_13.1/Video/lpm_shiftreg6.inc | 24 + FPGA_Quartus_13.1/Video/lpm_shiftreg6.qip | 6 + FPGA_Quartus_13.1/Video/lpm_shiftreg6.vhd | 125 + FPGA_Quartus_13.1/altddio_out0.bsf | 64 + FPGA_Quartus_13.1/altddio_out0.cmp | 24 + FPGA_Quartus_13.1/altddio_out0.inc | 25 + FPGA_Quartus_13.1/altddio_out0.ppf | 11 + FPGA_Quartus_13.1/altddio_out0.qip | 7 + FPGA_Quartus_13.1/altddio_out0.vhd | 146 + FPGA_Quartus_13.1/altddio_out3.bsf | 64 + FPGA_Quartus_13.1/altddio_out3.cmp | 24 + FPGA_Quartus_13.1/altddio_out3.inc | 25 + FPGA_Quartus_13.1/altddio_out3.ppf | 11 + FPGA_Quartus_13.1/altddio_out3.qip | 7 + FPGA_Quartus_13.1/altddio_out3.vhd | 146 + FPGA_Quartus_13.1/altpll0.bsf | 117 + FPGA_Quartus_13.1/altpll0.cmp | 26 + FPGA_Quartus_13.1/altpll0.inc | 27 + FPGA_Quartus_13.1/altpll0.ppf | 13 + FPGA_Quartus_13.1/altpll0.qip | 7 + FPGA_Quartus_13.1/altpll0.vhd | 477 + FPGA_Quartus_13.1/altpll0_waveforms.html | 10 + FPGA_Quartus_13.1/altpll1.bsf | 100 + FPGA_Quartus_13.1/altpll1.cmp | 25 + FPGA_Quartus_13.1/altpll1.inc | 26 + FPGA_Quartus_13.1/altpll1.ppf | 12 + FPGA_Quartus_13.1/altpll1.qip | 7 + FPGA_Quartus_13.1/altpll1.vhd | 423 + FPGA_Quartus_13.1/altpll1_waveforms.html | 10 + FPGA_Quartus_13.1/altpll2.bsf | 117 + FPGA_Quartus_13.1/altpll2.cmp | 26 + FPGA_Quartus_13.1/altpll2.inc | 27 + FPGA_Quartus_13.1/altpll2.ppf | 13 + FPGA_Quartus_13.1/altpll2.qip | 7 + FPGA_Quartus_13.1/altpll2.vhd | 477 + FPGA_Quartus_13.1/altpll2_waveforms.html | 10 + FPGA_Quartus_13.1/altpll3.bsf | 105 + FPGA_Quartus_13.1/altpll3.cmp | 25 + FPGA_Quartus_13.1/altpll3.inc | 26 + FPGA_Quartus_13.1/altpll3.ppf | 12 + FPGA_Quartus_13.1/altpll3.qip | 7 + FPGA_Quartus_13.1/altpll3.vhd | 445 + FPGA_Quartus_13.1/altpll3_waveforms.html | 10 + FPGA_Quartus_13.1/altpll4.bsf | 125 + FPGA_Quartus_13.1/altpll4.cmp | 30 + FPGA_Quartus_13.1/altpll4.inc | 31 + FPGA_Quartus_13.1/altpll4.mif | 174 + FPGA_Quartus_13.1/altpll4.ppf | 17 + FPGA_Quartus_13.1/altpll4.qip | 7 + FPGA_Quartus_13.1/altpll4.tdf | 298 + FPGA_Quartus_13.1/altpll_reconfig0.bsf | 162 + FPGA_Quartus_13.1/altpll_reconfig0.qip | 5 + FPGA_Quartus_13.1/altpll_reconfig1.bsf | 162 + FPGA_Quartus_13.1/altpll_reconfig1.cmp | 38 + FPGA_Quartus_13.1/altpll_reconfig1.inc | 39 + FPGA_Quartus_13.1/altpll_reconfig1.qip | 6 + FPGA_Quartus_13.1/altpll_reconfig1.tdf | 144 + .../altpll_reconfig1_pllrcfg_bju.tdf | 583 + .../altpll_reconfig1_pllrcfg_t4q.tdf | 582 + FPGA_Quartus_13.1/firebee1.asm.rpt | 128 + FPGA_Quartus_13.1/firebee1.bdf | 5837 +++++++++ FPGA_Quartus_13.1/firebee1.done | 1 + FPGA_Quartus_13.1/firebee1.dpf | 12 + FPGA_Quartus_13.1/firebee1.fit.rpt | 6866 ++++++++++ FPGA_Quartus_13.1/firebee1.fit.summary | 16 + FPGA_Quartus_13.1/firebee1.flow.rpt | 380 + FPGA_Quartus_13.1/firebee1.map.rpt | 8590 +++++++++++++ FPGA_Quartus_13.1/firebee1.map.summary | 14 + FPGA_Quartus_13.1/firebee1.pin | 557 + FPGA_Quartus_13.1/firebee1.qsf | 740 ++ FPGA_Quartus_13.1/firebee1.qws | 4 + FPGA_Quartus_13.1/firebee1.rbf | Bin 0 -> 428953 bytes FPGA_Quartus_13.1/firebee1.sof | Bin 0 -> 1171297 bytes FPGA_Quartus_13.1/firebee1.tan.rpt | 6936 ++++++++++ FPGA_Quartus_13.1/firebee1.tan.summary | 296 + .../firebee1_assignment_defaults.qdf | 687 + FPGA_Quartus_13.1/firebeei1.qpf | 23 + FPGA_Quartus_13.1/firebeei1.qws | 27 + FPGA_Quartus_13.1/lpm_bustri_BYT.bsf | 56 + FPGA_Quartus_13.1/lpm_bustri_BYT.cmp | 23 + FPGA_Quartus_13.1/lpm_bustri_BYT.inc | 24 + FPGA_Quartus_13.1/lpm_bustri_BYT.qip | 6 + FPGA_Quartus_13.1/lpm_bustri_BYT.vhd | 107 + FPGA_Quartus_13.1/lpm_bustri_LONG.bsf | 56 + FPGA_Quartus_13.1/lpm_bustri_LONG.cmp | 23 + FPGA_Quartus_13.1/lpm_bustri_LONG.inc | 24 + FPGA_Quartus_13.1/lpm_bustri_LONG.qip | 6 + FPGA_Quartus_13.1/lpm_bustri_LONG.vhd | 107 + FPGA_Quartus_13.1/lpm_bustri_WORD.bsf | 56 + FPGA_Quartus_13.1/lpm_bustri_WORD.cmp | 23 + FPGA_Quartus_13.1/lpm_bustri_WORD.inc | 24 + FPGA_Quartus_13.1/lpm_bustri_WORD.qip | 6 + FPGA_Quartus_13.1/lpm_bustri_WORD.vhd | 107 + FPGA_Quartus_13.1/lpm_counter0.bsf | 49 + FPGA_Quartus_13.1/lpm_counter0.cmp | 22 + FPGA_Quartus_13.1/lpm_counter0.qip | 5 + FPGA_Quartus_13.1/lpm_counter0.vhd | 126 + FPGA_Quartus_13.1/lpm_counter0_wave0.jpg | Bin 0 -> 56372 bytes FPGA_Quartus_13.1/lpm_counter0_waveforms.html | 13 + FPGA_Quartus_13.1/lpm_counter1_waveforms.html | 16 + FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html | 16 + FPGA_Quartus_13.1/lpm_latch0.bsf | 53 + FPGA_Quartus_13.1/lpm_latch0.cmp | 23 + FPGA_Quartus_13.1/lpm_latch0.qip | 5 + FPGA_Quartus_13.1/lpm_latch0.vhd | 110 + FPGA_Quartus_13.1/serv_req_info.txt | 115 + FPGA_Quartus_13.1/undo_redo.txt | 0 427 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FPGA_Quartus_13.1/DSP/src/memory_management.vhd create mode 100644 FPGA_Quartus_13.1/DSP/src/parameter_pkg.vhd create mode 100644 FPGA_Quartus_13.1/DSP/src/pipeline.vhd create mode 100644 FPGA_Quartus_13.1/DSP/src/reg_file.vhd create mode 100644 FPGA_Quartus_13.1/DSP/src/types_pkg.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd create 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FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd create mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd create mode 100644 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index 0000000..da581cf --- /dev/null +++ b/FPGA_Quartus_13.1/Coldari1.qsf @@ -0,0 +1,44 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2009 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 222 10/21/2009 SJ Web Edition +# Date created = 12:11:46 March 06, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# Coldari1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name DEVICE AUTO +set_global_assignment -name TOP_LEVEL_ENTITY Coldari1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46 MARCH 06, 2010" +set_global_assignment -name LAST_QUARTUS_VERSION 9.1 \ No newline at end of file diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd new file mode 100644 index 0000000..26f8e2e --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -0,0 +1,79 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:57 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY DSP IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nRSTO : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nSRCS : INOUT STD_LOGIC; + nSRBLE : OUT STD_LOGIC; + nSRBHE : OUT STD_LOGIC; + nSRWE : OUT STD_LOGIC; + nSROE : OUT STD_LOGIC; + DSP_INT : OUT STD_LOGIC; + DSP_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + IO : INOUT STD_LOGIC_VECTOR(17 downto 0); + SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END DSP; + + +-- Architecture Body + +ARCHITECTURE DSP_architecture OF DSP IS + + +BEGIN + nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; + nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; + nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + DSP_INT <= '0'; + DSP_TA <= '0'; + IO(17 downto 0) <= FB_ADR(18 downto 1); + SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + + +END DSP_architecture; diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd.bak b/FPGA_Quartus_13.1/DSP/DSP.vhd.bak new file mode 100644 index 0000000..2d4811a --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd.bak @@ -0,0 +1,79 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:57 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY DSP IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nRSTO : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nSRCS : OUT STD_LOGIC; + nSRBLE : OUT STD_LOGIC; + nSRBHE : OUT STD_LOGIC; + nSRWE : OUT STD_LOGIC; + nSROE : OUT STD_LOGIC; + DSP_INT : OUT STD_LOGIC; + DSP_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + IO : INOUT STD_LOGIC_VECTOR(17 downto 0); + SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END DSP; + + +-- Architecture Body + +ARCHITECTURE DSP_architecture OF DSP IS + + +BEGIN + nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; + nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; + nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + DSP_INT <= '0'; + DSP_TA <= '0'; + IO(17 downto 0) <= FB_ADR(18 downto 1); + SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; + + +END DSP_architecture; diff --git a/FPGA_Quartus_13.1/DSP/dsp56k.zip b/FPGA_Quartus_13.1/DSP/dsp56k.zip new file mode 100644 index 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activate_y_mem : in std_logic; + activate_l_mem : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + optional_ea_word : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + adgen_mode_a : in adgen_mode_type; + adgen_mode_b : in adgen_mode_type; + address_out_x : out unsigned(BW_ADDRESS-1 downto 0); + address_out_y : out unsigned(BW_ADDRESS-1 downto 0); + wr_R_port_A_valid : out std_logic; + wr_R_port_A : out addr_wr_port_type; + wr_R_port_B_valid : out std_logic; + wr_R_port_B : out addr_wr_port_type +); +end entity; + + +architecture rtl of adgen_stage is + + signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0); + + +begin + + address_out_x <= address_out_x_int; + + address_generator_X: process(activate_adgen, instr_word, register_file, adgen_mode_a) is + variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable op1 : unsigned(BW_ADDRESS-1 downto 0); + variable op2 : unsigned(BW_ADDRESS-1 downto 0); + variable addr_mod : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0); + variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0); + variable bit_set : std_logic; + begin + r_reg_local := register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8)))); + n_reg_local := register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8)))); + m_reg_local := register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8)))); + + -- select the operands for the calculation + case adgen_mode_a is + -- (Rn) - Nn + when POST_MIN_N => addr_mod := unsigned(- signed(n_reg_local)); + -- (Rn) + Nn + when POST_PLUS_N => addr_mod := n_reg_local; + -- (Rn)- + when POST_MIN_1 => addr_mod := (others => '1'); -- -1 + -- (Rn)+ + when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS); + -- (Rn) + when NOP => addr_mod := (others => '0'); + -- (Rn + Nn) + when INDEXED_N => addr_mod := n_reg_local; + -- -(Rn) + when PRE_MIN_1 => addr_mod := (others => '1'); -- - 1 + -- absolute address (appended to instruction word) + when ABSOLUTE => addr_mod := (others => '0'); + when IMMEDIATE => addr_mod := (others => '0'); + end case; + + op1 := r_reg_local; + op2 := addr_mod; + -- linear addressing + if m_reg_local = 2**BW_ADDRESS-1 then + op1 := r_reg_local; + op2 := addr_mod; + -- bit reverse operation + elsif m_reg_local = 0 then + -- reverse the input to the adder bit wise + -- so we just need to use a single adder + for i in 0 to BW_ADDRESS-1 loop + op1(BW_ADDRESS - 1 - i) := r_reg_local(i); + op2(BW_ADDRESS - 1 - i) := addr_mod(i); + end loop; + -- modulo arithmetic + else + bit_set := '0'; + for i in BW_ADDRESS-1 downto 0 loop + if m_reg_local(i) = '1' then + bit_set := '1'; + end if; + if bit_set = '1' then + modulo_bitmask(i) := '0'; + else + modulo_bitmask(i) := '1'; + end if; + end loop; + end if; + + new_r_reg_interm := op1 + op2; + + new_r_reg := new_r_reg_interm; + -- linear addressing + if m_reg_local = 2**BW_ADDRESS-1 then + new_r_reg := new_r_reg_interm; + -- bit reverse operation + elsif m_reg_local = 0 then + for i in 0 to BW_ADDRESS-1 loop + new_r_reg(BW_ADDRESS - 1 - i) := new_r_reg_interm(i); + end loop; + else + + end if; + + -- store the updated register in the global register file + -- do not store when we do nothing or there is nothing to update + -- LUA instructions DO NOT UPDATE the source register!! + if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then + wr_R_port_A_valid <= '0'; + else + wr_R_port_A_valid <= '1'; + end if; + wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8)); + wr_R_port_A.reg_value <= new_r_reg; + + -- select the output of the AGU + case adgen_mode_a is + -- (Rn) - Nn + when POST_MIN_N => address_out_x_int <= r_reg_local; + -- (Rn) + Nn + when POST_PLUS_N => address_out_x_int <= r_reg_local; + -- (Rn)- + when POST_MIN_1 => address_out_x_int <= r_reg_local; + -- (Rn)+ + when POST_PLUS_1 => address_out_x_int <= r_reg_local; + -- (Rn) + when NOP => address_out_x_int <= r_reg_local; + -- (Rn + Nn) + when INDEXED_N => address_out_x_int <= new_r_reg; + -- -(Rn) + when PRE_MIN_1 => address_out_x_int <= new_r_reg; + -- absolute address (appended to instruction word) + when ABSOLUTE => address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0)); + when IMMEDIATE => address_out_x_int <= r_reg_local; -- Done externally, value never used + end case; + -- LUA instructions only use the updated address! + if instr_array = INSTR_LUA then + address_out_x_int <= new_r_reg; + end if; + + end process address_generator_X; + + address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word, + register_file, adgen_mode_b, address_out_x_int) is + variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0); + variable op2 : unsigned(BW_ADDRESS-1 downto 0); + variable new_r_reg : unsigned(BW_ADDRESS-1 downto 0); + begin + r_reg_local := register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + n_reg_local := register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + m_reg_local := register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13)))); + + -- select the operands for the calculation + case adgen_mode_b is + -- (Rn) + Nn + when POST_PLUS_N => op2 := n_reg_local; + -- (Rn)- + when POST_MIN_1 => op2 := (others => '1'); -- -1 + -- (Rn)+ + when POST_PLUS_1 => op2 := to_unsigned(1, BW_ADDRESS); + -- (Rn) + when others => op2 := (others => '0'); + end case; + + new_r_reg := r_reg_local + op2; + -- TODO: USE modifier register! + + -- store the updated register in the global register file + -- do not store when we do nothing or there is nothing to update + if adgen_mode_b = NOP then + wr_R_port_B_valid <= '0'; + else + wr_R_port_B_valid <= '1'; + end if; + wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13)); + wr_R_port_B.reg_value <= new_r_reg; + + -- the address for the y memory is calculated in the first AGU if the x memory is not accessed! + -- so use the other output as address output for the y memory! + -- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!) + if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then + address_out_y <= address_out_x_int; + -- in any other case use the locally computed value + else + -- select the output of the AGU + case adgen_mode_b is + -- (Rn) + Nn + when POST_PLUS_N => address_out_y <= r_reg_local; + -- (Rn)- + when POST_MIN_1 => address_out_y <= r_reg_local; + -- (Rn)+ + when POST_PLUS_1 => address_out_y <= r_reg_local; + -- (Rn) + when others => address_out_y <= r_reg_local; + end case; + end if; + end process address_generator_Y; + +end architecture; diff --git a/FPGA_Quartus_13.1/DSP/src/constants_pkg.vhd b/FPGA_Quartus_13.1/DSP/src/constants_pkg.vhd new file mode 100644 index 0000000..4b8122d --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/constants_pkg.vhd @@ -0,0 +1,62 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + + +package constants_pkg is + + ------------------------- + -- Flags in CCR register + ------------------------- + constant C_FLAG : natural := 0; + constant V_FLAG : natural := 1; + constant Z_FLAG : natural := 2; + constant N_FLAG : natural := 3; + constant U_FLAG : natural := 4; + constant E_FLAG : natural := 5; + constant L_FLAG : natural := 6; + constant S_FLAG : natural := 7; + + ------------------- + -- Pipeline stages + ------------------- + constant ST_FETCH : natural := 0; + constant ST_FETCH2 : natural := 1; + constant ST_DECODE : natural := 2; + constant ST_ADGEN : natural := 3; + constant ST_EXEC : natural := 4; + + ---------------------- + -- Activation signals + ---------------------- + constant ACT_ADGEN : natural := 0; -- Run the address generator + constant ACT_ALU : natural := 1; -- Activation of ALU results in modification of the status register + constant ACT_EXEC_BRA : natural := 2; -- Branch (in execute stage) + constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage) + constant ACT_EXEC_LOOP : natural := 4; -- Loop instruction (REP, DO) + constant ACT_X_MEM_RD : natural := 5; -- Init read from X memory + constant ACT_Y_MEM_RD : natural := 6; -- Init read from Y memory + constant ACT_P_MEM_RD : natural := 7; -- Init read from P memory + constant ACT_X_MEM_WR : natural := 8; -- Init write to X memory + constant ACT_Y_MEM_WR : natural := 9; -- Init write to Y memory + constant ACT_P_MEM_WR : natural := 10; -- Init write to P memory + constant ACT_REG_RD : natural := 11; -- Read from register (6 bit addressing) + constant ACT_REG_WR : natural := 12; -- Write to register (6 bit addressing) + constant ACT_IMM_8BIT : natural := 13; -- 8 bit immediate operand (in instruction word) + constant ACT_IMM_12BIT : natural := 14; -- 12 bit immediate operand (in instruction word) + constant ACT_IMM_LONG : natural := 15; -- 24 bit immediate operant (in optional instruction word) + constant ACT_X_BUS_RD : natural := 16; -- Read data via X-bus (from x0,x1,a,b) + constant ACT_X_BUS_WR : natural := 17; -- Write data via X-bus (to x0,x1,a,b) + constant ACT_Y_BUS_RD : natural := 18; -- Read data via Y-bus (from y0,y1,a,b) + constant ACT_Y_BUS_WR : natural := 19; -- Write data via Y-bus (to y0,y1,a,b) + constant ACT_L_BUS_RD : natural := 20; -- Read data via L-bus (from a10, b10,x,y,a,b,ab,ba) + constant ACT_L_BUS_WR : natural := 21; -- Write data via L-bus (to a10, b10,x,y,a,b,ab,ba) + constant ACT_BIT_MOD_WR : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG) + constant ACT_REG_WR_CC : natural := 23; -- Write to register file conditionally (Tcc) + constant ACT_ALU_WR_CC : natural := 24; -- Write ALU result conditionally (Tcc) + constant ACT_NORM : natural := 25; -- NORM instruction needs special handling + +end package constants_pkg; diff --git a/FPGA_Quartus_13.1/DSP/src/decode_stage.vhd b/FPGA_Quartus_13.1/DSP/src/decode_stage.vhd new file mode 100644 index 0000000..0c62149 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/decode_stage.vhd @@ -0,0 +1,1221 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity decode_stage is port( + activate_dec : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + dble_word_instr : out std_logic; + instr_array : out instructions_type; + act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + reg_wr_addr : out std_logic_vector(5 downto 0); + reg_rd_addr : out std_logic_vector(5 downto 0); + x_bus_rd_addr : out std_logic_vector(1 downto 0); + x_bus_wr_addr : out std_logic_vector(1 downto 0); + y_bus_rd_addr : out std_logic_vector(1 downto 0); + y_bus_wr_addr : out std_logic_vector(1 downto 0); + l_bus_addr : out std_logic_vector(2 downto 0); + adgen_mode_a : out adgen_mode_type; + adgen_mode_b : out adgen_mode_type; + alu_ctrl : out alu_ctrl_type +); +end entity; + + +architecture rtl of decode_stage is + + signal instr_array_int : instructions_type; +-- signal activate_pm_int : std_logic; + type adgen_bittype_type is (NOP, SINGLE_X, SINGLE_X_SHORT, DOUBLE_X_Y); + -- SINGLE_X : MMMRRR + -- SINGLE_X_SHORT : MMRRR + -- DOUBLE_X_Y : mmrrMMRRR + signal adgen_bittype : adgen_bittype_type; + + signal ea_extension_available : std_logic; + + signal alu_tcc_decoded : std_logic; + signal alu_div_decoded : std_logic; + signal alu_norm_decoded : std_logic; + +begin + + + -- output the decoded instruction + instr_array <= instr_array_int; + + -- calculate whether this is a double word instruction + dble_word_instr <= '1' when ea_extension_available = '1' or + instr_array_int = INSTR_DO or + instr_array_int = INSTR_JCLR or + instr_array_int = INSTR_JSCLR or + instr_array_int = INSTR_JSET or + instr_array_int = INSTR_JSSET else + '0'; + + alu_instruction_decoder: process(instr_word, activate_dec, alu_tcc_decoded, + alu_div_decoded, alu_norm_decoded) is + variable instr_word_var : std_logic_vector(23 downto 0); + begin + if activate_dec = '1' then + instr_word_var := instr_word; + else + instr_word_var := (others => '0'); + end if; + + alu_ctrl.mul_op1 <= (others => '0'); + alu_ctrl.mul_op2 <= (others => '0'); + alu_ctrl.rotate <= '0'; + alu_ctrl.div_instr <= '0'; + alu_ctrl.norm_instr <= '0'; + alu_ctrl.shift_src <= '0'; + alu_ctrl.shift_src_sign <= (others => '0'); + alu_ctrl.shift_mode <= ZEROS; + alu_ctrl.add_src_stage_1 <= (others => '0'); + alu_ctrl.add_src_stage_2 <= (others => '0'); + alu_ctrl.add_src_sign <= (others => '0'); + alu_ctrl.logic_function <= (others => '0'); + alu_ctrl.word_24_update <= '0'; + alu_ctrl.rounding_used <= (others => '0'); + alu_ctrl.store_result <= '0'; + for i in 0 to 7 loop -- by default do not touch any of the ccr flags (L;E;U;N;Z;V;C) + alu_ctrl.ccr_flags_ctrl(i) <= DONT_TOUCH; + end loop; + alu_ctrl.dst_accu <= instr_word_var(3); -- default value for all alu operations + + -- check wether instruction that allows parallel moves + -- has to be decoded, then it is an ALU operation in the 8 LSBs + -- Only exceptions are DIV, NORM, and Tcc + if instr_word_var(23 downto 20) /= "0000" then + -- ABS + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- source/dst are the same register + alu_ctrl.shift_src_sign <= "10"; -- the sign of the operand depends on the operand + -- negative operand will negate the content of the accu as + -- needed by the ABS instruction + alu_ctrl.add_src_stage_2 <= "00"; -- select zero + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags but carry + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADC + if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "001" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= "01" & instr_word_var(4); -- X or Y + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "10"; -- add carry to result of addition + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADD + if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "000" and instr_word_var(6 downto 4) /= "000" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADDL + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ADDR + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- AND / OR / EOR + if instr_word_var(7 downto 6) = "01" and (instr_word_var(2 downto 0) = "110" or -- and + instr_word_var(2 downto 0) = "010" or -- or + instr_word_var(2 downto 0) = "011") then -- eor + alu_ctrl.logic_function <= instr_word_var(2 downto 0); -- 000: none, 110: and, 010: or, 011: eor, 111: not + alu_ctrl.word_24_update <= '1'; -- only accumulator bits 47 downto 24 affected? + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- ASL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ASR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "010" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags +-- alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; +-- alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; +-- alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + -- set all flags, V-flag will be cleared due to shifting + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- CLR + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "011" then + -- Read accu + alu_ctrl.shift_mode <= ZEROS; + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- CMP + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(2 downto 0) = "101" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1 + else + alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.store_result <= '0'; -- do not store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- CMPM + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(2 downto 0) = "111" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "10"; -- with the sign dependant sign (magnitude!) + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1 + else + alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "10"; -- with sign dependant sign (magnitude!) + alu_ctrl.store_result <= '0'; -- do not store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- LSL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "011" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set N,Z,V,C flags + for i in 0 to 3 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- LSR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "011" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set N,Z,V,C flags + for i in 0 to 3 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- MPY, MPYR, MAC, MACR + if instr_word_var(7) = '1' then + case instr_word_var(6 downto 4) is + when "000" => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "00"; -- x0,x0 + when "001" => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "10"; -- y0,y0 + when "010" => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "00"; -- x1,x0 + when "011" => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "10"; -- y1,y0 + when "100" => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "11"; -- x0,y1 + when "101" => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "00"; -- y0,x0 + when "110" => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "10"; -- x1,y0 + when others => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "01"; -- y1,x1 + end case; + alu_ctrl.store_result <= '1'; -- store result in accu + alu_ctrl.add_src_stage_2 <= "10"; -- select mul out for adder! + alu_ctrl.add_src_sign <= '0' & instr_word_var(2); -- select +/- + alu_ctrl.rounding_used <= '0' & instr_word_var(0); -- rounding is determined by that bit! + if instr_word_var(1) = '0' then -- MPY(R) + alu_ctrl.shift_mode <= ZEROS; + else -- MAC(R) + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + end if; + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- NEG + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= ZEROS; +-- alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to +-- alu_ctrl.shift_src_sign <= "01"; -- with negative sign + -- Read Accu + alu_ctrl.add_src_stage_1 <= "000"; -- source register equal to dst_register + alu_ctrl.add_src_stage_2 <= "01"; -- select register as operand + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- NOT + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.logic_function <= instr_word_var(2 downto 0); -- select not operation + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set following flags + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + end if; + -- RND + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "001" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "01"; -- normal rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- ROL + if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + alu_ctrl.rotate <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set the following flags + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + end if; + -- ROR + if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "111" then + alu_ctrl.word_24_update <= '1'; + alu_ctrl.rotate <= '1'; + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand + -- set the following flags + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR; + alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY; + end if; + -- SBC + if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "101" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) X,Y + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "11"; -- subtract carry + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUB + if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "100" then + -- Read accu + alu_ctrl.shift_mode <= NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUBL + if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_LEFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- SUBR + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "110" then + -- Read accu + alu_ctrl.shift_mode <= SHIFT_RIGHT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with normal sign + -- Read S + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "01"; -- with negative sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- set all flags! + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + -- TFR + if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and + instr_word_var(6 downto 4) /= "001" and instr_word_var(2 downto 0) = "001" then + -- do not read accu + alu_ctrl.shift_mode <= ZEROS; + -- Read S + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + else + alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the register source + alu_ctrl.add_src_sign <= "00"; -- with positive sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '1'; -- store the result + -- do not set any flag at all! + end if; + -- TST + if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "011" then + -- do not read accu + alu_ctrl.shift_mode <= NO_SHIFT; -- no shift + alu_ctrl.shift_src <= instr_word_var(3); -- read source accu + alu_ctrl.shift_src_sign <= "00"; -- sign unchanged + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero + alu_ctrl.add_src_sign <= "00"; -- with positive sign + alu_ctrl.rounding_used <= "00"; -- no rounding needed + alu_ctrl.store_result <= '0'; -- do not store the result + -- set all flags but carry! + for i in 1 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + end if; + end if; -- Parallel move ALU instructions + + -- Tcc + if alu_tcc_decoded = '1' then + -- Read source + if instr_word_var(6) = '1' then + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + else + alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu) + end if; + alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source + -- The .store_result flag is generated in the execute stage + -- depending on the condition codes + -- do not set any flag at all! + end if; +--mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 +--mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 +--shift_src : std_logic; -- a,b +--shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved +--shift_mode : alu_shift_mode; +--add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b +--add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved +--add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: div instruction! +--logic_function : std_logic_vector(2 downto 0); -- 000: none, 110: and, 010: or, 011: eor, 111: not +--word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected? +--rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry +--store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator +--dst_accu : std_logic; -- 0: a, 1: b + -- DIV + if alu_div_decoded = '1' then + alu_ctrl.store_result <= '1'; -- do store the result + -- shifter operation + alu_ctrl.shift_mode <= SHIFT_LEFT; -- shift left + alu_ctrl.shift_src <= instr_word_var(3); -- read source accu + alu_ctrl.div_instr <= '1'; -- this is THE div instruction, special handling needed + -- source operand loading + alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) + alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source + alu_ctrl.add_src_sign <= "11"; -- div instruction, sign dependant on D[55] XOR S[23] + -- if 1: positive, if 0: negative + alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(V_FLAG) <= MODIFY; + alu_ctrl.ccr_flags_ctrl(L_FLAG) <= MODIFY; + end if; + -- NORM + if alu_norm_decoded = '1' then + -- set all alu-ctrl signals to ASL/ASR already here + -- depending on the condition code registers the flags + -- will be completed in the execute stage + alu_ctrl.norm_instr <= '1'; + -- Read accu + --alu_ctrl.shift_mode <= SHIFT_RIGHT/SHIFT_LEFT/NO_SHIFT; + alu_ctrl.shift_src <= instr_word_var(3); -- accumulate to the same register we want to write to + alu_ctrl.shift_src_sign <= "00"; -- with the original sign + -- Read S + alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand + alu_ctrl.add_src_sign <= "00"; -- with original sign + alu_ctrl.store_result <= '1'; -- store the result + alu_ctrl.rounding_used <= "00"; -- no rounding needed + -- set all flags, V-flag will be cleared due to shifting + for i in 0 to 7 loop + alu_ctrl.ccr_flags_ctrl(i) <= MODIFY; + end loop; + + end if; + end process; + + + instruction_decoder: process(instr_word, activate_dec) is + variable instr_word_var : std_logic_vector(23 downto 0); + procedure activate_AGU is + begin + -- check for immediate long addressing + if instr_word_var(13 downto 8) = "110100" then + act_array(ACT_IMM_LONG) <= '1'; + act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing! + act_array(ACT_Y_MEM_RD) <= '0'; + act_array(ACT_X_MEM_WR) <= '0'; + act_array(ACT_Y_MEM_WR) <= '0'; + else + act_array(ACT_ADGEN) <= '1'; + end if; + end procedure activate_AGU; + begin + instr_array_int <= INSTR_NOP; + act_array <= (others => '0'); + adgen_bittype <= NOP; + reg_rd_addr <= (others => '0'); + reg_wr_addr <= (others => '0'); + x_bus_rd_addr <= (others => '0'); + x_bus_wr_addr <= (others => '0'); + y_bus_rd_addr <= (others => '0'); + y_bus_wr_addr <= (others => '0'); + l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16); + + alu_tcc_decoded <= '0'; + alu_div_decoded <= '0'; + alu_norm_decoded <= '0'; + + -- in case the decoding is not activated we insert a nop + if activate_dec = '1' then + instr_word_var := instr_word; + else + instr_word_var := (others => '0'); + end if; + + if instr_word_var(23 downto 16) = X"00" then + case instr_word_var(15 downto 0) is + when X"0000" => instr_array_int <= INSTR_NOP; + when X"0004" => instr_array_int <= INSTR_RTI; act_array(ACT_EXEC_BRA) <= '1'; + when X"0005" => instr_array_int <= INSTR_ILLEGAL; + when X"0006" => instr_array_int <= INSTR_SWI; + when X"000C" => instr_array_int <= INSTR_RTS; act_array(ACT_EXEC_BRA) <= '1'; + when X"0084" => instr_array_int <= INSTR_RESET; + when X"0086" => instr_array_int <= INSTR_WAIT; + when X"0087" => instr_array_int <= INSTR_STOP; + when X"008C" => instr_array_int <= INSTR_ENDDO; + act_array(ACT_EXEC_LOOP) <= '1'; + when others => + act_array(ACT_EXEC_CR_MOD) <= '1'; -- modify control register + if instr_word_var(7 downto 2) = "101110" then + instr_array_int <= INSTR_ANDI; + elsif instr_word_var(7 downto 2) = "111110" then + instr_array_int <= INSTR_ORI; + end if; + end case; + end if; + --------------------------------------------------------- + -- DIV and NORM + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"01" then + -- DIV + if instr_word_var(15 downto 6) = "1000000001" and instr_word_var(2 downto 0) = "000" then + alu_div_decoded <= '1'; + act_array(ACT_ALU) <= '1'; -- force ALU to update status register + end if; + -- NORM + if instr_word_var(15 downto 11) = "11011" and instr_word_var(7 downto 4) = "0001" and + instr_word_var(2 downto 0) = "101" then + alu_norm_decoded <= '1'; + act_array(ACT_NORM) <= '1'; -- NORM instruction decoded, + -- special handling in exec-stage is caused + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn + end if; + end if; + --------------------------------------------------------- + -- Tcc + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"02" or instr_word_var(23 downto 16) = X"03" then + -- Tcc S1, D1 S2, D2 (ALU/Reg file) + if instr_word_var(16) = '0' and instr_word_var(11 downto 7) = "00000" and + instr_word_var(2 downto 0) = "000" then + act_array(ACT_ALU_WR_CC) <= '1'; + alu_tcc_decoded <= '1'; + -- Tcc S1, D1 S2, D2 (ALU/Reg file) + elsif instr_word_var(16) = '1' and instr_word_var(11) = '0' and + instr_word_var(7) = '0' then + act_array(ACT_ALU_WR_CC) <= '1'; + alu_tcc_decoded <= '1'; + act_array(ACT_REG_WR_CC) <= '1'; + reg_rd_addr <= "010" & instr_word_var(10 downto 8); -- Read Rn + reg_wr_addr <= "010" & instr_word_var( 2 downto 0); -- Write to other Rn + end if; + end if; + --------------------------------------------------------- + -- MOVEC and LUA instruction with registers + --------------------------------------------------------- + if instr_word_var(23 downto 16) = X"04" then + act_array(ACT_REG_WR) <= '1'; + -- LUA instruction + if instr_word_var(15 downto 13) = "010" and instr_word_var(7 downto 4) = "0001" then + instr_array_int <= INSTR_LUA; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X_SHORT; + reg_wr_addr <= instr_word_var(5 downto 0); + end if; + -- MOVEC instruction (S1, D2) or (S2, D1) + if instr_word_var(14) = '1' and instr_word_var(7 downto 5) = "101" then + instr_array_int <= INSTR_MOVEC; + act_array(ACT_REG_RD) <= '1'; + -- Write D1 + if instr_word_var(15) = '1' then + reg_wr_addr <= instr_word_var(5 downto 0); + reg_rd_addr <= instr_word_var(13 downto 8); + -- Read S1 + else + reg_wr_addr <= instr_word_var(13 downto 8); + reg_rd_addr <= instr_word_var(5 downto 0); + end if; + end if; + end if; + ------------------------------------------------------------------------- + -- MOVEC instruction with memory access/absolute address + ------------------------------------------------------------------------- + if instr_word_var(23 downto 16) = X"05" and + instr_word_var(7) = '0' and instr_word_var(5) = '1' then + + instr_array_int <= INSTR_MOVEC; + -- read from memory, write to register + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + -- X Memory read? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- Y Memory read? + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + -- write to memory, read register + else + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(5 downto 0); + -- X Memory write? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_WR) <= '1'; + -- Y Memory write? + else + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + -- AGU needed? + if instr_word_var(14) = '1' then + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- check for immediate long addressing + if instr_word_var(13 downto 8) = "110100" then + act_array(ACT_IMM_LONG) <= '1'; + act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing! + act_array(ACT_Y_MEM_RD) <= '0'; + act_array(ACT_X_MEM_WR) <= '0'; + act_array(ACT_Y_MEM_WR) <= '0'; + else + act_array(ACT_ADGEN) <= '1'; + end if; + else + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + ------------------------------------------------------------------------- + -- MOVEC instruction with immediate + ------------------------------------------------------------------------- + if instr_word_var(23 downto 16) = X"05" and instr_word_var(7 downto 5) = "101" then + instr_array_int <= INSTR_MOVEC; + act_array(ACT_IMM_8BIT) <= '1'; + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + end if; + --------------------------------- + -- REP or DO loop? + --------------------------------- + if instr_word_var(23 downto 16) = X"06" then + -- Instruction encoding is the same for both except of this bit + if instr_word_var(5) = '1' then + instr_array_int <= INSTR_REP; + else + instr_array_int <= INSTR_DO; + end if; + act_array(ACT_EXEC_LOOP) <= '1'; + -- Init reading of loop counter from memory + if instr_word_var(15) = '0' and instr_word_var(7) = '0' then + -- X/Y: ea? + if instr_word_var(14) = '1' then + act_array(ACT_ADGEN) <= '1'; + end if; + -- X/Y: aa? + -- Done automatically in the ADGEN stage by testing whether the ADGEN unit activated or not! + -- If not the absolute address stored in the instruction word is used. + ------- + -- only a single memory access is required + adgen_bittype <= SINGLE_X; + -- X/Y as source? + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + elsif instr_word_var(15) = '1' and instr_word_var(7) = '0' then + -- S (register as source) + reg_rd_addr <= instr_word_var(13 downto 8); + act_array(ACT_REG_RD) <= '1'; + -- #xxx ,12 bit immediate + elsif instr_word_var(7 downto 6) = "10" and instr_word_var(4) = '0' then + act_array(ACT_IMM_12BIT) <= '1'; + end if; + end if; + -------------------------------- + -- MOVEM (Program memory move) + -------------------------------- + if instr_word_var(23 downto 16) = X"07" then + -- read memory, write reg + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= instr_word_var(5 downto 0); + act_array(ACT_P_MEM_RD) <= '1'; + -- read reg, write memory + elsif instr_word_var(15) = '0' then + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= instr_word_var(5 downto 0); + act_array(ACT_P_MEM_WR) <= '1'; + end if; + -- AGU needed? + if instr_word_var(14) = '1' and instr_word_var(7 downto 6) = "10" then + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + elsif instr_word_var(14) = '0' and instr_word_var(7 downto 6) = "00" then + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + -------------------------------- + -- MOVEP (Peripheral memory move) + -------------------------------- + if instr_word_var(23 downto 16) = "0000100-" then + -- TODO?? Why parallel moves in software model?? + case instr_word_var(15 downto 0) is +-- when "-1------1-------" => instr_array_int(INSTR_MOVEP) <= '1'; +-- when "-1------01------" => instr_array_int(INSTR_MOVEP) <= '1'; +-- when "-1------00------" => instr_array_int(INSTR_MOVEP) <= '1'; + when others => + end case; + end if; + -- BSET, BCLR, BCHG, BTST, JCLR, JSET, JSCLR, JSSET, JMP, JCC, JSCC, JSR + if instr_word_var(23 downto 16) = X"0A" or instr_word_var(23 downto 16) = X"0B" then + + reg_rd_addr <= instr_word_var(13 downto 8); + reg_wr_addr <= instr_word_var(13 downto 8); + + if instr_word_var(16) = '0' then + if instr_word_var(7) = '0' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_BCLR; + elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_BSET; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_JCLR; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_JSET; + end if; + elsif instr_word_var(16) = '1' then + if instr_word_var(7) = '0' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_BCHG; + elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_BTST; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then + instr_array_int <= INSTR_JSCLR; + elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then + instr_array_int <= INSTR_JSSET; + end if; + end if; + if instr_word_var(7) = '1' then + act_array(ACT_EXEC_BRA) <= '1'; + end if; + + -- memory access? + if instr_word_var(15) = '0' then + -- X: + if instr_word_var(6) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_X_MEM_WR) <= '1'; + end if; + -- Y: + else + act_array(ACT_Y_MEM_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + end if; + + case instr_word_var(15 downto 14) is + -- X:/Y: aa + when "00" => + + -- X:/Y: ea + when "01" => + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + + -- X:/Y: pp + -- TODO! + when "10" => + + when others => -- "11" + if instr_word_var(7 downto 0) = "10000000" then + -- JMP/JSR ea + act_array(ACT_EXEC_BRA) <= '1'; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + if instr_word_var(16) = '0' then + instr_array_int <= INSTR_JMP; + elsif instr_word_var(16) = '1' then + instr_array_int <= INSTR_JSR; + end if; + elsif instr_word_var(7 downto 4) = "1010" then + -- JCC/JSCC ea + act_array(ACT_EXEC_BRA) <= '1'; + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X; + if instr_word_var(16) = '0' then + instr_array_int <= INSTR_JCC; + elsif instr_word_var(16) = '1' then + instr_array_int <= INSTR_JSCC; + end if; + -- JSCLR,JSET,JCLR,JSSET,BTST,BCLR,BSET,BCHG S/D + else + act_array(ACT_REG_RD) <= '1'; + -- if not a jump instruction and not BTST write back the result + if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then + act_array(ACT_REG_WR) <= '1'; + end if; + end if; + end case; + end if; + -- JMP xxx (absoulute short) + if instr_word_var(23 downto 16) = X"0C" then + if instr_word_var(15 downto 12) = "0000" then + instr_array_int <= INSTR_JMP; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + end if; + -- JSR xxx (absolute short) + if instr_word_var(23 downto 16) = X"0D" then + if instr_word_var(15 downto 12) = "0000" then + instr_array_int <= INSTR_JSR; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + end if; + -- JCC xxx (absolute short) + if instr_word_var(23 downto 16) = X"0E" then + instr_array_int <= INSTR_JCC; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + -- JSCC xxx (absolute short) + if instr_word_var(23 downto 16) = X"0F" then + instr_array_int <= INSTR_JSCC; + act_array(ACT_EXEC_BRA) <= '1'; + end if; + + ------------------------------------------------ + -- PARALLEL MOVE SECTION!! + ------------------------------------------------ + -- Here are the ALU operations that allow for parallel moves + if instr_word_var(23 downto 20) /= "0000" then + act_array(ACT_ALU) <= '1'; -- force ALU to update status register + end if; + -- PM: I + if instr_word_var(23 downto 21) = "001" and instr_word_var(20 downto 18) /= "000" then + act_array(ACT_IMM_8BIT) <= '1'; + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(20 downto 16); + end if; + -- PM: R + if instr_word_var(23 downto 18) = "001000" then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(12 downto 8); + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= '0' & instr_word_var(17 downto 13); + end if; + -- PM: U + if instr_word_var(23 downto 13) = "00100000010" then + act_array(ACT_ADGEN) <= '1'; + adgen_bittype <= SINGLE_X_SHORT; + end if; + -- PM: X or PM:Y + if instr_word_var(23 downto 22) = "01" and + -- Check whether L: type parallel move. If so do not enter this branch! + not (instr_word_var(21 downto 20) = "00" and instr_word_var(18) = '0') then + -- read memory, write reg + if instr_word_var(15) = '1' then + act_array(ACT_REG_WR) <= '1'; + reg_wr_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!! + -- X Memory read? + if instr_word_var(19) = '0' then + act_array(ACT_X_MEM_RD) <= '1'; + -- Y Memory read? + else + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + -- read reg, write memory + elsif instr_word_var(15) = '0' then + act_array(ACT_REG_RD) <= '1'; + reg_rd_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!! + -- X Memory write? + if instr_word_var(19) = '0' then + act_array(ACT_X_MEM_WR) <= '1'; + -- Y Memory write? + else + act_array(ACT_Y_MEM_WR) <= '1'; + end if; + end if; + -- AGU needed? + if instr_word_var(14) = '1' then + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + else + -- X:/Y:aa short is done in the adgen-stage automatically + end if; + end if; + -- PM: X:R or R:Y (Class I) + if instr_word_var(23 downto 20) = "0001" then + adgen_bittype <= SINGLE_X; + -- X:R + if instr_word_var(14) = '0' then + x_bus_rd_addr <= instr_word_var(19 downto 18); + x_bus_wr_addr <= instr_word_var(19 downto 18); + y_bus_rd_addr <= '1' & instr_word_var(17); + y_bus_wr_addr <= '0' & instr_word_var(16); -- TODO: Check encoding, manual uses three fs! + -- S2,D2 in any case! + act_array(ACT_Y_BUS_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + -- Write D1? + if instr_word_var(15) = '1' then + act_array(ACT_X_MEM_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + else + -- Read S1? + act_array(ACT_X_MEM_WR) <= '1'; + act_array(ACT_X_BUS_RD) <= '1'; + end if; + -- R:Y + elsif instr_word_var(14) = '1' then + x_bus_rd_addr <= '1' & instr_word_var(19); + x_bus_wr_addr <= '0' & instr_word_var(18); + y_bus_rd_addr <= instr_word_var(17 downto 16); + y_bus_wr_addr <= instr_word_var(17 downto 16); + -- S1,D1 in any case! + act_array(ACT_X_BUS_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + -- Write D1? + if instr_word_var(15) = '1' then + act_array(ACT_Y_MEM_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + else + -- Read S1? + act_array(ACT_Y_MEM_WR) <= '1'; + act_array(ACT_Y_BUS_RD) <= '1'; + end if; + + end if; + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + end if; + -- PM: X:R or R:Y (Class II) + if instr_word_var(23 downto 17) = "0000100" and instr_word_var(14) = '0' then + act_array(ACT_REG_RD) <= '1'; + -- X:R + if instr_word_var(15) = '0' then + reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B + act_array(ACT_X_MEM_WR) <= '1'; -- and store it in X memory + x_bus_rd_addr <= "00"; -- read x0 + x_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B + act_array(ACT_X_BUS_RD) <= '1'; + act_array(ACT_X_BUS_WR) <= '1'; + -- R:Y + elsif instr_word_var(15) = '1' then + reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B + act_array(ACT_Y_MEM_WR) <= '1'; -- and store it in Y memory + y_bus_rd_addr <= "00"; -- read y0 + y_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B + act_array(ACT_Y_BUS_RD) <= '1'; + act_array(ACT_Y_BUS_WR) <= '1'; + end if; + -- detect whether two word instruction! + adgen_bittype <= SINGLE_X; + -- activate AGU and test whether immediate data is used + activate_AGU; + end if; + -- PM: L: + l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16); + if instr_word_var(23 downto 20) = "0100" and instr_word_var(18) = '0' then + -- Read S? + if instr_word_var(15) = '0' then + act_array(ACT_L_BUS_RD) <= '1'; + act_array(ACT_X_MEM_WR) <= '1'; + act_array(ACT_Y_MEM_WR) <= '1'; + else -- Write D + act_array(ACT_L_BUS_WR) <= '1'; + act_array(ACT_X_MEM_RD) <= '1'; + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + if instr_word_var(14) = '1' then + adgen_bittype <= SINGLE_X; + activate_AGU; + else + -- L:aa automatically performed in ADGEN stage + end if; + end if; + -- PM: X: Y: + if instr_word_var(23) = '1' then + adgen_bittype <= DOUBLE_X_Y; + -- No immediate value allowed, so activate in any case! + act_array(ACT_ADGEN) <= '1'; + -- S1, X: + if instr_word_var(15) = '0' then + act_array(ACT_X_BUS_RD) <= '1'; + x_bus_rd_addr <= instr_word_var(19 downto 18); + act_array(ACT_X_MEM_WR) <= '1'; + -- X:, D1 + else + act_array(ACT_X_BUS_WR) <= '1'; + x_bus_wr_addr <= instr_word_var(19 downto 18); + act_array(ACT_X_MEM_RD) <= '1'; + end if; + -- S2, Y: + if instr_word_var(22) = '0' then + act_array(ACT_Y_BUS_RD) <= '1'; + y_bus_rd_addr <= instr_word_var(17 downto 16); + act_array(ACT_Y_MEM_WR) <= '1'; + -- Y:, D2 + else + act_array(ACT_Y_BUS_WR) <= '1'; + y_bus_wr_addr <= instr_word_var(17 downto 16); + act_array(ACT_Y_MEM_RD) <= '1'; + end if; + end if; + end process; + + adgen_decoder: process(adgen_bittype, instr_word) is + begin + adgen_mode_a <= NOP; + adgen_mode_b <= NOP; + ea_extension_available <= '0'; + + case adgen_bittype is + when SINGLE_X => + case instr_word(13 downto 11) is + when "000" => adgen_mode_a <= POST_MIN_N; + when "001" => adgen_mode_a <= POST_PLUS_N; + when "010" => adgen_mode_a <= POST_MIN_1; + when "011" => adgen_mode_a <= POST_PLUS_1; + when "100" => adgen_mode_a <= NOP; + when "101" => adgen_mode_a <= INDEXED_N; + when "111" => adgen_mode_a <= PRE_MIN_1; + when "110" => + if instr_word(10 downto 8) = "000" then + adgen_mode_a <= ABSOLUTE; + ea_extension_available <= '1'; + elsif instr_word(10 downto 8) = "100" then + adgen_mode_a <= IMMEDIATE; + ea_extension_available <= '1'; + else + adgen_mode_a <= NOP; -- INVALID OPCODE! + end if; + when others => + end case; + when SINGLE_X_SHORT => + case instr_word(12 downto 11) is + when "00" => adgen_mode_a <= POST_MIN_N; + when "01" => adgen_mode_a <= POST_PLUS_N; + when "10" => adgen_mode_a <= POST_MIN_1; + when "11" => adgen_mode_a <= POST_PLUS_1; + when others => + end case; + when DOUBLE_X_Y => + case instr_word(12 downto 11) is + when "00" => adgen_mode_a <= NOP; + when "01" => adgen_mode_a <= POST_PLUS_N; + when "10" => adgen_mode_a <= POST_MIN_1; + when "11" => adgen_mode_a <= POST_PLUS_1; + when others => + end case; + case instr_word(21 downto 20) is + when "00" => adgen_mode_b <= NOP; + when "01" => adgen_mode_b <= POST_PLUS_N; + when "10" => adgen_mode_b <= POST_MIN_1; + when "11" => adgen_mode_b <= POST_PLUS_1; + when others => + end case; + when others => + end case; + end process adgen_decoder; + +end architecture rtl; + diff --git a/FPGA_Quartus_13.1/DSP/src/exec_stage_alu.vhd b/FPGA_Quartus_13.1/DSP/src/exec_stage_alu.vhd new file mode 100644 index 0000000..9f3c3b9 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/exec_stage_alu.vhd @@ -0,0 +1,603 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_alu is port( + alu_activate : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + alu_ctrl : in alu_ctrl_type; + register_file : in register_file_type; + addr_r_in : in unsigned(BW_ADDRESS-1 downto 0); + addr_r_out : out unsigned(BW_ADDRESS-1 downto 0); + modify_accu : out std_logic; + dst_accu : out std_logic; + modified_accu : out signed(55 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + +architecture rtl of exec_stage_alu is + + signal alu_shifter_out : signed(55 downto 0); + signal alu_shifter_carry_out : std_logic; + signal alu_shifter_overflow_out : std_logic; + + signal alu_logic_conj : signed(55 downto 0); + signal alu_multiplier_out : signed(55 downto 0); + signal alu_src_op : signed(55 downto 0); + signal alu_add_result : signed(56 downto 0); + signal alu_add_carry_out : std_logic; + signal alu_post_adder_result : signed(56 downto 0); + + signal scaling_mode : std_logic_vector(1 downto 0); + + signal modified_accu_int : signed(55 downto 0); + + signal norm_instr_asl : std_logic; + signal norm_instr_asr : std_logic; + signal norm_instr_nop : std_logic; + signal norm_update_ccr : std_logic; + +begin + + + -- store calculated value? + modify_accu <= alu_ctrl.store_result; + modified_accu <= modified_accu_int; + -- for the norm instruction we first need to determine whether we have to + -- update the CCR register or not + modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else + norm_update_ccr; + dst_accu <= alu_ctrl.dst_accu; + + scaling_mode <= register_file.sr(11 downto 10); + + + calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out, + alu_post_adder_result, modified_accu_int, alu_add_carry_out) is + begin + -- by default do not modify the flags in the status register + modified_sr <= register_file.sr; + + -- Carry flag generation + ------------------------- + case alu_ctrl.ccr_flags_ctrl(C_FLAG) is + when CLEAR => modified_sr(C_FLAG) <= '0'; + when SET => modified_sr(C_FLAG) <= '1'; + when MODIFY => + -- the carry flag can stem from the shifter or from the post adder + -- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR) + -- take the carry flag from the shifter, else from the post adder + if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and + alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting? + modified_sr(C_FLAG) <= alu_shifter_carry_out; + elsif alu_ctrl.div_instr = '1' then + modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55)); + else +-- modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57)); + modified_sr(C_FLAG) <= alu_add_carry_out; + end if; + when others => -- Don't touch + end case; + + -- Overflow flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(V_FLAG) is + when CLEAR => modified_sr(V_FLAG) <= '0'; + when SET => modified_sr(V_FLAG) <= '1'; + when MODIFY => + -- There are two sources for the overflow flag: + -- 1) + -- in case the result cannot be represented using 56 bits set + -- the overflow flag. this is the case when the two MSBs of + -- the 57 bit result are different + -- 2) + -- The shifter circuit performs a 56 bit left shift. In case the + -- two MSBs of the operand are different set the overflow flag as well + if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or + (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and + alu_shifter_overflow_out = '1' ) then + modified_sr(V_FLAG) <= '1'; + else + modified_sr(V_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Zero flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is + when CLEAR => modified_sr(Z_FLAG) <= '0'; + when SET => modified_sr(Z_FLAG) <= '1'; + when MODIFY => + -- in case the result is zero set this flag + -- distinguish between 24 bit and 56 bit ALU operations + -- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND + if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or + (alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto 0) = 0) then + modified_sr(Z_FLAG) <= '1'; + else + modified_sr(Z_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Negative flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(N_FLAG) is + when CLEAR => modified_sr(N_FLAG) <= '0'; + when SET => modified_sr(N_FLAG) <= '1'; + when MODIFY => + -- in case the result is negative set this flag + -- distinguish between 24 bit and 56 bit ALU operations + -- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND + if alu_ctrl.word_24_update = '1' then + modified_sr(N_FLAG) <= std_logic(modified_accu_int(47)); + else + modified_sr(N_FLAG) <= std_logic(modified_accu_int(55)); + end if; + when others => -- Don't touch + end case; + + -- Unnormalized flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(U_FLAG) is + when CLEAR => modified_sr(U_FLAG) <= '0'; + when SET => modified_sr(U_FLAG) <= '1'; + when MODIFY => + -- Set unnormalized bit according to the scaling mode + if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or + (scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or + (scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then + modified_sr(U_FLAG) <= '1'; + else + modified_sr(U_FLAG) <= '0'; + end if; + when others => -- Don't touch + end case; + + -- Extension flag generation + ---------------------------- + case alu_ctrl.ccr_flags_ctrl(E_FLAG) is + when CLEAR => modified_sr(E_FLAG) <= '0'; + when SET => modified_sr(E_FLAG) <= '1'; + when MODIFY => + -- Set extension flag by default + modified_sr(E_FLAG) <= '1'; + -- Clear extension flag according to the scaling mode + case scaling_mode is + when "00" => + if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when "01" => + if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when "10" => + if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then + modified_sr(E_FLAG) <= '0'; + end if; + when others => + modified_sr(E_FLAG) <= '0'; + end case; + when others => -- Don't touch + end case; + + -- Limit flag generation (equals overflow flag generaton!) + -- Clearing of the Limit flag has to be done by the user! + ----------------------------------------------------------- + case alu_ctrl.ccr_flags_ctrl(L_FLAG) is + when CLEAR => modified_sr(L_FLAG) <= '0'; + when SET => modified_sr(L_FLAG) <= '1'; + when MODIFY => + -- There are two sources for the overflow flag: + -- 1) + -- in case the result cannot be represented using 56 bits set + -- the overflow flag. this is the case when the two MSBs of + -- the 57 bit result are different + -- 2) + -- The shifter circuit performs a 56 bit left shift. In case the + -- two MSBs of the operand are different set the overflow flag as well + if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or + (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and + alu_shifter_overflow_out = '1' ) then + modified_sr(L_FLAG) <= '1'; + end if; + when others => -- Don't touch + end case; + + -- Scaling flag generation (DSP56002 and up) + -------------------------------------------- + -- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB + + end process; + + + src_operand_select: process(register_file, alu_ctrl) is + begin + -- decoding according similar to JJJ representation + case alu_ctrl.add_src_stage_1 is + when "000" => + -- select depending on destination accu + if alu_ctrl.dst_accu = '0' then + alu_src_op <= register_file.a; + else + alu_src_op <= register_file.b; + end if; + when "001" => -- A,B or B,A + -- select depending on destination accu + if alu_ctrl.dst_accu = '0' then + alu_src_op <= register_file.b; + else + alu_src_op <= register_file.a; + end if; + when "010" => -- X + alu_src_op(55 downto 48) <= (others => register_file.x1(23)); + alu_src_op(47 downto 0) <= register_file.x1 & register_file.x0; + when "011" => -- Y + alu_src_op(55 downto 48) <= (others => register_file.y1(23)); + alu_src_op(47 downto 0) <= register_file.y1 & register_file.y0; + when "100" => -- x0 + alu_src_op(55 downto 48) <= (others => register_file.x0(23)); + alu_src_op(47 downto 24) <= register_file.x0; + alu_src_op(23 downto 0) <= (others => '0'); + when "101" => -- y0 + alu_src_op(55 downto 48) <= (others => register_file.y0(23)); + alu_src_op(47 downto 24) <= register_file.y0; + alu_src_op(23 downto 0) <= (others => '0'); + when "110" => -- x1 + alu_src_op(55 downto 48) <= (others => register_file.x1(23)); + alu_src_op(47 downto 24) <= register_file.x1; + alu_src_op(23 downto 0) <= (others => '0'); + when "111" => -- y1 + alu_src_op(55 downto 48) <= (others => register_file.y1(23)); + alu_src_op(47 downto 24) <= register_file.y1; + alu_src_op(23 downto 0) <= (others => '0'); + when others => + end case; + end process; + + alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is + begin + alu_logic_conj <= alu_shifter_out; + case alu_ctrl.logic_function is + when "110" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24); + when "010" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or alu_src_op(47 downto 24); + when "011" => + alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24); + when "111" => + alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24); + when others => + end case; + end process; + + alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is + variable add_src_op_1 : signed(56 downto 0); + variable add_src_op_2 : signed(56 downto 0); + variable carry_const : signed(56 downto 0); + variable alu_shifter_out_57 : signed(56 downto 0); + variable alu_add_result_58 : signed(57 downto 0); + variable alu_add_result_interm : signed(56 downto 0); + variable invert_carry_flag : std_logic; + begin + + -- by default do not invert the carry + invert_carry_flag := '0'; + + -- determine whether to use multiplier output, the operand defined above, or zeros! + -- resizing is done here already. Like that we can see whether an overflow + -- occurs due to negating the source operand + case alu_ctrl.add_src_stage_2 is + when "00" => add_src_op_1 := (others => '0'); + when "10" => add_src_op_1 := resize(alu_multiplier_out, 57); + when others => add_src_op_1 := resize(alu_src_op, 57); + end case; + + -- determine the sign for the 1st operand! + case alu_ctrl.add_src_sign is + -- normal operation + when "00" => add_src_op_1 := add_src_op_1; + -- negative sign + when "01" => add_src_op_1 := - add_src_op_1; + invert_carry_flag := not invert_carry_flag; + -- change according to sign + -- performs - | accu | for the CMPM instruction + when "10" => + -- we subtract in any case, so invert the carry! + invert_carry_flag := not invert_carry_flag; + if add_src_op_1(55) = '0' then + add_src_op_1 := - add_src_op_1; + else + add_src_op_1 := add_src_op_1; + end if; + -- div instruction! + -- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative + -- add_src_op_1 holds S[23] (sign extension!) + when others => + if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or + (alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then + add_src_op_1 := add_src_op_1; + else + add_src_op_1 := - add_src_op_1; +-- invert_carry_flag := not invert_carry_flag; + end if; + end case; + + alu_shifter_out_57 := resize(alu_shifter_out, 57); + + -- determine the sign for the 2nd operand (coming from the shifter)! + case alu_ctrl.shift_src_sign is + -- negative sign + when "01" => + add_src_op_2 := - alu_shifter_out_57; + -- change according to sign + -- this allows to build the magnitude (ABS, CMPM) + when "10" => + if alu_shifter_out(55) = '1' then + add_src_op_2 := - alu_shifter_out_57; + else + add_src_op_2 := alu_shifter_out_57; + end if; + when others => + add_src_op_2 := alu_shifter_out_57; + end case; + + -- determine whether carry flag has to be added or subtracted + if alu_ctrl.rounding_used = "10" then + -- add carry flag + carry_const(0) := register_file.sr(C_FLAG); + elsif alu_ctrl.rounding_used = "11" then + -- subtract carry flag + carry_const := (others => register_file.sr(0)); -- carry flag + else + carry_const := (others => '0'); + end if; + + -- add the values and calculate the carry bit + alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) + + ('0' & add_src_op_2(55 downto 0)) + + ('0' & carry_const(55 downto 0)); + + -- here pops the new carry out of the adder + if invert_carry_flag = '0' then + alu_add_carry_out <= alu_add_result_interm(56); + else + alu_add_carry_out <= not alu_add_result_interm(56); + end if; + + -- calculate the last bit (56), in order to test for overflow later on + alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0); +-- alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56); + alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) + xor carry_const(56) xor alu_add_result_interm(56); + + end process alu_adder; + + + -- Adder after the normal arithmetic adder + -- This adder is responsible for +-- -- 1) carry addition +-- -- 2) carry subtration + -- 3) convergent rounding + alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is + variable post_adder_constant : signed(56 downto 0); + variable testing_constant : signed(24 downto 0); + begin + -- by default add nothing + post_adder_constant := (others => '0'); + + case alu_ctrl.rounding_used is + -- rounding dependant on scaling bits + when "01" => + case scaling_mode is + -- no scaling + when "00" => testing_constant := alu_add_result(23 downto 0) & '0'; + -- scale down + when "01" => testing_constant := alu_add_result(24 downto 0); + -- scale up + when "10" => testing_constant := alu_add_result(22 downto 0) & "00"; + when others => + testing_constant := alu_add_result(23 downto 0) & '0'; + end case; + + -- Special case! + if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then + -- add depending on bit left to the rounding position + case scaling_mode is + -- no scaling + when "00" => post_adder_constant(23) := alu_add_result(24); + -- scale down + when "01" => post_adder_constant(24) := alu_add_result(25); + -- scale up + when "10" => post_adder_constant(22) := alu_add_result(23); + when others => + end case; + else -- testing_constant /= X"1000000" + -- add rounding constant depending on scaling mode + -- results in round up if MSB of testing constant is set, else nothing happens + case scaling_mode is + -- no scaling + when "00" => post_adder_constant(23) := '1'; + -- scale down + when "01" => post_adder_constant(24) := '1'; + -- scale up + when "10" => post_adder_constant(22) := '1'; + when others => + end case; + end if; + -- no rounding + when others => + post_adder_constant := (others => '0'); + + end case; + + -- Add the result of the first adder to the constant (e.g., carry flag) + alu_post_adder_result <= alu_add_result + post_adder_constant; + + -- When rounding is used set 24 LSBs to zero! + if alu_ctrl.rounding_used = "01" then + alu_post_adder_result(23 downto 0) <= (others => '0'); + end if; + end process; + + + + alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is + begin + if alu_ctrl.logic_function /= "000" then + modified_accu_int <= alu_logic_conj; + else + modified_accu_int <= alu_post_adder_result(55 downto 0); + end if; + end process; + + + -- contains the 24*24 bit fractional multiplier + alu_multiplier : process(register_file, alu_ctrl) is + variable src_op1: signed(23 downto 0); + variable src_op2: signed(23 downto 0); + variable mul_result_interm : signed(47 downto 0); + begin + -- select source operands for multiplication + case alu_ctrl.mul_op1 is + when "00" => src_op1 := register_file.x0; + when "01" => src_op1 := register_file.x1; + when "10" => src_op1 := register_file.y0; + when others => src_op1 := register_file.y1; + end case; + case alu_ctrl.mul_op2 is + when "00" => src_op2 := register_file.x0; + when "01" => src_op2 := register_file.x1; + when "10" => src_op2 := register_file.y0; + when others => src_op2 := register_file.y1; + end case; + + -- perform integer multiplication + mul_result_interm := src_op1 * src_op2; + + -- sign extension of result + alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47)); + -- convert from two's complement representation to fractional format + -- signed integer multiplication delivers twice the sign bit, but only one is needed for the + -- fractional multiplication, so remove one and append a zero to the result + alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0'; + + end process alu_multiplier; + + + -- contains the data shifter + alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is + variable src_accu : signed(55 downto 0); + variable shift_to_perform : alu_shift_mode; + begin + -- read source accumulator + if alu_ctrl.shift_src = '0' then + src_accu := register_file.a; + else + src_accu := register_file.b; + end if; + + alu_shifter_carry_out <= '0'; + alu_shifter_overflow_out <= '0'; + + -- NORM instruction determines the shift value just + -- in time, so overwrite the flag from the alu_ctrl + -- for this instruction by the calculated value + if alu_ctrl.norm_instr = '0' then + shift_to_perform := alu_ctrl.shift_mode; + else + if norm_instr_asl = '1' then + shift_to_perform := SHIFT_LEFT; + elsif norm_instr_asr = '1' then + shift_to_perform := SHIFT_RIGHT; + else + shift_to_perform := NO_SHIFT; + end if; + end if; + + case shift_to_perform is + when NO_SHIFT => + alu_shifter_out <= src_accu; + when SHIFT_LEFT => + -- ASL, ADDL, DIV? + if alu_ctrl.word_24_update = '0' then + -- special handling for div instruction required + if alu_ctrl.div_instr = '1' then + alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG); + else + alu_shifter_out <= src_accu(54 downto 0) & '0'; + end if; + alu_shifter_carry_out <= src_accu(55); + -- detect overflow that results from left shifting + -- Needed for ASL, ADDL, DIV instructions + if src_accu(55) /= src_accu(54) then + alu_shifter_overflow_out <= '1'; + end if; + -- LSL/ROL? + elsif alu_ctrl.word_24_update = '1' then + alu_shifter_out(55 downto 48) <= src_accu(55 downto 48); + alu_shifter_out(23 downto 0) <= src_accu(23 downto 0); + alu_shifter_carry_out <= src_accu(47); + if alu_ctrl.rotate = '0' then -- LSL ? + alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0'; + else -- ROL ? + alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG); + end if; + end if; + when SHIFT_RIGHT => + -- ASR? + if alu_ctrl.word_24_update = '0' then + alu_shifter_out <= src_accu(55) & src_accu(55 downto 1); + alu_shifter_carry_out <= src_accu(0); + -- LSR/ROR? + elsif alu_ctrl.word_24_update = '1' then + alu_shifter_out(55 downto 48) <= src_accu(55 downto 48); + alu_shifter_out(23 downto 0) <= src_accu(23 downto 0); + alu_shifter_carry_out <= src_accu(24); + if alu_ctrl.rotate = '0' then -- LSR + alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25); + else -- ROR + alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25); + end if; + end if; + when ZEROS => + alu_shifter_out <= (others => '0'); + end case; + end process alu_shifter; + + + -- Special handling for NORM instruction + -- Determine which case occurs (see User's Manual for more information) + norm_instr_logic: process(register_file, addr_r_in) is + begin + norm_instr_asl <= '0'; + norm_instr_asr <= '0'; + + -- Either left shift + if register_file.sr(E_FLAG) = '0' and + register_file.sr(U_FLAG) = '1' and + register_file.sr(Z_FLAG) = '0' then + norm_instr_asl <= '1'; + norm_update_ccr <= '1'; + addr_r_out <= addr_r_in - 1; + -- Or right shift + elsif register_file.sr(E_FLAG) = '1' then + norm_instr_asr <= '1'; + norm_update_ccr <= '1'; + addr_r_out <= addr_r_in + 1; + -- Or do nothing! + else + norm_update_ccr <= '0'; + addr_r_out <= addr_r_in; + end if; + end process; + +end architecture; diff --git a/FPGA_Quartus_13.1/DSP/src/exec_stage_bit_modify.vhd b/FPGA_Quartus_13.1/DSP/src/exec_stage_bit_modify.vhd new file mode 100644 index 0000000..68fecbb --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/exec_stage_bit_modify.vhd @@ -0,0 +1,79 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_bit_modify is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + src_operand : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + dst_operand : out std_logic_vector(23 downto 0); + bit_cond_met : out std_logic; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_bit_modify is + + signal operand_bit : std_logic; + signal src_operand_32 : std_logic_vector(31 downto 0); + +begin + + -- this is just a helper signal to prevent the simulator + -- to stop when accessing a bit > 23. + src_operand_32 <= "00000000" & src_operand; + -- read the bit we want to test (and modify) + operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0)))); + + -- modify the Carry flag only for the bit modify instructions! + modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0'; + modified_sr <= register_file.sr(15 downto 1) & operand_bit; + + bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is + variable new_bit : std_logic; + begin + -- do nothing by default! + dst_operand <= src_operand; + bit_cond_met <= '0'; + + -- determine which bit to write + if instr_array = INSTR_BCLR then + new_bit := '0'; + elsif instr_array = INSTR_BSET then + new_bit := '1'; + else -- BCHG + new_bit := not operand_bit; + end if; + + if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then + dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit; + end if; + + + -- check for the jump instructions whether condition is met or not! + if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then + if operand_bit = '0' then + bit_cond_met <= '1'; + else + bit_cond_met <= '0'; + end if; + end if; + if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then + if operand_bit = '0' then + bit_cond_met <= '0'; + else + bit_cond_met <= '1'; + end if; + end if; + + end process; + + +end architecture; diff --git a/FPGA_Quartus_13.1/DSP/src/exec_stage_branch.vhd b/FPGA_Quartus_13.1/DSP/src/exec_stage_branch.vhd new file mode 100644 index 0000000..9b07913 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/exec_stage_branch.vhd @@ -0,0 +1,117 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_branch is port( + activate_exec_bra : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + jump_address : in unsigned(BW_ADDRESS-1 downto 0); + bit_cond_met : in std_logic; + cc_flag_set : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_branch is + + signal branch_condition_met : std_logic; + signal modify_pc_int : std_logic; + +begin + + modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0'; + modify_pc <= modify_pc_int; + + calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met) + begin + branch_condition_met <= '0'; + + -- unconditional jumps + if instr_array = INSTR_JMP or + instr_array = INSTR_JSR or + instr_array = INSTR_RTI or + instr_array = INSTR_RTS then + -- jump always + branch_condition_met <= '1'; + end if; + -- then see whether the branch condition is satisfied + if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then + branch_condition_met <= cc_flag_set; + end if; + -- jmp that is executed according to a certain bit condition + if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or + instr_array = INSTR_JSET or instr_array = INSTR_JSSET then + branch_condition_met <= bit_cond_met; + end if; + end process calculate_branch_condition; + + + calculate_branch_target : process(instr_array, instr_word, jump_address) + begin + modified_pc <= jump_address; + + -- address calculation is the same for the following instructions + if instr_array = INSTR_JMP or + instr_array = INSTR_JCC or + instr_array = INSTR_JSCC or + instr_array = INSTR_JSR then + if instr_word(18) = '1' then + -- short jump address included in opcode (bits 11 downto 0) + modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0)); + elsif instr_word(18) = '0' then + -- effective address defined by opcode and coming from address generator unit + modified_pc <= jump_address; + end if; + end if; + + -- jump address contains the obligatory address of the second + -- instruction word + if instr_array = INSTR_JCLR or + instr_array = INSTR_JSET or + instr_array = INSTR_JSCLR or + instr_array = INSTR_JSSET then + modified_pc <= jump_address; + end if; + + -- target address is stored on the stack + if instr_array = INSTR_RTS or + instr_array = INSTR_RTI then + modified_pc <= unsigned(register_file.current_ssh); + end if; + end process calculate_branch_target; + + -- Subroutine functions need to store PC and SR on the stack + push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC or instr_array = INSTR_JSR or + instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0'; + push_stack.content <= PC_AND_SR; + -- pc is set externally! + push_stack.pc <= (others => '0'); + + -- RTI/RTS instructions need to read from the stack + pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0'; + + -- some instructions require to set the SR + calculate_status_register : process(instr_array) + begin + modify_sr <= '0'; + modified_sr <= (others => '0'); + if instr_array = INSTR_RTI then + modify_sr <= '1'; + modified_sr <= register_file.current_ssl; + end if; + end process calculate_status_register; + + +end architecture rtl; diff --git a/FPGA_Quartus_13.1/DSP/src/exec_stage_cc_flag_calc.vhd b/FPGA_Quartus_13.1/DSP/src/exec_stage_cc_flag_calc.vhd new file mode 100644 index 0000000..63a0b2c --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/exec_stage_cc_flag_calc.vhd @@ -0,0 +1,75 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_cc_flag_calc is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + cc_flag_set : out std_logic +); +end entity; + + +architecture rtl of exec_stage_cc_flag_calc is + + +begin + + calculate_cc_flag : process(instr_word, instr_array, register_file) + + variable cc_select : std_logic_vector(3 downto 0); + + procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is + variable c_flag : std_logic := register_file.ccr(0); + variable v_flag : std_logic := register_file.ccr(1); + variable z_flag : std_logic := register_file.ccr(2); + variable n_flag : std_logic := register_file.ccr(3); + variable u_flag : std_logic := register_file.ccr(4); + variable e_flag : std_logic := register_file.ccr(5); + variable l_flag : std_logic := register_file.ccr(6); + + begin + if (cc = "0000" and c_flag = '0') or -- CC: carry clear + (cc = "1000" and c_flag = '1') or -- CS: carry set + (cc = "0101" and e_flag = '0') or -- EC: extension clear + (cc = "1010" and z_flag = '1') or -- EQ: equal + (cc = "1101" and e_flag = '1') or -- ES: extension set + (cc = "0001" and (n_flag = v_flag)) or -- GE: greater than or equal + (cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0') or -- GT: greater than + (cc = "0110" and l_flag = '0') or -- LC: limit clear + (cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1') or -- LE: less or equal + (cc = "1110" and l_flag = '1') or -- LS: limit set + (cc = "1001" and (n_flag /= v_flag)) or -- LT: less than + (cc = "1011" and n_flag = '1') or -- MI: minus + (cc = "0010" and z_flag = '0') or -- NE: not equal + (cc = "1100" and (( not u_flag and not e_flag) or z_flag) = '1') or -- NR: normalized + (cc = "0011" and n_flag = '0') or -- PL: plus + (cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0') -- NN: not normalized + then + cc_flag_set <= '1'; + end if; + end procedure; + + begin + + cc_flag_set <= '0'; + + -- Rip the flags we have to test for from the instruction word + if (instr_array = INSTR_JCC and instr_word(18) = '0') or + (instr_array = INSTR_JSCC) then + cc_select := instr_word(3 downto 0); + else + cc_select := instr_word(15 downto 12); + end if; + + calculate_cc_flag(cc_select); + + end process; + + +end architecture; diff --git a/FPGA_Quartus_13.1/DSP/src/exec_stage_cr_mod.vhd b/FPGA_Quartus_13.1/DSP/src/exec_stage_cr_mod.vhd new file mode 100644 index 0000000..c236db7 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/exec_stage_cr_mod.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_cr_mod is port ( + activate_exec_cr_mod : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0); + modify_omr : out std_logic; + modified_omr : out std_logic_vector(7 downto 0) +); +end exec_stage_cr_mod; + + +architecture rtl of exec_stage_cr_mod is + +begin + + process(activate_exec_cr_mod, instr_word, instr_array, register_file) is + variable imm8 : std_logic_vector(7 downto 0); + variable op8 : std_logic_vector(7 downto 0); + variable res8 : std_logic_vector(7 downto 0); + begin + modify_sr <= '0'; + modify_omr <= '0'; + modified_sr <= (others => '0'); + modified_omr <= (others => '0'); + + imm8 := instr_word(15 downto 8); + if instr_word(1 downto 0) = "00" then + -- read MR + op8 := register_file.mr; + elsif instr_word(1 downto 0) = "01" then + -- read CCR + op8 := register_file.ccr; + else -- instr_word(1 downto 0) = "10" + -- read OMR + op8 := register_file.omr; + end if; + + if instr_array = INSTR_ANDI then + res8 := imm8 and op8; + else -- instr_array = INSTR_ORI + res8 := imm8 or op8; + end if; + + -- only write the result when activated + if activate_exec_cr_mod = '1' then + if instr_word(1 downto 0) = "00" then + -- update MR + modify_sr <= '1'; + modified_sr <= res8 & register_file.ccr; + elsif instr_word(1 downto 0) = "01" then + -- update CCR + modify_sr <= '1'; + modified_sr <= register_file.mr & res8; + elsif instr_word(1 downto 0) = "10" then + -- update OMR + modify_omr <= '1'; + modified_omr <= res8; + end if; + end if; + end process; + +end architecture; diff --git a/FPGA_Quartus_13.1/DSP/src/exec_stage_loops.vhd b/FPGA_Quartus_13.1/DSP/src/exec_stage_loops.vhd new file mode 100644 index 0000000..cc32692 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/exec_stage_loops.vhd @@ -0,0 +1,200 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity exec_stage_loop is port( + clk, rst : in std_logic; + activate_exec_loop : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + loop_iterations : in unsigned(15 downto 0); + loop_address : in unsigned(BW_ADDRESS-1 downto 0); + loop_start_address: in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + fetch_perform_enddo: in std_logic; + memory_stall : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + stall_rep : out std_logic; + stall_do : out std_logic; + decrement_lc : out std_logic; + modify_lc : out std_logic; + modified_lc : out unsigned(15 downto 0); + modify_la : out std_logic; + modified_la : out unsigned(15 downto 0); + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) +); +end entity; + + +architecture rtl of exec_stage_loop is + + signal rep_loop_polling : std_logic; + signal do_loop_polling : std_logic; + signal enddo_polling : std_logic; + signal lc_temp : unsigned(15 downto 0); + signal rf_lc_eq_1 : std_logic; + signal memory_stall_t : std_logic; + +begin + + modified_pc <= loop_start_address; + + + -- loop counter in register file equal to 1? + rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0'; + + process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo, + rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is + begin + stall_rep <= '0'; + stall_do <= '0'; + + modify_la <= '0'; + modify_lc <= '0'; + modify_pc <= '0'; + modify_sr <= '0'; + modified_la <= loop_address; + modified_lc <= loop_iterations; -- default + -- set the loop flag LF (bit 15) of Status register + modified_sr(15) <= '1'; + modified_sr(14 downto 0) <= register_file.sr(14 downto 0); + + push_stack.valid <= '0'; -- push PC and SR on the stack + push_stack.pc <= loop_start_address; + push_stack.content <= LA_AND_LC; + + pop_stack.valid <= '0'; + decrement_lc <= '0'; + ------------------ + -- DO instruction + ------------------ + if activate_exec_loop = '1' and instr_array = INSTR_DO then + -- first instruction of the do loop instruction? + if do_loop_polling = '0' then + stall_do <= '1'; + modify_lc <= '1'; -- store the new loop counter + modify_la <= '1'; -- store the new loop address + push_stack.valid <= '1'; -- push LA and LC on the stack + push_stack.content <= LA_AND_LC; + else -- second clock cycle of the do loop instruction ? + push_stack.valid <= '1'; -- push PC and SR on the stack + push_stack.pc <= loop_start_address; + push_stack.content <= PC_AND_SR; + -- set the PC to the first instruction of the loop + -- the already fetched instruction are flushed from the pipeline + -- this prevents problems, when the loop consists of only one or two instructions + modify_pc <= '1'; + -- set the loop flag + modify_sr <= '1'; + end if; + end if; + ----------------------------------------------- + -- ENDDO instruction / loop end in fetch stage + ----------------------------------------------- + if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then + pop_stack.valid <= '1'; + if enddo_polling = '0' then + -- only restore the LF from the stack + modified_sr(15) <= register_file.current_ssl(15); + modify_sr <= '1'; + stall_do <= '1'; -- stall one clock cycle + else + -- restore loop counter and loop address in second clock cycle + modified_lc <= unsigned(register_file.current_ssl); + modify_lc <= '1'; + modified_la <= unsigned(register_file.current_ssh); + modify_la <= '1'; + end if; + end if; + ------------------- + -- REP instruction + ------------------- + if activate_exec_loop = '1' and instr_array = INSTR_REP then + -- only do something when there are more than 1 iterations + -- the first execution is already on the way + if loop_iterations /= 1 then + stall_rep <= '1'; -- stall the fetch and decode stages + modify_lc <= '1'; -- store the loop counter + modified_lc <= loop_iterations - 1; + end if; + end if; + + -- keep processing the single instruction + if rep_loop_polling = '1' then + stall_rep <= '1'; + -- if the REP instruction cause a stall do not modify the lc! + if memory_stall_t = '0' then + if rf_lc_eq_1 = '0' then + decrement_lc <= '1'; + -- when the instruction to repeat caused a memory stall + -- do not continue! + else + -- finish the REP instruction by restoring the LC + stall_rep <= '0'; + modify_lc <= '1'; + modified_lc <= lc_temp; + end if; + end if; + end if; + end process; + + + -- process that allows to remember that we are processing a REP/DO instruction + -- even though the REP instruction is not available in the pipeline anymore + -- also store the old loop counter + process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + rep_loop_polling <= '0'; + do_loop_polling <= '0'; + enddo_polling <= '0'; + lc_temp <= (others => '0'); + memory_stall_t <= '0'; + else + memory_stall_t <= memory_stall; + + if activate_exec_loop = '1' and instr_array = INSTR_REP then + -- only do something when there are more than 1 iterations + -- the first execution is already on the way + if loop_iterations /= 1 then + rep_loop_polling <= '1'; + lc_temp <= register_file.lc; + end if; + end if; + -- test whether the REP instruction has been executed + if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0' then + rep_loop_polling <= '0'; + end if; + + -- do loop execution takes two clock cycles + -- in the first clock cycle we store loop address and loop counter on the stack + -- in the second clock cycle we store programm counter and status register on the stack + if activate_exec_loop = '1' and instr_array = INSTR_DO then + do_loop_polling <= '1'; + end if; + -- clear the flag immediately again (only two cycles execution time!) + if do_loop_polling = '1' then + do_loop_polling <= '0'; + end if; + + -- ENDDO instructions take two clock cycles as well! + if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then + enddo_polling <= '1'; + end if; + if enddo_polling = '1' then + enddo_polling <= '0'; + end if; + end if; + end if; + end process; + +end architecture; diff --git a/FPGA_Quartus_13.1/DSP/src/fetch_stage.vhd b/FPGA_Quartus_13.1/DSP/src/fetch_stage.vhd new file mode 100644 index 0000000..6b22f09 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/fetch_stage.vhd @@ -0,0 +1,60 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + + +entity fetch_stage is port( + + pc_old : in unsigned(BW_ADDRESS-1 downto 0); + pc_new : out unsigned(BW_ADDRESS-1 downto 0); + modify_pc : in std_logic; + modified_pc : in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + decrement_lc : out std_logic; + perform_enddo : out std_logic + +); +end fetch_stage; + + +architecture rtl of fetch_stage is + + +begin + + pc_calculation: process(pc_old, modify_pc, modified_pc, register_file) is + begin + decrement_lc <= '0'; + perform_enddo <= '0'; + + -- by default increment pc by one + pc_new <= pc_old + 1; + if modify_pc = '1' then + pc_new <= modified_pc; + end if; + -- Loop Flag set? + if register_file.sr(15) = '1' then + if register_file.la = pc_old then + -- Loop not finished? + -- => start from the beginning if necessary + if register_file.lc /= 1 then + -- if the last address was LA and the loop is not finished yet, we have to + -- read now from the beginning of the loop again + pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0)); + -- decrement loop counter + decrement_lc <= '1'; + else + -- loop done! + -- => tell the loop controller in the exec stage to perform the enddo operation + -- (without flushing of the pipeline!) + perform_enddo <= '1'; + end if; + end if; + end if; + end process pc_calculation; + +end architecture rtl; + diff --git a/FPGA_Quartus_13.1/DSP/src/mem_control.vhd b/FPGA_Quartus_13.1/DSP/src/mem_control.vhd new file mode 100644 index 0000000..091fcf0 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/mem_control.vhd @@ -0,0 +1,1519 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; + +entity mem_control is + generic( + mem_type : memory_type := P_MEM + ); + port( + clk, rst : in std_logic; + rd_addr : in unsigned(BW_ADDRESS-1 downto 0); + rd_en : in std_logic; + data_out : out std_logic_vector(23 downto 0); + data_out_valid : out std_logic; + wr_addr : in unsigned(BW_ADDRESS-1 downto 0); + wr_en : in std_logic; + wr_accomplished : out std_logic; + data_in : in std_logic_vector(23 downto 0) + ); +end entity mem_control; + + +architecture rtl of mem_control is + + signal int_mem_rd_addr : std_logic_vector(7 downto 0); + type int_mem_type is array(0 to 255) of std_logic_vector(23 downto 0); + signal int_mem : int_mem_type; + signal int_pmem : int_mem_type := ( +-- ABS begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"200026", +--X"56F400", +--X"E00000", +--X"200026", +--X"56F400", +--X"000000", +--X"200026", +--X"52F400", +--X"000080", +--X"200026", +-- ABS end + +-- ADC begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"200039", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"200039", +-- ADC end + +-- ADD begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"200038", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"200038", +-- ADD end + +-- ADDL begin +--X"56F400", +--X"000055", +--X"20001B", +--X"51F400", +--X"000055", +--X"0000B9", +--X"20001A", +--X"56F400", +--X"0000AA", +--X"20001A", +--X"53F400", +--X"000080", +--X"20001A", +-- ADDL end + +-- ADDR begin +--X"56F400", +--X"000055", +--X"20001B", +--X"51F400", +--X"000055", +--X"0000B9", +--X"20000A", +--X"56F400", +--X"0000AA", +--X"20000A", +--X"53F400", +--X"000080", +--X"20000A", +-- ADDR end + +-- AND begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +--X"46F400", +--X"FFF000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +--X"46F400", +--X"000000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005E", +-- AND end + +-- EOR begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FF00FF", +--X"0000B9", +--X"20005B", +--X"46F400", +--X"FFFFFF", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20005B", +-- EOR end + +-- OR begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"FF00FF", +--X"0000B9", +--X"20005A", +--X"46F400", +--X"000000", +--X"57F400", +--X"000000", +--X"0000B9", +--X"20005A", +-- OR end + +-- NOT begin +--X"46F400", +--X"000FFF", +--X"57F400", +--X"7F00FF", +--X"0000B9", +--X"20001F", +--X"46F400", +--X"000000", +--X"57F400", +--X"FFFFFF", +--X"0000B9", +--X"20001F", +-- NOT end + +-- ASL begin +--X"20001B", +--X"51F400", +--X"0000A5", +--X"55F400", +--X"0000A5", +--X"53F400", +--X"0000A5", +--X"0000B9", +--X"20003A", +-- ASL end + +-- ASR begin +--X"20001B", +--X"51F400", +--X"0000A5", +--X"55F400", +--X"0000A5", +--X"53F400", +--X"0000A5", +--X"0000B9", +--X"20002A", +-- ASR end + +-- CLR begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"200013", +--X"56F400", +--X"E00000", +--X"0000B9", +--X"0001F9", +--X"200013", +-- CLR end + +-- CMP begin +--X"2F2000", +--X"262400", +--X"0000B9", +--X"20005D", +--X"2F2000", +--X"262000", +--X"0000B9", +--X"20005D", +--X"2F2400", +--X"262000", +--X"0000B9", +--X"20005D", +--X"57F400", +--X"800AAA", +--X"262000", +--X"0000B9", +--X"20005D", +--X"46F400", +--X"800AAA", +--X"2F2000", +--X"0000B9", +--X"20005D", +-- CMP end + +-- CMPM begin +--X"2F2000", +--X"262400", +--X"0000B9", +--X"20005F", +--X"2F2000", +--X"262000", +--X"0000B9", +--X"20005F", +--X"2F2400", +--X"262000", +--X"0000B9", +--X"20005F", +--X"57F400", +--X"800AAA", +--X"262000", +--X"0000B9", +--X"20005F", +--X"46F400", +--X"800AAA", +--X"2F2000", +--X"0000B9", +--X"20005F", +-- CMPM end + +-- DIV begin +--X"00FEB9", +--X"44F400", +--X"600000", +--X"56F400", +--X"200000", +--X"0618A0", +--X"018040", +--X"210E00", +-- DIV end + +-- LSL begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200033", +-- LSL end + +-- LSR begin +--X"0000B9", +--X"56F400", +--X"200000", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200023", +-- LSR end + +-- MPY begin +--X"0000B9", +--X"44F400", +--X"200000", +--X"46F400", +--X"400000", +--X"2000D0", +--X"44F400", +--X"E00000", +--X"46F400", +--X"B9999A", +--X"2000D0", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D0", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D4", +-- MPY end + +-- MAC begin +--X"0000B9", +--X"200013", +--X"2A8000", +--X"44F400", +--X"200000", +--X"46F400", +--X"400000", +--X"2000D6", +--X"44F400", +--X"E00000", +--X"46F400", +--X"B9999A", +--X"2000D2", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D2", +--X"44F400", +--X"E66666", +--X"46F400", +--X"466666", +--X"2000D6", +-- MAC end + +-- MACR begin +--X"0000B9", +--X"200013", +--X"2E1000", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +--X"56F400", +--X"100001", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +--X"2E1000", +--X"50F400", +--X"800000", +--X"44F400", +--X"123456", +--X"46F400", +--X"123456", +--X"2000D3", +-- MACR end + +-- MPYR begin +--X"0000B9", +--X"46F400", +--X"654321", +--X"200095", +-- MPYR end + +-- NEG begin +--X"0000B9", +--X"56F400", +--X"654321", +--X"200036", +--X"200013", +--X"52F400", +--X"000080", +--X"200036", +--X"56F400", +--X"800000", +--X"200036", +-- NEG end + +-- NORM begin +X"200013", +X"2C0100", +X"200003", +X"062FA0", +X"01DB15", +X"200013", +X"2EFF00", +X"2A8400", +X"200003", +X"062FA0", +X"01D915", +X"200013", +X"062FA0", +X"01DA15", +-- NORM end + +-- RND begin +--X"0000B9", +--X"54F400", +--X"123456", +--X"50F400", +--X"789ABC", +--X"200011", +--X"54F400", +--X"123456", +--X"50F400", +--X"800000", +--X"200011", +--X"54F400", +--X"123455", +--X"50F400", +--X"800000", +--X"200011", +-- RND end + +-- ROR begin +--X"0000B9", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200027", +-- ROR end + +-- ROL begin +--X"0000B9", +--X"56F400", +--X"AAAAAA", +--X"50F400", +--X"BCDEFA", +--X"0618A0", +--X"200037", +-- ROL end + + +-- SUB begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20003C", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20003C", +--X"20001B", +--X"53F400", +--X"000080", +--X"47F400", +--X"000001", +--X"20007C", +-- SUB end + +-- SUBL begin +--X"50F400", +--X"000000", +--X"54F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20001E", +--X"54F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20001E", +--X"20001B", +--X"53F400", +--X"000080", +--X"54F400", +--X"000001", +--X"20001E", +-- SUBL end + +-- SUBR begin +--X"50F400", +--X"000000", +--X"54F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20000E", +--X"54F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20000E", +--X"20001B", +--X"53F400", +--X"000080", +--X"54F400", +--X"000001", +--X"20000E", +-- SUBR end + +-- SBC begin +--X"46F400", +--X"000000", +--X"47F400", +--X"000001", +--X"20001B", +--X"51F400", +--X"000001", +--X"0000B9", +--X"0001F9", +--X"20003D", +--X"47F400", +--X"800000", +--X"53F400", +--X"000080", +--X"20003D", +--X"20001B", +--X"53F400", +--X"000080", +--X"47F400", +--X"000001", +--X"20003D", +-- SBC end + +-- TCC begin +--X"311400", +--X"44F400", +--X"ABCDEF", +--X"57F400", +--X"123456", +--X"0000B9", +--X"038143", +--X"03014A", +--X"0004F9", +--X"03A143", +--X"03214A", +-- TCC end + +-- TFR begin +--X"56F400", +--X"ABCDEF", +--X"57F400", +--X"123456", +--X"21EE09", +--X"44F400", +--X"555555", +--X"47F400", +--X"AAAAAA", +--X"21C441", +--X"21E679", +-- TFR end + +-- TST begin +--X"20001B", +--X"20000B", +--X"0000B9", +--X"0001F9", +--X"53F400", +--X"000080", +--X"20000B", +--X"53F400", +--X"00007F", +--X"20000B", +-- TST end + + +--X"2AFF00", +--X"54F400", +--X"FFFFFF", +--X"50F400", +--X"FFFFF2", +--X"200026", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +--X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +X"000000", +--X"44F400", +--X"100010", +--X"45F400", +--X"100011", +--X"0B5880", +--X"000017", +--X"46F400", +--X"100026", +--X"47F400", +--X"100027", +--X"425800", +--X"435800", +--X"420A00", +--X"431F00", +--X"437000", +--X"0000A0", +--X"427000", +--X"00004F", +-- X"42F800", +-- X"43F800", +-- X"428A00", +-- X"439F00", +-- "001100000100100000000000", -- 0 move #72,r0 +-- "001110000000100000000000", -- 1 move #8,n0 +-- "000001010000000010100000", -- 2 move #0,m0 +-- "000001010001000010100001", -- 3 move #16,m1 +-- "000001101110000100100000", -- 4 rep m1 +-- "010001001100100000000000", -- 5 move x:(r0)+n0,x0 +-- "000000000000000000000000", -- 6 +-- "000000000000000000000000", -- 7 +-- "000000000000000000000000", -- 8 +-- "000000000000000000000000", -- 9 +-- "000000000000000000000000", -- 10 +-- "000000000000000000000000", -- 11 +-- "000000000000000000000000", -- 12 +-- "000000000000000000000000", -- 13 +-- "000000000000000000000000", -- 14 +-- "000000000000000000000000", -- 15 +-- "000000000000000000000000", -- 16 +-- "000000000000000000000000", -- 17 +-- "000000000000000000000000", -- 18 +-- "000000000000000000000000", -- 19 +-- "000010101101101010000000", -- 20 -- JMP (r2)+ +-- "000000000000000000000000", -- 20 +-- "000000000000000000000000", -- 21 +-- "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + signal int_xmem : int_mem_type := ( +-- when "11------10000000" => instr_array(JMP_INSTR) <= '1'; +-- "000000000000111011111001", -- 0 -- ORI #$0E, CCR + "000000000000000000001100", -- 0 -- REP + "000000000000000000000101", -- 1 -- ORI #$0E, MR + "000000000000111011111010", -- 2 -- ORI #$0E, OMR + "000000000000100010111010", -- 3 -- ANDI #$08, OMR +-- "000010101111000010000000", -- 1 -- JMP absolute +-- "000000000000000000011111", -- 2 -- #31 +-- "000011000000000000010000", -- 3 -- JMP #16 + "000000000000000000000000", -- 4 + "000000000000000000000000", -- 5 + "000000000000000000000000", -- 6 + "000000000000000000000000", -- 7 + "000000000000000000000000", -- 8 + "000000000000000000000000", -- 9 + "000000000000000000000000", -- 10 + "000000000000000000000000", -- 11 + "000000000000000000000000", -- 12 + "000000000000000000000000", -- 13 + "000000000000000000000000", -- 14 + "000000000000000000000000", -- 15 + "000000000000000000000000", -- 16 +-- "000000000000000000000000", -- 17 + "000010101101010110100000", -- 17 -- JCC (r5)- + "000000000000000000000000", -- 18 + "000000000000000000000000", -- 19 + "000010101101101010000000", -- 20 -- JMP (r2)+ + "000000000000000000000000", -- 21 + "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + signal int_ymem : int_mem_type := ( +-- when "11------10000000" => instr_array(JMP_INSTR) <= '1'; +-- "000000000000111011111001", -- 0 -- ORI #$0E, CCR + "000000000000000000000001", -- 0 -- REP + "000000000000000000000010", -- 1 -- ORI #$0E, MR + "000000000000000000000011", -- 2 -- ORI #$0E, OMR + "000000000000000000000100", -- 3 -- ANDI #$08, OMR +-- "000010101111000010000000", -- 1 -- JMP absolute +-- "000000000000000000011111", -- 2 -- #31 +-- "000011000000000000010000", -- 3 -- JMP #16 + "000000000000000000000101", -- 4 + "000000000000000000000110", -- 5 + "000000000000000000000111", -- 6 + "000000000000000000001000", -- 7 + "000000000000000000001001", -- 8 + "000000000000000000001010", -- 9 + "000000000000000000001011", -- 10 + "000000000000000000001100", -- 11 + "000000000000000000001101", -- 12 + "000000000000000000001110", -- 13 + "000000000000000000001111", -- 14 + "000000000000000000010000", -- 15 + "000000000000000000010001", -- 16 +-- "000000000000000000000000", -- 17 + "000010101101010110100000", -- 17 -- JCC (r5)- + "000000000000000000000000", -- 18 + "000000000000000000000000", -- 19 + "000010101101101010000000", -- 20 -- JMP (r2)+ + "000000000000000000000000", -- 21 + "000000000000000000000000", -- 22 + "000000000000000000000000", -- 23 + "000000000000000000000000", -- 24 + "000000000000000000000000", -- 25 + "000000000000000000000000", -- 26 + "000000000000000000000000", -- 27 + "000000000000000000000000", -- 28 + "000000000000000000000000", -- 29 + "000000000000000000000000", -- 30 + "000000000000000000000000", -- 31 +-- "000000000000000000000000", -- 32 +-- "000011010000000000000000", -- 32 -- JSR #0 + "000010111111000010000000", -- 32 -- JSR absolute + "000000000000000001000000", -- 33 -- #64 + "000000000000000000000000", -- 34 + "000000000000000000000000", -- 35 + "000000000000000000000000", -- 36 + "000000000000000000000000", -- 37 + "000000000000000000000000", -- 38 + "000000000000000000000000", -- 39 + "000000000000000000000000", -- 40 + "000000000000000000000000", -- 41 + "000000000000000000000000", -- 42 + "000000000000000000000000", -- 43 + "000000000000000000000000", -- 44 + "000000000000000000000000", -- 45 + "000000000000000000000000", -- 46 + "000000000000000000000000", -- 47 + "000000000000000000000000", -- 48 + "000000000000000000000000", -- 49 + "000000000000000000000000", -- 50 + "000000000000000000000000", -- 51 + "000000000000000000000000", -- 52 + "000000000000000000000000", -- 53 + "000000000000000000000000", -- 54 + "000000000000000000000000", -- 55 + "000000000000000000000000", -- 56 + "000000000000000000000000", -- 57 + "000000000000000000000000", -- 58 + "000000000000000000000000", -- 59 + "000000000000000000000000", -- 60 + "000000000000000000000000", -- 61 + "000000000000000000000000", -- 62 + "000000000000000000000000", -- 63 + "000000000000000000000000", -- 64 + "000000000000000000000000", -- 65 + "000000000000000000000000", -- 66 + "000000000000000000000000", -- 67 + "000000000000000000000000", -- 68 + "000000000000000000000000", -- 69 + "000000000000000000000100", -- 70 -- RTI + "000000000000000000000000", -- 71 + "000000000000000000000000", -- 72 + "000000000000000000000000", -- 73 + "000000000000000000000000", -- 74 + "000000000000000000000000", -- 75 + "000000000000000000000000", -- 76 + "000000000000000000000000", -- 77 + "000000000000000000000000", -- 78 + "000000000000000000000000", -- 79 + "000000000000000000000000", -- 80 + "000000000000000000000000", -- 81 + "000000000000000000000000", -- 82 + "000000000000000000000000", -- 83 + "000000000000000000000000", -- 84 + "000000000000000000000000", -- 85 + "000000000000000000000000", -- 86 + "000000000000000000000000", -- 87 + "000000000000000000000000", -- 88 + "000000000000000000000000", -- 89 + "000000000000000000000000", -- 90 + "000000000000000000000000", -- 91 + "000000000000000000000000", -- 92 + "000000000000000000000000", -- 93 + "000000000000000000000000", -- 94 + "000000000000000000000000", -- 95 + "000000000000000000000000", -- 96 + "000000000000000000000000", -- 97 + "000000000000000000000000", -- 98 + "000000000000000000000000", -- 99 + "000000000000000000000000", -- 100 + "000000000000000000000000", -- 101 + "000000000000000000000000", -- 102 + "000000000000000000000000", -- 103 + "000000000000000000000000", -- 104 + "000000000000000000000000", -- 105 + "000000000000000000000000", -- 106 + "000000000000000000000000", -- 107 + "000000000000000000000000", -- 108 + "000000000000000000000000", -- 109 + "000000000000000000000000", -- 110 + "000000000000000000000000", -- 111 + "000000000000000000000000", -- 112 + "000000000000000000000000", -- 113 + "000000000000000000000000", -- 114 + "000000000000000000000000", -- 115 + "000000000000000000000000", -- 116 + "000000000000000000000000", -- 117 + "000000000000000000000000", -- 118 + "000000000000000000000000", -- 119 + "000000000000000000000000", -- 120 + "000000000000000000000000", -- 121 + "000000000000000000000000", -- 122 + "000000000000000000000000", -- 123 + "000000000000000000000000", -- 124 + "000000000000000000000000", -- 125 + "000000000000000000000000", -- 126 + "000000000000000000000000", -- 127 + "000000000000000000000000", -- 128 + "000000000000000000000000", -- 129 + "000000000000000000000000", -- 130 + "000000000000000000000000", -- 131 + "000000000000000000000000", -- 132 + "000000000000000000000000", -- 133 + "000000000000000000000000", -- 134 + "000000000000000000000000", -- 135 + "000000000000000000000000", -- 136 + "000000000000000000000000", -- 137 + "000000000000000000000000", -- 138 + "000000000000000000000000", -- 139 + "000000000000000000000000", -- 140 + "000000000000000000000000", -- 141 + "000000000000000000000000", -- 142 + "000000000000000000000000", -- 143 + "000000000000000000000000", -- 144 + "000000000000000000000000", -- 145 + "000000000000000000000000", -- 146 + "000000000000000000000000", -- 147 + "000000000000000000000000", -- 148 + "000000000000000000000000", -- 149 + "000000000000000000000000", -- 150 + "000000000000000000000000", -- 151 + "000000000000000000000000", -- 152 + "000000000000000000000000", -- 153 + "000000000000000000000000", -- 154 + "000000000000000000000000", -- 155 + "000000000000000000000000", -- 156 + "000000000000000000000000", -- 157 + "000000000000000000000000", -- 158 + "000000000000000000000000", -- 159 + "000000000000000000000000", -- 160 + "000000000000000000000000", -- 161 + "000000000000000000000000", -- 162 + "000000000000000000000000", -- 163 + "000000000000000000000000", -- 164 + "000000000000000000000000", -- 165 + "000000000000000000000000", -- 166 + "000000000000000000000000", -- 167 + "000000000000000000000000", -- 168 + "000000000000000000000000", -- 169 + "000000000000000000000000", -- 170 + "000000000000000000000000", -- 171 + "000000000000000000000000", -- 172 + "000000000000000000000000", -- 173 + "000000000000000000000000", -- 174 + "000000000000000000000000", -- 175 + "000000000000000000000000", -- 176 + "000000000000000000000000", -- 177 + "000000000000000000000000", -- 178 + "000000000000000000000000", -- 179 + "000000000000000000000000", -- 180 + "000000000000000000000000", -- 181 + "000000000000000000000000", -- 182 + "000000000000000000000000", -- 183 + "000000000000000000000000", -- 184 + "000000000000000000000000", -- 185 + "000000000000000000000000", -- 186 + "000000000000000000000000", -- 187 + "000000000000000000000000", -- 188 + "000000000000000000000000", -- 189 + "000000000000000000000000", -- 190 + "000000000000000000000000", -- 191 + "000000000000000000000000", -- 192 + "000000000000000000000000", -- 193 + "000000000000000000000000", -- 194 + "000000000000000000000000", -- 195 + "000000000000000000000000", -- 196 + "000000000000000000000000", -- 197 + "000000000000000000000000", -- 198 + "000000000000000000000000", -- 199 + "000000000000000000000000", -- 200 + "000000000000000000000000", -- 201 + "000000000000000000000000", -- 202 + "000000000000000000000000", -- 203 + "000000000000000000000000", -- 204 + "000000000000000000000000", -- 205 + "000000000000000000000000", -- 206 + "000000000000000000000000", -- 207 + "000000000000000000000000", -- 208 + "000000000000000000000000", -- 209 + "000000000000000000000000", -- 210 + "000000000000000000000000", -- 211 + "000000000000000000000000", -- 212 + "000000000000000000000000", -- 213 + "000000000000000000000000", -- 214 + "000000000000000000000000", -- 215 + "000000000000000000000000", -- 216 + "000000000000000000000000", -- 217 + "000000000000000000000000", -- 218 + "000000000000000000000000", -- 219 + "000000000000000000000000", -- 220 + "000000000000000000000000", -- 221 + "000000000000000000000000", -- 222 + "000000000000000000000000", -- 223 + "000000000000000000000000", -- 224 + "000000000000000000000000", -- 225 + "000000000000000000000000", -- 226 + "000000000000000000000000", -- 227 + "000000000000000000000000", -- 228 + "000000000000000000000000", -- 229 + "000000000000000000000000", -- 230 + "000000000000000000000000", -- 231 + "000000000000000000000000", -- 232 + "000000000000000000000000", -- 233 + "000000000000000000000000", -- 234 + "000000000000000000000000", -- 235 + "000000000000000000000000", -- 236 + "000000000000000000000000", -- 237 + "000000000000000000000000", -- 238 + "000000000000000000000000", -- 239 + "000000000000000000000000", -- 240 + "000000000000000000000000", -- 241 + "000000000000000000000000", -- 242 + "000000000000000000000000", -- 243 + "000000000000000000000000", -- 244 + "000000000000000000000000", -- 245 + "000000000000000000000000", -- 246 + "000000000000000000000000", -- 247 + "000000000000000000000000", -- 248 + "000000000000000000000000", -- 249 + "000000000000000000000000", -- 250 + "000000000000000000000000", -- 251 + "000000000000000000000000", -- 252 + "000000000000000000000000", -- 253 + "000000000000000000000000", -- 254 + "000000000000000000000000"); -- 255 + +begin + +-- int_mem <= int_pmem when mem_type = P_MEM else +-- int_xmem when mem_type = X_MEM else +-- int_ymem when mem_type = Y_MEM; + + wr_accomplished <= wr_en; + + PMEM_GEN: if mem_type = P_MEM generate + data_out <= int_pmem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_pmem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; + + XMEM_GEN: if mem_type = X_MEM generate + data_out <= int_xmem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_xmem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; + + YMEM_GEN: if mem_type = Y_MEM generate + data_out <= int_ymem(to_integer(unsigned(int_mem_rd_addr))); + process(clk) is + begin + if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else + int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); + data_out_valid <= rd_en; + if wr_en = '1' then + int_ymem(to_integer(wr_addr)) <= data_in; + end if; +-- end if; + end if; + end process; + end generate; +-- process(clk, rst) is +-- begin +-- if rising_edge(clk) then +-- if rst = '1' then +-- data_out_valid <= '0'; +-- int_mem_rd_addr <= (others => '0'); +-- else +-- int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0)); +-- data_out_valid <= rd_en; +-- if wr_en = '1' then +-- if mem_type = P_MEM then +-- int_pmem(to_integer(wr_addr)) <= data_in; +-- elsif mem_type = X_MEM then +-- int_xmem(to_integer(wr_addr)) <= data_in; +-- elsif mem_type = Y_MEM then +-- int_ymem(to_integer(wr_addr)) <= data_in; +-- end if; +-- end if; +-- end if; +-- end if; +-- end process; + +end architecture rtl; + diff --git a/FPGA_Quartus_13.1/DSP/src/memory_management.vhd b/FPGA_Quartus_13.1/DSP/src/memory_management.vhd new file mode 100644 index 0000000..6a25ac8 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/memory_management.vhd @@ -0,0 +1,206 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity memory_management is port ( + clk, rst : in std_logic; + stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : out std_logic; + data_rom_enable: in std_logic; + pmem_ctrl_in : in mem_ctrl_type_in; + pmem_ctrl_out : out mem_ctrl_type_out; + xmem_ctrl_in : in mem_ctrl_type_in; + xmem_ctrl_out : out mem_ctrl_type_out; + ymem_ctrl_in : in mem_ctrl_type_in; + ymem_ctrl_out : out mem_ctrl_type_out +); +end memory_management; + + +architecture rtl of memory_management is + + + component mem_control is + generic( + mem_type : memory_type + ); + port( + clk, rst : in std_logic; + rd_addr : in unsigned(BW_ADDRESS-1 downto 0); + rd_en : in std_logic; + data_out : out std_logic_vector(23 downto 0); + data_out_valid : out std_logic; + wr_addr : in unsigned(BW_ADDRESS-1 downto 0); + wr_en : in std_logic; + wr_accomplished : out std_logic; + data_in : in std_logic_vector(23 downto 0) + ); + end component mem_control; + + signal pmem_data_out : std_logic_vector(23 downto 0); + signal pmem_data_out_valid : std_logic; + + signal pmem_rd_addr : unsigned(BW_ADDRESS-1 downto 0); + signal pmem_rd_en : std_logic; + + signal xmem_rd_en : std_logic; + signal xmem_data_out : std_logic_vector(23 downto 0); + signal xmem_data_out_valid : std_logic; + signal xmem_rd_polling : std_logic; + + signal ymem_rd_en : std_logic; + signal ymem_data_out : std_logic_vector(23 downto 0); + signal ymem_data_out_valid : std_logic; + signal ymem_rd_polling : std_logic; + + signal pmem_stall_buffer : std_logic_vector(23 downto 0); + signal pmem_stall_buffer_valid : std_logic; + signal xmem_stall_buffer : std_logic_vector(23 downto 0); + signal ymem_stall_buffer : std_logic_vector(23 downto 0); + + signal stall_flags_d : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + +begin + + -- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall + -- when the pipeline wakes up, this temporal result is inserted into the pipeline + stall_buffer: process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + pmem_stall_buffer <= (others => '0'); + pmem_stall_buffer_valid <= '0'; + xmem_stall_buffer <= (others => '0'); + ymem_stall_buffer <= (others => '0'); + stall_flags_d <= (others => '0'); + else + stall_flags_d <= stall_flags; + if stall_flags(ST_FETCH2) = '1' and stall_flags_d(ST_FETCH2) = '0' then + if pmem_data_out_valid = '1' then + pmem_stall_buffer <= pmem_data_out; + pmem_stall_buffer_valid <= '1'; + end if; + end if; + if stall_flags(ST_FETCH2) = '0' and stall_flags_d(ST_FETCH2) = '1' then + pmem_stall_buffer_valid <= '0'; + end if; + + + end if; + end if; + end process stall_buffer; + + memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or + ( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else + '0'; + + ------------------------------- + -- PMEM CONTROLLER + ------------------------------- + inst_pmem_ctrl : mem_control + generic map( + mem_type => P_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => pmem_ctrl_in.rd_addr, + rd_en => pmem_ctrl_in.rd_en, + data_out => pmem_data_out, + data_out_valid => pmem_data_out_valid, + wr_addr => pmem_ctrl_in.wr_addr, + wr_en => pmem_ctrl_in.wr_en, + data_in => pmem_ctrl_in.data_in + ); + + -- In case we wake up from a stall use the buffered value + pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FETCH2) = '0' and + stall_flags_d(ST_FETCH2) = '1' and + pmem_stall_buffer_valid = '1' else + pmem_data_out; + + pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FETCH2) = '0' and + stall_flags_d(ST_FETCH2) = '1' else + '0' when stall_flags(ST_FETCH2) = '1' else + pmem_data_out_valid; + + ------------------------------- + -- XMEM CONTROLLER + ------------------------------- + inst_xmem_ctrl : mem_control + generic map( + mem_type => X_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => xmem_ctrl_in.rd_addr, + rd_en => xmem_rd_en, + data_out => xmem_data_out, + data_out_valid => xmem_data_out_valid, + wr_addr => xmem_ctrl_in.wr_addr, + wr_en => xmem_ctrl_in.wr_en, + data_in => xmem_ctrl_in.data_in + ); + + xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0'; + + xmem_ctrl_out.data_out <= xmem_data_out; + xmem_ctrl_out.data_out_valid <= xmem_data_out_valid; + + ------------------------------- + -- YMEM CONTROLLER + ------------------------------- + inst_ymem_ctrl : mem_control + generic map( + mem_type => Y_MEM + ) + port map( + clk => clk, + rst => rst, + rd_addr => ymem_ctrl_in.rd_addr, + rd_en => ymem_rd_en, + data_out => ymem_data_out, + data_out_valid => ymem_data_out_valid, + wr_addr => ymem_ctrl_in.wr_addr, + wr_en => ymem_ctrl_in.wr_en, + data_in => ymem_ctrl_in.data_in + ); + + ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0'; + + ymem_ctrl_out.data_out <= ymem_data_out; + ymem_ctrl_out.data_out_valid <= ymem_data_out_valid; + + mem_stall_control: process(clk) is + begin + if rising_edge(clk) then + if rst = '1' then + xmem_rd_polling <= '0'; + ymem_rd_polling <= '0'; + else + if xmem_rd_en = '1' then + xmem_rd_polling <= '1'; + end if; + + if xmem_data_out_valid = '1' then + xmem_rd_polling <= '0'; + end if; + + if ymem_rd_en = '1' then + ymem_rd_polling <= '1'; + end if; + + if ymem_data_out_valid = '1' then + ymem_rd_polling <= '0'; + end if; + + end if; + end if; + end process; +end architecture; + diff --git a/FPGA_Quartus_13.1/DSP/src/parameter_pkg.vhd b/FPGA_Quartus_13.1/DSP/src/parameter_pkg.vhd new file mode 100644 index 0000000..9e3c301 --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/parameter_pkg.vhd @@ -0,0 +1,10 @@ + +package parameter_pkg is + + constant BW_ADDRESS : natural := 16; + + constant PIPELINE_DEPTH : natural := 5; + + constant NUM_ACT_SIGNALS : natural := 26; + +end package; diff --git a/FPGA_Quartus_13.1/DSP/src/pipeline.vhd b/FPGA_Quartus_13.1/DSP/src/pipeline.vhd new file mode 100644 index 0000000..5b5a98e --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/pipeline.vhd @@ -0,0 +1,968 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity pipeline is port ( + clk, rst : in std_logic; + register_file_out : out register_file_type + +); +end pipeline; + +-- TODOs: +-- External memory accesses +-- ROM tables +-- Reading from SSH flag has to modify stack pointer +-- Memory access (x,y,p) and talling accordingly +-- Address Generator: ring buffers are not yet supported + +-- List of BUGS: +-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!! +-- - SBC instruction has errorneous carry flag calculation + +-- List of probable issues: +-- - Reading from XMEM/YMEM with stalls probably results in corrupted data +-- - ENDDO instruction probably has to flush the pipeline afterwards +-- - Writing to memory occurs twice, when stalls occur + +-- Things to optimize: +-- - RTS/RTI could be executed in the ADGEN Stage already +-- - DO loops always flush the pipeline. This is necessary in case we have a very short loop. +-- The single instruction of the loop then has passed the fetch stage already without the branch + + +architecture rtl of pipeline is + + signal pipeline_regs : pipeline_type; + signal stall_flags : std_logic_vector(PIPELINE_DEPTH-1 downto 0); + + component fetch_stage is port( + pc_old : in unsigned(BW_ADDRESS-1 downto 0); + pc_new : out unsigned(BW_ADDRESS-1 downto 0); + modify_pc : in std_logic; + modified_pc : in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + decrement_lc : out std_logic; + perform_enddo : out std_logic + ); + end component fetch_stage; + + signal pc_old, pc_new : unsigned(BW_ADDRESS-1 downto 0); + signal fetch_modify_pc : std_logic; + signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal fetch_perform_enddo: std_logic; + signal fetch_decrement_lc: std_logic; + + + component decode_stage is port( + activate_dec : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + dble_word_instr : out std_logic; + instr_array : out instructions_type; + act_array : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + reg_wr_addr : out std_logic_vector(5 downto 0); + reg_rd_addr : out std_logic_vector(5 downto 0); + x_bus_rd_addr : out std_logic_vector(1 downto 0); + x_bus_wr_addr : out std_logic_vector(1 downto 0); + y_bus_rd_addr : out std_logic_vector(1 downto 0); + y_bus_wr_addr : out std_logic_vector(1 downto 0); + l_bus_addr : out std_logic_vector(2 downto 0); + adgen_mode_a : out adgen_mode_type; + adgen_mode_b : out adgen_mode_type; + alu_ctrl : out alu_ctrl_type + ); + end component decode_stage; + + signal dec_activate : std_logic; + signal dec_instr_word : std_logic_vector(23 downto 0); + signal dec_dble_word_instr : std_logic; + signal dec_instr_array : instructions_type; + signal dec_act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + signal dec_reg_wr_addr : std_logic_vector(5 downto 0); + signal dec_reg_rd_addr : std_logic_vector(5 downto 0); + signal dec_x_bus_wr_addr : std_logic_vector(1 downto 0); + signal dec_x_bus_rd_addr : std_logic_vector(1 downto 0); + signal dec_y_bus_wr_addr : std_logic_vector(1 downto 0); + signal dec_y_bus_rd_addr : std_logic_vector(1 downto 0); + signal dec_l_bus_addr : std_logic_vector(2 downto 0); + signal dec_adgen_mode_a : adgen_mode_type; + signal dec_adgen_mode_b : adgen_mode_type; + signal dec_alu_ctrl : alu_ctrl_type; + + component adgen_stage is port( + activate_adgen : in std_logic; + activate_x_mem : in std_logic; + activate_y_mem : in std_logic; + activate_l_mem : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + optional_ea_word : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + adgen_mode_a : in adgen_mode_type; + adgen_mode_b : in adgen_mode_type; + address_out_x : out unsigned(BW_ADDRESS-1 downto 0); + address_out_y : out unsigned(BW_ADDRESS-1 downto 0); + wr_R_port_A_valid : out std_logic; + wr_R_port_A : out addr_wr_port_type; + wr_R_port_B_valid : out std_logic; + wr_R_port_B : out addr_wr_port_type + ); + end component adgen_stage; + + signal adgen_activate : std_logic; + signal adgen_activate_x_mem : std_logic; + signal adgen_activate_y_mem : std_logic; + signal adgen_activate_l_mem : std_logic; + signal adgen_instr_word : std_logic_vector(23 downto 0); + signal adgen_instr_array : instructions_type; + signal adgen_optional_ea_word : std_logic_vector(23 downto 0); + signal adgen_register_file : register_file_type; + signal adgen_mode_a : adgen_mode_type; + signal adgen_mode_b : adgen_mode_type; + signal adgen_address_out_x : unsigned(BW_ADDRESS-1 downto 0); + signal adgen_address_out_y : unsigned(BW_ADDRESS-1 downto 0); + signal adgen_wr_R_port_A_valid : std_logic; + signal adgen_wr_R_port_A : addr_wr_port_type; + signal adgen_wr_R_port_B_valid : std_logic; + signal adgen_wr_R_port_B : addr_wr_port_type; + + component exec_stage_bit_modify is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + src_operand : in std_logic_vector(23 downto 0); + register_file : in register_file_type; + dst_operand : out std_logic_vector(23 downto 0); + bit_cond_met : out std_logic; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_bit_modify; + + signal exec_bit_modify_instr_word : std_logic_vector(23 downto 0); + signal exec_bit_modify_instr_array : instructions_type; + signal exec_bit_modify_src_operand : std_logic_vector(23 downto 0); + signal exec_bit_modify_dst_operand : std_logic_vector(23 downto 0); + signal exec_bit_modify_bit_cond_met : std_logic; + signal exec_bit_modify_modify_sr : std_logic; + signal exec_bit_modify_modified_sr : std_logic_vector(15 downto 0); + + component exec_stage_branch is port( + activate_exec_bra : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + jump_address : in unsigned(BW_ADDRESS-1 downto 0); + bit_cond_met : in std_logic; + cc_flag_set : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_branch; + + signal exec_bra_activate : std_logic; + signal exec_bra_instr_word : std_logic_vector(23 downto 0); + signal exec_bra_instr_array : instructions_type; + signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_bra_bit_cond_met : std_logic; + signal exec_bra_push_stack : push_stack_type; + signal exec_bra_pop_stack : pop_stack_type; + signal exec_bra_modify_pc : std_logic; + signal exec_bra_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal exec_bra_modify_sr : std_logic; + signal exec_bra_modified_sr : std_logic_vector(15 downto 0); + + component exec_stage_cr_mod is port( + activate_exec_cr_mod : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0); + modify_omr : out std_logic; + modified_omr : out std_logic_vector(7 downto 0) + ); + end component exec_stage_cr_mod; + + signal exec_cr_mod_activate : std_logic; + signal exec_cr_mod_instr_word : std_logic_vector(23 downto 0); + signal exec_cr_mod_instr_array : instructions_type; + signal exec_cr_mod_modify_sr : std_logic; + signal exec_cr_mod_modified_sr : std_logic_vector(15 downto 0); + signal exec_cr_mod_modify_omr : std_logic; + signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0); + + component exec_stage_loop is port( + clk, rst : in std_logic; + activate_exec_loop : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + loop_iterations : in unsigned(15 downto 0); + loop_address : in unsigned(BW_ADDRESS-1 downto 0); + loop_start_address: in unsigned(BW_ADDRESS-1 downto 0); + register_file : in register_file_type; + fetch_perform_enddo: in std_logic; + memory_stall : in std_logic; + push_stack : out push_stack_type; + pop_stack : out pop_stack_type; + stall_rep : out std_logic; + stall_do : out std_logic; + decrement_lc : out std_logic; + modify_lc : out std_logic; + modified_lc : out unsigned(15 downto 0); + modify_la : out std_logic; + modified_la : out unsigned(15 downto 0); + modify_pc : out std_logic; + modified_pc : out unsigned(BW_ADDRESS-1 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_loop; + + signal exec_loop_activate : std_logic; + signal exec_loop_instr_word : std_logic_vector(23 downto 0); + signal exec_loop_instr_array : instructions_type; + signal exec_loop_iterations : unsigned(15 downto 0); + signal exec_loop_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_register_file : register_file_type; + signal exec_loop_push_stack : push_stack_type; + signal exec_loop_pop_stack : pop_stack_type; + signal exec_loop_stall_rep : std_logic; + signal exec_loop_stall_do : std_logic; + signal exec_loop_decrement_lc : std_logic; + signal exec_loop_modify_lc : std_logic; + signal exec_loop_modified_lc : unsigned(15 downto 0); + signal exec_loop_modify_la : std_logic; + signal exec_loop_modified_la : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_modify_pc : std_logic; + signal exec_loop_modified_pc : unsigned(BW_ADDRESS-1 downto 0); + signal exec_loop_modify_sr : std_logic; + signal exec_loop_modified_sr : std_logic_vector(BW_ADDRESS-1 downto 0); + + component exec_stage_alu is port( + alu_activate : in std_logic; + instr_word : in std_logic_vector(23 downto 0); + alu_ctrl : in alu_ctrl_type; + register_file : in register_file_type; + addr_r_in : in unsigned(BW_ADDRESS-1 downto 0); + addr_r_out : out unsigned(BW_ADDRESS-1 downto 0); + modify_accu : out std_logic; + dst_accu : out std_logic; + modified_accu : out signed(55 downto 0); + modify_sr : out std_logic; + modified_sr : out std_logic_vector(15 downto 0) + ); + end component exec_stage_alu; + + signal exec_alu_activate : std_logic; + signal exec_alu_instr_word : std_logic_vector(23 downto 0); + signal exec_alu_ctrl : alu_ctrl_type; + signal exec_alu_addr_r_in : unsigned(BW_ADDRESS-1 downto 0); + signal exec_alu_addr_r_out : unsigned(BW_ADDRESS-1 downto 0); + signal exec_alu_modify_accu : std_logic; + signal exec_alu_dst_accu : std_logic; + signal exec_alu_modified_accu : signed(55 downto 0); + signal exec_alu_modify_sr : std_logic; + signal exec_alu_modified_sr : std_logic_vector(15 downto 0); + + signal exec_imm_8bit : std_logic_vector(23 downto 0); + signal exec_imm_12bit : std_logic_vector(23 downto 0); + signal exec_src_operand : std_logic_vector(23 downto 0); + signal exec_dst_operand : std_logic_vector(23 downto 0); + + component exec_stage_cc_flag_calc is port( + instr_word : in std_logic_vector(23 downto 0); + instr_array : in instructions_type; + register_file : in register_file_type; + cc_flag_set : out std_logic + ); + end component exec_stage_cc_flag_calc; + + signal exec_cc_flag_calc_instr_word : std_logic_vector(23 downto 0); + signal exec_cc_flag_calc_instr_array : instructions_type; + signal exec_cc_flag_set : std_logic; + + component reg_file is port( + clk, rst : in std_logic; + register_file : out register_file_type; + wr_R_port_A_valid : in std_logic; + wr_R_port_A : in addr_wr_port_type; + wr_R_port_B_valid : in std_logic; + wr_R_port_B : in addr_wr_port_type; + alu_wr_valid : in std_logic; + alu_wr_addr : in std_logic; + alu_wr_data : in signed(55 downto 0); + reg_wr_addr : in std_logic_vector(5 downto 0); + reg_wr_addr_valid : in std_logic; + reg_wr_data : in std_Logic_vector(23 downto 0); + reg_rd_addr : in std_logic_vector(5 downto 0); + reg_rd_data : out std_Logic_vector(23 downto 0); + X_bus_rd_addr : in std_logic_vector(1 downto 0); + X_bus_data_out : out std_logic_vector(23 downto 0); + X_bus_wr_addr : in std_logic_vector(1 downto 0); + X_bus_wr_valid : in std_logic; + X_bus_data_in : in std_logic_vector(23 downto 0); + Y_bus_rd_addr : in std_logic_vector(1 downto 0); + Y_bus_data_out : out std_logic_vector(23 downto 0); + Y_bus_wr_addr : in std_logic_vector(1 downto 0); + Y_bus_wr_valid : in std_logic; + Y_bus_data_in : in std_logic_vector(23 downto 0); + L_bus_rd_addr : in std_logic_vector(2 downto 0); + L_bus_rd_valid : in std_logic; + L_bus_wr_addr : in std_logic_vector(2 downto 0); + L_bus_wr_valid : in std_logic; + push_stack : in push_stack_type; + pop_stack : in pop_stack_type; + set_sr : in std_logic; + new_sr : in std_logic_vector(15 downto 0); + set_omr : in std_logic; + new_omr : in std_logic_vector(7 downto 0); + set_lc : in std_logic; + new_lc : in unsigned(15 downto 0); + dec_lc : in std_logic; + set_la : in std_logic; + new_la : in unsigned(BW_ADDRESS-1 downto 0) + ); + end component reg_file; + + signal register_file : register_file_type; + signal rf_wr_R_port_A_valid : std_logic; + signal rf_wr_R_port_B_valid : std_logic; + signal rf_reg_wr_addr : std_logic_vector(5 downto 0); + signal rf_reg_wr_addr_valid : std_logic; + signal rf_reg_wr_data : std_logic_vector(23 downto 0); + signal rf_reg_rd_addr : std_logic_vector(5 downto 0); + signal rf_reg_rd_data : std_logic_vector(23 downto 0); + signal rf_X_bus_rd_addr : std_logic_vector(1 downto 0); + signal rf_X_bus_data_out : std_logic_vector(23 downto 0); + signal rf_X_bus_wr_addr : std_logic_vector(1 downto 0); + signal rf_X_bus_wr_valid : std_logic; + signal rf_X_bus_data_in : std_logic_vector(23 downto 0); + signal rf_Y_bus_rd_addr : std_logic_vector(1 downto 0); + signal rf_Y_bus_data_out : std_logic_vector(23 downto 0); + signal rf_Y_bus_wr_addr : std_logic_vector(1 downto 0); + signal rf_Y_bus_wr_valid : std_logic; + signal rf_Y_bus_data_in : std_logic_vector(23 downto 0); + signal rf_L_bus_rd_addr : std_logic_vector(2 downto 0); + signal rf_L_bus_rd_valid : std_logic; + signal rf_L_bus_wr_addr : std_logic_vector(2 downto 0); + signal rf_L_bus_wr_valid : std_logic; + signal push_stack : push_stack_type; + signal pop_stack : pop_stack_type; + signal rf_set_sr : std_logic; + signal rf_new_sr : std_logic_vector(15 downto 0); + signal rf_set_omr : std_logic; + signal rf_new_omr : std_logic_vector(7 downto 0); + signal rf_dec_lc : std_logic; + signal rf_set_lc : std_logic; + signal rf_new_lc : unsigned(15 downto 0); + signal rf_set_la : std_logic; + signal rf_new_la : unsigned(BW_ADDRESS-1 downto 0); + signal rf_alu_wr_valid : std_logic; + + component memory_management is port ( + clk, rst : in std_logic; + stall_flags : in std_logic_vector(PIPELINE_DEPTH-1 downto 0); + memory_stall : out std_logic; + data_rom_enable: in std_logic; + pmem_ctrl_in : in mem_ctrl_type_in; + pmem_ctrl_out : out mem_ctrl_type_out; + xmem_ctrl_in : in mem_ctrl_type_in; + xmem_ctrl_out : out mem_ctrl_type_out; + ymem_ctrl_in : in mem_ctrl_type_in; + ymem_ctrl_out : out mem_ctrl_type_out + ); + end component memory_management; + + signal memory_stall : std_logic; + signal pmem_ctrl_in : mem_ctrl_type_in; + signal pmem_ctrl_out : mem_ctrl_type_out; + signal xmem_ctrl_in : mem_ctrl_type_in; + signal xmem_ctrl_out : mem_ctrl_type_out; + signal ymem_ctrl_in : mem_ctrl_type_in; + signal ymem_ctrl_out : mem_ctrl_type_out; + + signal pmem_data_out : std_logic_vector(23 downto 0); + signal pmem_data_out_valid : std_logic; + signal xmem_data_out : std_logic_vector(23 downto 0); + signal xmem_data_out_valid : std_logic; + signal ymem_data_out : std_logic_vector(23 downto 0); + signal ymem_data_out_valid : std_logic; + +begin + register_file_out <= register_file; + + -- merge all stall sources + stall_flags(ST_FETCH) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_FETCH2) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_DECODE) <= '1' when exec_loop_stall_rep = '1' or + memory_stall = '1' or + exec_loop_stall_do = '1' else '0'; + stall_flags(ST_ADGEN) <= exec_loop_stall_do; +-- stall_flags(ST_ADGEN) <= '1' when memory_stall = '1' or +-- exec_loop_stall_do = '1' else '0'; +-- stall_flags(ST_EXEC) <= '0'; + stall_flags(ST_EXEC) <= exec_loop_stall_do; +-- stall_flags(ST_EXEC) <= '1' when memory_stall = '1' or +-- exec_loop_stall_do = '1' else '0'; + + shift_pipeline: process(clk, rst) is + procedure flush_pipeline_stage(stage: natural) is + begin + pipeline_regs(stage).pc <= (others => '1'); + pipeline_regs(stage).instr_word <= (others => '0'); + pipeline_regs(stage).act_array <= (others => '0'); + pipeline_regs(stage).instr_array <= INSTR_NOP; + pipeline_regs(stage).dble_word_instr <= '0'; + pipeline_regs(stage).dec_activate <= '0'; + pipeline_regs(stage).adgen_mode_a <= NOP; + pipeline_regs(stage).adgen_mode_b <= NOP; + pipeline_regs(stage).reg_wr_addr <= (others => '0'); + pipeline_regs(stage).reg_rd_addr <= (others => '0'); + pipeline_regs(stage).x_bus_rd_addr <= (others => '0'); + pipeline_regs(stage).x_bus_wr_addr <= (others => '0'); + pipeline_regs(stage).y_bus_rd_addr <= (others => '0'); + pipeline_regs(stage).y_bus_wr_addr <= (others => '0'); + pipeline_regs(stage).l_bus_addr <= (others => '0'); + pipeline_regs(stage).adgen_address_x <= (others => '0'); + pipeline_regs(stage).adgen_address_y <= (others => '0'); + pipeline_regs(stage).RAM_out_x <= (others => '0'); + pipeline_regs(stage).RAM_out_y <= (others => '0'); + pipeline_regs(stage).alu_ctrl.store_result <= '0'; + end procedure flush_pipeline_stage; + begin + if rising_edge(clk) then + if rst = '1' then + for i in 0 to PIPELINE_DEPTH-1 loop + flush_pipeline_stage(i); + end loop; + else + -- shift the pipeline registers when no stall applies + for i in 1 to PIPELINE_DEPTH-1 loop + if stall_flags(i) = '0' then + -- do not copy the pipeline registers from a stalled pipeline stage + -- for REP we do not flush +-- if stall_flags(i-1) = '1' then + if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or + (i = ST_ADGEN and memory_stall = '1' and exec_loop_stall_rep = '1') then + flush_pipeline_stage(i); + else + pipeline_regs(i) <= pipeline_regs(i-1); + end if; + end if; + end loop; + -- FETCH Pipeline Registers + if stall_flags(ST_FETCH) = '0' then + pipeline_regs(ST_FETCH).pc <= pc_new; + pipeline_regs(ST_FETCH).dec_activate <= '1'; + end if; + + -- FETCH2 Pipeline Registers + if stall_flags(ST_FETCH2) = '0' then + -- Normal pipeline operation? + -- Buffering of RAM output when stalling is performed in the memory management + if pmem_data_out_valid = '1' then + pipeline_regs(ST_FETCH2).instr_word <= pmem_data_out; + end if; + end if; + + -- DECODE Pipeline registers + if stall_flags(ST_DECODE) = '0' then + pipeline_regs(ST_DECODE).act_array <= dec_act_array; + pipeline_regs(ST_DECODE).instr_array <= dec_instr_array; + pipeline_regs(ST_DECODE).dble_word_instr <= dec_dble_word_instr; + pipeline_regs(ST_DECODE).reg_wr_addr <= dec_reg_wr_addr; + pipeline_regs(ST_DECODE).reg_rd_addr <= dec_reg_rd_addr; + pipeline_regs(ST_DECODE).x_bus_wr_addr <= dec_x_bus_wr_addr; + pipeline_regs(ST_DECODE).x_bus_rd_addr <= dec_x_bus_rd_addr; + pipeline_regs(ST_DECODE).y_bus_wr_addr <= dec_y_bus_wr_addr; + pipeline_regs(ST_DECODE).y_bus_rd_addr <= dec_y_bus_rd_addr; + pipeline_regs(ST_DECODE).l_bus_addr <= dec_l_bus_addr; + pipeline_regs(ST_DECODE).adgen_mode_a <= dec_adgen_mode_a; + pipeline_regs(ST_DECODE).adgen_mode_b <= dec_adgen_mode_b; + pipeline_regs(ST_DECODE).alu_ctrl <= dec_alu_ctrl; + end if; + + -- ADGEN Pipeline registers + if stall_flags(ST_ADGEN) = '0' then + pipeline_regs(ST_ADGEN).adgen_address_x <= adgen_address_out_x; + pipeline_regs(ST_ADGEN).adgen_address_y <= adgen_address_out_y; + end if; + if xmem_data_out_valid = '1' then + pipeline_regs(ST_ADGEN).RAM_out_x <= xmem_data_out; + end if; + if ymem_data_out_valid = '1' then + pipeline_regs(ST_ADGEN).RAM_out_y <= ymem_data_out; + end if; + + -- EXEC Pipeline stuff + if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then + -- clear the following pipeline stages, + -- since we modified the pc. + -- Do not flush ST_FETCH - it will hold the correct pc. + flush_pipeline_stage(ST_FETCH2); + flush_pipeline_stage(ST_DECODE); + flush_pipeline_stage(ST_ADGEN); + end if; + end if; + end if; + end process shift_pipeline; + + ------------------------------- + -- FETCH STAGE INSTANTIATION + ------------------------------- + inst_fetch_stage: fetch_stage port map( + pc_old => pc_old, + pc_new => pc_new, + modify_pc => fetch_modify_pc, + modified_pc => fetch_modified_pc, + register_file => register_file, + decrement_lc => fetch_decrement_lc, + perform_enddo => fetch_perform_enddo + ); + + pc_old <= pipeline_regs(ST_FETCH).pc; + + fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0'; + fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else + exec_loop_modified_pc; + + ------------------------------- + -- DECODE STAGE INSTANTIATION + ------------------------------- + inst_decode_stage : decode_stage port map( + activate_dec => dec_activate, + instr_word => dec_instr_word, + dble_word_instr => dec_dble_word_instr, + instr_array => dec_instr_array, + act_array => dec_act_array, + reg_wr_addr => dec_reg_wr_addr, + reg_rd_addr => dec_reg_rd_addr, + x_bus_wr_addr => dec_x_bus_wr_addr, + x_bus_rd_addr => dec_x_bus_rd_addr, + y_bus_wr_addr => dec_y_bus_wr_addr, + y_bus_rd_addr => dec_y_bus_rd_addr, + l_bus_addr => dec_l_bus_addr, + adgen_mode_a => dec_adgen_mode_a, + adgen_mode_b => dec_adgen_mode_b, + alu_ctrl => dec_alu_ctrl + ); + + dec_instr_word <= pipeline_regs(ST_DECODE-1).instr_word; + -- do not decode, when we have no valid instruction. This can happen when + -- 1) the pipeline just started its operation + -- 2) the pipeline was flushed due to a jump + -- 3) we are processing a instruction that consists of two words + dec_activate <= '1' when pipeline_regs(ST_DECODE-1).dec_activate = '1' and pipeline_regs(ST_DECODE).dble_word_instr = '0' else '0'; + + ------------------------------- + -- AGU STAGE INSTANTIATION + ------------------------------- + inst_adgen_stage: adgen_stage port map( + activate_adgen => adgen_activate, + activate_x_mem => adgen_activate_x_mem, + activate_y_mem => adgen_activate_y_mem, + activate_l_mem => adgen_activate_l_mem, + instr_word => adgen_instr_word, + instr_array => adgen_instr_array, + optional_ea_word => adgen_optional_ea_word, + register_file => register_file, + adgen_mode_a => adgen_mode_a, + adgen_mode_b => adgen_mode_b, + address_out_x => adgen_address_out_x, + address_out_y => adgen_address_out_y, + wr_R_port_A_valid => adgen_wr_R_port_A_valid, + wr_R_port_A => adgen_wr_R_port_A, + wr_R_port_B_valid => adgen_wr_R_port_B_valid, + wr_R_port_B => adgen_wr_R_port_B + ); + + adgen_activate <= pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN); + adgen_activate_x_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' or + pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_WR) = '1' else '0'; + adgen_activate_y_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' or + pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_WR) = '1' else '0'; + adgen_activate_l_mem <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_RD) = '1' or + pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_WR) = '1' else '0'; + adgen_instr_word <= pipeline_regs(ST_ADGEN-1).instr_word; + adgen_instr_array <= pipeline_regs(ST_ADGEN-1).instr_array; + adgen_optional_ea_word <= pipeline_regs(ST_ADGEN-2).instr_word; + adgen_mode_a <= pipeline_regs(ST_ADGEN-1).adgen_mode_a; + adgen_mode_b <= pipeline_regs(ST_ADGEN-1).adgen_mode_b; + + ------------------------------- + -- EXECUTE STAGE INSTANTIATIONS + ------------------------------- + inst_exec_stage_alu: exec_stage_alu port map( + alu_activate => exec_alu_activate, + instr_word => exec_alu_instr_word, + alu_ctrl => exec_alu_ctrl, + register_file => register_file, + addr_r_in => exec_alu_addr_r_in, + addr_r_out => exec_alu_addr_r_out, + modify_accu => exec_alu_modify_accu, + dst_accu => exec_alu_dst_accu, + modified_accu => exec_alu_modified_accu, + modify_sr => exec_alu_modify_sr, + modified_sr => exec_alu_modified_sr + ); + + exec_alu_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_ALU); + exec_alu_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_alu_ctrl <= pipeline_regs(ST_EXEC-1).alu_ctrl; + + exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0)); + + inst_exec_stage_bit_modify: exec_stage_bit_modify port map( + instr_word => exec_bit_modify_instr_word, + instr_array => exec_bit_modify_instr_array, + src_operand => exec_bit_modify_src_operand, + register_file => register_file, + dst_operand => exec_bit_modify_dst_operand, + bit_cond_met => exec_bit_modify_bit_cond_met, + modify_sr => exec_bit_modify_modify_sr, + modified_sr => exec_bit_modify_modified_sr + ); + + exec_bit_modify_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_bit_modify_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + exec_bit_modify_src_operand <= exec_src_operand; + + -- Writing to the register file using the 6 bit addressing scheme + -- sources are: + -- 1) X-RAM output + -- 2) Y-RAM output + -- 3) register file itself + -- 4) short immediate value (8 bit stored in instruction word) + -- 5) long immediate value (from optional effective address extension) + -- 5) address generated by the address generation unit (LUA instr) + exec_src_operand <= pipeline_regs(ST_EXEC-1).RAM_out_x when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else + pipeline_regs(ST_EXEC-1).RAM_out_y when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else + rf_reg_rd_data when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else + exec_imm_8bit when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_8BIT) = '1' else + exec_imm_12bit when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_12BIT) = '1' else + pipeline_regs(ST_EXEC-2).instr_word when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_LONG) = '1' else + std_logic_vector(resize(pipeline_regs(ST_EXEC-1).adgen_address_x, 24)); -- for LUA instr. + + -- Destination for the register file using the 6 bit addressing scheme. + -- Either read the bit modified version of the read value + -- or use the modified Rn in case of a NORM instruction +-- exec_dst_operand <= exec_bit_modify_dst_operand; + exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_EXEC-1).act_array(ACT_NORM) = '0' else + std_logic_vector(resize(exec_alu_addr_r_out,24)); + + -- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true + inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map( + instr_word => exec_cc_flag_calc_instr_word, + instr_array => exec_cc_flag_calc_instr_array, + register_file => register_file, + cc_flag_set => exec_cc_flag_set + ); + + exec_cc_flag_calc_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_cc_flag_calc_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + + + inst_exec_stage_branch : exec_stage_branch port map( + activate_exec_bra => exec_bra_activate, + instr_word => exec_bra_instr_word, + instr_array => exec_bra_instr_array, + register_file => register_file, + jump_address => exec_bra_jump_address, + bit_cond_met => exec_bra_bit_cond_met, + cc_flag_set => exec_cc_flag_set, + push_stack => exec_bra_push_stack, + pop_stack => exec_bra_pop_stack, + modify_pc => exec_bra_modify_pc, + modified_pc => exec_bra_modified_pc, + modify_sr => exec_bra_modify_sr, + modified_sr => exec_bra_modified_sr + ); + + exec_bra_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_BRA); + exec_bra_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_bra_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + exec_bra_jump_address <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else + unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)); + exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met; + + inst_exec_stage_cr_mod : exec_stage_cr_mod port map( + activate_exec_cr_mod => exec_cr_mod_activate, + instr_word => exec_cr_mod_instr_word, + instr_array => exec_cr_mod_instr_array, + register_file => register_file, + modify_sr => exec_cr_mod_modify_sr, + modified_sr => exec_cr_mod_modified_sr, + modify_omr => exec_cr_mod_modify_omr, + modified_omr => exec_cr_mod_modified_omr + ); + + exec_cr_mod_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_CR_MOD); + exec_cr_mod_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_cr_mod_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + + inst_exec_stage_loop: exec_stage_loop port map( + clk => clk, + rst => rst, + activate_exec_loop => exec_loop_activate, + instr_word => exec_loop_instr_word, + instr_array => exec_loop_instr_array, + loop_iterations => exec_loop_iterations, + loop_address => exec_loop_address, + loop_start_address => exec_loop_start_address, + register_file => register_file, + fetch_perform_enddo=> fetch_perform_enddo, + memory_stall => memory_stall, + push_stack => exec_loop_push_stack, + pop_stack => exec_loop_pop_stack, + stall_rep => exec_loop_stall_rep, + stall_do => exec_loop_stall_do, + modify_lc => exec_loop_modify_lc, + decrement_lc => exec_loop_decrement_lc, + modified_lc => exec_loop_modified_lc, + modify_la => exec_loop_modify_la, + modified_la => exec_loop_modified_la, + modify_pc => exec_loop_modify_pc, + modified_pc => exec_loop_modified_pc, + modify_sr => exec_loop_modify_sr, + modified_sr => exec_loop_modified_sr + ); + + exec_loop_activate <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_LOOP); + exec_loop_instr_word <= pipeline_regs(ST_EXEC-1).instr_word; + exec_loop_instr_array <= pipeline_regs(ST_EXEC-1).instr_array; + exec_loop_iterations <= unsigned(exec_src_operand(15 downto 0)); + -- from which source is our operand? + -- - XMEM + -- - YMEM + -- - Any register + -- - Immediate (from instruction word) +-- exec_src_operand <= unsigned(pipeline_regs(ST_EXEC-1).RAM_out_x(BW_ADDRESS-1 downto 0)) when +-- pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else +-- unsigned(pipeline_regs(ST_EXEC-1).RAM_out_y(BW_ADDRESS-1 downto 0)) when +-- pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else +-- unsigned(rf_reg_rd_data(15 downto 0)) when +-- pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else +-- "00000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(15 downto 8)); + + -- Loop address is given by the second instruction word of the DO instruction. + -- This address is available one previous stage within the pipeline + exec_loop_address <= unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)) - 1; + -- one more stage before we find the programm counter of the first instruction to be executed in a DO loop + exec_loop_start_address <= unsigned(pipeline_regs(ST_EXEC-3).pc); + + -- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest) + exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else + pipeline_regs(ST_EXEC-1).instr_word(15 downto 8); + exec_imm_8bit(15 downto 8) <= (others => '0'); + exec_imm_8bit( 7 downto 0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else + pipeline_regs(ST_EXEC-1).instr_word(15 downto 8); + -- The 12 bit immediate stems from the instruction word + exec_imm_12bit(23 downto 12) <= (others => '0'); + exec_imm_12bit(11 downto 0) <= pipeline_regs(ST_EXEC-1).instr_word(3 downto 0) & pipeline_regs(ST_EXEC-1).instr_word(15 downto 8); + ----------------- + -- REGISTER FILE + ----------------- + inst_reg_file: reg_file port map( + clk => clk, + rst => rst, + register_file => register_file, + wr_R_port_A_valid => rf_wr_R_port_A_valid, + wr_R_port_A => adgen_wr_R_port_A, + wr_R_port_B_valid => rf_wr_R_port_B_valid, + wr_R_port_B => adgen_wr_R_port_B, + reg_wr_addr => rf_reg_wr_addr, + reg_wr_addr_valid => rf_reg_wr_addr_valid, + reg_wr_data => rf_reg_wr_data, + reg_rd_addr => rf_reg_rd_addr, + reg_rd_data => rf_reg_rd_data, + alu_wr_valid => rf_alu_wr_valid, + alu_wr_addr => exec_alu_dst_accu, + alu_wr_data => exec_alu_modified_accu, + X_bus_rd_addr => rf_X_bus_rd_addr, + X_bus_data_out => rf_X_bus_data_out, + X_bus_wr_addr => rf_X_bus_wr_addr , + X_bus_wr_valid => rf_X_bus_wr_valid, + X_bus_data_in => rf_X_bus_data_in , + Y_bus_rd_addr => rf_Y_bus_rd_addr , + Y_bus_data_out => rf_Y_bus_data_out, + Y_bus_wr_addr => rf_Y_bus_wr_addr , + Y_bus_wr_valid => rf_Y_bus_wr_valid, + Y_bus_data_in => rf_Y_bus_data_in , + L_bus_rd_addr => rf_L_bus_rd_addr , + L_bus_rd_valid => rf_L_bus_rd_valid, + L_bus_wr_addr => rf_L_bus_wr_addr , + L_bus_wr_valid => rf_L_bus_wr_valid, + push_stack => push_stack, + pop_stack => pop_stack, + set_sr => rf_set_sr, + new_sr => rf_new_sr, + set_omr => rf_set_omr, + new_omr => rf_new_omr, + set_la => rf_set_la, + new_la => rf_new_la, + dec_lc => rf_dec_lc, + set_lc => rf_set_lc, + new_lc => rf_new_lc + ); + + ----------------- + -- BUSES (X,Y,L) + ----------------- + rf_X_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_WR); + rf_X_bus_wr_addr <= pipeline_regs(ST_EXEC-1).x_bus_wr_addr; + rf_X_bus_rd_addr <= pipeline_regs(ST_EXEC-1).x_bus_rd_addr; + rf_X_bus_data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' else + pipeline_regs(ST_EXEC-1).RAM_out_x; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else + + rf_Y_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_WR); + rf_Y_bus_wr_addr <= pipeline_regs(ST_EXEC-1).y_bus_wr_addr; + rf_Y_bus_rd_addr <= pipeline_regs(ST_EXEC-1).y_bus_rd_addr; + rf_Y_bus_data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' else + pipeline_regs(ST_EXEC-1).RAM_out_y; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else + + rf_L_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_WR); + rf_L_bus_rd_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD); + rf_L_bus_wr_addr <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- equal to bits in instruction word + rf_L_bus_rd_addr <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- could be simplified by taking these bits.. + + -- writing to the R registers within the ADGEN stage has to be prevented when + -- 1) a jump is currently being executed (which is detected in the exec stage) + -- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling. + -- 3) a memory access results in a stall (e.g. caused by the instruction to REP) + rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADGEN) = '1' or + exec_bra_modify_pc = '1' or + memory_stall = '1' else + adgen_wr_R_port_A_valid; + rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADGEN) = '1' or + exec_bra_modify_pc = '1' or + memory_stall = '1' else + adgen_wr_R_port_B_valid; + + + rf_reg_wr_addr <= pipeline_regs(ST_EXEC-1).reg_wr_addr; + -- can be set due to + -- 1) normal write operation (e.g., move) + -- 2) conditional move (Tcc) + rf_reg_wr_addr_valid <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR) = '1' else + exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR_CC) = '1' else '0'; + rf_reg_wr_data <= exec_dst_operand; + + rf_reg_rd_addr <= pipeline_regs(ST_EXEC-1).reg_rd_addr; + + -- Writing from the ALU can depend on the condition code (Tcc) instruction + rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_ALU_WR_CC) = '1' else + exec_alu_modify_accu; + + push_stack.valid <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0'; + push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else + exec_loop_push_stack.content; + -- for jump to subroutine store the pc of the subsequent instruction + push_stack.pc <= pipeline_regs(ST_EXEC-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else + pipeline_regs(ST_EXEC-3).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '1' else + exec_loop_push_stack.pc when exec_loop_push_stack.valid = '1' else + (others => '0'); + + pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0'; + + rf_set_sr <= '1' when exec_bra_modify_sr = '1' or + exec_cr_mod_modify_sr = '1' or + exec_loop_modify_sr = '1' or + exec_alu_modify_sr = '1' or + exec_bit_modify_modify_sr = '1' else '0'; + rf_new_sr <= exec_bra_modified_sr when exec_bra_modify_sr = '1' else + exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else + exec_loop_modified_sr when exec_loop_modify_sr = '1' else + exec_alu_modified_sr when exec_alu_modify_sr = '1' else + exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else + + rf_set_omr <= exec_cr_mod_modify_omr; + rf_new_omr <= exec_cr_mod_modified_omr; + rf_set_lc <= exec_loop_modify_lc; + rf_new_lc <= exec_loop_modified_lc; + rf_set_la <= exec_loop_modify_la; + rf_new_la <= exec_loop_modified_la; + + rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0'; + + --------------------- + -- MEMORY MANAGEMENT + --------------------- + MMU_inst: memory_management port map ( + clk => clk, + rst => rst, + stall_flags => stall_flags, + memory_stall => memory_stall, + data_rom_enable => register_file.omr(2), + pmem_ctrl_in => pmem_ctrl_in, + pmem_ctrl_out => pmem_ctrl_out, + xmem_ctrl_in => xmem_ctrl_in, + xmem_ctrl_out => xmem_ctrl_out, + ymem_ctrl_in => ymem_ctrl_in, + ymem_ctrl_out => ymem_ctrl_out + ); + + ------------------ + -- Program Memory + ------------------ + pmem_ctrl_in.rd_addr <= pc_new; + pmem_ctrl_in.rd_en <= '1' when stall_flags(ST_FETCH) = '0' else '0'; + -- TODO: Writing to PMEM! + pmem_ctrl_in.wr_addr <= (others => '0'); + pmem_ctrl_in.wr_en <= '0'; + pmem_ctrl_in.data_in <= (others => '0'); + + pmem_data_out <= pmem_ctrl_out.data_out; + pmem_data_out_valid <= pmem_ctrl_out.data_out_valid; + + + ------------------ + -- X Memory + ------------------ + -- Either take the result of the AGU or use the short absolute value stored in the instruction word + xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8)); + xmem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' else '0'; + -- Either take the result of the AGU or use the absolute value stored in the instruction word + xmem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8)); + xmem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_WR) = '1' else '0'; + xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' or + pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1' else + exec_dst_operand; + + xmem_data_out <= xmem_ctrl_out.data_out; + xmem_data_out_valid <= xmem_ctrl_out.data_out_valid; + + ------------------ + -- Y Memory + ------------------ + -- Either take the result of the AGU or use the absolute value stored in the instruction word + ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8)); + ymem_ctrl_in.rd_en <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' else '0'; + -- Either take the result of the AGU or use the absolute value stored in the instruction word + ymem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_y when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else + "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8)); + ymem_ctrl_in.wr_en <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_WR) = '1' else '0'; + ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' or + pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1' else + exec_dst_operand; + + ymem_data_out <= ymem_ctrl_out.data_out; + ymem_data_out_valid <= ymem_ctrl_out.data_out_valid; + + +end architecture rtl; diff --git a/FPGA_Quartus_13.1/DSP/src/reg_file.vhd b/FPGA_Quartus_13.1/DSP/src/reg_file.vhd new file mode 100644 index 0000000..7f3244c --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/reg_file.vhd @@ -0,0 +1,679 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; +use work.types_pkg.all; +use work.constants_pkg.all; + +entity reg_file is port( + clk, rst : in std_logic; + register_file : out register_file_type; + wr_R_port_A_valid : in std_logic; + wr_R_port_A : in addr_wr_port_type; + wr_R_port_B_valid : in std_logic; + wr_R_port_B : in addr_wr_port_type; + alu_wr_valid : in std_logic; + alu_wr_addr : in std_logic; + alu_wr_data : in signed(55 downto 0); + reg_wr_addr : in std_logic_vector(5 downto 0); + reg_wr_addr_valid : in std_logic; + reg_wr_data : in std_Logic_vector(23 downto 0); + reg_rd_addr : in std_logic_vector(5 downto 0); + reg_rd_data : out std_Logic_vector(23 downto 0); + X_bus_rd_addr : in std_logic_vector(1 downto 0); + X_bus_data_out : out std_logic_vector(23 downto 0); + X_bus_wr_addr : in std_logic_vector(1 downto 0); + X_bus_wr_valid : in std_logic; + X_bus_data_in : in std_logic_vector(23 downto 0); + Y_bus_rd_addr : in std_logic_vector(1 downto 0); + Y_bus_data_out : out std_logic_vector(23 downto 0); + Y_bus_wr_addr : in std_logic_vector(1 downto 0); + Y_bus_wr_valid : in std_logic; + Y_bus_data_in : in std_logic_vector(23 downto 0); + L_bus_rd_addr : in std_logic_vector(2 downto 0); + L_bus_rd_valid : in std_logic; + L_bus_wr_addr : in std_logic_vector(2 downto 0); + L_bus_wr_valid : in std_logic; + push_stack : in push_stack_type; + pop_stack : in pop_stack_type; + set_sr : in std_logic; + new_sr : in std_logic_vector(15 downto 0); + set_omr : in std_logic; + new_omr : in std_logic_vector(7 downto 0); + dec_lc : in std_logic; + set_lc : in std_logic; + new_lc : in unsigned(15 downto 0); + set_la : in std_logic; + new_la : in unsigned(BW_ADDRESS-1 downto 0) +); +end entity; + + +architecture rtl of reg_file is + + signal addr_r : addr_array; + signal addr_m : addr_array; + signal addr_n : addr_array; + + signal loop_address : unsigned(BW_ADDRESS-1 downto 0); + signal loop_counter : unsigned(15 downto 0); + + -- condition code register + signal ccr : std_logic_vector(7 downto 0); + -- mode register + signal mr : std_logic_vector(7 downto 0); + -- status register = mode register + condition code register + signal sr : std_logic_vector(15 downto 0); + -- operation mode register + signal omr : std_logic_vector(7 downto 0); + + signal stack_pointer : unsigned(5 downto 0); + signal system_stack_ssh : stack_array_type; + signal system_stack_ssl : stack_array_type; + + signal x0 : signed(23 downto 0); + signal x1 : signed(23 downto 0); + signal y0 : signed(23 downto 0); + signal y1 : signed(23 downto 0); + + signal a0 : signed(23 downto 0); + signal a1 : signed(23 downto 0); + signal a2 : signed(7 downto 0); + + signal b0 : signed(23 downto 0); + signal b1 : signed(23 downto 0); + signal b2 : signed(7 downto 0); + + signal limited_a1 : signed(23 downto 0); + signal limited_b1 : signed(23 downto 0); + signal limited_a0 : signed(23 downto 0); + signal limited_b0 : signed(23 downto 0); + signal set_limiting_flag : std_logic; + signal X_bus_rd_limited_a : std_logic; + signal X_bus_rd_limited_b : std_logic; + signal Y_bus_rd_limited_a : std_logic; + signal Y_bus_rd_limited_b : std_logic; + signal reg_rd_limited_a : std_logic; + signal reg_rd_limited_b : std_logic; + signal rd_limited_a : std_logic; + signal rd_limited_b : std_logic; + +begin + + + + sr <= mr & ccr; + + register_file.addr_r <= addr_r; + register_file.addr_n <= addr_n; + register_file.addr_m <= addr_m; + register_file.lc <= loop_counter; + register_file.la <= loop_address; + register_file.ccr <= ccr; + register_file.mr <= mr; + register_file.sr <= sr; + register_file.omr <= omr; + register_file.stack_pointer <= stack_pointer; + register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0))); + register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0))); + register_file.a <= a2 & a1 & a0; + register_file.b <= b2 & b1 & b0; + register_file.x0 <= x0; + register_file.x1 <= x1; + register_file.y0 <= y0; + register_file.y1 <= y1; + + + global_register_file: process(clk) is + variable stack_pointer_plus_1 : unsigned(3 downto 0); + variable reg_addr : integer range 0 to 7; + begin + if rising_edge(clk) then + if rst = '1' then + addr_r <= (others => (others => '0')); + addr_n <= (others => (others => '0')); + addr_m <= (others => (others => '1')); + ccr <= (others => '0'); + mr <= (others => '0'); + omr <= (others => '0'); + system_stack_ssl <= (others => (others => '0')); + system_stack_ssh <= (others => (others => '0')); + stack_pointer <= (others => '0'); + loop_counter <= (others => '0'); + loop_address <= (others => '0'); + x0 <= (others => '0'); + x1 <= (others => '0'); + y0 <= (others => '0'); + y1 <= (others => '0'); + a0 <= (others => '0'); + a1 <= (others => '0'); + a2 <= (others => '0'); + b0 <= (others => '0'); + b1 <= (others => '0'); + b2 <= (others => '0'); + else + reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0))); + ----------------------------------------------------------------------- + -- General write port to register file using 6 bit addressing scheme + ----------------------------------------------------------------------- + if reg_wr_addr_valid = '1' then + case reg_wr_addr(5 downto 3) is + -- X0, X1, Y0, Y1 + when "000" => + case reg_wr_addr(2 downto 0) is + when "100" => + x0 <= signed(reg_wr_data); + when "101" => + x1 <= signed(reg_wr_data); + when "110" => + y0 <= signed(reg_wr_data); + when "111" => + y1 <= signed(reg_wr_data); + when others => + end case; + + -- A0, B0, A2, B2, A1, B1, A, B + when "001" => + case reg_wr_addr(2 downto 0) is + when "000" => + a0 <= signed(reg_wr_data); + when "001" => + b0 <= signed(reg_wr_data); + when "010" => + a2 <= signed(reg_wr_data(7 downto 0)); + when "011" => + b2 <= signed(reg_wr_data(7 downto 0)); + when "100" => + a1 <= signed(reg_wr_data); + when "101" => + b1 <= signed(reg_wr_data); + when "110" => + a2 <= (others => reg_wr_data(23)); + a1 <= signed(reg_wr_data); + a0 <= (others => '0'); + when "111" => + b2 <= (others => reg_wr_data(23)); + b1 <= signed(reg_wr_data); + b0 <= (others => '0'); + when others => + end case; + + -- R0-R7 + when "010" => + addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- N0-N7 + when "011" => + addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- M0-M7 + when "100" => + addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- SR, OMR, SP, SSH, SSL, LA, LC + when "111" => + case reg_wr_addr(2 downto 0) is + -- SR + when "001" => + mr <= reg_wr_data(15 downto 8); + ccr <= reg_wr_data( 7 downto 0); + + -- OMR + when "010" => + omr <= reg_wr_data(7 downto 0); + + -- SP + when "011" => + stack_pointer <= unsigned(reg_wr_data(5 downto 0)); + + -- SSH + when "100" => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0); + -- increase stack after writing + stack_pointer(3 downto 0) <= stack_pointer_plus_1; + -- test whether stack is full, if so set the stack error flag (SE) + if stack_pointer(3 downto 0) = "1111" then + stack_pointer(4) <= '1'; + end if; + + -- SSL + when "101" => + system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0); + + -- LA + when "110" => + loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0)); + + -- LC + when "111" => + loop_counter <= unsigned(reg_wr_data(15 downto 0)); + + when others => + end case; + when others => + end case; + end if; + + ---------------- + -- X BUS Write + ---------------- + if X_bus_wr_valid = '1' then + case X_bus_wr_addr is + when "00" => + x0 <= signed(X_bus_data_in); + when "01" => + x1 <= signed(X_bus_data_in); + when "10" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= (others => '0'); + when others => + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + ---------------- + -- Y BUS Write + ---------------- + if Y_bus_wr_valid = '1' then + case Y_bus_wr_addr is + when "00" => + y0 <= signed(Y_bus_data_in); + when "01" => + y1 <= signed(Y_bus_data_in); + when "10" => + a2 <= (others => Y_bus_data_in(23)); + a1 <= signed(Y_bus_data_in); + a0 <= (others => '0'); + when others => + b2 <= (others => Y_bus_data_in(23)); + b1 <= signed(Y_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + ------------------ + -- L BUS Write + ------------------ + if L_bus_wr_valid = '1' then + case L_bus_wr_addr is + -- A10 + when "000" => + a1 <= signed(X_bus_data_in); + a0 <= signed(Y_bus_data_in); + -- B10 + when "001" => + b1 <= signed(X_bus_data_in); + b0 <= signed(Y_bus_data_in); + -- X + when "010" => + x1 <= signed(X_bus_data_in); + x0 <= signed(Y_bus_data_in); + -- Y + when "011" => + y1 <= signed(X_bus_data_in); + y0 <= signed(Y_bus_data_in); + -- A + when "100" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= signed(Y_bus_data_in); + -- B + when "101" => + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= signed(Y_bus_data_in); + -- AB + when "110" => + a2 <= (others => X_bus_data_in(23)); + a1 <= signed(X_bus_data_in); + a0 <= (others => '0'); + b2 <= (others => Y_bus_data_in(23)); + b1 <= signed(Y_bus_data_in); + b0 <= (others => '0'); + -- BA + when others => + a2 <= (others => Y_bus_data_in(23)); + a1 <= signed(Y_bus_data_in); + a0 <= (others => '0'); + b2 <= (others => X_bus_data_in(23)); + b1 <= signed(X_bus_data_in); + b0 <= (others => '0'); + end case; + end if; + + --------------------- + -- STATUS REGISTERS + --------------------- + if set_sr = '1' then + ccr <= new_sr( 7 downto 0); + mr <= new_sr(15 downto 8); + end if; + if set_omr = '1' then + omr <= new_omr; + end if; + -- data limiter active? + -- listing this statement after the set_sr test results + -- in the correct behaviour for ALU operations with parallel move + if set_limiting_flag = '1' then + ccr(6) <= '1'; + end if; + + -------------------- + -- LOOP REGISTERS + -------------------- + if set_la = '1' then + loop_address <= new_la; + end if; + if set_lc = '1' then + loop_counter <= new_lc; + end if; + if dec_lc = '1' then + loop_counter <= loop_counter - 1; + end if; + + --------------------- + -- ADDRESS REGISTER + --------------------- + if wr_R_port_A_valid = '1' then + addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value; + end if; + if wr_R_port_B_valid = '1' then + addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value; + end if; + + ------------------------- + -- ALU ACCUMULATOR WRITE + ------------------------- + if alu_wr_valid = '1' then + if alu_wr_addr = '0' then + a2 <= alu_wr_data(55 downto 48); + a1 <= alu_wr_data(47 downto 24); + a0 <= alu_wr_data(23 downto 0); + else + b2 <= alu_wr_data(55 downto 48); + b1 <= alu_wr_data(47 downto 24); + b0 <= alu_wr_data(23 downto 0); + end if; + end if; + + --------------------- + -- STACK CONTROLLER + --------------------- + stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1; + if push_stack.valid = '1' then + -- increase stack after writing + stack_pointer(3 downto 0) <= stack_pointer_plus_1; + -- test whether stack is full, if so set the stack error flag (SE) + if stack_pointer(3 downto 0) = "1111" then + stack_pointer(4) <= '1'; + end if; + case push_stack.content is + when PC => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc); + + when PC_AND_SR => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc); + system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR; + + when LA_AND_LC => + system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address); + system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter); + + end case; + end if; + + -- decrease stack pointer + if pop_stack.valid = '1' then + stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1; + -- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE) + if stack_pointer(3 downto 0) = "0000" then + stack_pointer(5) <= '1'; + stack_pointer(4) <= '1'; + end if; + end if; + end if; + end if; + end process; + + + x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1, + L_bus_rd_addr,L_bus_rd_valid,y1) is + begin + X_bus_rd_limited_a <= '0'; + X_bus_rd_limited_b <= '0'; + case X_bus_rd_addr is + when "00" => X_bus_data_out <= std_logic_vector(x0); + when "01" => X_bus_data_out <= std_logic_vector(x1); + when "10" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + end case; + if L_bus_rd_valid = '1' then + case L_bus_rd_addr is + when "000" => X_bus_data_out <= std_logic_vector(a1); + when "001" => X_bus_data_out <= std_logic_vector(b1); + when "010" => X_bus_data_out <= std_logic_vector(x1); + when "011" => X_bus_data_out <= std_logic_vector(y1); + when "100" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when "101" => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + when "110" => X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1'; + when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1'; + end case; + end if; + end process x_bus_rd_port; + + y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1, + L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is + begin + Y_bus_rd_limited_a <= '0'; + Y_bus_rd_limited_b <= '0'; + case Y_bus_rd_addr is + when "00" => Y_bus_data_out <= std_logic_vector(y0); + when "01" => Y_bus_data_out <= std_logic_vector(y1); + when "10" => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1'; + when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1'; + end case; + if L_bus_rd_valid = '1' then + case L_bus_rd_addr is + when "000" => Y_bus_data_out <= std_logic_vector(a0); + when "001" => Y_bus_data_out <= std_logic_vector(b0); + when "010" => Y_bus_data_out <= std_logic_vector(x0); + when "011" => Y_bus_data_out <= std_logic_vector(y0); + when "100" => Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1'; + when "101" => Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1'; + when "110" => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1'; + when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1'; + end case; + end if; + end process y_bus_rd_port; + + + reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2, + omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer, + loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is + variable reg_addr : integer range 0 to 7; + begin + reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0))); + reg_rd_data <= (others => '0'); + reg_rd_limited_a <= '0'; + reg_rd_limited_b <= '0'; + + case reg_rd_addr(5 downto 3) is + -- X0, X1, Y0, Y1 + when "000" => + case reg_rd_addr(2 downto 0) is + when "100" => + reg_rd_data <= std_logic_vector(x0); + when "101" => + reg_rd_data <= std_logic_vector(x1); + when "110" => + reg_rd_data <= std_logic_vector(y0); + when "111" => + reg_rd_data <= std_logic_vector(y1); + when others => + end case; + + -- A0, B0, A2, B2, A1, B1, A, B + when "001" => + case reg_rd_addr(2 downto 0) is + when "000" => + reg_rd_data <= std_logic_vector(a0); + when "001" => + reg_rd_data <= std_logic_vector(b0); + when "010" => + -- MSBs are read as zero! + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data(7 downto 0) <= std_logic_vector(a2); + when "011" => + -- MSBs are read as zero! + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data(7 downto 0) <= std_logic_vector(b2); + when "100" => + reg_rd_data <= std_logic_vector(a1); + when "101" => + reg_rd_data <= std_logic_vector(b1); + when "110" => + reg_rd_data <= std_logic_vector(limited_a1); + reg_rd_limited_a <= '1'; + when "111" => + reg_rd_data <= std_logic_vector(limited_b1); + reg_rd_limited_b <= '1'; + when others => + end case; + + -- R0-R7 + when "010" => + reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24)); + + -- N0-N7 + when "011" => + reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24)); + + -- M0-M7 + when "100" => + reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24)); + + -- SR, OMR, SP, SSH, SSL, LA, LC + when "111" => + case reg_wr_addr(2 downto 0) is + -- SR + when "001" => + reg_rd_data(23 downto 16) <= (others => '0'); + reg_rd_data(15 downto 0) <= mr & ccr; + + -- OMR + when "010" => + reg_rd_data(23 downto 8) <= (others => '0'); + reg_rd_data( 7 downto 0) <= omr; + + -- SP + when "011" => + reg_rd_data(23 downto 6) <= (others => '0'); + reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer); + + -- SSH + when "100" => +-- TODO! +-- system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0); +-- -- increase stack after writing +-- stack_pointer(3 downto 0) <= stack_pointer_plus_1; +-- -- test whether stack is full, if so set the stack error flag (SE) +-- if stack_pointer(3 downto 0) = "1111" then +-- stack_pointer(4) <= '1'; +-- end if; + + -- SSL + when "101" => + reg_rd_data <= (others => '0'); + reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer))); + + -- LA + when "110" => + reg_rd_data <= (others => '0'); + reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address); + + -- LC + when "111" => + reg_rd_data <= (others => '0'); + reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter); + + when others => + end case; + when others => + end case; + end process; + + rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0'; + rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0'; + + data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is + variable scaled_a : signed(55 downto 0); + variable scaled_b : signed(55 downto 0); + begin + + set_limiting_flag <= '0'; + ----------------- + -- DATA SCALING + ----------------- + -- test against scaling bits S1, S0 + case sr(11 downto 10) is + -- scale down (right shift) + when "01" => + scaled_a := a2(7) & a2 & a1 & a0(23 downto 1); + scaled_b := b2(7) & b2 & b1 & b0(23 downto 1); + -- scale up (arithmetic left shift) + when "10" => + scaled_a := a2(6 downto 0) & a1 & a0 & '0'; + scaled_b := b2(6 downto 0) & b1 & b0 & '0'; + -- "00" do not scale! + when others => + scaled_a := a2 & a1 & a0; + scaled_b := b2 & b1 & b0; + end case; + + -- only sign extension stored in a2? + -- Yes: No limiting needed! + if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then + limited_a1 <= scaled_a(47 downto 24); + limited_a0 <= scaled_a(23 downto 0); + else + -- positive value in a? + if scaled_a(55) = '0' then + limited_a1 <= X"7FFFFF"; + limited_a0 <= X"FFFFFF"; + -- negative value in a? + else + limited_a1 <= X"800000"; + limited_a0 <= X"000000"; + end if; + -- set the limit flag in the status register + if rd_limited_a = '1' then + set_limiting_flag <= '1'; + end if; + end if; + -- only sign extension stored in b2? + -- Yes: No limiting needed! + if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then + limited_b1 <= scaled_b(47 downto 24); + limited_b0 <= scaled_b(23 downto 0); + else + -- positive value in b? + if scaled_b(55) = '0' then + limited_b1 <= X"7FFFFF"; + limited_b0 <= X"FFFFFF"; + -- negative value in b? + else + limited_b1 <= X"800000"; + limited_b0 <= X"000000"; + end if; + -- set the limit flag in the status register + if rd_limited_b = '1' then + set_limiting_flag <= '1'; + end if; + end if; + + end process; + + +end architecture rtl; diff --git a/FPGA_Quartus_13.1/DSP/src/types_pkg.vhd b/FPGA_Quartus_13.1/DSP/src/types_pkg.vhd new file mode 100644 index 0000000..131f7fa --- /dev/null +++ b/FPGA_Quartus_13.1/DSP/src/types_pkg.vhd @@ -0,0 +1,167 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library work; +use work.parameter_pkg.all; + + + +package types_pkg is + + -- the different addressing modes + type adgen_mode_type is (NOP, POST_MIN_N, POST_PLUS_N, POST_MIN_1, POST_PLUS_1, INDEXED_N, PRE_MIN_1, ABSOLUTE, IMMEDIATE); + ------------------------ + -- Decoded instructions + ------------------------ + type instructions_type is ( + INSTR_NOP , + INSTR_RTI , + INSTR_ILLEGAL , + INSTR_SWI , + INSTR_RTS , + INSTR_RESET , + INSTR_WAIT , + INSTR_STOP , + INSTR_ENDDO , + INSTR_ANDI , + INSTR_ORI , + INSTR_DIV , + INSTR_NORM , + INSTR_LUA , + INSTR_MOVEC , + INSTR_REP , + INSTR_DO , + INSTR_MOVEM , + INSTR_MOVEP , + INSTR_PM_MOVEM, + INSTR_BCLR , + INSTR_BSET , + INSTR_JCLR , + INSTR_JSET , + INSTR_JMP , + INSTR_JCC , + INSTR_BCHG , + INSTR_BTST , + INSTR_JSCLR , + INSTR_JSSET , + INSTR_JSR , + INSTR_JSCC ); + + type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0); + + type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS); + type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET); + type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag; + + type alu_ctrl_type is record + mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 + mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1 + shift_src : std_logic; -- a,b + shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved + shift_mode : alu_shift_mode; + rotate : std_logic; -- 0: logical shift, 1: rotate shift + add_src_stage_1 : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b + add_src_stage_2 : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved + add_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved + logic_function : std_logic_vector(2 downto 0); -- 000: none, 001: and, 010: or, 011: eor, 100: not + word_24_update : std_logic; -- only accumulator bits 47 downto 24 affected? + rounding_used : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry + store_result : std_logic; -- 0: do not update accumulator, 1: update accumulator + dst_accu : std_logic; -- 0: a, 1: b + div_instr : std_logic; -- DIV instruction? Special ALU operations needed! + norm_instr : std_logic; -- NORM instruction? Special ALU operations needed! + ccr_flags_ctrl : alu_ccr_flag_array; + end record; + + type pipeline_signals is record + instr_word: std_logic_vector(23 downto 0); + pc : unsigned(BW_ADDRESS-1 downto 0); + dble_word_instr : std_logic; + instr_array : instructions_type; + act_array : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0); + dec_activate : std_logic; + adgen_mode_a : adgen_mode_type; + adgen_mode_b : adgen_mode_type; + reg_wr_addr : std_logic_vector(5 downto 0); + reg_rd_addr : std_logic_vector(5 downto 0); + x_bus_rd_addr : std_logic_vector(1 downto 0); + x_bus_wr_addr : std_logic_vector(1 downto 0); + y_bus_rd_addr : std_logic_vector(1 downto 0); + y_bus_wr_addr : std_logic_vector(1 downto 0); + l_bus_addr : std_logic_vector(2 downto 0); + adgen_address_x : unsigned(BW_ADDRESS-1 downto 0); + adgen_address_y : unsigned(BW_ADDRESS-1 downto 0); + RAM_out_x : std_logic_vector(23 downto 0); + RAM_out_y : std_logic_vector(23 downto 0); + alu_ctrl : alu_ctrl_type; + end record; + + type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals; + + + type register_file_type is record + a : signed(55 downto 0); + b : signed(55 downto 0); + x0 : signed(23 downto 0); + x1 : signed(23 downto 0); + y0 : signed(23 downto 0); + y1 : signed(23 downto 0); + la : unsigned(BW_ADDRESS-1 downto 0); + lc : unsigned(15 downto 0); + addr_r : addr_array; + addr_n : addr_array; + addr_m : addr_array; + ccr : std_logic_vector(7 downto 0); + mr : std_logic_vector(7 downto 0); + sr : std_logic_vector(15 downto 0); + omr : std_logic_vector(7 downto 0); + stack_pointer : unsigned(5 downto 0); +-- system_stack_ssh : stack_array_type; +-- system_stack_ssl : stack_array_type; + current_ssh : std_logic_vector(BW_ADDRESS-1 downto 0); + current_ssl : std_logic_vector(BW_ADDRESS-1 downto 0); + + end record; + + type addr_wr_port_type is record +-- write_valid : std_logic; + reg_number : unsigned(2 downto 0); + reg_value : unsigned(15 downto 0); + end record; + + type mem_ctrl_type_in is record + rd_addr : unsigned(BW_ADDRESS-1 downto 0); + rd_en : std_logic; + wr_addr : unsigned(BW_ADDRESS-1 downto 0); + wr_en : std_logic; + data_in : std_logic_vector(23 downto 0); + end record; + + type mem_ctrl_type_out is record + data_out : std_logic_vector(23 downto 0); + data_out_valid : std_logic; + end record; + + type memory_type is (X_MEM, Y_MEM, P_MEM); + --------------- + -- STACK TYPES + --------------- + type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0); + + type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC); + + type push_stack_type is record + valid : std_logic; + pc : unsigned(BW_ADDRESS-1 downto 0); + content : push_stack_content_type; + end record; + +-- type pop_stack_content_type is (PC, PC_AND_SR, SR, LA_AND_LC); + +-- type pop_stack_type is std_logic; + type pop_stack_type is record + valid : std_logic; +-- content : pop_stack_content_type; + end record; + +end package types_pkg; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd new file mode 100644 index 0000000..b2b8dbb --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -0,0 +1,971 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:20 2009 + +library work; +use work.FalconIO_SDCard_IDE_CF_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +-- Entity Declaration + + +-- Entity Declaration + +ENTITY FalconIO_SDCard_IDE_CF IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + CLK2M : IN STD_LOGIC; + CLK500k : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + LP_BUSY : IN STD_LOGIC; + nACSI_DRQ : IN STD_LOGIC; + nACSI_INT : IN STD_LOGIC; + nSCSI_DRQ : IN STD_LOGIC; + nSCSI_MSG : IN STD_LOGIC; + MIDI_IN : IN STD_LOGIC; + RxD : IN STD_LOGIC; + CTS : IN STD_LOGIC; + RI : IN STD_LOGIC; + DCD : IN STD_LOGIC; + AMKB_RX : IN STD_LOGIC; + PIC_AMKB_RX : IN STD_LOGIC; + IDE_RDY : IN STD_LOGIC; + IDE_INT : IN STD_LOGIC; + WP_CS_CARD : IN STD_LOGIC; + nINDEX : IN STD_LOGIC; + TRACK00 : IN STD_LOGIC; + nRD_DATA : IN STD_LOGIC; + nDCHG : IN STD_LOGIC; + SD_DATA0 : IN STD_LOGIC; + SD_DATA1 : IN STD_LOGIC; + SD_DATA2 : IN STD_LOGIC; + SD_CARD_DEDECT : IN STD_LOGIC; + SD_WP : IN STD_LOGIC; + nDACK0 : IN STD_LOGIC; + nFB_WR : INOUT STD_LOGIC; + WP_CF_CARD : IN STD_LOGIC; + nWP : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + HD_DD : IN STD_LOGIC; + nSCSI_C_D : IN STD_LOGIC; + nSCSI_I_O : IN STD_LOGIC; + CLK2M4576 : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + VSYNC : IN STD_LOGIC; + HSYNC : IN STD_LOGIC; + DSP_INT : IN STD_LOGIC; + nBLANK : IN STD_LOGIC; + FDC_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); + nIDE_CS1 : OUT STD_LOGIC; + nIDE_CS0 : OUT STD_LOGIC; + LP_STR : OUT STD_LOGIC; + LP_DIR : OUT STD_LOGIC; + nACSI_ACK : OUT STD_LOGIC; + nACSI_RESET : OUT STD_LOGIC; + nACSI_CS : OUT STD_LOGIC; + ACSI_DIR : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + nSCSI_ACK : OUT STD_LOGIC; + nSCSI_ATN : OUT STD_LOGIC; + SCSI_DIR : OUT STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + YM_QA : OUT STD_LOGIC; + YM_QC : OUT STD_LOGIC; + YM_QB : OUT STD_LOGIC; + nSDSEL : OUT STD_LOGIC; + STEP : OUT STD_LOGIC; + MOT_ON : OUT STD_LOGIC; + nRP_LDS : OUT STD_LOGIC; + nRP_UDS : OUT STD_LOGIC; + nROM4 : OUT STD_LOGIC; + nROM3 : OUT STD_LOGIC; + nCF_CS1 : OUT STD_LOGIC; + nCF_CS0 : OUT STD_LOGIC; + nIDE_RD : INOUT STD_LOGIC; + nIDE_WR : INOUT STD_LOGIC; + AMKB_TX : OUT STD_LOGIC; + IDE_RES : OUT STD_LOGIC; + DTR : OUT STD_LOGIC; + RTS : OUT STD_LOGIC; + TxD : OUT STD_LOGIC; + MIDI_OLR : OUT STD_LOGIC; + MIDI_TLR : OUT STD_LOGIC; + nDREQ0 : OUT STD_LOGIC; + DSA_D : OUT STD_LOGIC; + nMFP_INT : OUT STD_LOGIC; + FALCON_IO_TA : OUT STD_LOGIC; + STEP_DIR : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC; + WR_GATE : OUT STD_LOGIC; + DMA_DRQ : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_PAR : INOUT STD_LOGIC; + nSCSI_SEL : INOUT STD_LOGIC; + nSCSI_BUSY : INOUT STD_LOGIC; + nSCSI_RST : INOUT STD_LOGIC; + SD_CD_DATA3 : INOUT STD_LOGIC; + SD_CDM_D1 : INOUT STD_LOGIC + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END FalconIO_SDCard_IDE_CF; + + +-- Architecture Body + +ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS +-- system +signal SYS_CLK : STD_LOGIC; +signal RESETn : STD_LOGIC; +signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS +signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS +signal BYT : STD_LOGIC; -- WENN BYT -> 1 +signal LONG : STD_LOGIC; -- WENN -> 1 +-- KEYBOARD MIDI +signal ACIA_CS_I : STD_LOGIC; +signal IRQ_KEYBDn : STD_LOGIC; +signal IRQ_MIDIn : STD_LOGIC; +signal KEYB_RxD : STD_LOGIC; +signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); +signal MIDI_OUT : STD_LOGIC; +signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); +signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); +-- MFP +signal MFP_CS : STD_LOGIC; +signal MFP_INTACK : STD_LOGIC; +signal LDS : STD_LOGIC; +signal DTACK_OUT_MFPn : STD_LOGIC; +signal IRQ_ACIAn : STD_LOGIC; +signal DINTn : STD_LOGIC; +signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); +signal TDO : STD_LOGIC; +-- SOUND +signal SNDCS : STD_LOGIC; +signal SNDCS_I : STD_LOGIC; +signal SNDIR_I : STD_LOGIC; +signal LP_DIR_X : STD_LOGIC; +signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); +signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); +-- DIV +signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE +signal ROM_CS : STD_LOGIC; +-- DMA UND FLOPPY +signal DMA_DATEN_CS : STD_LOGIC; +signal DMA_MODUS_CS : STD_LOGIC; +signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); +signal WDC_BSL_CS : STD_LOGIC; +signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); +signal HD_DD_OUT : STD_LOGIC; +signal FDCS_In : STD_LOGIC; +signal CA0 : STD_LOGIC; +signal CA1 : STD_LOGIC; +signal CA2 : STD_LOGIC; +signal FDINT : STD_LOGIC; +signal FDRQ : STD_LOGIC; +signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_TOP_CS : STD_LOGIC; +signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_HIGH_CS : STD_LOGIC; +signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_MID_CS : STD_LOGIC; +signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_LOW_CS : STD_LOGIC; +signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_DIRM_CS : STD_LOGIC; +signal DMA_ADR_CS : STD_LOGIC; +signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); +signal DMA_DIR_OLD : STD_LOGIC; +signal DMA_BYT_CNT_CS : STD_LOGIC; +signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); +signal CLR_FIFO : STD_LOGIC; +signal DMA_DRQ_I : STD_LOGIC; +signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); +signal DMA_DRQQ : STD_LOGIC; +signal DMA_DRQ_Q : STD_LOGIC; +signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); +signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal RDF_RDE : STD_LOGIC; +signal RDF_WRE : STD_LOGIC; +signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal WRF_RDE : STD_LOGIC; +signal WRF_WRE : STD_LOGIC; +signal nFDC_WR : STD_LOGIC; +type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); +signal FCF_STATE : FCF_STATES; +signal NEXT_FCF_STATE : FCF_STATES; +signal DMA_REQ : STD_LOGIC; +signal FDC_CS : STD_LOGIC; +signal FCF_CS : STD_LOGIC; +signal FCF_APH : STD_LOGIC; +signal DMA_AZ_CS : STD_LOGIC; +signal DMA_ACTIV : STD_LOGIC; +signal DMA_ACTIV_NEW : STD_LOGIC; +signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); +-- SCSI +signal SCSI_CS : STD_LOGIC; +signal SCSI_CSn : STD_LOGIC; +signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal nSCSI_DACK : STD_LOGIC; +signal SCSI_DRQ : STD_LOGIC; +signal SCSI_INT : STD_LOGIC; +signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); +signal DB_EN : STD_LOGIC; +signal DBP_OUTn : STD_LOGIC; +signal DBP_EN : STD_LOGIC; +signal RST_OUTn : STD_LOGIC; +signal RST_EN : STD_LOGIC; +signal BSY_OUTn : STD_LOGIC; +signal BSY_EN : STD_LOGIC; +signal SEL_OUTn : STD_LOGIC; +signal SEL_EN : STD_LOGIC; +-- IDE +signal nnIDE_RES : STD_LOGIC; +signal IDE_CF_CS : STD_LOGIC; +signal IDE_CF_TA : STD_LOGIC; +signal NEXT_nIDE_RD : STD_LOGIC; +signal NEXT_nIDE_WR : STD_LOGIC; +type CMD_STATES is( IDLE, T1, T6, T7); +signal CMD_STATE : CMD_STATES; +signal NEXT_CMD_STATE : CMD_STATES; + + +BEGIN +LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; +BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; +FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; +FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; + +FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; +SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE + '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE + '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; +nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; +nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; +nDREQ0 <= '0'; +---------------------------------------------------------------------------- +-- SD +---------------------------------------------------------------------------- +SD_CLK <= 'Z'; +SD_CD_DATA3 <= 'Z'; +SD_CDM_D1 <= 'Z'; +---------------------------------------------------------------------------- +-- IDE +---------------------------------------------------------------------------- +CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + begin + if nRSTO = '0' then + CMD_STATE <= IDLE; + elsif rising_edge(MAIN_CLK) then + CMD_STATE <= NEXT_CMD_STATE; -- go to next + nIDE_RD <= NEXT_nIDE_RD; -- go to next + nIDE_WR <= NEXT_nIDE_WR; -- go to next + else + CMD_STATE <= CMD_STATE; -- halten + nIDE_RD <= nIDE_RD; -- halten + nIDE_WR <= nIDE_WR; -- halten + end if; + end process CMD_REG; + + CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + begin + case CMD_STATE is + when IDLE => + IDE_CF_TA <= '0'; + if IDE_CF_CS = '1' then + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T1; + else + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end if; + when T1 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + when T6 => + IF IDE_RDY = '1' then + IDE_CF_TA <= '1'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= T7; + else + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + end if; + when T7 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end case; + end process CMD_DECODER; + +IDE_RES <= not nnIDE_RES and nRSTO; +IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 +nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F +nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F +nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F +nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F +----------------------------------------------------------------------------------------------------------------------------------------- +-- ACSI, SCSI UND FLOPPY WD1772 +------------------------------------------------------------------------------------------------------------------------------------------- +-- daten read fifo + RDF: dcfifo0 + port map( + aclr => CLR_FIFO, + data => RDF_DIN, + rdclk => MAIN_CLK, + rdreq => RDF_RDE, + wrclk => FDC_CLK, + wrreq => RDF_WRE, + q => RDF_DOUT, + wrusedw => RDF_AZ + ); +FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY +FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY +RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE +FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; +-- daten write fifo + WRF: dcfifo1 + port map( + aclr => CLR_FIFO, + data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), + rdclk => FDC_CLK, + rdreq => WRF_RDE, + wrclk => MAIN_CLK, + wrreq => WRF_WRE, + q => WRF_DOUT, + rdusedw => WRF_AZ + ); +CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB +DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG +FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + begin + if nRSTO = '0' THEN + WRF_WRE <= '0'; + elsif rising_edge(MAIN_CLK) then + IF FCF_APH = '1' and nFB_WR = '0' then + WRF_WRE <= '1'; + else + WRF_WRE <= '0'; + end if; + else + WRF_WRE <= WRF_WRE; + end if; + END PROCESS; + +FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + begin + if nRSTO = '0' then + FCF_STATE <= FCF_IDLE; + DMA_ACTIV <= '0'; + elsif rising_edge(FDC_CLK) then + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + else + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + end if; + end process FCF_REG; + +FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + begin + if nRSTO = '0' then + FDC_OUT <= x"00"; + elsif rising_edge(FDC_CLK) and FDCS_In = '0' then + FDC_OUT <= CD_OUT_FDC; -- set + else + FDC_OUT <= FDC_OUT; -- halten + end if; + end process FDC_REG; + +DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; +FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; +SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; + + FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + begin + case FCF_STATE is + when FCF_IDLE => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then + DMA_ACTIV_NEW <= DMA_REQ; + NEXT_FCF_STATE <= FCF_T0; + else + DMA_ACTIV_NEW <= '0'; + NEXT_FCF_STATE <= FCF_IDLE; + end if; + when FCF_T0 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= DMA_REQ; + WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO + if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start + else + NEXT_FCF_STATE <= FCF_T1; + end if; + when FCF_T1 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T2; + when FCF_T2 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T3; + when FCF_T3 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T6; + when FCF_T6 => + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO + NEXT_FCF_STATE <= FCF_T7; + when FCF_T7 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= '0'; + if FDC_CS = '1' and DMA_REQ = '0' then + NEXT_FCF_STATE <= FCF_T7; + else + NEXT_FCF_STATE <= FCF_IDLE; + end if; + end case; + end process FCF_DECODER; + + I_FDC: WF1772IP_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + CSn => FDCS_In, + RWn => nFDC_WR, + A1 => CA2, + A0 => CA1, + DATA_IN => CD_IN_FDC, + DATA_OUT => CD_OUT_FDC, +-- DATA_EN => CD_EN_FDC, + RDn => nRD_DATA, + TR00n => TRACK00, + IPn => nINDEX, + WPRTn => nWP, + DDEn => '0', -- Fixed to MFM. + HDTYPE => HD_DD_OUT, + MO => MOT_ON, + WG => WR_GATE, + WD => WR_DATA, + STEP => STEP, + DIRC => STEP_DIR, + DRQ => DMA_DRQ_I, + INTRQ => FDINT + ); +DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 +DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 +WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 +HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); +nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; +CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); +CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); +CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); +FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else + SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else + DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +--- WDC BSL REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + WDC_BSL <= "00"; + elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + else + WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); + end if; + end if; + END PROCESS; +--- DMA MODUS REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + DMA_MODUS <= x"0000"; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); + else + DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); + end if; + IF FB_B1 = '1' THEN + DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); + else + DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); + end if; + else + DMA_MODUS <= DMA_MODUS; + end if; + END PROCESS; +-- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + begin + if nRSTO = '0' or CLR_FIFO = '1' THEN + DMA_BYT_CNT <= x"00000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then + DMA_BYT_CNT(31 downto 17) <= "000000000000000"; + DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); + DMA_BYT_CNT(8 downto 0) <= "000000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then + DMA_BYT_CNT <= FB_AD; + else + DMA_BYT_CNT <= DMA_BYT_CNT; + end if; + END PROCESS; +-------------------------------------------------------------------- +FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +DMA_STATUS(0) <= '1'; -- DMA OK +DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS +DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; +DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else + '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; +DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + process(FDC_CLK, nRSTO, DMA_DRQ_REG) + begin + if nRSTO = '0' THEN + DMA_DRQ_REG <= "00"; + elsif rising_edge(FDC_CLK) then + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + else + DMA_DRQ_REG <= DMA_DRQ_REG; + end if; + END PROCESS; +-- DMA ADRESSE ------------------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_TOP <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then + DMA_TOP <= FB_AD(31 downto 24); + else + DMA_TOP <= DMA_TOP; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_HIGH <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then + DMA_HIGH <= FB_AD(23 downto 16); + else + DMA_HIGH <= DMA_HIGH; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + begin + DMA_MID <= DMA_MID; + if nRSTO = '0' THEN + DMA_MID <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_MID_CS = '1' then + DMA_MID <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_MID <= FB_AD(15 downto 8); + end if; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + begin + DMA_LOW <= DMA_LOW; + if nRSTO = '0' THEN + DMA_LOW <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_LOW_CS = '1'then + DMA_LOW <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_LOW <= FB_AD(7 downto 0); + end if; + end if; + END PROCESS; +-------------------------------------------------------------------------------------------- +DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 +DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 +DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 +DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 +FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +-- DIRECTZUGRIFF +DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD +DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG +DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG +FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +-- DMA RW TOGGLE ------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + begin + if nRSTO = '0' THEN + DMA_DIR_OLD <= '0'; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then + DMA_DIR_OLD <= DMA_MODUS(8); + else + DMA_DIR_OLD <= DMA_DIR_OLD; + end if; + END PROCESS; +CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; +-- SCSI ---------------------------------------------------------------------------------- + I_SCSI: WF5380_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + ADR => CA2 & CA1 & CA0, + DATA_IN => CD_IN_FDC, + DATA_OUT => SCSI_DOUT, + --DATA_EN : out bit; + -- Bus and DMA controls: + CSn => '1', --SCSI_CSn, ABGESCHALTET + RDn => (not nFDC_WR) or (not SCSI_CS), + WRn => nFDC_WR or (not SCSI_CS), + EOPn => '1', + DACKn => nSCSI_DACK, + DRQ => SCSI_DRQ, + INT => SCSI_INT, +-- READY => + -- SCSI bus: + DB_INn => SCSI_D, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => SCSI_PAR, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, -- wenn 1 dann output + RST_INn => nSCSI_RST, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => nSCSI_BUSY, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => nSCSI_SEL, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => '1', + ACK_OUTn => nSCSI_ACK, +-- ACK_EN => ACK_EN, + ATN_INn => '1', + ATN_OUTn => nSCSI_ATN, +-- ATN_EN => ATN_EN, + REQ_INn => nSCSI_DRQ, +-- REQ_OUTn => REQ_OUTn, +-- REQ_EN => REQ_EN, + IOn_IN => nSCSI_I_O, +-- IOn_OUT => IOn_OUT, +-- IO_EN => IO_EN, + CDn_IN => nSCSI_C_D, +-- CDn_OUT => CDn_OUT, +-- CD_EN => CD_EN, + MSG_INn => nSCSI_MSG +-- MSG_OUTn => MSG_OUTn, +-- MSG_EN => MSG_EN + ); +-- SCSI ACSI --------------------------------------------------------------- +SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; +SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET +SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; +nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; +nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; +nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; +ACSI_DIR <= '0'; +ACSI_D <= "ZZZZZZZZ"; +nACSI_CS <= '1'; +ACSI_A1 <= CA1; +nACSI_RESET <= nRSTO; +nACSI_ACK <= '1'; +---------------------------------------------------------------------------- +-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns +---------------------------------------------------------------------------- +ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 +nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; +nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; +---------------------------------------------------------------------------- +-- ACIA KEYBOARD +---------------------------------------------------------------------------- + I_ACIA_KEYBOARD: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => FB_ADR(2), + CS1 => '1', + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_I, +-- DATA_EN => DATA_EN_ACIA_I, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => KEYB_RxD, + + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_KEYBDn, + TXDATA => AMKB_TX + --RTSn => -- Not used. + ); +ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 +KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL +FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; +-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + process(CLK2M, AMKB_RX, AMKB_REG) + begin + if rising_edge(CLK2M) then + IF AMKB_RX = '0' THEN + IF AMKB_REG < 16 THEN + AMKB_REG <= "00000"; + ELSE + AMKB_REG <= AMKB_REG - 1; + END IF; + ELSE + IF AMKB_REG > 15 THEN + AMKB_REG <= "11111"; + ELSE + AMKB_REG <= AMKB_REG + 1; + END IF; + END IF; + ELSE + AMKB_REG <= AMKB_REG; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- ACIA MIDI +---------------------------------------------------------------------------- + I_ACIA_MIDI: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => '0', + CS1 => FB_ADR(2), + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_II, +-- DATA_EN => DATA_EN_ACIA_II, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => MIDI_IN, + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_MIDIn, + TXDATA => MIDI_OUT + --RTSn => -- Not used. + ); +MIDI_TLR <= MIDI_OUT; +MIDI_OLR <= MIDI_OUT; +FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +---------------------------------------------------------------------------- +-- MFP +---------------------------------------------------------------------------- + I_MFP: WF68901IP_TOP_SOC + port map( + -- System control: + CLK => MAIN_CLK, + RESETn => nRSTO, + -- Asynchronous bus control: + DSn => not LDS, + CSn => not MFP_CS, + RWn => nFB_WR, + DTACKn => DTACK_OUT_MFPn, + -- Data and Adresses: + RS => FB_ADR(5 downto 1), + DATA_IN => FB_AD(23 downto 16), + DATA_OUT => DATA_OUT_MFP, +-- DATA_EN => DATA_EN_MFP, + GPIP_IN(7) => not DMA_DRQ_Q, + GPIP_IN(6) => not RI, + GPIP_IN(5) => DINTn, + GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(3) => DSP_INT, + GPIP_IN(2) => not CTS, + GPIP_IN(1) => not DCD, + GPIP_IN(0) => LP_BUSY, + -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. + -- GPIP_EN =>, -- Not used; all GPIPs are direction input. + -- Interrupt control: + IACKn => not MFP_INTACK, + IEIn => '0', + -- IEOn =>, -- Not used. + IRQn => nMFP_INT, + -- Timers and timer control: + XTAL1 => CLK2M4576, + TAI => '0', + TBI => nBLANK, + -- TAO =>, + -- TBO =>, + -- TCO =>, + TDO => TDO, + -- Serial I/O control: + RC => TDO, + TC => TDO, + SI => RxD, + SO => TxD + -- SO_EN => MFP_SO_EN + -- DMA control: + -- RRn =>, + -- TRn => + ); + +MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 +MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 +LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; +FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; +DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else + '0' when FDINT = '1' else + '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1'; +-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) + begin + if nRSTO = '0' THEN + IRQ_ACIAn <= '1'; + elsif rising_edge(MAIN_CLK) then + IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; + else + IRQ_ACIAn <= IRQ_ACIAn; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- Sound +---------------------------------------------------------------------------- + I_SOUND: WF2149IP_TOP_SOC + port map( + SYS_CLK => MAIN_CLK, + RESETn => nRSTO, + + WAV_CLK => CLK2M, + SELn => '1', + + BDIR => SNDIR_I, + BC2 => '1', + BC1 => SNDCS_I, + + A9n => '0', + A8 => '1', + DA_IN => FB_AD(31 downto 24), + DA_OUT => DA_OUT_X, + + IO_A_IN => x"00", -- All port pins are dedicated outputs. + IO_A_OUT(7) => nnIDE_RES, + IO_A_OUT(6) => LP_DIR_X, + IO_A_OUT(5) => LP_STR, + IO_A_OUT(4) => DTR, + IO_A_OUT(3) => RTS, +-- IO_A_OUT(2) => FDD_D1SEL, + IO_A_OUT(1) => DSA_D, + IO_A_OUT(0) => nSDSEL, + -- IO_A_EN =>, -- Not required. + IO_B_IN => LP_D, + IO_B_OUT => LP_D_X, + -- IO_B_EN => IO_B_EN, + + OUT_A => YM_QA, + OUT_B => YM_QB, + OUT_C => YM_QC + ); + +SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 +SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; +SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; +FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; +LP_DIR <= LP_DIR_X; + +END FalconIO_SDCard_IDE_CF_architecture; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak new file mode 100644 index 0000000..a339eda --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak @@ -0,0 +1,971 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Tue Sep 08 16:24:20 2009 + +library work; +use work.FalconIO_SDCard_IDE_CF_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +-- Entity Declaration + + +-- Entity Declaration + +ENTITY FalconIO_SDCard_IDE_CF IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + CLK33M : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + CLK2M : IN STD_LOGIC; + CLK500k : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + LP_BUSY : IN STD_LOGIC; + nACSI_DRQ : IN STD_LOGIC; + nACSI_INT : IN STD_LOGIC; + nSCSI_DRQ : IN STD_LOGIC; + nSCSI_MSG : IN STD_LOGIC; + MIDI_IN : IN STD_LOGIC; + RxD : IN STD_LOGIC; + CTS : IN STD_LOGIC; + RI : IN STD_LOGIC; + DCD : IN STD_LOGIC; + AMKB_RX : IN STD_LOGIC; + PIC_AMKB_RX : IN STD_LOGIC; + IDE_RDY : IN STD_LOGIC; + IDE_INT : IN STD_LOGIC; + WP_CS_CARD : IN STD_LOGIC; + nINDEX : IN STD_LOGIC; + TRACK00 : IN STD_LOGIC; + nRD_DATA : IN STD_LOGIC; + nDCHG : IN STD_LOGIC; + SD_DATA0 : IN STD_LOGIC; + SD_DATA1 : IN STD_LOGIC; + SD_DATA2 : IN STD_LOGIC; + SD_CARD_DEDECT : IN STD_LOGIC; + SD_WP : IN STD_LOGIC; + nDACK0 : IN STD_LOGIC; + nFB_WR : INOUT STD_LOGIC; + WP_CF_CARD : IN STD_LOGIC; + nWP : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + HD_DD : IN STD_LOGIC; + nSCSI_C_D : IN STD_LOGIC; + nSCSI_I_O : IN STD_LOGIC; + CLK2M4576 : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + VSYNC : IN STD_LOGIC; + HSYNC : IN STD_LOGIC; + DSP_INT : IN STD_LOGIC; + nBLANK : IN STD_LOGIC; + FDC_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); + nIDE_CS1 : OUT STD_LOGIC; + nIDE_CS0 : OUT STD_LOGIC; + LP_STR : OUT STD_LOGIC; + LP_DIR : OUT STD_LOGIC; + nACSI_ACK : OUT STD_LOGIC; + nACSI_RESET : OUT STD_LOGIC; + nACSI_CS : OUT STD_LOGIC; + ACSI_DIR : OUT STD_LOGIC; + ACSI_A1 : OUT STD_LOGIC; + nSCSI_ACK : OUT STD_LOGIC; + nSCSI_ATN : OUT STD_LOGIC; + SCSI_DIR : OUT STD_LOGIC; + SD_CLK : OUT STD_LOGIC; + YM_QA : OUT STD_LOGIC; + YM_QC : OUT STD_LOGIC; + YM_QB : OUT STD_LOGIC; + nSDSEL : OUT STD_LOGIC; + STEP : OUT STD_LOGIC; + MOT_ON : OUT STD_LOGIC; + nRP_LDS : OUT STD_LOGIC; + nRP_UDS : OUT STD_LOGIC; + nROM4 : OUT STD_LOGIC; + nROM3 : OUT STD_LOGIC; + nCF_CS1 : OUT STD_LOGIC; + nCF_CS0 : OUT STD_LOGIC; + nIDE_RD : INOUT STD_LOGIC; + nIDE_WR : INOUT STD_LOGIC; + AMKB_TX : OUT STD_LOGIC; + IDE_RES : OUT STD_LOGIC; + DTR : OUT STD_LOGIC; + RTS : OUT STD_LOGIC; + TxD : OUT STD_LOGIC; + MIDI_OLR : OUT STD_LOGIC; + MIDI_TLR : OUT STD_LOGIC; + nDREQ0 : OUT STD_LOGIC; + DSA_D : OUT STD_LOGIC; + nMFP_INT : OUT STD_LOGIC; + FALCON_IO_TA : OUT STD_LOGIC; + STEP_DIR : OUT STD_LOGIC; + WR_DATA : OUT STD_LOGIC; + WR_GATE : OUT STD_LOGIC; + DMA_DRQ : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); + LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); + SCSI_PAR : INOUT STD_LOGIC; + nSCSI_SEL : INOUT STD_LOGIC; + nSCSI_BUSY : INOUT STD_LOGIC; + nSCSI_RST : INOUT STD_LOGIC; + SD_CD_DATA3 : INOUT STD_LOGIC; + SD_CDM_D1 : INOUT STD_LOGIC + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END FalconIO_SDCard_IDE_CF; + + +-- Architecture Body + +ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS +-- system +signal SYS_CLK : STD_LOGIC; +signal RESETn : STD_LOGIC; +signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS +signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS +signal BYT : STD_LOGIC; -- WENN BYT -> 1 +signal LONG : STD_LOGIC; -- WENN -> 1 +-- KEYBOARD MIDI +signal ACIA_CS_I : STD_LOGIC; +signal IRQ_KEYBDn : STD_LOGIC; +signal IRQ_MIDIn : STD_LOGIC; +signal KEYB_RxD : STD_LOGIC; +signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); +signal MIDI_OUT : STD_LOGIC; +signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); +signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); +-- MFP +signal MFP_CS : STD_LOGIC; +signal MFP_INTACK : STD_LOGIC; +signal LDS : STD_LOGIC; +signal DTACK_OUT_MFPn : STD_LOGIC; +signal IRQ_ACIAn : STD_LOGIC; +signal DINTn : STD_LOGIC; +signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); +signal TDO : STD_LOGIC; +-- SOUND +signal SNDCS : STD_LOGIC; +signal SNDCS_I : STD_LOGIC; +signal SNDIR_I : STD_LOGIC; +signal LP_DIR_X : STD_LOGIC; +signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); +signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); +-- DIV +signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE +signal ROM_CS : STD_LOGIC; +-- DMA UND FLOPPY +signal DMA_DATEN_CS : STD_LOGIC; +signal DMA_MODUS_CS : STD_LOGIC; +signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); +signal WDC_BSL_CS : STD_LOGIC; +signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); +signal HD_DD_OUT : STD_LOGIC; +signal FDCS_In : STD_LOGIC; +signal CA0 : STD_LOGIC; +signal CA1 : STD_LOGIC; +signal CA2 : STD_LOGIC; +signal FDINT : STD_LOGIC; +signal FDRQ : STD_LOGIC; +signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_TOP_CS : STD_LOGIC; +signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_HIGH_CS : STD_LOGIC; +signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_MID_CS : STD_LOGIC; +signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_LOW_CS : STD_LOGIC; +signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); +signal DMA_DIRM_CS : STD_LOGIC; +signal DMA_ADR_CS : STD_LOGIC; +signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); +signal DMA_DIR_OLD : STD_LOGIC; +signal DMA_BYT_CNT_CS : STD_LOGIC; +signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); +signal CLR_FIFO : STD_LOGIC; +signal DMA_DRQ_I : STD_LOGIC; +signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); +signal DMA_DRQQ : STD_LOGIC; +signal DMA_DRQ_Q : STD_LOGIC; +signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); +signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal RDF_RDE : STD_LOGIC; +signal RDF_WRE : STD_LOGIC; +signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); +signal WRF_RDE : STD_LOGIC; +signal WRF_WRE : STD_LOGIC; +signal nFDC_WR : STD_LOGIC; +type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); +signal FCF_STATE : FCF_STATES; +signal NEXT_FCF_STATE : FCF_STATES; +signal DMA_REQ : STD_LOGIC; +signal FDC_CS : STD_LOGIC; +signal FCF_CS : STD_LOGIC; +signal FCF_APH : STD_LOGIC; +signal DMA_AZ_CS : STD_LOGIC; +signal DMA_ACTIV : STD_LOGIC; +signal DMA_ACTIV_NEW : STD_LOGIC; +signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); +-- SCSI +signal SCSI_CS : STD_LOGIC; +signal SCSI_CSn : STD_LOGIC; +signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); +signal nSCSI_DACK : STD_LOGIC; +signal SCSI_DRQ : STD_LOGIC; +signal SCSI_INT : STD_LOGIC; +signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); +signal DB_EN : STD_LOGIC; +signal DBP_OUTn : STD_LOGIC; +signal DBP_EN : STD_LOGIC; +signal RST_OUTn : STD_LOGIC; +signal RST_EN : STD_LOGIC; +signal BSY_OUTn : STD_LOGIC; +signal BSY_EN : STD_LOGIC; +signal SEL_OUTn : STD_LOGIC; +signal SEL_EN : STD_LOGIC; +-- IDE +signal nnIDE_RES : STD_LOGIC; +signal IDE_CF_CS : STD_LOGIC; +signal IDE_CF_TA : STD_LOGIC; +signal NEXT_nIDE_RD : STD_LOGIC; +signal NEXT_nIDE_WR : STD_LOGIC; +type CMD_STATES is( IDLE, T1, T6, T7); +signal CMD_STATE : CMD_STATES; +signal NEXT_CMD_STATE : CMD_STATES; + + +BEGIN +LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; +BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; +FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; +FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; + +FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; +SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE + '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE + '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; +nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; +nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; +nDREQ0 <= '0'; +---------------------------------------------------------------------------- +-- SD +---------------------------------------------------------------------------- +SD_CLK <= 'Z'; +SD_CD_DATA3 <= 'Z'; +SD_CDM_D1 <= 'Z'; +---------------------------------------------------------------------------- +-- IDE +---------------------------------------------------------------------------- +CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + begin + if nRSTO = '0' then + CMD_STATE <= IDLE; + elsif rising_edge(MAIN_CLK) then + CMD_STATE <= NEXT_CMD_STATE; -- go to next + nIDE_RD <= NEXT_nIDE_RD; -- go to next + nIDE_WR <= NEXT_nIDE_WR; -- go to next + else + CMD_STATE <= CMD_STATE; -- halten + nIDE_RD <= nIDE_RD; -- halten + nIDE_WR <= nIDE_WR; -- halten + end if; + end process CMD_REG; + + CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + begin + case CMD_STATE is + when IDLE => + IDE_CF_TA <= '0'; + if IDE_CF_CS = '1' then + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T1; + else + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end if; + when T1 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + when T6 => + IF IDE_RDY = '1' then + IDE_CF_TA <= '1'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= T7; + else + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= not nFB_WR; + NEXT_nIDE_WR <= nFB_WR; + NEXT_CMD_STATE <= T6; + end if; + when T7 => + IDE_CF_TA <= '0'; + NEXT_nIDE_RD <= '1'; + NEXT_nIDE_WR <= '1'; + NEXT_CMD_STATE <= IDLE; + end case; + end process CMD_DECODER; + +IDE_RES <= not nnIDE_RES and nRSTO; +IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 +nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F +nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F + '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F +nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F +nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F + '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F +----------------------------------------------------------------------------------------------------------------------------------------- +-- ACSI, SCSI UND FLOPPY WD1772 +------------------------------------------------------------------------------------------------------------------------------------------- +-- daten read fifo + RDF: dcfifo0 + port map( + aclr => CLR_FIFO, + data => RDF_DIN, + rdclk => MAIN_CLK, + rdreq => RDF_RDE, + wrclk => FDC_CLK, + wrreq => RDF_WRE, + q => RDF_DOUT, + wrusedw => RDF_AZ + ); +FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY +FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY +RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE +FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; +-- daten write fifo + WRF: dcfifo1 + port map( + aclr => CLR_FIFO, + data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), + rdclk => FDC_CLK, + rdreq => WRF_RDE, + wrclk => MAIN_CLK, + wrreq => WRF_WRE, + q => WRF_DOUT, + rdusedw => WRF_AZ + ); +CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB +DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG +FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + begin + if nRSTO = '0' THEN + WRF_WRE <= '0'; + elsif rising_edge(MAIN_CLK) then + IF FCF_APH = '1' and nFB_WR = '0' then + WRF_WRE <= '1'; + else + WRF_WRE <= '0'; + end if; + else + WRF_WRE <= WRF_WRE; + end if; + END PROCESS; + +FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + begin + if nRSTO = '0' then + FCF_STATE <= FCF_IDLE; + DMA_ACTIV <= '0'; + elsif rising_edge(FDC_CLK) then + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + else + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + end if; + end process FCF_REG; + +FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + begin + if nRSTO = '0' then + FDC_OUT <= x"00"; + elsif rising_edge(FDC_CLK) and FDCS_In = '0' then + FDC_OUT <= CD_OUT_FDC; -- set + else + FDC_OUT <= FDC_OUT; -- halten + end if; + end process FDC_REG; + +DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; +FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; +SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; + + FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + begin + case FCF_STATE is + when FCF_IDLE => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then + DMA_ACTIV_NEW <= DMA_REQ; + NEXT_FCF_STATE <= FCF_T0; + else + DMA_ACTIV_NEW <= '0'; + NEXT_FCF_STATE <= FCF_IDLE; + end if; + when FCF_T0 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= DMA_REQ; + WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO + if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start + else + NEXT_FCF_STATE <= FCF_T1; + end if; + when FCF_T1 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T2; + when FCF_T2 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T3; + when FCF_T3 => + RDF_WRE <= '0'; + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + NEXT_FCF_STATE <= FCF_T6; + when FCF_T6 => + WRF_RDE <= '0'; + DMA_ACTIV_NEW <= DMA_ACTIV; + SCSI_CSn <= not SCSI_CS; + FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO + NEXT_FCF_STATE <= FCF_T7; + when FCF_T7 => + SCSI_CSn <= '1'; + FDCS_In <= '1'; + RDF_WRE <= '0'; + WRF_RDE <= '0'; + nSCSI_DACK <= '1'; + DMA_ACTIV_NEW <= '0'; + if FDC_CS = '1' and DMA_REQ = '0' then + NEXT_FCF_STATE <= FCF_T7; + else + NEXT_FCF_STATE <= FCF_IDLE; + end if; + end case; + end process FCF_DECODER; + + I_FDC: WF1772IP_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + CSn => FDCS_In, + RWn => nFDC_WR, + A1 => CA2, + A0 => CA1, + DATA_IN => CD_IN_FDC, + DATA_OUT => CD_OUT_FDC, +-- DATA_EN => CD_EN_FDC, + RDn => nRD_DATA, + TR00n => TRACK00, + IPn => nINDEX, + WPRTn => nWP, + DDEn => '0', -- Fixed to MFM. + HDTYPE => HD_DD_OUT, + MO => MOT_ON, + WG => WR_GATE, + WD => WR_DATA, + STEP => STEP, + DIRC => STEP_DIR, + DRQ => DMA_DRQ_I, + INTRQ => FDINT + ); +DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 +DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 +WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 +HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); +nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; +CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); +CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); +CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); +FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else + SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else + DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +--- WDC BSL REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + WDC_BSL <= "00"; + elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + else + WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); + end if; + end if; + END PROCESS; +--- DMA MODUS REGISTER ------------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + begin + if nRSTO = '0' THEN + DMA_MODUS <= x"0000"; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then + IF FB_B0 = '1' THEN + DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); + else + DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); + end if; + IF FB_B1 = '1' THEN + DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); + else + DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); + end if; + else + DMA_MODUS <= DMA_MODUS; + end if; + END PROCESS; +-- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + begin + if nRSTO = '0' or CLR_FIFO = '1' THEN + DMA_BYT_CNT <= x"00000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then + DMA_BYT_CNT(31 downto 17) <= "000000000000000"; + DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); + DMA_BYT_CNT(8 downto 0) <= "000000000"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then + DMA_BYT_CNT <= FB_AD; + else + DMA_BYT_CNT <= DMA_BYT_CNT; + end if; + END PROCESS; +-------------------------------------------------------------------- +FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +DMA_STATUS(0) <= '1'; -- DMA OK +DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS +DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; +DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else + '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; +DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; +-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + process(FDC_CLK, nRSTO, DMA_DRQ_REG) + begin + if nRSTO = '0' THEN + DMA_DRQ_REG <= "00"; + elsif rising_edge(FDC_CLK) then + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + else + DMA_DRQ_REG <= DMA_DRQ_REG; + end if; + END PROCESS; +-- DMA ADRESSE ------------------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_TOP <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then + DMA_TOP <= FB_AD(31 downto 24); + else + DMA_TOP <= DMA_TOP; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + begin + if nRSTO = '0' THEN + DMA_HIGH <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then + DMA_HIGH <= FB_AD(23 downto 16); + else + DMA_HIGH <= DMA_HIGH; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + begin + DMA_MID <= DMA_MID; + if nRSTO = '0' THEN + DMA_MID <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_MID_CS = '1' then + DMA_MID <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_MID <= FB_AD(15 downto 8); + end if; + end if; + END PROCESS; + process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + begin + DMA_LOW <= DMA_LOW; + if nRSTO = '0' THEN + DMA_LOW <= x"00"; + elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then + if DMA_LOW_CS = '1'then + DMA_LOW <= FB_AD(23 downto 16); + elsif DMA_ADR_CS = '1' then + DMA_LOW <= FB_AD(7 downto 0); + end if; + end if; + END PROCESS; +-------------------------------------------------------------------------------------------- +DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 +DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 +DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 +DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 +FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +-- DIRECTZUGRIFF +DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD +DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG +DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG +FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; +FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; +-- DMA RW TOGGLE ------------------------------------------ + process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + begin + if nRSTO = '0' THEN + DMA_DIR_OLD <= '0'; + elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then + DMA_DIR_OLD <= DMA_MODUS(8); + else + DMA_DIR_OLD <= DMA_DIR_OLD; + end if; + END PROCESS; +CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; +-- SCSI ---------------------------------------------------------------------------------- + I_SCSI: WF5380_TOP_SOC + port map( + CLK => FDC_CLK, + RESETn => nRSTO, + ADR => CA2 & CA1 & CA0, + DATA_IN => CD_IN_FDC, + DATA_OUT => SCSI_DOUT, + --DATA_EN : out bit; + -- Bus and DMA controls: + CSn => '1', --SCSI_CSn, ABGESCHALTET + RDn => (not nFDC_WR) or (not SCSI_CS), + WRn => nFDC_WR or (not SCSI_CS), + EOPn => '1', + DACKn => nSCSI_DACK, + DRQ => SCSI_DRQ, + INT => SCSI_INT, +-- READY => + -- SCSI bus: + DB_INn => SCSI_D, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => SCSI_PAR, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, -- wenn 1 dann output + RST_INn => nSCSI_RST, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => nSCSI_BUSY, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => nSCSI_SEL, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => '1', + ACK_OUTn => nSCSI_ACK, +-- ACK_EN => ACK_EN, + ATN_INn => '1', + ATN_OUTn => nSCSI_ATN, +-- ATN_EN => ATN_EN, + REQ_INn => nSCSI_DRQ, +-- REQ_OUTn => REQ_OUTn, +-- REQ_EN => REQ_EN, + IOn_IN => nSCSI_I_O, +-- IOn_OUT => IOn_OUT, +-- IO_EN => IO_EN, + CDn_IN => nSCSI_C_D, +-- CDn_OUT => CDn_OUT, +-- CD_EN => CD_EN, + MSG_INn => nSCSI_MSG +-- MSG_OUTn => MSG_OUTn, +-- MSG_EN => MSG_EN + ); +-- SCSI ACSI --------------------------------------------------------------- +SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; +SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET +SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; +nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; +nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; +nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; +ACSI_DIR <= '0'; +ACSI_D <= "ZZZZZZZZ"; +nACSI_CS <= '1'; +ACSI_A1 <= CA1; +nACSI_RESET <= nRSTO; +nACSI_ACK <= '1'; +---------------------------------------------------------------------------- +-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns +---------------------------------------------------------------------------- +ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 +nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; +nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; +---------------------------------------------------------------------------- +-- ACIA KEYBOARD +---------------------------------------------------------------------------- + I_ACIA_KEYBOARD: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => FB_ADR(2), + CS1 => '1', + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_I, +-- DATA_EN => DATA_EN_ACIA_I, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => KEYB_RxD, + + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_KEYBDn, + TXDATA => AMKB_TX + --RTSn => -- Not used. + ); +ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 +KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL +FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; +-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + process(CLK2M, AMKB_RX, AMKB_REG) + begin + if rising_edge(CLK2M) then + IF AMKB_RX = '0' THEN + IF AMKB_REG < 16 THEN + AMKB_REG <= "00000"; + ELSE + AMKB_REG <= AMKB_REG - 1; + END IF; + ELSE + IF AMKB_REG > 15 THEN + AMKB_REG <= "11111"; + ELSE + AMKB_REG <= AMKB_REG + 1; + END IF; + END IF; + ELSE + AMKB_REG <= AMKB_REG; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- ACIA MIDI +---------------------------------------------------------------------------- + I_ACIA_MIDI: WF6850IP_TOP_SOC + port map( + CLK => MAIN_CLK, + RESETn => nRSTO, + + CS2n => '0', + CS1 => FB_ADR(2), + CS0 => ACIA_CS_I, + E => ACIA_CS_I, + RWn => nFB_WR, + RS => FB_ADR(1), + + DATA_IN => FB_AD(31 downto 24), + DATA_OUT => DATA_OUT_ACIA_II, +-- DATA_EN => DATA_EN_ACIA_II, + + TXCLK => CLK500k, + RXCLK => CLK500k, + RXDATA => MIDI_IN, + CTSn => '0', + DCDn => '0', + + IRQn => IRQ_MIDIn, + TXDATA => MIDI_OUT + --RTSn => -- Not used. + ); +MIDI_TLR <= MIDI_OUT; +MIDI_OLR <= MIDI_OUT; +FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +---------------------------------------------------------------------------- +-- MFP +---------------------------------------------------------------------------- + I_MFP: WF68901IP_TOP_SOC + port map( + -- System control: + CLK => MAIN_CLK, + RESETn => nRSTO, + -- Asynchronous bus control: + DSn => not LDS, + CSn => not MFP_CS, + RWn => nFB_WR, + DTACKn => DTACK_OUT_MFPn, + -- Data and Adresses: + RS => FB_ADR(5 downto 1), + DATA_IN => FB_AD(23 downto 16), + DATA_OUT => DATA_OUT_MFP, +-- DATA_EN => DATA_EN_MFP, + GPIP_IN(7) => not DMA_DRQ_Q, + GPIP_IN(6) => not RI, + GPIP_IN(5) => DINTn, + GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(3) => DSP_INT, + GPIP_IN(2) => not CTS, + GPIP_IN(1) => not DCD, + GPIP_IN(0) => LP_BUSY, + -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. + -- GPIP_EN =>, -- Not used; all GPIPs are direction input. + -- Interrupt control: + IACKn => not MFP_INTACK, + IEIn => '0', + -- IEOn =>, -- Not used. + IRQn => nMFP_INT, + -- Timers and timer control: + XTAL1 => CLK2M4576, + TAI => '0', + TBI => nBLANK, + -- TAO =>, + -- TBO =>, + -- TCO =>, + TDO => TDO, + -- Serial I/O control: + RC => TDO, + TC => TDO, + SI => RxD, + SO => TxD + -- SO_EN => MFP_SO_EN + -- DMA control: + -- RRn =>, + -- TRn => + ); + +MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 +MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 +LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; +FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; +FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; +DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else + '0' when FDINT = '1' else + '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1'; +-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) + begin + if nRSTO = '0' THEN + IRQ_ACIAn <= '1'; + elsif rising_edge(MAIN_CLK) then + IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; + else + IRQ_ACIAn <= IRQ_ACIAn; + end if; + END PROCESS; +---------------------------------------------------------------------------- +-- Sound +---------------------------------------------------------------------------- + I_SOUND: WF2149IP_TOP_SOC + port map( + SYS_CLK => MAIN_CLK, + RESETn => nRSTO, + + WAV_CLK => CLK2M, + SELn => '1', + + BDIR => SNDIR_I, + BC2 => '1', + BC1 => SNDCS_I, + + A9n => '0', + A8 => '1', + DA_IN => FB_AD(31 downto 24), + DA_OUT => DA_OUT_X, + + IO_A_IN => x"00", -- All port pins are dedicated outputs. + IO_A_OUT(7) => nnIDE_RES, + IO_A_OUT(6) => LP_DIR_X, + IO_A_OUT(5) => LP_STR, + IO_A_OUT(4) => DTR, + IO_A_OUT(3) => RTS, +-- IO_A_OUT(2) => FDD_D1SEL, + IO_A_OUT(1) => DSA_D, + IO_A_OUT(0) => nSDSEL, + -- IO_A_EN =>, -- Not required. + IO_B_IN => LP_D, + IO_B_OUT => LP_D_X, + -- IO_B_EN => IO_B_EN, + + OUT_A => YM_QA, + OUT_B => YM_QB, + OUT_C => YM_QC + ); + +SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 +SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; +SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; +FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; +LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; +LP_DIR <= LP_DIR_X; + +END FalconIO_SDCard_IDE_CF_architecture; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd new file mode 100644 index 0000000..edef447 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd @@ -0,0 +1,406 @@ +---------------------------------------------------------------------- +---- ---- +---- Atari Coldfire IP Core ---- +---- ---- +---- This file is part of the Atari Coldfire project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- 1.0 Initial Release, 20090925. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package FalconIO_SDCard_IDE_CF_PKG is + component WF25915IP_TOP_V1_SOC -- GLUE. + port ( + -- Clock system: + GL_CLK : in std_logic; -- Originally 8MHz. + GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK. + + -- Core address select: + GL_ROMSEL_FC_E0n : in std_logic; + EN_RAM_14MB : in std_logic; + -- Adress decoder outputs: + GL_ROM_6n : out std_logic; -- STE. + GL_ROM_5n : out std_logic; -- STE. + GL_ROM_4n : out std_logic; -- ST. + GL_ROM_3n : out std_logic; -- ST. + GL_ROM_2n : out std_logic; + GL_ROM_1n : out std_logic; + GL_ROM_0n : out std_logic; + + GL_ACIACS : out std_logic; + GL_MFPCSn : out std_logic; + GL_SNDCSn : out std_logic; + GL_FCSn : out std_logic; + + GL_STE_SNDCS : out std_logic; -- STE: Sound chip select. + GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control. + + GL_STE_RTCCSn : out std_logic; --STE only. + GL_STE_RTC_WRn : out std_logic; --STE only. + GL_STE_RTC_RDn : out std_logic; --STE only. + + -- 6800 peripheral control, + GL_VPAn : out std_logic; + GL_VMAn : in std_logic; + + GL_DMA_SYNC : in std_logic; + GL_DEVn : out std_logic; + GL_RAMn : out std_logic; + GL_DMAn : out std_logic; + + -- Interrupt system: + -- Comment out GL_AVECn for CPUs which do not provide the VMAn signal. + GL_AVECn : out std_logic; + GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only. + GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only. + GL_MFPINTn : in std_logic; -- ST. + GL_STE_EINT3n : in std_logic; --STE only. + GL_STE_EINT5n : in std_logic; --STE only. + GL_STE_EINT7n : in std_logic; --STE only. + GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only. + GL_IACKn : out std_logic; -- ST. + GL_STE_IPL2n : out std_logic; --STE only. + GL_STE_IPL1n : out std_logic; --STE only. + GL_STE_IPL0n : out std_logic; --STE only. + + -- Video timing: + GL_BLANKn : out std_logic; + GL_DE : out std_logic; + GL_MULTISYNC : in std_logic_vector(3 downto 2); + GL_VIDEO_HIMODE : out std_logic; + GL_HSYNC_INn : in std_logic; + GL_HSYNC_OUTn : out std_logic; + GL_VSYNC_INn : in std_logic; + GL_VSYNC_OUTn : out std_logic; + GL_SYNC_OUT_EN : out std_logic; + + -- Bus arstd_logicration control: + GL_RDY_INn : in std_logic; + GL_RDY_OUTn : out std_logic; + GL_BRn : out std_logic; + GL_BGIn : in std_logic; + GL_BGOn : out std_logic; + GL_BGACK_INn : in std_logic; + GL_BGACK_OUTn : out std_logic; + + -- Adress and data bus: + GL_ADDRESS : in std_logic_vector(23 downto 1); + -- ST: put the data bus to 1 downto 0. + -- STE: put the data out bus to 15 downto 0. + GL_DATA_IN : in std_logic_vector(7 downto 0); + GL_DATA_OUT : out std_logic_vector(15 downto 0); + GL_DATA_EN : out std_logic; + + -- Asynchronous bus control: + GL_RWn_IN : in std_logic; + GL_RWn_OUT : out std_logic; + GL_AS_INn : in std_logic; + GL_AS_OUTn : out std_logic; + GL_UDS_INn : in std_logic; + GL_UDS_OUTn : out std_logic; + GL_LDS_INn : in std_logic; + GL_LDS_OUTn : out std_logic; + GL_DTACK_INn : in std_logic; + GL_DTACK_OUTn : out std_logic; + GL_CTRL_EN : out std_logic; + + -- System control: + GL_RESETn : in std_logic; + GL_BERRn : out std_logic; + + -- Processor function codes: + GL_FC : in std_logic_vector(2 downto 0); + + -- STE enhancements: + GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD). + GL_STE_FCCLK : out std_logic; -- Floppy controller clock select. + GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte. + GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte. + GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte. + GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable. + GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte. + GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X. + GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y. + GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X. + GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y. + GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset. + GL_STE_PENn : in std_logic; -- Input of the light pen. + GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip. + GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor. + ); + end component WF25915IP_TOP_V1_SOC; + + component WF5380_TOP_SOC + port ( + CLK : in std_logic; + RESETn : in std_logic; + ADR : in std_logic_vector(2 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + CSn : in std_logic; + RDn : in std_logic; + WRn : in std_logic; + EOPn : in std_logic; + DACKn : in std_logic; + DRQ : out std_logic; + INT : out std_logic; + READY : out std_logic; + DB_INn : in std_logic_vector(7 downto 0); + DB_OUTn : out std_logic_vector(7 downto 0); + DB_EN : out std_logic; + DBP_INn : in std_logic; + DBP_OUTn : out std_logic; + DBP_EN : out std_logic; + RST_INn : in std_logic; + RST_OUTn : out std_logic; + RST_EN : out std_logic; + BSY_INn : in std_logic; + BSY_OUTn : out std_logic; + BSY_EN : out std_logic; + SEL_INn : in std_logic; + SEL_OUTn : out std_logic; + SEL_EN : out std_logic; + ACK_INn : in std_logic; + ACK_OUTn : out std_logic; + ACK_EN : out std_logic; + ATN_INn : in std_logic; + ATN_OUTn : out std_logic; + ATN_EN : out std_logic; + REQ_INn : in std_logic; + REQ_OUTn : out std_logic; + REQ_EN : out std_logic; + IOn_IN : in std_logic; + IOn_OUT : out std_logic; + IO_EN : out std_logic; + CDn_IN : in std_logic; + CDn_OUT : out std_logic; + CD_EN : out std_logic; + MSG_INn : in std_logic; + MSG_OUTn : out std_logic; + MSG_EN : out std_logic + ); + end component WF5380_TOP_SOC; + + component WF1772IP_TOP_SOC -- FDC. + port ( + CLK : in std_logic; -- 16MHz clock! + RESETn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + A1, A0 : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + RDn : in std_logic; + TR00n : in std_logic; + IPn : in std_logic; + WPRTn : in std_logic; + DDEn : in std_logic; + HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks. + MO : out std_logic; + WG : out std_logic; + WD : out std_logic; + STEP : out std_logic; + DIRC : out std_logic; + DRQ : out std_logic; + INTRQ : out std_logic + ); + end component WF1772IP_TOP_SOC; + + component WF68901IP_TOP_SOC -- MFP. + port ( -- System control: + CLK : in std_logic; + RESETn : in std_logic; + + -- Asynchronous bus control: + DSn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + DTACKn : out std_logic; + + -- Data and Adresses: + RS : in std_logic_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + GPIP_IN : in std_logic_vector(7 downto 0); + GPIP_OUT : out std_logic_vector(7 downto 0); + GPIP_EN : out std_logic_vector(7 downto 0); + + -- Interrupt control: + IACKn : in std_logic; + IEIn : in std_logic; + IEOn : out std_logic; + IRQn : out std_logic; + + -- Timers and timer control: + XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. + TAI : in std_logic; + TBI : in std_logic; + TAO : out std_logic; + TBO : out std_logic; + TCO : out std_logic; + TDO : out std_logic; + + -- Serial I/O control: + RC : in std_logic; + TC : in std_logic; + SI : in std_logic; + SO : out std_logic; + SO_EN : out std_logic; + + -- DMA control: + RRn : out std_logic; + TRn : out std_logic + ); + end component WF68901IP_TOP_SOC; + + component WF2149IP_TOP_SOC -- Sound. + port( + + SYS_CLK : in std_logic; -- Read the inforation in the header! + RESETn : in std_logic; + + WAV_CLK : in std_logic; -- Read the inforation in the header! + SELn : in std_logic; + + BDIR : in std_logic; + BC2, BC1 : in std_logic; + + A9n, A8 : in std_logic; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out std_logic; + + IO_A_IN : in std_logic_vector(7 downto 0); + IO_A_OUT : out std_logic_vector(7 downto 0); + IO_A_EN : out std_logic; + IO_B_IN : in std_logic_vector(7 downto 0); + IO_B_OUT : out std_logic_vector(7 downto 0); + IO_B_EN : out std_logic; + + OUT_A : out std_logic; -- Analog (PWM) outputs. + OUT_B : out std_logic; + OUT_C : out std_logic + ); + end component WF2149IP_TOP_SOC; + + component WF6850IP_TOP_SOC -- ACIA. + port ( + CLK : in std_logic; + RESETn : in std_logic; + + CS2n, CS1, CS0 : in std_logic; + E : in std_logic; + RWn : in std_logic; + RS : in std_logic; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + + TXCLK : in std_logic; + RXCLK : in std_logic; + RXDATA : in std_logic; + CTSn : in std_logic; + DCDn : in std_logic; + + IRQn : out std_logic; + TXDATA : out std_logic; + RTSn : out std_logic + ); + end component WF6850IP_TOP_SOC; + + component WF_SD_CARD + port ( + RESETn : in std_logic; + CLK : in std_logic; + ACSI_A1 : in std_logic; + ACSI_CSn : in std_logic; + ACSI_ACKn : in std_logic; + ACSI_INTn : out std_logic; + ACSI_DRQn : out std_logic; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out std_logic; + MC_DO : in std_logic; + MC_PIO_DMAn : in std_logic; + MC_RWn : in std_logic; + MC_CLR_CMD : in std_logic; + MC_DONE : out std_logic; + MC_GOT_CMD : out std_logic; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out std_logic + ); + end component WF_SD_CARD; + + component dcfifo0 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + end component dcfifo0; + + component dcfifo1 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + end component; + + +end FalconIO_SDCard_IDE_CF_PKG; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak new file mode 100644 index 0000000..4f42cf2 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak @@ -0,0 +1,406 @@ +---------------------------------------------------------------------- +---- ---- +---- Atari Coldfire IP Core ---- +---- ---- +---- This file is part of the Atari Coldfire project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- 1.0 Initial Release, 20090925. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package FalconIO_SDCard_IDE_CF_PKG is + component WF25915IP_TOP_V1_SOC -- GLUE. + port ( + -- Clock system: + GL_CLK : in std_logic; -- Originally 8MHz. + GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK. + + -- Core address select: + GL_ROMSEL_FC_E0n : in std_logic; + EN_RAM_14MB : in std_logic; + -- Adress decoder outputs: + GL_ROM_6n : out std_logic; -- STE. + GL_ROM_5n : out std_logic; -- STE. + GL_ROM_4n : out std_logic; -- ST. + GL_ROM_3n : out std_logic; -- ST. + GL_ROM_2n : out std_logic; + GL_ROM_1n : out std_logic; + GL_ROM_0n : out std_logic; + + GL_ACIACS : out std_logic; + GL_MFPCSn : out std_logic; + GL_SNDCSn : out std_logic; + GL_FCSn : out std_logic; + + GL_STE_SNDCS : out std_logic; -- STE: Sound chip select. + GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control. + + GL_STE_RTCCSn : out std_logic; --STE only. + GL_STE_RTC_WRn : out std_logic; --STE only. + GL_STE_RTC_RDn : out std_logic; --STE only. + + -- 6800 peripheral control, + GL_VPAn : out std_logic; + GL_VMAn : in std_logic; + + GL_DMA_SYNC : in std_logic; + GL_DEVn : out std_logic; + GL_RAMn : out std_logic; + GL_DMAn : out std_logic; + + -- Interrupt system: + -- Comment out GL_AVECn for CPUs which do not provide the VMAn signal. + GL_AVECn : out std_logic; + GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only. + GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only. + GL_MFPINTn : in std_logic; -- ST. + GL_STE_EINT3n : in std_logic; --STE only. + GL_STE_EINT5n : in std_logic; --STE only. + GL_STE_EINT7n : in std_logic; --STE only. + GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only. + GL_IACKn : out std_logic; -- ST. + GL_STE_IPL2n : out std_logic; --STE only. + GL_STE_IPL1n : out std_logic; --STE only. + GL_STE_IPL0n : out std_logic; --STE only. + + -- Video timing: + GL_BLANKn : out std_logic; + GL_DE : out std_logic; + GL_MULTISYNC : in std_logic_vector(3 downto 2); + GL_VIDEO_HIMODE : out std_logic; + GL_HSYNC_INn : in std_logic; + GL_HSYNC_OUTn : out std_logic; + GL_VSYNC_INn : in std_logic; + GL_VSYNC_OUTn : out std_logic; + GL_SYNC_OUT_EN : out std_logic; + + -- Bus arstd_logicration control: + GL_RDY_INn : in std_logic; + GL_RDY_OUTn : out std_logic; + GL_BRn : out std_logic; + GL_BGIn : in std_logic; + GL_BGOn : out std_logic; + GL_BGACK_INn : in std_logic; + GL_BGACK_OUTn : out std_logic; + + -- Adress and data bus: + GL_ADDRESS : in std_logic_vector(23 downto 1); + -- ST: put the data bus to 1 downto 0. + -- STE: put the data out bus to 15 downto 0. + GL_DATA_IN : in std_logic_vector(7 downto 0); + GL_DATA_OUT : out std_logic_vector(15 downto 0); + GL_DATA_EN : out std_logic; + + -- Asynchronous bus control: + GL_RWn_IN : in std_logic; + GL_RWn_OUT : out std_logic; + GL_AS_INn : in std_logic; + GL_AS_OUTn : out std_logic; + GL_UDS_INn : in std_logic; + GL_UDS_OUTn : out std_logic; + GL_LDS_INn : in std_logic; + GL_LDS_OUTn : out std_logic; + GL_DTACK_INn : in std_logic; + GL_DTACK_OUTn : out std_logic; + GL_CTRL_EN : out std_logic; + + -- System control: + GL_RESETn : in std_logic; + GL_BERRn : out std_logic; + + -- Processor function codes: + GL_FC : in std_logic_vector(2 downto 0); + + -- STE enhancements: + GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD). + GL_STE_FCCLK : out std_logic; -- Floppy controller clock select. + GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte. + GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte. + GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte. + GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable. + GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte. + GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X. + GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y. + GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X. + GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y. + GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset. + GL_STE_PENn : in std_logic; -- Input of the light pen. + GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip. + GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor. + ); + end component WF25915IP_TOP_V1_SOC; + + component WF5380_TOP_SOC + port ( + CLK : in std_logic; + RESETn : in std_logic; + ADR : in std_logic_vector(2 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + CSn : in std_logic; + RDn : in std_logic; + WRn : in std_logic; + EOPn : in std_logic; + DACKn : in std_logic; + DRQ : out std_logic; + INT : out std_logic; + READY : out std_logic; + DB_INn : in std_logic_vector(7 downto 0); + DB_OUTn : out std_logic_vector(7 downto 0); + DB_EN : out std_logic; + DBP_INn : in std_logic; + DBP_OUTn : out std_logic; + DBP_EN : out std_logic; + RST_INn : in std_logic; + RST_OUTn : out std_logic; + RST_EN : out std_logic; + BSY_INn : in std_logic; + BSY_OUTn : out std_logic; + BSY_EN : out std_logic; + SEL_INn : in std_logic; + SEL_OUTn : out std_logic; + SEL_EN : out std_logic; + ACK_INn : in std_logic; + ACK_OUTn : out std_logic; + ACK_EN : out std_logic; + ATN_INn : in std_logic; + ATN_OUTn : out std_logic; + ATN_EN : out std_logic; + REQ_INn : in std_logic; + REQ_OUTn : out std_logic; + REQ_EN : out std_logic; + IOn_IN : in std_logic; + IOn_OUT : out std_logic; + IO_EN : out std_logic; + CDn_IN : in std_logic; + CDn_OUT : out std_logic; + CD_EN : out std_logic; + MSG_INn : in std_logic; + MSG_OUTn : out std_logic; + MSG_EN : out std_logic + ); + end component WF5380_TOP_SOC; + + component WF1772IP_TOP_SOC -- FDC. + port ( + CLK : in std_logic; -- 16MHz clock! + RESETn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + A1, A0 : in std_logic; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + RDn : in std_logic; + TR00n : in std_logic; + IPn : in std_logic; + WPRTn : in std_logic; + DDEn : in std_logic; + HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks. + MO : out std_logic; + WG : out std_logic; + WD : out std_logic; + STEP : out std_logic; + DIRC : out std_logic; + DRQ : out std_logic; + INTRQ : out std_logic + ); + end component WF1772IP_TOP_SOC; + + component WF68901IP_TOP_SOC -- MFP. + port ( -- System control: + CLK : in std_logic; + RESETn : in std_logic; + + -- Asynchronous bus control: + DSn : in std_logic; + CSn : in std_logic; + RWn : in std_logic; + DTACKn : out std_logic; + + -- Data and Adresses: + RS : in std_logic_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + GPIP_IN : in std_logic_vector(7 downto 0); + GPIP_OUT : out std_logic_vector(7 downto 0); + GPIP_EN : out std_logic_vector(7 downto 0); + + -- Interrupt control: + IACKn : in std_logic; + IEIn : in std_logic; + IEOn : out std_logic; + IRQn : out std_logic; + + -- Timers and timer control: + XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. + TAI : in std_logic; + TBI : in std_logic; + TAO : out std_logic; + TBO : out std_logic; + TCO : out std_logic; + TDO : out std_logic; + + -- Serial I/O control: + RC : in std_logic; + TC : in std_logic; + SI : in std_logic; + SO : out std_logic; + SO_EN : out std_logic; + + -- DMA control: + RRn : out std_logic; + TRn : out std_logic + ); + end component WF68901IP_TOP_SOC; + + component WF2149IP_TOP_SOC -- Sound. + port( + + SYS_CLK : in std_logic; -- Read the inforation in the header! + RESETn : in std_logic; + + WAV_CLK : in std_logic; -- Read the inforation in the header! + SELn : in std_logic; + + BDIR : in std_logic; + BC2, BC1 : in std_logic; + + A9n, A8 : in std_logic; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out std_logic; + + IO_A_IN : in std_logic_vector(7 downto 0); + IO_A_OUT : out std_logic_vector(7 downto 0); + IO_A_EN : out std_logic; + IO_B_IN : in std_logic_vector(7 downto 0); + IO_B_OUT : out std_logic_vector(7 downto 0); + IO_B_EN : out std_logic; + + OUT_A : out std_logic; -- Analog (PWM) outputs. + OUT_B : out std_logic; + OUT_C : out std_logic + ); + end component WF2149IP_TOP_SOC; + + component WF6850IP_TOP_SOC -- ACIA. + port ( + CLK : in std_logic; + RESETn : in std_logic; + + CS2n, CS1, CS0 : in std_logic; + E : in std_logic; + RWn : in std_logic; + RS : in std_logic; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out std_logic; + + TXCLK : in std_logic; + RXCLK : in std_logic; + RXDATA : in std_logic; + CTSn : in std_logic; + DCDn : in std_logic; + + IRQn : out std_logic; + TXDATA : out std_logic; + RTSn : out std_logic + ); + end component WF6850IP_TOP_SOC; + + component WF_SD_CARD + port ( + RESETn : in std_logic; + CLK : in std_logic; + ACSI_A1 : in std_logic; + ACSI_CSn : in std_logic; + ACSI_ACKn : in std_logic; + ACSI_INTn : out std_logic; + ACSI_DRQn : out std_logic; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out std_logic; + MC_DO : in std_logic; + MC_PIO_DMAn : in std_logic; + MC_RWn : in std_logic; + MC_CLR_CMD : in std_logic; + MC_DONE : out std_logic; + MC_GOT_CMD : out std_logic; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out std_logic + ); + end component WF_SD_CARD; + + component dcfifo0 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + end component dcfifo0; + + component dcfifo1 + PORT ( + aclr : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + end component; + + +end FalconIO_SDCard_IDE_CF_PKG; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd new file mode 100644 index 0000000..4453332 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd @@ -0,0 +1,631 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the 5380's system controller. ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_CONTROL is + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; -- System reset. + + -- System controls: + BSY_INn : in bit; -- SCSI BSY_INn bit. + BSY_OUTn : out bit; -- SCSI BSY_INn bit. + DATA_EN : out bit; -- Enable the SCSI data lines. + SEL_INn : in bit; -- SCSI SEL_INn bit. + ARB_EN : in bit; -- Arbitration enable. + BSY_DISn : in bit; -- BSY monitoring enable. + RSTn : in bit; -- SCSI reset. + + ARB : out bit; -- Arbitration flag. + AIP : out bit; -- Arbitration in progress flag. + LA : out bit; -- Lost arbitration flag. + + ACK_INn : in bit; + ACK_OUTn : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + + DACKn : in bit; -- Data acknowledge. + READY : out bit; + DRQ : out bit; -- Data request. + + TARG : in bit; -- Target mode indicator. + BLK : in bit; -- Block mode indicator. + PINT_EN : in bit; -- Parity interrupt enable. + SPER : in bit; -- Parity error. + SER_ID : in bit; -- SER matches ODR bits. + RPI : in bit; -- Reset interrupts. + DMA_EN : in bit; -- DMA mode enable. + SDS : in bit; -- Start DMA send, write only. + SDT : in bit; -- Start DMA target receive, write only. + SDI : in bit; -- Start DMA initiator receive, write only. + EOP_EN : in bit; -- EOP interrupt enable. + EOPn : in bit; -- End of process indicator. + PHSM : in bit; -- Phase match flag. + + INT : out bit; -- Interrupt. + IDR_WR : out bit; -- Write input data register during DMA. + ODR_WR : out bit; -- Write output data register, during DMA. + CHK_PAR : out bit; -- Check Parity during DMA operation. + BSY_ERR : out bit; -- Busy monitoring error. + DMA_SND : out bit; -- Indicates direction of target DMA. + DMA_ACTIVE : out bit -- DMA is active. + ); +end entity WF5380_CONTROL; + +architecture BEHAVIOUR of WF5380_CONTROL is +type CTRL_STATES is (IDLE, WAIT_800ns, WAIT_2200ns, DMA_SEND, DMA_TARG_RCV, DMA_INIT_RCV); +type DMA_STATES is (IDLE, DMA_STEP_1, DMA_STEP_2, DMA_STEP_3, DMA_STEP_4); +signal CTRL_STATE : CTRL_STATES; +signal NEXT_CTRL_STATE : CTRL_STATES; +signal DMA_STATE : DMA_STATES; +signal NEXT_DMA_STATE : DMA_STATES; +signal BUS_FREE : bit; +signal DELAY_800ns : boolean; +signal DELAY_2200ns : boolean; +signal DMA_ACTIVE_I : bit; +signal EOP_In : bit; +begin + IN_BUFFER: process + -- This buffer shall prevent some signals against + -- setup hold effects and thus the state machine + -- against unpredictable behaviour. + begin + wait until CLK = '1' and CLK' event; + EOP_In <= EOPn; + end process IN_BUFFER; + + STATE_REGISTERS: process(RESETn, CLK) + -- This is the controller's state machine register. + variable BSY_LOCK : boolean; + begin + if RESETn = '0' then + CTRL_STATE <= IDLE; + DMA_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if RSTn = '0' then -- SCSI reset. + CTRL_STATE <= IDLE; + DMA_STATE <= IDLE; + else + CTRL_STATE <= NEXT_CTRL_STATE; + DMA_STATE <= NEXT_DMA_STATE; + end if; + -- + if DMA_EN = '0' then + DMA_STATE <= IDLE; + end if; + end if; + end process STATE_REGISTERS; + + CTRL_DECODER: process(CTRL_STATE, ARB_EN, BUS_FREE, DELAY_800ns, SEL_INn, DMA_ACTIVE_I, SDS, SDT, SDI) + -- This is the controller's state machine decoder. + variable BSY_LOCK : boolean; + begin + -- Defaults. + DMA_SND <= '0'; + -- + case CTRL_STATE is + when IDLE => + if ARB_EN = '1' and BUS_FREE = '1' then + NEXT_CTRL_STATE <= WAIT_800ns; + else + NEXT_CTRL_STATE <= IDLE; + end if; + when WAIT_800ns => + if DELAY_800ns = true then + NEXT_CTRL_STATE <= WAIT_2200ns; + else + NEXT_CTRL_STATE <= WAIT_800ns; + end if; + when WAIT_2200ns => + -- In this state the delay is provided by the + -- microprocessor and is at least 2.2us. The + -- delay is released by deasserting SELn. + if SEL_INn = '1' and SDS = '1' then + NEXT_CTRL_STATE <= DMA_SEND; + elsif SEL_INn = '1' and SDT = '1' then + NEXT_CTRL_STATE <= DMA_TARG_RCV; + elsif SEL_INn = '1' and SDI = '1' then + NEXT_CTRL_STATE <= DMA_INIT_RCV; + else + NEXT_CTRL_STATE <= WAIT_2200ns; + end if; + when DMA_SEND => + if DMA_ACTIVE_I = '0' then + NEXT_CTRL_STATE <= IDLE; + else + NEXT_CTRL_STATE <= DMA_SEND; + end if; + -- + DMA_SND <= '1'; + when DMA_TARG_RCV => + if DMA_ACTIVE_I = '0' then + NEXT_CTRL_STATE <= IDLE; + else + NEXT_CTRL_STATE <= DMA_TARG_RCV; + end if; + when DMA_INIT_RCV => + if DMA_ACTIVE_I = '0' then + NEXT_CTRL_STATE <= IDLE; + else + NEXT_CTRL_STATE <= DMA_INIT_RCV; + end if; + end case; + end process CTRL_DECODER; + + DMA_DECODER: process(CTRL_STATE, DMA_STATE, TARG, BLK, DACKn, REQ_INn, ACK_INn) + -- This is the DMA state machine decoder. + begin + -- Defaults: + IDR_WR <= '0'; + ODR_WR <= '0'; + CHK_PAR <= '0'; + -- + case DMA_STATE is + when IDLE => + if CTRL_STATE = DMA_SEND then + NEXT_DMA_STATE <= DMA_STEP_1; + elsif CTRL_STATE = DMA_INIT_RCV then + NEXT_DMA_STATE <= DMA_STEP_1; + elsif CTRL_STATE = DMA_TARG_RCV then + NEXT_DMA_STATE <= DMA_STEP_1; + else + NEXT_DMA_STATE <= IDLE; + end if; + when DMA_STEP_1 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted. + IDR_WR <= '1'; + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted. + IDR_WR <= '1'; + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted. + ODR_WR <= '1'; + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted. + IDR_WR <= '1'; + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted. + IDR_WR <= '1'; + else + NEXT_DMA_STATE <= DMA_STEP_1; + end if; + when DMA_STEP_2 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted. + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted. + else + NEXT_DMA_STATE <= DMA_STEP_2; + end if; + when DMA_STEP_3 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted. + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '0' then + NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted. + CHK_PAR <= '1'; + else + NEXT_DMA_STATE <= DMA_STEP_3; + end if; + when DMA_STEP_4 => + -- Initiator modes: + if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + -- Target modes: + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted. + elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '1' then + NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted. + else + NEXT_DMA_STATE <= DMA_STEP_4; + end if; + end case; + end process DMA_DECODER; + + P_REQn: process(DMA_STATE, CTRL_STATE, TARG, BLK) + -- This logic controls the REQn output in target mode. + begin + if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then + REQ_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then + REQ_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then + REQ_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then + REQ_OUTn <= '0'; + else + REQ_OUTn <= '1'; + end if; + end process P_REQn; + + P_ACKn: process(DMA_STATE, CTRL_STATE, TARG, BLK) + -- This logic controls the ACKn output in initiator mode. + begin + if DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then + ACK_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then + ACK_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then + ACK_OUTn <= '0'; + elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then + ACK_OUTn <= '0'; + else + ACK_OUTn <= '1'; + end if; + end process P_ACKn; + + P_READY: process(DMA_STATE, CTRL_STATE, TARG, BLK) + -- This logic controls the READY output in initiator and target block mode. + begin + if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then + READY <= '1'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then + READY <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then + READY <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then + READY <= '1'; + else + READY <= '0'; + end if; + end process P_READY; + + P_DRQ: process(RESETn, CLK) + -- This flip flop controls the DRQ flag during all initiator and all target modes + -- for both block mode and non block mode operation. + variable LOCK : boolean; + begin + if RESETn = '0' then + DRQ <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + -- Initiator modes: + if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and LOCK = false then + DRQ <= '1'; + LOCK := true; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then + DRQ <= '1'; + LOCK := true; + -- Target modes: + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then + DRQ <= '1'; + LOCK := true; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then + DRQ <= '1'; + elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then + DRQ <= '1'; + LOCK := true; + elsif DACKn = '0' and LOCK = false then + DRQ <= '0'; + elsif EOPn = '0' and DACKn = '0' then + DRQ <= '0'; + LOCK := false; + end if; + end if; + end process P_DRQ; + + P_BUSFREE: process(RESETn, CLK) + -- This is the logic for the bus free signal. + -- A bus free is valid if the BSY_INn signal is + -- at least 437.5ns inactive ans SEL_INn is inactive. + -- The delay are 7 clock cycles of 16MHz. + variable TMP : std_logic_vector(2 downto 0); + begin + if RESETn = '0' then + BUS_FREE <= '0'; + TMP := "000"; + elsif CLK = '1' and CLK' event then + if BSY_INn = '1' and TMP < x"111" then + TMP := TMP + '1'; + elsif BSY_INn = '0' then + TMP := "000"; + end if; + -- + if RSTn = '0' then -- SCSI reset. + BUS_FREE <= '0'; + elsif SEL_INn = '1' and TMP = "111" then + BUS_FREE <= '1'; + else + BUS_FREE <= '0'; + end if; + end if; + end process P_BUSFREE; + + DELAY_800: process(RESETn, CLK) + -- This is the delay of 812.5ns. + -- It is derived from 13 16MHz clock cycles. + variable TMP : std_logic_vector(3 downto 0); + begin + if RESETn = '0' then + DELAY_800ns <= false; + TMP := x"0"; + elsif CLK = '1' and CLK' event then + if CTRL_STATE /= WAIT_800ns then + TMP := x"0"; + elsif TMP <= x"D" then + TMP := TMP + '1'; + end if; + -- + if TMP = x"D" then + DELAY_800ns <= true; + else + DELAY_800ns <= false; + end if; + end if; + end process DELAY_800; + + P_ARB: process(RESETn, CLK) + -- This flip flop controls the ARB flag read back + -- by the microcontroller. + begin + if RESETn = '0' then + ARB <= '0'; + elsif CLK = '1' and CLK' event then + if CTRL_STATE /= WAIT_800ns and NEXT_CTRL_STATE = WAIT_800ns then + ARB <= '1'; + elsif ARB_EN = '0' then + ARB <= '0'; + end if; + end if; + end process P_ARB; + + P_AIP: process(RESETn, CLK) + -- This flip flop controls the AIP flag read back + -- by the microcontroller. + begin + if RESETn = '0' then + AIP <= '0'; + elsif CLK = '1' and CLK' event then + if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then + AIP <= '1'; + elsif ARB_EN = '0' then + AIP <= '0'; + end if; + end if; + end process P_AIP; + + P_BSY: process + -- This flip flop controls the BSYn output + -- to the SCSI bus. + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + BSY_OUTn <= '1'; + elsif CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then + BSY_OUTn <= '0'; + elsif ARB_EN = '0' then + BSY_OUTn <= '1'; + end if; + end process P_BSY; + + P_DATA_EN: process(RESETn, CLK) + -- This flip flop controls the data enable + -- of the SCSI bus. + begin + if RESETn = '0' then + DATA_EN <= '0'; + elsif CLK = '1' and CLK' event then + if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then + DATA_EN <= '1'; + elsif ARB_EN = '0' then + DATA_EN <= '0'; + end if; + end if; + end process P_DATA_EN; + + P_LA: process(RESETn, CLK) + -- This flip flop controls the LA + -- (lost arbitration) flag. + begin + if RESETn = '0' then + LA <= '0'; + elsif CLK = '1' and CLK' event then + if (CTRL_STATE = WAIT_800ns or CTRL_STATE = WAIT_2200ns) and SEL_INn = '0' then + LA <= '1'; + elsif ARB_EN = '0' then + LA <= '0'; + end if; + end if; + end process P_LA; + + P_DMA_ACTIVE: process(RESETn, CLK, DMA_ACTIVE_I) + -- This is the Flip Flop indicating if there is DMA + -- operation. + begin + if RESETn = '0' then + DMA_ACTIVE_I <= '0'; + elsif CLK = '1' and CLK' event then + if DMA_EN = '1' and SDS = '1' then + DMA_ACTIVE_I <= '1'; -- Start DMA send. + elsif DMA_EN = '1' and SDT = '1' then + DMA_ACTIVE_I <= '1'; -- Start DMA target receive. + elsif DMA_EN = '1' and SDI = '1' then + DMA_ACTIVE_I <= '1'; -- Start DMA initiator receive. + elsif DMA_EN = '0' then + DMA_ACTIVE_I <= '0'; -- Halt DMA via DMA flag in MR2. + elsif EOP_In = '0' then + DMA_ACTIVE_I <= '0'; -- Halt DMA via EOPn. + elsif PHSM = '0' then + DMA_ACTIVE_I <= '0'; -- Halt DMA via phase mismatch. + end if; + end if; + -- + DMA_ACTIVE <= DMA_ACTIVE_I; + end process P_DMA_ACTIVE; + + INTERRUPTS: process(RESETn, CLK) + -- This is the logic for all DP5380's interrupt sources. + -- A busy interrupt occurs if the BSY_INn signal is at + -- least 437.5ns inactive. The delay are 7 clock cycles + -- of 16MHz. This logic also provides the respective + -- error flags for the BSR. + variable TMP : std_logic_vector(2 downto 0); + begin + if RESETn = '0' then + INT <= '0'; + BSY_ERR <= '0'; + TMP := "000"; + elsif CLK = '1' and CLK' event then + if SPER = '1' and PINT_EN = '1' then + INT <= '1'; -- Parity interrupt. + elsif RPI = '0' then -- Reset interrupts. + INT <= '0'; + end if; + -- + if EOP_In = '0' and CTRL_STATE = DMA_SEND then + BSY_ERR <= '1'; -- End of DMA error. + elsif EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then + BSY_ERR <= '1'; -- End of DMA error. + elsif EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then + BSY_ERR <= '1'; -- End of DMA error. + elsif DMA_EN = '0' then -- Reset error. + INT <= '0'; + end if; + -- + if EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_SEND then + INT <= '1'; -- End of DMA interrupt. + elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then + INT <= '1'; -- End of DMA interrupt. + elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then + INT <= '1'; -- End of DMA interrupt. + elsif DMA_EN = '0' then -- Reset interrupt. + INT <= '0'; + end if; + + -- + if PHSM = '0' then + INT <= '1'; -- Phase mismatch interrupt. + elsif DMA_EN = '0' then -- Reset interrupts. + INT <= '0'; + end if; + -- + if SEL_INn = '0' and BSY_INn = '1' and SER_ID = '1' then + INT <= '1'; -- (Re)Selection interrupt. + elsif RPI = '1' then -- Reset interrupts. + INT <= '0'; + end if; + -- + if BSY_INn = '1' and TMP < x"111" then + TMP := TMP + '1'; -- Bus settle delay. + elsif BSY_INn = '0' then + TMP := "000"; + end if; + -- + if BSY_DISn = '1' and BSY_INn = '1' and TMP = x"111" then + INT <= '1'; -- Busy monitoring interrupt. + BSY_ERR <= '1'; + elsif RPI = '1' then -- Reset interrupts. + INT <= '0'; + BSY_ERR <= '0'; + end if; + -- + end if; + end process INTERRUPTS; +end BEHAVIOUR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd new file mode 100644 index 0000000..57cf305 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd @@ -0,0 +1,139 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the package file of the ip core. ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. + +library ieee; +use ieee.std_logic_1164.all; + +package WF5380_PKG is + component WF5380_REGISTERS + port ( + CLK : in bit; + RESETn : in bit; + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + CSn : in bit; + RDn : in bit; + WRn : in bit; + RSTn : in bit; + RST : out bit; + ARB_EN : out bit; + DMA_ACTIVE : in bit; + DMA_EN : out bit; + BSY_DISn : out bit; + EOP_EN : out bit; + PINT_EN : out bit; + SPER : out bit; + TARG : out bit; + BLK : out bit; + DMA_DIS : in bit; + IDR_WR : in bit; + ODR_WR : in bit; + CHK_PAR : in bit; + AIP : in bit; + ARB : in bit; + LA : in bit; + CSD : in bit_vector(7 downto 0); + CSB : in bit_vector(7 downto 0); + BSR : in bit_vector(7 downto 0); + ODR_OUT : out bit_vector(7 downto 0); + ICR_OUT : out bit_vector(7 downto 0); + TCR_OUT : out bit_vector(3 downto 0); + SER_OUT : out bit_vector(7 downto 0); + SDS : out bit; + SDT : out bit; + SDI : out bit; + RPI : out bit + ); + end component; + + component WF5380_CONTROL + port ( + CLK : in bit; + RESETn : in bit; + BSY_INn : in bit; + BSY_OUTn : out bit; + DATA_EN : out bit; + SEL_INn : in bit; + ARB_EN : in bit; + BSY_DISn : in bit; + RSTn : in bit; + ARB : out bit; + AIP : out bit; + LA : out bit; + ACK_INn : in bit; + ACK_OUTn : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + DACKn : in bit; + READY : out bit; + DRQ : out bit; + TARG : in bit; + BLK : in bit; + PINT_EN : in bit; + SPER : in bit; + SER_ID : in bit; + RPI : in bit; + DMA_EN : in bit; + SDS : in bit; + SDT : in bit; + SDI : in bit; + EOP_EN : in bit; + EOPn : in bit; + PHSM : in bit; + INT : out bit; + IDR_WR : out bit; + ODR_WR : out bit; + CHK_PAR : out bit; + BSY_ERR : out bit; + DMA_SND : out bit; + DMA_ACTIVE : out bit + ); + end component; +end WF5380_PKG; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd new file mode 100644 index 0000000..2c21c12 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd @@ -0,0 +1,265 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the 5380's register model. ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Register description (for more information see the DP5380 ---- +---- data sheet: ---- +---- ODR (address 0) Output data register, write only. ---- +---- CSD (address 0) Current SCSI data, read only. ---- +---- ICR (address 1) Initiator command register, read/write. ---- +---- MR2 (address 2) Mode register 2, read/write. ---- +---- TCR (address 3) Target command register, read/write. ---- +---- SER (address 4) Select enable register, write only. ---- +---- CSB (address 4) Current SCSI bus status, read only. ---- +---- BSR (address 5) Start DMA send, write only. ---- +---- SDS (address 5) Bus and status, read only. ---- +---- SDT (address 6) Start DMA target receive, write only. ---- +---- IDR (address 6) Input data register, read only. ---- +---- SDI (address 7) Start DMA initiator recive, write only. ---- +---- RPI (address 7) Reset parity / interrupts, read only. ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_REGISTERS is + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; -- System reset. + + -- Address and data: + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Bus and DMA controls: + CSn : in bit; + RDn : in bit; + WRn : in bit; + + -- Core controls: + RSTn : in bit; -- SCSI reset. + RST : out bit; -- Programmed SCSI reset. + ARB_EN : out bit; -- Arbitration enable. + DMA_ACTIVE : in bit; -- DMA is running. + DMA_EN : out bit; -- DMA mode enable. + BSY_DISn : out bit; -- BSY monitoring enable. + EOP_EN : out bit; -- EOP interrupt enable. + PINT_EN : out bit; -- Parity interrupt enable. + SPER : out bit; -- Parity error. + TARG : out bit; -- Target mode. + BLK : out bit; -- Block DMA mode. + DMA_DIS : in bit; -- Reset the DMA_EN by this signal. + IDR_WR : in bit; -- Write input data register during DMA. + ODR_WR : in bit; -- Write output data register, during DMA. + CHK_PAR : in bit; -- Check Parity during DMA operation. + AIP : in bit; -- Arbitration in progress. + ARB : in bit; -- Arbitration. + LA : in bit; -- Lost arbitration. + + CSD : in bit_vector(7 downto 0); -- SCSI data. + CSB : in bit_vector(7 downto 0); -- Current SCSI bus status. + BSR : in bit_vector(7 downto 0); -- Bus and status. + + ODR_OUT : out bit_vector(7 downto 0); -- This is the ODR register. + ICR_OUT : out bit_vector(7 downto 0); -- This is the ICR register. + TCR_OUT : out bit_vector(3 downto 0); -- This is the TCR register. + SER_OUT : out bit_vector(7 downto 0); -- This is the SER register. + + SDS : out bit; -- Start DMA send, write only. + SDT : out bit; -- Start DMA target receive, write only. + SDI : out bit; -- Start DMA initiator receive, write only. + RPI : out bit + ); +end entity WF5380_REGISTERS; + +architecture BEHAVIOUR of WF5380_REGISTERS is +signal ICR : bit_vector(7 downto 0); -- Initiator command register, read/write. +signal IDR : bit_vector(7 downto 0); -- Input data register. +signal MR2 : bit_vector(7 downto 0); -- Mode register 2, read/write. +signal ODR : bit_vector(7 downto 0); -- Output data register, write only. +signal SER : bit_vector(7 downto 0); -- Select enable register, write only. +signal TCR : bit_vector(3 downto 0); -- Target command register, read/write. +begin + REGISTERS: process(RESETn, CLK) + -- This process reflects all registers in the 5380. + variable BSY_LOCK : boolean; + begin + if RESETn = '0' then + ODR <= (others => '0'); + ICR <= (others => '0'); + MR2 <= (others => '0'); + TCR <= (others => '0'); + SER <= (others => '0'); + BSY_LOCK := false; + elsif CLK = '1' and CLK' event then + if RSTn = '0' then -- SCSI reset. + ODR <= (others => '0'); + ICR(6 downto 0) <= (others => '0'); + MR2(7) <= '0'; + MR2(5 downto 0) <= (others => '0'); + TCR <= (others => '0'); + SER <= (others => '0'); + BSY_LOCK := false; + elsif ADR = "000" and CSn = '0' and WRn = '0' then + ODR <= DATA_IN; + elsif ADR = "001" and CSn = '0' and WRn = '0' then + ICR <= DATA_IN; + elsif ADR = "010" and CSn = '0' and WRn = '0' then + MR2 <= DATA_IN; + elsif ADR = "011" and CSn = '0' and WRn = '0' then + TCR <= DATA_IN(3 downto 0); + elsif ADR = "100" and CSn = '0' and WRn = '0' then + SER <= DATA_IN; + end if; + -- + if ODR_WR = '1' then + ODR <= DATA_IN; + end if; + -- + -- This reset function is edge triggered on the 'Monitor Busy' + -- MR2(2). + if MR2(2) = '1' and BSY_LOCK = false then + ICR(5 downto 0) <= "000000"; + BSY_LOCK := true; + elsif MR2(2) = '0' then + BSY_LOCK := false; + end if; + -- + if DMA_DIS = '1' then + MR2(1) <= '0'; + end if; + end if; + end process REGISTERS; + + IDR_REGISTER: process(RESETn, CLK) + begin + if RESETn = '0' then + IDR <= x"00"; + elsif CLK = '1' and CLK' event then + if RSTn = '0' or ICR(7) = '1' then + IDR <= x"00"; -- SCSI reset. + elsif IDR_WR = '1' then + IDR <= CSD; + end if; + end if; + end process IDR_REGISTER; + + PARITY: process(RESETn, CLK) + -- This is the parity generating logic with it's related + -- error generation. + variable PAR_VAR : bit; + variable LOCK : boolean; + begin + if RESETn = '0' then + SPER <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + -- Parity checked during 'Read from CSD' + -- (registered I/O and selection/reselection): + if ADR = "000" and CSn = '0' and RDn = '0' and LOCK = false then + for i in 1 to 7 loop + PAR_VAR := CSD(i) xor CSD(i-1); + end loop; + SPER <= not PAR_VAR; + LOCK := true; + end if; + -- + -- Parity checking during DMA operation: + if DMA_ACTIVE = '1' and CHK_PAR = '1' then + for i in 1 to 7 loop + PAR_VAR := IDR(i) xor IDR(i-1); + end loop; + SPER <= not PAR_VAR; + LOCK := true; + end if; + -- + -- Reset parity flag: + if MR2(5) <= '0' then -- MR2(5) = PCHK (disabled). + SPER <= '0'; + elsif ADR = "111" and CSn = '0' and RDn = '0' then -- Reset parity/interrupts. + SPER <= '0'; + LOCK := false; + end if; + end if; + end process PARITY; + + DATA_EN <= '1' when ADR < "101" and CSn = '0' and WRn = '0' else '0'; + + SDS <= '1' when ADR = "101" and CSn = '0' and WRn = '0' else '0'; + SDT <= '1' when ADR = "110" and CSn = '0' and WRn = '0' else '0'; + SDI <= '1' when ADR = "111" and CSn = '0' and WRn = '0' else '0'; + + ICR_OUT <= ICR; + TCR_OUT <= TCR; + SER_OUT <= SER; + ODR_OUT <= ODR; + + ARB_EN <= MR2(0); + DMA_EN <= MR2(1); + BSY_DISn <= MR2(2); + EOP_EN <= MR2(3); + PINT_EN <= MR2(4); + TARG <= MR2(6); + BLK <= MR2(7); + + RST <= ICR(7); + + -- Readback, unused bit positions are read back zero. + DATA_OUT <= CSD when ADR = "000" and CSn = '0' and RDn = '0' else -- Current SCSI data. + ICR(7) & AIP & LA & ICR(4 downto 0) when ADR = "001" and CSn = '0' and RDn = '0' else + MR2 when ADR = "010" and CSn = '0' and RDn = '0' else + x"0" & TCR when ADR = "011" and CSn = '0' and RDn = '0' else + CSB when ADR = "100" and CSn = '0' and RDn = '0' else -- Current SCSI bus status. + BSR when ADR = "101" and CSn = '0' and RDn = '0' else -- Bus and status. + IDR when ADR = "110" and CSn = '0' and RDn = '0' else x"00"; -- Input data register. + + RPI <= '1' when ADR = "111" and CSn = '0' and RDn = '0' else '0'; -- Reset parity/interrupts. +end BEHAVIOUR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd new file mode 100644 index 0000000..abc0400 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd @@ -0,0 +1,300 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- Some remarks to the required input clock: ---- +---- This core is provided for a 16MHz input clock. To use other ---- +---- frequencies, it is necessary to modify the following proces- ---- +---- ses in the control file section: ---- +---- P_BUSFREE, DELAY_800, INTERRUPTS. ---- +---- ---- +---- This file is the top level file without tree state buses for ---- +---- use in 'systems on chip' designs. ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library work; +use work.wf5380_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_TOP_SOC is + port ( + -- System controls: + CLK : in bit; -- Use a 16MHz Clock. + RESETn : in bit; + + -- Address and data: + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Bus and DMA controls: + CSn : in bit; + RDn : in bit; + WRn : in bit; + EOPn : in bit; + DACKn : in bit; + DRQ : out bit; + INT : out bit; + READY : out bit; + + -- SCSI bus: + DB_INn : in bit_vector(7 downto 0); + DB_OUTn : out bit_vector(7 downto 0); + DB_EN : out bit; + DBP_INn : in bit; + DBP_OUTn : out bit; + DBP_EN : out bit; + RST_INn : in bit; + RST_OUTn : out bit; + RST_EN : out bit; + BSY_INn : in bit; + BSY_OUTn : out bit; + BSY_EN : out bit; + SEL_INn : in bit; + SEL_OUTn : out bit; + SEL_EN : out bit; + ACK_INn : in bit; + ACK_OUTn : out bit; + ACK_EN : out bit; + ATN_INn : in bit; + ATN_OUTn : out bit; + ATN_EN : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + REQ_EN : out bit; + IOn_IN : in bit; + IOn_OUT : out bit; + IO_EN : out bit; + CDn_IN : in bit; + CDn_OUT : out bit; + CD_EN : out bit; + MSG_INn : in bit; + MSG_OUTn : out bit; + MSG_EN : out bit + ); +end entity WF5380_TOP_SOC; + +architecture STRUCTURE of WF5380_TOP_SOC is +signal ACK_OUT_CTRLn : bit; +signal AIP : bit; +signal ARB : bit; +signal ARB_EN : bit; +signal BLK : bit; +signal BSR : bit_vector(7 downto 0); +signal BSY_DISn : bit; +signal BSY_ERR : bit; +signal BSY_OUT_CTRLn : bit; +signal CHK_PAR : bit; +signal CSD : bit_vector(7 downto 0); +signal CSB : bit_vector(7 downto 0); +signal DATA_EN_CTRL : bit; +signal DB_EN_I : bit; +signal DMA_ACTIVE : bit; +signal DMA_EN : bit; +signal DMA_DIS : bit; +signal DMA_SND : bit; +signal DRQ_I : bit; +signal EDMA : bit; +signal EOP_EN : bit; +signal ICR : bit_vector(7 downto 0); +signal IDR_WR : bit; +signal INT_I : bit; +signal LA : bit; +signal ODR : bit_vector(7 downto 0); +signal ODR_WR : bit; +signal PCHK : bit; +signal PHSM : bit; +signal PINT_EN : bit; +signal REQ_OUT_CTRLn : bit; +signal RPI : bit; +signal RST : bit; +signal SDI : bit; +signal SDS : bit; +signal SDT : bit; +signal SER : bit_vector(7 downto 0); +signal SER_ID : bit; +signal SPER : bit; +signal TARG : bit; +signal TCR : bit_vector(3 downto 0); +begin + EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else + '1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0'; + + PHSM <= '1' when DMA_ACTIVE = '0' else -- Always true, if there is no DMA. + '1' when DMA_ACTIVE = '1' and REQ_INn = '0' and CDn_In = TCR(1) and IOn_IN = TCR(0) and MSG_INn = TCR(2) else '0'; -- Phasematch. + + DMA_DIS <= '1' when DMA_ACTIVE = '1' and BSY_INn = '1' else '0'; + + SER_ID <= '1' when SER /= x"00" and SER = not CSD else '0'; + + DRQ <= DRQ_I; + INT <= INT_I; + + -- Pay attention: the SCSI bus is driven with inverted signals. + ACK_OUTn <= ACK_OUT_CTRLn when DMA_ACTIVE = '1' else not ICR(4); -- Valid in initiator mode. + REQ_OUTn <= REQ_OUT_CTRLn when DMA_ACTIVE = '1' else not TCR(3); -- Valid in Target mode. + BSY_OUTn <= '0' when BSY_OUT_CTRLn = '0' and TARG = '0' else -- Valid in initiator mode. + '0' when ICR(3) = '1' else '1'; + ATN_OUTn <= not ICR(1); -- Valid in initiator mode. + SEL_OUTn <= not ICR(2); -- Valid in initiator mode. + IOn_OUT <= not TCR(0); -- Valid in Target mode. + CDn_OUT <= not TCR(1); -- Valid in Target mode. + MSG_OUTn <= not TCR(2); -- Valid in Target mode. + RST_OUTn <= not RST; + + DB_OUTn <= not ODR; + DBP_OUTn <= not SPER; + + CSD <= not DB_INn; + CSB <= not RST_INn & not BSY_INn & not REQ_INn & not MSG_INn & not CDn_IN & not IOn_IN & not SEL_INn & not DBP_INn; + BSR <= EDMA & DRQ_I & SPER & INT_I & PHSM & BSY_ERR & not ATN_INn & not ACK_INn; + + -- Hi impedance control: + ATN_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + SEL_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + BSY_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + ACK_EN <= '1' when TARG = '0' else '0'; -- Initiator mode. + IO_EN <= '1' when TARG = '1' else '0'; -- Target mode. + CD_EN <= '1' when TARG = '1' else '0'; -- Target mode. + MSG_EN <= '1' when TARG = '1' else '0'; -- Target mode. + REQ_EN <= '1' when TARG = '1' else '0'; -- Target mode. + RST_EN <= '1' when RST = '1' else '0'; -- Open drain control. + + -- Data enables: + DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arbitration. + '1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode. + '1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else + '1' when ICR(6) = '1' else '0'; -- Test mode enable. + + DB_EN <= DB_EN_I; + DBP_EN <= DB_EN_I; + + I_REGISTERS: WF5380_REGISTERS + port map( + CLK => CLK, + RESETn => RESETn, + ADR => ADR, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + CSn => CSn, + RDn => RDn, + WRn => WRn, + RSTn => RST_INn, + RST => RST, + ARB_EN => ARB_EN, + DMA_ACTIVE => DMA_ACTIVE, + DMA_EN => DMA_EN, + BSY_DISn => BSY_DISn, + EOP_EN => EOP_EN, + PINT_EN => PINT_EN, + SPER => SPER, + TARG => TARG, + BLK => BLK, + DMA_DIS => DMA_DIS, + IDR_WR => IDR_WR, + ODR_WR => ODR_WR, + CHK_PAR => CHK_PAR, + AIP => AIP, + ARB => ARB, + LA => LA, + CSD => CSD, + CSB => CSB, + BSR => BSR, + ODR_OUT => ODR, + ICR_OUT => ICR, + TCR_OUT => TCR, + SER_OUT => SER, + SDS => SDS, + SDT => SDT, + SDI => SDI, + RPI => RPI + ); + + I_CONTROL: WF5380_CONTROL + port map( + CLK => CLK, + RESETn => RESETn, + BSY_INn => BSY_INn, + BSY_OUTn => BSY_OUT_CTRLn, + DATA_EN => DATA_EN_CTRL, + SEL_INn => SEL_INn, + ARB_EN => ARB_EN, + BSY_DISn => BSY_DISn, + RSTn => RST_INn, + ARB => ARB, + AIP => AIP, + LA => LA, + ACK_INn => ACK_INn, + ACK_OUTn => ACK_OUT_CTRLn, + REQ_INn => REQ_INn, + REQ_OUTn => REQ_OUT_CTRLn, + DACKn => DACKn, + READY => READY, + DRQ => DRQ_I, + TARG => TARG, + BLK => BLK, + PINT_EN => PINT_EN, + SPER => SPER, + SER_ID => SER_ID, + RPI => RPI, + DMA_EN => DMA_EN, + SDS => SDS, + SDT => SDT, + SDI => SDI, + EOP_EN => EOP_EN, + EOPn => EOPn, + PHSM => PHSM, + INT => INT_I, + IDR_WR => IDR_WR, + ODR_WR => ODR_WR, + CHK_PAR => CHK_PAR, + BSY_ERR => BSY_ERR, + DMA_SND => DMA_SND, + DMA_ACTIVE => DMA_ACTIVE + ); +end STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd new file mode 100644 index 0000000..bfb31fb --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd @@ -0,0 +1,275 @@ +---------------------------------------------------------------------- +---- ---- +---- WF5380 IP Core ---- +---- ---- +---- Description: ---- +---- This model provides an asynchronous SCSI interface compa- ---- +---- tible to the DP5380 from National Semiconductor and others. ---- +---- ---- +---- This file is the top level file with tree state buses. ---- +---- ---- +---- ---- +---- ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2009 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K9A 2009/06/20 WF +-- Initial Release. +-- + +library work; +use work.wf5380_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF5380_TOP is + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; + + -- Address and data: + ADR : in std_logic_vector(2 downto 0); + DATA : inout std_logic_vector(7 downto 0); + + -- Bus and DMA controls: + CSn : in bit; + RDn : in bit; + WRn : in bit; + EOPn : in bit; + DACKn : in bit; + DRQ : out bit; + INT : out bit; + READY : out bit; + + -- SCSI bus: + DBn : inout std_logic_vector(7 downto 0); + DBPn : inout std_logic; + RSTn : inout std_logic; + BSYn : inout std_logic; + SELn : inout std_logic; + ACKn : inout std_logic; + ATNn : inout std_logic; + REQn : inout std_logic; + IOn : inout std_logic; + CDn : inout std_logic; + MSGn : inout std_logic + ); +end entity WF5380_TOP; + +architecture STRUCTURE of WF5380_TOP is +component WF5380_TOP_SOC + port ( + -- System controls: + CLK : in bit; + RESETn : in bit; + ADR : in bit_vector(2 downto 0); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + CSn : in bit; + RDn : in bit; + WRn : in bit; + EOPn : in bit; + DACKn : in bit; + DRQ : out bit; + INT : out bit; + READY : out bit; + DB_INn : in bit_vector(7 downto 0); + DB_OUTn : out bit_vector(7 downto 0); + DB_EN : out bit; + DBP_INn : in bit; + DBP_OUTn : out bit; + DBP_EN : out bit; + RST_INn : in bit; + RST_OUTn : out bit; + RST_EN : out bit; + BSY_INn : in bit; + BSY_OUTn : out bit; + BSY_EN : out bit; + SEL_INn : in bit; + SEL_OUTn : out bit; + SEL_EN : out bit; + ACK_INn : in bit; + ACK_OUTn : out bit; + ACK_EN : out bit; + ATN_INn : in bit; + ATN_OUTn : out bit; + ATN_EN : out bit; + REQ_INn : in bit; + REQ_OUTn : out bit; + REQ_EN : out bit; + IOn_IN : in bit; + IOn_OUT : out bit; + IO_EN : out bit; + CDn_IN : in bit; + CDn_OUT : out bit; + CD_EN : out bit; + MSG_INn : in bit; + MSG_OUTn : out bit; + MSG_EN : out bit + ); +end component; +-- +signal ADR_IN : bit_vector(2 downto 0); +signal DATA_IN : bit_vector(7 downto 0); +signal DATA_OUT : bit_vector(7 downto 0); +signal DATA_EN : bit; +signal DB_INn : bit_vector(7 downto 0); +signal DB_OUTn : bit_vector(7 downto 0); +signal DB_EN : bit; +signal DBP_INn : bit; +signal DBP_OUTn : bit; +signal DBP_EN : bit; +signal RST_INn : bit; +signal RST_OUTn : bit; +signal RST_EN : bit; +signal BSY_INn : bit; +signal BSY_OUTn : bit; +signal BSY_EN : bit; +signal SEL_INn : bit; +signal SEL_OUTn : bit; +signal SEL_EN : bit; +signal ACK_INn : bit; +signal ACK_OUTn : bit; +signal ACK_EN : bit; +signal ATN_INn : bit; +signal ATN_OUTn : bit; +signal ATN_EN : bit; +signal REQ_INn : bit; +signal REQ_OUTn : bit; +signal REQ_EN : bit; +signal IOn_IN : bit; +signal IOn_OUT : bit; +signal IO_EN : bit; +signal CDn_IN : bit; +signal CDn_OUT : bit; +signal CD_EN : bit; +signal MSG_INn : bit; +signal MSG_OUTn : bit; +signal MSG_EN : bit; +begin + ADR_IN <= To_BitVector(ADR); + + DATA_IN <= To_BitVector(DATA); + DATA <= To_StdLogicVector(DATA_OUT) when DATA_EN = '1' else (others => 'Z'); + + DB_INn <= To_BitVector(DBn); + DBn <= To_StdLogicVector(DB_OUTn) when DB_EN = '1' else (others => 'Z'); + + DBP_INn <= To_Bit(DBPn); + + RST_INn <= To_Bit(RSTn); + BSY_INn <= To_Bit(BSYn); + SEL_INn <= To_Bit(SELn); + ACK_INn <= To_Bit(ACKn); + ATN_INn <= To_Bit(ATNn); + REQ_INn <= To_Bit(REQn); + IOn_IN <= To_Bit(IOn); + CDn_IN <= To_Bit(CDn); + MSG_INn <= To_Bit(MSGn); + + DBPn <= '1' when DBP_OUTn = '1' and DBP_EN = '1' else + '0' when DBP_OUTn = '0' and DBP_EN = '1' else 'Z'; + RSTn <= '1' when RST_OUTn = '1' and RST_EN = '1'else + '0' when RST_OUTn = '0' and RST_EN = '1' else 'Z'; + BSYn <= '1' when BSY_OUTn = '1' and BSY_EN = '1' else + '0' when BSY_OUTn = '0' and BSY_EN = '1' else 'Z'; + SELn <= '1' when SEL_OUTn = '1' and SEL_EN = '1' else + '0' when SEL_OUTn = '0' and SEL_EN = '1' else 'Z'; + ACKn <= '1' when ACK_OUTn = '1' and ACK_EN = '1' else + '0' when ACK_OUTn = '0' and ACK_EN = '1' else 'Z'; + ATNn <= '1' when ATN_OUTn = '1' and ATN_EN = '1' else + '0' when ATN_OUTn = '0' and ATN_EN = '1' else 'Z'; + REQn <= '1' when REQ_OUTn = '1' and REQ_EN = '1' else + '0' when REQ_OUTn = '0' and REQ_EN = '1' else 'Z'; + IOn <= '1' when IOn_OUT = '1' and IO_EN = '1' else + '0' when IOn_OUT = '0' and IO_EN = '1' else 'Z'; + CDn <= '1' when CDn_OUT = '1' and CD_EN = '1' else + '0' when CDn_OUT = '0' and CD_EN = '1' else 'Z'; + MSGn <= '1' when MSG_OUTn = '1' and MSG_EN = '1' else + '0' when MSG_OUTn = '0' and MSG_EN = '1' else 'Z'; + + I_5380: WF5380_TOP_SOC + port map( + CLK => CLK, + RESETn => RESETn, + ADR => ADR_IN, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + CSn => CSn, + RDn => RDn, + WRn => WRn, + EOPn => EOPn, + DACKn => DACKn, + DRQ => DRQ, + INT => INT, + READY => READY, + DB_INn => DB_INn, + DB_OUTn => DB_OUTn, + DB_EN => DB_EN, + DBP_INn => DBP_INn, + DBP_OUTn => DBP_OUTn, + DBP_EN => DBP_EN, + RST_INn => RST_INn, + RST_OUTn => RST_OUTn, + RST_EN => RST_EN, + BSY_INn => BSY_INn, + BSY_OUTn => BSY_OUTn, + BSY_EN => BSY_EN, + SEL_INn => SEL_INn, + SEL_OUTn => SEL_OUTn, + SEL_EN => SEL_EN, + ACK_INn => ACK_INn, + ACK_OUTn => ACK_OUTn, + ACK_EN => ACK_EN, + ATN_INn => ATN_INn, + ATN_OUTn => ATN_OUTn, + ATN_EN => ATN_EN, + REQ_INn => REQ_INn, + REQ_OUTn => REQ_OUTn, + REQ_EN => REQ_EN, + IOn_IN => IOn_IN, + IOn_OUT => IOn_OUT, + IO_EN => IO_EN, + CDn_IN => CDn_IN, + CDn_OUT => CDn_OUT, + CD_EN => CD_EN, + MSG_INn => MSG_INn, + MSG_OUTn => MSG_OUTn, + MSG_EN => MSG_EN + ); +end STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd new file mode 100644 index 0000000..10a86f9 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd @@ -0,0 +1,253 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- Address mark detector file. This part detects the address ---- +---- mark in the incoming data stream in FM and also in MFM mode ---- +---- and provides therewith synchronisation information for the ---- +---- control state machine and for the data separator in the ---- +---- transceiver unit. ---- +---- ---- +------------------------------- Some theory ------------------------------------- +---- Frequency modulation FM: ---- +---- The frequency modulation works as follows: ---- +---- 1. every first pulse of the clock and data line is a clock. ---- +---- 2. every second pulse is a data. ---- +---- 3. a logic 1 is represented by two consecutive pulses (clock and data). ---- +---- 4. a logic 0 is represented by one clock pulse and no data pulse. ---- +---- 5. Hence there are a maximum of two pulses per data bit. ---- +---- 6. one clock and one data pulse come together in one bit cell. ---- +---- 7. the duration of a bit cell in FM is 4 microseconds. ---- +---- 8. an ID address mark is represented as data FE with clock C7. ---- +---- 9. a DATA address mark is represented as data FB with clock C7. ---- +---- Examples: ---- +---- Binary data 1 1 0 0 1 0 1 1 is represented in FM as follows: ---- +---- 1111101011101111 ---- +---- the FE data 1 1 1 1 1 1 1 0 is represented as follows: ---- +---- 1111111111111110 ---- +---- with C7 clock mask 1 1 0 0 0 1 1 1 which masks the clock pulses there ---- +---- results: 1111010101111110 this is the ID address mark. ---- +---- the FB data 1 1 1 1 1 0 1 1 is represented as follows: ---- +---- 1111111111101111 ---- +---- with C7 clock mask 1 1 0 0 0 1 1 1 which masks the clock pulses there ---- +---- results: 1111010101101111 this is the DATA address mark. ---- +---- the F8 data 1 1 1 1 1 0 0 0 is represented as follows: ---- +---- 1111111111101010 ---- +---- with C7 clock mask 1 1 0 0 0 1 1 1 which masks the clock pulses there ---- +---- results: 1111010101101010 this is the deleted DATA mark. ---- +---- ---- +---- ---- +---- Modified frequency modulation MFM: ---- +---- The modified frequency modulation works as follows: ---- +---- 1. every first pulse of the clock and data line is a clock. ---- +---- 2. every second pulse is a data. ---- +---- 3. a logic 1 is represented by no clock but a data pulse. ---- +---- 4. a logic 0 is represented by a clock pulse and no data pulse if ---- +---- following a 0. ---- +---- 5. a logic 0 is represented by no pulse if following a 1. ---- +---- 6. Hence there are a maximum of one pulse per data bit. ---- +---- 7. one clock and one data pulse form together one bit cell. ---- +---- 8. the duration of a bit cell in MFM is 2 microseconds. ---- +---- 9. an address mark sync is represented as data A1 with missing clock ---- +---- pulse between bit 4 and 5. ---- +---- Examples: ---- +---- Binary data FE 1 1 1 1 1 1 1 0 is represented in MFM as follows: ---- +---- 0101010101010100 this is the ID address mark. ---- +---- Binary data FB 1 1 1 1 1 0 1 1 is represented in MFM as follows: ---- +---- 0101010101000101 this is the DATA address mark. ---- +---- Binary data F8 1 1 1 1 1 0 0 0 is represented in MFM as follows: ---- +---- 0101010101001010 this is the deleted DATA address mark. ---- +---- the A1 data 1 0 1 0 0 0 0 1 is represented as follows: ---- +---- 0100010010101001 ---- +---- with the missing clock pulse between bits 4 and 5 there results: ---- +---- results: 0100010010001001 this is the address mark sync. ---- +---- ---- +---- Both MFM and FM are during read and write shifted with most significant ---- +---- bit (MSB) first. During the FM address marks are written without a ---- +---- SYNC pulse the MFM coded data requires a synchronisation (A1 with ---- +---- missing clock pulse because at the beginning of the data stream it is ---- +---- not defined wether a clock pulse or a data pulse appears first. In FM ---- +---- coding the first pulse is in any case a clock pulse. ---- +--------------------------------------------------------------------------------- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_AM_DETECTOR is + port( + -- System control + CLK : in bit; + RESETn : in bit; + + -- Controls: + DDEn : in bit; + + -- Serial data and clock: + DATA : in bit; + DATA_STRB : in bit; + + -- Address mark detector: + ID_AM : out bit; -- ID address mark strobe. + DATA_AM : out bit; -- Data address mark strobe. + DDATA_AM : out bit -- Deleted data address mark strobe. + ); +end WF1772IP_AM_DETECTOR; + +architecture BEHAVIOR of WF1772IP_AM_DETECTOR is +signal SHIFT : bit_vector(15 downto 0); +signal SYNC : boolean; +signal ID_AM_I : bit; +signal DATA_AM_I : bit; +signal DDATA_AM_I : bit; +begin + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT <= (others => '0'); + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + -- MSB first leads to a shift left operation. + SHIFT <= SHIFT(14 downto 0) & DATA; + elsif DDEn = '0' and SHIFT = "0100010010001001" then -- This is the synchronisation in MFM. + SHIFT <= (others => '0'); + end if; + end if; + end process SHIFTREG; + + MFM_SYNCLOCK: process(RESETn, CLK) + -- The SYNC pulse is generated in MFM mode only when the sync character + -- appears in the shift register (A1 sync mark, see file header). + -- After the sync character is detected, the sync time counter is loaded + -- with a value of 17. During counting the following 17 read clock pulses + -- down, the SYNC is true. After exactly 16 pulses the address mark is + -- detected if the pattern in the shift register fits one of the address + -- marks. The address mark pulses are valid for one read clock cycle until + -- SYNC goes low again. This mechanism is used to detect the correct address + -- marks in the MFM data stream during the type III read track command. + -- This is an improvement over the original WD1772 chip. + variable TMP : std_logic_vector(4 downto 0); + begin + if RESETn = '0' then + TMP := "00000"; + elsif CLK = '1' and CLK' event then + if SHIFT = "0100010010001001" and DDEn = '0' then + TMP := "10001"; -- Load sync time counter. + elsif DATA_STRB = '1' and TMP > "00000" then + TMP := TMP - '1'; + end if; + end if; + case TMP is + when "00000" => SYNC <= false; + when others => SYNC <= true; + end case; + end process MFM_SYNCLOCK; + + -- The addressmark is nominally valid for one data pulse cycle (1us, 2us, 4us). + -- The pulse is shorter due to the fact that the detected address marks change the + -- state of the control state machine and so clear the address mark shift register... + ID_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101111110" else + '1' when DDEn = '0' and SHIFT = "0101010101010100" and SYNC = true else '0'; + DATA_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101101111" else + -- Normal data address mark... + '1' when DDEn = '0' and SHIFT = "0101010101000101" and SYNC = true else '0'; + DDATA_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101101010" else + -- ... and deleted address mark in MFM mode: + '1' when DDEn = '0' and SHIFT = "0101010101001010" and SYNC = true else '0'; + + ADRMARK_STROBES: process(RESETn, CLK) + -- ... nevertheless The controller and the transceiver require ID address mark strobes + -- and DATA address mark strobes. Therefore this process provides these strobe + -- signals independant of any 'feedbacks' like pulse shortening by the controller + -- state machine itself. + variable ID_AM_LOCK, DATA_AM_LOCK, DDATA_AM_LOCK : boolean; + begin + if RESETn = '0' then + ID_AM_LOCK := false; + DATA_AM_LOCK := false; + ID_AM <= '0'; + DATA_AM <= '0'; + elsif CLK = '1' and CLK' event then + -- ID address mark: + if ID_AM_I = '1' and ID_AM_LOCK = false then + ID_AM <= '1'; + ID_AM_LOCK := true; + elsif ID_AM_I = '0' then + ID_AM <= '0'; + ID_AM_LOCK := false; + else + ID_AM <= '0'; + end if; + -- Data address mark: + if DATA_AM_I = '1' and DATA_AM_LOCK = false then + DATA_AM <= '1'; + DATA_AM_LOCK := true; + elsif DATA_AM_I = '0' then + DATA_AM <= '0'; + DATA_AM_LOCK := false; + else + DATA_AM <= '0'; + end if; + -- Deleted data address mark: + if DDATA_AM_I = '1' and DDATA_AM_LOCK = false then + DDATA_AM <= '1'; + DDATA_AM_LOCK := true; + elsif DDATA_AM_I = '0' then + DDATA_AM <= '0'; + DDATA_AM_LOCK := false; + else + DDATA_AM <= '0'; + end if; + end if; + end process ADRMARK_STROBES; +end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd new file mode 100644 index 0000000..ce4c346 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd @@ -0,0 +1,1463 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This is file the control unit providing all signals for the ---- +---- data processing units like registers, addressmark detector, ---- +---- data separator, CRC redundancy checker or transceiver. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Fixed the polarity of the precompensation flag. +-- The flag is no active '0'. Thanks to Jorma +-- Oksanen for the information. +-- Revision 2K8A 2008/02/26 WF +-- Fixed a bug in the 6ms delay. Thanks to Lyndon Amsdon. +-- Revision 2K8B 2008/12/24 WF +-- Bugfixes to avoid hanging state machine. +-- Changed DELAY_30MS to DELAY_15MS, which is the correct value. Thanks to L. Amsdon for the information. +-- Removed CRC_BUSY. +-- Fixed a bug in the Delay for the state T2_VERIFY_AM. +-- Revision 2K9A 2009/06/20 WF +-- Fix to provide correct LOST_DATA_TR00 flag during seek command. + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_CONTROL is + port( + -- System control: + CLK : in bit; + RESETn : in bit; + + -- Chip control signals: + A1, A0 : in bit; + RWn : in bit; + CSn : in bit; + DDEn : in bit; + + -- Registers: + DR : in bit_vector(7 downto 0); -- Data register. + CMD : in std_logic_vector(7 downto 0); -- Command register. + DSR : in std_logic_vector(7 downto 0); -- Shift register. + TR : in std_logic_vector(7 downto 0); -- Track register. + SR : in std_logic_vector(7 downto 0); -- Sector register. + + -- Status flags: + MO : buffer bit; -- Motor on status flag. + WR_PR : out bit; -- Write protect status flag. + SPINUP_RECTYPE : out bit; -- Spin up / record type status flag. + SEEK_RNF : out bit; -- Seek error / record not found status flag. + CRC_ERRFLAG : out bit; -- CRC status flag. + LOST_DATA_TR00 : out bit; -- Status flag indicates lost data or track 00 position. + DRQ : out bit; -- Data request. + DRQ_IPn : out bit; -- Data request status flag. + BUSY : buffer bit; -- BUSY status flag. + + -- Address mark detector controls: + AM_2_DISK : out bit; -- Enables / disables the address mark detector. + ID_AM : in bit; -- Address mark of the ID field + DATA_AM : in bit; -- Address mark of the data field + DDATA_AM : in bit; -- Address mark of a deleted data field + + -- CRC unit controls: + CRC_ERR : in bit; -- CRC decoder's error. + CRC_PRES : out bit; -- Preset CRC during write operations. + + -- Track register controls: + TR_PRES : out bit; -- Set x"FF". + TR_CLR : out bit; -- Clear. + TR_INC : out bit; -- Increment. + TR_DEC : out bit; -- Decrement. + + -- Sector register control: + SR_LOAD : out bit; -- Load. + SR_INC : out bit; -- Increment. + -- The TRACK_NR is required during the type III command + -- 'Read Address'. TRACK_NR is the content of the TRACKMEM. + TRACK_NR : out std_logic_vector(7 downto 0); + + -- DATA register control: + DR_CLR : out bit; -- Clear. + DR_LOAD : out bit; -- LOAD. + + -- Shift register control: + SHFT_LOAD_ND : out bit; -- Load normal data. + SHFT_LOAD_SD : out bit; -- Load special data. + + -- Transceiver controls: + CRC_2_DISK : out bit; -- Cause the Transceiver to write out CRC data. + DSR_2_DISK : out bit; -- Cause the Transceiver to write normal data. + FF_2_DISK : out bit; -- Cause the Transceiver to write x"FF" bytes. + PRECOMP_EN : out bit; -- Enables the write precompensation. + + -- Miscellaneous Controls: + DATA_STRB : in bit; -- Data strobe (read and write operation) + WPRTn : in bit; -- Write protect flag + IPn : in bit; -- Index pulse flag + TRACK00n : in bit; -- Track zero flag + DISK_RWn : out bit; -- This signal reflects the data direction. + DIRC : out bit; -- Step direction control. + STEP : out bit; -- Step pulse. + WG : out bit; -- Write gate control. + INTRQ : out bit -- Interrupt request flag. + ); +end WF1772IP_CONTROL; + +architecture BEHAVIOR of WF1772IP_CONTROL is +-- The control state machine for the three command types I, II and III +-- (10 commands) has 73 states: +type CMD_STATES is( IDLE, INIT, SPINUP, DELAY_15MS, DECODE, T1_SEEK_RESTORE, T1_STEPPING, + T1_LOAD_SHFT, T1_COMP_TR_DSR, T1_CHECK_DIR, T1_HEAD_CTRL, T1_STEP, T1_TRAP, T1_STEP_DELAY, + T1_SPINDOWN, T1_SCAN_TRACK, T1_SCAN_CRC, T1_VERIFY_DELAY, T1_VERIFY_CRC, T2_RD_WR_SECT, + T2_INIT, T2_SCAN_TRACK, T2_SCAN_SECT, T2_SCAN_LEN, T2_VERIFY_CRC_1, T2_VERIFY_AM, T2_FIRSTBYTE, + T2_LOAD_DATA, T2_NEXTBYTE, T2_VERIFY_DRQ_1, T2_RDSTAT, T2_VERIFY_CRC_2, + T2_MULTISECT, T2_DELAY_B2, T2_SET_DRQ, T2_DELAY_B8, T2_VERIFY_DRQ_2, + T2_DELAY_B1, T2_CHECK_MODE, T2_DELAY_B11, T2_WR_LEADIN, T2_WR_AM, + T2_LOAD_SHFT, T2_WR_BYTE, T2_VERIFY_DRQ_3, T2_DATALOST, T2_WRSTAT, T2_WR_CRC, + T2_WR_FF, T3_WR, T3_DELAY_B3, T3_VERIFY_DRQ, T3_CHECK_INDEX_1, T3_LOAD_SHFT, + T3_WR_DATA, T3_CHECK_INDEX_2, T3_DATALOST, T3_RD_TRACK, T3_SHIFT, + T3_CHECK_INDEX_3, T3_DETECT_AM, T3_CHECK_BYTE, T3_CHECK_DR, T3_LOAD_DATA_1, + T3_SET_DRQ_1, T3_RD_ADR, T3_VERIFY_AM, T3_SHIFT_ADR, T3_LOAD_DATA_2, + T3_SET_DRQ_2, T3_CHECK_RD, T3_LOAD_SR, T3_VERIFY_CRC); +signal CMD_STATE : CMD_STATES; +signal NEXT_CMD_STATE : CMD_STATES; +signal DATA_WR : boolean; +signal DATA_RD : boolean; +signal CMD_WR : boolean; +signal STAT_RD : boolean; +signal DELAY : boolean; +signal DRQ_I : bit; +signal INDEX_CNT : boolean; +signal DIR : bit; +signal INDEX_MARK : bit; +signal STEP_TRAP : boolean; +signal TYPE_IV_BREAK : boolean; +signal BYTE_RDY : boolean; +signal SECT_LEN : std_logic_vector(10 downto 0); +signal TRACKMEM : std_logic_vector(7 downto 0); +signal T3_TRADR : boolean; +signal T3_DATATYPE : bit_vector(7 downto 0); +begin + -- The Forced interrupt stops any command at the end of an internal micro instruction. + -- Forced interrupt waits until ALU operations in progress are complete (CRC calculations, + -- compares etc.). the TYPE_IV_BREAK controls this behavior. + TYPE_IV_BREAK <= true when CMD(7 downto 4) = x"D" and DELAY = true else false; + + CMD_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + CMD_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if TYPE_IV_BREAK = true then + CMD_STATE <= IDLE; -- Forced interrupt break. + else + CMD_STATE <= NEXT_CMD_STATE; -- Normal operation. + end if; + end if; + end process CMD_REG; + + CMD_DECODER: process(CMD_STATE, CMD, DSR, TR, SR, INDEX_CNT, IPn, INDEX_MARK, DELAY, DIR, MO, CMD_WR, DRQ_I, + DDEn, CRC_ERR, TRACK00n, STEP_TRAP, ID_AM, DATA_AM, DDATA_AM, WPRTn, SECT_LEN, BYTE_RDY, + T3_TRADR) + begin + case CMD_STATE is + -------------------------------------------------------------------- + ------------------ type1, -2, -3 command stuff --------------------- + -------------------------------------------------------------------- + when IDLE => + -- The write access to the command register indicates a new command. + -- Any command received (type1, -2 or -3 but not type4): + if CMD_WR = true and CMD /= x"FF" and CMD(7 downto 4) /= "1101" then + NEXT_CMD_STATE <= INIT; + else + NEXT_CMD_STATE <= IDLE; -- No CMD detected. + end if; + when INIT => + -- The process goes on when the CMD_WR flag is released. + if CMD_WR = false and CMD(3) = '0' and MO = '0' then + -- Do not enter the SPINUP sequence + -- when the motor is already on (MO = '1'). + NEXT_CMD_STATE <= SPINUP; + elsif CMD_WR = false then + -- Proceed with the DELAY_15MS when the motor was + -- already on or when the SPINUP sequence is + -- disabled (CMD(3) = '1'). + NEXT_CMD_STATE <= DELAY_15MS; + else + NEXT_CMD_STATE <= INIT; + end if; + when SPINUP => + if INDEX_CNT = true then -- proceed after 6 revolutions + NEXT_CMD_STATE <= DELAY_15MS; + else + NEXT_CMD_STATE <= SPINUP; + end if; + when DELAY_15MS => + if CMD(7) = '0' then -- No delay for type1 commands. + NEXT_CMD_STATE <= DECODE; + elsif CMD(7) = '1' and CMD(2) = '0' then -- Delay for type2 and -3 disabled. + NEXT_CMD_STATE <= DECODE; + elsif CMD(7) = '1' and CMD(2) = '1' and DELAY = true then -- Delay enabled by CMD(2). + NEXT_CMD_STATE <= DECODE; + else + NEXT_CMD_STATE <= DELAY_15MS; + end if; + when DECODE => + case CMD(7 downto 5) is + when "000" => -- 'restore', 'seek'. + NEXT_CMD_STATE <= T1_SEEK_RESTORE; + when "001" |"010" | "011" => -- 'step', 'step in', 'step out'. + NEXT_CMD_STATE <= T1_STEPPING; + when "100" | "101" => -- 'read sector', 'write sector' + NEXT_CMD_STATE <= T2_RD_WR_SECT; + when "110" => -- 'read address'. + -- "110" is also used by the 'force interrupt'. + -- There will result no wrong encoding because + -- the 'force intterrupt' is predecoded in IDLE. + NEXT_CMD_STATE <= T3_RD_ADR; + when "111" => -- 'read track', 'write track'. + case CMD(4) is + when '0' => NEXT_CMD_STATE <= T3_RD_TRACK; + when '1' => NEXT_CMD_STATE <= T3_WR; + when others => NEXT_CMD_STATE <= T3_WR; -- Dummy for U, X, Z, W, H, L, -. + end case; + when others => + -- The following NEXT_CMD_STATE is chosen to compile fine with + -- the Xilinx ISE not to produce a latch. + NEXT_CMD_STATE <= IDLE; -- Never true due to IDLE preselection. + end case; + -------------------------------------------------------------------- + ------------------ special type1 command stuff --------------------- + -------------------------------------------------------------------- + when T1_SEEK_RESTORE => + -- In this state, the data register and the track register are updated, if the + -- command is a RESTORE. The update is done further down with the track register + -- and the data register controls. + NEXT_CMD_STATE <= T1_LOAD_SHFT; + when T1_STEPPING => + if CMD(4) = '1' then -- '1' means update track register. + NEXT_CMD_STATE <= T1_CHECK_DIR; + else + NEXT_CMD_STATE <= T1_HEAD_CTRL; + end if; + when T1_LOAD_SHFT => + NEXT_CMD_STATE <= T1_COMP_TR_DSR; + when T1_COMP_TR_DSR => + if DSR = TR then + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + else + -- The direction control is done further down. + NEXT_CMD_STATE <= T1_CHECK_DIR; + end if; + when T1_CHECK_DIR => + -- Track register modifications are done in + -- statements further down. + -- The delay is to provide the timing of the WD1772 which is DIR to step = + -- 24us in MFM mode and 48us in FM mode. + if DELAY = true then + NEXT_CMD_STATE <= T1_HEAD_CTRL; + else + NEXT_CMD_STATE <= T1_CHECK_DIR; + end if; + when T1_HEAD_CTRL => + if TRACK00n = '0' and DIR = '0' then + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + else + NEXT_CMD_STATE <= T1_STEP; + end if; + when T1_STEP => + NEXT_CMD_STATE <= T1_TRAP; + when T1_TRAP => + if STEP_TRAP = true then + NEXT_CMD_STATE <= IDLE; -- Break due to seek error. + else + NEXT_CMD_STATE <= T1_STEP_DELAY; + end if; + when T1_STEP_DELAY => + -- The delay in here is according to the CMD(1 downto 0) as follows: + -- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms. + if DELAY = true then + case CMD(7 downto 5) is + when "001" | "010" | "011" => -- STEP - STEP IN - STEP OUT. + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + when others => -- Seek or restore command. + NEXT_CMD_STATE <= T1_LOAD_SHFT; + end case; + else + NEXT_CMD_STATE <= T1_STEP_DELAY; + end if; + when T1_VERIFY_DELAY => + if CMD(2) = '0' then -- No verify. + NEXT_CMD_STATE <= IDLE; + else + if DELAY = true then -- Wait, if verify is active. + NEXT_CMD_STATE <= T1_SPINDOWN; + else + NEXT_CMD_STATE <= T1_VERIFY_DELAY; + end if; + end if; + when T1_SPINDOWN => -- Detect ID address mark in here. + if INDEX_CNT = true then + NEXT_CMD_STATE <= IDLE; -- Break due to timeout. + elsif ID_AM = '1' then -- Addressmark found. + NEXT_CMD_STATE <= T1_SCAN_TRACK; + else + NEXT_CMD_STATE <= T1_SPINDOWN; + end if; + when T1_SCAN_TRACK => + if DELAY = true then + -- Track found if shift register (DSR) equals track register (TR). + if DSR = TR then + NEXT_CMD_STATE <= T1_SCAN_CRC; + else + NEXT_CMD_STATE <= T1_SPINDOWN; + end if; + else + NEXT_CMD_STATE <= T1_SCAN_TRACK; + end if; + when T1_SCAN_CRC => + -- Scan the rest of the data header for correct CRC generation (3 Bytes). + -- Sector number side select byte and data length byte. + if DELAY = true then + NEXT_CMD_STATE <= T1_VERIFY_CRC; + else + NEXT_CMD_STATE <= T1_SCAN_CRC; + end if; + when T1_VERIFY_CRC => + -- The CRC logic starts during T1_SPINDOWN (missing clock transitions). + if DELAY = true then + if CRC_ERR = '1' then + NEXT_CMD_STATE <= T1_SPINDOWN; -- CRC error. + else + NEXT_CMD_STATE <= IDLE; -- Operation finished. + end if; + else + NEXT_CMD_STATE <= T1_VERIFY_CRC; -- Wait until CRC logic is ready. + end if; + -------------------------------------------------------------------- + ------------------ special type2 command stuff --------------------- + -------------------------------------------------------------------- + when T2_RD_WR_SECT => + if CMD(7 downto 5) = "101" and WPRTn = '0' then + NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk. + else + NEXT_CMD_STATE <= T2_INIT; + end if; + when T2_INIT => + if INDEX_CNT = true then + NEXT_CMD_STATE <= IDLE; -- Break due to timeout. + elsif ID_AM = '0' then + NEXT_CMD_STATE <= T2_INIT; -- Wait for address mark. + else -- INDEX_CNT = false and ID_AM = '1' -> ID address mark detected + NEXT_CMD_STATE <= T2_SCAN_TRACK; + end if; + when T2_SCAN_TRACK => + -- Track found if shift register (DSR) equals track register (TR). + if DELAY = true then + if DSR = TR then + NEXT_CMD_STATE <= T2_SCAN_SECT; + else + NEXT_CMD_STATE <= T2_INIT; + end if; + else + NEXT_CMD_STATE <= T2_SCAN_TRACK; + end if; + when T2_SCAN_SECT => + -- Sector found if shift register (DSR) equals sector register (SR). + if DELAY = true then + if DSR = SR then + NEXT_CMD_STATE <= T2_SCAN_LEN; + else + NEXT_CMD_STATE <= T2_INIT; + end if; + else + NEXT_CMD_STATE <= T2_SCAN_SECT; + end if; + when T2_SCAN_LEN => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_CRC_1; + else + NEXT_CMD_STATE <= T2_SCAN_LEN; + end if; + when T2_VERIFY_CRC_1 => + -- The CRC logic starts after T2_INIT (missing clock transitions). + if DELAY = true then + if CRC_ERR = '1' then + NEXT_CMD_STATE <= T2_INIT; -- CRC error. + elsif CRC_ERR = '0' and CMD(7 downto 5) = "101" then + NEXT_CMD_STATE <= T2_DELAY_B2; -- Comand is a write. + else -- Command is a read. + NEXT_CMD_STATE <= T2_VERIFY_AM; + end if; + else + NEXT_CMD_STATE <= T2_VERIFY_CRC_1; -- Wait until CRC logic is ready. + end if; + when T2_VERIFY_AM => + if DATA_AM = '1' or DDATA_AM = '1' then -- Data address mark detected, go on. + NEXT_CMD_STATE <= T2_FIRSTBYTE; + elsif DELAY = false then -- Stay in this state. + NEXT_CMD_STATE <= T2_VERIFY_AM; + else + NEXT_CMD_STATE <= T2_INIT; -- No addressmark detected. + end if; + when T2_FIRSTBYTE => + if DELAY = true then + NEXT_CMD_STATE <= T2_LOAD_DATA; + else + NEXT_CMD_STATE <= T2_FIRSTBYTE; + end if; + when T2_LOAD_DATA => + NEXT_CMD_STATE <= T2_NEXTBYTE; + when T2_NEXTBYTE => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_DRQ_1; + else + NEXT_CMD_STATE <= T2_NEXTBYTE; + end if; + when T2_VERIFY_DRQ_1 => + NEXT_CMD_STATE <= T2_RDSTAT; + when T2_RDSTAT => + if SECT_LEN = "00000000000" then + NEXT_CMD_STATE <= T2_VERIFY_CRC_2; + else + NEXT_CMD_STATE <= T2_LOAD_DATA; + end if; + when T2_VERIFY_CRC_2 => + -- The CRC logic starts after T2_VERIFY_AM (missing clock transitions). + if DELAY = true then + if CRC_ERR = '1' then + NEXT_CMD_STATE <= IDLE; -- Break due to CRC error. + else + NEXT_CMD_STATE <= T2_MULTISECT; + end if; + else + NEXT_CMD_STATE <= T2_VERIFY_CRC_2; -- Wait until CRC logic is ready. + end if; + when T2_MULTISECT => + if CMD(4) = '1' then + NEXT_CMD_STATE <= T2_RD_WR_SECT; + else + NEXT_CMD_STATE <= IDLE; -- Operation finished. + end if; + when T2_DELAY_B2 => + if DELAY = true then + NEXT_CMD_STATE <= T2_SET_DRQ; + else + NEXT_CMD_STATE <= T2_DELAY_B2; + end if; + when T2_SET_DRQ => + NEXT_CMD_STATE <= T2_DELAY_B8; + when T2_DELAY_B8 => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_DRQ_2; + else + NEXT_CMD_STATE <= T2_DELAY_B8; + end if; + when T2_VERIFY_DRQ_2 => + if DRQ_I = '0' then + NEXT_CMD_STATE <= T2_DELAY_B1; + else + NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host). + end if; + when T2_DELAY_B1 => + if DELAY = true then + NEXT_CMD_STATE <= T2_CHECK_MODE; + else + NEXT_CMD_STATE <= T2_DELAY_B1; + end if; + when T2_CHECK_MODE => + if DDEn = '1' then -- FM mode + NEXT_CMD_STATE <= T2_WR_LEADIN; + else + NEXT_CMD_STATE <= T2_DELAY_B11; + end if; + when T2_DELAY_B11 => + if DELAY = true then + NEXT_CMD_STATE <= T2_WR_LEADIN; + else + NEXT_CMD_STATE <= T2_DELAY_B11; + end if; + when T2_WR_LEADIN => + if DELAY = true then + NEXT_CMD_STATE <= T2_WR_AM; + else + NEXT_CMD_STATE <= T2_WR_LEADIN; + end if; + when T2_WR_AM => -- Write data address mark. + if DELAY = true then + NEXT_CMD_STATE <= T2_LOAD_SHFT; + else + NEXT_CMD_STATE <= T2_WR_AM; + end if; + when T2_LOAD_SHFT => + NEXT_CMD_STATE <= T2_WR_BYTE; + when T2_WR_BYTE => + if DELAY = true then + NEXT_CMD_STATE <= T2_VERIFY_DRQ_3; + else + NEXT_CMD_STATE <= T2_WR_BYTE; + end if; + when T2_VERIFY_DRQ_3 => + if DRQ_I = '0' then + NEXT_CMD_STATE <= T2_WRSTAT; + else + NEXT_CMD_STATE <= T2_DATALOST; + end if; + when T2_DATALOST => + if DELAY = true then + NEXT_CMD_STATE <= T2_WRSTAT; + else + NEXT_CMD_STATE <= T2_DATALOST; + end if; + when T2_WRSTAT => + if SECT_LEN = "00000000000" then + NEXT_CMD_STATE <= T2_WR_CRC; -- Write operation finished. + else + NEXT_CMD_STATE <= T2_LOAD_SHFT; + end if; + when T2_WR_CRC => + if DELAY = true then + NEXT_CMD_STATE <= T2_WR_FF; + else + NEXT_CMD_STATE <= T2_WR_CRC; + end if; + when T2_WR_FF => + if DELAY = true then + NEXT_CMD_STATE <= T2_MULTISECT; + else + NEXT_CMD_STATE <= T2_WR_FF; + end if; + -------------------------------------------------------------------- + ---------------- type3 write track command stuff ------------------- + -------------------------------------------------------------------- + when T3_WR => + if WPRTn = '0' then + NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk. + else + NEXT_CMD_STATE <= T3_DELAY_B3; + end if; + when T3_DELAY_B3 => + if DELAY = true then + NEXT_CMD_STATE <= T3_VERIFY_DRQ; + else + NEXT_CMD_STATE <= T3_DELAY_B3; + end if; + when T3_VERIFY_DRQ => + if DRQ_I = '0' then + NEXT_CMD_STATE <= T3_CHECK_INDEX_1; + else + NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host). + end if; + when T3_CHECK_INDEX_1 => + if IPn = '0' then + NEXT_CMD_STATE <= T3_LOAD_SHFT; + else + NEXT_CMD_STATE <= T3_CHECK_INDEX_1; + end if; + when T3_LOAD_SHFT => + NEXT_CMD_STATE <= T3_WR_DATA; + when T3_WR_DATA => + if DELAY = true then + NEXT_CMD_STATE <= T3_CHECK_INDEX_2; + else + NEXT_CMD_STATE <= T3_WR_DATA; + end if; + when T3_CHECK_INDEX_2 => + if INDEX_MARK = '1' then + NEXT_CMD_STATE <= IDLE; -- End of track reached. + elsif DRQ_I = '0' then -- New data has been loaded. + NEXT_CMD_STATE <= T3_LOAD_SHFT; -- Fetch new data. + else + NEXT_CMD_STATE <= T3_DATALOST; -- Fill in nullbyte. + end if; + when T3_DATALOST => + if DELAY = true then + NEXT_CMD_STATE <= T3_CHECK_INDEX_2; + else + NEXT_CMD_STATE <= T3_DATALOST; + end if; + -------------------------------------------------------------------- + --------------- type3 read track command stuff -------------------- + -------------------------------------------------------------------- + when T3_RD_TRACK => + -- wait for index pulse: + if IPn = '0' then + NEXT_CMD_STATE <= T3_SHIFT; + else + NEXT_CMD_STATE <= T3_RD_TRACK; + end if; + when T3_SHIFT => + if DELAY = true then + NEXT_CMD_STATE <= T3_CHECK_INDEX_3; + else + NEXT_CMD_STATE <= T3_SHIFT; + end if; + when T3_CHECK_INDEX_3 => + if INDEX_MARK = '1' then + NEXT_CMD_STATE <= IDLE; -- End of track reached. + else + NEXT_CMD_STATE <= T3_DETECT_AM; + end if; + when T3_DETECT_AM => -- Detect for ID address mark. + if ID_AM = '1' then + NEXT_CMD_STATE <= T3_CHECK_DR; + else + NEXT_CMD_STATE <= T3_CHECK_BYTE; + end if; + when T3_CHECK_BYTE => + if BYTE_RDY = true then + NEXT_CMD_STATE <= T3_CHECK_DR; + else + NEXT_CMD_STATE <= T3_SHIFT; + end if; + when T3_CHECK_DR => + NEXT_CMD_STATE <= T3_LOAD_DATA_1; + when T3_LOAD_DATA_1 => + NEXT_CMD_STATE <= T3_SET_DRQ_1; + when T3_SET_DRQ_1 => + NEXT_CMD_STATE <= T3_SHIFT; + -------------------------------------------------------------------- + ---------------- type3 read address command stuff ------------------ + -------------------------------------------------------------------- + when T3_RD_ADR => + -- check for 6 index holes + if INDEX_CNT = true then + NEXT_CMD_STATE <= IDLE; -- Break due to timeout. + else + NEXT_CMD_STATE <= T3_VERIFY_AM; + end if; + when T3_VERIFY_AM => -- Check for existing ID address mark + if ID_AM = '1' then + NEXT_CMD_STATE <= T3_SHIFT_ADR; + else + NEXT_CMD_STATE <= T3_RD_ADR; + end if; + when T3_SHIFT_ADR => + if DELAY = true then + NEXT_CMD_STATE <= T3_LOAD_DATA_2; + else + NEXT_CMD_STATE <= T3_SHIFT_ADR; + end if; + when T3_LOAD_DATA_2 => + NEXT_CMD_STATE <= T3_SET_DRQ_2; + when T3_SET_DRQ_2 => + NEXT_CMD_STATE <= T3_CHECK_RD; + when T3_CHECK_RD => + if T3_TRADR = true then + NEXT_CMD_STATE <= T3_LOAD_SR; + else + NEXT_CMD_STATE <= T3_SHIFT_ADR; + end if; + when T3_LOAD_SR => + NEXT_CMD_STATE <= T3_VERIFY_CRC; + when T3_VERIFY_CRC => + -- The CRC logic starts during T3_VERIFY_AM (missing clock transitions). + if DELAY = true then + NEXT_CMD_STATE <= IDLE; -- Operation finished (with or without CRC error). + else + NEXT_CMD_STATE <= T3_VERIFY_CRC; -- Wait until CRC logic is ready. + end if; + end case; + end process CMD_DECODER; + + P_DELAY: process(RESETn, CLK, CMD_STATE, T3_DATATYPE, DDEn, CMD) + -- This process is responsible to control the DELAY signal in the different command + -- states of the main state machine. These states finish, if the signal DELAY is + -- asserted. The condition for asserted DELAY is the correct number of data strobes + -- which are supervised by the DATA_STRB inputs. + -- Another condition is a time delay required in the following states: + -- In DELAY_15MS there is a delay of 30ms. + -- In T1_STEP_PULSE the delay is according to the CMD(1 downto 0) as follows: + -- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms. + -- In T1_VERIFY_DELAY there is a delay of 30ms. + variable DELCNT : std_logic_vector(19 downto 0); + begin + if RESETn = '0' then + DELCNT := (others => '0'); + elsif CLK = '1' and CLK' event then + -- Reset the delay right after it occurs: + if DELAY = true then + DELCNT := (others => '0'); + elsif DATA_AM = '1' or DDATA_AM = '1' then -- Reset in command state T2_VERIFY_AM. + DELCNT := (others => '0'); + else + case CMD_STATE is + -- Time delays work on CLK edges. + when DELAY_15MS | T1_CHECK_DIR | T1_STEP_DELAY | T1_VERIFY_DELAY => + DELCNT := DELCNT + '1'; + -- Bit count delays work on data strobes. + -- Read from disk operation: + when T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | T2_SCAN_TRACK | T2_SCAN_SECT | + T2_SCAN_LEN | T2_VERIFY_CRC_1 | T2_VERIFY_AM | T2_FIRSTBYTE | + T2_NEXTBYTE | T2_VERIFY_CRC_2 | T3_SHIFT | T3_SHIFT_ADR | T3_VERIFY_CRC => + if DATA_STRB = '1' then + DELCNT := DELCNT + '1'; + end if; + -- Write to disk operation: + when T2_DELAY_B2 | T2_DELAY_B8 | T2_WR_LEADIN | + T2_WR_AM | T2_DELAY_B1 |T2_DELAY_B11 | T2_WR_BYTE | T2_DATALOST | + T2_WR_CRC | T2_WR_FF | T3_DELAY_B3 | T3_WR_DATA | T3_DATALOST => + if DATA_STRB = '1' then + DELCNT := DELCNT + '1'; + end if; + when others => + DELCNT := (others => '0'); -- Clear the delay counter if not used. + end case; + end if; + end if; + + case CMD_STATE is + when DELAY_15MS | T1_VERIFY_DELAY => + case DELCNT is + --when x"75300" => DELAY <= true; -- 30ms + when x"3A980" => DELAY <= true; -- 15ms, thanks to L. Amsdon. + when others => DELAY <= false; + end case; + when T1_CHECK_DIR => + if DDEn = '1' and DELCNT = x"00300" then -- 48us in FM + DELAY <= true; + elsif DDEn = '0' and DELCNT = x"00180" then -- 24us in MFM. + DELAY <= true; + else + DELAY <= false; + end if; + when T1_STEP_DELAY => + if CMD(1 downto 0) = "11" and DELCNT >= x"0BB80" then -- 3ms + DELAY <= true; + elsif CMD(1 downto 0) = "10" and DELCNT >= x"07D00" then -- 2ms + DELAY <= true; + elsif CMD(1 downto 0) = "01" and DELCNT >= x"2EE00" then -- 12ms + DELAY <= true; + elsif CMD(1 downto 0) = "00" and DELCNT >= x"17700" then -- 6ms + DELAY <= true; + else + DELAY <= false; + end if; + when T1_SCAN_TRACK | T2_SCAN_TRACK | T2_SCAN_LEN | T2_FIRSTBYTE | T2_NEXTBYTE | + T2_WR_BYTE | T2_DATALOST | T2_WR_FF | T3_DATALOST | T3_SHIFT_ADR => + case DELCNT is + when x"00008" => DELAY <= true; -- The delay in this case is 8 bit times. + when others => DELAY <= false; + end case; + when T1_SCAN_CRC => + case DELCNT is + when x"00018" => DELAY <= true; -- Scan for 3 bytes. + when others => DELAY <= false; + end case; + when T2_WR_AM => + if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark bits (FM mode). + DELAY <= true; + elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark bits (MFM mode). + DELAY <= true; + else + DELAY <= false; + end if; + when T2_VERIFY_AM => + if DDEn = '1' and DELCNT >= x"00148" then -- FM mode. + DELAY <= true; -- (11+6+1)+1 = 19 Byte Times, plus 10 Byte times uncertainty. + elsif DDEn = '0' and DELCNT >= x"00188" then -- MFM mode. + DELAY <= true; -- (22+12+3+1)+1 = 39 Byte Times, plus 10 Byte times uncertainty. + else + DELAY <= false; + end if; + when T2_WR_LEADIN => + if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero bits in FM mode. + DELAY <= true; + elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero bits in MFM mode. + DELAY <= true; + else + DELAY <= false; + end if; + when T2_DELAY_B1 => + case DELCNT is + when x"00008" => DELAY <= true; -- Delay is 1 byte. + when others => DELAY <= false; + end case; + when T3_DELAY_B3 => + case DELCNT is + when x"00018" => DELAY <= true; -- Delay is 3 bytes. + when others => DELAY <= false; + end case; + when T2_DELAY_B8 => + case DELCNT is + when x"00040" => DELAY <= true; -- Delay is 8 bytes. + when others => DELAY <= false; + end case; + when T2_DELAY_B11 => + case DELCNT is + when x"00058" => DELAY <= true; -- Delay is 11 bytes. + when others => DELAY <= false; + end case; + when T2_VERIFY_CRC_2 => + -- In this state the original WD1772 state machine causes the CRC data to appear 1 byte + -- too early. The reason is the construction of the states T2_LOAD_DATA and T2_NEXTBYTE + -- where the length counter and the DRQ flag are serviced in T2_LOAD_DATA. Therefore the + -- delay is only 1 byte instead of 2. + case DELCNT is + when x"00008" => DELAY <= true; -- Scan for 2 bytes but wait only 1 byte. + when others => DELAY <= false; + end case; + when T1_VERIFY_CRC | T2_SCAN_SECT | T2_VERIFY_CRC_1 | T2_DELAY_B2 | T2_WR_CRC | T3_VERIFY_CRC => + case DELCNT is + when x"00010" => DELAY <= true; -- Scan for 2 bytes (e. g. side and sector in T2_SCAN_SECT). + when others => DELAY <= false; + end case; + when T3_WR_DATA => + if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC bits. + DELAY <= true; + elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data bits. + DELAY <= true; + else + DELAY <= false; + end if; + when T3_SHIFT => + case DELCNT is + when x"00001" => DELAY <= true; -- Scan just one data bit. + when others => DELAY <= false; + end case; + when others => + DELAY <= false; + end case; + end process P_DELAY; + + INDEX_COUNTER: process(RESETn, CLK, CMD_STATE) + -- This process is intended to control some command states via the index pulse behavior. + -- In the original WD177x there is foreseen a delay of several index pulses (about 1s). + -- It is achieved by counting the index pulses of the disk. This encounters problems, + -- if the disk is not inserted. For this reason there is additionally to the index counter + -- a timeout which is active if there are no index pulses. + variable CNT : std_logic_vector(3 downto 0); + variable TIMEOUT : std_logic_vector(27 downto 0); + variable LOCK : boolean; + begin + if RESETn = '0' then + CNT := x"0"; + TIMEOUT := (others => '0'); + LOCK := false; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + -- Be aware that there must sometimes checked several states for the presence of IPn! + when SPINUP | T1_SPINDOWN | T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | + T2_INIT | T2_SCAN_TRACK | T2_SCAN_SECT |T2_SCAN_LEN | T2_VERIFY_CRC_1 | T3_RD_ADR | T3_VERIFY_AM => + if IPn = '0' and LOCK = false then -- Count the index pulses. + CNT := CNT + '1'; + LOCK := true; + elsif IPn = '1' then + LOCK := false; + end if; + -- + if TIMEOUT < x"17FFFFF" then -- Timeout of about 1.5s. + TIMEOUT := TIMEOUT + '1'; + end if; + when others => + CNT := x"0"; + TIMEOUT := (others => '0'); + end case; + end if; + -- + if CMD_STATE = SPINUP and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout. + INDEX_CNT <= true; + elsif CMD_STATE = T1_SPINDOWN and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout. + INDEX_CNT <= true; + elsif CMD_STATE = T2_INIT and (CNT = "101" or TIMEOUT = x"17FFFFF") then -- 5 pulses or timeout. + INDEX_CNT <= true; + elsif CMD_STATE = T3_RD_ADR and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout. + INDEX_CNT <= true; + else + INDEX_CNT <= false; + end if; + end process INDEX_COUNTER; + + P_INDEX_MARK: process + -- This process controls the occurence of an index pulse during read track + -- and write track commands. The flag INDEX_MARK is cleared at the + -- beginning of these two commands during the first check for an index + -- pulse and is set right after the next index pulse occurs, which means + -- track processing has completed. + variable LOCK: boolean; + begin + wait until CLK = '1' and CLK' event; + if CMD_STATE = T3_RD_TRACK and IPn = '0' then + INDEX_MARK <= '0'; -- Reset the flag. + LOCK := true; + elsif CMD_STATE = T3_CHECK_INDEX_1 and IPn = '0' then + INDEX_MARK <= '0'; -- Reset the flag. + LOCK := true; + elsif IPn = '0' and LOCK = false then + INDEX_MARK <= '1'; -- Index pulse has passed. + LOCK := true; + elsif IPn = '1' then + LOCK := false; + end if; + end process P_INDEX_MARK; + + P_T3_DATATYPE: process(RESETn, CLK) + -- In type 3 write track command, it is necessary to store the information, which data + -- has to be written to disk (in command state T3_WR_DATA. This information is sampled + -- in the command state T3_LOAD_SHFT which preceeds the command state T3_WR_DATA. + begin + if RESETn = '0' then + T3_DATATYPE <= x"00"; + elsif CLK = '1' and CLK' event then + if CMD_STATE = T3_LOAD_SHFT then + T3_DATATYPE <= DR; + end if; + end if; + end process P_T3_DATATYPE; + + CNT_T3BYTES: process(RESETn, CLK, CMD_STATE) + -- This process counts the bytes read in the type III read address + -- command during the command states T3_SHIFT_ADR, T3_LOAD_DATA2, + -- T3_SET_DRQ_2 and T3_CHECK_RD. + variable CNT : std_logic_vector(2 downto 0); + begin + if RESETn = '0' then + CNT := "000"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when T3_VERIFY_AM => + CNT := "000"; -- Clear the counter right befor the count operation. + when T3_SET_DRQ_2 => + CNT := CNT + '1'; -- Increment after each read cycle. + when others => + null; + end case; + end if; + case CNT is + when "100" => T3_TRADR <= true; + when others => T3_TRADR <= false; + end case; + end process CNT_T3BYTES; + + BYTEASMBLY: process(RESETn, CLK) + -- This process controls the condition in the CMD_STATE T3_CHECK_DR. + -- Therefore the bits shifted into the DSR in command state T3_SHIFT are counted. + -- The count condition is entering the command state T3_CHECK_INDEX_3. The clear + -- condition is either the command state IDLE or the command state T3_CHECK_DR. + variable CNT : std_logic_vector(3 downto 0); + begin + if RESETn = '0' then + CNT := x"0"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when IDLE => CNT := x"0"; + when T3_CHECK_INDEX_3 => CNT := CNT + '1'; + when T3_CHECK_DR => CNT := (others => '0'); + when others => null; + end case; + end if; + case CNT is + when x"8" => BYTE_RDY <= true; + when others => BYTE_RDY <= false; + end case; + end process BYTEASMBLY; + + P_DIR: process(RESETn, CLK, DIR) + -- This portion of code is responsible to control the right stepping + -- direction in type I commands. + begin + if RESETn = '0' then + DIR <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = DECODE and CMD(7 downto 5) = "010" then -- Step in. + DIR <= '1'; + elsif CMD_STATE = DECODE and CMD(7 downto 5) = "011" then -- Step out. + DIR <= '0'; + elsif CMD_STATE = T1_COMP_TR_DSR and DSR > TR then -- Seek. + DIR <= '1'; + elsif CMD_STATE = T1_COMP_TR_DSR and DSR < TR then -- Seek. + DIR <= '0'; + end if; + end if; + DIRC <= DIR; -- Copy signal to the output. + end process P_DIR; + + P_DRQ: process(RESETn, CLK, DRQ_I) + begin + if RESETn = '0' then + DRQ_I <= '0'; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when INIT => + DRQ_I <= '0'; + when T2_LOAD_DATA | T2_SET_DRQ | T2_LOAD_SHFT => + DRQ_I <= '1'; + when T3_WR | T3_LOAD_SHFT | T3_SET_DRQ_1 | T3_SET_DRQ_2 => + DRQ_I <= '1'; + when others => + null; + end case; + -- The data request bit is also cleared by reading or writing the + -- data register (direct memory access operation). + if (DATA_RD = true or DATA_WR = true) then + DRQ_I <= '0'; + end if; + end if; + -- + DRQ <= DRQ_I; -- Copy to entity. + -- + end process P_DRQ; + + -- The DRQ_IPn detects the index pulse during type I commands and a forced interrupt or + -- DRQ during type II and III commands. + -- The index pulse flag is active high and can be used for the detection of an inserted disk. + DRQ_IPn <= not IPn when CMD(7) = '0' else + not IPn when CMD(7 downto 4) = x"D" and BUSY = '0' else DRQ_I; + + P_BUSY: process(RESETn, CLK) + begin + if RESETn = '0' then + BUSY <= '0'; + elsif CLK = '1' and CLK' event then + -- During forced interrupt, the busy flag is reset when the command + -- state machine enters the IDLE state. + if CMD_STATE = INIT then + BUSY <= '1'; -- set BUSY flag for all command types I ... III. + elsif CMD_STATE = IDLE then + BUSY <= '0'; -- Reset BUSY after entering IDLE in any case. + end if; + end if; + end process P_BUSY; + + P_SEEK_RNF: process(RESETn, CLK) + -- Seek error or record not found error flag. + begin + if RESETn = '0' then + SEEK_RNF <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = INIT then + SEEK_RNF <= '0'; -- Clear the flag for all command types I ... III. + elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then + SEEK_RNF <= '1'; -- Seek error (SEEK). + elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then + SEEK_RNF <= '1'; -- Seek error (SEEK). + elsif CMD_STATE = T2_INIT and INDEX_CNT = true then + SEEK_RNF <= '1'; -- Record not found (RNF). + elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then + SEEK_RNF <= '1'; -- Record not found (RNF). + end if; + end if; + end process P_SEEK_RNF; + + P_INTRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INTRQ <= '0'; + elsif CLK = '1' and CLK' event then + -- Interrupt reset conditions: + if STAT_RD = true and CMD /= x"D8" then + -- No clear during immediately forced interrupt. + INTRQ <= '0'; -- Clear the flag when status register is read. + elsif CMD_WR = true and CMD = x"D0" then + -- Clear with the next write access to the command register after the + -- forced interrupt x"D0" was written. + INTRQ <= '0'; + elsif CMD_STATE = INIT and CMD(7 downto 6) /= "11" then + INTRQ <= '0'; -- Clear the flag for type I and type II commands during start of execution. + -- Interrupt set conditions. + elsif CMD = x"D8" and CMD_STATE = IDLE then + INTRQ <= '1'; -- Force interrupt immediately (after the break took affect). + elsif CMD = x"D4" and IPn = '0' and CMD_STATE = IDLE then + INTRQ <= '1'; -- Force interrupt on next index pulse (after the break took affect). + elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then + INTRQ <= '1'; -- Indicate interrupt request due to seek error. + elsif CMD_STATE = T1_VERIFY_DELAY and CMD(2) = '0' then + INTRQ <= '1'; -- Indicate interrupt: command finished or interrupted. + elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then + INTRQ <= '1'; -- Indicate interrupt request, reason: seek error. + elsif CMD_STATE = T1_VERIFY_CRC and CRC_ERR = '0' then + INTRQ <= '1'; -- Indicate interrupt request; command correct, no CRC error. + elsif CMD_STATE = T2_RD_WR_SECT and CMD(7 downto 5) = "101" and WPRTn = '0' then + INTRQ <= '1'; -- Indicate interrupt request because disk is write protected. + elsif CMD_STATE = T2_INIT and INDEX_CNT = true then + INTRQ <= '1'; -- Indicate interrupt request, reason: timeout. + elsif CMD_STATE = T2_VERIFY_CRC_2 and DELAY = true and CRC_ERR = '1' then + INTRQ <= '1'; -- Indicate interrupt request due to CRC error. + elsif CMD_STATE = T2_MULTISECT and CMD(4) = '0' then + INTRQ <= '1'; -- Indicate interrupt request, command correct finished. + elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then + INTRQ <= '1'; -- Indicate interrupt request, reason: lost data. + elsif CMD_STATE = T3_WR and WPRTn = '0' then + INTRQ <= '1'; -- Indicate interrupt request, reason: disk is write protected. + elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then + INTRQ <= '1'; -- Indicate interrupt request due to lost data. + elsif CMD_STATE = T3_CHECK_INDEX_2 and INDEX_MARK = '1' then + INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly. + elsif CMD_STATE = T3_CHECK_INDEX_3 and INDEX_MARK = '1' then + INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly. + elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then + INTRQ <= '1'; -- Indicate interrupt request because record was not found. + elsif CMD_STATE = T3_VERIFY_CRC then + INTRQ <= '1'; -- Indicate interrupt request; command finished with or without CRC error. + end if; + end if; + end process P_INTRQ; + + P_LOST_DATA_TR00: process(RESETn, CLK) + -- Logic for the status bit number 2: + -- The TRACK00 flag is used to detect wether a floppy disk drive + -- is connected or not. + begin + if RESETn = '0' then + LOST_DATA_TR00 <= '0'; + elsif CLK = '1' and CLK' event then + if CMD(7 downto 4) = x"D" and BUSY = '0' then -- Forced interrupt. + LOST_DATA_TR00 <= not TRACK00n; + elsif CMD_STATE = INIT then + LOST_DATA_TR00 <= '0'; + elsif CMD_STATE = T1_VERIFY_DELAY then + LOST_DATA_TR00 <= not TRACK00n; + elsif CMD_STATE = T2_VERIFY_DRQ_1 and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T2_VERIFY_DRQ_3 and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T3_DATALOST then + LOST_DATA_TR00 <= '1'; + elsif CMD_STATE = T3_CHECK_DR and DRQ_I = '1' then + LOST_DATA_TR00 <= '1'; + end if; + end if; + end process P_LOST_DATA_TR00; + + MOTORSWITCH: process(RESETn, CLK) + variable INDEXCNT : std_logic_vector(3 downto 0); + variable LOCK : boolean; + begin + if RESETn = '0' then + MO <= '0'; + INDEXCNT := x"0"; + LOCK := false; + elsif CLK = '1' and CLK' event then + if CMD_STATE /= IDLE then + INDEXCNT := x"9"; -- Initialise the index counter. + LOCK := false; + elsif LOCK = false and IPn = '0' and INDEXCNT > x"0" then + INDEXCNT := INDEXCNT - '1'; -- Count the index pulses in the IDLE state. + LOCK := true; + elsif IPn = '1' then + LOCK := false; + end if; + -- + if CMD_STATE = INIT and CMD_WR = false then + MO <= '1'; -- Start the motor for all command types I ... III in this state. + elsif INDEXCNT = x"0" then + MO <= '0'; -- The motor stops after 9 index pulses in idle state. + end if; + end if; + end process MOTORSWITCH; + + WRITE_PROTECT: process(RESETn, CLK) + begin + if RESETn = '0' then + WR_PR <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = INIT and CMD(7) = '1' then + WR_PR <= '0'; -- Clear the flag for type II and type III commands. + elsif CMD_STATE = T2_RD_WR_SECT and WPRTn = '0' then + WR_PR <= '1'; + elsif CMD_STATE = T3_WR and WPRTn = '0' then + WR_PR <= '1'; + end if; + end if; + end process WRITE_PROTECT; + + RECTYPE_SPINUP: process(RESETn, CLK) + begin + if RESETn = '0' then + SPINUP_RECTYPE <= '0'; + elsif CLK = '1' and CLK' event then + if CMD_STATE = INIT then + SPINUP_RECTYPE <= '0'; -- Clear the flag for type II...III commands. + elsif CMD_STATE = SPINUP and CMD(7) = '0' and INDEX_CNT = true then + SPINUP_RECTYPE <= '1'; -- SPINUP SEQUENCE for type I commands has finished. + elsif CMD_STATE = T2_VERIFY_AM and (DATA_AM = '1' or DDATA_AM = '1') then + case DSR is + when x"F8" => SPINUP_RECTYPE <= '1'; -- Deleted data address mark. + when x"FB" => SPINUP_RECTYPE <= '0'; -- Normal data address mark. + when others => null; -- Forbidden, should never appear. + end case; + end if; + end if; + end process RECTYPE_SPINUP; + + WRITEGATE: process(RESETn, CLK) + begin + if RESETn = '0' then + WG <= '0'; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when T2_WR_LEADIN | T3_LOAD_SHFT => + WG <= '1'; + when T2_MULTISECT | IDLE => + WG <= '0'; + when others => + null; + end case; + end if; + end process WRITEGATE; + + RESTORE_TRAP: process(RESETn, CLK) + -- This process is responsible to supervise the RESTORE command. + -- If after 255 stepping pulses no TRACK00n was not detected, the + -- RESTORE command is terminated and the interrupt request and the + -- seek error are set. + variable STEP_CNT : std_logic_vector(7 downto 0); + begin + if RESETn = '0' then + STEP_CNT := (others => '0'); + elsif CLK = '1' and CLK' event then + if CMD_STATE = IDLE then + STEP_CNT := x"00"; + elsif CMD(7 downto 4) /= "0000" then -- No RESTORE command. + STEP_CNT := x"00"; + elsif CMD_STATE = T1_STEP and STEP_CNT < x"FF" then + STEP_CNT := STEP_CNT + '1'; + end if; + end if; + -- + case STEP_CNT is + when x"FF" => STEP_TRAP <= true; + when others => STEP_TRAP <= false; + end case; + end process RESTORE_TRAP; + + STEPPULSE: process(RESETn, CLK) + -- The step pulse duration is in the original WD1772 4us in MFM mode and 8 us. + -- in FM mode This process is responsible to provide the correct pulse lengths. + variable CNT : std_logic_vector(7 downto 0); + begin + if RESETn = '0' then + CNT := (others => '0'); + elsif CLK = '1' and CLK' event then + if CMD_STATE = T1_STEP then + case DDEn is + when '1' => CNT := x"80"; --Start counter for FM step pulse. + when '0' => CNT := x"40"; --Start counter for MFM step pulse. + end case; + elsif CNT > x"00" then + CNT := CNT -1; -- Count 63 or 127 CLK cycles ... + end if; + case CNT is + when x"00" => STEP <= '0'; + when others => STEP <= '1'; --...result in 3.875us or 7.75us pulse. + end case; + end if; + end process STEPPULSE; + + TRACK_MEM: process(RESETn, CLK, TRACKMEM) + -- This process is necessary to store the actual track number in the + -- type III command 'read address' because the track number is written + -- to the sector register some byte times after the detection of the + -- track number from disk. + begin + if RESETn = '0' then + TRACKMEM <= x"00"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when IDLE => + TRACKMEM <= x"00"; -- Clear the Track memory. + when T3_LOAD_DATA_2 => + TRACKMEM <= DSR; -- Store the actual track number. + when others => + null; + end case; + end if; + TRACK_NR <= TRACKMEM; -- Output the TRACKMEM. + end process TRACK_MEM; + + SECT_LENGTH: process(RESETn, CLK, SECT_LEN) + -- This process supervises the read sector and write sector + -- commands. If the sector read or write are equal to the + -- sector length, the commands read sector and write sector + -- are ready. + begin + if RESETn = '0' then + SECT_LEN <= "00000000000"; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when T2_SCAN_LEN => + -- Bring in the correct sector length. + case DSR(1 downto 0) is + when "00" => SECT_LEN <= "00010000000"; -- 128 Byte per sector. + when "01" => SECT_LEN <= "00100000000"; -- 256 Byte per sector. + when "10" => SECT_LEN <= "01000000000"; -- 512 Byte per sector. + when "11" => SECT_LEN <= "10000000000"; -- 1024 Byte per sector. + when others => SECT_LEN <= "10000000000"; -- Dummy for U, X, Z, W, H, L, -. + end case; + when T2_LOAD_DATA | T2_LOAD_SHFT => + SECT_LEN <= SECT_LEN - '1'; + when others => + null; + end case; + end if; + end process SECT_LENGTH; + + P_CRC_ERR: process(RESETn, CLK) + -- This code checks the CRC status in the right command states + -- and sets or resets the CRC error status flag. + begin + if RESETn = '0' then + CRC_ERRFLAG <= '0'; + elsif CLK = '1' and CLK' event then + case CMD_STATE is + when INIT => + if CMD(7) = '0' then + CRC_ERRFLAG <= '0'; -- Reset for type I commands only. + end if; + when T1_VERIFY_CRC | T2_VERIFY_CRC_1 => + if CRC_ERR = '1' and DELAY = true then + CRC_ERRFLAG <= '1'; -- Set CRC error flag... + elsif CRC_ERR = '0' and DELAY = true then + CRC_ERRFLAG <= '0'; -- ... or reset CRC error flag. + end if; + when T2_VERIFY_CRC_2 | T3_VERIFY_CRC => + if CRC_ERR = '1' and DELAY = true then + -- Set CRC error flag but no reset in here. + -- The CRC is already reset by the previous checks. + CRC_ERRFLAG <= '1'; + end if; + when others => + null; + end case; + end if; + end process P_CRC_ERR; + + CMD_WR <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '0' else false; -- Command register write. + STAT_RD <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '1' else false; -- Status register read. + DATA_WR <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '0' else false; -- Data register write. + DATA_RD <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '1' else false; -- Data register read. + + -- Track register arithmetics controls: + TR_PRES <= '1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command. + TR_CLR <= '1' when CMD_STATE = T1_HEAD_CTRL and TRACK00n = '0' and DIR = '0' else '0'; + TR_INC <= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '1' else '0'; + TR_DEC <= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '0' else '0'; + + -- Sector register arithmetics: + SR_INC <= '1' when CMD_STATE = T2_MULTISECT and CMD(4) = '1' else '0'; -- Multi sector enabled. + SR_LOAD <= '1' when CMD_STATE = T3_LOAD_SR else '0'; + + -- Data register arithmetics controls: + DR_CLR <= '1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command. + DR_LOAD <= '1' when CMD_STATE = T2_LOAD_DATA else + '1' when CMD_STATE = T3_LOAD_DATA_1 else + '1' when CMD_STATE = T3_LOAD_DATA_2 else '0'; + + -- Shift register arithmetics controls: + -- During type I and type II commands all characters are allowed as data. + -- During the type III write track command, there are some special characters + -- which may not appear as normal data. See the register file for more information. + SHFT_LOAD_SD <= '1' when CMD_STATE = T3_LOAD_SHFT else '0'; -- Special data. + SHFT_LOAD_ND <= '1' when CMD_STATE = T1_LOAD_SHFT else + '1' when CMD_STATE = T2_LOAD_SHFT else '0'; -- Normal data. + + P_CRC_PRES: process(RESETn, CLK) + -- CRC preset during write sector and write track commands. + variable LOCK : boolean; + begin + if RESETn = '0' then + CRC_PRES <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + -- In write track command, the CRC is initialised at the beginning of the + -- first A1 data and released during shifting the CRC out. + if CMD_STATE = T2_WR_AM and LOCK = false then + CRC_PRES <= '1'; -- Write sector command. + LOCK := true; + elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F5" and LOCK = false then -- x"F5" means write A1. + CRC_PRES <= '1'; -- Write track command. + LOCK := true; + elsif CMD_STATE = T2_WR_CRC then + CRC_PRES <= '0'; -- Write sector command. + LOCK := false; + elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F7" then + CRC_PRES <= '0'; -- Write track command. + LOCK := false; + else + CRC_PRES <= '0'; + end if; + end if; + end process P_CRC_PRES; + + -- Write control signals: + AM_2_DISK <= '1' when CMD_STATE = T2_WR_AM else '0'; + FF_2_DISK <= '1' when CMD_STATE = T2_WR_FF else '0'; + DSR_2_DISK <= '1' when CMD_STATE = T2_WR_BYTE else + '1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE /= x"F7" else '0'; -- not during CRC. + CRC_2_DISK <= '1' when CMD_STATE = T2_WR_CRC else + '1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE = x"F7" else '0'; + + -- Write precompensation control: + PRECOMP_EN <= '1' when CMD(7 downto 4) = x"A" and CMD(1) = '0' else -- Write single sector. + '1' when CMD(7 downto 4) = x"B" and CMD(1) = '0' else -- Write multiple sector. + '1' when CMD(7 downto 4) = x"F" and CMD(1) = '0' else '0'; -- Write track. + + -- Disk data flow direction: + DISK_RWn <= -- Write sector command: + '0' when CMD_STATE = T2_WR_LEADIN else + '0' when CMD_STATE = T2_WR_AM else + '0' when CMD_STATE = T2_LOAD_SHFT else + '0' when CMD_STATE = T2_WR_BYTE else + '0' when CMD_STATE = T2_VERIFY_DRQ_3 else + '0' when CMD_STATE = T2_DATALOST else + '0' when CMD_STATE = T2_WRSTAT else + '0' when CMD_STATE = T2_WR_CRC else + '0' when CMD_STATE = T2_WR_FF else + -- Write track command: + '0' when CMD_STATE = T3_LOAD_SHFT else + '0' when CMD_STATE = T3_WR_DATA else + '0' when CMD_STATE = T3_CHECK_INDEX_2 else + '0' when CMD_STATE = T3_DATALOST else '1'; +end BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd new file mode 100644 index 0000000..54b2060 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd @@ -0,0 +1,162 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- The CRC cyclic redundancy checker unit. Further description ---- +---- see below. ---- +---- ---- +---- Working principle of the CRC generator and verify unit: ---- +---- During read operation: ---- +---- The CRC generator is switched on via after the detection of ---- +---- the address ID of the data ID mark. The CRC generation last ---- +---- in case of the address ID until the lenght byte is read. ---- +---- In case of generation after the data address mark the CRC ---- +---- generator is activated until the last data byte is read. ---- +---- The number of data bytes to be read depends on the LENGHT ---- +---- information in the header file. After generation of the CRC ---- +---- the CRC_GEN is switched off and the VERIFY procedure begins ---- +---- by activating CRC_VERIFY. The previously generated CRC is ---- +---- then compared (serially) with the two consecutive read CRC ---- +---- bytes. The CRC error appeas, when the comparision fails. ---- +---- During write operation: ---- +---- The CRC generator is switched on via after the detection of ---- +---- the address ID of the data ID mark. The CRC generation last ---- +---- in case of the address ID until the lenght byte is read. ---- +---- In case of generation after the data address mark the CRC ---- +---- generator is activated until the last data byte is read. ---- +---- The number of data bytes to be read depends on the LENGHT ---- +---- information in the header file. After the generation of the ---- +---- two CRC bytes, the write out process begins by activating ---- +---- CRC_SHFTOUT. The CRC data appears in this case serially on ---- +---- the CRC_SDOUT. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- CRC_SHIFT has now synchronous reset to meeet preset behaviour. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_CRC_LOGIC is + port( + -- System control + CLK : in bit; + RESETn : in bit; + DISK_RWn : in bit; + + -- Preset controls: + DDEn : in bit; + ID_AM : in bit; + DATA_AM : in Bit; + DDATA_AM : in Bit; + + -- CRC unit: + SD : in bit; -- Serial data input. + CRC_STRB : in bit; -- Data strobe. + CRC_2_DISK : in bit; -- Forces the unit to flush the CRC remainder. + CRC_PRES : in bit; -- Presets the CRC unit during write to disk. + CRC_SDOUT : out bit; -- Serial data output. + CRC_ERR : out bit -- Indicates CRC error. + ); +end WF1772IP_CRC_LOGIC; + +architecture BEHAVIOR of WF1772IP_CRC_LOGIC is +signal CRC_SHIFT : bit_vector(15 downto 0); +begin + P_CRC: process + -- The shift register is initialised with appropriate values in HD or DD mode. + -- In theory the shift register should be preset to ones. Due to a latency of one byte + -- in FM mode or 4 bytes in MFM mode it is necessary to preset the shift register with + -- the CRC values of this ID address mark, data address mark and the A1 sync bytes. The + -- latency is caused by the addressmark detector which needs one or 4 byte time(s) for + -- detection. The CRC unit therefore starts with every detection of an address mark and + -- ends if the CRC unit is flushed. + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + CRC_SHIFT <= (others => '1'); + elsif CRC_2_DISK = '1' then + if CRC_STRB = '1' then + CRC_SHIFT <= CRC_SHIFT(14 downto 0) & '0'; + end if; + elsif CRC_PRES = '1' then -- Preset during write sector or write track command. + CRC_SHIFT <= x"FFFF"; + elsif DDEn = '1' and ID_AM = '1' then -- DD mode and ID address mark detected. + CRC_SHIFT <= x"EF21"; -- The CRC-CCITT for data x"FE" is x"EF21" + elsif DDEn = '1' and DATA_AM = '1' then -- DD mode and data address mark detected. + CRC_SHIFT <= x"BF84"; -- The CRC-CCITT for data x"FB" is x"BF84" + elsif DDEn = '1' and DDATA_AM = '1' then -- DD mode and deleted data address mark detected. + CRC_SHIFT <= x"8FE7"; -- The CRC-CCITT for data x"F8" is x"8FE7" + elsif DDEn = '0' and ID_AM = '1' then -- HD mode and ID address mark detected. + CRC_SHIFT <= x"B230"; -- The CRC-CCITT for data x"A1A1A1FE" is x"B230" + elsif DDEn = '0' and DATA_AM = '1' then -- HD mode and data address mark detected. + CRC_SHIFT <= x"E295"; -- The CRC-CCITT for data x"A1A1A1FB" is x"E295" + elsif DDEn = '0' and DDATA_AM = '1' then -- HD mode and deleted data address mark detected. + CRC_SHIFT <= x"D2F6"; -- The CRC-CCITT for data x"A1A1A1F8" is x"D2F6" + elsif CRC_STRB = '1' then + -- CRC-CCITT (xFFFF): + -- the polynomial is G(x) = x^16 + x^12 + x^5 + 1 + -- In this mode the CRC is encoded. In read from disk mode, the encoding works as CRC + -- verification. In this operating condition the ID or the data field is compared + -- against the CRC checksum. if there are no errors, the shift register's value is + -- x"0000" after the last bit of the checksum is shifted in. In write to disk mode the + -- CRC linear feedback shift register (lfsr) works to generate the CRC remainder of the + -- ID or data field. + CRC_SHIFT <= CRC_SHIFT(14 downto 12) & (CRC_SHIFT(15) xor CRC_SHIFT(11) xor SD) & + CRC_SHIFT(10 downto 5) & (CRC_SHIFT(15) xor CRC_SHIFT(4) xor SD) & + CRC_SHIFT(3 downto 0) & (CRC_SHIFT(15) xor SD); + end if; + end process P_CRC; + + CRC_SDOUT <= CRC_SHIFT(15); + CRC_ERR <= '0' when CRC_SHIFT = x"0000" else '1'; +end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd new file mode 100644 index 0000000..95ce08c --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd @@ -0,0 +1,426 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- The digital PLL is responsible to detect the incoming serial ---- +---- data stream and provide a system clock synchronous signal ---- +---- containing the data and clock information. ---- +---- To understand how the code works in detail refer to the free ---- +---- US patent no. 4,780,844. ---- +---- ---- +---- Attention: The settings for TOP and BOTTOM, which control ---- +---- the PLL frequency and for PHASE_CORR which control the PLL ---- +---- phase are rather critical for a good read condition! To test ---- +---- the PLL in the WD1772 compatible core do the following: ---- +---- Sample on an oscilloscope on one channel the falling edge of ---- +---- the RDn pulse and on the other channel the PLL_DSTRB. The ---- +---- RDn must be located exactly between the PLL_DSTRB pulses. ---- +---- Otherwise, the parameters TOP, BOTTOM and PHASE_CORR have to ---- +---- be optimized. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release: the MFM portion for HD and DD floppies is tested. +-- The FM mode (DDEn = '1') is not completely tested due to lack of FM +-- drives. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K7B 2006/12/29 WF +-- Introduced several improvements based on a very good examination +-- of the pll code by Jean Louis-Guerin. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/12/24 WF +-- Improvement of the INPORT process. +-- Bugfix of the FREQ_AMOUNT counter: now stops if its value is zero. +-- Several changes concerning the PLL parameters to improve the +-- stability of the PLL. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_DIGITAL_PLL is + generic( + -- The valid range of the period counter of the PLL is given by the TOP and BOTTOM + -- limits. The counter range is therefore BOTTOM <= counter value <= TOP. + -- The generic PHASE_CORR is responsible fo the center setting of PLL_DSTRB concerning + -- the RDn period. + -- The nominal frequency setting is 128. So it is recommended to use TOP and BOTTOM + -- settings symmetrically around 128. If TOP = BOTTOM = 128, the frequency control + -- is disabled. TOP + PHASE_CORR may not exceed a value of 255. BOTTOM - PHASE_CORR + -- may not drop below zero. + TOP : integer range 0 to 255 := 152; -- +18.0% + BOTTOM : integer range 0 to 255 := 104; -- -18.0% + PHASE_CORR : integer range 0 to 128 := 75 + ); + port( + -- System control + CLK : in bit; -- 16MHz clock. + RESETn : in bit; + + -- Controls + DDEn : in bit; -- Double density enable. + HDTYPE : in bit; -- This control is '1' when HD disks are inserted. + DISK_RWn : in bit; -- Read write control. + + -- Data and clock lines + RDn : in bit; -- Read signal from the disk. + PLL_D : out bit; -- Synchronous read signal. + PLL_DSTRB : out bit -- Read strobe. + ); +end WF1772IP_DIGITAL_PLL; + +architecture BEHAVIOR of WF1772IP_DIGITAL_PLL is +signal RD_In : bit; +signal UP, DOWN : bit; +signal PHASE_DECREASE : bit; +signal PHASE_INCREASE : bit; +signal HI_STOP, LOW_STOP : bit; +signal PER_CNT : std_logic_vector(7 downto 0); +signal ADDER_IN : std_logic_vector(7 downto 0); +signal ADDER_MSBs : bit_vector(2 downto 0); +signal RD_PULSE : bit; +signal ROLL_OVER : bit; +signal HISTORY_REG : bit_vector(1 downto 0); +signal ERROR_HISTORY : integer range 0 to 2; +begin + INPORT: process + -- This process is necessary due to the poor quality of the rising + -- edge of RDn. Let it work on the negative clock edge. + begin + wait until CLK = '0' and CLK' event; + RD_In <= RDn; + end process INPORT; + + EDGEDETECT: process(RESETn, CLK) + -- This process forms a falling edge detector for the incoming + -- data read port. The output (RD_PULSE) goes high for exactly + -- one clock period after the RDn is low and the positive + -- clock edge is detected. + variable LOCK : boolean; + begin + if RESETn = '0' then + RD_PULSE <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if DISK_RWn = '0' then -- Disable detector in write mode. + RD_PULSE <= '0'; + elsif RD_In = '0' and LOCK = false then + RD_PULSE <= '1'; -- READ_PULSE is inverted against RDn + LOCK := true; + elsif RD_In = '1' then + LOCK := false; + RD_PULSE <= '0'; + else + RD_PULSE <= '0'; + end if; + end if; + end process EDGEDETECT; + + PERIOD_CNT: process(RESETn, CLK) + -- This process provides the nominal variable added to the adder. To achieve a good + -- settling time of the PLL in all cases, the period counter is controlled via the DDEn + -- and HDTYPE flags respective to its added value. Be aware, that in case of adding "10" + -- or "11", the TOP value may be exceeded or the period counter may drop below the BOTTOM + -- value. The higher the value added, the faster will be the settling time of phase locked + -- loop . + begin + if RESETn = '0' then + PER_CNT <= "10000000"; -- Initial value is 128. + elsif CLK = '1' and CLK' event then + if UP = '1' then + PER_CNT <= PER_CNT + '1'; + elsif DOWN = '1' then + PER_CNT <= PER_CNT - '1'; + end if; + end if; + end process PERIOD_CNT; + + HI_STOP <= '1' when PER_CNT >= TOP else '0'; + LOW_STOP <= '1' when PER_CNT <= BOTTOM else '0'; + + ADDER_IN <= -- This DISK_RWn = '0' implementation keeps the last phase information + -- of the PLL in read from disk mode. It should be a good solution concer- + -- ning alternative read write cycles. + "10000000" when DISK_RWn = '0' else -- Nominal value for write to disk. + PER_CNT + PHASE_CORR when PHASE_INCREASE = '1' else -- Phase lags. + PER_CNT - PHASE_CORR when PHASE_DECREASE = '1' else -- Phase leeds. + PER_CNT; -- No phase correction; + + ADDER: process(RESETn, CLK, DDEn, HDTYPE) + -- Clock adjustment: The clock cycle is 62.5ns for the 16MHz system clock. + -- The offset (LSBs) of the adder input is chosen to be conform with the required + -- rollover period in the different DDEn and HDTYPE modi as follows: + -- With a nominal adder input term of 128: + -- The adder rolls over every 4us for DDEn = 1 and HDTYPE = 0. + -- The adder rolls over every 2us for DDEn = 1 and HDTYPE = 1. + -- The adder rolls over every 2us for DDEn = 0 and HDTYPE = 0. + -- The adder rolls over every 1us for DDEn = 0 and HDTYPE = 1. + -- The given times are the half of a data period time in MFM or FM. + variable ADDER_DATA : std_logic_vector(12 downto 0); + begin + if RESETn = '0' then + ADDER_DATA := (others => '0'); + elsif CLK = '1' and CLK' event then + ADDER_DATA := ADDER_DATA + ADDER_IN; + end if; + -- + case DDEn & HDTYPE is + when "01" => -- MFM mode using HD disks, results in 1us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(10 downto 8)); + when "00" => -- MFM mode using DD disks, results in 2us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9)); + when "11" => -- FM mode using HD disks, results in 2us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9)); + when "10" => -- FM mode using DD disks, results in 4us inspection period: + ADDER_MSBs <= To_BitVector(ADDER_DATA(12 downto 10)); + end case; + end process ADDER; + + ROLLOVER: process(RESETn, CLK) + -- This process forms a falling edge detector for the detection + -- of the adder's rollover time. The output goes low for exactly + -- one clock period after the rollover is detected and the positive + -- clock edge appears. + variable LOCK : boolean; + begin + if RESETn = '0' then + ROLL_OVER <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if ADDER_MSBs /= "111" and LOCK = false then + ROLL_OVER <= '1'; + LOCK := true; + elsif ADDER_MSBs = "111" then + LOCK := false; + ROLL_OVER <= '0'; + else + ROLL_OVER <= '0'; + end if; + end if; + end process ROLLOVER; + PLL_DSTRB <= ROLL_OVER; + + DATA_FLIP_FLOP: process(RESETn, CLK, RD_PULSE) + -- This flip-flop is responsible for 'catching' the read pulses of the + -- serial data input. + begin + if RESETn = '0' then + PLL_D <= '0'; -- Asynchronous reset. + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' then + PLL_D <= '1'; -- Read pulse detected. + elsif ROLL_OVER = '1' then + PLL_D <= '0'; + end if; + end if; + end process DATA_FLIP_FLOP; + + WIN_HISTORY: process(RESETn, CLK) + begin + if RESETn = '0' then + HISTORY_REG <= "00"; + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' then + HISTORY_REG <= ADDER_MSBs(2) & HISTORY_REG(1); + end if; + end if; + end process WIN_HISTORY; + + -- Error history: + -- This signal indicates the number of consequtive levels of the adder's + -- MSB and the history register as shown in the following table. The default + -- setting of 0 was added to compile with the Xilinx ISE. + ERROR_HISTORY <= 2 when ADDER_MSBs(2) = '0' and HISTORY_REG = "00" else -- Speed strongly up. + 1 when ADDER_MSBs(2) = '0' and HISTORY_REG = "01" else -- Speed up. + 0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "10" else -- o.k. + 0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "11" else -- Now adjusted. + 0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "00" else -- Now adjusted. + 0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "01" else -- o.k. + 1 when ADDER_MSBs(2) = '1' and HISTORY_REG = "10" else -- Slow down. + 2 when ADDER_MSBs(2) = '1' and HISTORY_REG = "11" else 0; -- Slow strongly down. + + FREQUENCY_DECODER: process(RESETn, CLK, HI_STOP, LOW_STOP) + -- The frequency decoder controls the period of the data inspection window respective to the + -- ERROR_HISTORY for the 11 bit adder is as follows: + -- ERROR_HISTORY = 0: + -- -> no correction necessary <- + -- ERROR_HISTORY = 1: + -- MSBs input: 7 6 5 4 3 2 1 0 + -- Correction output: -3 -2 -1 0 0 +1 +2 +3 + -- ERROR_HISTORY = 2: + -- MSBs input: 7 6 5 4 3 2 1 0 + -- Correction output: -4 -3 -2 -1 +1 +2 +3 +4 + -- The most significant bit of the FREQ_AMOUNT controls incrementation or decrementation + -- of the adder (0 is up). + variable FREQ_AMOUNT: std_logic_vector(3 downto 0); + begin + if RESETn = '0' then + FREQ_AMOUNT := "0000"; + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' then -- Load the frequency amount register. + case ERROR_HISTORY is + when 2 => + case ADDER_MSBs is + when "000" => FREQ_AMOUNT := "0100"; + when "001" => FREQ_AMOUNT := "0011"; + when "010" => FREQ_AMOUNT := "0010"; + when "011" => FREQ_AMOUNT := "0001"; + when "100" => FREQ_AMOUNT := "1001"; + when "101" => FREQ_AMOUNT := "1010"; + when "110" => FREQ_AMOUNT := "1011"; + when "111" => FREQ_AMOUNT := "1100"; + end case; + when 1 => + case ADDER_MSBs is + when "000" => FREQ_AMOUNT := "0011"; + when "001" => FREQ_AMOUNT := "0010"; + when "010" => FREQ_AMOUNT := "0001"; + when "011" => FREQ_AMOUNT := "0000"; + when "100" => FREQ_AMOUNT := "1000"; + when "101" => FREQ_AMOUNT := "1001"; + when "110" => FREQ_AMOUNT := "1010"; + when "111" => FREQ_AMOUNT := "1011"; + end case; + when others => + FREQ_AMOUNT := "0000"; + end case; + elsif FREQ_AMOUNT(2 downto 0) > "000" then + FREQ_AMOUNT := FREQ_AMOUNT - '1'; -- Modify the frequency amount register. + end if; + end if; + -- + if FREQ_AMOUNT(3) = '0' and FREQ_AMOUNT(2 downto 0) /= "000" and HI_STOP = '0' then + -- FREQ_AMOUNT(3) = '0' means Frequency is too low. Count up when counter is not at HI_STOP. + UP <= '1'; + DOWN <= '0'; + elsif FREQ_AMOUNT(3) = '1' and FREQ_AMOUNT (2 downto 0) /= "000" and LOW_STOP = '0' then + -- FREQ_AMOUNT(3) = '1' means Frequency is too high. Count down when counter is not at LOW_STOP. + UP <= '0'; + DOWN <= '1'; + else + UP <= '0'; + DOWN <= '0'; + end if; + end process FREQUENCY_DECODER; + + PHASE_DECODER: process(RESETn, CLK) + -- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant bit + -- of PHASE_AMOUNT indicates with a '0', that the next rollover should appear earlier. In case of a + -- phase lag, the next rollover should come later (indicated by a '1' of the most significant bit of + -- PHASE_AMOUNT). + -- This implementation gives the freedom to adjust the phase amount individually for every mode + -- depending on DDEn and HDTYPE. + variable PHASE_AMOUNT: std_logic_vector(5 downto 0); + begin + if RESETn = '0' then + PHASE_AMOUNT := "000000"; + elsif CLK = '1' and CLK' event then + if RD_PULSE = '1' and DDEn = '1' and HDTYPE = '0' then -- FM mode, single density. + case ADDER_MSBs is -- Multiplier: 4. + when "000" => PHASE_AMOUNT := "010000"; + when "001" => PHASE_AMOUNT := "001101"; + when "010" => PHASE_AMOUNT := "001000"; + when "011" => PHASE_AMOUNT := "000100"; + when "100" => PHASE_AMOUNT := "100100"; + when "101" => PHASE_AMOUNT := "101000"; + when "110" => PHASE_AMOUNT := "101100"; + when "111" => PHASE_AMOUNT := "110000"; + end case; + elsif RD_PULSE = '1' and DDEn = '1' and HDTYPE = '1' then -- FM mode, double density + case ADDER_MSBs is -- Multiplier: 2. + when "000" => PHASE_AMOUNT := "001000"; + when "001" => PHASE_AMOUNT := "000110"; + when "010" => PHASE_AMOUNT := "000100"; + when "011" => PHASE_AMOUNT := "000010"; + when "100" => PHASE_AMOUNT := "100010"; + when "101" => PHASE_AMOUNT := "100100"; + when "110" => PHASE_AMOUNT := "100110"; + when "111" => PHASE_AMOUNT := "101000"; + end case; + elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '0' then -- MFM mode, single density + case ADDER_MSBs is -- Multiplier: 2. + when "000" => PHASE_AMOUNT := "000110"; + when "001" => PHASE_AMOUNT := "000100"; + when "010" => PHASE_AMOUNT := "000011"; + when "011" => PHASE_AMOUNT := "000010"; + when "100" => PHASE_AMOUNT := "100010"; + when "101" => PHASE_AMOUNT := "100011"; + when "110" => PHASE_AMOUNT := "100100"; + when "111" => PHASE_AMOUNT := "100110"; + end case; + elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '1' then -- MFM mode, double density. + case ADDER_MSBs is -- Multiplier: 1. + when "000" => PHASE_AMOUNT := "000100"; + when "001" => PHASE_AMOUNT := "000011"; + when "010" => PHASE_AMOUNT := "000010"; + when "011" => PHASE_AMOUNT := "000001"; + when "100" => PHASE_AMOUNT := "100001"; + when "101" => PHASE_AMOUNT := "100010"; + when "110" => PHASE_AMOUNT := "100011"; + when "111" => PHASE_AMOUNT := "100100"; + end case; + else -- Modify phase amount register: + if PHASE_AMOUNT(4 downto 0) > x"0" then + PHASE_AMOUNT := PHASE_AMOUNT - 1; + end if; + end if; + end if; + -- + if PHASE_AMOUNT(5) = '0' and PHASE_AMOUNT(4 downto 0) > x"0" then + -- PHASE_AMOUNT(5) = '0' means, that the phase leeds. + PHASE_INCREASE <= '1'; -- Speed phase up, accelerate next rollover. + PHASE_DECREASE <= '0'; + elsif PHASE_AMOUNT(5) = '1' and PHASE_AMOUNT(4 downto 0) > x"0" then + -- PHASE_AMOUNT(5) = '1' means, that the phase lags. + PHASE_INCREASE <= '0'; + PHASE_DECREASE <= '1'; -- Speed phase down, delay of next rollover. + else + PHASE_INCREASE <= '0'; + PHASE_DECREASE <= '0'; + end if; + end process PHASE_DECODER; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd new file mode 100644 index 0000000..b365b3d --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd @@ -0,0 +1,232 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This is the package file containing the component ---- +---- declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Removed CRC_BUSY. + + +library ieee; +use ieee.std_logic_1164.all; + +package WF1772IP_PKG is +-- component declarations: +component WF1772IP_AM_DETECTOR + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + DATA : in bit; + DATA_STRB : in bit; + ID_AM : out bit; + DATA_AM : out bit; + DDATA_AM : out bit + ); +end component; + +component WF1772IP_CONTROL + port( + CLK : in bit; + RESETn : in bit; + A1, A0 : in bit; + RWn : in bit; + CSn : in bit; + DDEn : in bit; + DR : in bit_vector(7 downto 0); + CMD : in std_logic_vector(7 downto 0); + DSR : in std_logic_vector(7 downto 0); + TR : in std_logic_vector(7 downto 0); + SR : in std_logic_vector(7 downto 0); + MO : out bit; + WR_PR : out bit; + SPINUP_RECTYPE : out bit; + SEEK_RNF : out bit; + CRC_ERRFLAG : out bit; + LOST_DATA_TR00 : out bit; + DRQ : out bit; + DRQ_IPn : out bit; + BUSY : out bit; + AM_2_DISK : out bit; + ID_AM : in bit; + DATA_AM : in bit; + DDATA_AM : in bit; + CRC_ERR : in bit; + CRC_PRES : out bit; + TR_PRES : out bit; + TR_CLR : out bit; + TR_INC : out bit; + TR_DEC : out bit; + SR_LOAD : out bit; + SR_INC : out bit; + TRACK_NR : out std_logic_vector(7 downto 0); + DR_CLR : out bit; + DR_LOAD : out bit; + SHFT_LOAD_SD : out bit; + SHFT_LOAD_ND : out bit; + CRC_2_DISK : out bit; + DSR_2_DISK : out bit; + FF_2_DISK : out bit; + PRECOMP_EN : out bit; + DATA_STRB : in bit; + DISK_RWn : out bit; + WPRTn : in bit; + TRACK00n : in bit; + IPn : in bit; + DIRC : out bit; + STEP : out bit; + WG : out bit; + INTRQ : out bit + ); +end component; + +component WF1772IP_CRC_LOGIC + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + DISK_RWn : in bit; + ID_AM : in bit; + DATA_AM : in bit; + DDATA_AM : in bit; + SD : in bit; + CRC_STRB : in bit; + CRC_2_DISK : in bit; + CRC_PRES : in bit; + CRC_SDOUT : out bit; + CRC_ERR : out bit + ); +end component; + +component WF1772IP_DIGITAL_PLL + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + HDTYPE : in bit; + DISK_RWn : in bit; + RDn : in bit; + PLL_D : out bit; + PLL_DSTRB : out bit + ); +end component; + +component WF1772IP_REGISTERS + port( + CLK : in bit; + RESETn : in bit; + CSn : in bit; + ADR : in bit_vector(1 downto 0); + RWn : in bit; + DATA_IN : in std_logic_vector (7 downto 0); + DATA_OUT : out std_logic_vector (7 downto 0); + DATA_EN : out bit; + CMD : out std_logic_vector(7 downto 0); + SR : out std_logic_vector(7 downto 0); + TR : out std_logic_vector(7 downto 0); + DSR : out std_logic_vector(7 downto 0); + DR : out bit_vector(7 downto 0); + SD_R : in bit; + DATA_STRB : in bit; + DR_CLR : in bit; + DR_LOAD : in bit; + TR_PRES : in bit; + TR_CLR : in bit; + TR_INC : in bit; + TR_DEC : in bit; + TRACK_NR : in std_logic_vector(7 downto 0); + SR_LOAD : in bit; + SR_INC : in bit; + SHFT_LOAD_SD : in bit; + SHFT_LOAD_ND : in bit; + MOTOR_ON : in bit; + WRITE_PROTECT : in bit; + SPINUP_RECTYPE : in bit; + SEEK_RNF : in bit; + CRC_ERRFLAG : in bit; + LOST_DATA_TR00 : in bit; + DRQ : in bit; + DRQ_IPn : in bit; + BUSY : in bit; + DDEn : in bit + ); +end component; + +component WF1772IP_TRANSCEIVER + port( + CLK : in bit; + RESETn : in bit; + DDEn : in bit; + HDTYPE : in bit; + ID_AM : in bit; + DATA_AM : in bit; + DDATA_AM : in bit; + SHFT_LOAD_SD : in bit; + DR : in bit_vector(7 downto 0); + PRECOMP_EN : in bit; + AM_TYPE : in bit; + AM_2_DISK : in bit; + CRC_2_DISK : in bit; + DSR_2_DISK : in bit; + FF_2_DISK : in bit; + SR_SDOUT : in std_logic; + CRC_SDOUT : in bit; + WRn : out bit; + PLL_DSTRB : in bit; + PLL_D : in bit; + WDATA : out bit; + DATA_STRB : out bit; + SD_R : out bit + ); +end component; +end WF1772IP_PKG; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd new file mode 100644 index 0000000..7556fe5 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd @@ -0,0 +1,264 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This file models all the five WD1772 registers: DATA-, ---- +---- COMMAND-, SECTOR-, TRACK- and STATUS register as also the ---- +---- shift register. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_REGISTERS is + port( + -- System control: + CLK : in bit; + RESETn : in bit; + + -- Bus interface: + CSn : in bit; + ADR : in bit_vector(1 downto 0); + RWn : in bit; + DATA_IN : in std_logic_vector (7 downto 0); + DATA_OUT : out std_logic_vector (7 downto 0); + DATA_EN : out bit; + + -- FDC data: + CMD : out std_logic_vector(7 downto 0); -- Command register. + SR : out std_logic_vector(7 downto 0); -- Sector register. + TR : out std_logic_vector(7 downto 0); -- Track register. + DSR : out std_logic_vector(7 downto 0); -- Data shift register. + DR : out bit_vector(7 downto 0); -- Data register. + + -- Serial data and clock strobes (in and out): + DATA_STRB : in bit; -- Strobe for the incoming data. + SD_R : in bit; -- Serial data input. + + -- DATA register control: + DR_CLR : in bit; -- Clear. + DR_LOAD : in bit; -- LOAD. + + -- Track register controls: + TR_PRES : in bit; -- Set x"FF". + TR_CLR : in bit; -- Clear. + TR_INC : in bit; -- Increment. + TR_DEC : in bit; -- Decrement. + + -- Sector register control: + TRACK_NR : in std_logic_vector(7 downto 0); + SR_LOAD : in bit; -- Load. + SR_INC : in bit; -- Increment. + + -- Shift register control: + SHFT_LOAD_SD : in bit; + SHFT_LOAD_ND : in bit; + + -- Status register stuff + MOTOR_ON : in bit; + WRITE_PROTECT : in bit; + SPINUP_RECTYPE : in bit; -- Disk is on speed / data mark status. + SEEK_RNF : in bit; -- Seek error / record not found status flag. + CRC_ERRFLAG : in bit; -- CRC status flag. + LOST_DATA_TR00 : in bit; + DRQ : in bit; + DRQ_IPn : in bit; + BUSY : in bit; + + -- Others: + DDEn : in bit + ); +end WF1772IP_REGISTERS; + +architecture BEHAVIOR of WF1772IP_REGISTERS is +-- Remark: In the original data sheet 'WD17X-00' there is the following statement: +-- "After any register is written to, the same register cannot be read from until +-- 16us in MFM or 32us in FMMM have elapsed." If this is a hint for a hardware read +-- lock ... this lock is not implemented in this code. +signal SHIFT_REG : std_logic_vector(7 downto 0); +signal DATA_REG : std_logic_vector(7 downto 0); +signal COMMAND_REG : std_logic_vector(7 downto 0); +signal SECTOR_REG : std_logic_vector(7 downto 0); +signal TRACK_REG : std_logic_vector(7 downto 0); +signal STATUS_REG : bit_vector(7 downto 0); +signal SD_R_I : std_logic; +begin + -- Type conversion To_Std_Logic: + SD_R_I <= '1' when SD_R = '1' else '0'; + + P_SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if SHFT_LOAD_ND = '1' then + SHIFT_REG <= DATA_REG; -- Load data register stuff. + elsif SHFT_LOAD_SD = '1' and DDEn = '1' then + SHIFT_REG <= DATA_REG; -- Normal data in FM mode. + elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode: + case DATA_REG is + when x"F5" => SHIFT_REG <= x"A1"; -- Special character. + when x"F6" => SHIFT_REG <= x"C2"; -- Special character. + when others => SHIFT_REG <= DATA_REG; -- Normal MFM data. + end case; + elsif DATA_STRB = '1' then -- Shift left during read from disk or write to disk. + SHIFT_REG <= SHIFT_REG(6 downto 0) & SD_R_I; -- for write operation SD_R_I is a dummy. + end if; + end if; + end process P_SHIFTREG; + DSR <= SHIFT_REG; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "11" and RWn = '0' then + DATA_REG <= DATA_IN; -- Write bus data to register + elsif DR_LOAD = '1' and DRQ = '0' then + DATA_REG <= SHIFT_REG; -- Correct data loaded to shift register. + elsif DR_LOAD = '1' and DRQ = '1' then + DATA_REG <= x"00"; -- Dummy byte due to lost data loaded to shift register. + elsif DR_CLR = '1' then + DATA_REG <= (others => '0'); + end if; + end if; + end process DATAREG; + -- Data register buffered for further data processing. + DR <= To_BitVector(DATA_REG); + + SECTORREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SECTOR_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "10" and RWn = '0' and BUSY = '0' then + SECTOR_REG <= DATA_IN; -- Write to register when device is not busy. + elsif SR_LOAD = '1' then + -- Load the track number to the sector register in the type III command + -- 'Read Address'. + SECTOR_REG <= TRACK_NR; + elsif SR_INC = '1' then + SECTOR_REG <= SECTOR_REG + '1'; + end if; + end if; + end process SECTORREG; + SR <= SECTOR_REG; + + TRACKREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TRACK_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "01" and RWn = '0' and BUSY = '0' then + TRACK_REG <= DATA_IN; -- Write to register when device is busy. + elsif TR_PRES = '1' then + TRACK_REG <= (others => '1'); -- Preset the track register. + elsif TR_CLR = '1' then + TRACK_REG <= (others => '0'); -- Reset the track register. + elsif TR_INC = '1' then + TRACK_REG <= TRACK_REG + '1'; -- Increment register contents. + elsif TR_DEC = '1' then + TRACK_REG <= TRACK_REG - '1'; -- Decrement register contents. + end if; + end if; + end process TRACKREG; + TR <= TRACK_REG; + + COMMANDREG: process(RESETn, CLK) + -- The command register is write only. + begin + if RESETn = '0' then + COMMAND_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if CSn = '0' and ADR = "00" and RWn = '0' and BUSY = '0' then + COMMAND_REG <= DATA_IN; -- Write to register when device is not busy. + -- Write 'force interrupt' to register even when device is busy: + elsif CSn = '0' and ADR = "00" and RWn = '0' and DATA_IN(7 downto 4) = x"D" then + COMMAND_REG <= DATA_IN; + end if; + end if; + end process COMMANDREG; + CMD <= COMMAND_REG; + + STATUSREG: process(RESETn, CLK) + -- The status register is read only to the data bus. + begin + -- Status register wiring: + if RESETn = '0' then + STATUS_REG <= x"00"; + elsif CLK = '1' and CLK' event then + STATUS_REG(7) <= MOTOR_ON; + STATUS_REG(6) <= WRITE_PROTECT; + STATUS_REG(5) <= SPINUP_RECTYPE; + STATUS_REG(4) <= SEEK_RNF; + STATUS_REG(3) <= CRC_ERRFLAG; + STATUS_REG(2) <= LOST_DATA_TR00; + STATUS_REG(1) <= DRQ_IPn; + STATUS_REG(0) <= BUSY; + end if; + end process STATUSREG; + -- Read from track, sector or data register: + -- The register data after writing to the track register is valid at least + -- after 32us in FM mode and after 16us in MFM mode. + -- Read from status register. This register is read only: + -- Be aware, that the status register data bits 7 to 1 after writing + -- the command regsiter are valid at least after 64us in FM mode or 32us in MFM mode and + -- the bit 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode. + DATA_OUT <= TRACK_REG when CSn = '0' and ADR = "01" and RWn = '1' else + SECTOR_REG when CSn = '0' and ADR = "10" and RWn = '1' else + DATA_REG when CSn = '0' and ADR = "11" and RWn = '1' else + To_StdLogicVector(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0'); + DATA_EN <= '1' when CSn = '0' and RWn = '1' else '0'; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd new file mode 100644 index 0000000..71ef3f3 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd @@ -0,0 +1,154 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- This is the top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - Test of the FM portion of the code (if there is any need). ---- +---- - Test of the read track command. ---- +---- - Test of the read address command. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release: the MFM portion for HD and DD floppies is tested. +-- The FM mode (DDEn = '1') is not completely tested due to the lack +-- of FM drives. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Fixed the polarity of the precompensation flag. +-- The flag is no active '0'. Thanks to Jorma +-- Oksanen for the information. +-- Revision 2K7B 2006/12/29 WF +-- Introduced several improvements based on a very good examination +-- of the pll code by Jean Louis-Guerin. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. + +library work; +use work.WF1772IP_PKG.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_TOP is + port ( + CLK : in bit; -- 16MHz clock! + MRn : in bit; + CSn : in bit; + RWn : in bit; + A1, A0 : in bit; + DATA : inout std_logic_vector(7 downto 0); + RDn : in bit; + TR00n : in bit; + IPn : in bit; + WPRTn : in bit; + DDEn : in bit; + HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks. + MO : out bit; + WG : out bit; + WD : out bit; + STEP : out bit; + DIRC : out bit; + DRQ : out bit; + INTRQ : out bit + ); +end entity WF1772IP_TOP; + +architecture STRUCTURE of WF1772IP_TOP is +component WF1772IP_TOP_SOC + port ( + CLK : in bit; + RESETn : in bit; + CSn : in bit; + RWn : in bit; + A1, A0 : in bit; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + RDn : in bit; + TR00n : in bit; + IPn : in bit; + WPRTn : in bit; + DDEn : in bit; + HDTYPE : in bit; + MO : out bit; + WG : out bit; + WD : out bit; + STEP : out bit; + DIRC : out bit; + DRQ : out bit; + INTRQ : out bit + ); +end component; +signal DATA_OUT : std_logic_vector(7 downto 0); +signal DATA_EN : bit; +begin + DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); + + I_1772: WF1772IP_TOP_SOC + port map( + CLK => CLK, + RESETn => MRn, + CSn => CSn, + RWn => RWn, + A1 => A1, + A0 => A0, + DATA_IN => DATA, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + RDn => RDn, + TR00n => TR00n, + IPn => IPn, + WPRTn => WPRTn, + DDEn => DDEn, + HDTYPE => HDTYPE, + MO => MO, + WG => WG, + WD => WD, + STEP => STEP, + DIRC => DIRC, + DRQ => DRQ, + INTRQ => INTRQ + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd new file mode 100644 index 0000000..9cfd111 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd @@ -0,0 +1,333 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - Test of the FM portion of the code (if there is any need). ---- +---- - Test of the read track command. ---- +---- - Test of the read address command. ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release: the MFM portion for HD and DD floppies is tested. +-- The FM mode (DDEn = '1') is not completely tested due to the lack +-- of FM drives. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Fixed the polarity of the precompensation flag. +-- The flag is no active '0'. Thanks to Jorma Oksanen for the information. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K7B 2006/12/29 WF +-- Introduced several improvements based on a very good examination +-- of the pll code by Jean Louis-Guerin. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/12/24 WF +-- Bugfixes in the controller due to hanging state machine. +-- Removed CRC_BUSY. +-- + +library work; +use work.WF1772IP_PKG.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_TOP_SOC is + port ( + CLK : in bit; -- 16MHz clock! + RESETn : in bit; + CSn : in bit; + RWn : in bit; + A1, A0 : in bit; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + RDn : in bit; + TR00n : in bit; + IPn : in bit; + WPRTn : in bit; + DDEn : in bit; + HDTYPE : in bit; -- '0' = DD disks, '1' = HD disks. + MO : out bit; + WG : out bit; + WD : out bit; + STEP : out bit; + DIRC : out bit; + DRQ : out bit; + INTRQ : out bit + ); +end entity WF1772IP_TOP_SOC; + +architecture STRUCTURE of WF1772IP_TOP_SOC is +signal DATA_OUT_REG : std_logic_vector(7 downto 0); +signal DATA_EN_REG : bit; +signal CMD_I : std_logic_vector(7 downto 0); +signal DR_I : bit_vector(7 downto 0); +signal DSR_I : std_logic_vector(7 downto 0); +signal TR_I : std_logic_vector(7 downto 0); +signal SR_I : std_logic_vector(7 downto 0); +signal ID_AM_I : bit; +signal DATA_AM_I : bit; +signal DDATA_AM_I : bit; +signal AM_TYPE_I : bit; +signal AM_2_DISK_I : bit; +signal DATA_STRB_I : bit; +signal BUSY_I : bit; +signal DRQ_I : bit; +signal DRQ_IPn_I : bit; +signal LD_TR00_I : bit; +signal SP_RT_I : bit; +signal SEEK_RNF_I : bit; +signal WR_PR_I : bit; +signal MO_I : bit; +signal PLL_DSTRB_I : bit; +signal PLL_D_I : bit; +signal CRC_SD_I : bit; +signal CRC_ERR_I : bit; +signal CRC_PRES_I : bit; +signal CRC_ERRFLAG_I : bit; +signal SD_R_I : bit; +signal CRC_SDOUT_I : bit; +signal SHFT_LOAD_SD_I : bit; +signal SHFT_LOAD_ND_I : bit; +signal WR_In : bit; +signal TR_PRES_I : bit; +signal TR_CLR_I : bit; +signal TR_INC_I : bit; +signal TR_DEC_I : bit; +signal SR_LOAD_I : bit; +signal SR_INC_I : bit; +signal DR_CLR_I : bit; +signal DR_LOAD_I : bit; +signal TRACK_NR_I : std_logic_vector(7 downto 0); +signal CRC_2_DISK_I : bit; +signal DSR_2_DISK_I : bit; +signal FF_2_DISK_I : bit; +signal PRECOMP_EN_I : bit; +signal DISK_RWn_I : bit; +signal WDATA_I : bit; +begin + -- Three state data bus: + DATA_OUT <= DATA_OUT_REG when DATA_EN_REG = '1' else (others => '0'); + DATA_EN <= DATA_EN_REG; + + -- Some signals copied to the outputs: + WD <= not WR_In; + MO <= MO_I; + DRQ <= DRQ_I; + + -- Write deleted data address mark in MFM mode in 'Write Sector' command in + -- case of asserted command bit 0. + AM_TYPE_I <= '0' when CMD_I(7 downto 5) = "101" and CMD_I(0) = '1' else '1'; + + -- The CRC unit is used during read from disk and write to disk. + -- This is the data multiplexer for the data stream to encode. + CRC_SD_I <= SD_R_I when DISK_RWn_I = '1' else WDATA_I; + + I_CONTROL: WF1772IP_CONTROL + port map( + CLK => CLK, + RESETn => RESETn, + A1 => A0, + A0 => A1, + RWn => RWn, + CSn => CSn, + DDEn => DDEn, + DR => DR_I, + CMD => CMD_I, + DSR => DSR_I, + TR => TR_I, + SR => SR_I, + MO => MO_I, + WR_PR => WR_PR_I, + SPINUP_RECTYPE => SP_RT_I, + SEEK_RNF => SEEK_RNF_I, + CRC_ERRFLAG => CRC_ERRFLAG_I, + LOST_DATA_TR00 => LD_TR00_I, + DRQ => DRQ_I, + DRQ_IPn => DRQ_IPn_I, + BUSY => BUSY_I, + AM_2_DISK => AM_2_DISK_I, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I, + CRC_ERR => CRC_ERR_I, + CRC_PRES => CRC_PRES_I, + TR_PRES => TR_PRES_I, + TR_CLR => TR_CLR_I, + TR_INC => TR_INC_I, + TR_DEC => TR_DEC_I, + SR_LOAD => SR_LOAD_I, + SR_INC => SR_INC_I, + TRACK_NR => TRACK_NR_I, + DR_CLR => DR_CLR_I, + DR_LOAD => DR_LOAD_I, + SHFT_LOAD_SD => SHFT_LOAD_SD_I, + SHFT_LOAD_ND => SHFT_LOAD_ND_I, + CRC_2_DISK => CRC_2_DISK_I, + DSR_2_DISK => DSR_2_DISK_I, + FF_2_DISK => FF_2_DISK_I, + PRECOMP_EN => PRECOMP_EN_I, + DATA_STRB => DATA_STRB_I, + DISK_RWn => DISK_RWn_I, + WPRTn => WPRTn, + TRACK00n => TR00n, + IPn => IPn, + DIRC => DIRC, + STEP => STEP, + WG => WG, + INTRQ => INTRQ + ); + + I_REGISTERS: WF1772IP_REGISTERS + port map( + CLK => CLK, + RESETn => RESETn, + CSn => CSn, + ADR(1) => A1, + ADR(0) => A0, + RWn => RWn, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT_REG, + DATA_EN => DATA_EN_REG, + CMD => CMD_I, + TR => TR_I, + SR => SR_I, + DSR => DSR_I, + DR => DR_I, + SD_R => SD_R_I, + DATA_STRB => DATA_STRB_I, + DR_CLR => DR_CLR_I, + DR_LOAD => DR_LOAD_I, + TR_PRES => TR_PRES_I, + TR_CLR => TR_CLR_I, + TR_INC => TR_INC_I, + TR_DEC => TR_DEC_I, + TRACK_NR => TRACK_NR_I, + SR_LOAD => SR_LOAD_I, + SR_INC => SR_INC_I, + SHFT_LOAD_SD => SHFT_LOAD_SD_I, + SHFT_LOAD_ND => SHFT_LOAD_ND_I, + MOTOR_ON => MO_I, + WRITE_PROTECT => WR_PR_I, + SPINUP_RECTYPE => SP_RT_I, + SEEK_RNF => SEEK_RNF_I, + CRC_ERRFLAG => CRC_ERRFLAG_I, + LOST_DATA_TR00 => LD_TR00_I, + DRQ => DRQ_I, + DRQ_IPn => DRQ_IPn_I, + BUSY => BUSY_I, + DDEn => DDEn + ); + + I_DIGITAL_PLL: WF1772IP_DIGITAL_PLL + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + HDTYPE => HDTYPE, + DISK_RWn => DISK_RWn_I, + RDn => RDn, + PLL_D => PLL_D_I, + PLL_DSTRB => PLL_DSTRB_I + ); + + I_AM_DETECTOR: WF1772IP_AM_DETECTOR + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + DATA => PLL_D_I, + DATA_STRB => PLL_DSTRB_I, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I + ); + + I_CRC_LOGIC: WF1772IP_CRC_LOGIC + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + DISK_RWn => DISK_RWn_I, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I, + SD => CRC_SD_I, + CRC_STRB => DATA_STRB_I, + CRC_2_DISK => CRC_2_DISK_I, + CRC_PRES => CRC_PRES_I, + CRC_SDOUT => CRC_SDOUT_I, + CRC_ERR => CRC_ERR_I + ); + + I_TRANSCEIVER: WF1772IP_TRANSCEIVER + port map( + CLK => CLK, + RESETn => RESETn, + DDEn => DDEn, + HDTYPE => HDTYPE, + ID_AM => ID_AM_I, + DATA_AM => DATA_AM_I, + DDATA_AM => DDATA_AM_I, + SHFT_LOAD_SD => SHFT_LOAD_SD_I, + DR => DR_I, + PRECOMP_EN => PRECOMP_EN_I, + AM_TYPE => AM_TYPE_I, + AM_2_DISK => AM_2_DISK_I, + CRC_2_DISK => CRC_2_DISK_I, + DSR_2_DISK => DSR_2_DISK_I, + FF_2_DISK => FF_2_DISK_I, + SR_SDOUT => DSR_I(7), + CRC_SDOUT => CRC_SDOUT_I, + WRn => WR_In, + WDATA => WDATA_I, + PLL_DSTRB => PLL_DSTRB_I, + PLL_D => PLL_D_I, + DATA_STRB => DATA_STRB_I, + SD_R => SD_R_I + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd new file mode 100644 index 0000000..c836716 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd @@ -0,0 +1,517 @@ +---------------------------------------------------------------------- +---- ---- +---- WD1772 compatible floppy disk controller IP Core. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Floppy disk controller with all features of the Western ---- +---- Digital WD1772-02 controller. ---- +---- ---- +---- The transceiver unit contains on the one hand the receiver ---- +---- part which strips off the clock signal from the data stream ---- +---- and on the other hand the transmitter unit which provides in ---- +---- the different modes (FM and MFM) all functions which are ---- +---- necessary to send data, CRC bytes, 'FF', '00' or the address ---- +---- marks. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2006A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/05 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- MFM_In and MASK_SHFT have now synchronous reset to meet preset requirement. +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF1772IP_TRANSCEIVER is + port( + -- System control + CLK : in bit; -- must be 16MHz + RESETn : in bit; + + -- Data and Control: + HDTYPE : in bit; -- Floppy type HD or DD. + DDEn : in bit; -- Double density select (FM or MFM). + ID_AM : in bit; -- ID addressmark strobe. + DATA_AM : in Bit; -- Data addressmark strobe. + DDATA_AM : in Bit; -- Deleted data addressmark strobe. + SHFT_LOAD_SD : in bit; -- Indication for shift register load time. + DR : in bit_vector(7 downto 0); -- Content of the data register. + + -- Data strobes: + PLL_DSTRB : in bit; -- Clock strobe for RD serial data input. + DATA_STRB : buffer bit; + + -- Data strobe and data for the CRC during write operation: + WDATA : buffer bit; + + -- Encoder (logic to disk): + PRECOMP_EN : in bit; -- control signal for MFM write precompensation. + AM_TYPE : in bit; -- Write deleted address mark in MFM mode when 0. + AM_2_DISK : in bit; + DSR_2_DISK : in bit; + FF_2_DISK : in bit; + CRC_2_DISK : in bit; + SR_SDOUT : in std_logic; -- encoder's data input from the shift register (serial). + CRC_SDOUT : in bit; -- encoder's data input from the CRC unit (serial). + WRn : out bit; -- write output for the MFM drive containing clock and data. + + -- Decoder (disk to logic): + PLL_D : in bit; -- Serial data input. + SD_R : out bit -- Serial (decoded) data output. + ); +end WF1772IP_TRANSCEIVER; + +architecture BEHAVIOR of WF1772IP_TRANSCEIVER is +type MFM_STATES is (A_00, B_01, C_10); +type PRECOMP_VALUES is (EARLY, NOMINAL, LATE); +type DEC_STATES is (CLK_PHASE, DATA_PHASE); + +signal MFM_STATE : MFM_STATES; +signal NEXT_MFM_STATE : MFM_STATES; +signal PRECOMP : PRECOMP_VALUES; +signal DEC_STATE : DEC_STATES; +signal NEXT_DEC_STATE : DEC_STATES; + +signal FM_In : bit; + +signal CLKMASK : bit; -- Control for suppression of FM clock transitions. + +signal MFM_10_STRB : bit; +signal MFM_01_STRB : bit; + +signal WR_CNT : std_logic_vector(3 downto 0); +signal MFM_In : bit; + +signal AM_SHFT : bit_vector(31 downto 0); + +begin + -- ####################### encoder stuff ########################### + ADRMARK: process(RESETn, CLK) + -- This process provides the address mark data for both FM and MFM in + -- write to disk mode. In FM only one byte is written where in MFM + -- 3 sync bytes x"A1" and one data address mark is written. + -- In this process only the data address mark is provided. The only way + -- writing the ID address mark is the write track command. + begin + if RESETn = '0' then + AM_SHFT <= (others => '0'); + elsif CLK = '1' and CLK' event then + if AM_2_DISK = '1' and DATA_STRB = '1' then + AM_SHFT <= AM_SHFT (30 downto 0) & '0'; -- Shift out. + elsif AM_2_DISK = '0' and DDEn = '1' and AM_TYPE = '0' then -- FM mode. + AM_SHFT <= x"F8000000"; -- Load deleted FM address mark. + elsif AM_2_DISK = '0' and DDEn = '1' and AM_TYPE = '1' then -- FM mode. + AM_SHFT <= x"FB000000"; -- Load normal FM address mark. + elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '0' then -- MFM mode deleted data mark. + AM_SHFT <= x"A1A1A1F8"; -- Load MFM syncs and address mark. + elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '1' then -- Default: MFM mode normal data mark. + AM_SHFT <= x"A1A1A1FB"; -- Load MFM syncs and address mark. + end if; + end if; + end process ADRMARK; + + -- Input multiplexer: + WDATA <= AM_SHFT(31) when AM_2_DISK = '1' else -- Address mark data data. + To_Bit(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data. + CRC_SDOUT when CRC_2_DISK = '1' else -- CRC data. + '1' when FF_2_DISK = '1' else '0'; -- Write zeros is default. + + -- Output multiplexer: + WRn <= '0' when FM_In = '0' and DDEn = '1' else -- FM portion. + '0' when MFM_In = '0' and DDEn = '0' else '1'; -- MFM portion and default. + + CLK_MASK: process(CLK) + -- This part of software controls the suppression of the clock pulses + -- during transmission of several FM special characters. During writing + -- 'normal' data to the disk, only 8 mask bits of the shift register are + -- used. During writing MFM sync and address mark bits, the register is + -- used with 32 mask bits. + variable MASK_SHFT : bit_vector(23 downto 0); + variable LOCK : boolean; + begin + if CLK = '1' and CLK' event then + if RESETn = '0' then + MASK_SHFT := (others => '1'); + LOCK := false; + -- Load the mask shift register just in time when the shift register is + -- loaded with valid data from the data register. + elsif SHFT_LOAD_SD = '1' and DDEn = '1' then -- FM mode. + case DR is + when x"F8" | x"F9" | x"FA" | x"FB" | x"FE" => MASK_SHFT := x"C7FFFF"; + when x"FC" => MASK_SHFT := x"D7FFFF"; + when x"F5" | x"F6" => MASK_SHFT := (others => '0'); -- Not allowed. + when others => MASK_SHFT := x"FFFFFF"; -- Normal data. + end case; + elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode. + case DR is + when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between bits 4 and 5. + when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between bits 3 and 4. + when others => MASK_SHFT := x"FFFFFF"; -- Normal data. + end case; + elsif AM_2_DISK = '1' and DDEn = '1' and LOCK = false then -- FM mode. + MASK_SHFT := x"C7FFFF"; -- Load just once per AM_2_DISK rising edge. + LOCK := true; + elsif AM_2_DISK = '1' and DDEn = '0' and LOCK = false then -- MFM mode. + MASK_SHFT := x"FBFBFB"; -- Three syncs with suppressed clock pulse then transparent mask. + LOCK := true; + elsif DATA_STRB = '1' then -- shift as long as transmission is active + -- The Shift register is shifted left. After shifting the clockmasks out it is + -- transparent due to the '1's filled up from the left. + MASK_SHFT := MASK_SHFT(22 downto 0) & '1'; -- Shift left. + elsif AM_2_DISK = '0' then + LOCK := false; -- Release the lock after address mark has been written. + end if; + end if; + CLKMASK <= MASK_SHFT(23); + end process CLK_MASK; + + FM_ENCODER: process (RESETn, DATA_STRB, CLK) + -- For DD type floppies the data rate is 125kBps. Therefore there are 128 16-MHz clocks cycles + -- per FM bit. + -- For HD type floppies the data rate is 250kBps. Therefore there are 64 16-MHz clocks cycles + -- per FM bit. + -- The FM write pulse width is 1.375us for DD and 0.750us HD type floppies. + -- This process provides the FM encoded signal. The first pulse is in any case the clock + -- pulse and the second pulse is due to data. The FM encoding is very simple and therefore + -- self explaining. + variable CNT : std_logic_vector(7 downto 0); + begin + if RESETn = '0' then + FM_In <= '1'; + CNT := x"00"; + elsif CLK = '1' and CLK' event then + -- In case of HD type floppies the counter reaches a value of b"0100000" + -- In case of DD type floppies the counter reaches a value of b"1000000" + if DATA_STRB = '1' then + CNT := x"00"; + else + CNT := CNT + '1'; + end if; + -- The flux reversal pulses are centered between the DATA_STRB pulses. + -- In detail: the clock pulse appears in the middle of the first half + -- of the DATA_STRB period and the data pulse appears in the middle of + -- the second half. + case HDTYPE is + when '0' => -- DD type floppies: + if CNT > "00010101" and CNT <= "00101011" then + FM_In <= not CLKMASK; -- FM clock. + elsif CNT > "01010101" and CNT <= "01101011" then + FM_In <= not WDATA; -- FM data. + else + FM_In <= '1'; + end if; + when '1' => -- HD type floppies: + if CNT > "00001010" and CNT <= "00010110" then + FM_In <= not CLKMASK; -- FM clock. + elsif CNT > "00101010" and CNT <= "00110110" then + FM_In <= not WDATA; -- FM data. + else + FM_In <= '1'; + end if; + end case; + end if; + end process FM_ENCODER; + + MFM_ENCODE_REG: process(RESETn, CLK) + -- This process is the first portion of the more complicated MFM encoder. It can be interpreted + -- as a Moore machine. This part is the current state register. + begin + if RESETn = '0' then + MFM_STATE <= A_00; + elsif CLK = '1' and CLK' event then + MFM_STATE <= NEXT_MFM_STATE; + end if; + end process MFM_ENCODE_REG; + + MFM_ENCODE_LOGIC: process(MFM_STATE, WDATA, DATA_STRB) + -- Rules for Encoding: + -- transitions are never located at the mid point of a 'zero'. + -- transistions are always located at the mid point of a '1'. + -- no transitions at the borders of a '1'. + -- transitions appear between two adjacent 'zeros'. + -- states are as follows: + -- A_00: idle state, no transition. + -- B_01: transistion between the MFM clock edges. + -- C_10: transition on the leading MFM clock edges. + -- The timing of the MFM output is done in the process MFM_WR_OUT. + begin + case MFM_STATE is + when A_00 => + if WDATA = '0' and DATA_STRB = '1' then + NEXT_MFM_STATE <= C_10; + elsif WDATA = '1' and DATA_STRB = '1' then + NEXT_MFM_STATE <= B_01; + else + NEXT_MFM_STATE <= A_00; -- Stay, if there is no strobe. + end if; + when C_10 => + if WDATA = '0' and DATA_STRB = '1' then + NEXT_MFM_STATE <= C_10; + elsif WDATA = '1' and DATA_STRB = '1' then + NEXT_MFM_STATE <= B_01; + else + NEXT_MFM_STATE <= C_10; -- Stay, if there is no strobe. + end if; + when B_01 => + if WDATA = '0' and DATA_STRB = '1' then + NEXT_MFM_STATE <= A_00; + elsif WDATA = '1' and DATA_STRB = '1' then + NEXT_MFM_STATE <= B_01; + else + NEXT_MFM_STATE <= B_01; -- Stay, if there is no strobe. + end if; + end case; + end process MFM_ENCODE_LOGIC; + + MFM_PRECOMPENSATION: process(RESETn, CLK) + -- The write pattern is adjusted in the MFM write timing process as follows: + -- after DATA_STRB (the duty cycle of this strobe is exactly one CLK) the + -- incoming data is bufferd in WRITEPATTERN. After the following DATA_STRB + -- the WDATA is shifted through WRITEPATTERN. After further DATA_STRBs the + -- WRITEPATTERN consists of previous, current and next WDATA like this: + -- WRITEPATTERN(3) is the second previous WDATA. + -- WRITEPATTERN(2) is the previous WDATA. + -- WRITEPATTERN(1) is the current WDATA to be sent. + -- WRITEPATTERN(0) is the next WDATA to be sent. + variable WRITEPATTERN : bit_vector(3 downto 0); + begin + if RESETn = '0' then + PRECOMP <= NOMINAL; + WRITEPATTERN := "0000"; + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + WRITEPATTERN := WRITEPATTERN(2 downto 0) & WDATA; -- shift left + end if; + if PRECOMP_EN = '0' then + PRECOMP <= NOMINAL; -- no precompensation + else + case WRITEPATTERN is + when "1110" | "0110" => PRECOMP <= EARLY; + when "1011" | "0011" => PRECOMP <= LATE; + when "0001" => PRECOMP <= EARLY; + when "1000" => PRECOMP <= LATE; + when others => PRECOMP <= NOMINAL; + end case; + end if; + end if; + end process MFM_PRECOMPENSATION; + + MFM_STROBES: process (RESETn, DATA_STRB, CLK) + -- For the MFM frequency is 250 kBps for DD type floppies, there are 64 + -- 16 MHz clock cycles per MFM bit and for HD type floppies, which have + -- 500 kBps there are 32 16MHz clock pulses for one MFM bit. + -- The MFM state machine (Moore) switches on the DATA_STRB. + -- During one cycle there are the two further strobes MFM_10_STRB and + -- MFM_01_STRB which control the MFM output in the process MFM_WR_OUT. + -- The strobes are centered in the middle of the first half and in the + -- middle of the second half of the DATA_STRB cycle. + variable CNT : std_logic_vector(5 downto 0); + begin + if RESETn = '0' then + CNT := "000000"; + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + CNT := (others => '0'); + else + CNT := CNT + '1'; + end if; + if HDTYPE = '1' then + case CNT is + -- encoder timing for MFM and HD type floppies. + when "000100" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half. + when "010100" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half. + when others => MFM_10_STRB <= '0'; MFM_01_STRB <= '0'; + end case; + else + case CNT is + -- encoder timing for MFM and DD type floppies. + when "001010" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half. + when "101000" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half. + when others => MFM_10_STRB <= '0'; MFM_01_STRB <= '0'; + end case; + end if; + end if; + end process MFM_STROBES; + + -- MFM_WR_TIMING generates the timing for the write pulses which are + -- required by a MFM device like floppy disk drive. The pulse timing + -- meets the timing of the MFM data with pulse width of 700ns +/- 100ns + -- depending on write precompensation. + -- The original WD1772 (CLK = 8MHz) data timing was as follows: + -- The output is asserted as long as CNT is active; in detail + -- this are 4,5; 5,5 or 6,5 CLK cycles depending on the write + -- precompensation. + -- The new design which works with a 16MHz clock requires the following + -- timing: 9; 11 or 13 CLK cycles depending on the writeprecompensation + -- for DD floppies and 5; 6 or 7 CLK cycles depending on the write + -- precompensation for HD floppies. + -- To meet the timing requirements of half clocks + -- the WRn is controlled by the following three processes where the one + -- syncs on the positive clock edge and the other on the negative. + -- For more information on the WTn timing see the datasheet of the + -- WD177x floppy disc controller. + + MFM_WR_TIMING: process(RESETn, CLK) + variable CLKMASK_MFM : bit; + begin + if RESETn = '0' then + WR_CNT <= x"F"; + elsif CLK = '1' and CLK' event then + if DATA_STRB = '1' then + -- The CLKMASK_MFM is synchronised to DATA_STRB. This brings one strobe latency. + -- The timing in connection with the data is correct because the MFM encoder state machine + -- causes the data to be 1 DATA_STRB late too. + CLKMASK_MFM := CLKMASK; + end if; + if MFM_STATE = C_10 and MFM_10_STRB = '1' and CLKMASK_MFM = '1' then + WR_CNT <= x"0"; + elsif MFM_STATE = B_01 and MFM_01_STRB = '1' then + WR_CNT <= x"0"; + elsif WR_CNT < x"F" then + WR_CNT <= WR_CNT + '1'; + end if; + end if; + end process MFM_WR_TIMING; + + MFM_WR_OUT: process + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + MFM_In <= '1'; + else + case HDTYPE is + when '1' => -- HD type. + if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"9" then + MFM_In <= '0'; -- 9,0 clock cycles for WRn --> early timing + elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"8" then + MFM_In <= '0'; -- 8,0 clock cycles for WRn --> nominal timing + elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"7" then + MFM_In <= '0'; -- 7,0 clock cycles for WRn --> late timing + else + MFM_In <= '1'; + end if; + when '0' => -- DD type. + if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"D" then + MFM_In <= '0'; -- 13,0 clock cycles for WRn --> early timing + elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"B" then + MFM_In <= '0'; -- 11,0 clock cycles for WRn --> nominal timing + elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"9" then + MFM_In <= '0'; -- 9,0 clock cycles for WRn --> late timing + else + MFM_In <= '1'; + end if; + end case; + end if; + end process MFM_WR_OUT; + + -- ####################### Decoder stuff ########################### + -- The decoding of the serial FM or MFM encoded data stream + -- is done in the following two processes (Moore machine). + -- The decoder works in principle like a simple toggle Flip-Flop. + -- It is important to synchronise it in a way, that the clock + -- pulses are separated from the data pulses. The principle + -- works for both FM and MFM data due to the digital phase + -- locked loop, which delivers the serial data and the clock + -- strobe. In general this decoder can be understood as the + -- data separator where the digital phase locked loop provides + -- the FM or the MFM decoding. The data separation lives from + -- the fact, that FM and also MFM encoded signals consist of a + -- mixture of alternating data and clock pulses. + -- FM works as follows: + -- every first pulse of the FM signal is a clock pulse and every + -- second pulse is a logic '1' of the data. A missing second + -- pulse represents a logic '0' of the data. + -- MFM works as follows: + -- every first pulse of the MFM signal is a clock pulse. The coding + -- principle causes clock pulses to be absent in some conditions. + -- Every second pulse is a logic '1' of the data. A missing second + -- pulse represents a logic '0' of the data. + -- So FM and MFM compared, the data is represented directly by the + -- second pulses and the data separator has to look only for these. + -- The missing MFM clock pulses do not cause a problem because the + -- digital PLL used in conjunction with this data separator fills + -- up the clock pulses and delivers a PLL_DSTRB containing aequidistant + -- clock strobes and data strobes. + + DEC_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + DEC_STATE <= CLK_PHASE; + elsif CLK = '1' and CLK' event then + DEC_STATE <= NEXT_DEC_STATE; + end if; + end process DEC_REG; + + DEC_LOGIC: process(DEC_STATE, ID_AM, DATA_AM, DDATA_AM, PLL_DSTRB, PLL_D) + begin + case DEC_STATE is + when CLK_PHASE => + if PLL_DSTRB = '1' then + NEXT_DEC_STATE <= DATA_PHASE; + else + NEXT_DEC_STATE <= CLK_PHASE; + end if; + DATA_STRB <= '0'; -- Inactive during clock pulse time. + SD_R <= '0'; -- Inactive during clock pulse time. + when DATA_PHASE => + if ID_AM = '1' or DATA_AM = '1' or DDATA_AM = '1' then + -- Here the state machine is synchronised + -- to separate data and clock pulses correctly. + NEXT_DEC_STATE <= CLK_PHASE; + elsif PLL_DSTRB = '1' then + NEXT_DEC_STATE <= CLK_PHASE; + else + NEXT_DEC_STATE <= DATA_PHASE; + end if; + -- During the data phase valid data appears at SD. + -- The data is valid during DATA_STRB. + DATA_STRB <= PLL_DSTRB; + SD_R <= PLL_D; + end case; + end process DEC_LOGIC; +end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd new file mode 100644 index 0000000..7660aa2 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd @@ -0,0 +1,141 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This are the SUSKA MFP IP core's general purpose I/Os. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_GPIO is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Timer controls: + AER_4 : out bit; + AER_3 : out bit; + + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_OUT_EN : buffer bit_vector(7 downto 0); + GP_INT : out bit_vector(7 downto 0) + ); +end entity WF68901IP_GPIO; + +architecture BEHAVIOR of WF68901IP_GPIO is +signal GPDR : bit_vector(7 downto 0); +signal DDR : bit_vector(7 downto 0); +signal AER : bit_vector(7 downto 0); +signal GPDR_I : bit_vector(7 downto 0); +begin + -- These two bits control the timers A and B pulse width operation and the + -- timers A and B event count operation. + AER_4 <= AER(4); + AER_3 <= AER(3); + -- This statement provides 8 XOR units setting the desired interrupt polarity. + -- While the level control is done here, the edge triggering is provided by + -- the interrupt control hardware. The level control is individually for each + -- GPIP port pin. The interrupt edge trigger unit must operate in any case on + -- the low to high transistion of the respective port pin. + GP_INT <= AER xnor GPIP_IN; + + GPIO_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + GPDR <= (others => '0'); + DDR <= (others => '0'); + AER <= (others => '0'); + elsif CLK = '1' and CLK' event then + if CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "00000" => GPDR <= DATA_IN; + when "00001" => AER <= DATA_IN; + when "00010" => DDR <= DATA_IN; + when others => null; + end case; + end if; + end if; + end process GPIO_REGISTERS; + GPIP_OUT <= GPDR; -- Port outputs. + GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP. + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0'; + DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else + AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else + GPDR_I when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00000" else (others => '0'); + + P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR) + -- Read back control: Read the port pins, if the data direction is configured as input. + -- Read the respective GPDR register bit, if the data direction is configured as output. + begin + for i in 7 downto 0 loop + if GPIP_OUT_EN(i) = '1' then -- Port is configured output. + GPDR_I(i) <= GPDR(i); + else + GPDR_I(i) <= GPIP_IN(i); -- Port is configured input. + end if; + end loop; + end process P_GPDR; +end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd new file mode 100644 index 0000000..91417f8 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd @@ -0,0 +1,391 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core interrupt logic file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/06/03 WF +-- Fixed Pending register logic. +-- Revision 2K9A 2009/06/20 WF +-- Fixed interrupt polarity for TA_I and TB_I. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_INTERRUPTS is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Interrupt control: + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + + -- Interrupt sources: + GP_INT : in bit_vector(7 downto 0); + + AER_4 : in bit; + AER_3 : in bit; + TAI : in bit; + TBI : in bit; + TA_PWM : in bit; + TB_PWM : in bit; + TIMER_A_INT : in bit; + TIMER_B_INT : in bit; + TIMER_C_INT : in bit; + TIMER_D_INT : in bit; + + RCV_ERR : in bit; + TRM_ERR : in bit; + RCV_BUF_F : in bit; + TRM_BUF_E : in bit + ); +end entity WF68901IP_INTERRUPTS; + +architecture BEHAVIOR of WF68901IP_INTERRUPTS is +-- Interrupt state machine: +type INT_STATES is (SCAN, REQUEST, VECTOR_OUT); +signal INT_STATE : INT_STATES; +-- The registers: +signal IERA : bit_vector(7 downto 0); +signal IERB : bit_vector(7 downto 0); +signal IPRA : bit_vector(7 downto 0); +signal IPRB : bit_vector(7 downto 0); +signal ISRA : bit_vector(7 downto 0); +signal ISRB : bit_vector(7 downto 0); +signal IMRA : bit_vector(7 downto 0); +signal IMRB : bit_vector(7 downto 0); +signal VR : bit_vector(7 downto 3); +-- Interconnect: +signal VECT_NUMBER : bit_vector(7 downto 0); +signal INT_SRC : bit_vector(15 downto 0); +signal INT_SRC_EDGE : bit_vector(15 downto 0); +signal INT_ENA : bit_vector(15 downto 0); +signal INT_MASK : bit_vector(15 downto 0); +signal INT_PENDING : bit_vector(15 downto 0); +signal INT_SERVICE : bit_vector(15 downto 0); +signal INT_PASS : bit_vector(15 downto 0); +signal INT_OUT : bit_vector(15 downto 0); +signal GP_INT_4 : bit; +signal GP_INT_3 : bit; +begin + -- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin. + -- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated + -- to timer A and timer B. + -- The xor logic provides polarity control for the interrupt transition. Be aware, + -- that the PWM signals cause an interrupt on the opposite transition like the + -- respective GPIP port pins (with the same AER settings). + --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4; + --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3; + GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct. + GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3; + + + -- Interrupt source priority sorted (15 = highest): + INT_SRC <= GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & + GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0); + + INT_ENA <= IERA & IERB; + INT_MASK <= IMRA & IMRB; + INT_PENDING <= IPRA & IPRB; + INT_SERVICE <= ISRA & ISRB; + INT_OUT <= INT_PENDING and INT_MASK; -- Masking: + + -- Enable the daisy chain, if there is no pending interrupt and + -- the interrupt state machine is not in service. + IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1'; + + -- Interrupt request: + IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1'; + + EDGE_ENA: process(RESETn, CLK) + -- These are the 16 edge detectors of the 16 interrupt input sources. This + -- process also provides the disabling or enabling via the IERA and IERB registers. + variable LOCK : bit_vector(15 downto 0); + begin + if RESETn = '0' then + INT_SRC_EDGE <= x"0000"; + LOCK := x"0000"; + elsif CLK = '1' and CLK' event then + for i in 15 downto 0 loop + if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then + LOCK(i) := '1'; + INT_SRC_EDGE(i) <= '1'; + elsif INT_SRC(i) = '0' then + LOCK(i) := '0'; + INT_SRC_EDGE(i) <= '0'; + else + INT_SRC_EDGE(i) <= '0'; + end if; + end loop; + end if; + end process EDGE_ENA; + + INT_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + IERA <= (others => '0'); + IERB <= (others => '0'); + IPRA <= (others => '0'); + IPRB <= (others => '0'); + ISRA <= (others => '0'); + ISRB <= (others => '0'); + IMRA <= (others => '0'); + IMRB <= (others => '0'); + elsif CLK = '1' and CLK' event then + if CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "00011" => IERA <= DATA_IN; -- Enable A. + when "00100" => IERB <= DATA_IN; -- Enable B. + when "00101" => + -- Only a '0' can be written to the pending register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + IPRA(i) <= '0'; -- Pending A. + end if; + end loop; + when "00110" => + -- Only a '0' can be written to the pending register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + IPRB(i) <= '0'; -- Pending B. + end if; + end loop; + when "00111" => + -- Only a '0' can be written to the in service register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + ISRA(i) <= '0'; -- In Service A. + end if; + end loop; + when "01000" => + -- Only a '0' can be written to the in service register. + for i in 7 downto 0 loop + if DATA_IN(i) = '0' then + ISRB(i) <= '0'; -- In Service B. + end if; + end loop; + when "01001" => IMRA <= DATA_IN; -- Mask A. + when "01010" => IMRB <= DATA_IN; -- Mask B. + when "01011" => VR <= DATA_IN(7 downto 3); -- Vector register. + when others => null; + end case; + end if; + + -- Pending register: + -- set and clear bit logic. + for i in 15 downto 8 loop + if INT_SRC_EDGE(i) = '1' then + IPRA(i-8) <= '1'; + elsif INT_ENA(i) = '0' then + IPRA(i-8) <= '0'; -- Clear by disabling the channel. + elsif INT_PASS(i) = '1' then + IPRA(i-8) <= '0'; -- Clear by passing the interrupt. + end if; + end loop; + for i in 7 downto 0 loop + if INT_SRC_EDGE(i) = '1' then + IPRB(i) <= '1'; + elsif INT_ENA(i) = '0' then + IPRB(i) <= '0'; -- Clear by disabling the channel. + elsif INT_PASS(i) = '1' then + IPRB(i) <= '0'; -- Clear by passing the interrupt. + end if; + end loop; + + -- In-Service register: + -- Set bit logic, VR(3) is the service register enable. + for i in 15 downto 8 loop + if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then + ISRA(i-8) <= '1'; + end if; + end loop; + for i in 7 downto 0 loop + if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then + ISRB(i) <= '1'; + end if; + end loop; + end if; + end process INT_REGISTERS; + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else '1' when INT_STATE = VECTOR_OUT else '0'; + + DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else + IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else + IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else + IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else + ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else + ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else + IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else + IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else + VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else + VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00"; + + P_INT_STATE : process(RESETn, CLK) + begin + if RESETn = '0' then + INT_STATE <= SCAN; + elsif CLK = '1' and CLK' event then + case INT_STATE is + when SCAN => + INT_PASS <= x"0000"; + -- Automatic End of Interrupt mode. Service register disabled. + -- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized + -- vector number (VR(7 downto 4) = x"0"). + if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then + INT_STATE <= REQUEST; -- Non masked interrupt is pending. + -- The following 16 are the Software end of interrupt mode. Service register enabled. + -- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized + -- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized. + elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then + if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then + INT_STATE <= REQUEST; + elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then + INT_STATE <= REQUEST; + elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then + INT_STATE <= REQUEST; + elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then + INT_STATE <= REQUEST; + elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then + INT_STATE <= REQUEST; + elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then + INT_STATE <= REQUEST; + elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then + INT_STATE <= REQUEST; + else + INT_STATE <= SCAN; -- Wait for interrupt. + end if; + else + INT_STATE <= SCAN; + end if; + when REQUEST => + if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode. + INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending. + if INT_OUT(15) = '1' then + INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7. + elsif INT_OUT(14) = '1' then + INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6. + elsif INT_OUT(13) = '1' then + INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A. + elsif INT_OUT(12) = '1' then + INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full. + elsif INT_OUT(11) = '1' then + INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error. + elsif INT_OUT(10) = '1' then + INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty. + elsif INT_OUT(9) = '1' then + INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error. + elsif INT_OUT(8) = '1' then + INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B. + elsif INT_OUT(7) = '1' then + INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5. + elsif INT_OUT(6) = '1' then + INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4. + elsif INT_OUT(5) = '1' then + INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C. + elsif INT_OUT(4) = '1' then + INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D. + elsif INT_OUT(3) = '1' then + INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3. + elsif INT_OUT(2) = '1' then + INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2. + elsif INT_OUT(1) = '1' then + INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1. + elsif INT_OUT(0) = '1' then + INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0. + end if; + -- Polled interrupt mode: End of interrupt by writing to the pending registers. + elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then + INT_STATE <= SCAN; + else + INT_STATE <= REQUEST; -- Wait. + end if; + when VECTOR_OUT => + INT_PASS <= x"0000"; + if DSn = '1' or IACKn = '1' then + INT_STATE <= SCAN; -- Finished. + else + INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector. + end if; + end case; + end if; + end process P_INT_STATE; +end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd new file mode 100644 index 0000000..73c0cdc --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd @@ -0,0 +1,263 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the package file containing the component ---- +---- declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package WF68901IP_PKG is +component WF68901IP_USART_TOP + port ( CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + RC : in bit; + TC : in bit; + SI : in bit; + SO : out bit; + SO_EN : out bit; + RX_ERR_INT : out bit; + RX_BUFF_INT : out bit; + TX_ERR_INT : out bit; + TX_BUFF_INT : out bit; + RRn : out bit; + TRn : out bit + ); +end component; + +component WF68901IP_USART_CTRL + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + RX_SAMPLE : in bit; + RX_DATA : in bit_vector(7 downto 0); + TX_DATA : out bit_vector(7 downto 0); + SCR_OUT : out bit_vector(7 downto 0); + BF : in bit; + BE : in bit; + FE : in bit; + OE : in bit; + UE : in bit; + PE : in bit; + M_CIP : in bit; + FS_B : in bit; + TX_END : in bit; + CL : out bit_vector(1 downto 0); + ST : out bit_vector(1 downto 0); + FS_CLR : out bit; + RSR_READ : out bit; + TSR_READ : out bit; + UDR_READ : out bit; + UDR_WRITE : out bit; + LOOPBACK : out bit; + SDOUT_EN : out bit; + SD_LEVEL : out bit; + CLK_MODE : out bit; + RE : out bit; + TE : out bit; + P_ENA : out bit; + P_EOn : out bit; + SS : out bit; + BR : out bit + ); +end component; + +component WF68901IP_USART_TX + port ( + CLK : in bit; + RESETn : in bit; + SCR : in bit_vector(7 downto 0); + TX_DATA : in bit_vector(7 downto 0); + SDATA_OUT : out bit; + TXCLK : in bit; + CL : in bit_vector(1 downto 0); + ST : in bit_vector(1 downto 0); + TE : in bit; + BR : in bit; + P_ENA : in bit; + P_EOn : in bit; + UDR_WRITE : in bit; + TSR_READ : in bit; + CLK_MODE : in bit; + TX_END : out bit; + UE : out bit; + BE : out bit + ); +end component; + +component WF68901IP_USART_RX + port ( + CLK : in bit; + RESETn : in bit; + SCR : in bit_vector(7 downto 0); + RX_SAMPLE : out bit; + RX_DATA : out bit_vector(7 downto 0); + RXCLK : in bit; + SDATA_IN : in bit; + CL : in bit_vector(1 downto 0); + ST : in bit_vector(1 downto 0); + P_ENA : in bit; + P_EOn : in bit; + CLK_MODE : in bit; + RE : in bit; + FS_CLR : in bit; + SS : in bit; + RSR_READ : in bit; + UDR_READ : in bit; + M_CIP : out bit; + FS_B : out bit; + BF : out bit; + OE : out bit; + PE : out bit; + FE : out bit + ); +end component; + +component WF68901IP_INTERRUPTS + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + GP_INT : in bit_vector(7 downto 0); + AER_4 : in bit; + AER_3 : in bit; + TAI : in bit; + TBI : in bit; + TA_PWM : in bit; + TB_PWM : in bit; + TIMER_A_INT : in bit; + TIMER_B_INT : in bit; + TIMER_C_INT : in bit; + TIMER_D_INT : in bit; + RCV_ERR : in bit; + TRM_ERR : in bit; + RCV_BUF_F : in bit; + TRM_BUF_E : in bit + ); +end component; + +component WF68901IP_GPIO + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + AER_4 : out bit; + AER_3 : out bit; + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_OUT_EN : out bit_vector(7 downto 0); + GP_INT : out bit_vector(7 downto 0) + ); +end component; + +component WF68901IP_TIMERS + port ( + CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + XTAL1 : in bit; + TAI : in bit; + TBI : in bit; + AER_4 : in bit; + AER_3 : in bit; + TA_PWM : out bit; + TB_PWM : out bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + TIMER_A_INT : out bit; + TIMER_B_INT : out bit; + TIMER_C_INT : out bit; + TIMER_D_INT : out bit + ); +end component; + +end WF68901IP_PKG; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd new file mode 100644 index 0000000..b339af5 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd @@ -0,0 +1,533 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core timers logic file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K7A 2006/12/28 WF +-- The timer is modified to work on the CLK instead +-- of XTAL1. This modification is done to provide +-- a synchronous design. +-- Revision 2K8A 2008/02/29 WF +-- Fixed a serious prescaler bug. +-- Revision 2K9A 20090620 WF +-- Introduced timer readback registers. +-- TIMER_x_INT is now a strobe. +-- Minor improvements. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_TIMERS is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Timers and timer control: + XTAL1 : in bit; -- Use an oszillator instead of a quartz. + TAI : in bit; + TBI : in bit; + AER_4 : in bit; + AER_3 : in bit; + TA_PWM : out bit; -- Indicates, that timer A is in PWM mode (used in Interrupt logic). + TB_PWM : out bit; -- Indicates, that timer B is in PWM mode (used in Interrupt logic). + TAO : buffer bit; + TBO : buffer bit; + TCO : buffer bit; + TDO : buffer bit; + TIMER_A_INT : out bit; + TIMER_B_INT : out bit; + TIMER_C_INT : out bit; + TIMER_D_INT : out bit + ); +end entity WF68901IP_TIMERS; + +architecture BEHAVIOR of WF68901IP_TIMERS is +signal XTAL1_S : bit; +signal XTAL_STRB : bit; +signal TACR : bit_vector(4 downto 0); -- Timer A control register. +signal TBCR : bit_vector(4 downto 0); -- Timer B control register. +signal TCDCR : bit_vector(5 downto 0); -- Timer C and D control register. +signal TADR : bit_vector(7 downto 0); -- Timer A data register. +signal TBDR : bit_vector(7 downto 0); -- Timer B data register. +signal TCDR : bit_vector(7 downto 0); -- Timer C data register. +signal TDDR : bit_vector(7 downto 0); -- Timer D data register. +signal TIMER_A : std_logic_vector(7 downto 0); -- Timer A count register. +signal TIMER_B : std_logic_vector(7 downto 0); -- Timer B count register. +signal TIMER_C : std_logic_vector(7 downto 0); -- Timer C count register. +signal TIMER_D : std_logic_vector(7 downto 0); -- Timer D count register. +signal TIMER_R_A : bit_vector(7 downto 0); -- Timer A readback register. +signal TIMER_R_B : bit_vector(7 downto 0); -- Timer B readback register. +signal TIMER_R_C : bit_vector(7 downto 0); -- Timer C readback register. +signal TIMER_R_D : bit_vector(7 downto 0); -- Timer D readback register. +signal A_CNTSTRB : bit; +signal B_CNTSTRB : bit; +signal C_CNTSTRB : bit; +signal D_CNTSTRB : bit; +signal TAI_I : bit; +signal TBI_I : bit; +signal TAI_STRB : bit; -- Strobe for the event counter mode. +signal TBI_STRB : bit; -- Strobe for the event counter mode. +signal TAO_I : bit; -- Timer A output signal. +signal TBO_I : bit; -- Timer A output signal. +begin + SYNC: process + -- This process provides a 'clean' XTAL1. + -- Without this sync, the edge detector for + -- XTAL_STRB does not work properly. + begin + wait until CLK = '1' and CLK' event; + XTAL1_S <= XTAL1; + -- Polarity control for the event counter and the PWM mode: + TAI_I <= TAI xnor AER_4; + TBI_I <= TBI xnor AER_3; + end process SYNC; + + -- Output enables for timer A and timer B: + -- The outputs are held low for asserted reset flags in the control registers TACR + -- and TBCR but also during a write operation to these registers. + TAO <= '0' when TACR(4) = '1' else + '0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01100" else TAO_I; + TBO <= '0' when TBCR(4) = '1' else + '0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01101" else TBO_I; + + -- Control outputs for the PWM modi of the timers A and B. These + -- controls are used in the interrupt logic to select the interrupt + -- sources GPIP4 or TAI repective GPIP3 or TBI. + TA_PWM <= '1' when TACR(3 downto 0) > x"8" else '0'; + TB_PWM <= '1' when TBCR(3 downto 0) > x"8" else '0'; + + TIMER_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + TACR <= (others => '0'); + TBCR <= (others => '0'); + TCDCR <= (others => '0'); + -- TADR <= Do not clear during reset! + -- TBDR <= Do not clear during reset! + -- TCDR <= Do not clear during reset! + -- TDDR <= Do not clear during reset! + elsif CLK = '1' and CLK' event then + if CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "01100" => TACR <= DATA_IN(4 downto 0); + when "01101" => TBCR <= DATA_IN(4 downto 0); + when "01110" => TCDCR <= DATA_IN(6 downto 4) & DATA_IN(2 downto 0); + when "01111" => TADR <= DATA_IN; + when "10000" => TBDR <= DATA_IN; + when "10001" => TCDR <= DATA_IN; + when "10010" => TDDR <= DATA_IN; + when others => null; + end case; + end if; + end if; + end process TIMER_REGISTERS; + + TIMER_READBACK : process(RESETn, CLK) + -- This process provides the readback information for the + -- timers A to D. The information read is the information + -- last clocked into the timer read register when the DSn + -- pin had last gone high prior to the current read cycle. + variable READ_A : boolean; + variable READ_B : boolean; + variable READ_C : boolean; + variable READ_D : boolean; + begin + if RESETn = '0' then + TIMER_R_A <= x"00"; + TIMER_R_B <= x"00"; + TIMER_R_C <= x"00"; + TIMER_R_D <= x"00"; + elsif CLK = '1' and CLK' event then + if DSn = '0' and RS = "01111" then + READ_A := true; + elsif DSn = '0' and RS = "10000" then + READ_B := true; + elsif DSn = '0' and RS = "10001" then + READ_C := true; + elsif DSn = '0' and RS = "10010" then + READ_D := true; + elsif DSn = '1' and READ_A = true then + TIMER_R_A <= To_BitVector(TIMER_A); + READ_A := false; + elsif DSn = '1' and READ_B = true then + TIMER_R_B <= To_BitVector(TIMER_B); + READ_B := false; + elsif DSn = '1' and READ_C = true then + TIMER_R_C <= To_BitVector(TIMER_C); + READ_C := false; + elsif DSn = '1' and READ_D = true then + TIMER_R_D <= To_BitVector(TIMER_D); + READ_D := false; + end if; + end if; + end process TIMER_READBACK; + + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "01011" and RS <= "10010" else '0'; + DATA_OUT <= "000" & TACR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01100" else + "000" & TBCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01101" else + '0' & TCDCR(5 downto 3) & '0' & TCDCR(2 downto 0) when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01110" else + TIMER_R_A when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01111" else + TIMER_R_B when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10000" else + TIMER_R_C when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10001" else + TIMER_R_D when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10010" else (others => '0'); + + XTAL_STROBE: process(RESETn, CLK) + -- This process provides a strobe with 1 clock cycle + -- (CLK) length after every rising edge of XTAL1. + variable LOCK : boolean; + begin + if RESETn = '0' then + XTAL_STRB <= '0'; + elsif CLK = '1' and CLK' event then + if XTAL1_S = '1' and LOCK = false then + XTAL_STRB <= '1'; + LOCK := true; + elsif XTAL1_S = '0' then + XTAL_STRB <= '0'; + LOCK := false; + else + XTAL_STRB <= '0'; + end if; + end if; + end process XTAL_STROBE; + + TAI_STROBE: process(RESETn, CLK) + variable LOCK : boolean; + begin + if RESETn = '0' then + TAI_STRB <= '0'; + elsif CLK = '1' and CLK' event then + if TAI_I = '1' and XTAL_STRB = '1' and LOCK = false then + LOCK := true; + TAI_STRB <= '1'; + elsif TAI_I = '0' then + LOCK := false; + TAI_STRB <= '0'; + else + TAI_STRB <= '0'; + end if; + end if; + end process TAI_STROBE; + + TBI_STROBE: process(RESETn, CLK) + variable LOCK : boolean; + begin + if RESETn = '0' then + TBI_STRB <= '0'; + elsif CLK = '1' and CLK' event then + if TBI_I = '1' and XTAL_STRB = '1' and LOCK = false then + LOCK := true; + TBI_STRB <= '1'; + elsif TBI_I = '0' then + LOCK := false; + TBI_STRB <= '0'; + else + TBI_STRB <= '0'; + end if; + end if; + end process TBI_STROBE; + + PRESCALE_A: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + A_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TACR(2 downto 0) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode. + end case; + A_CNTSTRB <= '1'; + end if; + end process PRESCALE_A; + + PRESCALE_B: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + B_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TBCR(2 downto 0) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode. + end case; + B_CNTSTRB <= '1'; + end if; + end process PRESCALE_B; + + PRESCALE_C: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + C_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TCDCR(5 downto 3) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped. + end case; + C_CNTSTRB <= '1'; + end if; + end process PRESCALE_C; + + PRESCALE_D: process + -- The prescalers work even if the RESETn is asserted. + variable PRESCALE : std_logic_vector(7 downto 0); + begin + wait until CLK = '1' and CLK' event; + D_CNTSTRB <= '0'; + if PRESCALE > x"00" and XTAL_STRB = '1' then + PRESCALE := PRESCALE - '1'; + elsif XTAL_STRB = '1' then + case TCDCR(2 downto 0) is + when "111" => PRESCALE := x"C7"; -- Prescaler = 200. + when "110" => PRESCALE := x"63"; -- Prescaler = 100. + when "101" => PRESCALE := x"3F"; -- Prescaler = 64. + when "100" => PRESCALE := x"31"; -- Prescaler = 50. + when "011" => PRESCALE := x"0F"; -- Prescaler = 16. + when "010" => PRESCALE := x"09"; -- Prescaler = 10. + when "001" => PRESCALE := x"03"; -- Prescaler = 4. + when "000" => PRESCALE := x"00"; -- Timer stopped. + end case; + D_CNTSTRB <= '1'; + end if; + end process PRESCALE_D; + + TIMERA: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TAO_I <= '0'; + TIMER_A_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_A_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "01111" and TACR(3 downto 0) = x"0" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_A <= To_StdLogicVector(DATA_IN); + else + case TACR(3 downto 0) is + when x"0" => -- Timer is off. + TAO_I <= '0'; + when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode. + if A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count. + TIMER_A <= TIMER_A - '1'; + elsif A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload. + TIMER_A <= To_StdLogicVector(TADR); + TAO_I <= not TAO_I; -- Toggle the timer A output pin. + TIMER_A_INT <= '1'; + end if; + when x"8" => -- Event count operation. + if TAI_STRB = '1' and TIMER_A /= x"01" then -- Count. + TIMER_A <= TIMER_A - '1'; + elsif TAI_STRB = '1' and TIMER_A = x"01" then -- Reload. + TIMER_A <= To_StdLogicVector(TADR); + TAO_I <= not TAO_I; -- Toggle the timer A output pin. + TIMER_A_INT <= '1'; + end if; + when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode. + if TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count. + TIMER_A <= TIMER_A - '1'; + elsif TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload. + TIMER_A <= To_StdLogicVector(TADR); + TAO_I <= not TAO_I; -- Toggle the timer A output pin. + TIMER_A_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERA; + + TIMERB: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TBO_I <= '0'; + TIMER_B_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_B_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10000" and TBCR(3 downto 0) = x"0" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_B <= To_StdLogicVector(DATA_IN); + else + case TBCR(3 downto 0) is + when x"0" => -- Timer is off. + TBO_I <= '0'; + when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode. + if B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count. + TIMER_B <= TIMER_B - '1'; + elsif B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload. + TIMER_B <= To_StdLogicVector(TBDR); + TBO_I <= not TBO_I; -- Toggle the timer B output pin. + TIMER_B_INT <= '1'; + end if; + when x"8" => -- Event count operation. + if TBI_STRB = '1' and TIMER_B /= x"01" then -- Count. + TIMER_B <= TIMER_B - '1'; + elsif TBI_STRB = '1' and TIMER_B = x"01" then -- Reload. + TIMER_B <= To_StdLogicVector(TBDR); + TBO_I <= not TBO_I; -- Toggle the timer B output pin. + TIMER_B_INT <= '1'; + end if; + when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode. + if TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count. + TIMER_B <= TIMER_B - '1'; + elsif TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload. + TIMER_B <= To_StdLogicVector(TBDR); + TBO_I <= not TBO_I; -- Toggle the timer B output pin. + TIMER_B_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERB; + + TIMERC: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TCO <= '0'; + TIMER_C_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_C_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10001" and TCDCR(5 downto 3) = "000" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_C <= To_StdLogicVector(DATA_IN); + else + case TCDCR(5 downto 3) is + when "000" => -- Timer is off. + TCO <= '0'; + when others => -- Delay counter mode. + if C_CNTSTRB = '1' and TIMER_C /= x"01" then -- Count. + TIMER_C <= TIMER_C - '1'; + elsif C_CNTSTRB = '1' and TIMER_C = x"01" then -- Reload. + TIMER_C <= To_StdLogicVector(TCDR); + TCO <= not TCO; -- Toggle the timer C output pin. + TIMER_C_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERC; + + TIMERD: process(RESETn, CLK) + begin + if RESETn = '0' then + -- Do not clear the timer registers during system reset. + TDO <= '0'; + TIMER_D_INT <= '0'; + elsif CLK = '1' and CLK' event then + TIMER_D_INT <= '0'; + -- + if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10010" and TCDCR(2 downto 0) = "000" then + -- The timer is reloaded simultaneously to it's timer data register, if it is off. + -- The loading works asynchronous due to the possibly low XTAL1 clock. + TIMER_D <= To_StdLogicVector(DATA_IN); + else + case TCDCR(2 downto 0) is + when "000" => -- Timer is off. + TDO <= '0'; + when others => -- Delay counter mode. + if D_CNTSTRB = '1' and TIMER_D /= x"01" then -- Count. + TIMER_D <= TIMER_D - '1'; + elsif D_CNTSTRB = '1' and TIMER_D = x"01" then -- Reload. + TIMER_D <= To_StdLogicVector(TDDR); + TDO <= not TDO; -- Toggle the timer D output pin. + TIMER_D_INT <= '1'; + end if; + end case; + end if; + end if; + end process TIMERD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd new file mode 100644 index 0000000..783ba56 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd @@ -0,0 +1,213 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K7A 2006/12/28 WF +-- The timer is modified to work on the CLK instead +-- of XTAL1. This modification is done to provide +-- a synchronous design. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. +-- + +use work.wf68901ip_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_TOP is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + DTACKn : out std_logic; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA : inout std_logic_vector(7 downto 0); + GPIP : inout std_logic_vector(7 downto 0); + + -- Interrupt control: + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out std_logic; + + -- Timers and timer control: + XTAL1 : in bit; -- Use an oszillator instead of a quartz. + TAI : in bit; + TBI : in bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + + -- Serial I/O control: + RC : in bit; + TC : in bit; + SI : in bit; + SO : out std_logic; + + -- DMA control: + RRn : out bit; + TRn : out bit + ); +end entity WF68901IP_TOP; + +architecture STRUCTURE of WF68901IP_TOP is +component WF68901IP_TOP_SOC + port(CLK : in bit; + RESETn : in bit; + DSn : in bit; + CSn : in bit; + RWn : in bit; + DTACKn : out bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_EN : out bit_vector(7 downto 0); + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + XTAL1 : in bit; + TAI : in bit; + TBI : in bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + RC : in bit; + TC : in bit; + SI : in bit; + SO : out bit; + SO_EN : out bit; + RRn : out bit; + TRn : out bit + ); +end component; +-- +signal DTACK_In : bit; +signal IRQ_In : bit; +signal DATA_OUT : std_logic_vector(7 downto 0); +signal DATA_EN : bit; +signal GPIP_IN : bit_vector(7 downto 0); +signal GPIP_OUT : bit_vector(7 downto 0); +signal GPIP_EN : bit_vector(7 downto 0); +signal SO_I : bit; +signal SO_EN : bit; +begin + DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain. + IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. + + DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); + + GPIP_IN <= To_BitVector(GPIP); + + P_GPIP_OUT: process(GPIP_OUT, GPIP_EN) + begin + for i in 7 downto 0 loop + if GPIP_EN(i) = '1' then + case GPIP_OUT(i) is + when '0' => GPIP(i) <= '0'; + when others => GPIP(i) <= '1'; + end case; + else + GPIP(i) <= 'Z'; + end if; + end loop; + end process P_GPIP_OUT; + + SO <= '0' when SO_I = '0' and SO_EN = '1' else + '1' when SO_I = '1' and SO_EN = '1' else 'Z'; + + I_MFP: WF68901IP_TOP_SOC + port map(CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + DTACKn => DTACK_In, + RS => RS, + DATA_IN => DATA, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + GPIP_IN => GPIP_IN, + GPIP_OUT => GPIP_OUT, + GPIP_EN => GPIP_EN, + IACKn => IACKn, + IEIn => IEIn, + IEOn => IEOn, + IRQn => IRQ_In, + XTAL1 => XTAL1, + TAI => TAI, + TBI => TBI, + TAO => TAO, + TBO => TBO, + TCO => TCO, + TDO => TDO, + RC => RC, + TC => TC, + SI => SI, + SO => SO_I, + SO_EN => SO_EN, + RRn => RRn, + TRn => TRn + ); +end architecture STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd new file mode 100644 index 0000000..1e559d9 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd @@ -0,0 +1,309 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core top level file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K7A 2006/12/28 WF +-- The timer is modified to work on the CLK instead +-- of XTAL1. This modification is done to provide +-- a synchronous design. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- DTACK_OUTn has now synchronous reset to meet preset requirement. +-- +-- + +use work.wf68901ip_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_TOP_SOC is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + DTACKn : out bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + GPIP_IN : in bit_vector(7 downto 0); + GPIP_OUT : out bit_vector(7 downto 0); + GPIP_EN : out bit_vector(7 downto 0); + + -- Interrupt control: + IACKn : in bit; + IEIn : in bit; + IEOn : out bit; + IRQn : out bit; + + -- Timers and timer control: + XTAL1 : in bit; -- Use an oszillator instead of a quartz. + TAI : in bit; + TBI : in bit; + TAO : out bit; + TBO : out bit; + TCO : out bit; + TDO : out bit; + + -- Serial I/O control: + RC : in bit; + TC : in bit; + SI : in bit; + SO : out bit; + SO_EN : out bit; + + -- DMA control: + RRn : out bit; + TRn : out bit + ); +end entity WF68901IP_TOP_SOC; + +architecture STRUCTURE of WF68901IP_TOP_SOC is +signal DATA_IN_I : bit_vector(7 downto 0); +signal DTACK_In : bit; +signal DTACK_LOCK : boolean; +signal DTACK_OUTn : bit; +signal RX_ERR_INT_I : bit; +signal TX_ERR_INT_I : bit; +signal RX_BUFF_INT_I : bit; +signal TX_BUFF_INT_I : bit; +signal DATA_OUT_USART_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_USART_I : bit; +signal DATA_OUT_INT_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_INT_I : bit; +signal DATA_OUT_GPIO_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_GPIO_I : bit; +signal DATA_OUT_TIMERS_I : bit_vector(7 downto 0); +signal DATA_OUT_EN_TIMERS_I : bit; +signal SO_I : bit; +signal SO_EN_I : bit; +signal GPIP_IN_I : bit_vector(7 downto 0); +signal GPIP_OUT_I : bit_vector(7 downto 0); +signal GPIP_EN_I : bit_vector(7 downto 0); +signal GP_INT_I : bit_vector(7 downto 0); +signal TIMER_A_INT_I : bit; +signal TIMER_B_INT_I : bit; +signal TIMER_C_INT_I : bit; +signal TIMER_D_INT_I : bit; +signal IRQ_In : bit; +signal AER_4_I : bit; +signal AER_3_I : bit; +signal TA_PWM_I : bit; +signal TB_PWM_I : bit; +begin + -- Interrupt request (open drain): + IRQn <= IRQ_In; + + -- Serial data output: + SO <= SO_I; + SO_EN <= SO_EN_I and RESETn; + + -- General purpose port: + GPIP_IN_I <= GPIP_IN; + GPIP_OUT <= GPIP_OUT_I; + GPIP_EN <= GPIP_EN_I; + + DATA_IN_I <= To_BitVector(DATA_IN); + DATA_EN <= DATA_OUT_EN_USART_I or DATA_OUT_EN_INT_I or DATA_OUT_EN_GPIO_I or DATA_OUT_EN_TIMERS_I; + -- Output data multiplexer: + DATA_OUT <= To_StdLogicVector(DATA_OUT_USART_I) when DATA_OUT_EN_USART_I = '1' else + To_StdLogicVector(DATA_OUT_INT_I) when DATA_OUT_EN_INT_I = '1' else + To_StdLogicVector(DATA_OUT_GPIO_I) when DATA_OUT_EN_GPIO_I = '1' else + To_StdLogicVector(DATA_OUT_TIMERS_I) when DATA_OUT_EN_TIMERS_I = '1' else (others => '1'); + + -- Data acknowledge handshake is provided by the following statement and the consecutive two + -- processes. For more information refer to the M68000 family reference manual. + DTACK_In <= '0' when CSn = '0' and DSn = '0' and RS <= "10111" else -- Read and write operation. + '0' when IACKn = '0' and DSn = '0' and IEIn = '0' else '1'; -- Interrupt vector data acknowledge. + + P_DTACK_LOCK: process + -- This process releases a data acknowledge detect, one rising clock + -- edge after the DTACK_In occured. This is necessary to ensure write + -- data to registers for there is one rising clock edge required. + begin + wait until CLK = '1' and CLK' event; + if DTACK_In = '0' then + DTACK_LOCK <= false; + else + DTACK_LOCK <= true; + end if; + end process P_DTACK_LOCK; + + DTACK_OUT: process + -- The DTACKn port pin is released on the falling clock edge after the data + -- acknowledge detect (DTACK_LOCK) is asserted. The DTACKn is deasserted + -- immediately when there is no further register access DTACK_In = '1'; + begin + wait until CLK = '0' and CLK' event; + if RESETn = '0' then + DTACK_OUTn <= '1'; + elsif DTACK_In = '1' then + DTACK_OUTn <= '1'; + elsif DTACK_LOCK = false then + DTACK_OUTn <= '0'; + end if; + end process DTACK_OUT; + DTACKn <= '0' when DTACK_OUTn = '0' else '1'; + + I_USART: WF68901IP_USART_TOP + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_USART_I, + DATA_OUT_EN => DATA_OUT_EN_USART_I, + RC => RC, + TC => TC, + SI => SI, + SO => SO_I, + SO_EN => SO_EN_I, + RX_ERR_INT => RX_ERR_INT_I, + RX_BUFF_INT => RX_BUFF_INT_I, + TX_ERR_INT => TX_ERR_INT_I, + TX_BUFF_INT => TX_BUFF_INT_I, + RRn => RRn, + TRn => TRn + ); + + I_INTERRUPTS: WF68901IP_INTERRUPTS + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_INT_I, + DATA_OUT_EN => DATA_OUT_EN_INT_I, + IACKn => IACKn, + IEIn => IEIn, + IEOn => IEOn, + IRQn => IRQ_In, + GP_INT => GP_INT_I, + AER_4 => AER_4_I, + AER_3 => AER_3_I, + TAI => TAI, + TBI => TBI, + TA_PWM => TA_PWM_I, + TB_PWM => TB_PWM_I, + TIMER_A_INT => TIMER_A_INT_I, + TIMER_B_INT => TIMER_B_INT_I, + TIMER_C_INT => TIMER_C_INT_I, + TIMER_D_INT => TIMER_D_INT_I, + RCV_ERR => RX_ERR_INT_I, + TRM_ERR => TX_ERR_INT_I, + RCV_BUF_F => RX_BUFF_INT_I, + TRM_BUF_E => TX_BUFF_INT_I + ); + + I_GPIO: WF68901IP_GPIO + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_GPIO_I, + DATA_OUT_EN => DATA_OUT_EN_GPIO_I, + AER_4 => AER_4_I, + AER_3 => AER_3_I, + GPIP_IN => GPIP_IN_I, + GPIP_OUT => GPIP_OUT_I, + GPIP_OUT_EN => GPIP_EN_I, + GP_INT => GP_INT_I + ); + + I_TIMERS: WF68901IP_TIMERS + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_OUT_TIMERS_I, + DATA_OUT_EN => DATA_OUT_EN_TIMERS_I, + XTAL1 => XTAL1, + AER_4 => AER_4_I, + AER_3 => AER_3_I, + TAI => TAI, + TBI => TBI, + TAO => TAO, + TBO => TBO, + TCO => TCO, + TDO => TDO, + TA_PWM => TA_PWM_I, + TB_PWM => TB_PWM_I, + TIMER_A_INT => TIMER_A_INT_I, + TIMER_B_INT => TIMER_B_INT_I, + TIMER_C_INT => TIMER_C_INT_I, + TIMER_D_INT => TIMER_D_INT_I + ); +end architecture STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd new file mode 100644 index 0000000..8e7c3cc --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd @@ -0,0 +1,191 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This is the SUSKA MFP IP core USART control file. ---- +---- ---- +---- Control unit and status logic. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_CTRL is + port ( + -- System Control: + CLK : in bit; + RESETn : in bit; + + -- Bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- USART data register + RX_SAMPLE : in bit; + RX_DATA : in bit_vector(7 downto 0); + TX_DATA : out bit_vector(7 downto 0); + SCR_OUT : out bit_vector(7 downto 0); + + -- USART control inputs: + BF : in bit; + BE : in bit; + FE : in bit; + OE : in bit; + UE : in bit; + PE : in bit; + M_CIP : in bit; + FS_B : in bit; + TX_END : in bit; + + -- USART control outputs: + CL : out bit_vector(1 downto 0); + ST : out bit_vector(1 downto 0); + FS_CLR : out bit; + UDR_WRITE : out bit; + UDR_READ : out bit; + RSR_READ : out bit; + TSR_READ : out bit; + LOOPBACK : out bit; + SDOUT_EN : out bit; + SD_LEVEL : out bit; + CLK_MODE : out bit; + RE : out bit; + TE : out bit; + P_ENA : out bit; + P_EOn : out bit; + SS : out bit; + BR : out bit + ); +end entity WF68901IP_USART_CTRL; + +architecture BEHAVIOR of WF68901IP_USART_CTRL is +signal SCR : bit_vector(7 downto 0); -- Synchronous data register. +signal UCR : bit_vector(7 downto 1); -- USART control register. +signal RSR : bit_vector(7 downto 0); -- Receiver status register. +signal TSR : bit_vector(7 downto 0); -- Transmitter status register. +signal UDR : bit_vector(7 downto 0); -- USART data register. +begin + USART_REGISTERS: process(RESETn, CLK) + begin + if RESETn = '0' then + SCR <= (others => '0'); + UCR <= (others => '0'); + RSR <= (others => '0'); + -- TSR and UDR are not cleared during an asserted RESETn + elsif CLK = '1' and CLK' event then + -- Loading via receiver shift register + -- has priority over data buss access: + if RX_SAMPLE = '1' then + UDR <= RX_DATA; + elsif CSn = '0' and DSn = '0' and RWn = '0' then + case RS is + when "10011" => SCR <= DATA_IN; + when "10100" => UCR <= DATA_IN(7 downto 1); + when "10101" => RSR(1 downto 0) <= DATA_IN(1 downto 0); -- Only the two LSB are read/write. + when "10110" => TSR(5) <= DATA_IN(5); TSR(3 downto 0) <= DATA_IN(3 downto 0); + when "10111" => UDR <= DATA_IN; + when others => null; + end case; + end if; + RSR(7 downto 2) <= BF & OE & PE & FE & FS_B & M_CIP; + TSR(7 downto 6) <= BE & UE; + TSR(4) <= TX_END; + TX_DATA <= UDR; + end if; + end process USART_REGISTERS; + DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS >= "10011" and RS <= "10111" else '0'; + DATA_OUT <= SCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10011" else + UCR & '0' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10100" else + RSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else + TSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else + UDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else x"00"; + + UDR_WRITE <= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10111" else '0'; + UDR_READ <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else '0'; + RSR_READ <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else '0'; + TSR_READ <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else '0'; + FS_CLR <= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10011" else '0'; + + RE <= '1' when RSR(0) = '1' else -- Receiver enable. + '1' when TSR(5) = '1' and TX_END = '1' else '0'; -- Auto Turnaround. + SS <= RSR(1); -- Synchronous strip enable. + BR <= TSR(3); -- Send break. + TE <= TSR(0); -- Transmitter enable. + + SCR_OUT <= SCR; + + CLK_MODE <= UCR(7); -- Clock mode. + CL <= UCR(6 downto 5); -- Character length. + ST <= UCR(4 downto 3); -- Start/Stop configuration. + P_ENA <= UCR(2); -- Parity enable. + P_EOn <= UCR(1); -- Even or odd parity. + + SOUT_CONFIG: process + begin + wait until CLK = '1' and CLK' event; + -- Do not change the output configuration until the transmitter is disabled and + -- current character has been transmitted (TX_END = '1'). + if TX_END = '1' then + case TSR(2 downto 1) is + when "00" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '0'; + when "01" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '1'; + when "10" => LOOPBACK <= '0'; SD_LEVEL <= '1'; SDOUT_EN <= '1'; + when "11" => LOOPBACK <= '1'; SD_LEVEL <= '1'; SDOUT_EN <= '1'; + end case; + end if; + end process SOUT_CONFIG; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd new file mode 100644 index 0000000..eb00a11 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd @@ -0,0 +1,590 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This is the SUSKA MFP IP core USART receiver file. ---- +---- ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- Process P_STARTBIT has now synchronous reset to meet preset requirement. +-- Process P_SAMPLE has now synchronous reset to meet preset requirement. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_RX is + port ( + CLK : in bit; + RESETn : in bit; + + SCR : in bit_vector(7 downto 0); -- Synchronous character. + RX_SAMPLE : buffer bit; -- Flag indicating valid shift register data. + RX_DATA : out bit_vector(7 downto 0); -- Received data. + + RXCLK : in bit; -- Receiver clock. + SDATA_IN : in bit; -- Serial data input. + + CL : in bit_vector(1 downto 0); -- Character length. + ST : in bit_vector(1 downto 0); -- Start and stop bit configuration. + P_ENA : in bit; -- Parity enable. + P_EOn : in bit; -- Even or odd parity. + CLK_MODE : in bit; -- Clock mode configuration bit. + RE : in bit; -- Receiver enable. + FS_CLR : in bit; -- Clear the Found/Search flag for resynchronisation purpose. + SS : in bit; -- Synchronous strip enable. + UDR_READ : in bit; -- Flag indicating reading the data register. + RSR_READ : in bit; -- Flag indicating reading the receiver status register. + + M_CIP : out bit; -- Match/Character in progress. + FS_B : buffer bit; -- Find/Search or Break detect flag. + BF : out bit; -- Buffer full. + OE : out bit; -- Overrun error. + PE : out bit; -- Parity error. + FE : out bit -- Framing error. + ); +end entity WF68901IP_USART_RX; + +architecture BEHAVIOR of WF68901IP_USART_RX is +type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); +signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; +signal SDATA_DIV16 : bit; +signal SDATA_IN_I : bit; +signal SDATA_EDGE : bit; +signal SHIFT_REG : bit_vector(7 downto 0); +signal CLK_STRB : bit; +signal CLK_2_STRB : bit; +signal BITCNT : std_logic_vector(2 downto 0); +signal BREAK : boolean; +signal RDRF : bit; +signal STARTBIT : boolean; +begin + BF <= RDRF; -- Buffer full = Receiver Data Register Full. + RX_SAMPLE <= '1' when RCV_STATE = SYNC and ST /= "00" else -- Asynchronous mode: + -- Synchronous modes: + '1' when RCV_STATE = SYNC and ST = "00" and SS = '0' else + '1' when RCV_STATE = SYNC and ST = "00" and SS = '1' and SHIFT_REG /= SCR else '0'; + + -- Data multiplexer for the received data: + RX_DATA <= "000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 databits. + "00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 databits. + '0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 databits. + SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 databits. + + P_SAMPLE: process + -- This process provides the 'valid transition logic' of the originally MC68901. For further + -- details see the 'M68000 FAMILY REFERENCE MANUAL'. + variable LOW_FLT : std_logic_vector(1 downto 0); + variable HI_FLT : std_logic_vector(1 downto 0); + variable CLK_LOCK : boolean; + variable EDGE_LOCK : boolean; + variable TIMER : std_logic_vector(2 downto 0); + variable TIMER_LOCK : boolean; + variable NEW_SDATA : bit; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' or RE = '0' then + -- The reset condition assumes the SDATA_IN logic high. Otherwise + -- one not valid SDATA_EDGE pulse occurs during system startup. + CLK_LOCK := true; + EDGE_LOCK := true; + HI_FLT := "11"; + LOW_FLT := "11"; + SDATA_EDGE <= '0'; + NEW_SDATA := '1'; + -- Positive or negative edge detector for the incoming data. + -- Any transition must be valid for at least three receiver clock + -- cycles. The TIMER locking inhibits detecting four receiver + -- clock cycles after a valid transition. + elsif RXCLK = '1' and SDATA_IN = '0' and CLK_LOCK = false and LOW_FLT > "00" then + CLK_LOCK := true; + EDGE_LOCK := false; + HI_FLT := "00"; + LOW_FLT := LOW_FLT - '1'; + elsif RXCLK = '1' and SDATA_IN = '1' and CLK_LOCK = false and HI_FLT < "11" then + CLK_LOCK := true; + EDGE_LOCK := false; + LOW_FLT := "11"; + HI_FLT := HI_FLT + '1'; + elsif RXCLK = '1' and EDGE_LOCK = false and LOW_FLT = "00" then + EDGE_LOCK := true; + SDATA_EDGE <= '1'; -- Falling edge detected. + NEW_SDATA := '0'; + elsif RXCLK = '1' and EDGE_LOCK = false and HI_FLT = "11" then + EDGE_LOCK := true; + SDATA_EDGE <= '1'; -- Rising edge detected. + NEW_SDATA := '1'; + elsif RXCLK = '1' and CLK_LOCK = false then + CLK_LOCK := true; + SDATA_EDGE <= '0'; + elsif RXCLK = '0' then + CLK_LOCK := false; + end if; + -- + if RESETn = '0' or RE = '0' then + -- The reset condition assumes the SDATA_IN logic high. Otherwise + -- one not valid SDATA_EDGE pulse occurs during system startup. + TIMER := "111"; + TIMER_LOCK := true; + SDATA_DIV16 <= '1'; + -- The timer controls the SDATA in a way, that after a detected valid + -- Transistion, the serial data is sampled on the 8th receiver clock + -- edge after the initial valid transition occured. + elsif RXCLK = '1' and SDATA_EDGE = '1' and TIMER_LOCK = false then + TIMER_LOCK := true; + TIMER := "000"; -- Resynchronisation. + elsif RXCLK = '1' and TIMER = "011" and TIMER_LOCK = false then + TIMER_LOCK := true; + SDATA_DIV16 <= NEW_SDATA; -- Scan the new data. + TIMER := TIMER + '1'; -- Timing is active. + elsif RXCLK = '1' and TIMER < "111" and TIMER_LOCK = false then + TIMER_LOCK := true; + TIMER := TIMER + '1'; -- Timing is active. + elsif RXCLK = '0' then + TIMER_LOCK := false; + end if; + end process P_SAMPLE; + + P_START_BIT: process(CLK) + -- This is the valid start bit logic of the original MC68901 multi function + -- port's USART receiver. + variable TMP : std_logic_vector(2 downto 0); + variable LOCK : boolean; + begin + if CLK = '1' and CLK' event then + if RESETn = '0' then + TMP := "000"; + LOCK := true; + elsif RE = '0' or RCV_STATE /= IDLE then -- Start bit logic disabled. + TMP := "000"; + LOCK := true; + elsif SDATA_EDGE = '1' then + TMP := "000"; -- (Re)-Initialize. + LOCK := false; -- Start counting. + elsif RXCLK = '1' and SDATA_IN = '0' and TMP < "111" and LOCK = false then + LOCK := true; + TMP := TMP + '1'; -- Count 8 low bits to declare start condition valid. + elsif RXCLK = '0' then + LOCK := false; + end if; + end if; + + case TMP is + when "111" => STARTBIT <= true; + when others => STARTBIT <= false; + end case; + end process P_START_BIT; + + SDATA_IN_I <= SDATA_IN when CLK_MODE = '0' else -- Clock div by 1 mode. + SDATA_IN when ST = "00" else SDATA_DIV16; -- Synchronous mode. + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(4 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CLK_MODE = '0' then -- Divider off. + if RXCLK = '1' and STRB_LOCK = false then + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif RXCLK = '0' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode. + elsif SDATA_EDGE = '1' then +CLK_DIVCNT := "01100"; -- Div by 16 mode. + CLK_STRB <= '0'; -- Default. + CLK_2_STRB <= '0'; -- Default. + else + CLK_STRB <= '0'; -- Default. + CLK_2_STRB <= '0'; -- Default. + if CLK_DIVCNT > "00000" and RXCLK = '1' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_LOCK := true; + if CLK_DIVCNT = "01000" then + -- This strobe is asserted at half of the clock cycle. + -- It is used for the stop bit timing. + CLK_2_STRB <= '1'; + end if; + elsif CLK_DIVCNT = "00000" then + CLK_DIVCNT := "10000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + end if; + elsif RXCLK = '0' then + CLK_LOCK := false; + STRB_LOCK := false; + end if; + end if; + end process CLKDIV; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if RE = '0' then + SHIFT_REG <= x"00"; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then + SHIFT_REG <= SDATA_IN_I & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_M_CIP: process(RESETn, CLK) + -- In Synchronous mode this flag indicates wether a synchronous character M_CIP = '1' + -- or another character (M_CIP = '0') is transferred to the receive buffer. + -- In asynchronous mode the flag indicates sampling condition. + begin + if RESETn = '0' then + M_CIP <= '0'; + elsif CLK = '0' and CLK' event then + if RE = '0' then + M_CIP <= '0'; + elsif ST = "00" then -- Synchronous mode. + if RCV_STATE = SYNC and SHIFT_REG = SCR and RDRF = '0' then + M_CIP <= '1'; -- SCR transferred. + elsif RCV_STATE = SYNC and RDRF = '0' then + M_CIP <= '0'; -- No SCR transferred. + end if; + else -- Asynchronous mode. + case RCV_STATE is + when SAMPLE | PARITY | STOP1 | STOP2 => M_CIP <= '1'; -- Sampling. + when others => M_CIP <= '0'; -- No Sampling. + end case; + end if; + end if; + end process P_M_CIP; + + BREAK_DETECT: process(RESETn, CLK) + -- A break condition occurs, if there is no STOP1 bit and the + -- shift register contains zero data. + begin + if RESETn = '0' then + BREAK <= false; + elsif CLK = '1' and CLK' event then + if RE = '0' then + BREAK <= false; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG = x"00" then + BREAK <= true; -- Break detected (empty shift register and no stop bit). + elsif RCV_STATE = STOP1 and SDATA_IN_I = '1' then + BREAK <= false; -- UPDATE. + elsif RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then + BREAK <= false; -- UPDATE, but framing error. + end if; + end if; + end if; + end process BREAK_DETECT; + + P_FS_B: process(RESETn, CLK) + -- In the synchronous mode, this process provides the flag detecting the synchronous + -- character. In the asynchronous mode, the flag indicates a break condition. + variable FS_B_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + FS_B <= '0'; + FIRST_READ := false; + FS_B_I := '0'; + elsif CLK = '0' and CLK' event then + if RE = '0' then + FS_B <= '0'; + FS_B_I := '0'; + else + if ST = "00" then -- Synchronous operation. + if FS_CLR = '1' then + FS_B <= '0'; -- Clear during writing to the SCR. + elsif SHIFT_REG = SCR then + FS_B <= '1'; -- SCR detected. + end if; + else -- Asynchronous operation. + if RX_SAMPLE = '1' and BREAK = true then -- Break condition detected. + FS_B_I := '1'; -- Update. + elsif RX_SAMPLE = '1' then -- No break condition. + FS_B_I := '0'; -- Update. + elsif RSR_READ = '1' and FS_B_I = '1' then + -- If a break condition was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the break flag is reset + -- and the break condition disappears after a second read + -- (in time) of the receiver status register. + if FIRST_READ = false then + FS_B <= '1'; + FIRST_READ := true; + else + FS_B <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end if; + end if; + end process P_FS_B; + + P_BITCNT: process + begin + wait until CLK = '1' and CLK' event; + if RCV_STATE = SAMPLE and CLK_STRB = '1' and ST /= "00" then -- Asynchronous mode. + BITCNT <= BITCNT + '1'; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' and ST = "00" and FS_B = '1' then -- Synchronous mode. + BITCNT <= BITCNT + '1'; -- Count, if matched data found (FS_B = '1'). + elsif RCV_STATE /= SAMPLE then + BITCNT <= (others => '0'); + end if; + end process P_BITCNT; + + BUFFER_FULL: process(RESETn, CLK) + -- Receive data register full flag. + begin + if RESETn = '0' then + RDRF <= '0'; + elsif CLK = '1' and CLK' event then + if RE = '0' then + RDRF <= '0'; + elsif RX_SAMPLE = '1' then + RDRF <= '1'; -- Data register is full until now! + elsif UDR_READ = '1' then + RDRF <= '0'; -- After reading the data register ... + end if; + end if; + end process BUFFER_FULL; + + OVERRUN: process(RESETn, CLK) + variable OE_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + OE_I := '0'; + OE <= '0'; + FIRST_READ := false; + elsif CLK = '1' and CLK' event then + if RESETn = '0' then + OE_I := '0'; + OE <= '0'; + FIRST_READ := false; + elsif CLK_STRB = '1' and RCV_STATE = SYNC and BREAK = false then + -- Overrun appears if RDRF is '1' in this state and there + -- is no break condition. + OE_I := RDRF; + end if; + if RSR_READ = '1' and OE_I = '1' then + -- if an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OE_I goes low) after + -- a second read (in time) of the receiver data register. + if FIRST_READ = false then + OE <= '1'; + FIRST_READ := true; + else + OE <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end process OVERRUN; + + PARITY_TEST: process(RESETn, CLK) + variable PAR_TMP : bit; + variable P_ERR : bit; + begin + if RESETn = '0' then + PE <= '0'; + elsif CLK = '1' and CLK' event then + if RE = '0' then + PE <= '0'; + elsif RX_SAMPLE = '1' then + PE <= P_ERR; -- Update on load shift register to data register. + elsif CLK_STRB = '1' then -- Sample parity on clock strobe. + P_ERR := '0'; -- Initialise. + if RCV_STATE = PARITY then + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if P_ENA = '1' and P_EOn = '1' then -- Even parity. + P_ERR := PAR_TMP xor SDATA_IN_I; + elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity. + P_ERR := not PAR_TMP xor SDATA_IN_I; + elsif P_ENA = '0' then -- No parity. + P_ERR := '0'; + end if; + end if; + end if; + end if; + end process PARITY_TEST; + + FRAME_ERR: process(RESETn, CLK) + -- This module detects a framing error + -- during stop bit 1 and stop bit 2. + variable FE_I: bit; + begin + if RESETn = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK = '1' and CLK' event then + if RE = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then + FE_I := '1'; + elsif RCV_STATE = STOP2 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then + FE_I := '1'; + elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then + FE_I := '0'; -- Error resets when correct data appears. + end if; + end if; + if RCV_STATE = SYNC then + FE <= FE_I; -- Update the FE every SYNC time. + end if; + end if; + end process FRAME_ERR; + + RCV_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + RCV_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if RE = '0' then + RCV_STATE <= IDLE; + else + RCV_STATE <= RCV_NEXT_STATE; + end if; + end if; + end process RCV_STATEREG; + + RCV_STATEDEC: process(RCV_STATE, SDATA_IN_I, BITCNT, CLK_STRB, STARTBIT, + CLK_2_STRB, ST, CLK_MODE, CL, P_ENA, SHIFT_REG) + begin + case RCV_STATE is + when IDLE => + if ST = "00" then + RCV_NEXT_STATE <= SAMPLE; -- Synchronous mode. + elsif SDATA_IN_I = '0' and CLK_MODE = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. + elsif STARTBIT = true and CLK_MODE = '1' then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. + else + RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) + end if; + when WAIT_START => + -- This state delays the sample process by one CLK_STRB pulse + -- to eliminate the start bit. + if CLK_STRB = '1' then + RCV_NEXT_STATE <= SAMPLE; + else + RCV_NEXT_STATE <= WAIT_START; + end if; + when SAMPLE => + if CLK_STRB = '1' then + if CL = "11" and BITCNT < "100" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data bits. + elsif CL = "10" and BITCNT < "101" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data bits. + elsif CL = "01" and BITCNT < "110" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. + elsif CL = "00" and BITCNT < "111" then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. + elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop bits). + RCV_NEXT_STATE <= IDLE; -- No parity check enabled. + elsif P_ENA = '0' then + RCV_NEXT_STATE <= STOP1; -- No parity check enabled. + else + RCV_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. + end if; + when PARITY => + if CLK_STRB = '1' then + if ST = "00" then -- Synchronous mode (no stop bits). + RCV_NEXT_STATE <= IDLE; + else + RCV_NEXT_STATE <= STOP1; + end if; + else + RCV_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' then + if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop bit after non zero data. + RCV_NEXT_STATE <= SYNC; -- Framing error detected. + elsif ST = "11" or ST = "10" then + RCV_NEXT_STATE <= STOP2; -- More than one stop bits selected. + else + RCV_NEXT_STATE <= SYNC; -- One stop bit selected. + end if; + else + RCV_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_2_STRB = '1' and ST = "10" then + RCV_NEXT_STATE <= SYNC; -- One and a half stop bits selected. + elsif CLK_STRB = '1' then + RCV_NEXT_STATE <= SYNC; -- Two stop bits selected. + else + RCV_NEXT_STATE <= STOP2; + end if; + when SYNC => + RCV_NEXT_STATE <= IDLE; + end case; + end process RCV_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd new file mode 100644 index 0000000..fd06bf1 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd @@ -0,0 +1,238 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- MC68901 compatible multi function port core. ---- +---- ---- +---- This is the SUSKA MFP IP core USART top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +use work.wf68901ip_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_TOP is + port ( -- System control: + CLK : in bit; + RESETn : in bit; + + -- Asynchronous bus control: + DSn : in bit; + CSn : in bit; + RWn : in bit; + + -- Data and Adresses: + RS : in bit_vector(5 downto 1); + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_OUT_EN : out bit; + + -- Serial I/O control: + RC : in bit; -- Receiver clock. + TC : in bit; -- Transmitter clock. + SI : in bit; -- Serial input. + SO : out bit; -- Serial output. + SO_EN : out bit; -- Serial output enable. + + -- Interrupt channels: + RX_ERR_INT : out bit; -- Receiver errors. + RX_BUFF_INT : out bit; -- Receiver buffer full. + TX_ERR_INT : out bit; -- Transmitter errors. + TX_BUFF_INT : out bit; -- Transmitter buffer empty. + + -- DMA control: + RRn : out bit; + TRn : out bit + ); +end entity WF68901IP_USART_TOP; + +architecture STRUCTURE of WF68901IP_USART_TOP is + signal BF_I : bit; + signal BE_I : bit; + signal FE_I : bit; + signal OE_I : bit; + signal UE_I : bit; + signal PE_I : bit; + signal LOOPBACK_I : bit; + signal SD_LEVEL_I : bit; + signal SDATA_IN_I : bit; + signal SDATA_OUT_I : bit; + signal RXCLK_I : bit; + signal CLK_MODE_I : bit; + signal SCR_I : bit_vector(7 downto 0); + signal RX_SAMPLE_I : bit; + signal RX_DATA_I : bit_vector(7 downto 0); + signal TX_DATA_I : bit_vector(7 downto 0); + signal CL_I : bit_vector(1 downto 0); + signal ST_I : bit_vector(1 downto 0); + signal P_ENA_I : bit; + signal P_EOn_I : bit; + signal RE_I : bit; + signal TE_I : bit; + signal FS_CLR_I : bit; + signal SS_I : bit; + signal M_CIP_I : bit; + signal FS_B_I : bit; + signal BR_I : bit; + signal UDR_READ_I : bit; + signal UDR_WRITE_I : bit; + signal RSR_READ_I : bit; + signal TSR_READ_I : bit; + signal TX_END_I : bit; +begin + SO <= SDATA_OUT_I when TE_I = '1' else SD_LEVEL_I; + -- Loopback mode: + SDATA_IN_I <= SDATA_OUT_I when LOOPBACK_I = '1' and TE_I = '1' else -- Loopback, transmitter enabled. + '1' when LOOPBACK_I = '1' and TE_I = '0' else SI; -- Loopback, transmitter disabled. + + RXCLK_I <= TC when LOOPBACK_I = '1' else RC; + RRn <= '0' when BF_I = '1' and PE_I = '0' and FE_I = '0' else '1'; + TRn <= not BE_I; + + -- Interrupt sources: + RX_ERR_INT <= OE_I or PE_I or FE_I or FS_B_I; + RX_BUFF_INT <= BF_I; + TX_ERR_INT <= UE_I or TX_END_I; + TX_BUFF_INT <= BE_I; + + I_USART_CTRL: WF68901IP_USART_CTRL + port map( + CLK => CLK, + RESETn => RESETn, + DSn => DSn, + CSn => CSn, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN, + DATA_OUT => DATA_OUT, + DATA_OUT_EN => DATA_OUT_EN, + LOOPBACK => LOOPBACK_I, + SDOUT_EN => SO_EN, + SD_LEVEL => SD_LEVEL_I, + CLK_MODE => CLK_MODE_I, + RE => RE_I, + TE => TE_I, + P_ENA => P_ENA_I, + P_EOn => P_EOn_I, + BF => BF_I, + BE => BE_I, + FE => FE_I, + OE => OE_I, + UE => UE_I, + PE => PE_I, + M_CIP => M_CIP_I, + FS_B => FS_B_I, + SCR_OUT => SCR_I, + TX_DATA => TX_DATA_I, + RX_SAMPLE => RX_SAMPLE_I, + RX_DATA => RX_DATA_I, + SS => SS_I, + BR => BR_I, + CL => CL_I, + ST => ST_I, + FS_CLR => FS_CLR_I, + UDR_READ => UDR_READ_I, + UDR_WRITE => UDR_WRITE_I, + RSR_READ => RSR_READ_I, + TSR_READ => TSR_READ_I, + TX_END => TX_END_I + ); + + I_USART_RECEIVE: WF68901IP_USART_RX + port map ( + CLK => CLK, + RESETn => RESETn, + SCR => SCR_I, + RX_SAMPLE => RX_SAMPLE_I, + RX_DATA => RX_DATA_I, + CL => CL_I, + ST => ST_I, + P_ENA => P_ENA_I, + P_EOn => P_EOn_I, + CLK_MODE => CLK_MODE_I, + RE => RE_I, + FS_CLR => FS_CLR_I, + SS => SS_I, + RXCLK => RXCLK_I, + SDATA_IN => SDATA_IN_I, + RSR_READ => RSR_READ_I, + UDR_READ => UDR_READ_I, + M_CIP => M_CIP_I, + FS_B => FS_B_I, + BF => BF_I, + OE => OE_I, + PE => PE_I, + FE => FE_I + ); + + I_USART_TRANSMIT: WF68901IP_USART_TX + port map ( + CLK => CLK, + RESETn => RESETn, + SCR => SCR_I, + TX_DATA => TX_DATA_I, + SDATA_OUT => SDATA_OUT_I, + TXCLK => TC, + CL => CL_I, + ST => ST_I, + TE => TE_I, + BR => BR_I, + P_ENA => P_ENA_I, + P_EOn => P_EOn_I, + UDR_WRITE => UDR_WRITE_I, + TSR_READ => TSR_READ_I, + CLK_MODE => CLK_MODE_I, + TX_END => TX_END_I, + UE => UE_I, + BE => BE_I + ); +end architecture STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd new file mode 100644 index 0000000..8de27f3 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd @@ -0,0 +1,387 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI MFP compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This is the SUSKA MFP IP core USART transmitter file. ---- +---- ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- TDRE has now synchronous reset to meet preset requirement. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF68901IP_USART_TX is + port ( + CLK : in bit; + RESETn : in bit; + + SCR : in bit_vector(7 downto 0); -- Synchronous character. + TX_DATA : in bit_vector(7 downto 0); -- Normal data. + + SDATA_OUT : out bit; -- Serial data output. + TXCLK : in bit; -- Transmitter clock. + + CL : in bit_vector(1 downto 0); -- Character length. + ST : in bit_vector(1 downto 0); -- Start and stop bit configuration. + TE : in bit; -- Transmitter enable. + BR : in bit; -- BREAK character send enable (all '0' without stop bit). + P_ENA : in bit; -- Parity enable. + P_EOn : in bit; -- Even or odd parity. + UDR_WRITE : in bit; -- Flag indicating writing the data register. + TSR_READ : in bit; -- Flag indicating reading the transmitter status register. + CLK_MODE : in bit; -- Transmitter clock mode. + + TX_END : out bit; -- End of transmission flag. + UE : out bit; -- Underrun Flag. + BE : out bit -- Buffer empty flag. + ); +end entity WF68901IP_USART_TX; + +architecture BEHAVIOR of WF68901IP_USART_TX is +type TR_STATES is (IDLE, CHECK_BREAK, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); +signal TR_STATE, TR_NEXT_STATE : TR_STATES; +signal CLK_STRB : bit; +signal CLK_2_STRB : bit; +signal SHIFT_REG : bit_vector(7 downto 0); +signal BITCNT : std_logic_vector(2 downto 0); +signal PARITY_I : bit; +signal TDRE : bit; +signal BREAK : bit; +begin + BE <= TDRE; -- Buffer empty flag. + + -- The default condition in this statement is to ensure + -- to cover all possibilities for example if there is a + -- one hot decoding of the state machine with wrong states + -- (e.g. not one of the given here). + SDATA_OUT <= '0' when BREAK = '1' else + '1' when TR_STATE = IDLE else + '1' when TR_STATE = LOAD_SHFT else + '0' when TR_STATE = START else + SHIFT_REG(0) when TR_STATE = SHIFTOUT else + PARITY_I when TR_STATE = PARITY else + '1' when TR_STATE = STOP1 else + '1' when TR_STATE = STOP2 else '1'; + + P_BREAK : process(RESETn, CLK) + -- This process is responsible to control the BREAK signal. After the break request + -- is asserted via BR, the break character will be sent after the current transmission has + -- finished. The BREAK character is sent until the BR is disabled. + variable LOCK : boolean; + begin + if RESETn = '0' then + BREAK <= '0'; + elsif CLK = '1' and CLK' event then + -- Break is only available in the asynchronous mode (ST /= "00"). + -- The LOCK mechanism is reponsible for sending the BREAK character just once. + if TE = '1' and BR = '1' and ST /= "00" and TR_STATE = IDLE and LOCK = false then + BREAK <= '1'; -- Break for the case that there is no current transmission. + LOCK := true; + elsif BR = '1' and ST /= "00" and TR_STATE = STOP1 then + BREAK <= '0'; -- Break character sent. + elsif BR = '0' then + BREAK <= '0'; + LOCK := false; + else + BREAK <= '0'; + end if; + end if; + end process P_BREAK; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(4 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CLK_MODE = '0' then -- Divider off. + if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif TXCLK = '1' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode. + elsif TR_STATE = IDLE then + CLK_DIVCNT := "10000"; -- Div by 16 mode. + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; -- Default. + CLK_2_STRB <= '0'; -- Default. + -- Works on negative TXCLK edge: + if CLK_DIVCNT > "00000" and TXCLK = '0' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_LOCK := true; + if CLK_DIVCNT = "01000" then + -- This strobe is asserted at half of the clock cycle. + -- It is used for the stop bit timing. + CLK_2_STRB <= '1'; + end if; + elsif CLK_DIVCNT = "00000" then + CLK_DIVCNT := "10000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + end if; + elsif TXCLK = '1' then + CLK_LOCK := false; + STRB_LOCK := false; + end if; + end if; + end process CLKDIV; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if TR_STATE = LOAD_SHFT and TDRE = '1' then -- Lost data ... + case ST is + when "00" => -- Synchronous mode. + SHIFT_REG <= SCR; -- Send the synchronous character. + when others => -- Asynchronous mode. + SHIFT_REG <= x"5A"; -- Load the shift register with a mark (underrun). + end case; + elsif TR_STATE = LOAD_SHFT then + -- Load 'normal' data if there is no break condition: + case CL is + when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits. + when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits. + when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits. + when "00" => SHIFT_REG <= TX_DATA; -- 8 databits. + end case; + elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then + SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + -- Counter for the data bits transmitted. + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = SHIFTOUT and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif TR_STATE /= SHIFTOUT then + BITCNT <= "000"; + end if; + end process P_BITCNT; + + BUFFER_EMPTY: process + -- Transmit data register empty flag. + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + TDRE <= '1'; + elsif TE = '0' then + TDRE <= '1'; + elsif TR_STATE = START and BREAK = '0' then + -- Data has been loaded to the shift register, + -- thus data register is free again. + -- If the BREAK flag is enabled, the BE flag + -- respective TDRE flag cannot be set. + TDRE <= '1'; + elsif UDR_WRITE = '1' then + TDRE <= '0'; + end if; + end process BUFFER_EMPTY; + + UNDERRUN: process(RESETn, CLK) + variable LOCK : boolean; + begin + if RESETn = '0' then + UE <= '0'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if TE = '0' then + UE <= '0'; + LOCK := false; + elsif CLK_STRB = '1' and TR_STATE = START then + -- Underrun appears if TDRE is '0' at the end of this state. + UE <= TDRE; -- Never true for enabled BREAK flag. See alos process BUFFER_EMPTY. + LOCK := true; + elsif CLK_STRB = '1' then + LOCK := false; -- Disables clearing UE one transmit clock cycle. + elsif TSR_READ = '1' and LOCK = false then + UE <= '0'; + end if; + end if; + end process UNDERRUN; + + P_TX_END: process(RESETn, CLK) + begin + if RESETn = '0' then + TX_END <= '0'; + elsif CLK = '1' and CLK' event then + if TE = '1' then -- Transmitter enabled. + TX_END <= '0'; + elsif TE = '0' and TR_STATE = IDLE then + TX_END <= '1'; + end if; + end if; + end process P_TX_END; + + PARITY_GEN: process + variable PAR_TMP : bit; + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = START then -- Calculate the parity during the start phase. + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if P_ENA = '1' and P_EOn = '1' then -- Even parity. + PARITY_I <= PAR_TMP; + elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity. + PARITY_I <= not PAR_TMP; + else -- No parity. + PARITY_I <= '0'; + end if; + end if; + end process PARITY_GEN; + + TR_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TR_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + TR_STATE <= TR_NEXT_STATE; + end if; + end process TR_STATEREG; + + TR_STATEDEC: process(TR_STATE, CLK_STRB, CLK_2_STRB, BITCNT, TDRE, BREAK, TE, ST, P_ENA, CL, BR) + begin + case TR_STATE is + when IDLE => + -- This IDLE state is just one clock cycle and is required to give the + -- break process time to set the BREAK flag. + TR_NEXT_STATE <= CHECK_BREAK; + when CHECK_BREAK => + if BREAK = '1' then -- Send break character. + -- Do not load any data to the shift register, go directly + -- to the START state. + TR_NEXT_STATE <= START; + -- Start enabled transmitter, if the data register is not empty. + -- Do not send any further data for the case of an asserted BR flag. + elsif TE = '1' and TDRE = '0' and BR = '0' then + TR_NEXT_STATE <= LOAD_SHFT; + else + TR_NEXT_STATE <= IDLE; -- Go back, scan for BREAK. + end if; + when LOAD_SHFT => + TR_NEXT_STATE <= START; + when START => -- Send the start bit. + if CLK_STRB = '1' then + TR_NEXT_STATE <= SHIFTOUT; + else + TR_NEXT_STATE <= START; + end if; + when SHIFTOUT => + if CLK_STRB = '1' then + if BITCNT < "100" and CL = "11" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data bits. + elsif BITCNT < "101" and CL = "10" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data bits. + elsif BITCNT < "110" and CL = "01" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. + elsif BITCNT < "111" and CL = "00" then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. + elsif P_ENA = '0' and BREAK = '1' then + TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop bits. + elsif P_ENA = '0' and ST = "00" then + TR_NEXT_STATE <= IDLE; -- Synchronous mode, no parity check enabled. + elsif P_ENA = '0' then + TR_NEXT_STATE <= STOP1; -- Asynchronous mode, no parity check enabled. + else + TR_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + TR_NEXT_STATE <= SHIFTOUT; + end if; + when PARITY => + if CLK_STRB = '1' then + if ST = "00" then -- Synchronous mode (no stop bits). + TR_NEXT_STATE <= IDLE; + elsif BREAK = '1' then -- No stop bits during break condition. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; + end if; + else + TR_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' and (ST = "11" or ST = "10") then + TR_NEXT_STATE <= STOP2; -- More than one stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- One stop bits selected. + else + TR_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_2_STRB = '1' and ST = "10" then + TR_NEXT_STATE <= IDLE; -- One and a half stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- Two stop bits detected. + else + TR_NEXT_STATE <= STOP2; + end if; + end case; + end process TR_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd new file mode 100644 index 0000000..685fc02 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd @@ -0,0 +1,228 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI IP Core peripheral Add-On ---- +---- ---- +---- This file is part of the FPGA-ATARI project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This hardware provides an interface to connect to a SD-Card. ---- +---- ---- +---- This interface is based on the project 'SatanDisk' of ---- +---- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- +---- the original code, written in VERILOG. It is provided for ---- +---- the use in a system on programmable chips (SOPC). ---- +---- ---- +---- Timing: Use a clock frequency of 16MHz for this component. ---- +---- Use the same clock frequency for the connected AVR ---- +---- microcontroller. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2007 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +---- This hardware works with the original ATARI ---- +---- hard dik driver. ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 1.0 2007/01/05 WF +-- Initial Release. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF_SD_CARD is + port ( + -- System: + RESETn : in bit; + CLK : in bit; -- 16MHz, see above. + + -- ACSI section: + ACSI_A1 : in bit; + ACSI_CSn : in bit; + ACSI_ACKn : in bit; + ACSI_INTn : out bit; + ACSI_DRQn : out bit; + ACSI_D : inout std_logic_vector(7 downto 0); + + -- Microcontroller interface: + MC_D : inout std_logic_vector(7 downto 0); + MC_DO : in bit; + MC_PIO_DMAn : in bit; + MC_RWn : in bit; + MC_CLR_CMD : in bit; + MC_DONE : out bit; + MC_GOT_CMD : out bit + ); +end WF_SD_CARD; + +architecture BEHAVIOR of WF_SD_CARD is +signal DATA_REG : std_logic_vector(7 downto 0); +signal D0_REG : bit; +signal INT_REG : bit; +signal DRQ_REG : bit; +signal DONE_REG : bit; +signal GOT_CMD_REG : bit; +signal HOLD : bit; +signal PREV_CSn : bit; +signal PREV_ACKn : bit; +begin + MC_D <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => 'Z'); + ACSI_D <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => 'Z'); + ACSI_INTn <= INT_REG; + ACSI_DRQn <= DRQ_REG; + MC_DONE <= DONE_REG; + MC_GOT_CMD <= GOT_CMD_REG; + + P_DATA: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= (others => '0'); + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then + DATA_REG <= MC_D; -- Read from AVR to ACSI. + end if; + -- + if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D; -- Write from ACSI to AVR. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D; -- Write from ACSI to AVR. + end if; + end if; + end process P_DATA; + + P_SYNC: process + begin + wait until CLK = '1' and CLK' event; + PREV_CSn <= ACSI_CSn; + PREV_ACKn <= ACSI_ACKn; + end process P_SYNC; + + P_INT_DRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INT_REG <= '1'; -- No interrupt. + DRQ_REG <= '1'; -- No data request. + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. + INT_REG <= '0'; -- Release an interrupt. + DRQ_REG <= '1'; + elsif D0_REG = '0' and MC_DO = '1' then + INT_REG <= '1'; + DRQ_REG <= '0'; -- Release a data request. + end if; + -- + if MC_CLR_CMD = '1' then -- Clear done. + INT_REG <= '1'; -- Restore INT_REG. + DRQ_REG <= '1'; -- Restore DRQ_REG. + end if; + -- + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + if ACSI_CSn = '0' then + INT_REG <= '1'; + end if; + -- + if ACSI_ACKn = '0' then + DRQ_REG <= '1'; + end if; + end if; + end if; + end process P_INT_DRQ; + + P_HOLD: process(RESETn, CLK) + begin + if RESETn = '0' then + HOLD <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + HOLD <= '1'; + elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. + HOLD <= '1'; + elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. + HOLD <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + HOLD <= '0'; + end if; + end if; + end process P_HOLD; + + P_DONE: process(RESETn, CLK) + begin + if RESETn = '0' then + DONE_REG <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + DONE_REG <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + DONE_REG <= '0'; + elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + DONE_REG <= '0'; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + DONE_REG <= '0'; + end if; + end if; + end process P_DONE; + + P_DO_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + D0_REG <= '0'; + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + D0_REG <= MC_DO; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + D0_REG <= MC_DO; + end if; + end if; + end process P_DO_REG; + + P_GOT_CMD: process(RESETn, CLK) + begin + if RESETn = '0' then + GOT_CMD_REG <= '0'; + elsif CLK = '1' and CLK' event then + if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif MC_CLR_CMD = '1' then -- Clear done. + GOT_CMD_REG <= '0'; + end if; + end if; + end process P_GOT_CMD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd new file mode 100644 index 0000000..b1dfe91 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd @@ -0,0 +1,240 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI IP Core peripheral Add-On ---- +---- ---- +---- This file is part of the FPGA-ATARI project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This hardware provides an interface to connect to a SD-Card. ---- +---- ---- +---- This interface is based on the project 'SatanDisk' of ---- +---- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- +---- the original code, written in VERILOG. It is provided for ---- +---- the use in a system on programmable chips (SOPC). ---- +---- ---- +---- Timing: Use a clock frequency of 16MHz for this component. ---- +---- Use the same clock frequency for the connected AVR ---- +---- microcontroller. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +---- This hardware works with the original ATARI ---- +---- hard dik driver. ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K7A 2007/01/05 WF +-- Initial Release. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF_SD_CARD is + port ( + -- System: + RESETn : in bit; + CLK : in bit; -- 16MHz, see above. + + -- ACSI section: + ACSI_A1 : in bit; + ACSI_CSn : in bit; + ACSI_ACKn : in bit; + ACSI_INTn : out bit; + ACSI_DRQn : out bit; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out bit; + + -- Microcontroller interface: + MC_DO : in bit; + MC_PIO_DMAn : in bit; + MC_RWn : in bit; + MC_CLR_CMD : in bit; + MC_DONE : out bit; + MC_GOT_CMD : out bit; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out bit + ); +end WF_SD_CARD; + +architecture BEHAVIOR of WF_SD_CARD is +signal DATA_REG : std_logic_vector(7 downto 0); +signal D0_REG : bit; +signal INT_REG : bit; +signal DRQ_REG : bit; +signal DONE_REG : bit; +signal GOT_CMD_REG : bit; +signal HOLD : bit; +signal PREV_CSn : bit; +signal PREV_ACKn : bit; +begin + MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); + MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; + ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); +--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; +ACSI_D_EN <= '0'; -- Disabled. +--ACSI_INTn <= INT_REG; +ACSI_INTn <= '1'; -- Disabled. +--ACSI_DRQn <= DRQ_REG; +ACSI_DRQn <= '1'; -- Disabled. + MC_DONE <= DONE_REG; + MC_GOT_CMD <= GOT_CMD_REG; + + P_DATA: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= (others => '0'); + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then + DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. + end if; + -- + if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + end if; + end if; + end process P_DATA; + + P_SYNC: process + begin + wait until CLK = '1' and CLK' event; + PREV_CSn <= ACSI_CSn; + PREV_ACKn <= ACSI_ACKn; + end process P_SYNC; + + P_INT_DRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INT_REG <= '1'; -- No interrupt. + DRQ_REG <= '1'; -- No data request. + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. + INT_REG <= '0'; -- Release an interrupt. + DRQ_REG <= '1'; + elsif D0_REG = '0' and MC_DO = '1' then + INT_REG <= '1'; + DRQ_REG <= '0'; -- Release a data request. + end if; + -- + if MC_CLR_CMD = '1' then -- Clear done. + INT_REG <= '1'; -- Restore INT_REG. + DRQ_REG <= '1'; -- Restore DRQ_REG. + end if; + -- + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + if ACSI_CSn = '0' then + INT_REG <= '1'; + end if; + -- + if ACSI_ACKn = '0' then + DRQ_REG <= '1'; + end if; + end if; + end if; + end process P_INT_DRQ; + + P_HOLD: process(RESETn, CLK) + begin + if RESETn = '0' then + HOLD <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + HOLD <= '1'; + elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. + HOLD <= '1'; + elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. + HOLD <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + HOLD <= '0'; + end if; + end if; + end process P_HOLD; + + P_DONE: process(RESETn, CLK) + begin + if RESETn = '0' then + DONE_REG <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + DONE_REG <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + DONE_REG <= '0'; + elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + DONE_REG <= '0'; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + DONE_REG <= '0'; + end if; + end if; + end process P_DONE; + + P_DO_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + D0_REG <= '0'; + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + D0_REG <= MC_DO; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + D0_REG <= MC_DO; + end if; + end if; + end process P_DO_REG; + + P_GOT_CMD: process(RESETn, CLK) + begin + if RESETn = '0' then + GOT_CMD_REG <= '0'; + elsif CLK = '1' and CLK' event then +-- ?? ACSI_CSn doppelt! +if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif MC_CLR_CMD = '1' then -- Clear done. + GOT_CMD_REG <= '0'; + end if; + end if; + end process P_GOT_CMD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak new file mode 100644 index 0000000..0200dea --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak @@ -0,0 +1,239 @@ +---------------------------------------------------------------------- +---- ---- +---- ATARI IP Core peripheral Add-On ---- +---- ---- +---- This file is part of the FPGA-ATARI project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- This hardware provides an interface to connect to a SD-Card. ---- +---- ---- +---- This interface is based on the project 'SatanDisk' of ---- +---- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- +---- the original code, written in VERILOG. It is provided for ---- +---- the use in a system on programmable chips (SOPC). ---- +---- ---- +---- Timing: Use a clock frequency of 16MHz for this component. ---- +---- Use the same clock frequency for the connected AVR ---- +---- microcontroller. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +---- This hardware works with the original ATARI ---- +---- hard dik driver. ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K7A 2007/01/05 WF +-- Initial Release. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF_SD_CARD is + port ( + -- System: + RESETn : in bit; + CLK : in bit; -- 16MHz, see above. + + -- ACSI section: + ACSI_A1 : in bit; + ACSI_CSn : in bit; + ACSI_ACKn : in bit; + ACSI_INTn : out bit; + ACSI_DRQn : out bit; + ACSI_D_IN : in std_logic_vector(7 downto 0); + ACSI_D_OUT : out std_logic_vector(7 downto 0); + ACSI_D_EN : out bit; + + -- Microcontroller interface: + MC_DO : in bit; + MC_PIO_DMAn : in bit; + MC_RWn : in bit; + MC_CLR_CMD : in bit; + MC_DONE : out bit; + MC_GOT_CMD : out bit; + MC_D_IN : in std_logic_vector(7 downto 0); + MC_D_OUT : out std_logic_vector(7 downto 0); + MC_D_EN : out bit + ); +end WF_SD_CARD; + +architecture BEHAVIOR of WF_SD_CARD is +signal DATA_REG : std_logic_vector(7 downto 0); +signal D0_REG : bit; +signal INT_REG : bit; +signal DRQ_REG : bit; +signal DONE_REG : bit; +signal GOT_CMD_REG : bit; +signal HOLD : bit; +signal PREV_CSn : bit; +signal PREV_ACKn : bit; +begin + MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); + MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; + ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); +-- ???: +--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; +ACSI_D_EN <= '0'; + ACSI_INTn <= INT_REG; + ACSI_DRQn <= DRQ_REG; + MC_DONE <= DONE_REG; + MC_GOT_CMD <= GOT_CMD_REG; + + P_DATA: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= (others => '0'); + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then + DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. + end if; + -- + if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then + DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. + end if; + end if; + end process P_DATA; + + P_SYNC: process + begin + wait until CLK = '1' and CLK' event; + PREV_CSn <= ACSI_CSn; + PREV_ACKn <= ACSI_ACKn; + end process P_SYNC; + + P_INT_DRQ: process(RESETn, CLK) + begin + if RESETn = '0' then + INT_REG <= '1'; -- No interrupt. + DRQ_REG <= '1'; -- No data request. + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. + INT_REG <= '0'; -- Release an interrupt. + DRQ_REG <= '1'; + elsif D0_REG = '0' and MC_DO = '1' then + INT_REG <= '1'; + DRQ_REG <= '0'; -- Release a data request. + end if; + -- + if MC_CLR_CMD = '1' then -- Clear done. + INT_REG <= '1'; -- Restore INT_REG. + DRQ_REG <= '1'; -- Restore DRQ_REG. + end if; + -- + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + if ACSI_CSn = '0' then + INT_REG <= '1'; + end if; + -- + if ACSI_ACKn = '0' then + DRQ_REG <= '1'; + end if; + end if; + end if; + end process P_INT_DRQ; + + P_HOLD: process(RESETn, CLK) + begin + if RESETn = '0' then + HOLD <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + HOLD <= '1'; + elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. + HOLD <= '0'; + elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. + HOLD <= '1'; + elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. + HOLD <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + HOLD <= '0'; + end if; + end if; + end process P_HOLD; + + P_DONE: process(RESETn, CLK) + begin + if RESETn = '0' then + DONE_REG <= '0'; + elsif CLK = '1' and CLK' event then + if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then + DONE_REG <= '1'; + elsif MC_CLR_CMD = '1' then -- Clear done. + DONE_REG <= '0'; + elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + DONE_REG <= '0'; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + DONE_REG <= '0'; + end if; + end if; + end process P_DONE; + + P_DO_REG: process(RESETn, CLK) + begin + if RESETn = '0' then + D0_REG <= '0'; + elsif CLK = '1' and CLK' event then + if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. + D0_REG <= MC_DO; + elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. + D0_REG <= MC_DO; + end if; + end if; + end process P_DO_REG; + + P_GOT_CMD: process(RESETn, CLK) + begin + if RESETn = '0' then + GOT_CMD_REG <= '0'; + elsif CLK = '1' and CLK' event then +-- ?? ACSI_CSn doppelt! +--if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then + GOT_CMD_REG <= '1'; -- If command was received. + elsif MC_CLR_CMD = '1' then -- Clear done. + GOT_CMD_REG <= '0'; + end if; + end if; + end process P_GOT_CMD; +end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd new file mode 100644 index 0000000..9d048de --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd @@ -0,0 +1,84 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- ---- +---- This is the package file containing the component ---- +---- declarations. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; + +package WF2149IP_PKG is +type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS); + +component WF2149IP_WAVE + port( + RESETn : in bit; + SYS_CLK : in bit; + + WAV_STRB : in bit; + + ADR : in bit_vector(3 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + BUSCYCLE : in BUSCYCLES; + CTRL_REG : in bit_vector(5 downto 0); + + OUT_A : out bit; + OUT_B : out bit; + OUT_C : out bit + ); +end component; +end WF2149IP_PKG; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd new file mode 100644 index 0000000..3f5024a --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd @@ -0,0 +1,170 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- This IP core of the sound generator differs slightly from ---- +---- the original. Firstly it is a synchronous design without any ---- +---- latches (like assumed in the original chip). This required ---- +---- the introduction of a system adequate clock. In detail this ---- +---- SYS_CLK should on the one hand be fast enough to meet the ---- +---- timing requirements of the system's bus cycle and should one ---- +---- the other hand drive the PWM modules correctly. To meet both ---- +---- a SYS_CLK of 16MHz or above is recommended. ---- +---- Secondly, the original chip has an implemented DA converter. ---- +---- This feature is not possible in today's FPGAs. Therefore the ---- +---- converter is replaced by pulse width modulators. This solu- ---- +---- tion is very simple in comparison to other approaches like ---- +---- external DA converters with wave tables etc. The soltution ---- +---- with the pulse width modulators is probably not as accurate ---- +---- DAs with wavetables. For a detailed descrition of the hard- ---- +---- ware PWM filter look at the end of the wave file, where the ---- +---- pulse width modulators can be found. ---- +---- For a proper operation it is required, that the wave clock ---- +---- is lower than the system clock. A good choice is for example ---- +---- 2MHz for the wave clock and 16MHz for the system clock. ---- +---- ---- +---- Main module file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.wf2149ip_pkg.all; + +entity WF2149IP_TOP is + port( + + SYS_CLK : in bit; -- Read the inforation in the header! + RESETn : in bit; + + WAV_CLK : in bit; -- Read the inforation in the header! + SELn : in bit; + + BDIR : in bit; + BC2, BC1 : in bit; + + A9n, A8 : in bit; + DA : inout std_logic_vector(7 downto 0); + + IO_A : inout std_logic_vector(7 downto 0); + IO_B : inout std_logic_vector(7 downto 0); + + OUT_A : out bit; -- Analog (PWM) outputs. + OUT_B : out bit; + OUT_C : out bit + ); +end WF2149IP_TOP; + +architecture STRUCTURE of WF2149IP_TOP is +component WF2149IP_TOP_SOC + port( + SYS_CLK : in bit; + RESETn : in bit; + WAV_CLK : in bit; + SELn : in bit; + BDIR : in bit; + BC2, BC1 : in bit; + A9n, A8 : in bit; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out bit; + IO_A_IN : in bit_vector(7 downto 0); + IO_A_OUT : out bit_vector(7 downto 0); + IO_A_EN : out bit; + IO_B_IN : in bit_vector(7 downto 0); + IO_B_OUT : out bit_vector(7 downto 0); + IO_B_EN : out bit; + OUT_A : out bit; + OUT_B : out bit; + OUT_C : out bit + ); +end component; +-- +signal DA_OUT : std_logic_vector(7 downto 0); +signal DA_EN : bit; +signal IO_A_IN : bit_vector(7 downto 0); +signal IO_A_OUT : bit_vector(7 downto 0); +signal IO_A_EN : bit; +signal IO_B_IN : bit_vector(7 downto 0); +signal IO_B_OUT : bit_vector(7 downto 0); +signal IO_B_EN : bit; +begin + IO_A_IN <= To_BitVector(IO_A); + IO_B_IN <= To_BitVector(IO_B); + + IO_A <= To_StdLogicVector(IO_A_OUT) when IO_A_EN = '1' else (others => 'Z'); + IO_B <= To_StdLogicVector(IO_B_OUT) when IO_B_EN = '1' else (others => 'Z'); + + DA <= DA_OUT when DA_EN = '1' else (others => 'Z'); + + I_SOUND: WF2149IP_TOP_SOC + port map(SYS_CLK => SYS_CLK, + RESETn => RESETn, + WAV_CLK => WAV_CLK, + SELn => SELn, + BDIR => BDIR, + BC2 => BC2, + BC1 => BC1, + A9n => A9n, + A8 => A8, + DA_IN => DA, + DA_OUT => DA_OUT, + DA_EN => DA_EN, + IO_A_IN => IO_A_IN, + IO_A_OUT => IO_A_OUT, + IO_A_EN => IO_A_EN, + IO_B_IN => IO_B_IN, + IO_B_OUT => IO_B_OUT, + IO_B_EN => IO_B_EN, + OUT_A => OUT_A, + OUT_B => OUT_B, + OUT_C => OUT_C + ); +end STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd new file mode 100644 index 0000000..77ea5ef --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd @@ -0,0 +1,229 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- This IP core of the sound generator differs slightly from ---- +---- the original. Firstly it is a synchronous design without any ---- +---- latches (like assumed in the original chip). This required ---- +---- the introduction of a system adequate clock. In detail this ---- +---- SYS_CLK should on the one hand be fast enough to meet the ---- +---- timing requirements of the system's bus cycle and should one ---- +---- the other hand drive the PWM modules correctly. To meet both ---- +---- a SYS_CLK of 16MHz or above is recommended. ---- +---- Secondly, the original chip has an implemented DA converter. ---- +---- This feature is not possible in today's FPGAs. Therefore the ---- +---- converter is replaced by pulse width modulators. This solu- ---- +---- tion is very simple in comparison to other approaches like ---- +---- external DA converters with wave tables etc. The soltution ---- +---- with the pulse width modulators is probably not as accurate ---- +---- DAs with wavetables. For a detailed descrition of the hard- ---- +---- ware PWM filter look at the end of the wave file, where the ---- +---- pulse width modulators can be found. ---- +---- For a proper operation it is required, that the wave clock ---- +---- is lower than the system clock. A good choice is for example ---- +---- 2MHz for the wave clock and 16MHz for the system clock. ---- +---- ---- +---- Main module file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use work.wf2149ip_pkg.all; + +entity WF2149IP_TOP_SOC is + port( + + SYS_CLK : in bit; -- Read the inforation in the header! + RESETn : in bit; + + WAV_CLK : in bit; -- Read the inforation in the header! + SELn : in bit; + + BDIR : in bit; + BC2, BC1 : in bit; + + A9n, A8 : in bit; + DA_IN : in std_logic_vector(7 downto 0); + DA_OUT : out std_logic_vector(7 downto 0); + DA_EN : out bit; + + IO_A_IN : in bit_vector(7 downto 0); + IO_A_OUT : out bit_vector(7 downto 0); + IO_A_EN : out bit; + IO_B_IN : in bit_vector(7 downto 0); + IO_B_OUT : out bit_vector(7 downto 0); + IO_B_EN : out bit; + + OUT_A : out bit; -- Analog (PWM) outputs. + OUT_B : out bit; + OUT_C : out bit + ); +end WF2149IP_TOP_SOC; + +architecture STRUCTURE of WF2149IP_TOP_SOC is +signal BUSCYCLE : BUSCYCLES; +signal DATA_OUT_I : std_logic_vector(7 downto 0); +signal DATA_EN_I : bit; +signal WAV_STRB : bit; +signal ADR_I : bit_vector(3 downto 0); +signal CTRL_REG : bit_vector(7 downto 0); +signal PORT_A : bit_vector(7 downto 0); +signal PORT_B : bit_vector(7 downto 0); +begin + P_WAVSTRB: process(RESETn, SYS_CLK) + variable LOCK : boolean; + variable TMP : bit; + begin + if RESETn = '0' then + LOCK := false; + TMP := '0'; + elsif SYS_CLK = '1' and SYS_CLK' event then + if WAV_CLK = '1' and LOCK = false then + LOCK := true; + TMP := not TMP; -- Divider by 2. + case SELn is + when '1' => WAV_STRB <= '1'; + when others => WAV_STRB <= TMP; + end case; + elsif WAV_CLK = '0' then + LOCK := false; + WAV_STRB <= '0'; + else + WAV_STRB <= '0'; + end if; + end if; + end process P_WAVSTRB; + + with BDIR & BC2 & BC1 select + BUSCYCLE <= INACTIVE when "000" | "010" | "101", + ADDRESS when "001" | "100" | "111", + R_READ when "011", + R_WRITE when "110"; + + ADDRESSLATCH: process(RESETn, SYS_CLK) + -- This process is responsible to store the desired register + -- address. The default (after reset) is channel A fine tone + -- adjustment. + begin + if RESETn = '0' then + ADR_I <= (others => '0'); + elsif SYS_CLK = '1' and SYS_CLK' event then + if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then + ADR_I <= To_BitVector(DA_IN(3 downto 0)); + end if; + end if; + end process ADDRESSLATCH; + + P_CTRL_REG: process(RESETn, SYS_CLK) + -- THIS is the Control register for the mixer and for the I/O ports. + begin + if RESETn = '0' then + CTRL_REG <= x"00"; + elsif SYS_CLK = '1' and SYS_CLK' event then + if BUSCYCLE = R_WRITE and ADR_I = x"7" then + CTRL_REG <= To_BitVector(DA_IN); + end if; + end if; + end process P_CTRL_REG; + + DIG_PORTS: process(RESETn, SYS_CLK) + begin + if RESETn = '0' then + PORT_A <= x"00"; + PORT_B <= x"00"; + elsif SYS_CLK = '1' and SYS_CLK' event then + if BUSCYCLE = R_WRITE and ADR_I = x"E" then + PORT_A <= To_BitVector(DA_IN); + elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then + PORT_B <= To_BitVector(DA_IN); + end if; + end if; + end process DIG_PORTS; + -- Set port direction to input or to output: + IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0'; + IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0'; + IO_A_OUT <= PORT_A; + IO_B_OUT <= PORT_B; + + I_PSG_WAVE: WF2149IP_WAVE + port map( + RESETn => RESETn, + SYS_CLK => SYS_CLK, + + WAV_STRB => WAV_STRB, + + ADR => ADR_I, + DATA_IN => DA_IN, + DATA_OUT => DATA_OUT_I, + DATA_EN => DATA_EN_I, + + BUSCYCLE => BUSCYCLE, + CTRL_REG => CTRL_REG(5 downto 0), + + OUT_A => OUT_A, + OUT_B => OUT_B, + OUT_C => OUT_C + ); + + -- Read the ports and registers: + DA_EN <= '1' when DATA_EN_I = '1' else + '1' when BUSCYCLE = R_READ and ADR_I = x"7" else + '1' when BUSCYCLE = R_READ and ADR_I = x"E" else + '1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0'; + + DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff. + To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else + To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else + To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0'); + +end STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd new file mode 100644 index 0000000..d829f9b --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd @@ -0,0 +1,533 @@ +---------------------------------------------------------------------- +---- ---- +---- YM2149 compatible sound generator. ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- Model of the ST or STE's YM2149 sound generator. ---- +---- ---- +---- Waveform generator. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- NOISE_OUT has now synchronous reset to meet preset requirement. +-- Fixed a bug in the envelope generator. Thanks to Lyndon Amsdon finding it. +-- Correction of the schematic given in the end of this file. + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use work.wf2149ip_pkg.all; + +entity WF2149IP_WAVE is + port( + RESETn : in bit; + SYS_CLK : in bit; + + WAV_STRB : in bit; + + ADR : in bit_vector(3 downto 0); + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + BUSCYCLE : in BUSCYCLES; + CTRL_REG : in bit_vector(5 downto 0); + + OUT_A : out bit; + OUT_B : out bit; + OUT_C : out bit + ); +end entity WF2149IP_WAVE; + +architecture BEHAVIOR of WF2149IP_WAVE is +signal FREQUENCY_A : std_logic_vector(11 downto 0); +signal FREQUENCY_B : std_logic_vector(11 downto 0); +signal FREQUENCY_C : std_logic_vector(11 downto 0); +signal NOISE_FREQ : std_logic_vector(4 downto 0); +signal LEVEL_A : std_logic_vector(4 downto 0); +signal LEVEL_B : std_logic_vector(4 downto 0); +signal LEVEL_C : std_logic_vector(4 downto 0); +signal ENV_FREQ : std_logic_vector(15 downto 0); +signal ENV_SHAPE : std_logic_vector(3 downto 0); +signal ENV_RESET : boolean; +signal ENV_STRB : bit; +signal OSC_A_OUT : bit; +signal OSC_B_OUT : bit; +signal OSC_C_OUT : bit; +signal NOISE_OUT : bit; +signal AUDIO_A : bit; +signal AUDIO_B : bit; +signal AUDIO_C : bit; +signal VOL_ENV : std_logic_vector(4 downto 0); +signal AMPLITUDE_A : std_logic_vector(4 downto 0); +signal AMPLITUDE_B : std_logic_vector(4 downto 0); +signal AMPLITUDE_C : std_logic_vector(4 downto 0); +signal VOLUME_A : std_logic_vector(7 downto 0); +signal VOLUME_B : std_logic_vector(7 downto 0); +signal VOLUME_C : std_logic_vector(7 downto 0); +signal PWM_RAMP : std_logic_vector(7 downto 0); +begin + REGISTERS: process(RESETn, SYS_CLK) + -- This process is responsible for initialisation + -- and write access to the configuration registers. + begin + if RESETn = '0' then + FREQUENCY_A <= x"000"; + FREQUENCY_B <= x"000"; + FREQUENCY_C <= x"000"; + NOISE_FREQ <= "00000"; + LEVEL_A <= "00000"; + LEVEL_B <= "00000"; + LEVEL_C <= "00000"; + ENV_FREQ <= (others => '0'); + ENV_SHAPE <= "0000"; + elsif SYS_CLK = '1' and SYS_CLK' event then + ENV_RESET <= false; -- Initialize signal. + if BUSCYCLE = R_WRITE then + case ADR is + when x"0" => FREQUENCY_A(7 downto 0) <= DATA_IN; + when x"1" => FREQUENCY_A(11 downto 8) <= DATA_IN(3 downto 0); + when x"2" => FREQUENCY_B(7 downto 0) <= DATA_IN; + when x"3" => FREQUENCY_B(11 downto 8) <= DATA_IN(3 downto 0); + when x"4" => FREQUENCY_C(7 downto 0) <= DATA_IN; + when x"5" => FREQUENCY_C(11 downto 8) <= DATA_IN(3 downto 0); + when x"6" => NOISE_FREQ <= DATA_IN(4 downto 0); + when x"8" => LEVEL_A <= DATA_IN(4 downto 0); + when x"9" => LEVEL_B <= DATA_IN(4 downto 0); + when x"A" => LEVEL_C <= DATA_IN(4 downto 0); + when x"B" => ENV_FREQ(7 downto 0) <= DATA_IN; + when x"C" => ENV_FREQ(15 downto 8) <= DATA_IN; + ENV_RESET <= true; -- Initialize the envelope generator. + when x"D" => ENV_SHAPE <= DATA_IN(3 downto 0); + when others => null; + end case; + end if; + end if; + end process REGISTERS; + + -- Read back the configuration registers: + DATA_OUT <= FREQUENCY_A(7 downto 0) when BUSCYCLE = R_READ and ADR = x"0" else + "0000" & FREQUENCY_A(11 downto 8) when BUSCYCLE = R_READ and ADR = x"1" else + FREQUENCY_B(7 downto 0) when BUSCYCLE = R_READ and ADR = x"2" else + "0000" & FREQUENCY_B(11 downto 8) when BUSCYCLE = R_READ and ADR = x"3" else + FREQUENCY_C(7 downto 0) when BUSCYCLE = R_READ and ADR = x"4" else + "0000" & FREQUENCY_C(11 downto 8) when BUSCYCLE = R_READ and ADR = x"5" else + "000" & NOISE_FREQ when BUSCYCLE = R_READ and ADR = x"6" else + "000" & LEVEL_A when BUSCYCLE = R_READ and ADR = x"8" else + "000" & LEVEL_B when BUSCYCLE = R_READ and ADR = x"9" else + "000" & LEVEL_C when BUSCYCLE = R_READ and ADR = x"A" else + ENV_FREQ(7 downto 0) when BUSCYCLE = R_READ and ADR = x"B" else + ENV_FREQ(15 downto 8) when BUSCYCLE = R_READ and ADR = x"C" else + x"0" & ENV_SHAPE when BUSCYCLE = R_READ and ADR = x"D" else (others => '0'); + DATA_EN <= '1' when BUSCYCLE = R_READ and ADR >= x"0" and ADR <= x"6" else + '1' when BUSCYCLE = R_READ and ADR >= x"8" and ADR <= x"D" else '0'; + + MUSICGENERATOR: process(RESETn, SYS_CLK) + variable CLK_DIV : std_logic_vector(2 downto 0); + variable CNT_CH_A : std_logic_vector(11 downto 0); + variable CNT_CH_B : std_logic_vector(11 downto 0); + variable CNT_CH_C : std_logic_vector(11 downto 0); + begin + if RESETn = '0' then + CLK_DIV := "000"; + CNT_CH_A := (others => '0'); + CNT_CH_B := (others => '0'); + CNT_CH_C := (others => '0'); + OSC_A_OUT <= '0'; + OSC_B_OUT <= '0'; + OSC_C_OUT <= '0'; + elsif SYS_CLK = '1' and SYS_CLK' event then + if WAV_STRB = '1' then + -- Divider by 8 for the oscillators brings in connection + -- with the toggle flip flops CH_x_OUT the required divider + -- ratio of 16. + CLK_DIV := CLK_DIV + '1'; + + if CLK_DIV = "000" then + if FREQUENCY_A = x"000" then + CNT_CH_A := (others => '0'); + OSC_A_OUT <= '0'; + elsif CNT_CH_A = x"000" then + CNT_CH_A := FREQUENCY_A - '1' ; + OSC_A_OUT <= not OSC_A_OUT; + else + CNT_CH_A := CNT_CH_A - '1'; + end if; + + if FREQUENCY_B = x"000" then + CNT_CH_B := (others => '0'); + OSC_B_OUT <= '0'; + elsif CNT_CH_B = x"000" then + CNT_CH_B := FREQUENCY_B - '1' ; + OSC_B_OUT <= not OSC_B_OUT; + else + CNT_CH_B := CNT_CH_B - '1'; + end if; + + if FREQUENCY_C = x"000" then + CNT_CH_C := (others => '0'); + OSC_C_OUT <= '0'; + elsif CNT_CH_C = x"000" then + CNT_CH_C := FREQUENCY_C - '1' ; + OSC_C_OUT <= not OSC_C_OUT; + else + CNT_CH_C := CNT_CH_C - '1'; + end if; + end if; + end if; + end if; + end process MUSICGENERATOR; + + NOISEGENERATOR: process + -- The noise shift polynomial is taken from a template of Kazuhiro TSUJIKAWA's + -- (ESE Artists' factory) approach for a 2149 equivalent. But the implementation + -- is done in another way. + -- LFSR (linear feedback shift register polynomial: f(x) = x^17 + x^14 + 1. + variable CLK_DIV : std_logic_vector(3 downto 0); + variable CNT_NOISE : std_logic_vector(4 downto 0); + variable N_SHFT : std_logic_vector(16 downto 0); + begin + wait until SYS_CLK = '1' and SYS_CLK' event; + if RESETn = '0' then + CLK_DIV := x"0"; + CNT_NOISE := (others => '1'); -- Preset the polynomial shift register. + NOISE_OUT <= '1'; + elsif WAV_STRB = '1' then + -- Divider by 16 for the noise generator. + CLK_DIV := CLK_DIV + '1'; + if CLK_DIV = x"0" then + -- Noise frequency counter. + if NOISE_FREQ = "00000" then + CNT_NOISE := (others => '0'); + elsif CNT_NOISE = "00000" then + CNT_NOISE := NOISE_FREQ - '1' ; + N_SHFT := N_SHFT(15 downto 14) & not(N_SHFT(16) xor N_SHFT(13)) & + N_SHFT(12 downto 0) & not N_SHFT(16); + else + CNT_NOISE := CNT_NOISE - '1'; + end if; + end if; + end if; + NOISE_OUT <= To_Bit(N_SHFT(16)); + end process NOISEGENERATOR; + + ENVELOPE_PERIOD: process(RESETn, SYS_CLK) + -- The envelope period is controlled by the Envelope Frequency and the divider ratio which is + -- 256/32 = 8. For further information see the original data sheet. + variable ENV_CLK : std_logic_vector(18 downto 0); + variable LOCK : boolean; + begin + if RESETn = '0' then + ENV_STRB <= '0'; + ENV_CLK := (others => '0'); + LOCK := false; + elsif SYS_CLK = '1' and SYS_CLK' event then + if WAV_STRB = '1' and LOCK = false then + LOCK := true; + if ENV_FREQ = x"0000" then + ENV_STRB <= '0'; + elsif ENV_CLK = x"0000" & "000" then + ENV_CLK := (ENV_FREQ & "111") - '1' ; + ENV_STRB <= '1'; + else + ENV_CLK := ENV_CLK - '1'; + ENV_STRB <= '0'; + end if; + elsif WAV_STRB = '0' then + LOCK := false; + ENV_STRB <= '0'; + else + ENV_STRB <= '0'; + end if; + end if; + end process ENVELOPE_PERIOD; + + ENVELOPE: process(RESETn, SYS_CLK) + -- Envelope shapes: + -- case ENV_SHAPE: + -- + -- 0 0 x x \___ + -- + -- 0 1 x x /|___ + -- + -- 1 0 0 0 _|\|\|\|\| + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \| + -- + -- 1 1 0 0 /|/|/|/| + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /|___ + -- + variable ENV_STOP : boolean; + variable ENV_UP_DNn : bit; + begin + if RESETn = '0' then + VOL_ENV <= (others => '0'); + ENV_UP_DNn := '0'; + ENV_STOP := false; + elsif SYS_CLK = '1' and SYS_CLK' event then + if ENV_RESET = true then + ENV_STOP := false; + case ENV_SHAPE is + when "1011" | "1010" | "1001" | "1000" | "0011" | "0010" | "0001" | "0000" => + VOL_ENV <= "11111"; -- Start on top. + ENV_UP_DNn := '0'; + when others => + VOL_ENV <= "00000"; -- Start at bottom. + ENV_UP_DNn := '1'; + end case; + elsif ENV_STRB = '1' then + case ENV_SHAPE is + when "1001" | "0011" | "0010" | "0001" | "0000" => + if VOL_ENV > "00000" then + VOL_ENV <= VOL_ENV - '1'; + end if; + when "1111" | "0111" | "0110" | "0101" | "0100" => + if VOL_ENV < "11111" and ENV_STOP = false then + VOL_ENV <= VOL_ENV + '1'; + else + VOL_ENV <= "00000"; + ENV_STOP := true; + end if; + when "1000" => + VOL_ENV <= VOL_ENV - '1'; + when "1110" | "1010" => + if ENV_UP_DNn = '0' then + VOL_ENV <= VOL_ENV - '1'; + else + VOL_ENV <= VOL_ENV + '1'; + end if; + -- + if VOL_ENV = "00001" then + ENV_UP_DNn := '1'; + elsif VOL_ENV = "11110" then + ENV_UP_DNn := '0'; + end if; + when "1011" => + if VOL_ENV > "00000" and ENV_STOP = false then + VOL_ENV <= VOL_ENV - '1'; + else + VOL_ENV <= "11111"; + ENV_STOP := true; + end if; + when "1100" => + VOL_ENV <= VOL_ENV + '1'; + when "1101" => + if VOL_ENV < "11111" then + VOL_ENV <= VOL_ENV + '1'; + end if; + when others => null; -- Covers U, X, Z, W, H, L, -. + end case; + end if; + end if; + end process ENVELOPE; + + --MIXER: + -- The mixer controls are dependant on the mixer settings and the output of the + -- audio data for all three channels. The noise generator and the square wave + -- generators A, B and C are mixed together by a simple boolean OR. + AUDIO_A <= (OSC_A_OUT and not CTRL_REG(0)) or (NOISE_OUT and not CTRL_REG(3)); + AUDIO_B <= (OSC_B_OUT and not CTRL_REG(1)) or (NOISE_OUT and not CTRL_REG(4)); + AUDIO_C <= (OSC_C_OUT and not CTRL_REG(2)) or (NOISE_OUT and not CTRL_REG(5)); + + --LEVEL (e.g. volume control): + -- The linear amplitude for the DA converters of channel A, B or C are fixed + -- (LEVEL(3 downto 0)) or delivered by the envelope generator. + -- The following behavior is taken from the 2149 IP core of Mike J (www.fpgaarcade.com): + -- "make sure level 31 (env) = level 15 (tone)" + -- Thus there is a resulting & '1' modeling if LEVEL amplitudes are selected. + AMPLITUDE_A <= LEVEL_A(3 downto 0) & '1' when LEVEL_A(4) = '0' and AUDIO_A = '1' else + VOL_ENV when LEVEL_A(4) = '1' and AUDIO_A = '1' else "00000"; + AMPLITUDE_B <= LEVEL_B(3 downto 0) & '1' when LEVEL_B(4) = '0' and AUDIO_B = '1' else + VOL_ENV when LEVEL_B(4) = '1' and AUDIO_B = '1' else "00000"; + AMPLITUDE_C <= LEVEL_C(3 downto 0) & '1' when LEVEL_C(4) = '0' and AUDIO_C = '1' else + VOL_ENV when LEVEL_C(4) = '1' and AUDIO_C = '1' else "00000"; + + -- The values for the logarithmic DA converter volume controls are taken from the linear + -- mixer of Mike J's 2149 IP core (www.fpgaarcade.com). + with AMPLITUDE_A select + VOLUME_A <= x"FF" when "11111", + x"D9" when "11110", + x"BA" when "11101", + x"9F" when "11100", + x"88" when "11011", + x"74" when "11010", + x"63" when "11001", + x"54" when "11000", + x"48" when "10111", + x"3D" when "10110", + x"34" when "10101", + x"2C" when "10100", + x"25" when "10011", + x"1F" when "10010", + x"1A" when "10001", + x"16" when "10000", + x"13" when "01111", + x"10" when "01110", + x"0D" when "01101", + x"0B" when "01100", + x"09" when "01011", + x"08" when "01010", + x"07" when "01001", + x"06" when "01000", + x"05" when "00111", + x"04" when "00110", + x"03" when "00101", + x"03" when "00100", + x"02" when "00011", + x"02" when "00010", + x"01" when "00001", + x"00" when others; -- Also covers U, X, Z, W, H, L, -. + + with AMPLITUDE_B select + VOLUME_B <= x"FF" when "11111", + x"D9" when "11110", + x"BA" when "11101", + x"9F" when "11100", + x"88" when "11011", + x"74" when "11010", + x"63" when "11001", + x"54" when "11000", + x"48" when "10111", + x"3D" when "10110", + x"34" when "10101", + x"2C" when "10100", + x"25" when "10011", + x"1F" when "10010", + x"1A" when "10001", + x"16" when "10000", + x"13" when "01111", + x"10" when "01110", + x"0D" when "01101", + x"0B" when "01100", + x"09" when "01011", + x"08" when "01010", + x"07" when "01001", + x"06" when "01000", + x"05" when "00111", + x"04" when "00110", + x"03" when "00101", + x"03" when "00100", + x"02" when "00011", + x"02" when "00010", + x"01" when "00001", + x"00" when others; -- Also covers U, X, Z, W, H, L, -. + + with AMPLITUDE_C select + VOLUME_C <= x"FF" when "11111", + x"D9" when "11110", + x"BA" when "11101", + x"9F" when "11100", + x"88" when "11011", + x"74" when "11010", + x"63" when "11001", + x"54" when "11000", + x"48" when "10111", + x"3D" when "10110", + x"34" when "10101", + x"2C" when "10100", + x"25" when "10011", + x"1F" when "10010", + x"1A" when "10001", + x"16" when "10000", + x"13" when "01111", + x"10" when "01110", + x"0D" when "01101", + x"0B" when "01100", + x"09" when "01011", + x"08" when "01010", + x"07" when "01001", + x"06" when "01000", + x"05" when "00111", + x"04" when "00110", + x"03" when "00101", + x"03" when "00100", + x"02" when "00011", + x"02" when "00010", + x"01" when "00001", + x"00" when others; -- Also covers U, X, Z, W, H, L, -. + + DA_CONVERSION: process + -- The DA conversion for the three analog outputs is originally performed by a built in DA converter. + -- For this is not possible in current FPGA designs, the converter is replaced by three PWM units + -- operating at a frequency which is 100 times higher than the highest noise or music frequency which + -- is 2MHz/16 = 125kHz. So the PWM frequency requires about 12.5MHz or more. The design is done for + -- a PWM frequency of 16MHz). + begin + wait until SYS_CLK = '1' and SYS_CLK' event; + PWM_RAMP <= PWM_RAMP + '1'; + end process DA_CONVERSION; + OUT_A <= '0' when VOLUME_A = x"00" else '1' when PWM_RAMP < VOLUME_A else '0'; + OUT_B <= '0' when VOLUME_B = x"00" else '1' when PWM_RAMP < VOLUME_B else '0'; + OUT_C <= '0' when VOLUME_C = x"00" else '1' when PWM_RAMP < VOLUME_C else '0'; + -- + -- To obtain proper analog output it is necessary to install analog RC filters to the pulse width + -- outputs. An example is given for the direct wiring of the three analog outputs and for a system + -- clock frequency of 16MHz. The output circuitry looks in this case as follows: + -- + -- OUT_A ---------|1kOhm|-----------| |\ e.g. LM741 + -- |----------------------|+\ || + -- OUT_B ---------|1kOhm|-----------| | OP------||--- Analog Signal + -- | |-----|-/ | || + -- OUT_C ---------|1kOhm|-----------| | |/ | 4u7 + -- | |__________| + -- | + -- --- 10nF. + -- --- + -- | + -- | + -- --- + -- WF. +end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd new file mode 100644 index 0000000..e60cc43 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd @@ -0,0 +1,244 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- Control unit and status logic. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- CTRL_REG has now synchronous reset to meet preset requirements. +-- Process P_DCD has now synchronous reset to meet preset requirements. +-- IRQ_In has now synchronous reset to meet preset requirement. +-- Revision 2K9B 2009/12/24 WF +-- Fixed the interrupt logic. +-- Introduced a minor RTSn correction. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_CTRL_STATUS is + port ( + CLK : in bit; + RESETn : in bit; + + CS : in bit_vector(2 downto 0); -- Active if "011". + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Status register stuff: + RDRF : in bit; -- Receive data register full. + TDRE : in bit; -- Transmit data register empty. + DCDn : in bit; -- Data carrier detect. + CTSn : in bit; -- Clear to send. + FE : in bit; -- Framing error. + OVR : in bit; -- Overrun error. + PE : in bit; -- Parity error. + + -- Control register stuff: + MCLR : buffer bit; -- Master clear (high active). + RTSn : out bit; -- Request to send. + CDS : out bit_vector(1 downto 0); -- Clock control. + WS : out bit_vector(2 downto 0); -- Word select. + TC : out bit_vector(1 downto 0); -- Transmit control. + IRQn : out bit -- Interrupt request. + ); +end entity WF6850IP_CTRL_STATUS; + +architecture BEHAVIOR of WF6850IP_CTRL_STATUS is +signal CTRL_REG : bit_vector(7 downto 0); +signal STATUS_REG : bit_vector(7 downto 0); +signal RIE : bit; +signal IRQ_I : bit; +signal CTS_In : bit; +signal DCD_In : bit; +signal DCD_FLAGn : bit; +begin + P_SAMPLE: process + begin + wait until CLK = '0' and CLK' event; + CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. + DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. + end process P_SAMPLE; + + STATUS_REG(7) <= IRQ_I; + STATUS_REG(6) <= PE; + STATUS_REG(5) <= OVR; + STATUS_REG(4) <= FE; + STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. + STATUS_REG(2) <= DCD_FLAGn; + STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. + STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. + + DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; + + MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; + RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; + + CDS <= CTRL_REG(1 downto 0); + WS <= CTRL_REG(4 downto 2); + TC <= CTRL_REG(6 downto 5); + RIE <= CTRL_REG(7); + + P_IRQ: process + variable DCD_OVR_LOCK : boolean; + variable DCD_LOCK : boolean; + variable DCD_TRANS : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_OVR_LOCK := false; + IRQn <= '1'; + IRQ_I <= '0'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + DCD_OVR_LOCK := false; -- Enable reset by reading the status. + end if; + + -- Clear interrupts when disabled. + if CTRL_REG(7) = '0' then + IRQn <= '1'; + IRQ_I <= '0'; + elsif CTRL_REG(6 downto 5) /= "01" then + IRQn <= '1'; + IRQ_I <= '0'; + end if; + + -- Transmitter interrupt: + if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by writing to the transmit data register. + end if; + + -- Receiver interrupts: + if RDRF = '1' and RIE = '1' and DCD_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by reading the receive data register. + end if; + + if OVR = '1' and RIE = '1' then + IRQn <= '0'; + IRQ_I <= '1'; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + end if; + + if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then + IRQn <= '0'; + IRQ_I <= '1'; + -- DCD_TRANS is used to detect a low to high transition of DCDn. + DCD_TRANS := true; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + elsif DCD_In = '0' then + DCD_TRANS := false; + end if; + + -- The reset of the IRQ status flag: + -- Clear by writing to the transmit data register. + -- Clear by reading the receive data register. + if CS = "011" and RS = '1' and E = '1' then + IRQ_I <= '0'; + end if; + end process P_IRQ; + + CONTROL: process + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + CTRL_REG <= "01000000"; + elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then + CTRL_REG <= DATA_IN; + end if; + end process CONTROL; + + P_DCD: process + -- This process is some kind of tricky. Refer to the MC6850 data + -- sheet for more information. + variable READ_LOCK : boolean; + variable DCD_RELEASE : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_FLAGn <= '0'; -- This interrupt source must initialise low. + READ_LOCK := true; + DCD_RELEASE := false; + elsif MCLR = '1' then + DCD_FLAGn <= DCD_In; + READ_LOCK := true; + elsif DCD_In = '1' then + DCD_FLAGn <= '1'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then + -- Clear if receiver status register read access. + -- After data register has ben read and READ_LOCK again. + DCD_RELEASE := true; + READ_LOCK := true; + DCD_FLAGn <= DCD_In; + elsif DCD_In = '0' and DCD_RELEASE = true then + DCD_FLAGn <= '0'; + DCD_RELEASE := false; + end if; + end process P_DCD; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak new file mode 100644 index 0000000..a0ea9e4 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak @@ -0,0 +1,244 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- Control unit and status logic. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9A 2009/06/20 WF +-- CTRL_REG has now synchronous reset to meet preset requirements. +-- Process P_DCD has now synchronous reset to meet preset requirements. +-- IRQ_In has now synchronous reset to meet preset requirement. +-- Revision 2K9B 2009/12/24 WF +-- Fixed the interrupt logic. +-- Introduced a minor RTSn correction. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_CTRL_STATUS is + port ( + CLK : in bit; + RESETn : in bit; + + CS : in bit_vector(2 downto 0); -- Active if "011". + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + -- Status register stuff: + RDRF : in bit; -- Receive data register full. + TDRE : in bit; -- Transmit data register empty. + DCDn : in bit; -- Data carrier detect. + CTSn : in bit; -- Clear to send. + FE : in bit; -- Framing error. + OVR : in bit; -- Overrun error. + PE : in bit; -- Parity error. + + -- Control register stuff: + MCLR : buffer bit; -- Master clear (high active). + RTSn : out bit; -- Request to send. + CDS : out bit_vector(1 downto 0); -- Clock control. + WS : out bit_vector(2 downto 0); -- Word select. + TC : out bit_vector(1 downto 0); -- Transmit control. + IRQn : out bit -- Interrupt request. + ); +end entity WF6850IP_CTRL_STATUS; + +architecture BEHAVIOR of WF6850IP_CTRL_STATUS is +signal CTRL_REG : bit_vector(7 downto 0); +signal STATUS_REG : bit_vector(7 downto 0); +signal RIE : bit; +signal IRQ_I : bit; +signal CTS_In : bit; +signal DCD_In : bit; +signal DCD_FLAGn : bit; +begin + P_SAMPLE: process + begin + wait until CLK = '0' and CLK' event; + CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. + DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. + end process P_SAMPLE; + + STATUS_REG(7) <= IRQ_I; + STATUS_REG(6) <= PE; + STATUS_REG(5) <= OVR; + STATUS_REG(4) <= FE; + STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. + STATUS_REG(2) <= DCD_FLAGn; + STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. + STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. + + DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; + + MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; + RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; + + CDS <= CTRL_REG(1 downto 0); + WS <= CTRL_REG(4 downto 2); + TC <= CTRL_REG(6 downto 5); + RIE <= CTRL_REG(7); + + P_IRQ: process + variable DCD_OVR_LOCK : boolean; + variable DCD_LOCK : boolean; + variable DCD_TRANS : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_OVR_LOCK := false; + IRQn <= '1'; + IRQ_I <= '0'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + DCD_OVR_LOCK := false; -- Enable reset by reading the status. + end if; + +-- Clear interrupts when disabled. +if CTRL_REG(7) = '0' then + IRQn <= '1'; + IRQ_I <= '0'; +elsif CTRL_REG(6 downto 5) /= "01" then + IRQn <= '1'; + IRQ_I <= '0'; +end if; + + -- Transmitter interrupt: + if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by writing to the transmit data register. + end if; + + -- Receiver interrupts: + if RDRF = '1' and RIE = '1' and DCD_In = '0' then + IRQn <= '0'; + IRQ_I <= '1'; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + IRQn <= '1'; -- Clear by reading the receive data register. + end if; + + if OVR = '1' and RIE = '1' then + IRQn <= '0'; + IRQ_I <= '1'; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + end if; + + if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then + IRQn <= '0'; + IRQ_I <= '1'; + -- DCD_TRANS is used to detect a low to high transition of DCDn. + DCD_TRANS := true; + DCD_OVR_LOCK := true; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then + IRQn <= '1'; -- Clear by reading the receive data register after the status. + elsif DCD_In = '0' then + DCD_TRANS := false; + end if; + + -- The reset of the IRQ status flag: + -- Clear by writing to the transmit data register. + -- Clear by reading the receive data register. + if CS = "011" and RS = '1' and E = '1' then + IRQ_I <= '0'; + end if; + end process P_IRQ; + + CONTROL: process + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + CTRL_REG <= "01000000"; + elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then + CTRL_REG <= DATA_IN; + end if; + end process CONTROL; + + P_DCD: process + -- This process is some kind of tricky. Refer to the MC6850 data + -- sheet for more information. + variable READ_LOCK : boolean; + variable DCD_RELEASE : boolean; + begin + wait until CLK = '1' and CLK' event; + if RESETn = '0' then + DCD_FLAGn <= '0'; -- This interrupt source must initialise low. + READ_LOCK := true; + DCD_RELEASE := false; + elsif MCLR = '1' then + DCD_FLAGn <= DCD_In; + READ_LOCK := true; + elsif DCD_In = '1' then + DCD_FLAGn <= '1'; + elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then + -- Clear if receiver status register read access. + -- After data register has ben read and READ_LOCK again. + DCD_RELEASE := true; + READ_LOCK := true; + DCD_FLAGn <= DCD_In; + elsif DCD_In = '0' and DCD_RELEASE = true then + DCD_FLAGn <= '0'; + DCD_RELEASE := false; + end if; + end process P_DCD; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd new file mode 100644 index 0000000..755e018 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd @@ -0,0 +1,415 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's receiver unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_RECEIVE is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + RXCLK : in bit; + RXDATA : in bit; + + RDRF : buffer bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end entity WF6850IP_RECEIVE; + +architecture BEHAVIOR of WF6850IP_RECEIVE is +type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); +signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; +signal RXDATA_I : bit; +signal RXDATA_S : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal CLK_STRB : bit; +signal BITCNT : std_logic_vector(2 downto 0); +begin + P_SAMPLE: process + -- This filter provides a synchronisation to the system + -- clock, even for random baud rates of the received data + -- stream. + variable FLT_TMP : integer range 0 to 2; + begin + wait until CLK = '1' and CLK' event; + -- + RXDATA_I <= RXDATA; + -- + if RXDATA_I = '1' and FLT_TMP < 2 then + FLT_TMP := FLT_TMP + 1; + elsif RXDATA_I = '1' then + RXDATA_S <= '1'; + elsif RXDATA_I = '0' and FLT_TMP > 0 then + FLT_TMP := FLT_TMP - 1; + elsif RXDATA_I = '0' then + RXDATA_S <= '0'; + end if; + end process P_SAMPLE; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- Divider off. + if RXCLK = '1' and STRB_LOCK = false then + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif RXCLK = '0' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif RCV_STATE = IDLE then + -- Preset the CLKDIV with the start delays. + if CDS = "01" then + CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. + elsif CDS = "10" then + CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. + end if; + CLK_STRB <= '0'; + else + if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + -- + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif RXCLK = '0' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= '0' & SHIFT_REG(7 downto 1); + elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= SHIFT_REG; + end if; + end if; + end process DATAREG; + DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then + SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + begin + wait until CLK = '1' and CLK' event; + if RCV_STATE = SAMPLE and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif RCV_STATE /= SAMPLE then + BITCNT <= (others => '0'); + end if; + end process P_BITCNT; + + FRAME_ERR: process(RESETn, CLK) + -- This module detects a framing error + -- during stop bit 1 and stop bit 2. + variable FE_I: bit; + begin + if RESETn = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + FE_I := '0'; + FE <= '0'; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP2 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then + FE_I := '0'; -- Error resets when correct data appears. + end if; + end if; + if RCV_STATE = SYNC then + FE <= FE_I; -- Update the FE every SYNC time. + end if; + end if; + end process FRAME_ERR; + + OVERRUN: process(RESETn, CLK) + variable OVR_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK_STRB = '1' and RCV_STATE = STOP1 then + -- Overrun appears if RDRF is '1' in this state. + OVR_I := RDRF; + end if; + if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then + -- If an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OVR_I goes low) after + -- a second read (in time) of the receiver data register. + if FIRST_READ = false then + OVR <= '1'; + FIRST_READ := true; + else + OVR <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end process OVERRUN; + + PARITY_TEST: process(RESETn, CLK) + variable PAR_TMP : bit; + variable PE_I : bit; + begin + if RESETn = '0' then + PE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + PE <= '0'; + elsif CLK_STRB = '1' then -- Sample parity on clock strobe. + PE_I := '0'; -- Initialise. + if RCV_STATE = PARITY then + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PE_I := PAR_TMP xor RXDATA_S; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PE_I := not PAR_TMP xor RXDATA_S; + else -- No parity for WS = "100" and WS = "101". + PE_I := '0'; + end if; + end if; + end if; + -- Transmit the parity flag together with the data + -- In other words: no parity to the status register + -- when RDRF inhibits the data transfer to the + -- receiver data register. + if RCV_STATE = SYNC and RDRF = '0' then + PE <= PE_I; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + PE <= '0'; -- Clear when reading the data register. + end if; + end if; + end process PARITY_TEST; + + P_RDRF: process(RESETn, CLK) + -- Receive data register full flag. + begin + if RESETn = '0' then + RDRF <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RDRF <= '0'; + elsif RCV_STATE = SYNC then + RDRF <= '1'; -- Data register is full until now! + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + RDRF <= '0'; -- After reading the data register ... + end if; + end if; + end process P_RDRF; + + RCV_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + RCV_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RCV_STATE <= IDLE; + else + RCV_STATE <= RCV_NEXT_STATE; + end if; + end if; + end process RCV_STATEREG; + + RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) + begin + case RCV_STATE is + when IDLE => + if RXDATA_S = '0' and CDS = "00" then + RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. + elsif RXDATA_S = '0' and CDS = "01" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. + elsif RXDATA_S = '0' and CDS = "10" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. + else + RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) + end if; + when WAIT_START => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. + else + RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. + end if; + else + RCV_NEXT_STATE <= WAIT_START; -- Stay. + end if; + when SAMPLE => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. + elsif WS = "100" or WS = "101" then + RCV_NEXT_STATE <= STOP1; -- No parity check enabled. + else + RCV_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. + end if; + when PARITY => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= STOP1; + else + RCV_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SYNC; -- Framing error detected. + elsif WS = "000" or WS = "001" or WS = "100" then + RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. + else + RCV_NEXT_STATE <= SYNC; -- One stop bit selected. + end if; + else + RCV_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= SYNC; + else + RCV_NEXT_STATE <= STOP2; + end if; + when SYNC => + RCV_NEXT_STATE <= IDLE; + end case; + end process RCV_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak new file mode 100644 index 0000000..e8c82b2 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak @@ -0,0 +1,415 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's receiver unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_RECEIVE is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + RXCLK : in bit; + RXDATA : in bit; + + RDRF : buffer bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end entity WF6850IP_RECEIVE; + +architecture BEHAVIOR of WF6850IP_RECEIVE is +type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); +signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; +signal RXDATA_I : bit; +signal RXDATA_S : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal CLK_STRB : bit; +signal BITCNT : std_logic_vector(2 downto 0); +begin + P_SAMPLE: process + -- This filter provides a synchronisation to the system + -- clock, even for random baud rates of the received data + -- stream. + variable FLT_TMP : integer range 0 to 2; + begin + wait until CLK = '1' and CLK' event; + -- + RXDATA_I <= RXDATA; + -- + if RXDATA_I = '1' and FLT_TMP < 2 then + FLT_TMP := FLT_TMP + 1; + elsif RXDATA_I = '1' then + RXDATA_S <= '1'; + elsif RXDATA_I = '0' and FLT_TMP > 0 then + FLT_TMP := FLT_TMP - 1; + elsif RXDATA_I = '0' then + RXDATA_S <= '0'; + end if; + end process P_SAMPLE; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- Divider off. + if RXCLK = '1' and STRB_LOCK = false then + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif RXCLK = '0' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif RCV_STATE = IDLE then + -- Preset the CLKDIV with the start delays. + if CDS = "01" then + CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. + elsif CDS = "10" then + CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. + end if; + CLK_STRB <= '0'; + else + if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + -- + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif RXCLK = '0' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= '0' & SHIFT_REG(7 downto 1); + elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= SHIFT_REG; + end if; + end if; + end process DATAREG; +--DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); +--DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; +DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0'); +DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0'; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then + SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + begin + wait until CLK = '1' and CLK' event; + if RCV_STATE = SAMPLE and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif RCV_STATE /= SAMPLE then + BITCNT <= (others => '0'); + end if; + end process P_BITCNT; + + FRAME_ERR: process(RESETn, CLK) + -- This module detects a framing error + -- during stop bit 1 and stop bit 2. + variable FE_I: bit; + begin + if RESETn = '0' then + FE_I := '0'; + FE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + FE_I := '0'; + FE <= '0'; + elsif CLK_STRB = '1' then + if RCV_STATE = STOP1 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP2 and RXDATA_S = '0' then + FE_I := '1'; + elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then + FE_I := '0'; -- Error resets when correct data appears. + end if; + end if; + if RCV_STATE = SYNC then + FE <= FE_I; -- Update the FE every SYNC time. + end if; + end if; + end process FRAME_ERR; + + OVERRUN: process(RESETn, CLK) + variable OVR_I : bit; + variable FIRST_READ : boolean; + begin + if RESETn = '0' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + OVR_I := '0'; + OVR <= '0'; + FIRST_READ := false; + elsif CLK_STRB = '1' and RCV_STATE = STOP1 then + -- Overrun appears if RDRF is '1' in this state. + OVR_I := RDRF; + end if; + if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then + -- If an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OVR_I goes low) after + -- a second read (in time) of the receiver data register. + if FIRST_READ = false then + OVR <= '1'; + FIRST_READ := true; + else + OVR <= '0'; + FIRST_READ := false; + end if; + end if; + end if; + end process OVERRUN; + + PARITY_TEST: process(RESETn, CLK) + variable PAR_TMP : bit; + variable PE_I : bit; + begin + if RESETn = '0' then + PE <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + PE <= '0'; + elsif CLK_STRB = '1' then -- Sample parity on clock strobe. + PE_I := '0'; -- Initialise. + if RCV_STATE = PARITY then + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PE_I := PAR_TMP xor RXDATA_S; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PE_I := not PAR_TMP xor RXDATA_S; + else -- No parity for WS = "100" and WS = "101". + PE_I := '0'; + end if; + end if; + end if; + -- Transmit the parity flag together with the data + -- In other words: no parity to the status register + -- when RDRF inhibits the data transfer to the + -- receiver data register. + if RCV_STATE = SYNC and RDRF = '0' then + PE <= PE_I; + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + PE <= '0'; -- Clear when reading the data register. + end if; + end if; + end process PARITY_TEST; + + P_RDRF: process(RESETn, CLK) + -- Receive data register full flag. + begin + if RESETn = '0' then + RDRF <= '0'; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RDRF <= '0'; + elsif RCV_STATE = SYNC then + RDRF <= '1'; -- Data register is full until now! + elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + RDRF <= '0'; -- After reading the data register ... + end if; + end if; + end process P_RDRF; + + RCV_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + RCV_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + RCV_STATE <= IDLE; + else + RCV_STATE <= RCV_NEXT_STATE; + end if; + end if; + end process RCV_STATEREG; + + RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) + begin + case RCV_STATE is + when IDLE => + if RXDATA_S = '0' and CDS = "00" then + RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. + elsif RXDATA_S = '0' and CDS = "01" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. + elsif RXDATA_S = '0' and CDS = "10" then + RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. + else + RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) + end if; + when WAIT_START => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. + else + RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. + end if; + else + RCV_NEXT_STATE <= WAIT_START; -- Stay. + end if; + when SAMPLE => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. + elsif WS = "100" or WS = "101" then + RCV_NEXT_STATE <= STOP1; -- No parity check enabled. + else + RCV_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. + end if; + when PARITY => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= STOP1; + else + RCV_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' then + if RXDATA_S = '0' then + RCV_NEXT_STATE <= SYNC; -- Framing error detected. + elsif WS = "000" or WS = "001" or WS = "100" then + RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. + else + RCV_NEXT_STATE <= SYNC; -- One stop bit selected. + end if; + else + RCV_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + RCV_NEXT_STATE <= SYNC; + else + RCV_NEXT_STATE <= STOP2; + end if; + when SYNC => + RCV_NEXT_STATE <= IDLE; + end case; + end process RCV_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd new file mode 100644 index 0000000..60a7885 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd @@ -0,0 +1,135 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- This is the top level file. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8B 2008/12/24 WF +-- Rewritten this top level file as a wrapper for the top_soc file. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TOP is + port ( + CLK : in bit; + RESETn : in bit; + + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + + DATA : inout std_logic_vector(7 downto 0); + + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + + IRQn : out std_logic; + TXDATA : out bit; + RTSn : out bit + ); +end entity WF6850IP_TOP; + +architecture STRUCTURE of WF6850IP_TOP is +component WF6850IP_TOP_SOC + port ( + CLK : in bit; + RESETn : in bit; + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + IRQn : out bit; + TXDATA : out bit; + RTSn : out bit + ); +end component; +signal DATA_OUT : std_logic_vector(7 downto 0); +signal DATA_EN : bit; +signal IRQ_In : bit; +begin + DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z'); + IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain. + + I_UART: WF6850IP_TOP_SOC + port map(CLK => CLK, + RESETn => RESETn, + CS2n => CS2n, + CS1 => CS1, + CS0 => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA, + DATA_OUT => DATA_OUT, + DATA_EN => DATA_EN, + TXCLK => TXCLK, + RXCLK => RXCLK, + RXDATA => RXDATA, + CTSn => CTSn, + DCDn => DCDn, + IRQn => IRQ_In, + TXDATA => TXDATA, + RTSn => RTSn + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd new file mode 100644 index 0000000..cbca6bd --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -0,0 +1,255 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- This is the top level file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K9B 2009/12/24 WF +-- Fixed the interrupt logic. +-- Introduced a minor RTSn correction. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TOP_SOC is + port ( + CLK : in bit; + RESETn : in bit; + + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + + IRQn : out bit; + TXDATA : out bit; + RTSn : out bit + ); +end entity WF6850IP_TOP_SOC; + +architecture STRUCTURE of WF6850IP_TOP_SOC is +component WF6850IP_CTRL_STATUS + port ( + CLK : in bit; + RESETn : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + RDRF : in bit; + TDRE : in bit; + DCDn : in bit; + CTSn : in bit; + FE : in bit; + OVR : in bit; + PE : in bit; + MCLR : out bit; + RTSn : out bit; + CDS : out bit_vector(1 downto 0); + WS : out bit_vector(2 downto 0); + TC : out bit_vector(1 downto 0); + IRQn : out bit + ); +end component; + +component WF6850IP_RECEIVE + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + RXCLK : in bit; + RXDATA : in bit; + RDRF : out bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end component; + +component WF6850IP_TRANSMIT + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + CTSn : in bit; + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + TXCLK : in bit; + TDRE : out bit; + TXDATA : out bit + ); +end component; +signal DATA_IN_I : bit_vector(7 downto 0); +signal DATA_RX : bit_vector(7 downto 0); +signal DATA_RX_EN : bit; +signal DATA_CTRL : bit_vector(7 downto 0); +signal DATA_CTRL_EN : bit; +signal RDRF_I : bit; +signal TDRE_I : bit; +signal FE_I : bit; +signal OVR_I : bit; +signal PE_I : bit; +signal MCLR_I : bit; +signal CDS_I : bit_vector(1 downto 0); +signal WS_I : bit_vector(2 downto 0); +signal TC_I : bit_vector(1 downto 0); +signal IRQ_In : bit; +begin + DATA_IN_I <= To_BitVector(DATA_IN); + DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; + DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else + To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); + + IRQn <= '0' when IRQ_In = '0' else '1'; + + I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS + port map( + CLK => CLK, + RESETn => RESETn, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_CTRL, + DATA_EN => DATA_CTRL_EN, + RDRF => RDRF_I, + TDRE => TDRE_I, + DCDn => DCDn, + CTSn => CTSn, + FE => FE_I, + OVR => OVR_I, + PE => PE_I, + MCLR => MCLR_I, + RTSn => RTSn, + CDS => CDS_I, + WS => WS_I, + TC => TC_I, + IRQn => IRQ_In + ); + + I_UART_RECEIVE: WF6850IP_RECEIVE + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_OUT => DATA_RX, + DATA_EN => DATA_RX_EN, + WS => WS_I, + CDS => CDS_I, + RXCLK => RXCLK, + RXDATA => RXDATA, + RDRF => RDRF_I, + OVR => OVR_I, + PE => PE_I, + FE => FE_I + ); + + I_UART_TRANSMIT: WF6850IP_TRANSMIT + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + CTSn => CTSn, + TC => TC_I, + WS => WS_I, + CDS => CDS_I, + TDRE => TDRE_I, + TXCLK => TXCLK, + TXDATA => TXDATA + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak new file mode 100644 index 0000000..6f80a67 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak @@ -0,0 +1,252 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- This is the top level file. ---- +---- Top level file for use in systems on programmable chips. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Top level file provided for SOC (systems on programmable chips). +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TOP_SOC is + port ( + CLK : in bit; + RESETn : in bit; + + CS2n, CS1, CS0 : in bit; + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in std_logic_vector(7 downto 0); + DATA_OUT : out std_logic_vector(7 downto 0); + DATA_EN : out bit; + + TXCLK : in bit; + RXCLK : in bit; + RXDATA : in bit; + CTSn : in bit; + DCDn : in bit; + + IRQn : out bit; + TXDATA : out bit; + RTSn : out bit + ); +end entity WF6850IP_TOP_SOC; + +architecture STRUCTURE of WF6850IP_TOP_SOC is +component WF6850IP_CTRL_STATUS + port ( + CLK : in bit; + RESETn : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + RDRF : in bit; + TDRE : in bit; + DCDn : in bit; + CTSn : in bit; + FE : in bit; + OVR : in bit; + PE : in bit; + MCLR : out bit; + RTSn : out bit; + CDS : out bit_vector(1 downto 0); + WS : out bit_vector(2 downto 0); + TC : out bit_vector(1 downto 0); + IRQn : out bit + ); +end component; + +component WF6850IP_RECEIVE + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_OUT : out bit_vector(7 downto 0); + DATA_EN : out bit; + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + RXCLK : in bit; + RXDATA : in bit; + RDRF : out bit; + OVR : out bit; + PE : out bit; + FE : out bit + ); +end component; + +component WF6850IP_TRANSMIT + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + DATA_IN : in bit_vector(7 downto 0); + CTSn : in bit; + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + TXCLK : in bit; + TDRE : out bit; + TXDATA : out bit + ); +end component; +signal DATA_IN_I : bit_vector(7 downto 0); +signal DATA_RX : bit_vector(7 downto 0); +signal DATA_RX_EN : bit; +signal DATA_CTRL : bit_vector(7 downto 0); +signal DATA_CTRL_EN : bit; +signal RDRF_I : bit; +signal TDRE_I : bit; +signal FE_I : bit; +signal OVR_I : bit; +signal PE_I : bit; +signal MCLR_I : bit; +signal CDS_I : bit_vector(1 downto 0); +signal WS_I : bit_vector(2 downto 0); +signal TC_I : bit_vector(1 downto 0); +signal IRQ_In : bit; +begin + DATA_IN_I <= To_BitVector(DATA_IN); + DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; + DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else + To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); + + IRQn <= '0' when IRQ_In = '0' else '1'; + + I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS + port map( + CLK => CLK, + RESETn => RESETn, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + DATA_OUT => DATA_CTRL, + DATA_EN => DATA_CTRL_EN, + RDRF => RDRF_I, + TDRE => TDRE_I, + DCDn => DCDn, + CTSn => CTSn, + FE => FE_I, + OVR => OVR_I, + PE => PE_I, + MCLR => MCLR_I, + RTSn => RTSn, + CDS => CDS_I, + WS => WS_I, + TC => TC_I, + IRQn => IRQ_In + ); + + I_UART_RECEIVE: WF6850IP_RECEIVE + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_OUT => DATA_RX, + DATA_EN => DATA_RX_EN, + WS => WS_I, + CDS => CDS_I, + RXCLK => RXCLK, + RXDATA => RXDATA, + RDRF => RDRF_I, + OVR => OVR_I, + PE => PE_I, + FE => FE_I + ); + + I_UART_TRANSMIT: WF6850IP_TRANSMIT + port map ( + CLK => CLK, + RESETn => RESETn, + MCLR => MCLR_I, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, + RWn => RWn, + RS => RS, + DATA_IN => DATA_IN_I, + CTSn => CTSn, + TC => TC_I, + WS => WS_I, + CDS => CDS_I, + TDRE => TDRE_I, + TXCLK => TXCLK, + TXDATA => TXDATA + ); +end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd new file mode 100644 index 0000000..c8ae6fc --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd @@ -0,0 +1,339 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's transmitter unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/11/01 WF +-- Fixed the T_DRE process concerning the TDRE <= '1' setting. +-- Thanks to Lyndon Amsdon finding the bug. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TRANSMIT is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + + CTSn : in bit; + + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + TXCLK : in bit; + + TDRE : buffer bit; + TXDATA : out bit + ); +end entity WF6850IP_TRANSMIT; + +architecture BEHAVIOR of WF6850IP_TRANSMIT is +type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); +signal TR_STATE, TR_NEXT_STATE : TR_STATES; +signal CLK_STRB : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal BITCNT : std_logic_vector(2 downto 0); +signal PARITY_I : bit; +begin + -- The default condition in this statement is to ensure + -- to cover all possibilities for example if there is a + -- one hot decoding of the state machine with wrong states + -- (e.g. not one of the given here). + TXDATA <= '1' when TR_STATE = IDLE else + '1' when TR_STATE = LOAD_SHFT else + '0' when TR_STATE = START else + SHIFT_REG(0) when TR_STATE = SHIFTOUT else + PARITY_I when TR_STATE = PARITY else + '1' when TR_STATE = STOP1 else + '1' when TR_STATE = STOP2 else '1'; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- divider off + if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif TXCLK = '1' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif TR_STATE = IDLE then + -- preset the CLKDIV with the start delays + if CDS = "01" then + CLK_DIVCNT := "0010000"; -- div by 16 mode + elsif CDS = "10" then + CLK_DIVCNT := "1000000"; -- div by 64 mode + end if; + CLK_STRB <= '0'; + else + -- Works on negative TXCLK edge: + if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif TXCLK = '1' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. + elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= DATA_IN; -- 8 bit data mode. + end if; + end if; + end process DATAREG; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif TR_STATE = LOAD_SHFT and TDRE = '0' then + -- If during LOAD_SHIFT the transmitter data register + -- is empty (TDRE = '1') the shift register will not + -- be loaded. When additionally TC = "11", the break + -- character (zero data and no stop bits) is sent. + SHIFT_REG <= DATA_REG; + elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then + SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + -- Counter for the data bits transmitted. + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = SHIFTOUT and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif TR_STATE /= SHIFTOUT then + BITCNT <= "000"; + end if; + end process P_BITCNT; + + P_TDRE: process(RESETn, CLK) + -- Transmit data register empty flag. + variable LOCK : boolean; + begin + if RESETn = '0' then + TDRE <= '1'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TDRE <= '1'; + elsif TR_NEXT_STATE = START and TR_STATE /= START then + -- Data has been loaded to shift register, thus data register is free again. + -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once + -- entering the state now. + TDRE <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then + LOCK := true; + elsif E = '0' and LOCK = true then + -- This construction clears TDRE after the falling edge of E + -- and after the transmit data register has been written to. + TDRE <= '0'; + LOCK := false; + end if; + end if; + end process P_TDRE; + + PARITY_GEN: process + variable PAR_TMP : bit; + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = START then -- Calculate the parity during the start phase. + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PARITY_I <= PAR_TMP; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PARITY_I <= not PAR_TMP; + else -- No parity for WS = "100" and WS = "101". + PARITY_I <= '0'; + end if; + end if; + end process PARITY_GEN; + + TR_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TR_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TR_STATE <= IDLE; + else + TR_STATE <= TR_NEXT_STATE; + end if; + end if; + end process TR_STATEREG; + + TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) + begin + case TR_STATE is + when IDLE => + if TDRE = '1' and TC = "11" then + TR_NEXT_STATE <= LOAD_SHFT; + elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. + TR_NEXT_STATE <= LOAD_SHFT; + else + TR_NEXT_STATE <= IDLE; + end if; + when LOAD_SHFT => + TR_NEXT_STATE <= START; + when START => + if CLK_STRB = '1' then + TR_NEXT_STATE <= SHIFTOUT; + else + TR_NEXT_STATE <= START; + end if; + when SHIFTOUT => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. + elsif WS = "100" or WS = "101" then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + TR_NEXT_STATE <= SHIFTOUT; + end if; + when PARITY => + if CLK_STRB = '1' then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then + TR_NEXT_STATE <= STOP2; -- Two stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- One stop bits selected. + else + TR_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP2; + end if; + end case; + end process TR_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak new file mode 100644 index 0000000..bcff094 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak @@ -0,0 +1,339 @@ +---------------------------------------------------------------------- +---- ---- +---- 6850 compatible IP Core ---- +---- ---- +---- This file is part of the SUSKA ATARI clone project. ---- +---- http://www.experiment-s.de ---- +---- ---- +---- Description: ---- +---- UART 6850 compatible IP core ---- +---- ---- +---- 6850's transmitter unit. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.gnu.org/licenses/lgpl.html ---- +---- ---- +---------------------------------------------------------------------- +-- +-- Revision History +-- +-- Revision 2K6A 2006/06/03 WF +-- Initial Release. +-- Revision 2K6B 2006/11/07 WF +-- Modified Source to compile with the Xilinx ISE. +-- Revision 2K8A 2008/07/14 WF +-- Minor changes. +-- Revision 2K8B 2008/11/01 WF +-- Fixed the T_DRE process concerning the TDRE <= '1' setting. +-- Thanks to Lyndon Amsdon finding the bug. +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +entity WF6850IP_TRANSMIT is + port ( + CLK : in bit; + RESETn : in bit; + MCLR : in bit; + + CS : in bit_vector(2 downto 0); + E : in bit; + RWn : in bit; + RS : in bit; + + DATA_IN : in bit_vector(7 downto 0); + + CTSn : in bit; + + TC : in bit_vector(1 downto 0); + WS : in bit_vector(2 downto 0); + CDS : in bit_vector(1 downto 0); + + TXCLK : in bit; + + TDRE : buffer bit; + TXDATA : out bit + ); +end entity WF6850IP_TRANSMIT; + +architecture BEHAVIOR of WF6850IP_TRANSMIT is +type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); +signal TR_STATE, TR_NEXT_STATE : TR_STATES; +signal CLK_STRB : bit; +signal DATA_REG : bit_vector(7 downto 0); +signal SHIFT_REG : bit_vector(7 downto 0); +signal BITCNT : std_logic_vector(2 downto 0); +signal PARITY_I : bit; +begin + -- The default condition in this statement is to ensure + -- to cover all possibilities for example if there is a + -- one hot decoding of the state machine with wrong states + -- (e.g. not one of the given here). + TXDATA <= '1' when TR_STATE = IDLE else + '1' when TR_STATE = LOAD_SHFT else + '0' when TR_STATE = START else + SHIFT_REG(0) when TR_STATE = SHIFTOUT else + PARITY_I when TR_STATE = PARITY else + '1' when TR_STATE = STOP1 else + '1' when TR_STATE = STOP2 else '1'; + + CLKDIV: process + variable CLK_LOCK : boolean; + variable STRB_LOCK : boolean; + variable CLK_DIVCNT : std_logic_vector(6 downto 0); + begin + wait until CLK = '1' and CLK' event; + if CDS = "00" then -- divider off + if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. + CLK_STRB <= '1'; + STRB_LOCK := true; + elsif TXCLK = '1' then + CLK_STRB <= '0'; + STRB_LOCK := false; + else + CLK_STRB <= '0'; + end if; + elsif TR_STATE = IDLE then + -- preset the CLKDIV with the start delays + if CDS = "01" then + CLK_DIVCNT := "0010000"; -- div by 16 mode + elsif CDS = "10" then + CLK_DIVCNT := "1000000"; -- div by 64 mode + end if; + CLK_STRB <= '0'; + else + -- Works on negative TXCLK edge: + if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + elsif CDS = "01" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif CDS = "10" and CLK_DIVCNT = "0000000" then + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + if STRB_LOCK = false then + STRB_LOCK := true; + CLK_STRB <= '1'; + else + CLK_STRB <= '0'; + end if; + elsif TXCLK = '1' then + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + else + CLK_STRB <= '0'; + end if; + end if; + end process CLKDIV; + + DATAREG: process(RESETn, CLK) + begin + if RESETn = '0' then + DATA_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + DATA_REG <= x"00"; + elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. + elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then + DATA_REG <= DATA_IN; -- 8 bit data mode. + end if; + end if; + end process DATAREG; + + SHIFTREG: process(RESETn, CLK) + begin + if RESETn = '0' then + SHIFT_REG <= x"00"; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + SHIFT_REG <= x"00"; + elsif TR_STATE = LOAD_SHFT and TDRE = '0' then + -- If during LOAD_SHIFT the transmitter data register + -- is empty (TDRE = '1') the shift register will not + -- be loaded. When additionally TC = "11", the break + -- character (zero data and no stop bits) is sent. + SHIFT_REG <= DATA_REG; + elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then + SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. + end if; + end if; + end process SHIFTREG; + + P_BITCNT: process + -- Counter for the data bits transmitted. + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = SHIFTOUT and CLK_STRB = '1' then + BITCNT <= BITCNT + '1'; + elsif TR_STATE /= SHIFTOUT then + BITCNT <= "000"; + end if; + end process P_BITCNT; + + P_TDRE: process(RESETn, CLK) + -- Transmit data register empty flag. + variable LOCK : boolean; + begin + if RESETn = '0' then + TDRE <= '1'; + LOCK := false; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TDRE <= '1'; + elsif TR_NEXT_STATE = START and TR_STATE /= START then + -- Data has been loaded to shift register, thus data register is free again. + -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once + -- entering the state now. + TDRE <= '1'; + elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then + LOCK := true; + elsif E = '0' and LOCK = true and CS /= "011" then + -- This construction clears TDRE after the falling edge of E + -- and after the transmit data register has been written to. + TDRE <= '0'; + LOCK := false; + end if; + end if; + end process P_TDRE; + + PARITY_GEN: process + variable PAR_TMP : bit; + begin + wait until CLK = '1' and CLK' event; + if TR_STATE = START then -- Calculate the parity during the start phase. + for i in 1 to 7 loop + if i = 1 then + PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); + else + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + end if; + end loop; + if WS = "000" or WS = "010" or WS = "110" then -- Even parity. + PARITY_I <= PAR_TMP; + elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. + PARITY_I <= not PAR_TMP; + else -- No parity for WS = "100" and WS = "101". + PARITY_I <= '0'; + end if; + end if; + end process PARITY_GEN; + + TR_STATEREG: process(RESETn, CLK) + begin + if RESETn = '0' then + TR_STATE <= IDLE; + elsif CLK = '1' and CLK' event then + if MCLR = '1' then + TR_STATE <= IDLE; + else + TR_STATE <= TR_NEXT_STATE; + end if; + end if; + end process TR_STATEREG; + + TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) + begin + case TR_STATE is + when IDLE => + if TDRE = '1' and TC = "11" then + TR_NEXT_STATE <= LOAD_SHFT; + elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. + TR_NEXT_STATE <= LOAD_SHFT; + else + TR_NEXT_STATE <= IDLE; + end if; + when LOAD_SHFT => + TR_NEXT_STATE <= START; + when START => + if CLK_STRB = '1' then + TR_NEXT_STATE <= SHIFTOUT; + else + TR_NEXT_STATE <= START; + end if; + when SHIFTOUT => + if CLK_STRB = '1' then + if BITCNT < "110" and WS(2) = '0' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. + elsif BITCNT < "111" and WS(2) = '1' then + TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. + elsif WS = "100" or WS = "101" then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; -- Parity enabled. + end if; + else + TR_NEXT_STATE <= SHIFTOUT; + end if; + when PARITY => + if CLK_STRB = '1' then + if TDRE = '1' and TC = "11" then + -- Break condition, do not send a stop bit. + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP1; -- No parity check enabled. + end if; + else + TR_NEXT_STATE <= PARITY; + end if; + when STOP1 => + if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then + TR_NEXT_STATE <= STOP2; -- Two stop bits selected. + elsif CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; -- One stop bits selected. + else + TR_NEXT_STATE <= STOP1; + end if; + when STOP2 => + if CLK_STRB = '1' then + TR_NEXT_STATE <= IDLE; + else + TR_NEXT_STATE <= STOP2; + end if; + end case; + end process TR_STATEDEC; +end architecture BEHAVIOR; + diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf new file mode 100644 index 0000000..f4d66a5 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf @@ -0,0 +1,95 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 168) + (text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 152 25 164)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) + (text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (drawing + (text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 152)(line_width 1)) + (line (pt 144 152)(pt 16 152)(line_width 1)) + (line (pt 16 152)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 132)(pt 144 132)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.cmp b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.cmp new file mode 100644 index 0000000..1f8ad52 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.cmp @@ -0,0 +1,28 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component dcfifo0 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.qip b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.qip new file mode 100644 index 0000000..a22ffe4 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.cmp"] diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd new file mode 100644 index 0000000..9db22fa --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo0.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo0 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +END dcfifo0; + + +ARCHITECTURE SYN OF dcfifo0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(9 DOWNTO 0); + q <= sub_wire1(31 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 1024, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 8, + lpm_widthu => 10, + lpm_widthu_r => 8, + lpm_width_r => 32, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "1024" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "32" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0] +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak new file mode 100644 index 0000000..c3ca670 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo0.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo0 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END dcfifo0; + + +ARCHITECTURE SYN OF dcfifo0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(4 DOWNTO 0); + q <= sub_wire1(15 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 32, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 8, + lpm_widthu => 5, + lpm_widthu_r => 4, + lpm_width_r => 16, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "32" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "16" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0] +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf new file mode 100644 index 0000000..7a4a386 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf @@ -0,0 +1,95 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 168) + (text "dcfifo1" (rect 62 1 105 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 152 25 164)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 160 96) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 111 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size 8))) + (text "rdusedw[9..0]" (rect 73 114 135 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 3)) + ) + (drawing + (text "32 bits x 256 words" (rect 63 140 144 152)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 152)(line_width 1)) + (line (pt 144 152)(pt 16 152)(line_width 1)) + (line (pt 16 152)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 132)(pt 144 132)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.cmp b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.cmp new file mode 100644 index 0000000..a1b8d55 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.cmp @@ -0,0 +1,28 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component dcfifo1 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.qip b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.qip new file mode 100644 index 0000000..bf1428c --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.cmp"] diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd new file mode 100644 index 0000000..d05dd0a --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo1.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo1 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); +END dcfifo1; + + +ARCHITECTURE SYN OF dcfifo1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + rdusedw : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + rdusedw <= sub_wire1(9 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 256, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 32, + lpm_widthu => 8, + lpm_widthu_r => 10, + lpm_width_r => 8, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + q => sub_wire0, + rdusedw => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "256" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "32" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0] +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak new file mode 100644 index 0000000..e7c6ae6 --- /dev/null +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo1.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo1 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END dcfifo1; + + +ARCHITECTURE SYN OF dcfifo1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(3 DOWNTO 0); + q <= sub_wire1(7 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 16, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 16, + lpm_widthu => 4, + lpm_widthu_r => 5, + lpm_width_r => 8, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "16" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "16" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0] +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf new file mode 100644 index 0000000..a455469 --- /dev/null +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -0,0 +1,478 @@ +TITLE "INTERRUPT HANDLER UND C1287"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_LONG.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + + +-- Parameters Statement (optional) + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + + +-- Subdesign Section + +SUBDESIGN interrupt_handler +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; + ANZAHL_TAGE_DES_MONATS[7..0]:NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; + +BEGIN +-- BYT SELECT + FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + INT_CTR[].CLK = MAIN_CLK; + INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 + INT_CTR[] = FB_AD[]; + INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; + INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; + INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; + INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + INT_ENA[].CLK = MAIN_CLK; + INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 + INT_ENA[] = FB_AD[]; + INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; + INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; + INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; + INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; +-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + INT_CLEAR[].CLK = MAIN_CLK; + INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 + INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; + INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; + INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; + INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT LATCH REGISTER READ ONLY + INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 +-- INTERRUPT + !nIRQ2 = HSYNC & INT_ENA[26]; + !nIRQ3 = INT_CTR0 & INT_ENA[27]; + !nIRQ4 = VSYNC & INT_ENA[28]; + nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; + !nIRQ6 = !nMFP_INT & INT_ENA[30]; + !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; + +PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC + # FB_ADR[19..4]==H"F8E0" -- VME + # FB_ADR[19..4]==H"F920" -- PADDLE + # FB_ADR[19..4]==H"F921" -- PADDLE + # FB_ADR[19..4]==H"F922" -- PADDLE + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..4]==H"FFA9" -- MFP2 + # FB_ADR[19..4]==H"FFAA" -- MFP2 + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..8]==H"F87" -- TT SCSI + # FB_ADR[19..4]==H"FFC2" -- ST UHR + # FB_ADR[19..4]==H"FFC3" -- ST UHR + # FB_ADR[19..4]==H"F890" -- DMA SOUND + # FB_ADR[19..4]==H"F891" -- DMA SOUND + # FB_ADR[19..4]==H"F892"); -- DMA SOUND +-- IF VIDEO ADR CHANGE +TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 + +-- INTERRUPT LATCH + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; + INT_LATCH1.CLK = E0_INT & INT_ENA[1]; + INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; + INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; + INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; + INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; + INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; + INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; + INT_LATCH8.CLK = VSYNC & INT_ENA[8]; + INT_LATCH9.CLK = HSYNC & INT_ENA[9]; + +-- INTERRUPT CLEAR + INT_LATCH[].CLRN = !INT_CLEAR[]; + +-- INT_IN + INT_IN0 = PIC_INT; + INT_IN1 = E0_INT; + INT_IN2 = DVI_INT; + INT_IN3 = !nPCI_INTA; + INT_IN4 = !nPCI_INTB; + INT_IN5 = !nPCI_INTC; + INT_IN6 = !nPCI_INTD; + INT_IN7 = DSP_INT; + INT_IN8 = VSYNC; + INT_IN9 = HSYNC; + INT_IN[25..10] = H"0"; + INT_IN26 = HSYNC; + INT_IN27 = INT_CTR0; + INT_IN28 = VSYNC; + INT_IN29 = INT_LATCH[]!=H"00000000"; + INT_IN30 = !nMFP_INT; + INT_IN31 = DMA_DRQ; +--*************************************************************************************** +-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + ACP_CONF[].CLK = MAIN_CLK; + ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 + ACP_CONF[] = FB_AD[]; + ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; + ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; + ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; + ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; +--*************************************************************************************** + +-------------------------------------------------------------- +-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR +---------------------------------------------------------- + RTC_ADR[].CLK = MAIN_CLK; + RTC_ADR[] = FB_AD[21..16]; + UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 + UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 + RTC_ADR[].ENA = UHR_AS & !nFB_WR; + WERTE[][].CLK = MAIN_CLK; + WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[7..0][1] = FB_AD[23..16]; + WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[7..0][3] = FB_AD[23..16]; + WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[7..0][5] = FB_AD[23..16]; + WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[7..0][10] = FB_AD[23..16]; + WERTE[7..0][11] = FB_AD[23..16]; + WERTE[7..0][12] = FB_AD[23..16]; + WERTE[7..0][13] = FB_AD[23..16]; + WERTE[7..0][14] = FB_AD[23..16]; + WERTE[7..0][15] = FB_AD[23..16]; + WERTE[7..0][16] = FB_AD[23..16]; + WERTE[7..0][17] = FB_AD[23..16]; + WERTE[7..0][18] = FB_AD[23..16]; + WERTE[7..0][19] = FB_AD[23..16]; + WERTE[7..0][20] = FB_AD[23..16]; + WERTE[7..0][21] = FB_AD[23..16]; + WERTE[7..0][22] = FB_AD[23..16]; + WERTE[7..0][23] = FB_AD[23..16]; + WERTE[7..0][24] = FB_AD[23..16]; + WERTE[7..0][25] = FB_AD[23..16]; + WERTE[7..0][26] = FB_AD[23..16]; + WERTE[7..0][27] = FB_AD[23..16]; + WERTE[7..0][28] = FB_AD[23..16]; + WERTE[7..0][29] = FB_AD[23..16]; + WERTE[7..0][30] = FB_AD[23..16]; + WERTE[7..0][31] = FB_AD[23..16]; + WERTE[7..0][32] = FB_AD[23..16]; + WERTE[7..0][33] = FB_AD[23..16]; + WERTE[7..0][34] = FB_AD[23..16]; + WERTE[7..0][35] = FB_AD[23..16]; + WERTE[7..0][36] = FB_AD[23..16]; + WERTE[7..0][37] = FB_AD[23..16]; + WERTE[7..0][38] = FB_AD[23..16]; + WERTE[7..0][39] = FB_AD[23..16]; + WERTE[7..0][40] = FB_AD[23..16]; + WERTE[7..0][41] = FB_AD[23..16]; + WERTE[7..0][42] = FB_AD[23..16]; + WERTE[7..0][43] = FB_AD[23..16]; + WERTE[7..0][44] = FB_AD[23..16]; + WERTE[7..0][45] = FB_AD[23..16]; + WERTE[7..0][46] = FB_AD[23..16]; + WERTE[7..0][47] = FB_AD[23..16]; + WERTE[7..0][48] = FB_AD[23..16]; + WERTE[7..0][49] = FB_AD[23..16]; + WERTE[7..0][50] = FB_AD[23..16]; + WERTE[7..0][51] = FB_AD[23..16]; + WERTE[7..0][52] = FB_AD[23..16]; + WERTE[7..0][53] = FB_AD[23..16]; + WERTE[7..0][54] = FB_AD[23..16]; + WERTE[7..0][55] = FB_AD[23..16]; + WERTE[7..0][56] = FB_AD[23..16]; + WERTE[7..0][57] = FB_AD[23..16]; + WERTE[7..0][58] = FB_AD[23..16]; + WERTE[7..0][59] = FB_AD[23..16]; + WERTE[7..0][60] = FB_AD[23..16]; + WERTE[7..0][61] = FB_AD[23..16]; + WERTE[7..0][62] = FB_AD[23..16]; + WERTE[7..0][63] = FB_AD[23..16]; + WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; + WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; + WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; + WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; + WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; + WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; + WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; + WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; + WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; + WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; + WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; + WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; + WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; + WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; + WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; + WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; + WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; + WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; + WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; + WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; + WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; + WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; + WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; + WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; + WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; + WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; + WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; + WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; + WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; + WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; + WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; + WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; + WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; + WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; + WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; + WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; + WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; + WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; + WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; + WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; + WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; + WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; + WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; + WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; + WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; + WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; + WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; + WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; + WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; + WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; + WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; + WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; + WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; + WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; + WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; + WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; + WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; + PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; + PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; + PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; + WERTE[6][10].CLRN = GND; -- KEIN UIP + UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF + WERTE[2][11] = VCC; -- IMMER BINARY + WERTE[1][11] = VCC; -- IMMER 24H FORMAT + WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR + WERTE[7][13] = VCC; -- IMMER RICHTIG +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) + SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL + WERTE[0][13] = SOMMERZEIT; + WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); + WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER +-- ACHTELSEKUNDEN + ACHTELSEKUNDEN[].CLK = MAIN_CLK; + ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; + ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; +-- SEKUNDEN + INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); +-- MINUTEN + INC_MIN = INC_SEC & WERTE[][0]==59; -- + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- +-- STUNDEN + INC_STD = INC_MIN & WERTE[][2]==59; + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT +-- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); + ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) + # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) + # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 + # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- +-- MONATE + INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); +-- JAHR + INC_JAHR = INC_MONAT & WERTE[][8]==12; -- + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); +-- TRISTATE OUTPUT + + FB_AD[31..24] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[31..24] + # INT_ENA_CS & INT_ENA[31..24] + # INT_LATCH_CS & INT_LATCH[31..24] + # INT_CLEAR_CS & INT_IN[31..24] + # ACP_CONF_CS & ACP_CONF[31..24] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[23..16] = lpm_bustri_BYT( + WERTE[][0] & RTC_ADR[]==0 & UHR_DS + # WERTE[][1] & RTC_ADR[]==1 & UHR_DS + # WERTE[][2] & RTC_ADR[]==2 & UHR_DS + # WERTE[][3] & RTC_ADR[]==3 & UHR_DS + # WERTE[][4] & RTC_ADR[]==4 & UHR_DS + # WERTE[][5] & RTC_ADR[]==5 & UHR_DS + # WERTE[][6] & RTC_ADR[]==6 & UHR_DS + # WERTE[][7] & RTC_ADR[]==7 & UHR_DS + # WERTE[][8] & RTC_ADR[]==8 & UHR_DS + # WERTE[][9] & RTC_ADR[]==9 & UHR_DS + # WERTE[][10] & RTC_ADR[]==10 & UHR_DS + # WERTE[][11] & RTC_ADR[]==11 & UHR_DS + # WERTE[][12] & RTC_ADR[]==12 & UHR_DS + # WERTE[][13] & RTC_ADR[]==13 & UHR_DS + # WERTE[][14] & RTC_ADR[]==14 & UHR_DS + # WERTE[][15] & RTC_ADR[]==15 & UHR_DS + # WERTE[][16] & RTC_ADR[]==16 & UHR_DS + # WERTE[][17] & RTC_ADR[]==17 & UHR_DS + # WERTE[][18] & RTC_ADR[]==18 & UHR_DS + # WERTE[][19] & RTC_ADR[]==19 & UHR_DS + # WERTE[][20] & RTC_ADR[]==20 & UHR_DS + # WERTE[][21] & RTC_ADR[]==21 & UHR_DS + # WERTE[][22] & RTC_ADR[]==22 & UHR_DS + # WERTE[][23] & RTC_ADR[]==23 & UHR_DS + # WERTE[][24] & RTC_ADR[]==24 & UHR_DS + # WERTE[][25] & RTC_ADR[]==25 & UHR_DS + # WERTE[][26] & RTC_ADR[]==26 & UHR_DS + # WERTE[][27] & RTC_ADR[]==27 & UHR_DS + # WERTE[][28] & RTC_ADR[]==28 & UHR_DS + # WERTE[][29] & RTC_ADR[]==29 & UHR_DS + # WERTE[][30] & RTC_ADR[]==30 & UHR_DS + # WERTE[][31] & RTC_ADR[]==31 & UHR_DS + # WERTE[][32] & RTC_ADR[]==32 & UHR_DS + # WERTE[][33] & RTC_ADR[]==33 & UHR_DS + # WERTE[][34] & RTC_ADR[]==34 & UHR_DS + # WERTE[][35] & RTC_ADR[]==35 & UHR_DS + # WERTE[][36] & RTC_ADR[]==36 & UHR_DS + # WERTE[][37] & RTC_ADR[]==37 & UHR_DS + # WERTE[][38] & RTC_ADR[]==38 & UHR_DS + # WERTE[][39] & RTC_ADR[]==39 & UHR_DS + # WERTE[][40] & RTC_ADR[]==40 & UHR_DS + # WERTE[][41] & RTC_ADR[]==41 & UHR_DS + # WERTE[][42] & RTC_ADR[]==42 & UHR_DS + # WERTE[][43] & RTC_ADR[]==43 & UHR_DS + # WERTE[][44] & RTC_ADR[]==44 & UHR_DS + # WERTE[][45] & RTC_ADR[]==45 & UHR_DS + # WERTE[][46] & RTC_ADR[]==46 & UHR_DS + # WERTE[][47] & RTC_ADR[]==47 & UHR_DS + # WERTE[][48] & RTC_ADR[]==48 & UHR_DS + # WERTE[][49] & RTC_ADR[]==49 & UHR_DS + # WERTE[][50] & RTC_ADR[]==50 & UHR_DS + # WERTE[][51] & RTC_ADR[]==51 & UHR_DS + # WERTE[][52] & RTC_ADR[]==52 & UHR_DS + # WERTE[][53] & RTC_ADR[]==53 & UHR_DS + # WERTE[][54] & RTC_ADR[]==54 & UHR_DS + # WERTE[][55] & RTC_ADR[]==55 & UHR_DS + # WERTE[][56] & RTC_ADR[]==56 & UHR_DS + # WERTE[][57] & RTC_ADR[]==57 & UHR_DS + # WERTE[][58] & RTC_ADR[]==58 & UHR_DS + # WERTE[][59] & RTC_ADR[]==59 & UHR_DS + # WERTE[][60] & RTC_ADR[]==60 & UHR_DS + # WERTE[][61] & RTC_ADR[]==61 & UHR_DS + # WERTE[][62] & RTC_ADR[]==62 & UHR_DS + # WERTE[][63] & RTC_ADR[]==63 & UHR_DS + # (0,RTC_ADR[]) & UHR_AS + # INT_CTR_CS & INT_CTR[23..16] + # INT_ENA_CS & INT_ENA[23..16] + # INT_LATCH_CS & INT_LATCH[23..16] + # INT_CLEAR_CS & INT_IN[23..16] + # ACP_CONF_CS & ACP_CONF[23..16] + ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[15..8] + # INT_ENA_CS & INT_ENA[15..8] + # INT_LATCH_CS & INT_LATCH[15..8] + # INT_CLEAR_CS & INT_IN[15..8] + # ACP_CONF_CS & ACP_CONF[15..8] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[7..0] + # INT_ENA_CS & INT_ENA[7..0] + # INT_LATCH_CS & INT_LATCH[7..0] + # INT_CLEAR_CS & INT_IN[7..0] + # ACP_CONF_CS & ACP_CONF[7..0] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + + INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; +END; + + diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak new file mode 100644 index 0000000..e3e49eb --- /dev/null +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak @@ -0,0 +1,478 @@ +TITLE "INTERRUPT HANDLER UND C1287"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_LONG.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + + +-- Parameters Statement (optional) + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + + +-- Subdesign Section + +SUBDESIGN interrupt_handler +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; + ANZAHL_TAGE_DES_MONATS[7..0]:NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; + +BEGIN +-- BYT SELECT + FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + INT_CTR[].CLK = MAIN_CLK; + INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 + INT_CTR[] = FB_AD[]; + INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; + INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; + INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; + INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + INT_ENA[].CLK = MAIN_CLK; + INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 + INT_ENA[] = FB_AD[]; + INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; + INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; + INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; + INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; +-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + INT_CLEAR[].CLK = MAIN_CLK; + INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 + INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; + INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; + INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; + INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT LATCH REGISTER READ ONLY + INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 +-- INTERRUPT + !nIRQ2 = HSYNC & INT_ENA[26]; + !nIRQ3 = INT_CTR0 & INT_ENA[27]; + !nIRQ4 = VSYNC & INT_ENA[28]; + nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; + !nIRQ6 = !nMFP_INT & INT_ENA[30]; + !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; + +PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC + # FB_ADR[19..4]==H"F8E0" -- VME + # FB_ADR[19..4]==H"F920" -- PADDLE + # FB_ADR[19..4]==H"F921" -- PADDLE + # FB_ADR[19..4]==H"F922" -- PADDLE + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..4]==H"FFA9" -- MFP2 + # FB_ADR[19..4]==H"FFAA" -- MFP2 + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..8]==H"F87" -- TT SCSI + # FB_ADR[19..4]==H"FFC2" -- ST UHR + # FB_ADR[19..4]==H"FFC3" -- ST UHR + # FB_ADR[19..4]==H"F890" -- DMA SOUND + # FB_ADR[19..4]==H"F891" -- DMA SOUND + # FB_ADR[19..4]==H"F892"); -- DMA SOUND +-- IF VIDEO ADR CHANGE +TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- VIDEO BASE ADR HIGH 0xFFFF8201/2 + +-- INTERRUPT LATCH + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; + INT_LATCH1.CLK = E0_INT & INT_ENA[1]; + INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; + INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; + INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; + INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; + INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; + INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; + INT_LATCH8.CLK = VSYNC & INT_ENA[8]; + INT_LATCH9.CLK = HSYNC & INT_ENA[9]; + +-- INTERRUPT CLEAR + INT_LATCH[].CLRN = !INT_CLEAR[]; + +-- INT_IN + INT_IN0 = PIC_INT; + INT_IN1 = E0_INT; + INT_IN2 = DVI_INT; + INT_IN3 = !nPCI_INTA; + INT_IN4 = !nPCI_INTB; + INT_IN5 = !nPCI_INTC; + INT_IN6 = !nPCI_INTD; + INT_IN7 = DSP_INT; + INT_IN8 = VSYNC; + INT_IN9 = HSYNC; + INT_IN[25..10] = H"0"; + INT_IN26 = HSYNC; + INT_IN27 = INT_CTR0; + INT_IN28 = VSYNC; + INT_IN29 = INT_LATCH[]!=H"00000000"; + INT_IN30 = !nMFP_INT; + INT_IN31 = DMA_DRQ; +--*************************************************************************************** +-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + ACP_CONF[].CLK = MAIN_CLK; + ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 + ACP_CONF[] = FB_AD[]; + ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; + ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; + ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; + ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; +--*************************************************************************************** + +-------------------------------------------------------------- +-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR +---------------------------------------------------------- + RTC_ADR[].CLK = MAIN_CLK; + RTC_ADR[] = FB_AD[21..16]; + UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 + UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 + RTC_ADR[].ENA = UHR_AS & !nFB_WR; + WERTE[][].CLK = MAIN_CLK; + WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[7..0][1] = FB_AD[23..16]; + WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[7..0][3] = FB_AD[23..16]; + WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[7..0][5] = FB_AD[23..16]; + WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[7..0][10] = FB_AD[23..16]; + WERTE[7..0][11] = FB_AD[23..16]; + WERTE[7..0][12] = FB_AD[23..16]; + WERTE[7..0][13] = FB_AD[23..16]; + WERTE[7..0][14] = FB_AD[23..16]; + WERTE[7..0][15] = FB_AD[23..16]; + WERTE[7..0][16] = FB_AD[23..16]; + WERTE[7..0][17] = FB_AD[23..16]; + WERTE[7..0][18] = FB_AD[23..16]; + WERTE[7..0][19] = FB_AD[23..16]; + WERTE[7..0][20] = FB_AD[23..16]; + WERTE[7..0][21] = FB_AD[23..16]; + WERTE[7..0][22] = FB_AD[23..16]; + WERTE[7..0][23] = FB_AD[23..16]; + WERTE[7..0][24] = FB_AD[23..16]; + WERTE[7..0][25] = FB_AD[23..16]; + WERTE[7..0][26] = FB_AD[23..16]; + WERTE[7..0][27] = FB_AD[23..16]; + WERTE[7..0][28] = FB_AD[23..16]; + WERTE[7..0][29] = FB_AD[23..16]; + WERTE[7..0][30] = FB_AD[23..16]; + WERTE[7..0][31] = FB_AD[23..16]; + WERTE[7..0][32] = FB_AD[23..16]; + WERTE[7..0][33] = FB_AD[23..16]; + WERTE[7..0][34] = FB_AD[23..16]; + WERTE[7..0][35] = FB_AD[23..16]; + WERTE[7..0][36] = FB_AD[23..16]; + WERTE[7..0][37] = FB_AD[23..16]; + WERTE[7..0][38] = FB_AD[23..16]; + WERTE[7..0][39] = FB_AD[23..16]; + WERTE[7..0][40] = FB_AD[23..16]; + WERTE[7..0][41] = FB_AD[23..16]; + WERTE[7..0][42] = FB_AD[23..16]; + WERTE[7..0][43] = FB_AD[23..16]; + WERTE[7..0][44] = FB_AD[23..16]; + WERTE[7..0][45] = FB_AD[23..16]; + WERTE[7..0][46] = FB_AD[23..16]; + WERTE[7..0][47] = FB_AD[23..16]; + WERTE[7..0][48] = FB_AD[23..16]; + WERTE[7..0][49] = FB_AD[23..16]; + WERTE[7..0][50] = FB_AD[23..16]; + WERTE[7..0][51] = FB_AD[23..16]; + WERTE[7..0][52] = FB_AD[23..16]; + WERTE[7..0][53] = FB_AD[23..16]; + WERTE[7..0][54] = FB_AD[23..16]; + WERTE[7..0][55] = FB_AD[23..16]; + WERTE[7..0][56] = FB_AD[23..16]; + WERTE[7..0][57] = FB_AD[23..16]; + WERTE[7..0][58] = FB_AD[23..16]; + WERTE[7..0][59] = FB_AD[23..16]; + WERTE[7..0][60] = FB_AD[23..16]; + WERTE[7..0][61] = FB_AD[23..16]; + WERTE[7..0][62] = FB_AD[23..16]; + WERTE[7..0][63] = FB_AD[23..16]; + WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; + WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; + WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; + WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; + WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; + WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; + WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; + WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; + WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; + WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; + WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; + WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; + WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; + WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; + WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; + WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; + WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; + WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; + WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; + WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; + WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; + WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; + WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; + WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; + WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; + WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; + WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; + WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; + WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; + WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; + WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; + WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; + WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; + WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; + WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; + WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; + WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; + WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; + WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; + WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; + WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; + WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; + WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; + WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; + WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; + WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; + WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; + WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; + WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; + WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; + WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; + WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; + WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; + WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; + WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; + WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; + WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; + WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; + PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; + PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; + PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; + WERTE[6][10].CLRN = GND; -- KEIN UIP + UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF + WERTE[2][11] = VCC; -- IMMER BINARY + WERTE[1][11] = VCC; -- IMMER 24H FORMAT + WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR + WERTE[7][13] = VCC; -- IMMER RICHTIG +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) + SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL + WERTE[0][13] = SOMMERZEIT; + WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); + WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER +-- ACHTELSEKUNDEN + ACHTELSEKUNDEN[].CLK = MAIN_CLK; + ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; + ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; +-- SEKUNDEN + INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); +-- MINUTEN + INC_MIN = INC_SEC & WERTE[][0]==59; -- + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- +-- STUNDEN + INC_STD = INC_MIN & WERTE[][2]==59; + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT +-- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); + ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) + # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) + # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 + # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- +-- MONATE + INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); +-- JAHR + INC_JAHR = INC_MONAT & WERTE[][8]==12; -- + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); +-- TRISTATE OUTPUT + + FB_AD[31..24] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[31..24] + # INT_ENA_CS & INT_ENA[31..24] + # INT_LATCH_CS & INT_LATCH[31..24] + # INT_CLEAR_CS & INT_IN[31..24] + # ACP_CONF_CS & ACP_CONF[31..24] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[23..16] = lpm_bustri_BYT( + WERTE[][0] & RTC_ADR[]==0 & UHR_DS + # WERTE[][1] & RTC_ADR[]==1 & UHR_DS + # WERTE[][2] & RTC_ADR[]==2 & UHR_DS + # WERTE[][3] & RTC_ADR[]==3 & UHR_DS + # WERTE[][4] & RTC_ADR[]==4 & UHR_DS + # WERTE[][5] & RTC_ADR[]==5 & UHR_DS + # WERTE[][6] & RTC_ADR[]==6 & UHR_DS + # WERTE[][7] & RTC_ADR[]==7 & UHR_DS + # WERTE[][8] & RTC_ADR[]==8 & UHR_DS + # WERTE[][9] & RTC_ADR[]==9 & UHR_DS + # WERTE[][10] & RTC_ADR[]==10 & UHR_DS + # WERTE[][11] & RTC_ADR[]==11 & UHR_DS + # WERTE[][12] & RTC_ADR[]==12 & UHR_DS + # WERTE[][13] & RTC_ADR[]==13 & UHR_DS + # WERTE[][14] & RTC_ADR[]==14 & UHR_DS + # WERTE[][15] & RTC_ADR[]==15 & UHR_DS + # WERTE[][16] & RTC_ADR[]==16 & UHR_DS + # WERTE[][17] & RTC_ADR[]==17 & UHR_DS + # WERTE[][18] & RTC_ADR[]==18 & UHR_DS + # WERTE[][19] & RTC_ADR[]==19 & UHR_DS + # WERTE[][20] & RTC_ADR[]==20 & UHR_DS + # WERTE[][21] & RTC_ADR[]==21 & UHR_DS + # WERTE[][22] & RTC_ADR[]==22 & UHR_DS + # WERTE[][23] & RTC_ADR[]==23 & UHR_DS + # WERTE[][24] & RTC_ADR[]==24 & UHR_DS + # WERTE[][25] & RTC_ADR[]==25 & UHR_DS + # WERTE[][26] & RTC_ADR[]==26 & UHR_DS + # WERTE[][27] & RTC_ADR[]==27 & UHR_DS + # WERTE[][28] & RTC_ADR[]==28 & UHR_DS + # WERTE[][29] & RTC_ADR[]==29 & UHR_DS + # WERTE[][30] & RTC_ADR[]==30 & UHR_DS + # WERTE[][31] & RTC_ADR[]==31 & UHR_DS + # WERTE[][32] & RTC_ADR[]==32 & UHR_DS + # WERTE[][33] & RTC_ADR[]==33 & UHR_DS + # WERTE[][34] & RTC_ADR[]==34 & UHR_DS + # WERTE[][35] & RTC_ADR[]==35 & UHR_DS + # WERTE[][36] & RTC_ADR[]==36 & UHR_DS + # WERTE[][37] & RTC_ADR[]==37 & UHR_DS + # WERTE[][38] & RTC_ADR[]==38 & UHR_DS + # WERTE[][39] & RTC_ADR[]==39 & UHR_DS + # WERTE[][40] & RTC_ADR[]==40 & UHR_DS + # WERTE[][41] & RTC_ADR[]==41 & UHR_DS + # WERTE[][42] & RTC_ADR[]==42 & UHR_DS + # WERTE[][43] & RTC_ADR[]==43 & UHR_DS + # WERTE[][44] & RTC_ADR[]==44 & UHR_DS + # WERTE[][45] & RTC_ADR[]==45 & UHR_DS + # WERTE[][46] & RTC_ADR[]==46 & UHR_DS + # WERTE[][47] & RTC_ADR[]==47 & UHR_DS + # WERTE[][48] & RTC_ADR[]==48 & UHR_DS + # WERTE[][49] & RTC_ADR[]==49 & UHR_DS + # WERTE[][50] & RTC_ADR[]==50 & UHR_DS + # WERTE[][51] & RTC_ADR[]==51 & UHR_DS + # WERTE[][52] & RTC_ADR[]==52 & UHR_DS + # WERTE[][53] & RTC_ADR[]==53 & UHR_DS + # WERTE[][54] & RTC_ADR[]==54 & UHR_DS + # WERTE[][55] & RTC_ADR[]==55 & UHR_DS + # WERTE[][56] & RTC_ADR[]==56 & UHR_DS + # WERTE[][57] & RTC_ADR[]==57 & UHR_DS + # WERTE[][58] & RTC_ADR[]==58 & UHR_DS + # WERTE[][59] & RTC_ADR[]==59 & UHR_DS + # WERTE[][60] & RTC_ADR[]==60 & UHR_DS + # WERTE[][61] & RTC_ADR[]==61 & UHR_DS + # WERTE[][62] & RTC_ADR[]==62 & UHR_DS + # WERTE[][63] & RTC_ADR[]==63 & UHR_DS + # (0,RTC_ADR[]) & UHR_AS + # INT_CTR_CS & INT_CTR[23..16] + # INT_ENA_CS & INT_ENA[23..16] + # INT_LATCH_CS & INT_LATCH[23..16] + # INT_CLEAR_CS & INT_IN[23..16] + # ACP_CONF_CS & ACP_CONF[23..16] + ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[15..8] + # INT_ENA_CS & INT_ENA[15..8] + # INT_LATCH_CS & INT_LATCH[15..8] + # INT_CLEAR_CS & INT_IN[15..8] + # ACP_CONF_CS & ACP_CONF[15..8] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[7..0] + # INT_ENA_CS & INT_ENA[7..0] + # INT_LATCH_CS & INT_LATCH[7..0] + # INT_CLEAR_CS & INT_IN[7..0] + # ACP_CONF_CS & ACP_CONF[7..0] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + + INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; +END; + + diff --git a/FPGA_Quartus_13.1/UNUSED b/FPGA_Quartus_13.1/UNUSED new file mode 100644 index 0000000..3a7d9e6 --- /dev/null +++ b/FPGA_Quartus_13.1/UNUSED @@ -0,0 +1,27 @@ + +-- Clearbox generated Memory Initialization File (.mif) + +WIDTH=3; +DEPTH=16; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 00 : 7; + 01 : 6; + 02 : 5; + 03 : 4; + 04 : 3; + 05 : 2; + 06 : 1; + 07 : 0; + 08 : 7; + 09 : 6; + 0a : 5; + 0b : 4; + 0c : 3; + 0d : 2; + 0e : 1; + 0f : 0; +END; diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd new file mode 100644 index 0000000..e09ed0b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -0,0 +1,75 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Fri Oct 16 15:40:59 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY BLITTER IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); + BLITTER_ON : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END BLITTER; + + +-- Architecture Body + +ARCHITECTURE BLITTER_architecture OF BLITTER IS + + +BEGIN + BLITTER_RUN <= '0'; + BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + BLITTER_ADR <= x"76543210"; + BLITTER_SIG <= '0'; + BLITTER_WR <= '0'; + BLITTER_TA <= '0'; + +END BLITTER_architecture; diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak new file mode 100644 index 0000000..f674080 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak @@ -0,0 +1,75 @@ +-- WARNING: Do NOT edit the input and output ports in this file in a text +-- editor if you plan to continue editing the block that represents it in +-- the Block Editor! File corruption is VERY likely to occur. + +-- Copyright (C) 1991-2008 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) +-- Created on Fri Oct 16 15:40:59 2009 + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + + +-- Entity Declaration + +ENTITY BLITTER IS + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + PORT + ( + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); + BLITTER_ON : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + ); + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + +END BLITTER; + + +-- Architecture Body + +ARCHITECTURE BLITTER_architecture OF BLITTER IS + + +BEGIN + BLITTER_RUN <= '0'; + BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + BLITTER_ADR <= x"FEDCBA9876543210"; + BLITTER_SIG <= '0'; + BLITTER_WR <= '0'; + BLITTER_TA <= '0'; + +END BLITTER_architecture; diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf new file mode 100644 index 0000000..d5b5ec2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -0,0 +1,659 @@ +TITLE "DDR_CTR"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + +-- FIFO WATER MARK +CONSTANT FIFO_LWM = 0; +CONSTANT FIFO_MWM = 200; +CONSTANT FIFO_HWM = 500; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + DDRCLK0 : INPUT; + CLK33M : INPUT; + FIFO_MW[8..0] : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + BA[1..0] : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + DS_T4R,DS_T5R, -- READ CPU UND BLITTER, + DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER + DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO + DS_CB6, DS_CB8, -- CLOSE FIFO BANK + DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA_P[12..0] :DFF; + BA_P[1..0] :DFF; + VA_S[12..0] :DFF; + BA_S[1..0] :DFF; + MCS[1..0] :DFF; + CPU_DDR_SYNC :DFF; + DDR_SEL :NODE; + DDR_CS :DFFE; + DDR_CONFIG :NODE; + SR_DDR_WR :DFF; + SR_DDRWR_D_SEL :DFF; + SR_VDMP[7..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA[1..0] :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + CPU_AC :DFF; + BUS_CYC :DFF; + BUS_CYC_END :NODE; + BLITTER_REQ :DFF; + BLITTER_AC :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA[1..0] :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_REQ :DFF; + FIFO_AC :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA[1..0] :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_ACTIVE :NODE; + CLR_FIFO_SYNC :DFF; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + SR_FIFO_WRE :DFF; + FIFO_BANK_OK :DFF; + FIFO_BANK_NOT_OK :NODE; + DDR_REFRESH_ON :NODE; + DDR_REFRESH_CNT[10..0] :DFF; + DDR_REFRESH_REQ :DFF; + DDR_REFRESH_SIG[3..0] :DFFE; + REFRESH_TIME :DFF; + VIDEO_BASE_L_D[7..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[2..0] :DFFE; + VIDEO_ADR_CNT[22..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[22..0] :NODE; + VIDEO_ACT_ADR[26..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0 -- ADR==0 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + FB_LE0 = !nFB_WR; + IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + IF DDR_CS THEN + FB_LE0 = !nFB_WR; + VIDEO_DDR_TA = VCC; + IF LINE THEN + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_REGDDR = FR_S1; + ELSE + BUS_CYC_END = VCC; + FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_REGDDR = FR_WAIT; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + IF DDR_CS THEN + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S2; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S2 => + IF DDR_CS THEN + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN + FB_REGDDR = FR_S2; + ELSE + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S3; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S3 => + IF DDR_CS THEN + FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + VIDEO_DDR_TA = VCC; + BUS_CYC_END = VCC; + FB_REGDDR = FR_WAIT; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + DDR_REFRESH_ON = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + FIFO_ACTIVE = VIDEO_RAM_CTR8; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA[] = FB_ADR[13..12]; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + SR_DDR_WR.CLK = DDRCLK0; + SR_DDRWR_D_SEL.CLK = DDRCLK0; + SR_VDMP[7..0].CLK = DDRCLK0; + SR_FIFO_WRE.CLK = DDRCLK0; + CPU_AC.CLK = DDRCLK0; + FIFO_AC.CLK = DDRCLK0; + BLITTER_AC.CLK = DDRCLK0; + DDRWR_D_SEL1 = BLITTER_AC; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; + DDR_CS.CLK = MAIN_CLK; + DDR_CS.ENA = FB_ALE; + DDR_CS = DDR_SEL; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + CPU_REQ.CLK = DDR_SYNC_66M; + CPU_REQ = CPU_SIG + # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG + BUS_CYC.CLK = DDRCLK0; + BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS[].CLK = DDRCLK0; + MCS0 = MAIN_CLK; + MCS1 = MCS0; + CPU_DDR_SYNC.CLK = DDRCLK0; + CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN + --------------------------------------------------- + VA_S[].CLK = DDRCLK0; + BA_S[].CLK = DDRCLK0; + VA[] = VA_S[]; + BA[] = BA_S[]; + VA_P[].CLK = DDRCLK0; + BA_P[].CLK = DDRCLK0; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF DDR_REFRESH_REQ THEN + DDR_SM = DS_R2; + ELSE + IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? + IF DDR_CONFIG THEN -- JA + DDR_SM = DS_C2; + ELSE + IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE + VA_S[] = CPU_ROW_ADR[]; + BA_S[] = CPU_BA[]; + CPU_AC = VCC; + BUS_CYC = VCC; + DDR_SM = DS_T2B; + ELSE + IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT + VA_P[] = FIFO_ROW_ADR[]; + BA_P[] = FIFO_BA[]; + FIFO_AC = VCC; -- VORBESETZEN + ELSE + VA_P[] = BLITTER_ROW_ADR[]; + BA_P[] = BLITTER_BA[]; + BLITTER_AC = VCC; -- VORBESETZEN + END IF; + DDR_SM = DS_T2A; + END IF; + END IF; + ELSE + DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN + END IF; + END IF; + + WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF DDR_SEL & (nFB_WR # !LINE) THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + ELSE + VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; + VA[] = VA_P[]; + BA[] = BA_P[]; + VA_S[10] = !(FIFO_AC & FIFO_REQ); + FIFO_BANK_OK = FIFO_AC & FIFO_REQ; + FIFO_AC = FIFO_AC & FIFO_REQ; + BLITTER_AC = BLITTER_AC & BLITTER_REQ; + END IF; + DDR_SM = DS_T3; + + WHEN DS_T2B => + VRAS = VCC; + FIFO_BANK_NOT_OK = VCC; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + DDR_SM = DS_T3; + + WHEN DS_T3 => + CPU_AC = CPU_AC; + FIFO_AC = FIFO_AC; + BLITTER_AC = BLITTER_AC; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN + DDR_SM = DS_T4W; + ELSE + IF CPU_AC THEN -- CPU? + VA_S[9..0] = CPU_COL_ADR[]; + BA_S[] = CPU_BA[]; + DDR_SM = DS_T4R; + ELSE + IF FIFO_AC THEN -- FIFO? + VA_S[9..0] = FIFO_COL_ADR[]; + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T4F; + ELSE + IF BLITTER_AC THEN + VA_S[9..0] = BLITTER_COL_ADR[]; + BA_S[] = BLITTER_BA[]; + DDR_SM = DS_T4R; + ELSE + DDR_SM = DS_N8; + END IF; + END IF; + END IF; + END IF; +-- READ + WHEN DS_T4R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN + DDR_SM = DS_T5R; + + WHEN DS_T5R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- MANUEL PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- WRITE + WHEN DS_T4W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + DDR_SM = DS_T5W; + + WHEN DS_T5W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VA_S[9..0] = CPU_AC & CPU_COL_ADR[] + # BLITTER_AC & BLITTER_COL_ADR[]; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + BA_S[] = CPU_AC & CPU_BA[] + # BLITTER_AC & BLITTER_BA[]; + SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE + SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE + DDR_SM = DS_T6W; + + WHEN DS_T6W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + VWE = VCC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV + DDR_SM = DS_T7W; + + WHEN DS_T7W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + DDR_SM = DS_T8W; + + WHEN DS_T8W => + DDR_SM = DS_T9W; + + WHEN DS_T9W => + IF FIFO_REQ & FIFO_BANK_OK THEN + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- FIFO READ + WHEN DS_T4F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T5F; + + WHEN DS_T5F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN + END IF; + + WHEN DS_T6F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + + WHEN DS_T7F => + IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T8F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + END IF; + END IF; + + WHEN DS_T8F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + IF FIFO_MW[] + ELSE + DDR_SM = DS_T9F; + END IF; + + WHEN DS_T9F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_P[9..0] = FIFO_COL_ADR[]+4; + VA_P[10] = GND; -- NON AUTO PRECHARGE + BA_P[] = FIFO_BA[]; + DDR_SM = DS_T10F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + END IF; + + WHEN DS_T10F => + IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK + DDR_SM = DS_T3; + ELSE + VCAS = VCC; + VA[] = VA_P[]; + BA[] = BA_P[]; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + END IF; + +-- CONFIG CYCLUS + WHEN DS_C2 => + DDR_SM = DS_C3; + WHEN DS_C3 => + BUS_CYC = CPU_REQ; + DDR_SM = DS_C4; + WHEN DS_C4 => + IF CPU_REQ THEN + DDR_SM = DS_C5; + ELSE + DDR_SM = DS_T1; + END IF; + WHEN DS_C5 => + DDR_SM = DS_C6; + WHEN DS_C6 => + VA_S[] = FB_AD[12..0]; + BA_S[] = FB_AD[14..13]; + DDR_SM = DS_C7; + WHEN DS_C7 => + VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + DDR_SM = DS_N8; +-- CLOSE FIFO BANK + WHEN DS_CB6 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_N7; + WHEN DS_CB8 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_T1; +-- REFRESH 70NS = 10 ZYCLEN + WHEN DS_R2 => + IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + VRAS = VCC; -- ALLE BANKS SCHLIESSEN + VWE = VCC; + VA[10] = VCC; + FIFO_BANK_NOT_OK = VCC; + DDR_SM = DS_R4; + ELSE + VCAS = VCC; + VRAS = VCC; + DDR_SM = DS_R3; + END IF; + WHEN DS_R3 => + DDR_SM = DS_R4; + WHEN DS_R4 => + DDR_SM = DS_R5; + WHEN DS_R5 => + DDR_SM = DS_R6; + WHEN DS_R6 => + DDR_SM = DS_N5; +-- LEERSCHLAUFE + WHEN DS_N5 => + DDR_SM = DS_N6; + WHEN DS_N6 => + DDR_SM = DS_N7; + WHEN DS_N7 => + DDR_SM = DS_N8; + WHEN DS_N8 => + DDR_SM = DS_T1; + END CASE; + +--------------------------------------------------------------- +-- BLITTER ---------------------- +----------------------------------------- + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; + BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; + BLITTER_BA1 = BLITTER_ADR13; + BLITTER_BA0 = BLITTER_ADR12; + BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- +-------------------------------------------------------- + FIFO_REQ.CLK = DDRCLK0; + FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS +----------------------------------------------------------------------------------------- + DDR_REFRESH_CNT[].CLK = CLK33M; + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + REFRESH_TIME.CLK = DDRCLK0; + REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC + DDR_REFRESH_SIG[].CLK = DDRCLK0; + DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT + DDR_REFRESH_REQ.CLK = DDRCLK0; + DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[26..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) + # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & VIDEO_BASE_L_D[] + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] + # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] + # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); +END; + diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak new file mode 100644 index 0000000..ead66e8 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak @@ -0,0 +1,660 @@ +TITLE "DDR_CTR"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + +-- FIFO WATER MARK +CONSTANT FIFO_LWM = 0; +CONSTANT FIFO_MWM = 200; +CONSTANT FIFO_HWM = 500; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + DDRCLK0 : INPUT; + CLK33M : INPUT; + FIFO_MW[8..0] : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + CLEAR_FIFO_CNT : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + BA[1..0] : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + DS_T4R,DS_T5R, -- READ CPU UND BLITTER, + DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER + DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO + DS_CB6, DS_CB8, -- CLOSE FIFO BANK + DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA_P[12..0] :DFF; + BA_P[1..0] :DFF; + VA_S[12..0] :DFF; + BA_S[1..0] :DFF; + MCS[1..0] :DFF; + CPU_DDR_SYNC :DFF; + DDR_SEL :NODE; + DDR_CS :DFFE; + DDR_CONFIG :NODE; + SR_DDR_WR :DFF; + SR_DDRWR_D_SEL :DFF; + SR_VDMP[7..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA[1..0] :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + CPU_AC :DFF; + BUS_CYC :DFF; + BUS_CYC_END :NODE; + BLITTER_REQ :DFF; + BLITTER_AC :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA[1..0] :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_REQ :DFF; + FIFO_AC :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA[1..0] :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_ACTIVE :NODE; + CLR_FIFO_SYNC :DFF; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + SR_FIFO_WRE :DFF; + FIFO_BANK_OK :DFF; + FIFO_BANK_NOT_OK :NODE; + DDR_REFRESH_ON :NODE; + DDR_REFRESH_CNT[10..0] :DFF; + DDR_REFRESH_REQ :DFF; + DDR_REFRESH_SIG[3..0] :DFFE; + REFRESH_TIME :DFF; + VIDEO_BASE_L_D[7..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[2..0] :DFFE; + VIDEO_ADR_CNT[22..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[22..0] :NODE; + VIDEO_ACT_ADR[26..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0 -- ADR==0 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + FB_LE0 = !nFB_WR; + IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + IF DDR_CS THEN + FB_LE0 = !nFB_WR; + VIDEO_DDR_TA = VCC; + IF LINE THEN + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_REGDDR = FR_S1; + ELSE + BUS_CYC_END = VCC; + FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_REGDDR = FR_WAIT; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + IF DDR_CS THEN + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S2; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S2 => + IF DDR_CS THEN + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN + FB_REGDDR = FR_S2; + ELSE + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S3; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S3 => + IF DDR_CS THEN + FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + VIDEO_DDR_TA = VCC; + BUS_CYC_END = VCC; + FB_REGDDR = FR_WAIT; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + DDR_REFRESH_ON = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + FIFO_ACTIVE = VIDEO_RAM_CTR8; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA[] = FB_ADR[13..12]; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + SR_DDR_WR.CLK = DDRCLK0; + SR_DDRWR_D_SEL.CLK = DDRCLK0; + SR_VDMP[7..0].CLK = DDRCLK0; + SR_FIFO_WRE.CLK = DDRCLK0; + CPU_AC.CLK = DDRCLK0; + FIFO_AC.CLK = DDRCLK0; + BLITTER_AC.CLK = DDRCLK0; + DDRWR_D_SEL1 = BLITTER_AC; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; + DDR_CS.CLK = MAIN_CLK; + DDR_CS.ENA = FB_ALE; + DDR_CS = DDR_SEL; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + CPU_REQ.CLK = DDR_SYNC_66M; + CPU_REQ = CPU_SIG + # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG + BUS_CYC.CLK = DDRCLK0; + BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS[].CLK = DDRCLK0; + MCS0 = MAIN_CLK; + MCS1 = MCS0; + CPU_DDR_SYNC.CLK = DDRCLK0; + CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN + --------------------------------------------------- + VA_S[].CLK = DDRCLK0; + BA_S[].CLK = DDRCLK0; + VA[] = VA_S[]; + BA[] = BA_S[]; + VA_P[].CLK = DDRCLK0; + BA_P[].CLK = DDRCLK0; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF DDR_REFRESH_REQ THEN + DDR_SM = DS_R2; + ELSE + IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? + IF DDR_CONFIG THEN -- JA + DDR_SM = DS_C2; + ELSE + IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE + VA_S[] = CPU_ROW_ADR[]; + BA_S[] = CPU_BA[]; + CPU_AC = VCC; + BUS_CYC = VCC; + DDR_SM = DS_T2B; + ELSE + IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT + VA_P[] = FIFO_ROW_ADR[]; + BA_P[] = FIFO_BA[]; + FIFO_AC = VCC; -- VORBESETZEN + ELSE + VA_P[] = BLITTER_ROW_ADR[]; + BA_P[] = BLITTER_BA[]; + BLITTER_AC = VCC; -- VORBESETZEN + END IF; + DDR_SM = DS_T2A; + END IF; + END IF; + ELSE + DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN + END IF; + END IF; + + WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF DDR_SEL & (nFB_WR # !LINE) THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + ELSE + VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; + VA[] = VA_P[]; + BA[] = BA_P[]; + VA_S[10] = !(FIFO_AC & FIFO_REQ); + FIFO_BANK_OK = FIFO_AC & FIFO_REQ; + FIFO_AC = FIFO_AC & FIFO_REQ; + BLITTER_AC = BLITTER_AC & BLITTER_REQ; + END IF; + DDR_SM = DS_T3; + + WHEN DS_T2B => + VRAS = VCC; + FIFO_BANK_NOT_OK = VCC; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + DDR_SM = DS_T3; + + WHEN DS_T3 => + CPU_AC = CPU_AC; + FIFO_AC = FIFO_AC; + BLITTER_AC = BLITTER_AC; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN + DDR_SM = DS_T4W; + ELSE + IF CPU_AC THEN -- CPU? + VA_S[9..0] = CPU_COL_ADR[]; + BA_S[] = CPU_BA[]; + DDR_SM = DS_T4R; + ELSE + IF FIFO_AC THEN -- FIFO? + VA_S[9..0] = FIFO_COL_ADR[]; + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T4F; + ELSE + IF BLITTER_AC THEN + VA_S[9..0] = BLITTER_COL_ADR[]; + BA_S[] = BLITTER_BA[]; + DDR_SM = DS_T4R; + ELSE + DDR_SM = DS_N8; + END IF; + END IF; + END IF; + END IF; +-- READ + WHEN DS_T4R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN + DDR_SM = DS_T5R; + + WHEN DS_T5R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- MANUEL PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- WRITE + WHEN DS_T4W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + DDR_SM = DS_T5W; + + WHEN DS_T5W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VA_S[9..0] = CPU_AC & CPU_COL_ADR[] + # BLITTER_AC & BLITTER_COL_ADR[]; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + BA_S[] = CPU_AC & CPU_BA[] + # BLITTER_AC & BLITTER_BA[]; + SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE + SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE + DDR_SM = DS_T6W; + + WHEN DS_T6W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + VWE = VCC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV + DDR_SM = DS_T7W; + + WHEN DS_T7W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + DDR_SM = DS_T8W; + + WHEN DS_T8W => + DDR_SM = DS_T9W; + + WHEN DS_T9W => + IF FIFO_REQ & FIFO_BANK_OK THEN + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- FIFO READ + WHEN DS_T4F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T5F; + + WHEN DS_T5F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN + END IF; + + WHEN DS_T6F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + + WHEN DS_T7F => + IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T8F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + END IF; + END IF; + + WHEN DS_T8F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + IF FIFO_MW[] + ELSE + DDR_SM = DS_T9F; + END IF; + + WHEN DS_T9F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_P[9..0] = FIFO_COL_ADR[]+4; + VA_P[10] = GND; -- NON AUTO PRECHARGE + BA_P[] = FIFO_BA[]; + DDR_SM = DS_T10F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + END IF; + + WHEN DS_T10F => + IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK + DDR_SM = DS_T3; + ELSE + VCAS = VCC; + VA[] = VA_P[]; + BA[] = BA_P[]; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + END IF; + +-- CONFIG CYCLUS + WHEN DS_C2 => + DDR_SM = DS_C3; + WHEN DS_C3 => + BUS_CYC = CPU_REQ; + DDR_SM = DS_C4; + WHEN DS_C4 => + IF CPU_REQ THEN + DDR_SM = DS_C5; + ELSE + DDR_SM = DS_T1; + END IF; + WHEN DS_C5 => + DDR_SM = DS_C6; + WHEN DS_C6 => + VA_S[] = FB_AD[12..0]; + BA_S[] = FB_AD[14..13]; + DDR_SM = DS_C7; + WHEN DS_C7 => + VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + DDR_SM = DS_N8; +-- CLOSE FIFO BANK + WHEN DS_CB6 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_N7; + WHEN DS_CB8 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_T1; +-- REFRESH 70NS = 10 ZYCLEN + WHEN DS_R2 => + IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + VRAS = VCC; -- ALLE BANKS SCHLIESSEN + VWE = VCC; + VA[10] = VCC; + FIFO_BANK_NOT_OK = VCC; + DDR_SM = DS_R4; + ELSE + VCAS = VCC; + VRAS = VCC; + DDR_SM = DS_R3; + END IF; + WHEN DS_R3 => + DDR_SM = DS_R4; + WHEN DS_R4 => + DDR_SM = DS_R5; + WHEN DS_R5 => + DDR_SM = DS_R6; + WHEN DS_R6 => + DDR_SM = DS_N5; +-- LEERSCHLAUFE + WHEN DS_N5 => + DDR_SM = DS_N6; + WHEN DS_N6 => + DDR_SM = DS_N7; + WHEN DS_N7 => + DDR_SM = DS_N8; + WHEN DS_N8 => + DDR_SM = DS_T1; + END CASE; + +--------------------------------------------------------------- +-- BLITTER ---------------------- +----------------------------------------- + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; + BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; + BLITTER_BA1 = BLITTER_ADR13; + BLITTER_BA0 = BLITTER_ADR12; + BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- +-------------------------------------------------------- + FIFO_REQ.CLK = DDRCLK0; + FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS +----------------------------------------------------------------------------------------- + DDR_REFRESH_CNT[].CLK = CLK33M; + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + REFRESH_TIME.CLK = DDRCLK0; + REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC + DDR_REFRESH_SIG[].CLK = DDRCLK0; + DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT + DDR_REFRESH_REQ.CLK = DDRCLK0; + DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[26..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) + # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & VIDEO_BASE_L_D[] + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] + # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] + # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); +END; + diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak new file mode 100644 index 0000000..03052b4 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak @@ -0,0 +1,352 @@ +TITLE "DDR_CTR_BLITTER"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR_BLITTER +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FIFO_FULL : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + VSYNC : INPUT; + BLITTER_ON : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + VDVZ[127..0] : INPUT; + DDRCLK[3..0] : INPUT; + BA0 : OUTPUT; + BA1 : OUTPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FIFO_WRE : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + START_CYC_RDWR : OUTPUT; + DDR_WR : OUTPUT; + CLEAR_FIFO_CNT : OUTPUT; + BLITTER_RUN : OUTPUT; + BLITTER_DOUT[127..0] : OUTPUT; + BLITTER_LE[3..0] : OUTPUT; + BLITTER_RDE : OUTPUT; + DDRWR_D_SEL[1..0] : OUTPUT; + VDMP[7..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS); + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA[12..0] :NODE; + BA0 :NODE; + BA1 :NODE; + DDR_WR :DFF; + DDR_SEL :NODE; + DDR_CONFIG :NODE; + DDRWR_D_SEL[1..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA0 :NODE; + CPU_BA1 :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + BLITTER_SIG :NODE; + BLITTER_REQ :DFF; + BLITTER_RUN :DFF; + BLITTER_WR :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA0 :NODE; + BLITTER_BA1 :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_SIG :NODE; + FIFO_REQ :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA0 :NODE; + FIFO_BA1 :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_WRE :DFF; + FIFO_ACTIVE :NODE; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + DDR_REFRESH_ON :NODE; + VIDEO_BASE_L_D[3..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[7..0] :DFFE; + VIDEO_ADR_CNT[27..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[27..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0; -- ADR==0 + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + IF DDR_SEL THEN + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_LE0 = !nFB_WR; + IF LINE THEN + FB_REGDDR = FR_S1; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + FB_REGDDR = FR_S2; + WHEN FR_S2 => + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + FB_REGDDR = FR_S3; + WHEN FR_S3 => + FB_VDOE3 = !nFB_OE & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + FB_REGDDR = FR_WAIT; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + FIFO_ACTIVE = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + DDR_REFRESH_ON = VIDEO_RAM_CTR4; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA1 = FB_ADR13; + CPU_BA0 = FB_ADR12; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + DDR_WR.CLK = DDRCLK0; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..29]==B"011"; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS + # FR_S0 & !nFB_WR -- WRITE SPÄTER AUCH CONFIG + # FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE + CPU_REQ = CPU_SIG; + CPU_REQ.CLK = DDR_SYNC_66M; + DDR_D_SEL[].CLK = DDRCLK3; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF MAIN_CLK THEN + DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4) + DDR_SM = DS_T2; + ELSE + DDR_SM = DS_LS; -- SYNCHRONISIEREN + END IF; + WHEN DS_T2 => + IF !DDR_CONFIG THEN + VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON; + VA[] = CPU_SIG & CPU_ROW_ADR[] + # BLITTER_SIG & BLITTER_ROW_ADR[] + # FIFO_SIG & FIFO_ROW_ADR[]; + BA0 = CPU_SIG & CPU_BA0 + # BLITTER_SIG & BLITTER_BA0 + # FIFO_SIG & FIFO_BA0; + BA1 = CPU_SIG & CPU_BA1 + # BLITTER_SIG & BLITTER_BA1 + # FIFO_SIG & FIFO_BA1; + VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS + BLITTER_REQ = BLITTER_SIG; + FIFO_REQ = FIFO_SIG; + END IF; + IF MAIN_CLK THEN + DDR_SM = DS_T3; + ELSE + DDR_SM = DS_LS; + END IF; + WHEN DS_T3 => + IF DDR_CONFIG & CPU_REQ THEN + VRAS = FB_AD18; + VCAS = FB_AD17; + VWE = FB_AD16; + BA1 = FB_AD14; + BA0 = FB_AD13; + VA[] = FB_AD[12..0]; + END IF; + IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN + DDR_SM = DS_LS; + ELSE + BLITTER_REQ = BLITTER_SIG; + FIFO_REQ = FIFO_SIG; + DDR_SM = DS_T4; + END IF; + WHEN DS_T4 => + FIFO_REQ = FIFO_SIG; + VCAS = VCC; + VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; + VA[9..0] = CPU_REQ & CPU_COL_ADR[] + # BLITTER_REQ & BLITTER_COL_ADR[] + # FIFO_REQ & FIFO_COL_ADR[]; + VA10 = VCC; -- AUTO PRECHARGE + BA0 = CPU_REQ & CPU_BA0 + # BLITTER_REQ & BLITTER_BA0 + # FIFO_REQ & FIFO_BA0; + BA1 = CPU_REQ & CPU_BA1 + # BLITTER_REQ & BLITTER_BA1 + # FIFO_REQ & FIFO_BA1; + DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; + FIFO_REQ = FIFO_SIG; + IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? + DDR_SM = DS_T5; -- JA-> + ELSE + DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN + END IF; + WHEN DS_T5 => + FIFO_REQ = FIFO_SIG; + DDR_SM = DS_T6; + WHEN DS_T6 => + IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ + VRAS = VCC; + VA[] = CPU_ROW_ADR[]; + BA1 = CPU_BA1; + BA0 = CPU_BA0; + DDR_SM = DS_T3; + ELSE + FIFO_REQ = FIFO_SIG; + VCAS = VCC; + VA[9..0] = FIFO_COL_ADR[]; + VA10 = VCC; -- AUTO PRECHARGE + BA0 = FIFO_BA0; + BA1 = FIFO_BA1; + FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133 + IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? + DDR_SM = DS_T5; -- JA-> + ELSE + DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN + END IF; + END IF; + WHEN DS_LS => + IF !MAIN_CLK THEN -- LEERSTATE UND SYNC + DDR_SM = DS_T1; + ELSE + DDR_SM = DS_LS; + END IF; + END CASE; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- + FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG; + FIFO_REQ.CLK = DDR_SYNC_66M; + FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12]; + FIFO_BA1 = VIDEO_ADR_CNT11; + FIFO_BA0 = VIDEO_ADR_CNT10; + FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0]; + -- ZÄHLER RÜCKSETZEN WENN VSYNC ---------------- + CLEAR_FIFO_CNT.CLK = DDRCLK0; + CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE; + STOP.CLK = DDRCLK0; + STOP = VSYNC # CLEAR_FIFO_CNT; + VIDEO_ADR_CNT[].CLK = DDRCLK0; + VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET + # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS + VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE; + FIFO_WRE.CLK = DDRCLK0; +--------------------------------------------------------------- +-- BLITTER BUS IST 128 BIT BREIT ------ + BLITTER_SIG = GND & !CPU_SIG; + BLITTER_REQ.CLK = DDR_SYNC_66M; + BLITTER_RUN.CLK = DDRCLK0; + BLITTER_RUN = GND; + BLITTER_WR.CLK = DDRCLK0; + BLITTER_WR = GND; + DDRWR_D_SEL1 = BLITTER_WR; + BLITTER_ROW_ADR[] = H"0"; + BLITTER_BA1 = GND; + BLITTER_BA0 = GND; + BLITTER_COL_ADR[] = H"0"; + BLITTER_DOUT[] = H"0"; + BLITTER_LE[] = H"0"; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[31..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & VIDEO_BASE_X_D[] + # VIDEO_CNT_H & VIDEO_ADR_CNT[27..20] + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000") + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000") + # VIDEO_CNT_M & VIDEO_ADR_CNT[11..4] + # VIDEO_CNT_H & VIDEO_ADR_CNT[19..12] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); + + VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[]; + VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[]; + VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[]; + VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[]; +END; + diff --git a/FPGA_Quartus_13.1/Video/UNUSED b/FPGA_Quartus_13.1/Video/UNUSED new file mode 100644 index 0000000..12f424b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/UNUSED @@ -0,0 +1,267 @@ + +-- Clearbox generated Memory Initialization File (.mif) + +WIDTH=6; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 000 : 0F; + 001 : 0E; + 002 : 0D; + 003 : 0C; + 004 : 0B; + 005 : 0A; + 006 : 09; + 007 : 08; + 008 : 07; + 009 : 06; + 00a : 05; + 00b : 04; + 00c : 03; + 00d : 02; + 00e : 01; + 00f : 00; + 010 : 0F; + 011 : 0E; + 012 : 0D; + 013 : 0C; + 014 : 0B; + 015 : 0A; + 016 : 09; + 017 : 08; + 018 : 07; + 019 : 06; + 01a : 05; + 01b : 04; + 01c : 03; + 01d : 02; + 01e : 01; + 01f : 00; + 020 : 0F; + 021 : 0E; + 022 : 0D; + 023 : 0C; + 024 : 0B; + 025 : 0A; + 026 : 09; + 027 : 08; + 028 : 07; + 029 : 06; + 02a : 05; + 02b : 04; + 02c : 03; + 02d : 02; + 02e : 01; + 02f : 00; + 030 : 0F; + 031 : 0E; + 032 : 0D; + 033 : 0C; + 034 : 0B; + 035 : 0A; + 036 : 09; + 037 : 08; + 038 : 07; + 039 : 06; + 03a : 05; + 03b : 04; + 03c : 03; + 03d : 02; + 03e : 01; + 03f : 00; + 040 : 0F; + 041 : 0E; + 042 : 0D; + 043 : 0C; + 044 : 0B; + 045 : 0A; + 046 : 09; + 047 : 08; + 048 : 07; + 049 : 06; + 04a : 05; + 04b : 04; + 04c : 03; + 04d : 02; + 04e : 01; + 04f : 00; + 050 : 0F; + 051 : 0E; + 052 : 0D; + 053 : 0C; + 054 : 0B; + 055 : 0A; + 056 : 09; + 057 : 08; + 058 : 07; + 059 : 06; + 05a : 05; + 05b : 04; + 05c : 03; + 05d : 02; + 05e : 01; + 05f : 00; + 060 : 0F; + 061 : 0E; + 062 : 0D; + 063 : 0C; + 064 : 0B; + 065 : 0A; + 066 : 09; + 067 : 08; + 068 : 07; + 069 : 06; + 06a : 05; + 06b : 04; + 06c : 03; + 06d : 02; + 06e : 01; + 06f : 00; + 070 : 0F; + 071 : 0E; + 072 : 0D; + 073 : 0C; + 074 : 0B; + 075 : 0A; + 076 : 09; + 077 : 08; + 078 : 07; + 079 : 06; + 07a : 05; + 07b : 04; + 07c : 03; + 07d : 02; + 07e : 01; + 07f : 00; + 080 : 0F; + 081 : 0E; + 082 : 0D; + 083 : 0C; + 084 : 0B; + 085 : 0A; + 086 : 09; + 087 : 08; + 088 : 07; + 089 : 06; + 08a : 05; + 08b : 04; + 08c : 03; + 08d : 02; + 08e : 01; + 08f : 00; + 090 : 0F; + 091 : 0E; + 092 : 0D; + 093 : 0C; + 094 : 0B; + 095 : 0A; + 096 : 09; + 097 : 08; + 098 : 07; + 099 : 06; + 09a : 05; + 09b : 04; + 09c : 03; + 09d : 02; + 09e : 01; + 09f : 00; + 0a0 : 0F; + 0a1 : 0E; + 0a2 : 0D; + 0a3 : 0C; + 0a4 : 0B; + 0a5 : 0A; + 0a6 : 09; + 0a7 : 08; + 0a8 : 07; + 0a9 : 06; + 0aa : 05; + 0ab : 04; + 0ac : 03; + 0ad : 02; + 0ae : 01; + 0af : 00; + 0b0 : 0F; + 0b1 : 0E; + 0b2 : 0D; + 0b3 : 0C; + 0b4 : 0B; + 0b5 : 0A; + 0b6 : 09; + 0b7 : 08; + 0b8 : 07; + 0b9 : 06; + 0ba : 05; + 0bb : 04; + 0bc : 03; + 0bd : 02; + 0be : 01; + 0bf : 00; + 0c0 : 0F; + 0c1 : 0E; + 0c2 : 0D; + 0c3 : 0C; + 0c4 : 0B; + 0c5 : 0A; + 0c6 : 09; + 0c7 : 08; + 0c8 : 07; + 0c9 : 06; + 0ca : 05; + 0cb : 04; + 0cc : 03; + 0cd : 02; + 0ce : 01; + 0cf : 00; + 0d0 : 0F; + 0d1 : 0E; + 0d2 : 0D; + 0d3 : 0C; + 0d4 : 0B; + 0d5 : 0A; + 0d6 : 09; + 0d7 : 08; + 0d8 : 07; + 0d9 : 06; + 0da : 05; + 0db : 04; + 0dc : 03; + 0dd : 02; + 0de : 01; + 0df : 00; + 0e0 : 0F; + 0e1 : 0E; + 0e2 : 0D; + 0e3 : 0C; + 0e4 : 0B; + 0e5 : 0A; + 0e6 : 09; + 0e7 : 08; + 0e8 : 07; + 0e9 : 06; + 0ea : 05; + 0eb : 04; + 0ec : 03; + 0ed : 02; + 0ee : 01; + 0ef : 00; + 0f0 : 0F; + 0f1 : 0E; + 0f2 : 0D; + 0f3 : 0C; + 0f4 : 0B; + 0f5 : 0A; + 0f6 : 09; + 0f7 : 08; + 0f8 : 07; + 0f9 : 06; + 0fa : 05; + 0fb : 04; + 0fc : 03; + 0fd : 02; + 0fe : 01; + 0ff : 00; +END; diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf new file mode 100644 index 0000000..2c9adcc --- /dev/null +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -0,0 +1,675 @@ +TITLE "VIDEO MODUSE UND CLUT CONTROL"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_WORD.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN VIDEO_MOD_MUX_CLUTCTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + nRSTO : INPUT; + MAIN_CLK : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_WR : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nFB_BURST : INPUT; + FB_ADR[31..0] : INPUT; + CLK33M : INPUT; + CLK25M : INPUT; + BLITTER_RUN : INPUT; + CLK_VIDEO : INPUT; + VR_D[8..0] : INPUT; + VR_BUSY : INPUT; + COLOR8 : OUTPUT; + ACP_CLUT_RD : OUTPUT; + COLOR1 : OUTPUT; + FALCON_CLUT_RDH : OUTPUT; + FALCON_CLUT_RDL : OUTPUT; + FALCON_CLUT_WR[3..0] : OUTPUT; + ST_CLUT_RD : OUTPUT; + ST_CLUT_WR[1..0] : OUTPUT; + CLUT_MUX_ADR[3..0] : OUTPUT; + HSYNC : OUTPUT; + VSYNC : OUTPUT; + nBLANK : OUTPUT; + nSYNC : OUTPUT; + nPD_VGA : OUTPUT; + FIFO_RDE : OUTPUT; + COLOR2 : OUTPUT; + COLOR4 : OUTPUT; + PIXEL_CLK : OUTPUT; + CLUT_OFF[3..0] : OUTPUT; + BLITTER_ON : OUTPUT; + VIDEO_RAM_CTR[15..0] : OUTPUT; + VIDEO_MOD_TA : OUTPUT; + CCR[23..0] : OUTPUT; + CCSEL[2..0] : OUTPUT; + ACP_CLUT_WR[3..0] : OUTPUT; + INTER_ZEI : OUTPUT; + DOP_FIFO_CLR : OUTPUT; + VIDEO_RECONFIG : OUTPUT; + VR_WR : OUTPUT; + VR_RD : OUTPUT; + CLR_FIFO : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + CLK17M :DFF; + CLK13M :DFF; + ACP_CLUT_CS :NODE; + ACP_CLUT :NODE; + VIDEO_PLL_CONFIG_CS :NODE; + VR_WR :DFF; + VR_DOUT[8..0] :DFFE; + VR_FRQ[7..0] :DFFE; + VIDEO_PLL_RECONFIG_CS :NODE; + VIDEO_RECONFIG :DFF; + FALCON_CLUT_CS :NODE; + FALCON_CLUT :NODE; + ST_CLUT_CS :NODE; + ST_CLUT :NODE; + FB_B[3..0] :NODE; + FB_16B[1..0] :NODE; + ST_SHIFT_MODE[1..0] :DFFE; + ST_SHIFT_MODE_CS :NODE; + FALCON_SHIFT_MODE[10..0] :DFFE; + FALCON_SHIFT_MODE_CS :NODE; + CLUT_MUX_ADR[3..0] :DFF; + CLUT_MUX_AV[1..0][3..0] :DFF; + ACP_VCTR_CS :NODE; + ACP_VCTR[31..0] :DFFE; + CCR_CS :NODE; + CCR[23..0] :DFFE; + ACP_VIDEO_ON :NODE; + SYS_CTR[6..0] :DFFE; + SYS_CTR_CS :NODE; + VDL_LOF[15..0] :DFFE; + VDL_LOF_CS :NODE; + VDL_LWD[15..0] :DFFE; + VDL_LWD_CS :NODE; +-- DIV. CONTROL REGISTER + CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT + HSYNC :DFF; + HSYNC_I[7..0] :DFF; + HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK + HSYNC_START :DFF; + LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT + VSYNC :DFF; + VSYNC_START :DFFE; + VSYNC_I[2..0] :DFFE; + nBLANK :DFF; + DISP_ON :DFF; + DPO_ZL :DFFE; + DPO_ON :DFF; + DPO_OFF :DFF; + VDTRON :DFF; + VDO_ZL :DFFE; + VDO_ON :DFF; + VDO_OFF :DFF; + VHCNT[11..0] :DFF; + SUB_PIXEL_CNT[6..0] :DFFE; + VVCNT[10..0] :DFFE; + VERZ[2..0][9..0] :DFF; + RAND[6..0] :DFF; + RAND_ON :NODE; + FIFO_RDE :DFF; + CLR_FIFO :DFFE; + START_ZEILE :DFFE; + SYNC_PIX :DFF; + SYNC_PIX1 :DFF; + SYNC_PIX2 :DFF; + CCSEL[2..0] :DFF; + COLOR16 :NODE; + COLOR24 :NODE; +-- ATARI RESOLUTION + ATARI_SYNC :NODE; + ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 + ATARI_HH_CS :NODE; + ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480 + ATARI_VH_CS :NODE; + ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240 + ATARI_HL_CS :NODE; + ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240 + ATARI_VL_CS :NODE; +-- HORIZONTAL + RAND_LINKS[11..0] :NODE; + HDIS_START[11..0] :NODE; + HDIS_END[11..0] :NODE; + RAND_RECHTS[11..0] :NODE; + HS_START[11..0] :NODE; + H_TOTAL[11..0] :NODE; + HDIS_LEN[11..0] :NODE; + MULF[5..0] :NODE; + VDL_HHT[11..0] :DFFE; + VDL_HHT_CS :NODE; + VDL_HBE[11..0] :DFFE; + VDL_HBE_CS :NODE; + VDL_HDB[11..0] :DFFE; + VDL_HDB_CS :NODE; + VDL_HDE[11..0] :DFFE; + VDL_HDE_CS :NODE; + VDL_HBB[11..0] :DFFE; + VDL_HBB_CS :NODE; + VDL_HSS[11..0] :DFFE; + VDL_HSS_CS :NODE; +-- VERTIKAL + RAND_OBEN[10..0] :NODE; + VDIS_START[10..0] :NODE; + VDIS_END[10..0] :NODE; + RAND_UNTEN[10..0] :NODE; + VS_START[10..0] :NODE; + V_TOTAL[10..0] :NODE; + FALCON_VIDEO :NODE; + ST_VIDEO :NODE; + INTER_ZEI :DFF; + DOP_ZEI :DFF; + DOP_FIFO_CLR :DFF; + + VDL_VBE[10..0] :DFFE; + VDL_VBE_CS :NODE; + VDL_VDB[10..0] :DFFE; + VDL_VDB_CS :NODE; + VDL_VDE[10..0] :DFFE; + VDL_VDE_CS :NODE; + VDL_VBB[10..0] :DFFE; + VDL_VBB_CS :NODE; + VDL_VSS[10..0] :DFFE; + VDL_VSS_CS :NODE; + VDL_VFT[10..0] :DFFE; + VDL_VFT_CS :NODE; + VDL_VCT[8..0] :DFFE; + VDL_VCT_CS :NODE; + VDL_VMD[3..0] :DFFE; + VDL_VMD_CS :NODE; + +BEGIN +-- BYT SELECT 32 BIT + FB_B0 = FB_ADR[1..0]==0; -- ADR==0 + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- BYT SELECT 16 BIT + FB_16B0 = FB_ADR[0]==0; -- ADR==0 + FB_16B1 = FB_ADR[0]==1 -- ADR==1 + # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT +-- ACP CLUT -- + ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 + ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; + ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; + CLUT_TA.CLK = MAIN_CLK; + CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; +--FALCON CLUT -- + FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 + FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD + FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD + FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; + FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; +-- ST CLUT -- + ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 + ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; + ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; +-- ST SHIFT MODE + ST_SHIFT_MODE[].CLK = MAIN_CLK; + ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 + ST_SHIFT_MODE[] = FB_AD[25..24]; + ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; + COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN + COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN +-- FALCON SHIFT MODE + FALCON_SHIFT_MODE[].CLK = MAIN_CLK; + FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 + FALCON_SHIFT_MODE[] = FB_AD[26..16]; + FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; + FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; + CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; + COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; +-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + ACP_VCTR[].CLK = MAIN_CLK; + ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 + ACP_VCTR[31..8] = FB_AD[31..8]; + ACP_VCTR[5..0] = FB_AD[5..0]; + ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; + ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; + ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; + ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; + ACP_VIDEO_ON = ACP_VCTR0; + nPD_VGA = ACP_VCTR1; + -- ATARI MODUS + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG + -- HORIZONTAL TIMING 640x480 + ATARI_HH[].CLK = MAIN_CLK; + ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 + ATARI_HH[] = FB_AD[]; + ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; + ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; + ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; + ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 640x480 + ATARI_VH[].CLK = MAIN_CLK; + ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 + ATARI_VH[] = FB_AD[]; + ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; + ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; + ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; + ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; + -- HORIZONTAL TIMING 320x240 + ATARI_HL[].CLK = MAIN_CLK; + ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 + ATARI_HL[] = FB_AD[]; + ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; + ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; + ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; + ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 320x240 + ATARI_VL[].CLK = MAIN_CLK; + ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 + ATARI_VL[] = FB_AD[]; + ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; + ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; + ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; + ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; +-- VIDEO PLL CONFIG + VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + VR_WR.CLK = MAIN_CLK; + VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; + VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; + VR_DOUT[].CLK = MAIN_CLK; + VR_DOUT[].ENA = !VR_BUSY; + VR_DOUT[] = VR_D[]; + VR_FRQ[].CLK = MAIN_CLK; + VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; + VR_FRQ[] = FB_AD[23..16]; +-- VIDEO PLL RECONFIG + VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 + VIDEO_RECONFIG.CLK = MAIN_CLK; + VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; +------------------------------------------------------------------------------------------------------------------------ + VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; +-------------- COLOR MODE IM ACP SETZEN + COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; + ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; +-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; + FALCON_VIDEO = ACP_VCTR7; + FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; + ST_VIDEO = ACP_VCTR6; + ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; + CCSEL[].CLK = PIXEL_CLK; + CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION + # B"001" & FALCON_CLUT + # B"100" & ACP_CLUT + # B"101" & COLOR16 + # B"110" & COLOR24 + # B"111" & RAND_ON; +-- DIVERSE (VIDEO)-REGISTER ---------------------------- +-- RANDFARBE + CCR[].CLK = MAIN_CLK; + CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 + CCR[] = FB_AD[23..0]; + CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; + CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; + CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; +--SYS CTR + SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 + SYS_CTR[].CLK = MAIN_CLK; + SYS_CTR[6..0] = FB_AD[22..16]; + SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; + BLITTER_ON = !SYS_CTR3; +--VDL_LOF + VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 + VDL_LOF[].CLK = MAIN_CLK; + VDL_LOF[] = FB_AD[31..16]; + VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; + VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; +--VDL_LWD + VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 + VDL_LWD[].CLK = MAIN_CLK; + VDL_LWD[] = FB_AD[31..16]; + VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; + VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; +-- HORIZONTAL +-- VDL_HHT + VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 + VDL_HHT[].CLK = MAIN_CLK; + VDL_HHT[] = FB_AD[27..16]; + VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; + VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; +-- VDL_HBE + VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 + VDL_HBE[].CLK = MAIN_CLK; + VDL_HBE[] = FB_AD[27..16]; + VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; + VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; +-- VDL_HDB + VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 + VDL_HDB[].CLK = MAIN_CLK; + VDL_HDB[] = FB_AD[27..16]; + VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; + VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; +-- VDL_HDE + VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 + VDL_HDE[].CLK = MAIN_CLK; + VDL_HDE[] = FB_AD[27..16]; + VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; + VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; +-- VDL_HBB + VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 + VDL_HBB[].CLK = MAIN_CLK; + VDL_HBB[] = FB_AD[27..16]; + VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; + VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; +-- VDL_HSS + VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 + VDL_HSS[].CLK = MAIN_CLK; + VDL_HSS[] = FB_AD[27..16]; + VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; + VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; +-- VERTIKAL +-- VDL_VBE + VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 + VDL_VBE[].CLK = MAIN_CLK; + VDL_VBE[] = FB_AD[26..16]; + VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; + VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; +-- VDL_VDB + VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 + VDL_VDB[].CLK = MAIN_CLK; + VDL_VDB[] = FB_AD[26..16]; + VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; + VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; +-- VDL_VDE + VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 + VDL_VDE[].CLK = MAIN_CLK; + VDL_VDE[] = FB_AD[26..16]; + VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; + VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; +-- VDL_VBB + VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 + VDL_VBB[].CLK = MAIN_CLK; + VDL_VBB[] = FB_AD[26..16]; + VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; + VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; +-- VDL_VSS + VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 + VDL_VSS[].CLK = MAIN_CLK; + VDL_VSS[] = FB_AD[26..16]; + VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; + VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; +-- VDL_VFT + VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 + VDL_VFT[].CLK = MAIN_CLK; + VDL_VFT[] = FB_AD[26..16]; + VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; + VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; +-- VDL_VCT + VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 + VDL_VCT[].CLK = MAIN_CLK; + VDL_VCT[] = FB_AD[24..16]; + VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; + VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; +-- VDL_VMD + VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 + VDL_VMD[].CLK = MAIN_CLK; + VDL_VMD[] = FB_AD[19..16]; + VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; +--- REGISTER OUT + FB_AD[31..16] = lpm_bustri_WORD( + ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") + # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) + # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) + # VDL_LOF_CS & VDL_LOF[] + # VDL_LWD_CS & VDL_LWD[] + # VDL_HBE_CS & (0,VDL_HBE[]) + # VDL_HDB_CS & (0,VDL_HDB[]) + # VDL_HDE_CS & (0,VDL_HDE[]) + # VDL_HBB_CS & (0,VDL_HBB[]) + # VDL_HSS_CS & (0,VDL_HSS[]) + # VDL_HHT_CS & (0,VDL_HHT[]) + # VDL_VBE_CS & (0,VDL_VBE[]) + # VDL_VDB_CS & (0,VDL_VDB[]) + # VDL_VDE_CS & (0,VDL_VDE[]) + # VDL_VBB_CS & (0,VDL_VBB[]) + # VDL_VSS_CS & (0,VDL_VSS[]) + # VDL_VFT_CS & (0,VDL_VFT[]) + # VDL_VCT_CS & (0,VDL_VCT[]) + # VDL_VMD_CS & (0,VDL_VMD[]) + # ACP_VCTR_CS & ACP_VCTR[31..16] + # ATARI_HH_CS & ATARI_HH[31..16] + # ATARI_VH_CS & ATARI_VH[31..16] + # ATARI_HL_CS & ATARI_HL[31..16] + # ATARI_VL_CS & ATARI_VL[31..16] + # CCR_CS & (0,CCR[23..16]) + # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) + # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); + + FB_AD[15..0] = lpm_bustri_WORD( + ACP_VCTR_CS & ACP_VCTR[15..0] + # ATARI_HH_CS & ATARI_HH[15..0] + # ATARI_VH_CS & ATARI_VH[15..0] + # ATARI_HL_CS & ATARI_HL[15..0] + # ATARI_VL_CS & ATARI_VL[15..0] + # CCR_CS & CCR[15..0] + ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + + VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; + +-- VIDEO AUSGABE SETZEN + CLK17M.CLK = CLK33M; + CLK17M = !CLK17M; + CLK13M.CLK = CLK25M; + CLK13M = !CLK13M; + PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; +-------------------------------------------------------------- +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +---------------------------------------------------------------- + HSY_LEN[].CLK = MAIN_CLK; + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns + + MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR + # 4 & !ST_VIDEO & !VDL_VMD2 + # 16 & ST_VIDEO & VDL_VMD2 + # 32 & ST_VIDEO & !VDL_VMD2; + + + HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN + # 640 & !VDL_VMD2; + +-- DOPPELZEILENMODUS + DOP_ZEI.CLK = MAIN_CLK; + DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS + INTER_ZEI.CLK = PIXEL_CLK; + INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC + # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + DOP_FIFO_CLR.CLK = PIXEL_CLK; + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + + RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON + # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON + # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- + HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON + # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- + RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON + # HDIS_END[]+1 & !ACP_VIDEO_ON; -- + HS_START[] = VDL_HSS[] & ACP_VIDEO_ON + # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON + # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON + # 31 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON + # 32 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON + # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO + # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO + # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON + # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VS_START[] = VDL_VSS[] & ACP_VIDEO_ON + # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON + # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; +-- ZÄHLER + LAST.CLK = PIXEL_CLK; + LAST = VHCNT[]==(H_TOTAL[]-2); + VHCNT[].CLK = PIXEL_CLK; + VHCNT[] = (VHCNT[] + 1) & !LAST; + VVCNT[].CLK = PIXEL_CLK; + VVCNT[].ENA = LAST; + VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); +-- DISPLAY ON OFF + DPO_ZL.CLK = PIXEL_CLK; + DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[]6/2 WORD RESP LONG ONLY + VR_WR.CLK = MAIN_CLK; + VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; + VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; + VR_DOUT[].CLK = MAIN_CLK; + VR_DOUT[].ENA = !VR_BUSY; + VR_DOUT[] = VR_D[]; + VR_FRQ[].CLK = MAIN_CLK; + VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; + VR_FRQ[] = FB_AD[23..16]; +-- VIDEO PLL RECONFIG + VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 + VIDEO_RECONFIG.CLK = MAIN_CLK; + VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; +------------------------------------------------------------------------------------------------------------------------ + VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; +-------------- COLOR MODE IM ACP SETZEN + COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; + ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; +-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; + FALCON_VIDEO = ACP_VCTR7; + FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; + ST_VIDEO = ACP_VCTR6; + ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; + CCSEL[].CLK = PIXEL_CLK; + CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION + # B"001" & FALCON_CLUT + # B"100" & ACP_CLUT + # B"101" & COLOR16 + # B"110" & COLOR24 + # B"111" & RAND_ON; +-- DIVERSE (VIDEO)-REGISTER ---------------------------- +-- RANDFARBE + CCR[].CLK = MAIN_CLK; + CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 + CCR[] = FB_AD[23..0]; + CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; + CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; + CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; +--SYS CTR + SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 + SYS_CTR[].CLK = MAIN_CLK; + SYS_CTR[6..0] = FB_AD[22..16]; + SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; + BLITTER_ON = !SYS_CTR3; +--VDL_LOF + VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 + VDL_LOF[].CLK = MAIN_CLK; + VDL_LOF[] = FB_AD[31..16]; + VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; + VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; +--VDL_LWD + VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 + VDL_LWD[].CLK = MAIN_CLK; + VDL_LWD[] = FB_AD[31..16]; + VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; + VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; +-- HORIZONTAL +-- VDL_HHT + VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 + VDL_HHT[].CLK = MAIN_CLK; + VDL_HHT[] = FB_AD[27..16]; + VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; + VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; +-- VDL_HBE + VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 + VDL_HBE[].CLK = MAIN_CLK; + VDL_HBE[] = FB_AD[27..16]; + VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; + VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; +-- VDL_HDB + VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 + VDL_HDB[].CLK = MAIN_CLK; + VDL_HDB[] = FB_AD[27..16]; + VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; + VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; +-- VDL_HDE + VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 + VDL_HDE[].CLK = MAIN_CLK; + VDL_HDE[] = FB_AD[27..16]; + VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; + VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; +-- VDL_HBB + VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 + VDL_HBB[].CLK = MAIN_CLK; + VDL_HBB[] = FB_AD[27..16]; + VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; + VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; +-- VDL_HSS + VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 + VDL_HSS[].CLK = MAIN_CLK; + VDL_HSS[] = FB_AD[27..16]; + VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; + VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; +-- VERTIKAL +-- VDL_VBE + VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 + VDL_VBE[].CLK = MAIN_CLK; + VDL_VBE[] = FB_AD[26..16]; + VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; + VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; +-- VDL_VDB + VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 + VDL_VDB[].CLK = MAIN_CLK; + VDL_VDB[] = FB_AD[26..16]; + VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; + VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; +-- VDL_VDE + VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 + VDL_VDE[].CLK = MAIN_CLK; + VDL_VDE[] = FB_AD[26..16]; + VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; + VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; +-- VDL_VBB + VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 + VDL_VBB[].CLK = MAIN_CLK; + VDL_VBB[] = FB_AD[26..16]; + VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; + VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; +-- VDL_VSS + VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 + VDL_VSS[].CLK = MAIN_CLK; + VDL_VSS[] = FB_AD[26..16]; + VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; + VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; +-- VDL_VFT + VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 + VDL_VFT[].CLK = MAIN_CLK; + VDL_VFT[] = FB_AD[26..16]; + VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; + VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; +-- VDL_VCT + VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 + VDL_VCT[].CLK = MAIN_CLK; + VDL_VCT[] = FB_AD[24..16]; + VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; + VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; +-- VDL_VMD + VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 + VDL_VMD[].CLK = MAIN_CLK; + VDL_VMD[] = FB_AD[19..16]; + VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; +--- REGISTER OUT + FB_AD[31..16] = lpm_bustri_WORD( + ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") + # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) + # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) + # VDL_LOF_CS & VDL_LOF[] + # VDL_LWD_CS & VDL_LWD[] + # VDL_HBE_CS & (0,VDL_HBE[]) + # VDL_HDB_CS & (0,VDL_HDB[]) + # VDL_HDE_CS & (0,VDL_HDE[]) + # VDL_HBB_CS & (0,VDL_HBB[]) + # VDL_HSS_CS & (0,VDL_HSS[]) + # VDL_HHT_CS & (0,VDL_HHT[]) + # VDL_VBE_CS & (0,VDL_VBE[]) + # VDL_VDB_CS & (0,VDL_VDB[]) + # VDL_VDE_CS & (0,VDL_VDE[]) + # VDL_VBB_CS & (0,VDL_VBB[]) + # VDL_VSS_CS & (0,VDL_VSS[]) + # VDL_VFT_CS & (0,VDL_VFT[]) + # VDL_VCT_CS & (0,VDL_VCT[]) + # VDL_VMD_CS & (0,VDL_VMD[]) + # ACP_VCTR_CS & ACP_VCTR[31..16] + # ATARI_HH_CS & ATARI_HH[31..16] + # ATARI_VH_CS & ATARI_VH[31..16] + # ATARI_HL_CS & ATARI_HL[31..16] + # ATARI_VL_CS & ATARI_VL[31..16] + # CCR_CS & (0,CCR[23..16]) + # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) + # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); + + FB_AD[15..0] = lpm_bustri_WORD( + ACP_VCTR_CS & ACP_VCTR[15..0] + # ATARI_HH_CS & ATARI_HH[15..0] + # ATARI_VH_CS & ATARI_VH[15..0] + # ATARI_HL_CS & ATARI_HL[15..0] + # ATARI_VL_CS & ATARI_VL[15..0] + # CCR_CS & CCR[15..0] + ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + + VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; + +-- VIDEO AUSGABE SETZEN + CLK17M.CLK = CLK33M; + CLK17M = !CLK17M; + CLK13M.CLK = CLK25M; + CLK13M = !CLK13M; + PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; +-------------------------------------------------------------- +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +---------------------------------------------------------------- + HSY_LEN[].CLK = MAIN_CLK; + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns + + MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR + # 4 & !ST_VIDEO & !VDL_VMD2 + # 16 & ST_VIDEO & VDL_VMD2 + # 32 & ST_VIDEO & !VDL_VMD2; + + + HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN + # 640 & !VDL_VMD2; + +-- DOPPELZEILENMODUS + DOP_ZEI.CLK = MAIN_CLK; + DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS + INTER_ZEI.CLK = PIXEL_CLK; + INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC + # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + DOP_FIFO_CLR.CLK = PIXEL_CLK; + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + + RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON + # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON + # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- + HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON + # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- + RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON + # HDIS_END[]+1 & !ACP_VIDEO_ON; -- + HS_START[] = VDL_HSS[] & ACP_VIDEO_ON + # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON + # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON + # 31 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON + # 32 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON + # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO + # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO + # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON + # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VS_START[] = VDL_VSS[] & ACP_VIDEO_ON + # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON + # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; +-- ZÄHLER + LAST.CLK = PIXEL_CLK; + LAST = VHCNT[]==(H_TOTAL[]-2); + VHCNT[].CLK = PIXEL_CLK; + VHCNT[] = (VHCNT[] + 1) & !LAST; + VVCNT[].CLK = PIXEL_CLK; + VVCNT[].ENA = LAST; + VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); +-- DISPLAY ON OFF + DPO_ZL.CLK = PIXEL_CLK; + DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] + + + + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.qip b/FPGA_Quartus_13.1/Video/altddio_bidir0.qip new file mode 100644 index 0000000..3339057 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_bidir0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"] diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.vhd b/FPGA_Quartus_13.1/Video/altddio_bidir0.vhd new file mode 100644 index 0000000..a0ae0e0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_bidir0.vhd @@ -0,0 +1,172 @@ +-- megafunction wizard: %ALTDDIO_BIDIR% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_bidir + +-- ============================================================ +-- File Name: altddio_bidir0.vhd +-- Megafunction Name(s): +-- altddio_bidir +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_bidir0 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + inclock : IN STD_LOGIC ; + oe : IN STD_LOGIC := '1'; + outclock : IN STD_LOGIC ; + combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END altddio_bidir0; + + +ARCHITECTURE SYN OF altddio_bidir0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT altddio_bidir + GENERIC ( + extend_oe_disable : STRING; + implement_input_in_lcell : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + outclock : IN STD_LOGIC ; + padio : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); + inclock : IN STD_LOGIC ; + dataout_h : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + oe : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + combout : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout_h <= sub_wire0(31 DOWNTO 0); + combout <= sub_wire1(31 DOWNTO 0); + dataout_l <= sub_wire2(31 DOWNTO 0); + + altddio_bidir_component : altddio_bidir + GENERIC MAP ( + extend_oe_disable => "UNUSED", + implement_input_in_lcell => "ON", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_bidir", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 32 + ) + PORT MAP ( + outclock => outclock, + inclock => inclock, + oe => oe, + datain_h => datain_h, + datain_l => datain_l, + dataout_h => sub_wire0, + combout => sub_wire1, + dataout_l => sub_wire2, + padio => padio + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "1" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1" +-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1" +-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0] +-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0] +-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0] +-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0] +-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0] +-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock +-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0] +-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0 +-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0 +-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0 +-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0 +-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0 +-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0 +-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.bsf b/FPGA_Quartus_13.1/Video/altddio_out0.bsf new file mode 100644 index 0000000..6554c2f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out0.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8))) + (text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 3)) + ) + (port + (pt 0 40) + (input) + (text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8))) + (text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 3)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "high" (rect 92 84 109 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.cmp b/FPGA_Quartus_13.1/Video/altddio_out0.cmp new file mode 100644 index 0000000..df70a5a --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out0.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out0 + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.inc b/FPGA_Quartus_13.1/Video/altddio_out0.inc new file mode 100644 index 0000000..f534925 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out0.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out0 +( + datain_h[3..0], + datain_l[3..0], + outclock +) + +RETURNS ( + dataout[3..0] +); diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.ppf b/FPGA_Quartus_13.1/Video/altddio_out0.ppf new file mode 100644 index 0000000..3f3cfb5 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out0.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.qip b/FPGA_Quartus_13.1/Video/altddio_out0.qip new file mode 100644 index 0000000..8193856 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.vhd b/FPGA_Quartus_13.1/Video/altddio_out0.vhd new file mode 100644 index 0000000..f129798 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out0.vhd @@ -0,0 +1,136 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out0.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out0 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END altddio_out0; + + +ARCHITECTURE SYN OF altddio_out0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout <= sub_wire0(3 DOWNTO 0); + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "ON", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "ON", + width => 4 + ) + PORT MAP ( + outclock => outclock, + datain_h => datain_h, + datain_l => datain_l, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "4" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0] +-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0] +-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0] +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0 +-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0 +-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.bsf b/FPGA_Quartus_13.1/Video/altddio_out1.bsf new file mode 100644 index 0000000..8289852 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out1.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.cmp b/FPGA_Quartus_13.1/Video/altddio_out1.cmp new file mode 100644 index 0000000..cdb7766 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out1.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out1 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.inc b/FPGA_Quartus_13.1/Video/altddio_out1.inc new file mode 100644 index 0000000..4d50b26 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out1.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out1 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.ppf b/FPGA_Quartus_13.1/Video/altddio_out1.ppf new file mode 100644 index 0000000..9772cd3 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out1.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.qip b/FPGA_Quartus_13.1/Video/altddio_out1.qip new file mode 100644 index 0000000..606e0b7 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out1.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"] diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.vhd b/FPGA_Quartus_13.1/Video/altddio_out1.vhd new file mode 100644 index 0000000..cb76474 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out1.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out1.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out1 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out1; + + +ARCHITECTURE SYN OF altddio_out1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.bsf b/FPGA_Quartus_13.1/Video/altddio_out2.bsf new file mode 100644 index 0000000..ff039ee --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out2.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8))) + (text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 3)) + ) + (port + (pt 0 40) + (input) + (text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8))) + (text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 3)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.cmp b/FPGA_Quartus_13.1/Video/altddio_out2.cmp new file mode 100644 index 0000000..ad8aa55 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out2.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out2 + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.inc b/FPGA_Quartus_13.1/Video/altddio_out2.inc new file mode 100644 index 0000000..2257c30 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out2.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out2 +( + datain_h[23..0], + datain_l[23..0], + outclock +) + +RETURNS ( + dataout[23..0] +); diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.ppf b/FPGA_Quartus_13.1/Video/altddio_out2.ppf new file mode 100644 index 0000000..93df472 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out2.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.qip b/FPGA_Quartus_13.1/Video/altddio_out2.qip new file mode 100644 index 0000000..d72d5ce --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out2.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"] diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.vhd b/FPGA_Quartus_13.1/Video/altddio_out2.vhd new file mode 100644 index 0000000..30a8586 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altddio_out2.vhd @@ -0,0 +1,136 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out2.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out2 IS + PORT + ( + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END altddio_out2; + + +ARCHITECTURE SYN OF altddio_out2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + dataout <= sub_wire0(23 DOWNTO 0); + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 24 + ) + PORT MAP ( + outclock => outclock, + datain_h => datain_h, + datain_l => datain_l, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0] +-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0] +-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0] +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0 +-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0 +-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Video/altdpram0.bsf b/FPGA_Quartus_13.1/Video/altdpram0.bsf new file mode 100644 index 0000000..e0d3ce3 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram0.bsf @@ -0,0 +1,173 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 256 208) + (text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 192 25 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 112 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 112 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 112 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 112 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 112 128)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 176 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8))) + (line (pt 0 176)(pt 181 176)(line_width 1)) + ) + (port + (pt 256 32) + (output) + (text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q_a[2..0]" (rect 211 19 253 32)(font "Arial" (font_size 8))) + (line (pt 256 32)(pt 192 32)(line_width 3)) + ) + (port + (pt 256 96) + (output) + (text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q_b[2..0]" (rect 211 83 253 96)(font "Arial" (font_size 8))) + (line (pt 256 96)(pt 192 96)(line_width 3)) + ) + (drawing + (text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical)) + (text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical)) + (text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" )) + (line (pt 128 24)(pt 168 24)(line_width 1)) + (line (pt 168 24)(pt 168 144)(line_width 1)) + (line (pt 168 144)(pt 128 144)(line_width 1)) + (line (pt 128 144)(pt 128 24)(line_width 1)) + (line (pt 112 27)(pt 120 27)(line_width 1)) + (line (pt 120 27)(pt 120 39)(line_width 1)) + (line (pt 120 39)(pt 112 39)(line_width 1)) + (line (pt 112 39)(pt 112 27)(line_width 1)) + (line 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132)(line_width 1)) + (line (pt 120 128)(pt 128 128)(line_width 1)) + (line (pt 92 36)(pt 92 161)(line_width 1)) + (line (pt 176 36)(pt 176 161)(line_width 1)) + (line (pt 104 100)(pt 104 177)(line_width 1)) + (line (pt 181 100)(pt 181 177)(line_width 1)) + (line (pt 184 27)(pt 192 27)(line_width 1)) + (line (pt 192 27)(pt 192 39)(line_width 1)) + (line (pt 192 39)(pt 184 39)(line_width 1)) + (line (pt 184 39)(pt 184 27)(line_width 1)) + (line (pt 184 34)(pt 186 36)(line_width 1)) + (line (pt 186 36)(pt 184 38)(line_width 1)) + (line (pt 176 36)(pt 184 36)(line_width 1)) + (line (pt 168 32)(pt 184 32)(line_width 3)) + (line (pt 184 91)(pt 192 91)(line_width 1)) + (line (pt 192 91)(pt 192 103)(line_width 1)) + (line (pt 192 103)(pt 184 103)(line_width 1)) + (line (pt 184 103)(pt 184 91)(line_width 1)) + (line (pt 184 98)(pt 186 100)(line_width 1)) + (line (pt 186 100)(pt 184 102)(line_width 1)) + (line (pt 181 100)(pt 184 100)(line_width 1)) + (line (pt 168 96)(pt 184 96)(line_width 3)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/altdpram0.cmp b/FPGA_Quartus_13.1/Video/altdpram0.cmp new file mode 100644 index 0000000..566f5cd --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram0.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altdpram0 + PORT + ( + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/altdpram0.inc b/FPGA_Quartus_13.1/Video/altdpram0.inc new file mode 100644 index 0000000..828067d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram0.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altdpram0 +( + address_a[3..0], + address_b[3..0], + clock_a, + clock_b, + data_a[2..0], + data_b[2..0], + wren_a, + wren_b +) + +RETURNS ( + q_a[2..0], + q_b[2..0] +); diff --git a/FPGA_Quartus_13.1/Video/altdpram0.qip b/FPGA_Quartus_13.1/Video/altdpram0.qip new file mode 100644 index 0000000..e4d02ab --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/altdpram0.vhd b/FPGA_Quartus_13.1/Video/altdpram0.vhd new file mode 100644 index 0000000..c883f02 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram0.vhd @@ -0,0 +1,273 @@ +-- megafunction wizard: %LPM_RAM_DP+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: altdpram0.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altdpram0 IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +END altdpram0; + + +ARCHITECTURE SYN OF altdpram0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (2 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (2 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (2 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(2 DOWNTO 0); + q_b <= sub_wire1(2 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 16, + numwords_b => 16, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "CLOCK0", + outdata_reg_b => "CLOCK1", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "OLD_DATA", + read_during_write_mode_port_b => "OLD_DATA", + widthad_a => 4, + widthad_b => 4, + width_a => 3, + width_b => 3, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: ECC NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0] +-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0] +-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0] +-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0] +-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0 +-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0 +-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0 +-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0 +-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git 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Sample behavioral waveforms for design file altdpram0.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_Quartus_13.1/Video/altdpram1.bsf b/FPGA_Quartus_13.1/Video/altdpram1.bsf new file mode 100644 index 0000000..d75db28 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram1.bsf @@ -0,0 +1,173 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 256 208) + (text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 192 25 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 112 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 112 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + 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+ ) +) diff --git a/FPGA_Quartus_13.1/Video/altdpram1.cmp b/FPGA_Quartus_13.1/Video/altdpram1.cmp new file mode 100644 index 0000000..a482250 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram1.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altdpram1 + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/altdpram1.inc b/FPGA_Quartus_13.1/Video/altdpram1.inc new file mode 100644 index 0000000..4a7924e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram1.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altdpram1 +( + address_a[7..0], + address_b[7..0], + clock_a, + clock_b, + data_a[5..0], + data_b[5..0], + wren_a, + wren_b +) + +RETURNS ( + q_a[5..0], + q_b[5..0] +); diff --git a/FPGA_Quartus_13.1/Video/altdpram1.qip b/FPGA_Quartus_13.1/Video/altdpram1.qip new file mode 100644 index 0000000..cdd178f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/altdpram1.vhd b/FPGA_Quartus_13.1/Video/altdpram1.vhd new file mode 100644 index 0000000..b2e0435 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram1.vhd @@ -0,0 +1,273 @@ +-- megafunction wizard: %LPM_RAM_DP+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: altdpram1.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altdpram1 IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +END altdpram1; + + +ARCHITECTURE SYN OF altdpram1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (5 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(5 DOWNTO 0); + q_b <= sub_wire1(5 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 256, + numwords_b => 256, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "CLOCK0", + outdata_reg_b => "CLOCK1", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "OLD_DATA", + read_during_write_mode_port_b => "OLD_DATA", + widthad_a => 8, + widthad_b => 8, + width_a => 6, + width_b => 6, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: ECC NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0] +-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0] +-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0] +-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0] +-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0 +-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0 +-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0 +-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git 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zpZhYz=TR0wc$OwW%DTrC2%p^WMhL$K0@hac&wNnx2q1hy1*_Yg57M4r2*y&0pC8T| zAbjYzjp@Zxl>eTV|L3)g7P>gTi!Gm`$08ed zw)&84@$|jebc8g)k?OBMJV$Es=Kd17h9H|MiDMcp8o#Oke)tT9w>WWMS-Lsl@m49r zCJT0Qu+{Bj7te(>`;7YL(a$s$SvF%mu><+BX|C6py);*a%=sdt2fb7`X`5KN?668| z7d$ODhIy#0p9 + +Sample Waveforms for altdpram1.vhd + + +

Sample behavioral waveforms for design file altdpram1.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_Quartus_13.1/Video/altdpram2.bsf b/FPGA_Quartus_13.1/Video/altdpram2.bsf new file mode 100644 index 0000000..75c64aa --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram2.bsf @@ -0,0 +1,173 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 256 208) + (text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 192 25 204)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 112 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 112 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 112 64)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 112 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8))) + (text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 112 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 112 128)(line_width 1)) + ) + (port + (pt 0 160) + (input) + (text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8))) + (line (pt 0 160)(pt 176 160)(line_width 1)) + ) + (port + (pt 0 176) + (input) + (text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8))) + (line (pt 0 176)(pt 181 176)(line_width 1)) + ) + (port + (pt 256 32) + (output) + (text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8))) + (line (pt 256 32)(pt 192 32)(line_width 3)) + ) + (port + (pt 256 96) + (output) + (text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8))) + (line (pt 256 96)(pt 192 96)(line_width 3)) + ) + (drawing + (text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical)) + (text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical)) + (text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" )) + (line (pt 128 24)(pt 168 24)(line_width 1)) + (line (pt 168 24)(pt 168 144)(line_width 1)) + (line (pt 168 144)(pt 128 144)(line_width 1)) + (line (pt 128 144)(pt 128 24)(line_width 1)) + (line (pt 112 27)(pt 120 27)(line_width 1)) + (line (pt 120 27)(pt 120 39)(line_width 1)) + (line (pt 120 39)(pt 112 39)(line_width 1)) + (line (pt 112 39)(pt 112 27)(line_width 1)) + (line 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132)(line_width 1)) + (line (pt 120 128)(pt 128 128)(line_width 1)) + (line (pt 92 36)(pt 92 161)(line_width 1)) + (line (pt 176 36)(pt 176 161)(line_width 1)) + (line (pt 104 100)(pt 104 177)(line_width 1)) + (line (pt 181 100)(pt 181 177)(line_width 1)) + (line (pt 184 27)(pt 192 27)(line_width 1)) + (line (pt 192 27)(pt 192 39)(line_width 1)) + (line (pt 192 39)(pt 184 39)(line_width 1)) + (line (pt 184 39)(pt 184 27)(line_width 1)) + (line (pt 184 34)(pt 186 36)(line_width 1)) + (line (pt 186 36)(pt 184 38)(line_width 1)) + (line (pt 176 36)(pt 184 36)(line_width 1)) + (line (pt 168 32)(pt 184 32)(line_width 3)) + (line (pt 184 91)(pt 192 91)(line_width 1)) + (line (pt 192 91)(pt 192 103)(line_width 1)) + (line (pt 192 103)(pt 184 103)(line_width 1)) + (line (pt 184 103)(pt 184 91)(line_width 1)) + (line (pt 184 98)(pt 186 100)(line_width 1)) + (line (pt 186 100)(pt 184 102)(line_width 1)) + (line (pt 181 100)(pt 184 100)(line_width 1)) + (line (pt 168 96)(pt 184 96)(line_width 3)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/altdpram2.cmp b/FPGA_Quartus_13.1/Video/altdpram2.cmp new file mode 100644 index 0000000..4895f04 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram2.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altdpram2 + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/altdpram2.inc b/FPGA_Quartus_13.1/Video/altdpram2.inc new file mode 100644 index 0000000..1909de8 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram2.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altdpram2 +( + address_a[7..0], + address_b[7..0], + clock_a, + clock_b, + data_a[7..0], + data_b[7..0], + wren_a, + wren_b +) + +RETURNS ( + q_a[7..0], + q_b[7..0] +); diff --git a/FPGA_Quartus_13.1/Video/altdpram2.qip b/FPGA_Quartus_13.1/Video/altdpram2.qip new file mode 100644 index 0000000..f84925c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram2.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/altdpram2.vhd b/FPGA_Quartus_13.1/Video/altdpram2.vhd new file mode 100644 index 0000000..238e6f3 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/altdpram2.vhd @@ -0,0 +1,273 @@ +-- megafunction wizard: %LPM_RAM_DP+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: altdpram2.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altdpram2 IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + clock_a : IN STD_LOGIC ; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + wren_a : IN STD_LOGIC := '1'; + wren_b : IN STD_LOGIC := '1'; + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END altdpram2; + + +ARCHITECTURE SYN OF altdpram2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + address_reg_b : STRING; + clock_enable_input_a : STRING; + clock_enable_input_b : STRING; + clock_enable_output_a : STRING; + clock_enable_output_b : STRING; + indata_reg_b : STRING; + intended_device_family : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + numwords_b : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_aclr_b : STRING; + outdata_reg_a : STRING; + outdata_reg_b : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + read_during_write_mode_port_b : STRING; + widthad_a : NATURAL; + widthad_b : NATURAL; + width_a : NATURAL; + width_b : NATURAL; + width_byteena_a : NATURAL; + width_byteena_b : NATURAL; + wrcontrol_wraddress_reg_b : STRING + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + wren_b : IN STD_LOGIC ; + clock1 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q_a <= sub_wire0(7 DOWNTO 0); + q_b <= sub_wire1(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + intended_device_family => "Cyclone III", + lpm_type => "altsyncram", + numwords_a => 256, + numwords_b => 256, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "CLOCK0", + outdata_reg_b => "CLOCK1", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "OLD_DATA", + read_during_write_mode_port_b => "OLD_DATA", + widthad_a => 8, + widthad_b => 8, + width_a => 8, + width_b => 8, + width_byteena_a => 1, + width_byteena_b => 1, + wrcontrol_wraddress_reg_b => "CLOCK1" + ) + PORT MAP ( + wren_a => wren_a, + clock0 => clock_a, + wren_b => wren_b, + clock1 => clock_b, + address_a => address_a, + address_b => address_b, + data_a => data_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: ECC NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "0" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0] +-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0] +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b +-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0] +-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0] +-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0] +-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0] +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b +-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0 +-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0 +-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0 +-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git 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Sample behavioral waveforms for design file altdpram2.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri0.bsf new file mode 100644 index 0000000..f65e217 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri0.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "32" (rect 61 25 71 37)(font "Arial" )) + (text "32" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri0.cmp new file mode 100644 index 0000000..9426443 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri0.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri0 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.inc b/FPGA_Quartus_13.1/Video/lpm_bustri0.inc new file mode 100644 index 0000000..1b15c22 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri0.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri0 +( + data[31..0], + enabledt +) + +RETURNS ( + tridata[31..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.qip b/FPGA_Quartus_13.1/Video/lpm_bustri0.qip new file mode 100644 index 0000000..c70041d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri0.vhd new file mode 100644 index 0000000..494b3c2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri0.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri0.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri0 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_bustri0; + + +ARCHITECTURE SYN OF lpm_bustri0 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 32 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0] +-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri1.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri1.bsf new file mode 100644 index 0000000..058fffb --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri1.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "3" (rect 63 25 68 37)(font "Arial" )) + (text "3" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri1.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri1.cmp new file mode 100644 index 0000000..48a33f0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri1 + PORT + ( + data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri1.qip b/FPGA_Quartus_13.1/Video/lpm_bustri1.qip new file mode 100644 index 0000000..fd76bb2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri1.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri1.vhd new file mode 100644 index 0000000..47db597 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri1.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri1.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri1 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); +END lpm_bustri1; + + +ARCHITECTURE SYN OF lpm_bustri1 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (2 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 3 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "3" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3" +-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0] +-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0 +-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri2.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri2.bsf new file mode 100644 index 0000000..36a4813 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri2.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "18" (rect 61 25 71 37)(font "Arial" )) + (text "18" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri2.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri2.cmp new file mode 100644 index 0000000..e45fbdd --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri2.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri2 + PORT + ( + data : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri2.qip b/FPGA_Quartus_13.1/Video/lpm_bustri2.qip new file mode 100644 index 0000000..676e430 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri2.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri2.vhd new file mode 100644 index 0000000..0966743 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri2.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri2.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri2 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +END lpm_bustri2; + + +ARCHITECTURE SYN OF lpm_bustri2 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 18 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "18" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0] +-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0 +-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri3.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri3.bsf new file mode 100644 index 0000000..2dde401 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri3.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "6" (rect 63 25 68 37)(font "Arial" )) + (text "6" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri3.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri3.cmp new file mode 100644 index 0000000..f3836e3 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri3.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri3 + PORT + ( + data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri3.qip b/FPGA_Quartus_13.1/Video/lpm_bustri3.qip new file mode 100644 index 0000000..8c41556 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri3.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri3.vhd new file mode 100644 index 0000000..2344712 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri3.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri3.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri3 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +END lpm_bustri3; + + +ARCHITECTURE SYN OF lpm_bustri3 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 6 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "6" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6" +-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0] +-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0 +-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri4.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri4.bsf new file mode 100644 index 0000000..cd9edcc --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri4.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "5" (rect 63 25 68 37)(font "Arial" )) + (text "5" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri4.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri4.cmp new file mode 100644 index 0000000..37bee59 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri4.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri4 + PORT + ( + data : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri4.qip b/FPGA_Quartus_13.1/Video/lpm_bustri4.qip new file mode 100644 index 0000000..39eb21d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri4.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri4.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri4.vhd new file mode 100644 index 0000000..5bb209b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri4.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri4.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri4 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_bustri4; + + +ARCHITECTURE SYN OF lpm_bustri4 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 5 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0] +-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0 +-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri5.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri5.bsf new file mode 100644 index 0000000..1d9b178 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri5.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "8" (rect 63 25 68 37)(font "Arial" )) + (text "8" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri5.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri5.cmp new file mode 100644 index 0000000..5c719c7 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri5.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri5 + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri5.inc b/FPGA_Quartus_13.1/Video/lpm_bustri5.inc new file mode 100644 index 0000000..fdb4877 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri5.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri5 +( + data[7..0], + enabledt +) + +RETURNS ( + tridata[7..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri5.qip b/FPGA_Quartus_13.1/Video/lpm_bustri5.qip new file mode 100644 index 0000000..daa3efa --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri5.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri5.vhd new file mode 100644 index 0000000..e1973b4 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri5.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri5.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri5 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_bustri5; + + +ARCHITECTURE SYN OF lpm_bustri5 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 8 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0] +-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri6.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri6.bsf new file mode 100644 index 0000000..4c9344e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri6.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "24" (rect 61 25 71 37)(font "Arial" )) + (text "24" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 56 28)(pt 64 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri6.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri6.cmp new file mode 100644 index 0000000..67529c9 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri6.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri6 + PORT + ( + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri6.qip b/FPGA_Quartus_13.1/Video/lpm_bustri6.qip new file mode 100644 index 0000000..6b9f1df --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri6.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri6.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri6.vhd new file mode 100644 index 0000000..45f409f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri6.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri6.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri6 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_bustri6; + + +ARCHITECTURE SYN OF lpm_bustri6 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 24 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 24 0 BIDIR NODEFVAL tridata[23..0] +-- Retrieval info: CONNECT: tridata 0 0 24 0 @tridata 0 0 24 0 +-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri7.bsf b/FPGA_Quartus_13.1/Video/lpm_bustri7.bsf new file mode 100644 index 0000000..399a828 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri7.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 40) + (text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 80 24) + (bidir) + (text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 80 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "4" (rect 63 25 68 37)(font "Arial" )) + (text "4" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 58 28)(pt 66 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri7.cmp b/FPGA_Quartus_13.1/Video/lpm_bustri7.cmp new file mode 100644 index 0000000..2d5983d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri7.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri7 + PORT + ( + data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri7.qip b/FPGA_Quartus_13.1/Video/lpm_bustri7.qip new file mode 100644 index 0000000..f32324c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri7.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri7.vhd b/FPGA_Quartus_13.1/Video/lpm_bustri7.vhd new file mode 100644 index 0000000..4bf883d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_bustri7.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri7.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri7 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END lpm_bustri7; + + +ARCHITECTURE SYN OF lpm_bustri7 IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 4 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 4 0 BIDIR NODEFVAL tridata[3..0] +-- Retrieval info: CONNECT: tridata 0 0 4 0 @tridata 0 0 4 0 +-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_compare1.bsf b/FPGA_Quartus_13.1/Video/lpm_compare1.bsf new file mode 100644 index 0000000..9ec3796 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_compare1.bsf @@ -0,0 +1,54 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 128 96) + (text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 48) + (input) + (text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 128 56) + (output) + (text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8))) + (line (pt 128 56)(pt 112 56)(line_width 1)) + ) + (drawing + (text "unsigned compare" (rect 36 17 112 29)(font "Arial" )) + (line (pt 16 16)(pt 112 16)(line_width 1)) + (line (pt 112 16)(pt 112 80)(line_width 1)) + (line (pt 112 80)(pt 16 80)(line_width 1)) + (line (pt 16 80)(pt 16 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_compare1.cmp b/FPGA_Quartus_13.1/Video/lpm_compare1.cmp new file mode 100644 index 0000000..9bab50e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_compare1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_compare1 + PORT + ( + dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + AgB : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_compare1.inc b/FPGA_Quartus_13.1/Video/lpm_compare1.inc new file mode 100644 index 0000000..bde0ab9 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_compare1.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_compare1 +( + dataa[10..0], + datab[10..0] +) + +RETURNS ( + AgB +); diff --git a/FPGA_Quartus_13.1/Video/lpm_compare1.qip b/FPGA_Quartus_13.1/Video/lpm_compare1.qip new file mode 100644 index 0000000..ea93f3c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_compare1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_compare1.vhd b/FPGA_Quartus_13.1/Video/lpm_compare1.vhd new file mode 100644 index 0000000..a85e3b2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_compare1.vhd @@ -0,0 +1,127 @@ +-- megafunction wizard: %LPM_COMPARE% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_compare + +-- ============================================================ +-- File Name: lpm_compare1.vhd +-- Megafunction Name(s): +-- lpm_compare +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_compare1 IS + PORT + ( + dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + AgB : OUT STD_LOGIC + ); +END lpm_compare1; + + +ARCHITECTURE SYN OF lpm_compare1 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_compare + GENERIC ( + lpm_representation : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0); + AgB : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + AgB <= sub_wire0; + + lpm_compare_component : lpm_compare + GENERIC MAP ( + lpm_representation => "UNSIGNED", + lpm_type => "LPM_COMPARE", + lpm_width => 11 + ) + PORT MAP ( + dataa => dataa, + datab => datab, + AgB => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AeqB NUMERIC "0" +-- Retrieval info: PRIVATE: AgeB NUMERIC "0" +-- Retrieval info: PRIVATE: AgtB NUMERIC "1" +-- Retrieval info: PRIVATE: AleB NUMERIC "0" +-- Retrieval info: PRIVATE: AltB NUMERIC "0" +-- Retrieval info: PRIVATE: AneB NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +-- Retrieval info: PRIVATE: Latency NUMERIC "0" +-- Retrieval info: PRIVATE: PortBValue NUMERIC "0" +-- Retrieval info: PRIVATE: Radix NUMERIC "10" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: clken NUMERIC "0" +-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "11" +-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11" +-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB +-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL dataa[10..0] +-- Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL datab[10..0] +-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0 +-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0 +-- Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_waveforms.html TRUE +-- Retrieval info: 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Sample behavioral waveforms for design file lpm_compare1.vhd

+

The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator.

+
+

Fig. 1 : Wave showing comparator operation.

+

+

+ + diff --git a/FPGA_Quartus_13.1/Video/lpm_constant0.bsf b/FPGA_Quartus_13.1/Video/lpm_constant0.bsf new file mode 100644 index 0000000..684bbae --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant0.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "5" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_constant0.cmp b/FPGA_Quartus_13.1/Video/lpm_constant0.cmp new file mode 100644 index 0000000..7143429 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant0.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant0 + PORT + ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_constant0.qip b/FPGA_Quartus_13.1/Video/lpm_constant0.qip new file mode 100644 index 0000000..bb19c49 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_constant0.vhd b/FPGA_Quartus_13.1/Video/lpm_constant0.vhd new file mode 100644 index 0000000..63631cc --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant0.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant0.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant0 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_constant0; + + +ARCHITECTURE SYN OF lpm_constant0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(4 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 5 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0] +-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_constant1.bsf b/FPGA_Quartus_13.1/Video/lpm_constant1.bsf new file mode 100644 index 0000000..01fdb2b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant1.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "2" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_constant1.cmp b/FPGA_Quartus_13.1/Video/lpm_constant1.cmp new file mode 100644 index 0000000..a7e275c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant1.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant1 + PORT + ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_constant1.inc b/FPGA_Quartus_13.1/Video/lpm_constant1.inc new file mode 100644 index 0000000..9b556e7 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant1.inc @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_constant1 +( + +) + +RETURNS ( + result[1..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_constant1.qip b/FPGA_Quartus_13.1/Video/lpm_constant1.qip new file mode 100644 index 0000000..2bc12e7 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_constant1.vhd b/FPGA_Quartus_13.1/Video/lpm_constant1.vhd new file mode 100644 index 0000000..afa67ba --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant1.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant1.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant1 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END lpm_constant1; + + +ARCHITECTURE SYN OF lpm_constant1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(1 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 2 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0] +-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_constant2.bsf b/FPGA_Quartus_13.1/Video/lpm_constant2.bsf new file mode 100644 index 0000000..a4b7697 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant2.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "8" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_constant2.cmp b/FPGA_Quartus_13.1/Video/lpm_constant2.cmp new file mode 100644 index 0000000..63cc406 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant2.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant2 + PORT + ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_constant2.qip b/FPGA_Quartus_13.1/Video/lpm_constant2.qip new file mode 100644 index 0000000..ad38485 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_constant2.vhd b/FPGA_Quartus_13.1/Video/lpm_constant2.vhd new file mode 100644 index 0000000..f25e68f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant2.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant2.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant2 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_constant2; + + +ARCHITECTURE SYN OF lpm_constant2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(7 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 8 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_constant3.bsf b/FPGA_Quartus_13.1/Video/lpm_constant3.bsf new file mode 100644 index 0000000..7616869 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant3.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "0" (rect 75 18 80 30)(font "Arial" )) + (text "7" (rect 87 25 92 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 82 28)(pt 90 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_constant3.cmp b/FPGA_Quartus_13.1/Video/lpm_constant3.cmp new file mode 100644 index 0000000..0e2f877 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant3.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant3 + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_constant3.qip b/FPGA_Quartus_13.1/Video/lpm_constant3.qip new file mode 100644 index 0000000..615a781 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_constant3.vhd b/FPGA_Quartus_13.1/Video/lpm_constant3.vhd new file mode 100644 index 0000000..5d47d8e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant3.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant3.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant3 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_constant3; + + +ARCHITECTURE SYN OF lpm_constant3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(6 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 0, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 7 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0] +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_constant4.bsf b/FPGA_Quartus_13.1/Video/lpm_constant4.bsf new file mode 100644 index 0000000..181c667 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant4.bsf @@ -0,0 +1,42 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 48) + (text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 32 25 44)(font "Arial" )) + (port + (pt 96 24) + (output) + (text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 80 24)(line_width 3)) + ) + (drawing + (text "2040" (rect 60 18 80 30)(font "Arial" )) + (text "11" (rect 85 25 95 37)(font "Arial" )) + (line (pt 16 16)(pt 80 16)(line_width 1)) + (line (pt 80 16)(pt 80 32)(line_width 1)) + (line (pt 80 32)(pt 16 32)(line_width 1)) + (line (pt 16 32)(pt 16 16)(line_width 1)) + (line (pt 80 28)(pt 88 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_constant4.cmp b/FPGA_Quartus_13.1/Video/lpm_constant4.cmp new file mode 100644 index 0000000..fd7f4cd --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant4.cmp @@ -0,0 +1,21 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_constant4 + PORT + ( + result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_constant4.inc b/FPGA_Quartus_13.1/Video/lpm_constant4.inc new file mode 100644 index 0000000..a913739 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant4.inc @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_constant4 +( + +) + +RETURNS ( + result[10..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_constant4.qip b/FPGA_Quartus_13.1/Video/lpm_constant4.qip new file mode 100644 index 0000000..44fa63f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant4.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_constant4.vhd b/FPGA_Quartus_13.1/Video/lpm_constant4.vhd new file mode 100644 index 0000000..e0fc73d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_constant4.vhd @@ -0,0 +1,108 @@ +-- megafunction wizard: %LPM_CONSTANT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_constant + +-- ============================================================ +-- File Name: lpm_constant4.vhd +-- Megafunction Name(s): +-- lpm_constant +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_constant4 IS + PORT + ( + result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); +END lpm_constant4; + + +ARCHITECTURE SYN OF lpm_constant4 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (10 DOWNTO 0); + + + + COMPONENT lpm_constant + GENERIC ( + lpm_cvalue : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + result <= sub_wire0(10 DOWNTO 0); + + lpm_constant_component : lpm_constant + GENERIC MAP ( + lpm_cvalue => 2040, + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "LPM_CONSTANT", + lpm_width => 11 + ) + PORT MAP ( + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: Radix NUMERIC "10" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: Value NUMERIC "2040" +-- Retrieval info: PRIVATE: nBit NUMERIC "11" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "2040" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11" +-- Retrieval info: USED_PORT: result 0 0 11 0 OUTPUT NODEFVAL result[10..0] +-- Retrieval info: CONNECT: result 0 0 11 0 @result 0 0 11 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff0.bsf b/FPGA_Quartus_13.1/Video/lpm_ff0.bsf new file mode 100644 index 0000000..6675606 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff0.bsf @@ -0,0 +1,63 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 96) + (text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 144 56) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 89 50 125 63)(font "Arial" (font_size 8))) + (line (pt 144 56)(pt 128 56)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 80)(line_width 1)) + (line (pt 128 80)(pt 16 80)(line_width 1)) + (line (pt 16 80)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff0.cmp b/FPGA_Quartus_13.1/Video/lpm_ff0.cmp new file mode 100644 index 0000000..0d8e769 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff0.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff0 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff0.qip b/FPGA_Quartus_13.1/Video/lpm_ff0.qip new file mode 100644 index 0000000..d33c680 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff0.vhd b/FPGA_Quartus_13.1/Video/lpm_ff0.vhd new file mode 100644 index 0000000..4c17d8f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff0.vhd @@ -0,0 +1,127 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff0.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff0 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_ff0; + + +ARCHITECTURE SYN OF lpm_ff0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enable : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 32 + ) + PORT MAP ( + enable => enable, + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff1.bsf b/FPGA_Quartus_13.1/Video/lpm_ff1.bsf new file mode 100644 index 0000000..947a023 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff1.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff1.cmp b/FPGA_Quartus_13.1/Video/lpm_ff1.cmp new file mode 100644 index 0000000..4b25f14 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff1 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff1.qip b/FPGA_Quartus_13.1/Video/lpm_ff1.qip new file mode 100644 index 0000000..94b30af --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff1.vhd b/FPGA_Quartus_13.1/Video/lpm_ff1.vhd new file mode 100644 index 0000000..da02a15 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff1.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff1.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff1 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_ff1; + + +ARCHITECTURE SYN OF lpm_ff1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 32 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff2.bsf b/FPGA_Quartus_13.1/Video/lpm_ff2.bsf new file mode 100644 index 0000000..b52c75b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff2.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff2.cmp b/FPGA_Quartus_13.1/Video/lpm_ff2.cmp new file mode 100644 index 0000000..6b5b979 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff2.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff2 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff2.qip b/FPGA_Quartus_13.1/Video/lpm_ff2.qip new file mode 100644 index 0000000..9c46273 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff2.vhd b/FPGA_Quartus_13.1/Video/lpm_ff2.vhd new file mode 100644 index 0000000..27b4c3a --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff2.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff2.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff2 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_ff2; + + +ARCHITECTURE SYN OF lpm_ff2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(127 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 128 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff3.bsf b/FPGA_Quartus_13.1/Video/lpm_ff3.bsf new file mode 100644 index 0000000..51248ea --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff3.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff3.cmp b/FPGA_Quartus_13.1/Video/lpm_ff3.cmp new file mode 100644 index 0000000..b3b5513 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff3.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff3 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff3.qip b/FPGA_Quartus_13.1/Video/lpm_ff3.qip new file mode 100644 index 0000000..98d1312 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff3.vhd b/FPGA_Quartus_13.1/Video/lpm_ff3.vhd new file mode 100644 index 0000000..a86b4ee --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff3.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff3.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff3 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_ff3; + + +ARCHITECTURE SYN OF lpm_ff3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (23 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(23 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 24 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0] +-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL q[23..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0 +-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff4.bsf b/FPGA_Quartus_13.1/Video/lpm_ff4.bsf new file mode 100644 index 0000000..be432cb --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff4.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff4.cmp b/FPGA_Quartus_13.1/Video/lpm_ff4.cmp new file mode 100644 index 0000000..f3a15e2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff4.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff4 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff4.inc b/FPGA_Quartus_13.1/Video/lpm_ff4.inc new file mode 100644 index 0000000..ea243d6 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff4.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_ff4 +( + clock, + data[15..0] +) + +RETURNS ( + q[15..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_ff4.qip b/FPGA_Quartus_13.1/Video/lpm_ff4.qip new file mode 100644 index 0000000..f5a0a35 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff4.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff4.vhd b/FPGA_Quartus_13.1/Video/lpm_ff4.vhd new file mode 100644 index 0000000..a738a64 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff4.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff4.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff4 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_ff4; + + +ARCHITECTURE SYN OF lpm_ff4 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(15 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 16 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff5.bsf b/FPGA_Quartus_13.1/Video/lpm_ff5.bsf new file mode 100644 index 0000000..a69af6e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff5.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff5.cmp b/FPGA_Quartus_13.1/Video/lpm_ff5.cmp new file mode 100644 index 0000000..6ad77c9 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff5.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff5 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff5.inc b/FPGA_Quartus_13.1/Video/lpm_ff5.inc new file mode 100644 index 0000000..f65f941 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff5.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_ff5 +( + clock, + data[7..0] +) + +RETURNS ( + q[7..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_ff5.qip b/FPGA_Quartus_13.1/Video/lpm_ff5.qip new file mode 100644 index 0000000..0d13267 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff5.vhd b/FPGA_Quartus_13.1/Video/lpm_ff5.vhd new file mode 100644 index 0000000..96063a2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff5.vhd @@ -0,0 +1,122 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff5.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff5 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_ff5; + + +ARCHITECTURE SYN OF lpm_ff5 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 8 + ) + PORT MAP ( + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_ff6.bsf b/FPGA_Quartus_13.1/Video/lpm_ff6.bsf new file mode 100644 index 0000000..73a2df0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff6.bsf @@ -0,0 +1,63 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 96) + (text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 144 56) + (output) + (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 83 50 125 63)(font "Arial" (font_size 8))) + (line (pt 144 56)(pt 128 56)(line_width 3)) + ) + (drawing + (text "DFF" (rect 109 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 80)(line_width 1)) + (line (pt 128 80)(pt 16 80)(line_width 1)) + (line (pt 16 80)(pt 16 16)(line_width 1)) + (line (pt 16 42)(pt 22 48)(line_width 1)) + (line (pt 22 48)(pt 16 54)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_ff6.cmp b/FPGA_Quartus_13.1/Video/lpm_ff6.cmp new file mode 100644 index 0000000..50df3ad --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff6.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_ff6 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_ff6.inc b/FPGA_Quartus_13.1/Video/lpm_ff6.inc new file mode 100644 index 0000000..c8a5a36 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff6.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_ff6 +( + clock, + data[127..0], + enable +) + +RETURNS ( + q[127..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_ff6.qip b/FPGA_Quartus_13.1/Video/lpm_ff6.qip new file mode 100644 index 0000000..08e02f0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff6.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FF" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_ff6.vhd b/FPGA_Quartus_13.1/Video/lpm_ff6.vhd new file mode 100644 index 0000000..5cc384d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_ff6.vhd @@ -0,0 +1,127 @@ +-- megafunction wizard: %LPM_FF% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_ff + +-- ============================================================ +-- File Name: lpm_ff6.vhd +-- Megafunction Name(s): +-- lpm_ff +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_ff6 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + enable : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_ff6; + + +ARCHITECTURE SYN OF lpm_ff6 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT lpm_ff + GENERIC ( + lpm_fftype : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enable : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(127 DOWNTO 0); + + lpm_ff_component : lpm_ff + GENERIC MAP ( + lpm_fftype => "DFF", + lpm_type => "LPM_FF", + lpm_width => 128 + ) + PORT MAP ( + enable => enable, + clock => clock, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1" +-- Retrieval info: PRIVATE: DFF NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_fifoDZ.bsf b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.bsf new file mode 100644 index 0000000..1e24640 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.bsf @@ -0,0 +1,79 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 144) + (text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10))) + (text "inst" (rect 8 125 31 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (drawing + (text "(ack)" (rect 51 67 76 81)(font "Arial" )) + (text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 128)(line_width 1)) + (line (pt 144 128)(pt 16 128)(line_width 1)) + (line (pt 16 128)(pt 16 16)(line_width 1)) + (line (pt 16 108)(pt 144 108)(line_width 1)) + (line (pt 16 90)(pt 22 96)(line_width 1)) + (line (pt 22 96)(pt 16 102)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_fifoDZ.cmp b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.cmp new file mode 100644 index 0000000..153e7c2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_fifoDZ + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_fifoDZ.qip b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.qip new file mode 100644 index 0000000..5444627 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_fifoDZ.vhd b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.vhd new file mode 100644 index 0000000..95486bb --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifoDZ.vhd @@ -0,0 +1,178 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: scfifo + +-- ============================================================ +-- File Name: lpm_fifoDZ.vhd +-- Megafunction Name(s): +-- scfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY lpm_fifoDZ IS + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_fifoDZ; + + +ARCHITECTURE SYN OF lpm_fifodz IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT scfifo + GENERIC ( + add_ram_output_register : STRING; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + underflow_checking : STRING; + use_eab : STRING + ); + PORT ( + rdreq : IN STD_LOGIC ; + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(127 DOWNTO 0); + + scfifo_component : scfifo + GENERIC MAP ( + add_ram_output_register => "OFF", + intended_device_family => "Cyclone III", + lpm_numwords => 128, + lpm_showahead => "ON", + lpm_type => "scfifo", + lpm_width => 128, + lpm_widthu => 7, + overflow_checking => "OFF", + underflow_checking => "OFF", + use_eab => "ON" + ) + PORT MAP ( + rdreq => rdreq, + aclr => aclr, + clock => clock, + wrreq => wrreq, + data => data, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Depth NUMERIC "128" +-- Retrieval info: PRIVATE: Empty NUMERIC "0" +-- Retrieval info: PRIVATE: Full NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: Optimize NUMERIC "2" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: UsedW NUMERIC "0" +-- Retrieval info: PRIVATE: Width NUMERIC "128" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "128" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Video/lpm_fifoDZ_wave0.jpg b/FPGA_Quartus_13.1/Video/lpm_fifoDZ_wave0.jpg new file mode 100644 index 0000000000000000000000000000000000000000..63d8667e35986c03b7ebcb8480a483ab092ffa40 GIT binary patch literal 86257 zcmeFa2Ut_-x<48#N--k6W)$flN(YgQ1sFhr)KDZDLArAcyNWazW4jy@_TEzZ@CkY zgBGUdrjQ*wAdns4KL~deau)pUzxTC$lmFfwz`y3cf(Y(|tnIwAYsV4DPQe|!1b1+0 z5E!`5J%7J9$Dy@t)~>+HWsIOv3E$%C4Zpmxgn76cpz3oz*X$#I?S!Pk7!Y*$g`GvwNh%q{;(br zx|V1@P`p$E^|vzUpH94@^xy?i9P{!FQ!G}8C=L`dKKE0{WUB+roExip*9szT$QUb{ zydXzvQ8%K>AHVkYl*+3xo##{ju|EX3TC4h{u7BxR<)u&+yAnjGUzc#X?d`|*<+e64 zh9Pt@<*wj#o7;zlrhbkO{@Q8d*gZ2|i{-qBRRXUp!mG1BS_4Reqfmw@Bjnc>Tn-7O} z%Z|>WV1OMn+orFkn-7Zs(k85o1tPhC4 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y)%>aEo}GoW0SyZTGqu#@w$prn)1gamo!{PbIi?$A@>Q7a|G)m*bFli4iT?yQZa#(p literal 0 HcmV?d00001 diff --git a/FPGA_Quartus_13.1/Video/lpm_fifoDZ_waveforms.html b/FPGA_Quartus_13.1/Video/lpm_fifoDZ_waveforms.html new file mode 100644 index 0000000..467441f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifoDZ_waveforms.html @@ -0,0 +1,13 @@ + + +Sample Waveforms for "lpm_fifoDZ.vhd" + + +

Sample behavioral waveforms for design file "lpm_fifoDZ.vhd"

+

The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions with aclr .

+

+ + diff --git a/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.bsf b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.bsf new file mode 100644 index 0000000..61b485b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.bsf @@ -0,0 +1,102 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 168) + (text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 152 25 164)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 104) + (input) + (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) + (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 16 104)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) + (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 16 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) + (text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 144 72)(line_width 3)) + ) + (port + (pt 160 96) + (output) + (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) + (text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8))) + (line (pt 160 96)(pt 144 96)(line_width 3)) + ) + (port + (pt 160 120) + (output) + (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) + (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) + (line (pt 160 120)(pt 144 120)(line_width 1)) + ) + (drawing + (text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" )) + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 152)(line_width 1)) + (line (pt 144 152)(pt 16 152)(line_width 1)) + (line (pt 16 152)(pt 16 16)(line_width 1)) + (line (pt 16 84)(pt 144 84)(line_width 1)) + (line (pt 16 132)(pt 144 132)(line_width 1)) + (line (pt 16 66)(pt 22 72)(line_width 1)) + (line (pt 22 72)(pt 16 78)(line_width 1)) + (line (pt 16 114)(pt 22 120)(line_width 1)) + (line (pt 22 120)(pt 16 126)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.cmp b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.cmp new file mode 100644 index 0000000..08f6114 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_fifo_dc0 + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.inc b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.inc new file mode 100644 index 0000000..d29fb88 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.inc @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_fifo_dc0 +( + aclr, + data[127..0], + rdclk, + rdreq, + wrclk, + wrreq +) + +RETURNS ( + q[127..0], + rdempty, + wrusedw[8..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.qip b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.qip new file mode 100644 index 0000000..e883724 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.vhd b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.vhd new file mode 100644 index 0000000..8646d9c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_fifo_dc0.vhd @@ -0,0 +1,203 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo + +-- ============================================================ +-- File Name: lpm_fifo_dc0.vhd +-- Megafunction Name(s): +-- dcfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY lpm_fifo_dc0 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + rdempty : OUT STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0) + ); +END lpm_fifo_dc0; + + +ARCHITECTURE SYN OF lpm_fifo_dc0 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (127 DOWNTO 0); + + + + COMPONENT dcfifo + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdempty : OUT STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (127 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + rdempty <= sub_wire0; + wrusedw <= sub_wire1(8 DOWNTO 0); + q <= sub_wire2(127 DOWNTO 0); + + dcfifo_component : dcfifo + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 512, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 128, + lpm_widthu => 9, + overflow_checking => "OFF", + rdsync_delaypipe => 6, + underflow_checking => "OFF", + use_eab => "ON", + write_aclr_synch => "ON", + wrsync_delaypipe => 6 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + rdempty => sub_wire0, + wrusedw => sub_wire1, + q => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "512" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "128" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "128" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "6" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0] +-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0] +-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0 +-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL 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Sample behavioral waveforms for design file lpm_fifo_dc0.vhd

+

The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd. The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions with aclr .

+

+ + diff --git a/FPGA_Quartus_13.1/Video/lpm_latch1.bsf b/FPGA_Quartus_13.1/Video/lpm_latch1.bsf new file mode 100644 index 0000000..7197b2f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_latch1.bsf @@ -0,0 +1,53 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 80) + (text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) + (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (drawing + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 64)(line_width 1)) + (line (pt 144 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_latch1.cmp b/FPGA_Quartus_13.1/Video/lpm_latch1.cmp new file mode 100644 index 0000000..ac4b322 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_latch1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_latch1 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_latch1.qip b/FPGA_Quartus_13.1/Video/lpm_latch1.qip new file mode 100644 index 0000000..bc53d50 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_latch1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_LATCH" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_latch1.vhd b/FPGA_Quartus_13.1/Video/lpm_latch1.vhd new file mode 100644 index 0000000..0afc209 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_latch1.vhd @@ -0,0 +1,110 @@ +-- megafunction wizard: %LPM_LATCH% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_latch + +-- ============================================================ +-- File Name: lpm_latch1.vhd +-- Megafunction Name(s): +-- lpm_latch +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_latch1 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_latch1; + + +ARCHITECTURE SYN OF lpm_latch1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_latch + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_latch_component : lpm_latch + GENERIC MAP ( + lpm_type => "LPM_LATCH", + lpm_width => 32 + ) + PORT MAP ( + data => data, + gate => gate, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: aset NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux0.bsf b/FPGA_Quartus_13.1/Video/lpm_mux0.bsf new file mode 100644 index 0000000..ce1e27e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux0.bsf @@ -0,0 +1,83 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 128) + (text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 1)) + ) + (port + (pt 80 128) + (input) + (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8))) + (line (pt 80 128)(pt 80 116)(line_width 3)) + ) + (port + (pt 152 72) + (output) + (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8))) + (line (pt 152 72)(pt 88 72)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 120)(line_width 1)) + (line (pt 88 32)(pt 88 112)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 120)(pt 88 112)(line_width 1)) + (line (pt 72 98)(pt 78 104)(line_width 1)) + (line (pt 78 104)(pt 72 110)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux0.cmp b/FPGA_Quartus_13.1/Video/lpm_mux0.cmp new file mode 100644 index 0000000..7b6c18f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux0.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux0 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux0.inc b/FPGA_Quartus_13.1/Video/lpm_mux0.inc new file mode 100644 index 0000000..b0bc2be --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux0.inc @@ -0,0 +1,28 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux0 +( + clock, + data0x[31..0], + data1x[31..0], + data2x[31..0], + data3x[31..0], + sel[1..0] +) + +RETURNS ( + result[31..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_mux0.qip b/FPGA_Quartus_13.1/Video/lpm_mux0.qip new file mode 100644 index 0000000..5e8e2b6 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux0.vhd b/FPGA_Quartus_13.1/Video/lpm_mux0.vhd new file mode 100644 index 0000000..9d641a4 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux0.vhd @@ -0,0 +1,251 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux0.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux0 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_mux0; + + +ARCHITECTURE SYN OF lpm_mux0 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (31 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (31 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(31 DOWNTO 0); + sub_wire4 <= data1x(31 DOWNTO 0); + sub_wire3 <= data2x(31 DOWNTO 0); + result <= sub_wire0(31 DOWNTO 0); + sub_wire1 <= data3x(31 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(3, 7) <= sub_wire1(7); + sub_wire2(3, 8) <= sub_wire1(8); + sub_wire2(3, 9) <= sub_wire1(9); + sub_wire2(3, 10) <= sub_wire1(10); + sub_wire2(3, 11) <= sub_wire1(11); + sub_wire2(3, 12) <= sub_wire1(12); + sub_wire2(3, 13) <= sub_wire1(13); + sub_wire2(3, 14) <= sub_wire1(14); + sub_wire2(3, 15) <= sub_wire1(15); + sub_wire2(3, 16) <= sub_wire1(16); + sub_wire2(3, 17) <= sub_wire1(17); + sub_wire2(3, 18) <= sub_wire1(18); + sub_wire2(3, 19) <= sub_wire1(19); + sub_wire2(3, 20) <= sub_wire1(20); + sub_wire2(3, 21) <= sub_wire1(21); + sub_wire2(3, 22) <= sub_wire1(22); + sub_wire2(3, 23) <= sub_wire1(23); + sub_wire2(3, 24) <= sub_wire1(24); + sub_wire2(3, 25) <= sub_wire1(25); + sub_wire2(3, 26) <= sub_wire1(26); + sub_wire2(3, 27) <= sub_wire1(27); + sub_wire2(3, 28) <= sub_wire1(28); + sub_wire2(3, 29) <= sub_wire1(29); + sub_wire2(3, 30) <= sub_wire1(30); + sub_wire2(3, 31) <= sub_wire1(31); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(2, 7) <= sub_wire3(7); + sub_wire2(2, 8) <= sub_wire3(8); + sub_wire2(2, 9) <= sub_wire3(9); + sub_wire2(2, 10) <= sub_wire3(10); + sub_wire2(2, 11) <= sub_wire3(11); + sub_wire2(2, 12) <= sub_wire3(12); + sub_wire2(2, 13) <= sub_wire3(13); + sub_wire2(2, 14) <= sub_wire3(14); + sub_wire2(2, 15) <= sub_wire3(15); + sub_wire2(2, 16) <= sub_wire3(16); + sub_wire2(2, 17) <= sub_wire3(17); + sub_wire2(2, 18) <= sub_wire3(18); + sub_wire2(2, 19) <= sub_wire3(19); + sub_wire2(2, 20) <= sub_wire3(20); + sub_wire2(2, 21) <= sub_wire3(21); + sub_wire2(2, 22) <= sub_wire3(22); + sub_wire2(2, 23) <= sub_wire3(23); + sub_wire2(2, 24) <= sub_wire3(24); + sub_wire2(2, 25) <= sub_wire3(25); + sub_wire2(2, 26) <= sub_wire3(26); + sub_wire2(2, 27) <= sub_wire3(27); + sub_wire2(2, 28) <= sub_wire3(28); + sub_wire2(2, 29) <= sub_wire3(29); + sub_wire2(2, 30) <= sub_wire3(30); + sub_wire2(2, 31) <= sub_wire3(31); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(1, 7) <= sub_wire4(7); + sub_wire2(1, 8) <= sub_wire4(8); + sub_wire2(1, 9) <= sub_wire4(9); + sub_wire2(1, 10) <= sub_wire4(10); + sub_wire2(1, 11) <= sub_wire4(11); + sub_wire2(1, 12) <= sub_wire4(12); + sub_wire2(1, 13) <= sub_wire4(13); + sub_wire2(1, 14) <= sub_wire4(14); + sub_wire2(1, 15) <= sub_wire4(15); + sub_wire2(1, 16) <= sub_wire4(16); + sub_wire2(1, 17) <= sub_wire4(17); + sub_wire2(1, 18) <= sub_wire4(18); + sub_wire2(1, 19) <= sub_wire4(19); + sub_wire2(1, 20) <= sub_wire4(20); + sub_wire2(1, 21) <= sub_wire4(21); + sub_wire2(1, 22) <= sub_wire4(22); + sub_wire2(1, 23) <= sub_wire4(23); + sub_wire2(1, 24) <= sub_wire4(24); + sub_wire2(1, 25) <= sub_wire4(25); + sub_wire2(1, 26) <= sub_wire4(26); + sub_wire2(1, 27) <= sub_wire4(27); + sub_wire2(1, 28) <= sub_wire4(28); + sub_wire2(1, 29) <= sub_wire4(29); + sub_wire2(1, 30) <= sub_wire4(30); + sub_wire2(1, 31) <= sub_wire4(31); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + sub_wire2(0, 7) <= sub_wire5(7); + sub_wire2(0, 8) <= sub_wire5(8); + sub_wire2(0, 9) <= sub_wire5(9); + sub_wire2(0, 10) <= sub_wire5(10); + sub_wire2(0, 11) <= sub_wire5(11); + sub_wire2(0, 12) <= sub_wire5(12); + sub_wire2(0, 13) <= sub_wire5(13); + sub_wire2(0, 14) <= sub_wire5(14); + sub_wire2(0, 15) <= sub_wire5(15); + sub_wire2(0, 16) <= sub_wire5(16); + sub_wire2(0, 17) <= sub_wire5(17); + sub_wire2(0, 18) <= sub_wire5(18); + sub_wire2(0, 19) <= sub_wire5(19); + sub_wire2(0, 20) <= sub_wire5(20); + sub_wire2(0, 21) <= sub_wire5(21); + sub_wire2(0, 22) <= sub_wire5(22); + sub_wire2(0, 23) <= sub_wire5(23); + sub_wire2(0, 24) <= sub_wire5(24); + sub_wire2(0, 25) <= sub_wire5(25); + sub_wire2(0, 26) <= sub_wire5(26); + sub_wire2(0, 27) <= sub_wire5(27); + sub_wire2(0, 28) <= sub_wire5(28); + sub_wire2(0, 29) <= sub_wire5(29); + sub_wire2(0, 30) <= sub_wire5(30); + sub_wire2(0, 31) <= sub_wire5(31); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 4, + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 32, + lpm_widths => 2 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0] +-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0] +-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0] +-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0] +-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0] +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0 +-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux1.bsf b/FPGA_Quartus_13.1/Video/lpm_mux1.bsf new file mode 100644 index 0000000..24ee953 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux1.bsf @@ -0,0 +1,111 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 192) + (text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 176 25 188)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 1)) + ) + (port + (pt 80 192) + (input) + (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) + (line (pt 80 192)(pt 80 180)(line_width 3)) + ) + (port + (pt 152 104) + (output) + (text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) + (line (pt 152 104)(pt 88 104)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 184)(line_width 1)) + (line (pt 88 32)(pt 88 176)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 184)(pt 88 176)(line_width 1)) + (line (pt 72 162)(pt 78 168)(line_width 1)) + (line (pt 78 168)(pt 72 174)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux1.cmp b/FPGA_Quartus_13.1/Video/lpm_mux1.cmp new file mode 100644 index 0000000..cfc222a --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux1.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux1 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux1.inc b/FPGA_Quartus_13.1/Video/lpm_mux1.inc new file mode 100644 index 0000000..e2f94a4 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux1.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux1 +( + clock, + data0x[15..0], + data1x[15..0], + data2x[15..0], + data3x[15..0], + data4x[15..0], + data5x[15..0], + data6x[15..0], + data7x[15..0], + sel[2..0] +) + +RETURNS ( + result[15..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_mux1.qip b/FPGA_Quartus_13.1/Video/lpm_mux1.qip new file mode 100644 index 0000000..8a445b2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux1.vhd b/FPGA_Quartus_13.1/Video/lpm_mux1.vhd new file mode 100644 index 0000000..a9ad991 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux1.vhd @@ -0,0 +1,271 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux1.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux1 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_mux1; + + +ARCHITECTURE SYN OF lpm_mux1 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +BEGIN + sub_wire9 <= data0x(15 DOWNTO 0); + sub_wire8 <= data1x(15 DOWNTO 0); + sub_wire7 <= data2x(15 DOWNTO 0); + sub_wire6 <= data3x(15 DOWNTO 0); + sub_wire5 <= data4x(15 DOWNTO 0); + sub_wire4 <= data5x(15 DOWNTO 0); + sub_wire3 <= data6x(15 DOWNTO 0); + result <= sub_wire0(15 DOWNTO 0); + sub_wire1 <= data7x(15 DOWNTO 0); + sub_wire2(7, 0) <= sub_wire1(0); + sub_wire2(7, 1) <= sub_wire1(1); + sub_wire2(7, 2) <= sub_wire1(2); + sub_wire2(7, 3) <= sub_wire1(3); + sub_wire2(7, 4) <= sub_wire1(4); + sub_wire2(7, 5) <= sub_wire1(5); + sub_wire2(7, 6) <= sub_wire1(6); + sub_wire2(7, 7) <= sub_wire1(7); + sub_wire2(7, 8) <= sub_wire1(8); + sub_wire2(7, 9) <= sub_wire1(9); + sub_wire2(7, 10) <= sub_wire1(10); + sub_wire2(7, 11) <= sub_wire1(11); + sub_wire2(7, 12) <= sub_wire1(12); + sub_wire2(7, 13) <= sub_wire1(13); + sub_wire2(7, 14) <= sub_wire1(14); + sub_wire2(7, 15) <= sub_wire1(15); + sub_wire2(6, 0) <= sub_wire3(0); + sub_wire2(6, 1) <= sub_wire3(1); + sub_wire2(6, 2) <= sub_wire3(2); + sub_wire2(6, 3) <= sub_wire3(3); + sub_wire2(6, 4) <= sub_wire3(4); + sub_wire2(6, 5) <= sub_wire3(5); + sub_wire2(6, 6) <= sub_wire3(6); + sub_wire2(6, 7) <= sub_wire3(7); + sub_wire2(6, 8) <= sub_wire3(8); + sub_wire2(6, 9) <= sub_wire3(9); + sub_wire2(6, 10) <= sub_wire3(10); + sub_wire2(6, 11) <= sub_wire3(11); + sub_wire2(6, 12) <= sub_wire3(12); + sub_wire2(6, 13) <= sub_wire3(13); + sub_wire2(6, 14) <= sub_wire3(14); + sub_wire2(6, 15) <= sub_wire3(15); + sub_wire2(5, 0) <= sub_wire4(0); + sub_wire2(5, 1) <= sub_wire4(1); + sub_wire2(5, 2) <= sub_wire4(2); + sub_wire2(5, 3) <= sub_wire4(3); + sub_wire2(5, 4) <= sub_wire4(4); + sub_wire2(5, 5) <= sub_wire4(5); + sub_wire2(5, 6) <= sub_wire4(6); + sub_wire2(5, 7) <= sub_wire4(7); + sub_wire2(5, 8) <= sub_wire4(8); + sub_wire2(5, 9) <= sub_wire4(9); + sub_wire2(5, 10) <= sub_wire4(10); + sub_wire2(5, 11) <= sub_wire4(11); + sub_wire2(5, 12) <= sub_wire4(12); + sub_wire2(5, 13) <= sub_wire4(13); + sub_wire2(5, 14) <= sub_wire4(14); + sub_wire2(5, 15) <= sub_wire4(15); + sub_wire2(4, 0) <= sub_wire5(0); + sub_wire2(4, 1) <= sub_wire5(1); + sub_wire2(4, 2) <= sub_wire5(2); + sub_wire2(4, 3) <= sub_wire5(3); + sub_wire2(4, 4) <= sub_wire5(4); + sub_wire2(4, 5) <= sub_wire5(5); + sub_wire2(4, 6) <= sub_wire5(6); + sub_wire2(4, 7) <= sub_wire5(7); + sub_wire2(4, 8) <= sub_wire5(8); + sub_wire2(4, 9) <= sub_wire5(9); + sub_wire2(4, 10) <= sub_wire5(10); + sub_wire2(4, 11) <= sub_wire5(11); + sub_wire2(4, 12) <= sub_wire5(12); + sub_wire2(4, 13) <= sub_wire5(13); + sub_wire2(4, 14) <= sub_wire5(14); + sub_wire2(4, 15) <= sub_wire5(15); + sub_wire2(3, 0) <= sub_wire6(0); + sub_wire2(3, 1) <= sub_wire6(1); + sub_wire2(3, 2) <= sub_wire6(2); + sub_wire2(3, 3) <= sub_wire6(3); + sub_wire2(3, 4) <= sub_wire6(4); + sub_wire2(3, 5) <= sub_wire6(5); + sub_wire2(3, 6) <= sub_wire6(6); + sub_wire2(3, 7) <= sub_wire6(7); + sub_wire2(3, 8) <= sub_wire6(8); + sub_wire2(3, 9) <= sub_wire6(9); + sub_wire2(3, 10) <= sub_wire6(10); + sub_wire2(3, 11) <= sub_wire6(11); + sub_wire2(3, 12) <= sub_wire6(12); + sub_wire2(3, 13) <= sub_wire6(13); + sub_wire2(3, 14) <= sub_wire6(14); + sub_wire2(3, 15) <= sub_wire6(15); + sub_wire2(2, 0) <= sub_wire7(0); + sub_wire2(2, 1) <= sub_wire7(1); + sub_wire2(2, 2) <= sub_wire7(2); + sub_wire2(2, 3) <= sub_wire7(3); + sub_wire2(2, 4) <= sub_wire7(4); + sub_wire2(2, 5) <= sub_wire7(5); + sub_wire2(2, 6) <= sub_wire7(6); + sub_wire2(2, 7) <= sub_wire7(7); + sub_wire2(2, 8) <= sub_wire7(8); + sub_wire2(2, 9) <= sub_wire7(9); + sub_wire2(2, 10) <= sub_wire7(10); + sub_wire2(2, 11) <= sub_wire7(11); + sub_wire2(2, 12) <= sub_wire7(12); + sub_wire2(2, 13) <= sub_wire7(13); + sub_wire2(2, 14) <= sub_wire7(14); + sub_wire2(2, 15) <= sub_wire7(15); + sub_wire2(1, 0) <= sub_wire8(0); + sub_wire2(1, 1) <= sub_wire8(1); + sub_wire2(1, 2) <= sub_wire8(2); + sub_wire2(1, 3) <= sub_wire8(3); + sub_wire2(1, 4) <= sub_wire8(4); + sub_wire2(1, 5) <= sub_wire8(5); + sub_wire2(1, 6) <= sub_wire8(6); + sub_wire2(1, 7) <= sub_wire8(7); + sub_wire2(1, 8) <= sub_wire8(8); + sub_wire2(1, 9) <= sub_wire8(9); + sub_wire2(1, 10) <= sub_wire8(10); + sub_wire2(1, 11) <= sub_wire8(11); + sub_wire2(1, 12) <= sub_wire8(12); + sub_wire2(1, 13) <= sub_wire8(13); + sub_wire2(1, 14) <= sub_wire8(14); + sub_wire2(1, 15) <= sub_wire8(15); + sub_wire2(0, 0) <= sub_wire9(0); + sub_wire2(0, 1) <= sub_wire9(1); + sub_wire2(0, 2) <= sub_wire9(2); + sub_wire2(0, 3) <= sub_wire9(3); + sub_wire2(0, 4) <= sub_wire9(4); + sub_wire2(0, 5) <= sub_wire9(5); + sub_wire2(0, 6) <= sub_wire9(6); + sub_wire2(0, 7) <= sub_wire9(7); + sub_wire2(0, 8) <= sub_wire9(8); + sub_wire2(0, 9) <= sub_wire9(9); + sub_wire2(0, 10) <= sub_wire9(10); + sub_wire2(0, 11) <= sub_wire9(11); + sub_wire2(0, 12) <= sub_wire9(12); + sub_wire2(0, 13) <= sub_wire9(13); + sub_wire2(0, 14) <= sub_wire9(14); + sub_wire2(0, 15) <= sub_wire9(15); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 4, + lpm_size => 8, + lpm_type => "LPM_MUX", + lpm_width => 16, + lpm_widths => 3 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0] +-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0] +-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0] +-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0] +-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0] +-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0] +-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0] +-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0] +-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0] +-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0 +-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0 +-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux2.bsf b/FPGA_Quartus_13.1/Video/lpm_mux2.bsf new file mode 100644 index 0000000..b37c425 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux2.bsf @@ -0,0 +1,167 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 320) + (text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 304 25 316)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 3)) + ) + (port + (pt 0 184) + (input) + (text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 72 184)(line_width 3)) + ) + (port + (pt 0 200) + (input) + (text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 72 200)(line_width 3)) + ) + (port + (pt 0 216) + (input) + (text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 72 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 72 232)(line_width 3)) + ) + (port + (pt 0 248) + (input) + (text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 72 248)(line_width 3)) + ) + (port + (pt 0 264) + (input) + (text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 72 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 72 280)(line_width 3)) + ) + (port + (pt 0 296) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 72 296)(line_width 1)) + ) + (port + (pt 80 320) + (input) + (text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8))) + (line (pt 80 320)(pt 80 308)(line_width 3)) + ) + (port + (pt 144 168) + (output) + (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8))) + (line (pt 144 168)(pt 88 168)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 312)(line_width 1)) + (line (pt 88 32)(pt 88 304)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 312)(pt 88 304)(line_width 1)) + (line (pt 72 290)(pt 78 296)(line_width 1)) + (line (pt 78 296)(pt 72 302)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux2.cmp b/FPGA_Quartus_13.1/Video/lpm_mux2.cmp new file mode 100644 index 0000000..d94260c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux2.cmp @@ -0,0 +1,39 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux2 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux2.inc b/FPGA_Quartus_13.1/Video/lpm_mux2.inc new file mode 100644 index 0000000..2334c7e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux2.inc @@ -0,0 +1,40 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux2 +( + clock, + data0x[7..0], + data10x[7..0], + data11x[7..0], + data12x[7..0], + data13x[7..0], + data14x[7..0], + data15x[7..0], + data1x[7..0], + data2x[7..0], + data3x[7..0], + data4x[7..0], + data5x[7..0], + data6x[7..0], + data7x[7..0], + data8x[7..0], + data9x[7..0], + sel[3..0] +) + +RETURNS ( + result[7..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_mux2.qip b/FPGA_Quartus_13.1/Video/lpm_mux2.qip new file mode 100644 index 0000000..7b5db74 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux2.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux2.vhd b/FPGA_Quartus_13.1/Video/lpm_mux2.vhd new file mode 100644 index 0000000..cfece2e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux2.vhd @@ -0,0 +1,311 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux2.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux2 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_mux2; + + +ARCHITECTURE SYN OF lpm_mux2 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (7 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + sub_wire17 <= data0x(7 DOWNTO 0); + sub_wire16 <= data1x(7 DOWNTO 0); + sub_wire15 <= data2x(7 DOWNTO 0); + sub_wire14 <= data3x(7 DOWNTO 0); + sub_wire13 <= data4x(7 DOWNTO 0); + sub_wire12 <= data5x(7 DOWNTO 0); + sub_wire11 <= data6x(7 DOWNTO 0); + sub_wire10 <= data7x(7 DOWNTO 0); + sub_wire9 <= data8x(7 DOWNTO 0); + sub_wire8 <= data9x(7 DOWNTO 0); + sub_wire7 <= data10x(7 DOWNTO 0); + sub_wire6 <= data11x(7 DOWNTO 0); + sub_wire5 <= data12x(7 DOWNTO 0); + sub_wire4 <= data13x(7 DOWNTO 0); + sub_wire3 <= data14x(7 DOWNTO 0); + result <= sub_wire0(7 DOWNTO 0); + sub_wire1 <= data15x(7 DOWNTO 0); + sub_wire2(15, 0) <= sub_wire1(0); + sub_wire2(15, 1) <= sub_wire1(1); + sub_wire2(15, 2) <= sub_wire1(2); + sub_wire2(15, 3) <= sub_wire1(3); + sub_wire2(15, 4) <= sub_wire1(4); + sub_wire2(15, 5) <= sub_wire1(5); + sub_wire2(15, 6) <= sub_wire1(6); + sub_wire2(15, 7) <= sub_wire1(7); + sub_wire2(14, 0) <= sub_wire3(0); + sub_wire2(14, 1) <= sub_wire3(1); + sub_wire2(14, 2) <= sub_wire3(2); + sub_wire2(14, 3) <= sub_wire3(3); + sub_wire2(14, 4) <= sub_wire3(4); + sub_wire2(14, 5) <= sub_wire3(5); + sub_wire2(14, 6) <= sub_wire3(6); + sub_wire2(14, 7) <= sub_wire3(7); + sub_wire2(13, 0) <= sub_wire4(0); + sub_wire2(13, 1) <= sub_wire4(1); + sub_wire2(13, 2) <= sub_wire4(2); + sub_wire2(13, 3) <= sub_wire4(3); + sub_wire2(13, 4) <= sub_wire4(4); + sub_wire2(13, 5) <= sub_wire4(5); + sub_wire2(13, 6) <= sub_wire4(6); + sub_wire2(13, 7) <= sub_wire4(7); + sub_wire2(12, 0) <= sub_wire5(0); + sub_wire2(12, 1) <= sub_wire5(1); + sub_wire2(12, 2) <= sub_wire5(2); + sub_wire2(12, 3) <= sub_wire5(3); + sub_wire2(12, 4) <= sub_wire5(4); + sub_wire2(12, 5) <= sub_wire5(5); + sub_wire2(12, 6) <= sub_wire5(6); + sub_wire2(12, 7) <= sub_wire5(7); + sub_wire2(11, 0) <= sub_wire6(0); + sub_wire2(11, 1) <= sub_wire6(1); + sub_wire2(11, 2) <= sub_wire6(2); + sub_wire2(11, 3) <= sub_wire6(3); + sub_wire2(11, 4) <= sub_wire6(4); + sub_wire2(11, 5) <= sub_wire6(5); + sub_wire2(11, 6) <= sub_wire6(6); + sub_wire2(11, 7) <= sub_wire6(7); + sub_wire2(10, 0) <= sub_wire7(0); + sub_wire2(10, 1) <= sub_wire7(1); + sub_wire2(10, 2) <= sub_wire7(2); + sub_wire2(10, 3) <= sub_wire7(3); + sub_wire2(10, 4) <= sub_wire7(4); + sub_wire2(10, 5) <= sub_wire7(5); + sub_wire2(10, 6) <= sub_wire7(6); + sub_wire2(10, 7) <= sub_wire7(7); + sub_wire2(9, 0) <= sub_wire8(0); + sub_wire2(9, 1) <= sub_wire8(1); + sub_wire2(9, 2) <= sub_wire8(2); + sub_wire2(9, 3) <= sub_wire8(3); + sub_wire2(9, 4) <= sub_wire8(4); + sub_wire2(9, 5) <= sub_wire8(5); + sub_wire2(9, 6) <= sub_wire8(6); + sub_wire2(9, 7) <= sub_wire8(7); + sub_wire2(8, 0) <= sub_wire9(0); + sub_wire2(8, 1) <= sub_wire9(1); + sub_wire2(8, 2) <= sub_wire9(2); + sub_wire2(8, 3) <= sub_wire9(3); + sub_wire2(8, 4) <= sub_wire9(4); + sub_wire2(8, 5) <= sub_wire9(5); + sub_wire2(8, 6) <= sub_wire9(6); + sub_wire2(8, 7) <= sub_wire9(7); + sub_wire2(7, 0) <= sub_wire10(0); + sub_wire2(7, 1) <= sub_wire10(1); + sub_wire2(7, 2) <= sub_wire10(2); + sub_wire2(7, 3) <= sub_wire10(3); + sub_wire2(7, 4) <= sub_wire10(4); + sub_wire2(7, 5) <= sub_wire10(5); + sub_wire2(7, 6) <= sub_wire10(6); + sub_wire2(7, 7) <= sub_wire10(7); + sub_wire2(6, 0) <= sub_wire11(0); + sub_wire2(6, 1) <= sub_wire11(1); + sub_wire2(6, 2) <= sub_wire11(2); + sub_wire2(6, 3) <= sub_wire11(3); + sub_wire2(6, 4) <= sub_wire11(4); + sub_wire2(6, 5) <= sub_wire11(5); + sub_wire2(6, 6) <= sub_wire11(6); + sub_wire2(6, 7) <= sub_wire11(7); + sub_wire2(5, 0) <= sub_wire12(0); + sub_wire2(5, 1) <= sub_wire12(1); + sub_wire2(5, 2) <= sub_wire12(2); + sub_wire2(5, 3) <= sub_wire12(3); + sub_wire2(5, 4) <= sub_wire12(4); + sub_wire2(5, 5) <= sub_wire12(5); + sub_wire2(5, 6) <= sub_wire12(6); + sub_wire2(5, 7) <= sub_wire12(7); + sub_wire2(4, 0) <= sub_wire13(0); + sub_wire2(4, 1) <= sub_wire13(1); + sub_wire2(4, 2) <= sub_wire13(2); + sub_wire2(4, 3) <= sub_wire13(3); + sub_wire2(4, 4) <= sub_wire13(4); + sub_wire2(4, 5) <= sub_wire13(5); + sub_wire2(4, 6) <= sub_wire13(6); + sub_wire2(4, 7) <= sub_wire13(7); + sub_wire2(3, 0) <= sub_wire14(0); + sub_wire2(3, 1) <= sub_wire14(1); + sub_wire2(3, 2) <= sub_wire14(2); + sub_wire2(3, 3) <= sub_wire14(3); + sub_wire2(3, 4) <= sub_wire14(4); + sub_wire2(3, 5) <= sub_wire14(5); + sub_wire2(3, 6) <= sub_wire14(6); + sub_wire2(3, 7) <= sub_wire14(7); + sub_wire2(2, 0) <= sub_wire15(0); + sub_wire2(2, 1) <= sub_wire15(1); + sub_wire2(2, 2) <= sub_wire15(2); + sub_wire2(2, 3) <= sub_wire15(3); + sub_wire2(2, 4) <= sub_wire15(4); + sub_wire2(2, 5) <= sub_wire15(5); + sub_wire2(2, 6) <= sub_wire15(6); + sub_wire2(2, 7) <= sub_wire15(7); + sub_wire2(1, 0) <= sub_wire16(0); + sub_wire2(1, 1) <= sub_wire16(1); + sub_wire2(1, 2) <= sub_wire16(2); + sub_wire2(1, 3) <= sub_wire16(3); + sub_wire2(1, 4) <= sub_wire16(4); + sub_wire2(1, 5) <= sub_wire16(5); + sub_wire2(1, 6) <= sub_wire16(6); + sub_wire2(1, 7) <= sub_wire16(7); + sub_wire2(0, 0) <= sub_wire17(0); + sub_wire2(0, 1) <= sub_wire17(1); + sub_wire2(0, 2) <= sub_wire17(2); + sub_wire2(0, 3) <= sub_wire17(3); + sub_wire2(0, 4) <= sub_wire17(4); + sub_wire2(0, 5) <= sub_wire17(5); + sub_wire2(0, 6) <= sub_wire17(6); + sub_wire2(0, 7) <= sub_wire17(7); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 2, + lpm_size => 16, + lpm_type => "LPM_MUX", + lpm_width => 8, + lpm_widths => 4 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0] +-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0] +-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0] +-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0] +-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0] +-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0] +-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0] +-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0] +-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0] +-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0] +-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0] +-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0] +-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0] +-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0] +-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0] +-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0] +-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0] +-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0 +-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0 +-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux3.bsf b/FPGA_Quartus_13.1/Video/lpm_mux3.bsf new file mode 100644 index 0000000..c389543 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux3.bsf @@ -0,0 +1,60 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 80 80) + (text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 32 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 32 56)(line_width 1)) + ) + (port + (pt 40 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8))) + (line (pt 40 80)(pt 40 68)(line_width 1)) + ) + (port + (pt 80 48) + (output) + (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "result" (rect 50 35 75 48)(font "Arial" (font_size 8))) + (line (pt 80 48)(pt 48 48)(line_width 1)) + ) + (drawing + (line (pt 32 24)(pt 32 72)(line_width 1)) + (line (pt 48 32)(pt 48 64)(line_width 1)) + (line (pt 32 24)(pt 48 32)(line_width 1)) + (line (pt 32 72)(pt 48 64)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux3.cmp b/FPGA_Quartus_13.1/Video/lpm_mux3.cmp new file mode 100644 index 0000000..48f730d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux3.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux3 + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux3.qip b/FPGA_Quartus_13.1/Video/lpm_mux3.qip new file mode 100644 index 0000000..ca1e672 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux3.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux3.vhd b/FPGA_Quartus_13.1/Video/lpm_mux3.vhd new file mode 100644 index 0000000..b975686 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux3.vhd @@ -0,0 +1,115 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux3.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux3 IS + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +END lpm_mux3; + + +ARCHITECTURE SYN OF lpm_mux3 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + +BEGIN + sub_wire6 <= data0; + sub_wire1 <= sub_wire0(0); + result <= sub_wire1; + sub_wire2 <= sel; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= data1; + sub_wire5(1, 0) <= sub_wire4; + sub_wire5(0, 0) <= sub_wire6; + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 1, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire3, + data => sub_wire5, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0 +-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1 +-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 +-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 +-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux4.bsf b/FPGA_Quartus_13.1/Video/lpm_mux4.bsf new file mode 100644 index 0000000..a1c9ca0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux4.bsf @@ -0,0 +1,60 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 136 80) + (text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 72 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8))) + (line (pt 72 80)(pt 72 68)(line_width 1)) + ) + (port + (pt 136 48) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8))) + (line (pt 136 48)(pt 80 48)(line_width 3)) + ) + (drawing + (line (pt 64 24)(pt 64 72)(line_width 1)) + (line (pt 80 32)(pt 80 64)(line_width 1)) + (line (pt 64 24)(pt 80 32)(line_width 1)) + (line (pt 64 72)(pt 80 64)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux4.cmp b/FPGA_Quartus_13.1/Video/lpm_mux4.cmp new file mode 100644 index 0000000..05e7a07 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux4.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux4 + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux4.qip b/FPGA_Quartus_13.1/Video/lpm_mux4.qip new file mode 100644 index 0000000..7712e39 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux4.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux4.vhd b/FPGA_Quartus_13.1/Video/lpm_mux4.vhd new file mode 100644 index 0000000..854a491 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux4.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux4.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux4 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_mux4; + + +ARCHITECTURE SYN OF lpm_mux4 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (6 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(6 DOWNTO 0); + result <= sub_wire0(6 DOWNTO 0); + sub_wire1 <= sel; + sub_wire2(0) <= sub_wire1; + sub_wire3 <= data1x(6 DOWNTO 0); + sub_wire4(1, 0) <= sub_wire3(0); + sub_wire4(1, 1) <= sub_wire3(1); + sub_wire4(1, 2) <= sub_wire3(2); + sub_wire4(1, 3) <= sub_wire3(3); + sub_wire4(1, 4) <= sub_wire3(4); + sub_wire4(1, 5) <= sub_wire3(5); + sub_wire4(1, 6) <= sub_wire3(6); + sub_wire4(0, 0) <= sub_wire5(0); + sub_wire4(0, 1) <= sub_wire5(1); + sub_wire4(0, 2) <= sub_wire5(2); + sub_wire4(0, 3) <= sub_wire5(3); + sub_wire4(0, 4) <= sub_wire5(4); + sub_wire4(0, 5) <= sub_wire5(5); + sub_wire4(0, 6) <= sub_wire5(6); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 7, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire2, + data => sub_wire4, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0] +-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0] +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0] +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux5.bsf b/FPGA_Quartus_13.1/Video/lpm_mux5.bsf new file mode 100644 index 0000000..e63ce50 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux5.bsf @@ -0,0 +1,74 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 112) + (text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 80 112) + (input) + (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8))) + (line (pt 80 112)(pt 80 100)(line_width 3)) + ) + (port + (pt 152 64) + (output) + (text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8))) + (line (pt 152 64)(pt 88 64)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 104)(line_width 1)) + (line (pt 88 32)(pt 88 96)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 104)(pt 88 96)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux5.cmp b/FPGA_Quartus_13.1/Video/lpm_mux5.cmp new file mode 100644 index 0000000..efc712a --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux5.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux5 + PORT + ( + data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux5.inc b/FPGA_Quartus_13.1/Video/lpm_mux5.inc new file mode 100644 index 0000000..a063f55 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux5.inc @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux5 +( + data0x[63..0], + data1x[63..0], + data2x[63..0], + data3x[63..0], + sel[1..0] +) + +RETURNS ( + result[63..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_mux5.qip b/FPGA_Quartus_13.1/Video/lpm_mux5.qip new file mode 100644 index 0000000..08b2e74 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux5.vhd b/FPGA_Quartus_13.1/Video/lpm_mux5.vhd new file mode 100644 index 0000000..1d35347 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux5.vhd @@ -0,0 +1,373 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux5.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux5 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0) + ); +END lpm_mux5; + + +ARCHITECTURE SYN OF lpm_mux5 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (63 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (63 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(63 DOWNTO 0); + sub_wire4 <= data1x(63 DOWNTO 0); + sub_wire3 <= data2x(63 DOWNTO 0); + result <= sub_wire0(63 DOWNTO 0); + sub_wire1 <= data3x(63 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(3, 7) <= sub_wire1(7); + sub_wire2(3, 8) <= sub_wire1(8); + sub_wire2(3, 9) <= sub_wire1(9); + sub_wire2(3, 10) <= sub_wire1(10); + sub_wire2(3, 11) <= sub_wire1(11); + sub_wire2(3, 12) <= sub_wire1(12); + sub_wire2(3, 13) <= sub_wire1(13); + sub_wire2(3, 14) <= sub_wire1(14); + sub_wire2(3, 15) <= sub_wire1(15); + sub_wire2(3, 16) <= sub_wire1(16); + sub_wire2(3, 17) <= sub_wire1(17); + sub_wire2(3, 18) <= sub_wire1(18); + sub_wire2(3, 19) <= sub_wire1(19); + sub_wire2(3, 20) <= sub_wire1(20); + sub_wire2(3, 21) <= sub_wire1(21); + sub_wire2(3, 22) <= sub_wire1(22); + sub_wire2(3, 23) <= sub_wire1(23); + sub_wire2(3, 24) <= sub_wire1(24); + sub_wire2(3, 25) <= sub_wire1(25); + sub_wire2(3, 26) <= sub_wire1(26); + sub_wire2(3, 27) <= sub_wire1(27); + sub_wire2(3, 28) <= sub_wire1(28); + sub_wire2(3, 29) <= sub_wire1(29); + sub_wire2(3, 30) <= sub_wire1(30); + sub_wire2(3, 31) <= sub_wire1(31); + sub_wire2(3, 32) <= sub_wire1(32); + sub_wire2(3, 33) <= sub_wire1(33); + sub_wire2(3, 34) <= sub_wire1(34); + sub_wire2(3, 35) <= sub_wire1(35); + sub_wire2(3, 36) <= sub_wire1(36); + sub_wire2(3, 37) <= sub_wire1(37); + sub_wire2(3, 38) <= sub_wire1(38); + sub_wire2(3, 39) <= sub_wire1(39); + sub_wire2(3, 40) <= sub_wire1(40); + sub_wire2(3, 41) <= sub_wire1(41); + sub_wire2(3, 42) <= sub_wire1(42); + sub_wire2(3, 43) <= sub_wire1(43); + sub_wire2(3, 44) <= sub_wire1(44); + sub_wire2(3, 45) <= sub_wire1(45); + sub_wire2(3, 46) <= sub_wire1(46); + sub_wire2(3, 47) <= sub_wire1(47); + sub_wire2(3, 48) <= sub_wire1(48); + sub_wire2(3, 49) <= sub_wire1(49); + sub_wire2(3, 50) <= sub_wire1(50); + sub_wire2(3, 51) <= sub_wire1(51); + sub_wire2(3, 52) <= sub_wire1(52); + sub_wire2(3, 53) <= sub_wire1(53); + sub_wire2(3, 54) <= sub_wire1(54); + sub_wire2(3, 55) <= sub_wire1(55); + sub_wire2(3, 56) <= sub_wire1(56); + sub_wire2(3, 57) <= sub_wire1(57); + sub_wire2(3, 58) <= sub_wire1(58); + sub_wire2(3, 59) <= sub_wire1(59); + sub_wire2(3, 60) <= sub_wire1(60); + sub_wire2(3, 61) <= sub_wire1(61); + sub_wire2(3, 62) <= sub_wire1(62); + sub_wire2(3, 63) <= sub_wire1(63); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(2, 7) <= sub_wire3(7); + sub_wire2(2, 8) <= sub_wire3(8); + sub_wire2(2, 9) <= sub_wire3(9); + sub_wire2(2, 10) <= sub_wire3(10); + sub_wire2(2, 11) <= sub_wire3(11); + sub_wire2(2, 12) <= sub_wire3(12); + sub_wire2(2, 13) <= sub_wire3(13); + sub_wire2(2, 14) <= sub_wire3(14); + sub_wire2(2, 15) <= sub_wire3(15); + sub_wire2(2, 16) <= sub_wire3(16); + sub_wire2(2, 17) <= sub_wire3(17); + sub_wire2(2, 18) <= sub_wire3(18); + sub_wire2(2, 19) <= sub_wire3(19); + sub_wire2(2, 20) <= sub_wire3(20); + sub_wire2(2, 21) <= sub_wire3(21); + sub_wire2(2, 22) <= sub_wire3(22); + sub_wire2(2, 23) <= sub_wire3(23); + sub_wire2(2, 24) <= sub_wire3(24); + sub_wire2(2, 25) <= sub_wire3(25); + sub_wire2(2, 26) <= sub_wire3(26); + sub_wire2(2, 27) <= sub_wire3(27); + sub_wire2(2, 28) <= sub_wire3(28); + sub_wire2(2, 29) <= sub_wire3(29); + sub_wire2(2, 30) <= sub_wire3(30); + sub_wire2(2, 31) <= sub_wire3(31); + sub_wire2(2, 32) <= sub_wire3(32); + sub_wire2(2, 33) <= sub_wire3(33); + sub_wire2(2, 34) <= sub_wire3(34); + sub_wire2(2, 35) <= sub_wire3(35); + sub_wire2(2, 36) <= sub_wire3(36); + sub_wire2(2, 37) <= sub_wire3(37); + sub_wire2(2, 38) <= sub_wire3(38); + sub_wire2(2, 39) <= sub_wire3(39); + sub_wire2(2, 40) <= sub_wire3(40); + sub_wire2(2, 41) <= sub_wire3(41); + sub_wire2(2, 42) <= sub_wire3(42); + sub_wire2(2, 43) <= sub_wire3(43); + sub_wire2(2, 44) <= sub_wire3(44); + sub_wire2(2, 45) <= sub_wire3(45); + sub_wire2(2, 46) <= sub_wire3(46); + sub_wire2(2, 47) <= sub_wire3(47); + sub_wire2(2, 48) <= sub_wire3(48); + sub_wire2(2, 49) <= sub_wire3(49); + sub_wire2(2, 50) <= sub_wire3(50); + sub_wire2(2, 51) <= sub_wire3(51); + sub_wire2(2, 52) <= sub_wire3(52); + sub_wire2(2, 53) <= sub_wire3(53); + sub_wire2(2, 54) <= sub_wire3(54); + sub_wire2(2, 55) <= sub_wire3(55); + sub_wire2(2, 56) <= sub_wire3(56); + sub_wire2(2, 57) <= sub_wire3(57); + sub_wire2(2, 58) <= sub_wire3(58); + sub_wire2(2, 59) <= sub_wire3(59); + sub_wire2(2, 60) <= sub_wire3(60); + sub_wire2(2, 61) <= sub_wire3(61); + sub_wire2(2, 62) <= sub_wire3(62); + sub_wire2(2, 63) <= sub_wire3(63); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(1, 7) <= sub_wire4(7); + sub_wire2(1, 8) <= sub_wire4(8); + sub_wire2(1, 9) <= sub_wire4(9); + sub_wire2(1, 10) <= sub_wire4(10); + sub_wire2(1, 11) <= sub_wire4(11); + sub_wire2(1, 12) <= sub_wire4(12); + sub_wire2(1, 13) <= sub_wire4(13); + sub_wire2(1, 14) <= sub_wire4(14); + sub_wire2(1, 15) <= sub_wire4(15); + sub_wire2(1, 16) <= sub_wire4(16); + sub_wire2(1, 17) <= sub_wire4(17); + sub_wire2(1, 18) <= sub_wire4(18); + sub_wire2(1, 19) <= sub_wire4(19); + sub_wire2(1, 20) <= sub_wire4(20); + sub_wire2(1, 21) <= sub_wire4(21); + sub_wire2(1, 22) <= sub_wire4(22); + sub_wire2(1, 23) <= sub_wire4(23); + sub_wire2(1, 24) <= sub_wire4(24); + sub_wire2(1, 25) <= sub_wire4(25); + sub_wire2(1, 26) <= sub_wire4(26); + sub_wire2(1, 27) <= sub_wire4(27); + sub_wire2(1, 28) <= sub_wire4(28); + sub_wire2(1, 29) <= sub_wire4(29); + sub_wire2(1, 30) <= sub_wire4(30); + sub_wire2(1, 31) <= sub_wire4(31); + sub_wire2(1, 32) <= sub_wire4(32); + sub_wire2(1, 33) <= sub_wire4(33); + sub_wire2(1, 34) <= sub_wire4(34); + sub_wire2(1, 35) <= sub_wire4(35); + sub_wire2(1, 36) <= sub_wire4(36); + sub_wire2(1, 37) <= sub_wire4(37); + sub_wire2(1, 38) <= sub_wire4(38); + sub_wire2(1, 39) <= sub_wire4(39); + sub_wire2(1, 40) <= sub_wire4(40); + sub_wire2(1, 41) <= sub_wire4(41); + sub_wire2(1, 42) <= sub_wire4(42); + sub_wire2(1, 43) <= sub_wire4(43); + sub_wire2(1, 44) <= sub_wire4(44); + sub_wire2(1, 45) <= sub_wire4(45); + sub_wire2(1, 46) <= sub_wire4(46); + sub_wire2(1, 47) <= sub_wire4(47); + sub_wire2(1, 48) <= sub_wire4(48); + sub_wire2(1, 49) <= sub_wire4(49); + sub_wire2(1, 50) <= sub_wire4(50); + sub_wire2(1, 51) <= sub_wire4(51); + sub_wire2(1, 52) <= sub_wire4(52); + sub_wire2(1, 53) <= sub_wire4(53); + sub_wire2(1, 54) <= sub_wire4(54); + sub_wire2(1, 55) <= sub_wire4(55); + sub_wire2(1, 56) <= sub_wire4(56); + sub_wire2(1, 57) <= sub_wire4(57); + sub_wire2(1, 58) <= sub_wire4(58); + sub_wire2(1, 59) <= sub_wire4(59); + sub_wire2(1, 60) <= sub_wire4(60); + sub_wire2(1, 61) <= sub_wire4(61); + sub_wire2(1, 62) <= sub_wire4(62); + sub_wire2(1, 63) <= sub_wire4(63); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + sub_wire2(0, 7) <= sub_wire5(7); + sub_wire2(0, 8) <= sub_wire5(8); + sub_wire2(0, 9) <= sub_wire5(9); + sub_wire2(0, 10) <= sub_wire5(10); + sub_wire2(0, 11) <= sub_wire5(11); + sub_wire2(0, 12) <= sub_wire5(12); + sub_wire2(0, 13) <= sub_wire5(13); + sub_wire2(0, 14) <= sub_wire5(14); + sub_wire2(0, 15) <= sub_wire5(15); + sub_wire2(0, 16) <= sub_wire5(16); + sub_wire2(0, 17) <= sub_wire5(17); + sub_wire2(0, 18) <= sub_wire5(18); + sub_wire2(0, 19) <= sub_wire5(19); + sub_wire2(0, 20) <= sub_wire5(20); + sub_wire2(0, 21) <= sub_wire5(21); + sub_wire2(0, 22) <= sub_wire5(22); + sub_wire2(0, 23) <= sub_wire5(23); + sub_wire2(0, 24) <= sub_wire5(24); + sub_wire2(0, 25) <= sub_wire5(25); + sub_wire2(0, 26) <= sub_wire5(26); + sub_wire2(0, 27) <= sub_wire5(27); + sub_wire2(0, 28) <= sub_wire5(28); + sub_wire2(0, 29) <= sub_wire5(29); + sub_wire2(0, 30) <= sub_wire5(30); + sub_wire2(0, 31) <= sub_wire5(31); + sub_wire2(0, 32) <= sub_wire5(32); + sub_wire2(0, 33) <= sub_wire5(33); + sub_wire2(0, 34) <= sub_wire5(34); + sub_wire2(0, 35) <= sub_wire5(35); + sub_wire2(0, 36) <= sub_wire5(36); + sub_wire2(0, 37) <= sub_wire5(37); + sub_wire2(0, 38) <= sub_wire5(38); + sub_wire2(0, 39) <= sub_wire5(39); + sub_wire2(0, 40) <= sub_wire5(40); + sub_wire2(0, 41) <= sub_wire5(41); + sub_wire2(0, 42) <= sub_wire5(42); + sub_wire2(0, 43) <= sub_wire5(43); + sub_wire2(0, 44) <= sub_wire5(44); + sub_wire2(0, 45) <= sub_wire5(45); + sub_wire2(0, 46) <= sub_wire5(46); + sub_wire2(0, 47) <= sub_wire5(47); + sub_wire2(0, 48) <= sub_wire5(48); + sub_wire2(0, 49) <= sub_wire5(49); + sub_wire2(0, 50) <= sub_wire5(50); + sub_wire2(0, 51) <= sub_wire5(51); + sub_wire2(0, 52) <= sub_wire5(52); + sub_wire2(0, 53) <= sub_wire5(53); + sub_wire2(0, 54) <= sub_wire5(54); + sub_wire2(0, 55) <= sub_wire5(55); + sub_wire2(0, 56) <= sub_wire5(56); + sub_wire2(0, 57) <= sub_wire5(57); + sub_wire2(0, 58) <= sub_wire5(58); + sub_wire2(0, 59) <= sub_wire5(59); + sub_wire2(0, 60) <= sub_wire5(60); + sub_wire2(0, 61) <= sub_wire5(61); + sub_wire2(0, 62) <= sub_wire5(62); + sub_wire2(0, 63) <= sub_wire5(63); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 64, + lpm_widths => 2 + ) + PORT MAP ( + sel => sel, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0] +-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0] +-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0] +-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0] +-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0] +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0] +-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0 +-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_mux6.bsf b/FPGA_Quartus_13.1/Video/lpm_mux6.bsf new file mode 100644 index 0000000..2196842 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux6.bsf @@ -0,0 +1,111 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 152 192) + (text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 176 25 188)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 72 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 72 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 72 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 72 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 72 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 72 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 72 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 72 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 72 168)(line_width 1)) + ) + (port + (pt 80 192) + (input) + (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) + (line (pt 80 192)(pt 80 180)(line_width 3)) + ) + (port + (pt 152 104) + (output) + (text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) + (line (pt 152 104)(pt 88 104)(line_width 3)) + ) + (drawing + (line (pt 72 24)(pt 72 184)(line_width 1)) + (line (pt 88 32)(pt 88 176)(line_width 1)) + (line (pt 72 24)(pt 88 32)(line_width 1)) + (line (pt 72 184)(pt 88 176)(line_width 1)) + (line (pt 72 162)(pt 78 168)(line_width 1)) + (line (pt 78 168)(pt 72 174)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_mux6.cmp b/FPGA_Quartus_13.1/Video/lpm_mux6.cmp new file mode 100644 index 0000000..543da1f --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux6.cmp @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_mux6 + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_mux6.inc b/FPGA_Quartus_13.1/Video/lpm_mux6.inc new file mode 100644 index 0000000..3cf223d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux6.inc @@ -0,0 +1,32 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_mux6 +( + clock, + data0x[23..0], + data1x[23..0], + data2x[23..0], + data3x[23..0], + data4x[23..0], + data5x[23..0], + data6x[23..0], + data7x[23..0], + sel[2..0] +) + +RETURNS ( + result[23..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_mux6.qip b/FPGA_Quartus_13.1/Video/lpm_mux6.qip new file mode 100644 index 0000000..051a945 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux6.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_mux6.vhd b/FPGA_Quartus_13.1/Video/lpm_mux6.vhd new file mode 100644 index 0000000..42d5aae --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_mux6.vhd @@ -0,0 +1,335 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_mux6.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux6 IS + PORT + ( + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (23 DOWNTO 0) + ); +END lpm_mux6; + + +ARCHITECTURE SYN OF lpm_mux6 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (23 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (23 DOWNTO 0); + +BEGIN + sub_wire9 <= data0x(23 DOWNTO 0); + sub_wire8 <= data1x(23 DOWNTO 0); + sub_wire7 <= data2x(23 DOWNTO 0); + sub_wire6 <= data3x(23 DOWNTO 0); + sub_wire5 <= data4x(23 DOWNTO 0); + sub_wire4 <= data5x(23 DOWNTO 0); + sub_wire3 <= data6x(23 DOWNTO 0); + result <= sub_wire0(23 DOWNTO 0); + sub_wire1 <= data7x(23 DOWNTO 0); + sub_wire2(7, 0) <= sub_wire1(0); + sub_wire2(7, 1) <= sub_wire1(1); + sub_wire2(7, 2) <= sub_wire1(2); + sub_wire2(7, 3) <= sub_wire1(3); + sub_wire2(7, 4) <= sub_wire1(4); + sub_wire2(7, 5) <= sub_wire1(5); + sub_wire2(7, 6) <= sub_wire1(6); + sub_wire2(7, 7) <= sub_wire1(7); + sub_wire2(7, 8) <= sub_wire1(8); + sub_wire2(7, 9) <= sub_wire1(9); + sub_wire2(7, 10) <= sub_wire1(10); + sub_wire2(7, 11) <= sub_wire1(11); + sub_wire2(7, 12) <= sub_wire1(12); + sub_wire2(7, 13) <= sub_wire1(13); + sub_wire2(7, 14) <= sub_wire1(14); + sub_wire2(7, 15) <= sub_wire1(15); + sub_wire2(7, 16) <= sub_wire1(16); + sub_wire2(7, 17) <= sub_wire1(17); + sub_wire2(7, 18) <= sub_wire1(18); + sub_wire2(7, 19) <= sub_wire1(19); + sub_wire2(7, 20) <= sub_wire1(20); + sub_wire2(7, 21) <= sub_wire1(21); + sub_wire2(7, 22) <= sub_wire1(22); + sub_wire2(7, 23) <= sub_wire1(23); + sub_wire2(6, 0) <= sub_wire3(0); + sub_wire2(6, 1) <= sub_wire3(1); + sub_wire2(6, 2) <= sub_wire3(2); + sub_wire2(6, 3) <= sub_wire3(3); + sub_wire2(6, 4) <= sub_wire3(4); + sub_wire2(6, 5) <= sub_wire3(5); + sub_wire2(6, 6) <= sub_wire3(6); + sub_wire2(6, 7) <= sub_wire3(7); + sub_wire2(6, 8) <= sub_wire3(8); + sub_wire2(6, 9) <= sub_wire3(9); + sub_wire2(6, 10) <= sub_wire3(10); + sub_wire2(6, 11) <= sub_wire3(11); + sub_wire2(6, 12) <= sub_wire3(12); + sub_wire2(6, 13) <= sub_wire3(13); + sub_wire2(6, 14) <= sub_wire3(14); + sub_wire2(6, 15) <= sub_wire3(15); + sub_wire2(6, 16) <= sub_wire3(16); + sub_wire2(6, 17) <= sub_wire3(17); + sub_wire2(6, 18) <= sub_wire3(18); + sub_wire2(6, 19) <= sub_wire3(19); + sub_wire2(6, 20) <= sub_wire3(20); + sub_wire2(6, 21) <= sub_wire3(21); + sub_wire2(6, 22) <= sub_wire3(22); + sub_wire2(6, 23) <= sub_wire3(23); + sub_wire2(5, 0) <= sub_wire4(0); + sub_wire2(5, 1) <= sub_wire4(1); + sub_wire2(5, 2) <= sub_wire4(2); + sub_wire2(5, 3) <= sub_wire4(3); + sub_wire2(5, 4) <= sub_wire4(4); + sub_wire2(5, 5) <= sub_wire4(5); + sub_wire2(5, 6) <= sub_wire4(6); + sub_wire2(5, 7) <= sub_wire4(7); + sub_wire2(5, 8) <= sub_wire4(8); + sub_wire2(5, 9) <= sub_wire4(9); + sub_wire2(5, 10) <= sub_wire4(10); + sub_wire2(5, 11) <= sub_wire4(11); + sub_wire2(5, 12) <= sub_wire4(12); + sub_wire2(5, 13) <= sub_wire4(13); + sub_wire2(5, 14) <= sub_wire4(14); + sub_wire2(5, 15) <= sub_wire4(15); + sub_wire2(5, 16) <= sub_wire4(16); + sub_wire2(5, 17) <= sub_wire4(17); + sub_wire2(5, 18) <= sub_wire4(18); + sub_wire2(5, 19) <= sub_wire4(19); + sub_wire2(5, 20) <= sub_wire4(20); + sub_wire2(5, 21) <= sub_wire4(21); + sub_wire2(5, 22) <= sub_wire4(22); + sub_wire2(5, 23) <= sub_wire4(23); + sub_wire2(4, 0) <= sub_wire5(0); + sub_wire2(4, 1) <= sub_wire5(1); + sub_wire2(4, 2) <= sub_wire5(2); + sub_wire2(4, 3) <= sub_wire5(3); + sub_wire2(4, 4) <= sub_wire5(4); + sub_wire2(4, 5) <= sub_wire5(5); + sub_wire2(4, 6) <= sub_wire5(6); + sub_wire2(4, 7) <= sub_wire5(7); + sub_wire2(4, 8) <= sub_wire5(8); + sub_wire2(4, 9) <= sub_wire5(9); + sub_wire2(4, 10) <= sub_wire5(10); + sub_wire2(4, 11) <= sub_wire5(11); + sub_wire2(4, 12) <= sub_wire5(12); + sub_wire2(4, 13) <= sub_wire5(13); + sub_wire2(4, 14) <= sub_wire5(14); + sub_wire2(4, 15) <= sub_wire5(15); + sub_wire2(4, 16) <= sub_wire5(16); + sub_wire2(4, 17) <= sub_wire5(17); + sub_wire2(4, 18) <= sub_wire5(18); + sub_wire2(4, 19) <= sub_wire5(19); + sub_wire2(4, 20) <= sub_wire5(20); + sub_wire2(4, 21) <= sub_wire5(21); + sub_wire2(4, 22) <= sub_wire5(22); + sub_wire2(4, 23) <= sub_wire5(23); + sub_wire2(3, 0) <= sub_wire6(0); + sub_wire2(3, 1) <= sub_wire6(1); + sub_wire2(3, 2) <= sub_wire6(2); + sub_wire2(3, 3) <= sub_wire6(3); + sub_wire2(3, 4) <= sub_wire6(4); + sub_wire2(3, 5) <= sub_wire6(5); + sub_wire2(3, 6) <= sub_wire6(6); + sub_wire2(3, 7) <= sub_wire6(7); + sub_wire2(3, 8) <= sub_wire6(8); + sub_wire2(3, 9) <= sub_wire6(9); + sub_wire2(3, 10) <= sub_wire6(10); + sub_wire2(3, 11) <= sub_wire6(11); + sub_wire2(3, 12) <= sub_wire6(12); + sub_wire2(3, 13) <= sub_wire6(13); + sub_wire2(3, 14) <= sub_wire6(14); + sub_wire2(3, 15) <= sub_wire6(15); + sub_wire2(3, 16) <= sub_wire6(16); + sub_wire2(3, 17) <= sub_wire6(17); + sub_wire2(3, 18) <= sub_wire6(18); + sub_wire2(3, 19) <= sub_wire6(19); + sub_wire2(3, 20) <= sub_wire6(20); + sub_wire2(3, 21) <= sub_wire6(21); + sub_wire2(3, 22) <= sub_wire6(22); + sub_wire2(3, 23) <= sub_wire6(23); + sub_wire2(2, 0) <= sub_wire7(0); + sub_wire2(2, 1) <= sub_wire7(1); + sub_wire2(2, 2) <= sub_wire7(2); + sub_wire2(2, 3) <= sub_wire7(3); + sub_wire2(2, 4) <= sub_wire7(4); + sub_wire2(2, 5) <= sub_wire7(5); + sub_wire2(2, 6) <= sub_wire7(6); + sub_wire2(2, 7) <= sub_wire7(7); + sub_wire2(2, 8) <= sub_wire7(8); + sub_wire2(2, 9) <= sub_wire7(9); + sub_wire2(2, 10) <= sub_wire7(10); + sub_wire2(2, 11) <= sub_wire7(11); + sub_wire2(2, 12) <= sub_wire7(12); + sub_wire2(2, 13) <= sub_wire7(13); + sub_wire2(2, 14) <= sub_wire7(14); + sub_wire2(2, 15) <= sub_wire7(15); + sub_wire2(2, 16) <= sub_wire7(16); + sub_wire2(2, 17) <= sub_wire7(17); + sub_wire2(2, 18) <= sub_wire7(18); + sub_wire2(2, 19) <= sub_wire7(19); + sub_wire2(2, 20) <= sub_wire7(20); + sub_wire2(2, 21) <= sub_wire7(21); + sub_wire2(2, 22) <= sub_wire7(22); + sub_wire2(2, 23) <= sub_wire7(23); + sub_wire2(1, 0) <= sub_wire8(0); + sub_wire2(1, 1) <= sub_wire8(1); + sub_wire2(1, 2) <= sub_wire8(2); + sub_wire2(1, 3) <= sub_wire8(3); + sub_wire2(1, 4) <= sub_wire8(4); + sub_wire2(1, 5) <= sub_wire8(5); + sub_wire2(1, 6) <= sub_wire8(6); + sub_wire2(1, 7) <= sub_wire8(7); + sub_wire2(1, 8) <= sub_wire8(8); + sub_wire2(1, 9) <= sub_wire8(9); + sub_wire2(1, 10) <= sub_wire8(10); + sub_wire2(1, 11) <= sub_wire8(11); + sub_wire2(1, 12) <= sub_wire8(12); + sub_wire2(1, 13) <= sub_wire8(13); + sub_wire2(1, 14) <= sub_wire8(14); + sub_wire2(1, 15) <= sub_wire8(15); + sub_wire2(1, 16) <= sub_wire8(16); + sub_wire2(1, 17) <= sub_wire8(17); + sub_wire2(1, 18) <= sub_wire8(18); + sub_wire2(1, 19) <= sub_wire8(19); + sub_wire2(1, 20) <= sub_wire8(20); + sub_wire2(1, 21) <= sub_wire8(21); + sub_wire2(1, 22) <= sub_wire8(22); + sub_wire2(1, 23) <= sub_wire8(23); + sub_wire2(0, 0) <= sub_wire9(0); + sub_wire2(0, 1) <= sub_wire9(1); + sub_wire2(0, 2) <= sub_wire9(2); + sub_wire2(0, 3) <= sub_wire9(3); + sub_wire2(0, 4) <= sub_wire9(4); + sub_wire2(0, 5) <= sub_wire9(5); + sub_wire2(0, 6) <= sub_wire9(6); + sub_wire2(0, 7) <= sub_wire9(7); + sub_wire2(0, 8) <= sub_wire9(8); + sub_wire2(0, 9) <= sub_wire9(9); + sub_wire2(0, 10) <= sub_wire9(10); + sub_wire2(0, 11) <= sub_wire9(11); + sub_wire2(0, 12) <= sub_wire9(12); + sub_wire2(0, 13) <= sub_wire9(13); + sub_wire2(0, 14) <= sub_wire9(14); + sub_wire2(0, 15) <= sub_wire9(15); + sub_wire2(0, 16) <= sub_wire9(16); + sub_wire2(0, 17) <= sub_wire9(17); + sub_wire2(0, 18) <= sub_wire9(18); + sub_wire2(0, 19) <= sub_wire9(19); + sub_wire2(0, 20) <= sub_wire9(20); + sub_wire2(0, 21) <= sub_wire9(21); + sub_wire2(0, 22) <= sub_wire9(22); + sub_wire2(0, 23) <= sub_wire9(23); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 2, + lpm_size => 8, + lpm_type => "LPM_MUX", + lpm_width => 24, + lpm_widths => 3 + ) + PORT MAP ( + sel => sel, + clock => clock, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0] +-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0] +-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0] +-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0] +-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0] +-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0] +-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0] +-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0] +-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0] +-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0 +-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0 +-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.bsf b/FPGA_Quartus_13.1/Video/lpm_muxDZ.bsf new file mode 100644 index 0000000..f4f1c7d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ.bsf @@ -0,0 +1,76 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 112) + (text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 80 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 80 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 80 72)(line_width 1)) + ) + (port + (pt 0 88) + (input) + (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 80 88)(line_width 1)) + ) + (port + (pt 88 112) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8))) + (line (pt 88 112)(pt 88 100)(line_width 1)) + ) + (port + (pt 168 64) + (output) + (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8))) + (line (pt 168 64)(pt 96 64)(line_width 3)) + ) + (drawing + (line (pt 80 24)(pt 80 104)(line_width 1)) + (line (pt 96 32)(pt 96 96)(line_width 1)) + (line (pt 80 24)(pt 96 32)(line_width 1)) + (line (pt 80 104)(pt 96 96)(line_width 1)) + (line (pt 80 66)(pt 86 72)(line_width 1)) + (line (pt 86 72)(pt 80 78)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.cmp b/FPGA_Quartus_13.1/Video/lpm_muxDZ.cmp new file mode 100644 index 0000000..f177216 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxDZ + PORT + ( + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.qip b/FPGA_Quartus_13.1/Video/lpm_muxDZ.qip new file mode 100644 index 0000000..34ffc75 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.vhd b/FPGA_Quartus_13.1/Video/lpm_muxDZ.vhd new file mode 100644 index 0000000..e9bd32e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ.vhd @@ -0,0 +1,377 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxDZ.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxDZ IS + PORT + ( + clken : IN STD_LOGIC := '1'; + clock : IN STD_LOGIC ; + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_muxDZ; + + +ARCHITECTURE SYN OF lpm_muxdz IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(127 DOWNTO 0); + result <= sub_wire0(127 DOWNTO 0); + sub_wire1 <= sel; + sub_wire2(0) <= sub_wire1; + sub_wire3 <= data1x(127 DOWNTO 0); + sub_wire4(1, 0) <= sub_wire3(0); + sub_wire4(1, 1) <= sub_wire3(1); + sub_wire4(1, 2) <= sub_wire3(2); + sub_wire4(1, 3) <= sub_wire3(3); + sub_wire4(1, 4) <= sub_wire3(4); + sub_wire4(1, 5) <= sub_wire3(5); + sub_wire4(1, 6) <= sub_wire3(6); + sub_wire4(1, 7) <= sub_wire3(7); + sub_wire4(1, 8) <= sub_wire3(8); + sub_wire4(1, 9) <= sub_wire3(9); + sub_wire4(1, 10) <= sub_wire3(10); + sub_wire4(1, 11) <= sub_wire3(11); + sub_wire4(1, 12) <= sub_wire3(12); + sub_wire4(1, 13) <= sub_wire3(13); + sub_wire4(1, 14) <= sub_wire3(14); + sub_wire4(1, 15) <= sub_wire3(15); + sub_wire4(1, 16) <= sub_wire3(16); + sub_wire4(1, 17) <= sub_wire3(17); + sub_wire4(1, 18) <= sub_wire3(18); + sub_wire4(1, 19) <= sub_wire3(19); + sub_wire4(1, 20) <= sub_wire3(20); + sub_wire4(1, 21) <= sub_wire3(21); + sub_wire4(1, 22) <= sub_wire3(22); + sub_wire4(1, 23) <= sub_wire3(23); + sub_wire4(1, 24) <= sub_wire3(24); + sub_wire4(1, 25) <= sub_wire3(25); + sub_wire4(1, 26) <= sub_wire3(26); + sub_wire4(1, 27) <= sub_wire3(27); + sub_wire4(1, 28) <= sub_wire3(28); + sub_wire4(1, 29) <= sub_wire3(29); + sub_wire4(1, 30) <= sub_wire3(30); + sub_wire4(1, 31) <= sub_wire3(31); + sub_wire4(1, 32) <= sub_wire3(32); + sub_wire4(1, 33) <= sub_wire3(33); + sub_wire4(1, 34) <= sub_wire3(34); + sub_wire4(1, 35) <= sub_wire3(35); + sub_wire4(1, 36) <= sub_wire3(36); + sub_wire4(1, 37) <= sub_wire3(37); + sub_wire4(1, 38) <= sub_wire3(38); + sub_wire4(1, 39) <= sub_wire3(39); + sub_wire4(1, 40) <= sub_wire3(40); + sub_wire4(1, 41) <= sub_wire3(41); + sub_wire4(1, 42) <= sub_wire3(42); + sub_wire4(1, 43) <= sub_wire3(43); + sub_wire4(1, 44) <= sub_wire3(44); + sub_wire4(1, 45) <= sub_wire3(45); + sub_wire4(1, 46) <= sub_wire3(46); + sub_wire4(1, 47) <= sub_wire3(47); + sub_wire4(1, 48) <= sub_wire3(48); + sub_wire4(1, 49) <= sub_wire3(49); + sub_wire4(1, 50) <= sub_wire3(50); + sub_wire4(1, 51) <= sub_wire3(51); + sub_wire4(1, 52) <= sub_wire3(52); + sub_wire4(1, 53) <= sub_wire3(53); + sub_wire4(1, 54) <= sub_wire3(54); + sub_wire4(1, 55) <= sub_wire3(55); + sub_wire4(1, 56) <= sub_wire3(56); + sub_wire4(1, 57) <= sub_wire3(57); + sub_wire4(1, 58) <= sub_wire3(58); + sub_wire4(1, 59) <= sub_wire3(59); + sub_wire4(1, 60) <= sub_wire3(60); + sub_wire4(1, 61) <= sub_wire3(61); + sub_wire4(1, 62) <= sub_wire3(62); + sub_wire4(1, 63) <= sub_wire3(63); + sub_wire4(1, 64) <= sub_wire3(64); + sub_wire4(1, 65) <= sub_wire3(65); + sub_wire4(1, 66) <= sub_wire3(66); + sub_wire4(1, 67) <= sub_wire3(67); + sub_wire4(1, 68) <= sub_wire3(68); + sub_wire4(1, 69) <= sub_wire3(69); + sub_wire4(1, 70) <= sub_wire3(70); + sub_wire4(1, 71) <= sub_wire3(71); + sub_wire4(1, 72) <= sub_wire3(72); + sub_wire4(1, 73) <= sub_wire3(73); + sub_wire4(1, 74) <= sub_wire3(74); + sub_wire4(1, 75) <= sub_wire3(75); + sub_wire4(1, 76) <= sub_wire3(76); + sub_wire4(1, 77) <= sub_wire3(77); + sub_wire4(1, 78) <= sub_wire3(78); + sub_wire4(1, 79) <= sub_wire3(79); + sub_wire4(1, 80) <= sub_wire3(80); + sub_wire4(1, 81) <= sub_wire3(81); + sub_wire4(1, 82) <= sub_wire3(82); + sub_wire4(1, 83) <= sub_wire3(83); + sub_wire4(1, 84) <= sub_wire3(84); + sub_wire4(1, 85) <= sub_wire3(85); + sub_wire4(1, 86) <= sub_wire3(86); + sub_wire4(1, 87) <= sub_wire3(87); + sub_wire4(1, 88) <= sub_wire3(88); + sub_wire4(1, 89) <= sub_wire3(89); + sub_wire4(1, 90) <= sub_wire3(90); + sub_wire4(1, 91) <= sub_wire3(91); + sub_wire4(1, 92) <= sub_wire3(92); + sub_wire4(1, 93) <= sub_wire3(93); + sub_wire4(1, 94) <= sub_wire3(94); + sub_wire4(1, 95) <= sub_wire3(95); + sub_wire4(1, 96) <= sub_wire3(96); + sub_wire4(1, 97) <= sub_wire3(97); + sub_wire4(1, 98) <= sub_wire3(98); + sub_wire4(1, 99) <= sub_wire3(99); + sub_wire4(1, 100) <= sub_wire3(100); + sub_wire4(1, 101) <= sub_wire3(101); + sub_wire4(1, 102) <= sub_wire3(102); + sub_wire4(1, 103) <= sub_wire3(103); + sub_wire4(1, 104) <= sub_wire3(104); + sub_wire4(1, 105) <= sub_wire3(105); + sub_wire4(1, 106) <= sub_wire3(106); + sub_wire4(1, 107) <= sub_wire3(107); + sub_wire4(1, 108) <= sub_wire3(108); + sub_wire4(1, 109) <= sub_wire3(109); + sub_wire4(1, 110) <= sub_wire3(110); + sub_wire4(1, 111) <= sub_wire3(111); + sub_wire4(1, 112) <= sub_wire3(112); + sub_wire4(1, 113) <= sub_wire3(113); + sub_wire4(1, 114) <= sub_wire3(114); + sub_wire4(1, 115) <= sub_wire3(115); + sub_wire4(1, 116) <= sub_wire3(116); + sub_wire4(1, 117) <= sub_wire3(117); + sub_wire4(1, 118) <= sub_wire3(118); + sub_wire4(1, 119) <= sub_wire3(119); + sub_wire4(1, 120) <= sub_wire3(120); + sub_wire4(1, 121) <= sub_wire3(121); + sub_wire4(1, 122) <= sub_wire3(122); + sub_wire4(1, 123) <= sub_wire3(123); + sub_wire4(1, 124) <= sub_wire3(124); + sub_wire4(1, 125) <= sub_wire3(125); + sub_wire4(1, 126) <= sub_wire3(126); + sub_wire4(1, 127) <= sub_wire3(127); + sub_wire4(0, 0) <= sub_wire5(0); + sub_wire4(0, 1) <= sub_wire5(1); + sub_wire4(0, 2) <= sub_wire5(2); + sub_wire4(0, 3) <= sub_wire5(3); + sub_wire4(0, 4) <= sub_wire5(4); + sub_wire4(0, 5) <= sub_wire5(5); + sub_wire4(0, 6) <= sub_wire5(6); + sub_wire4(0, 7) <= sub_wire5(7); + sub_wire4(0, 8) <= sub_wire5(8); + sub_wire4(0, 9) <= sub_wire5(9); + sub_wire4(0, 10) <= sub_wire5(10); + sub_wire4(0, 11) <= sub_wire5(11); + sub_wire4(0, 12) <= sub_wire5(12); + sub_wire4(0, 13) <= sub_wire5(13); + sub_wire4(0, 14) <= sub_wire5(14); + sub_wire4(0, 15) <= sub_wire5(15); + sub_wire4(0, 16) <= sub_wire5(16); + sub_wire4(0, 17) <= sub_wire5(17); + sub_wire4(0, 18) <= sub_wire5(18); + sub_wire4(0, 19) <= sub_wire5(19); + sub_wire4(0, 20) <= sub_wire5(20); + sub_wire4(0, 21) <= sub_wire5(21); + sub_wire4(0, 22) <= sub_wire5(22); + sub_wire4(0, 23) <= sub_wire5(23); + sub_wire4(0, 24) <= sub_wire5(24); + sub_wire4(0, 25) <= sub_wire5(25); + sub_wire4(0, 26) <= sub_wire5(26); + sub_wire4(0, 27) <= sub_wire5(27); + sub_wire4(0, 28) <= sub_wire5(28); + sub_wire4(0, 29) <= sub_wire5(29); + sub_wire4(0, 30) <= sub_wire5(30); + sub_wire4(0, 31) <= sub_wire5(31); + sub_wire4(0, 32) <= sub_wire5(32); + sub_wire4(0, 33) <= sub_wire5(33); + sub_wire4(0, 34) <= sub_wire5(34); + sub_wire4(0, 35) <= sub_wire5(35); + sub_wire4(0, 36) <= sub_wire5(36); + sub_wire4(0, 37) <= sub_wire5(37); + sub_wire4(0, 38) <= sub_wire5(38); + sub_wire4(0, 39) <= sub_wire5(39); + sub_wire4(0, 40) <= sub_wire5(40); + sub_wire4(0, 41) <= sub_wire5(41); + sub_wire4(0, 42) <= sub_wire5(42); + sub_wire4(0, 43) <= sub_wire5(43); + sub_wire4(0, 44) <= sub_wire5(44); + sub_wire4(0, 45) <= sub_wire5(45); + sub_wire4(0, 46) <= sub_wire5(46); + sub_wire4(0, 47) <= sub_wire5(47); + sub_wire4(0, 48) <= sub_wire5(48); + sub_wire4(0, 49) <= sub_wire5(49); + sub_wire4(0, 50) <= sub_wire5(50); + sub_wire4(0, 51) <= sub_wire5(51); + sub_wire4(0, 52) <= sub_wire5(52); + sub_wire4(0, 53) <= sub_wire5(53); + sub_wire4(0, 54) <= sub_wire5(54); + sub_wire4(0, 55) <= sub_wire5(55); + sub_wire4(0, 56) <= sub_wire5(56); + sub_wire4(0, 57) <= sub_wire5(57); + sub_wire4(0, 58) <= sub_wire5(58); + sub_wire4(0, 59) <= sub_wire5(59); + sub_wire4(0, 60) <= sub_wire5(60); + sub_wire4(0, 61) <= sub_wire5(61); + sub_wire4(0, 62) <= sub_wire5(62); + sub_wire4(0, 63) <= sub_wire5(63); + sub_wire4(0, 64) <= sub_wire5(64); + sub_wire4(0, 65) <= sub_wire5(65); + sub_wire4(0, 66) <= sub_wire5(66); + sub_wire4(0, 67) <= sub_wire5(67); + sub_wire4(0, 68) <= sub_wire5(68); + sub_wire4(0, 69) <= sub_wire5(69); + sub_wire4(0, 70) <= sub_wire5(70); + sub_wire4(0, 71) <= sub_wire5(71); + sub_wire4(0, 72) <= sub_wire5(72); + sub_wire4(0, 73) <= sub_wire5(73); + sub_wire4(0, 74) <= sub_wire5(74); + sub_wire4(0, 75) <= sub_wire5(75); + sub_wire4(0, 76) <= sub_wire5(76); + sub_wire4(0, 77) <= sub_wire5(77); + sub_wire4(0, 78) <= sub_wire5(78); + sub_wire4(0, 79) <= sub_wire5(79); + sub_wire4(0, 80) <= sub_wire5(80); + sub_wire4(0, 81) <= sub_wire5(81); + sub_wire4(0, 82) <= sub_wire5(82); + sub_wire4(0, 83) <= sub_wire5(83); + sub_wire4(0, 84) <= sub_wire5(84); + sub_wire4(0, 85) <= sub_wire5(85); + sub_wire4(0, 86) <= sub_wire5(86); + sub_wire4(0, 87) <= sub_wire5(87); + sub_wire4(0, 88) <= sub_wire5(88); + sub_wire4(0, 89) <= sub_wire5(89); + sub_wire4(0, 90) <= sub_wire5(90); + sub_wire4(0, 91) <= sub_wire5(91); + sub_wire4(0, 92) <= sub_wire5(92); + sub_wire4(0, 93) <= sub_wire5(93); + sub_wire4(0, 94) <= sub_wire5(94); + sub_wire4(0, 95) <= sub_wire5(95); + sub_wire4(0, 96) <= sub_wire5(96); + sub_wire4(0, 97) <= sub_wire5(97); + sub_wire4(0, 98) <= sub_wire5(98); + sub_wire4(0, 99) <= sub_wire5(99); + sub_wire4(0, 100) <= sub_wire5(100); + sub_wire4(0, 101) <= sub_wire5(101); + sub_wire4(0, 102) <= sub_wire5(102); + sub_wire4(0, 103) <= sub_wire5(103); + sub_wire4(0, 104) <= sub_wire5(104); + sub_wire4(0, 105) <= sub_wire5(105); + sub_wire4(0, 106) <= sub_wire5(106); + sub_wire4(0, 107) <= sub_wire5(107); + sub_wire4(0, 108) <= sub_wire5(108); + sub_wire4(0, 109) <= sub_wire5(109); + sub_wire4(0, 110) <= sub_wire5(110); + sub_wire4(0, 111) <= sub_wire5(111); + sub_wire4(0, 112) <= sub_wire5(112); + sub_wire4(0, 113) <= sub_wire5(113); + sub_wire4(0, 114) <= sub_wire5(114); + sub_wire4(0, 115) <= sub_wire5(115); + sub_wire4(0, 116) <= sub_wire5(116); + sub_wire4(0, 117) <= sub_wire5(117); + sub_wire4(0, 118) <= sub_wire5(118); + sub_wire4(0, 119) <= sub_wire5(119); + sub_wire4(0, 120) <= sub_wire5(120); + sub_wire4(0, 121) <= sub_wire5(121); + sub_wire4(0, 122) <= sub_wire5(122); + sub_wire4(0, 123) <= sub_wire5(123); + sub_wire4(0, 124) <= sub_wire5(124); + sub_wire4(0, 125) <= sub_wire5(125); + sub_wire4(0, 126) <= sub_wire5(126); + sub_wire4(0, 127) <= sub_wire5(127); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_pipeline => 1, + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 128, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire2, + clken => clken, + clock => clock, + data => sub_wire4, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0] +-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0] +-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0] +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.bsf b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.bsf new file mode 100644 index 0000000..b7e3184 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.bsf @@ -0,0 +1,60 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 80) + (text "lpm_muxDZ2" (rect 10 2 99 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 40 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 40 56)(line_width 1)) + ) + (port + (pt 48 80) + (input) + (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "sel" (rect 52 67 65 80)(font "Arial" (font_size 8))) + (line (pt 48 80)(pt 48 68)(line_width 1)) + ) + (port + (pt 96 48) + (output) + (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "result" (rect 66 35 91 48)(font "Arial" (font_size 8))) + (line (pt 96 48)(pt 56 48)(line_width 1)) + ) + (drawing + (line (pt 40 24)(pt 40 72)(line_width 1)) + (line (pt 56 32)(pt 56 64)(line_width 1)) + (line (pt 40 24)(pt 56 32)(line_width 1)) + (line (pt 40 72)(pt 56 64)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.cmp b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.cmp new file mode 100644 index 0000000..725acf4 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxDZ2 + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.qip b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.qip new file mode 100644 index 0000000..8203bc6 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.vhd b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.vhd new file mode 100644 index 0000000..42e0c81 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxDZ2.vhd @@ -0,0 +1,115 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxDZ2.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxDZ2 IS + PORT + ( + data0 : IN STD_LOGIC ; + data1 : IN STD_LOGIC ; + sel : IN STD_LOGIC ; + result : OUT STD_LOGIC + ); +END lpm_muxDZ2; + + +ARCHITECTURE SYN OF lpm_muxdz2 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + +BEGIN + sub_wire6 <= data0; + sub_wire1 <= sub_wire0(0); + result <= sub_wire1; + sub_wire2 <= sel; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= data1; + sub_wire5(1, 0) <= sub_wire4; + sub_wire5(0, 0) <= sub_wire6; + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 2, + lpm_type => "LPM_MUX", + lpm_width => 1, + lpm_widths => 1 + ) + PORT MAP ( + sel => sub_wire3, + data => sub_wire5, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1" +-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0 +-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1 +-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result +-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel +-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0 +-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0 +-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0 +-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.bsf b/FPGA_Quartus_13.1/Video/lpm_muxVDM.bsf new file mode 100644 index 0000000..42d235c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxVDM.bsf @@ -0,0 +1,158 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2009 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 168 304) + (text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 25 300)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 80 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 80 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 80 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 80 88)(line_width 3)) + ) + (port + (pt 0 104) + (input) + (text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8))) + (line (pt 0 104)(pt 80 104)(line_width 3)) + ) + (port + (pt 0 120) + (input) + (text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8))) + (text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 80 120)(line_width 3)) + ) + (port + (pt 0 136) + (input) + (text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8))) + (line (pt 0 136)(pt 80 136)(line_width 3)) + ) + (port + (pt 0 152) + (input) + (text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 80 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 80 168)(line_width 3)) + ) + (port + (pt 0 184) + (input) + (text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 80 184)(line_width 3)) + ) + (port + (pt 0 200) + (input) + (text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 80 200)(line_width 3)) + ) + (port + (pt 0 216) + (input) + (text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8))) + (line (pt 0 216)(pt 80 216)(line_width 3)) + ) + (port + (pt 0 232) + (input) + (text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8))) + (line (pt 0 232)(pt 80 232)(line_width 3)) + ) + (port + (pt 0 248) + (input) + (text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 80 248)(line_width 3)) + ) + (port + (pt 0 264) + (input) + (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8))) + (line (pt 0 264)(pt 80 264)(line_width 3)) + ) + (port + (pt 0 280) + (input) + (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) + (text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 80 280)(line_width 3)) + ) + (port + (pt 88 304) + (input) + (text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) + (text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8))) + (line (pt 88 304)(pt 88 292)(line_width 3)) + ) + (port + (pt 168 160) + (output) + (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8))) + (line (pt 168 160)(pt 96 160)(line_width 3)) + ) + (drawing + (line (pt 80 24)(pt 80 296)(line_width 1)) + (line (pt 96 32)(pt 96 288)(line_width 1)) + (line (pt 80 24)(pt 96 32)(line_width 1)) + (line (pt 80 296)(pt 96 288)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.cmp b/FPGA_Quartus_13.1/Video/lpm_muxVDM.cmp new file mode 100644 index 0000000..867776d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxVDM.cmp @@ -0,0 +1,38 @@ +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_muxVDM + PORT + ( + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.qip b/FPGA_Quartus_13.1/Video/lpm_muxVDM.qip new file mode 100644 index 0000000..08a824e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxVDM.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.vhd b/FPGA_Quartus_13.1/Video/lpm_muxVDM.vhd new file mode 100644 index 0000000..662c8be --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_muxVDM.vhd @@ -0,0 +1,2225 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_mux + +-- ============================================================ +-- File Name: lpm_muxVDM.vhd +-- Megafunction Name(s): +-- lpm_mux +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_muxVDM IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (127 DOWNTO 0) + ); +END lpm_muxVDM; + + +ARCHITECTURE SYN OF lpm_muxvdm IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (15 DOWNTO 0, 127 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (127 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (127 DOWNTO 0); + +BEGIN + sub_wire17 <= data0x(127 DOWNTO 0); + sub_wire16 <= data1x(127 DOWNTO 0); + sub_wire15 <= data2x(127 DOWNTO 0); + sub_wire14 <= data3x(127 DOWNTO 0); + sub_wire13 <= data4x(127 DOWNTO 0); + sub_wire12 <= data5x(127 DOWNTO 0); + sub_wire11 <= data6x(127 DOWNTO 0); + sub_wire10 <= data7x(127 DOWNTO 0); + sub_wire9 <= data8x(127 DOWNTO 0); + sub_wire8 <= data9x(127 DOWNTO 0); + sub_wire7 <= data10x(127 DOWNTO 0); + sub_wire6 <= data11x(127 DOWNTO 0); + sub_wire5 <= data12x(127 DOWNTO 0); + sub_wire4 <= data13x(127 DOWNTO 0); + sub_wire3 <= data14x(127 DOWNTO 0); + result <= sub_wire0(127 DOWNTO 0); + sub_wire1 <= data15x(127 DOWNTO 0); + sub_wire2(15, 0) <= sub_wire1(0); + sub_wire2(15, 1) <= sub_wire1(1); + sub_wire2(15, 2) <= sub_wire1(2); + sub_wire2(15, 3) <= sub_wire1(3); + sub_wire2(15, 4) <= sub_wire1(4); + sub_wire2(15, 5) <= sub_wire1(5); + sub_wire2(15, 6) <= sub_wire1(6); + sub_wire2(15, 7) <= sub_wire1(7); + sub_wire2(15, 8) <= sub_wire1(8); + sub_wire2(15, 9) <= sub_wire1(9); + sub_wire2(15, 10) <= sub_wire1(10); + sub_wire2(15, 11) <= sub_wire1(11); + sub_wire2(15, 12) <= sub_wire1(12); + sub_wire2(15, 13) <= sub_wire1(13); + sub_wire2(15, 14) <= sub_wire1(14); + sub_wire2(15, 15) <= sub_wire1(15); + sub_wire2(15, 16) <= sub_wire1(16); + sub_wire2(15, 17) <= sub_wire1(17); + sub_wire2(15, 18) <= sub_wire1(18); + sub_wire2(15, 19) <= sub_wire1(19); + sub_wire2(15, 20) <= sub_wire1(20); + sub_wire2(15, 21) <= sub_wire1(21); + sub_wire2(15, 22) <= sub_wire1(22); + sub_wire2(15, 23) <= sub_wire1(23); + sub_wire2(15, 24) <= sub_wire1(24); + sub_wire2(15, 25) <= sub_wire1(25); + sub_wire2(15, 26) <= sub_wire1(26); + sub_wire2(15, 27) <= sub_wire1(27); + sub_wire2(15, 28) <= sub_wire1(28); + sub_wire2(15, 29) <= sub_wire1(29); + sub_wire2(15, 30) <= sub_wire1(30); + sub_wire2(15, 31) <= sub_wire1(31); + sub_wire2(15, 32) <= sub_wire1(32); + sub_wire2(15, 33) <= sub_wire1(33); + sub_wire2(15, 34) <= sub_wire1(34); + sub_wire2(15, 35) <= sub_wire1(35); + sub_wire2(15, 36) <= sub_wire1(36); + sub_wire2(15, 37) <= sub_wire1(37); + sub_wire2(15, 38) <= sub_wire1(38); + sub_wire2(15, 39) <= sub_wire1(39); + sub_wire2(15, 40) <= sub_wire1(40); + sub_wire2(15, 41) <= sub_wire1(41); + sub_wire2(15, 42) <= sub_wire1(42); + sub_wire2(15, 43) <= sub_wire1(43); + sub_wire2(15, 44) <= sub_wire1(44); + sub_wire2(15, 45) <= sub_wire1(45); + sub_wire2(15, 46) <= sub_wire1(46); + sub_wire2(15, 47) <= sub_wire1(47); + sub_wire2(15, 48) <= sub_wire1(48); + sub_wire2(15, 49) <= sub_wire1(49); + sub_wire2(15, 50) <= sub_wire1(50); + sub_wire2(15, 51) <= sub_wire1(51); + sub_wire2(15, 52) <= sub_wire1(52); + sub_wire2(15, 53) <= sub_wire1(53); + sub_wire2(15, 54) <= sub_wire1(54); + sub_wire2(15, 55) <= sub_wire1(55); + sub_wire2(15, 56) <= sub_wire1(56); + sub_wire2(15, 57) <= sub_wire1(57); + sub_wire2(15, 58) <= sub_wire1(58); + sub_wire2(15, 59) <= sub_wire1(59); + sub_wire2(15, 60) <= sub_wire1(60); + sub_wire2(15, 61) <= sub_wire1(61); + sub_wire2(15, 62) <= sub_wire1(62); + sub_wire2(15, 63) <= sub_wire1(63); + sub_wire2(15, 64) <= sub_wire1(64); + sub_wire2(15, 65) <= sub_wire1(65); + sub_wire2(15, 66) <= sub_wire1(66); + sub_wire2(15, 67) <= sub_wire1(67); + sub_wire2(15, 68) <= sub_wire1(68); + sub_wire2(15, 69) <= sub_wire1(69); + sub_wire2(15, 70) <= sub_wire1(70); + sub_wire2(15, 71) <= sub_wire1(71); + sub_wire2(15, 72) <= sub_wire1(72); + sub_wire2(15, 73) <= sub_wire1(73); + sub_wire2(15, 74) <= sub_wire1(74); + sub_wire2(15, 75) <= sub_wire1(75); + sub_wire2(15, 76) <= sub_wire1(76); + sub_wire2(15, 77) <= sub_wire1(77); + sub_wire2(15, 78) <= sub_wire1(78); + sub_wire2(15, 79) <= sub_wire1(79); + sub_wire2(15, 80) <= sub_wire1(80); + sub_wire2(15, 81) <= sub_wire1(81); + sub_wire2(15, 82) <= sub_wire1(82); + sub_wire2(15, 83) <= sub_wire1(83); + sub_wire2(15, 84) <= sub_wire1(84); + sub_wire2(15, 85) <= sub_wire1(85); + sub_wire2(15, 86) <= sub_wire1(86); + sub_wire2(15, 87) <= sub_wire1(87); + sub_wire2(15, 88) <= sub_wire1(88); + sub_wire2(15, 89) <= sub_wire1(89); + sub_wire2(15, 90) <= sub_wire1(90); + sub_wire2(15, 91) <= sub_wire1(91); + sub_wire2(15, 92) <= sub_wire1(92); + sub_wire2(15, 93) <= sub_wire1(93); + sub_wire2(15, 94) <= sub_wire1(94); + sub_wire2(15, 95) <= sub_wire1(95); + sub_wire2(15, 96) <= sub_wire1(96); + sub_wire2(15, 97) <= sub_wire1(97); + sub_wire2(15, 98) <= sub_wire1(98); + sub_wire2(15, 99) <= sub_wire1(99); + sub_wire2(15, 100) <= sub_wire1(100); + sub_wire2(15, 101) <= sub_wire1(101); + sub_wire2(15, 102) <= sub_wire1(102); + sub_wire2(15, 103) <= sub_wire1(103); + sub_wire2(15, 104) <= sub_wire1(104); + sub_wire2(15, 105) <= sub_wire1(105); + sub_wire2(15, 106) <= sub_wire1(106); + sub_wire2(15, 107) <= sub_wire1(107); + sub_wire2(15, 108) <= sub_wire1(108); + sub_wire2(15, 109) <= sub_wire1(109); + sub_wire2(15, 110) <= sub_wire1(110); + sub_wire2(15, 111) <= sub_wire1(111); + sub_wire2(15, 112) <= sub_wire1(112); + sub_wire2(15, 113) <= sub_wire1(113); + sub_wire2(15, 114) <= sub_wire1(114); + sub_wire2(15, 115) <= sub_wire1(115); + sub_wire2(15, 116) <= sub_wire1(116); + sub_wire2(15, 117) <= sub_wire1(117); + sub_wire2(15, 118) <= sub_wire1(118); + sub_wire2(15, 119) <= sub_wire1(119); + sub_wire2(15, 120) <= sub_wire1(120); + sub_wire2(15, 121) <= sub_wire1(121); + sub_wire2(15, 122) <= sub_wire1(122); + sub_wire2(15, 123) <= sub_wire1(123); + sub_wire2(15, 124) <= sub_wire1(124); + sub_wire2(15, 125) <= sub_wire1(125); + sub_wire2(15, 126) <= sub_wire1(126); + sub_wire2(15, 127) <= sub_wire1(127); + sub_wire2(14, 0) <= sub_wire3(0); + sub_wire2(14, 1) <= sub_wire3(1); + sub_wire2(14, 2) <= sub_wire3(2); + sub_wire2(14, 3) <= sub_wire3(3); + sub_wire2(14, 4) <= sub_wire3(4); + sub_wire2(14, 5) <= sub_wire3(5); + sub_wire2(14, 6) <= sub_wire3(6); + sub_wire2(14, 7) <= sub_wire3(7); + sub_wire2(14, 8) <= sub_wire3(8); + sub_wire2(14, 9) <= sub_wire3(9); + sub_wire2(14, 10) <= sub_wire3(10); + sub_wire2(14, 11) <= sub_wire3(11); + sub_wire2(14, 12) <= sub_wire3(12); + sub_wire2(14, 13) <= sub_wire3(13); + sub_wire2(14, 14) <= sub_wire3(14); + sub_wire2(14, 15) <= sub_wire3(15); + sub_wire2(14, 16) <= sub_wire3(16); + sub_wire2(14, 17) <= sub_wire3(17); + sub_wire2(14, 18) <= sub_wire3(18); + sub_wire2(14, 19) <= sub_wire3(19); + sub_wire2(14, 20) <= sub_wire3(20); + sub_wire2(14, 21) <= sub_wire3(21); + sub_wire2(14, 22) <= sub_wire3(22); + sub_wire2(14, 23) <= sub_wire3(23); + sub_wire2(14, 24) <= sub_wire3(24); + sub_wire2(14, 25) <= sub_wire3(25); + sub_wire2(14, 26) <= sub_wire3(26); + sub_wire2(14, 27) <= sub_wire3(27); + sub_wire2(14, 28) <= sub_wire3(28); + sub_wire2(14, 29) <= sub_wire3(29); + sub_wire2(14, 30) <= sub_wire3(30); + sub_wire2(14, 31) <= sub_wire3(31); + sub_wire2(14, 32) <= sub_wire3(32); + sub_wire2(14, 33) <= sub_wire3(33); + sub_wire2(14, 34) <= sub_wire3(34); + sub_wire2(14, 35) <= sub_wire3(35); + sub_wire2(14, 36) <= sub_wire3(36); + sub_wire2(14, 37) <= sub_wire3(37); + sub_wire2(14, 38) <= sub_wire3(38); + sub_wire2(14, 39) <= sub_wire3(39); + sub_wire2(14, 40) <= sub_wire3(40); + sub_wire2(14, 41) <= sub_wire3(41); + sub_wire2(14, 42) <= sub_wire3(42); + sub_wire2(14, 43) <= sub_wire3(43); + sub_wire2(14, 44) <= sub_wire3(44); + sub_wire2(14, 45) <= sub_wire3(45); + sub_wire2(14, 46) <= sub_wire3(46); + sub_wire2(14, 47) <= sub_wire3(47); + sub_wire2(14, 48) <= sub_wire3(48); + sub_wire2(14, 49) <= sub_wire3(49); + sub_wire2(14, 50) <= sub_wire3(50); + sub_wire2(14, 51) <= sub_wire3(51); + sub_wire2(14, 52) <= sub_wire3(52); + sub_wire2(14, 53) <= sub_wire3(53); + sub_wire2(14, 54) <= sub_wire3(54); + sub_wire2(14, 55) <= sub_wire3(55); + sub_wire2(14, 56) <= sub_wire3(56); + sub_wire2(14, 57) <= sub_wire3(57); + sub_wire2(14, 58) <= sub_wire3(58); + sub_wire2(14, 59) <= sub_wire3(59); + sub_wire2(14, 60) <= sub_wire3(60); + sub_wire2(14, 61) <= sub_wire3(61); + sub_wire2(14, 62) <= sub_wire3(62); + sub_wire2(14, 63) <= sub_wire3(63); + sub_wire2(14, 64) <= sub_wire3(64); + sub_wire2(14, 65) <= sub_wire3(65); + sub_wire2(14, 66) <= sub_wire3(66); + sub_wire2(14, 67) <= sub_wire3(67); + sub_wire2(14, 68) <= sub_wire3(68); + sub_wire2(14, 69) <= sub_wire3(69); + sub_wire2(14, 70) <= sub_wire3(70); + sub_wire2(14, 71) <= sub_wire3(71); + sub_wire2(14, 72) <= sub_wire3(72); + sub_wire2(14, 73) <= sub_wire3(73); + sub_wire2(14, 74) <= sub_wire3(74); + sub_wire2(14, 75) <= sub_wire3(75); + sub_wire2(14, 76) <= sub_wire3(76); + sub_wire2(14, 77) <= sub_wire3(77); + sub_wire2(14, 78) <= sub_wire3(78); + sub_wire2(14, 79) <= sub_wire3(79); + sub_wire2(14, 80) <= sub_wire3(80); + sub_wire2(14, 81) <= sub_wire3(81); + sub_wire2(14, 82) <= sub_wire3(82); + sub_wire2(14, 83) <= sub_wire3(83); + sub_wire2(14, 84) <= sub_wire3(84); + sub_wire2(14, 85) <= sub_wire3(85); + sub_wire2(14, 86) <= sub_wire3(86); + sub_wire2(14, 87) <= sub_wire3(87); + sub_wire2(14, 88) <= sub_wire3(88); + sub_wire2(14, 89) <= sub_wire3(89); + sub_wire2(14, 90) <= sub_wire3(90); + sub_wire2(14, 91) <= sub_wire3(91); + sub_wire2(14, 92) <= sub_wire3(92); + sub_wire2(14, 93) <= sub_wire3(93); + sub_wire2(14, 94) <= sub_wire3(94); + sub_wire2(14, 95) <= sub_wire3(95); + sub_wire2(14, 96) <= sub_wire3(96); + sub_wire2(14, 97) <= sub_wire3(97); + sub_wire2(14, 98) <= sub_wire3(98); + sub_wire2(14, 99) <= sub_wire3(99); + sub_wire2(14, 100) <= sub_wire3(100); + sub_wire2(14, 101) <= sub_wire3(101); + sub_wire2(14, 102) <= sub_wire3(102); + sub_wire2(14, 103) <= sub_wire3(103); + sub_wire2(14, 104) <= sub_wire3(104); + sub_wire2(14, 105) <= sub_wire3(105); + sub_wire2(14, 106) <= sub_wire3(106); + sub_wire2(14, 107) <= sub_wire3(107); + sub_wire2(14, 108) <= sub_wire3(108); + sub_wire2(14, 109) <= sub_wire3(109); + sub_wire2(14, 110) <= sub_wire3(110); + sub_wire2(14, 111) <= sub_wire3(111); + sub_wire2(14, 112) <= sub_wire3(112); + sub_wire2(14, 113) <= sub_wire3(113); + sub_wire2(14, 114) <= sub_wire3(114); + sub_wire2(14, 115) <= sub_wire3(115); + sub_wire2(14, 116) <= sub_wire3(116); + sub_wire2(14, 117) <= sub_wire3(117); + sub_wire2(14, 118) <= sub_wire3(118); + sub_wire2(14, 119) <= sub_wire3(119); + sub_wire2(14, 120) <= sub_wire3(120); + sub_wire2(14, 121) <= sub_wire3(121); + sub_wire2(14, 122) <= sub_wire3(122); + sub_wire2(14, 123) <= sub_wire3(123); + sub_wire2(14, 124) <= sub_wire3(124); + sub_wire2(14, 125) <= sub_wire3(125); + sub_wire2(14, 126) <= sub_wire3(126); + sub_wire2(14, 127) <= sub_wire3(127); + sub_wire2(13, 0) <= sub_wire4(0); + sub_wire2(13, 1) <= sub_wire4(1); + sub_wire2(13, 2) <= sub_wire4(2); + sub_wire2(13, 3) <= sub_wire4(3); + sub_wire2(13, 4) <= sub_wire4(4); + sub_wire2(13, 5) <= sub_wire4(5); + sub_wire2(13, 6) <= sub_wire4(6); + sub_wire2(13, 7) <= sub_wire4(7); + sub_wire2(13, 8) <= sub_wire4(8); + sub_wire2(13, 9) <= sub_wire4(9); + sub_wire2(13, 10) <= sub_wire4(10); + sub_wire2(13, 11) <= sub_wire4(11); + sub_wire2(13, 12) <= sub_wire4(12); + sub_wire2(13, 13) <= sub_wire4(13); + sub_wire2(13, 14) <= sub_wire4(14); + sub_wire2(13, 15) <= sub_wire4(15); + sub_wire2(13, 16) <= sub_wire4(16); + sub_wire2(13, 17) <= sub_wire4(17); + sub_wire2(13, 18) <= sub_wire4(18); + sub_wire2(13, 19) <= sub_wire4(19); + sub_wire2(13, 20) <= sub_wire4(20); + sub_wire2(13, 21) <= sub_wire4(21); + sub_wire2(13, 22) <= sub_wire4(22); + sub_wire2(13, 23) <= sub_wire4(23); + sub_wire2(13, 24) <= sub_wire4(24); + sub_wire2(13, 25) <= sub_wire4(25); + sub_wire2(13, 26) <= sub_wire4(26); + sub_wire2(13, 27) <= sub_wire4(27); + sub_wire2(13, 28) <= sub_wire4(28); + sub_wire2(13, 29) <= sub_wire4(29); + sub_wire2(13, 30) <= sub_wire4(30); + sub_wire2(13, 31) <= sub_wire4(31); + sub_wire2(13, 32) <= sub_wire4(32); + sub_wire2(13, 33) <= sub_wire4(33); + sub_wire2(13, 34) <= sub_wire4(34); + sub_wire2(13, 35) <= sub_wire4(35); + sub_wire2(13, 36) <= sub_wire4(36); + sub_wire2(13, 37) <= sub_wire4(37); + sub_wire2(13, 38) <= sub_wire4(38); + sub_wire2(13, 39) <= sub_wire4(39); + sub_wire2(13, 40) <= sub_wire4(40); + sub_wire2(13, 41) <= sub_wire4(41); + sub_wire2(13, 42) <= sub_wire4(42); + sub_wire2(13, 43) <= sub_wire4(43); + sub_wire2(13, 44) <= sub_wire4(44); + sub_wire2(13, 45) <= sub_wire4(45); + sub_wire2(13, 46) <= sub_wire4(46); + sub_wire2(13, 47) <= sub_wire4(47); + sub_wire2(13, 48) <= sub_wire4(48); + sub_wire2(13, 49) <= sub_wire4(49); + sub_wire2(13, 50) <= sub_wire4(50); + sub_wire2(13, 51) <= sub_wire4(51); + sub_wire2(13, 52) <= sub_wire4(52); + sub_wire2(13, 53) <= sub_wire4(53); + sub_wire2(13, 54) <= sub_wire4(54); + sub_wire2(13, 55) <= sub_wire4(55); + sub_wire2(13, 56) <= sub_wire4(56); + sub_wire2(13, 57) <= sub_wire4(57); + sub_wire2(13, 58) <= sub_wire4(58); + sub_wire2(13, 59) <= sub_wire4(59); + sub_wire2(13, 60) <= sub_wire4(60); + sub_wire2(13, 61) <= sub_wire4(61); + sub_wire2(13, 62) <= sub_wire4(62); + sub_wire2(13, 63) <= sub_wire4(63); + sub_wire2(13, 64) <= sub_wire4(64); + sub_wire2(13, 65) <= sub_wire4(65); + sub_wire2(13, 66) <= sub_wire4(66); + sub_wire2(13, 67) <= sub_wire4(67); + sub_wire2(13, 68) <= sub_wire4(68); + sub_wire2(13, 69) <= sub_wire4(69); + sub_wire2(13, 70) <= sub_wire4(70); + sub_wire2(13, 71) <= sub_wire4(71); + sub_wire2(13, 72) <= sub_wire4(72); + sub_wire2(13, 73) <= sub_wire4(73); + sub_wire2(13, 74) <= sub_wire4(74); + sub_wire2(13, 75) <= sub_wire4(75); + sub_wire2(13, 76) <= sub_wire4(76); + sub_wire2(13, 77) <= sub_wire4(77); + sub_wire2(13, 78) <= sub_wire4(78); + sub_wire2(13, 79) <= sub_wire4(79); + sub_wire2(13, 80) <= sub_wire4(80); + sub_wire2(13, 81) <= sub_wire4(81); + sub_wire2(13, 82) <= sub_wire4(82); + sub_wire2(13, 83) <= sub_wire4(83); + sub_wire2(13, 84) <= sub_wire4(84); + sub_wire2(13, 85) <= sub_wire4(85); + sub_wire2(13, 86) <= sub_wire4(86); + sub_wire2(13, 87) <= sub_wire4(87); + sub_wire2(13, 88) <= sub_wire4(88); + sub_wire2(13, 89) <= sub_wire4(89); + sub_wire2(13, 90) <= sub_wire4(90); + sub_wire2(13, 91) <= sub_wire4(91); + sub_wire2(13, 92) <= sub_wire4(92); + sub_wire2(13, 93) <= sub_wire4(93); + sub_wire2(13, 94) <= sub_wire4(94); + sub_wire2(13, 95) <= sub_wire4(95); + sub_wire2(13, 96) <= sub_wire4(96); + sub_wire2(13, 97) <= sub_wire4(97); + sub_wire2(13, 98) <= sub_wire4(98); + sub_wire2(13, 99) <= sub_wire4(99); + sub_wire2(13, 100) <= sub_wire4(100); + sub_wire2(13, 101) <= sub_wire4(101); + sub_wire2(13, 102) <= sub_wire4(102); + sub_wire2(13, 103) <= sub_wire4(103); + sub_wire2(13, 104) <= sub_wire4(104); + sub_wire2(13, 105) <= sub_wire4(105); + sub_wire2(13, 106) <= sub_wire4(106); + sub_wire2(13, 107) <= sub_wire4(107); + sub_wire2(13, 108) <= sub_wire4(108); + sub_wire2(13, 109) <= sub_wire4(109); + sub_wire2(13, 110) <= sub_wire4(110); + sub_wire2(13, 111) <= sub_wire4(111); + sub_wire2(13, 112) <= sub_wire4(112); + sub_wire2(13, 113) <= sub_wire4(113); + sub_wire2(13, 114) <= sub_wire4(114); + sub_wire2(13, 115) <= sub_wire4(115); + sub_wire2(13, 116) <= sub_wire4(116); + sub_wire2(13, 117) <= sub_wire4(117); + sub_wire2(13, 118) <= sub_wire4(118); + sub_wire2(13, 119) <= sub_wire4(119); + sub_wire2(13, 120) <= sub_wire4(120); + sub_wire2(13, 121) <= sub_wire4(121); + sub_wire2(13, 122) <= sub_wire4(122); + sub_wire2(13, 123) <= sub_wire4(123); + sub_wire2(13, 124) <= sub_wire4(124); + sub_wire2(13, 125) <= sub_wire4(125); + sub_wire2(13, 126) <= sub_wire4(126); + sub_wire2(13, 127) <= sub_wire4(127); + sub_wire2(12, 0) <= sub_wire5(0); + sub_wire2(12, 1) <= sub_wire5(1); + sub_wire2(12, 2) <= sub_wire5(2); + sub_wire2(12, 3) <= sub_wire5(3); + sub_wire2(12, 4) <= sub_wire5(4); + sub_wire2(12, 5) <= sub_wire5(5); + sub_wire2(12, 6) <= sub_wire5(6); + sub_wire2(12, 7) <= sub_wire5(7); + sub_wire2(12, 8) <= sub_wire5(8); + sub_wire2(12, 9) <= sub_wire5(9); + sub_wire2(12, 10) <= sub_wire5(10); + sub_wire2(12, 11) <= sub_wire5(11); + sub_wire2(12, 12) <= sub_wire5(12); + sub_wire2(12, 13) <= sub_wire5(13); + sub_wire2(12, 14) <= sub_wire5(14); + sub_wire2(12, 15) <= sub_wire5(15); + sub_wire2(12, 16) <= sub_wire5(16); + sub_wire2(12, 17) <= sub_wire5(17); + sub_wire2(12, 18) <= sub_wire5(18); + sub_wire2(12, 19) <= sub_wire5(19); + sub_wire2(12, 20) <= sub_wire5(20); + sub_wire2(12, 21) <= sub_wire5(21); + sub_wire2(12, 22) <= sub_wire5(22); + sub_wire2(12, 23) <= sub_wire5(23); + sub_wire2(12, 24) <= sub_wire5(24); + sub_wire2(12, 25) <= sub_wire5(25); + sub_wire2(12, 26) <= sub_wire5(26); + sub_wire2(12, 27) <= sub_wire5(27); + sub_wire2(12, 28) <= sub_wire5(28); + sub_wire2(12, 29) <= sub_wire5(29); + sub_wire2(12, 30) <= sub_wire5(30); + sub_wire2(12, 31) <= sub_wire5(31); + sub_wire2(12, 32) <= sub_wire5(32); + sub_wire2(12, 33) <= sub_wire5(33); + sub_wire2(12, 34) <= sub_wire5(34); + sub_wire2(12, 35) <= sub_wire5(35); + sub_wire2(12, 36) <= sub_wire5(36); + sub_wire2(12, 37) <= sub_wire5(37); + sub_wire2(12, 38) <= sub_wire5(38); + sub_wire2(12, 39) <= sub_wire5(39); + sub_wire2(12, 40) <= sub_wire5(40); + sub_wire2(12, 41) <= sub_wire5(41); + sub_wire2(12, 42) <= sub_wire5(42); + sub_wire2(12, 43) <= sub_wire5(43); + sub_wire2(12, 44) <= sub_wire5(44); + sub_wire2(12, 45) <= sub_wire5(45); + sub_wire2(12, 46) <= sub_wire5(46); + sub_wire2(12, 47) <= sub_wire5(47); + sub_wire2(12, 48) <= sub_wire5(48); + sub_wire2(12, 49) <= sub_wire5(49); + sub_wire2(12, 50) <= sub_wire5(50); + sub_wire2(12, 51) <= sub_wire5(51); + sub_wire2(12, 52) <= sub_wire5(52); + sub_wire2(12, 53) <= sub_wire5(53); + sub_wire2(12, 54) <= sub_wire5(54); + sub_wire2(12, 55) <= sub_wire5(55); + sub_wire2(12, 56) <= sub_wire5(56); + sub_wire2(12, 57) <= sub_wire5(57); + sub_wire2(12, 58) <= sub_wire5(58); + sub_wire2(12, 59) <= sub_wire5(59); + sub_wire2(12, 60) <= sub_wire5(60); + sub_wire2(12, 61) <= sub_wire5(61); + sub_wire2(12, 62) <= sub_wire5(62); + sub_wire2(12, 63) <= sub_wire5(63); + sub_wire2(12, 64) <= sub_wire5(64); + sub_wire2(12, 65) <= sub_wire5(65); + sub_wire2(12, 66) <= sub_wire5(66); + sub_wire2(12, 67) <= sub_wire5(67); + sub_wire2(12, 68) <= sub_wire5(68); + sub_wire2(12, 69) <= sub_wire5(69); + sub_wire2(12, 70) <= sub_wire5(70); + sub_wire2(12, 71) <= sub_wire5(71); + sub_wire2(12, 72) <= sub_wire5(72); + sub_wire2(12, 73) <= sub_wire5(73); + sub_wire2(12, 74) <= sub_wire5(74); + sub_wire2(12, 75) <= sub_wire5(75); + sub_wire2(12, 76) <= sub_wire5(76); + sub_wire2(12, 77) <= sub_wire5(77); + sub_wire2(12, 78) <= sub_wire5(78); + sub_wire2(12, 79) <= sub_wire5(79); + sub_wire2(12, 80) <= sub_wire5(80); + sub_wire2(12, 81) <= sub_wire5(81); + sub_wire2(12, 82) <= sub_wire5(82); + sub_wire2(12, 83) <= sub_wire5(83); + sub_wire2(12, 84) <= sub_wire5(84); + sub_wire2(12, 85) <= sub_wire5(85); + sub_wire2(12, 86) <= sub_wire5(86); + sub_wire2(12, 87) <= sub_wire5(87); + sub_wire2(12, 88) <= sub_wire5(88); + sub_wire2(12, 89) <= sub_wire5(89); + sub_wire2(12, 90) <= sub_wire5(90); + sub_wire2(12, 91) <= sub_wire5(91); + sub_wire2(12, 92) <= sub_wire5(92); + sub_wire2(12, 93) <= sub_wire5(93); + sub_wire2(12, 94) <= sub_wire5(94); + sub_wire2(12, 95) <= sub_wire5(95); + sub_wire2(12, 96) <= sub_wire5(96); + sub_wire2(12, 97) <= sub_wire5(97); + sub_wire2(12, 98) <= sub_wire5(98); + sub_wire2(12, 99) <= sub_wire5(99); + sub_wire2(12, 100) <= sub_wire5(100); + sub_wire2(12, 101) <= sub_wire5(101); + sub_wire2(12, 102) <= sub_wire5(102); + sub_wire2(12, 103) <= sub_wire5(103); + sub_wire2(12, 104) <= sub_wire5(104); + sub_wire2(12, 105) <= sub_wire5(105); + sub_wire2(12, 106) <= sub_wire5(106); + sub_wire2(12, 107) <= sub_wire5(107); + sub_wire2(12, 108) <= sub_wire5(108); + sub_wire2(12, 109) <= sub_wire5(109); + sub_wire2(12, 110) <= sub_wire5(110); + sub_wire2(12, 111) <= sub_wire5(111); + sub_wire2(12, 112) <= sub_wire5(112); + sub_wire2(12, 113) <= sub_wire5(113); + sub_wire2(12, 114) <= sub_wire5(114); + sub_wire2(12, 115) <= sub_wire5(115); + sub_wire2(12, 116) <= sub_wire5(116); + sub_wire2(12, 117) <= sub_wire5(117); + sub_wire2(12, 118) <= sub_wire5(118); + sub_wire2(12, 119) <= sub_wire5(119); + sub_wire2(12, 120) <= sub_wire5(120); + sub_wire2(12, 121) <= sub_wire5(121); + sub_wire2(12, 122) <= sub_wire5(122); + sub_wire2(12, 123) <= sub_wire5(123); + sub_wire2(12, 124) <= sub_wire5(124); + sub_wire2(12, 125) <= sub_wire5(125); + sub_wire2(12, 126) <= sub_wire5(126); + sub_wire2(12, 127) <= sub_wire5(127); + sub_wire2(11, 0) <= sub_wire6(0); + sub_wire2(11, 1) <= sub_wire6(1); + sub_wire2(11, 2) <= sub_wire6(2); + sub_wire2(11, 3) <= sub_wire6(3); + sub_wire2(11, 4) <= sub_wire6(4); + sub_wire2(11, 5) <= sub_wire6(5); + sub_wire2(11, 6) <= sub_wire6(6); + sub_wire2(11, 7) <= sub_wire6(7); + sub_wire2(11, 8) <= sub_wire6(8); + sub_wire2(11, 9) <= sub_wire6(9); + sub_wire2(11, 10) <= sub_wire6(10); + sub_wire2(11, 11) <= sub_wire6(11); + sub_wire2(11, 12) <= sub_wire6(12); + sub_wire2(11, 13) <= sub_wire6(13); + sub_wire2(11, 14) <= sub_wire6(14); + sub_wire2(11, 15) <= sub_wire6(15); + sub_wire2(11, 16) <= sub_wire6(16); + sub_wire2(11, 17) <= sub_wire6(17); + sub_wire2(11, 18) <= sub_wire6(18); + sub_wire2(11, 19) <= sub_wire6(19); + sub_wire2(11, 20) <= sub_wire6(20); + sub_wire2(11, 21) <= sub_wire6(21); + sub_wire2(11, 22) <= sub_wire6(22); + sub_wire2(11, 23) <= sub_wire6(23); + sub_wire2(11, 24) <= sub_wire6(24); + sub_wire2(11, 25) <= sub_wire6(25); + sub_wire2(11, 26) <= sub_wire6(26); + sub_wire2(11, 27) <= sub_wire6(27); + sub_wire2(11, 28) <= sub_wire6(28); + sub_wire2(11, 29) <= sub_wire6(29); + sub_wire2(11, 30) <= sub_wire6(30); + sub_wire2(11, 31) <= sub_wire6(31); + sub_wire2(11, 32) <= sub_wire6(32); + sub_wire2(11, 33) <= sub_wire6(33); + sub_wire2(11, 34) <= sub_wire6(34); + sub_wire2(11, 35) <= sub_wire6(35); + sub_wire2(11, 36) <= sub_wire6(36); + sub_wire2(11, 37) <= sub_wire6(37); + sub_wire2(11, 38) <= sub_wire6(38); + sub_wire2(11, 39) <= sub_wire6(39); + sub_wire2(11, 40) <= sub_wire6(40); + sub_wire2(11, 41) <= sub_wire6(41); + sub_wire2(11, 42) <= sub_wire6(42); + sub_wire2(11, 43) <= sub_wire6(43); + sub_wire2(11, 44) <= sub_wire6(44); + sub_wire2(11, 45) <= sub_wire6(45); + sub_wire2(11, 46) <= sub_wire6(46); + sub_wire2(11, 47) <= sub_wire6(47); + sub_wire2(11, 48) <= sub_wire6(48); + sub_wire2(11, 49) <= sub_wire6(49); + sub_wire2(11, 50) <= sub_wire6(50); + sub_wire2(11, 51) <= sub_wire6(51); + sub_wire2(11, 52) <= sub_wire6(52); + sub_wire2(11, 53) <= sub_wire6(53); + sub_wire2(11, 54) <= sub_wire6(54); + sub_wire2(11, 55) <= sub_wire6(55); + sub_wire2(11, 56) <= sub_wire6(56); + sub_wire2(11, 57) <= sub_wire6(57); + sub_wire2(11, 58) <= sub_wire6(58); + sub_wire2(11, 59) <= sub_wire6(59); + sub_wire2(11, 60) <= sub_wire6(60); + sub_wire2(11, 61) <= sub_wire6(61); + sub_wire2(11, 62) <= sub_wire6(62); + sub_wire2(11, 63) <= sub_wire6(63); + sub_wire2(11, 64) <= sub_wire6(64); + sub_wire2(11, 65) <= sub_wire6(65); + sub_wire2(11, 66) <= sub_wire6(66); + sub_wire2(11, 67) <= sub_wire6(67); + sub_wire2(11, 68) <= sub_wire6(68); + sub_wire2(11, 69) <= sub_wire6(69); + sub_wire2(11, 70) <= sub_wire6(70); + sub_wire2(11, 71) <= sub_wire6(71); + sub_wire2(11, 72) <= sub_wire6(72); + sub_wire2(11, 73) <= sub_wire6(73); + sub_wire2(11, 74) <= sub_wire6(74); + sub_wire2(11, 75) <= sub_wire6(75); + sub_wire2(11, 76) <= sub_wire6(76); + sub_wire2(11, 77) <= sub_wire6(77); + sub_wire2(11, 78) <= sub_wire6(78); + sub_wire2(11, 79) <= sub_wire6(79); + sub_wire2(11, 80) <= sub_wire6(80); + sub_wire2(11, 81) <= sub_wire6(81); + sub_wire2(11, 82) <= sub_wire6(82); + sub_wire2(11, 83) <= sub_wire6(83); + sub_wire2(11, 84) <= sub_wire6(84); + sub_wire2(11, 85) <= sub_wire6(85); + sub_wire2(11, 86) <= sub_wire6(86); + sub_wire2(11, 87) <= sub_wire6(87); + sub_wire2(11, 88) <= sub_wire6(88); + sub_wire2(11, 89) <= sub_wire6(89); + sub_wire2(11, 90) <= sub_wire6(90); + sub_wire2(11, 91) <= sub_wire6(91); + sub_wire2(11, 92) <= sub_wire6(92); + sub_wire2(11, 93) <= sub_wire6(93); + sub_wire2(11, 94) <= sub_wire6(94); + sub_wire2(11, 95) <= sub_wire6(95); + sub_wire2(11, 96) <= sub_wire6(96); + sub_wire2(11, 97) <= sub_wire6(97); + sub_wire2(11, 98) <= sub_wire6(98); + sub_wire2(11, 99) <= sub_wire6(99); + sub_wire2(11, 100) <= sub_wire6(100); + sub_wire2(11, 101) <= sub_wire6(101); + sub_wire2(11, 102) <= sub_wire6(102); + sub_wire2(11, 103) <= sub_wire6(103); + sub_wire2(11, 104) <= sub_wire6(104); + sub_wire2(11, 105) <= sub_wire6(105); + sub_wire2(11, 106) <= sub_wire6(106); + sub_wire2(11, 107) <= sub_wire6(107); + sub_wire2(11, 108) <= sub_wire6(108); + sub_wire2(11, 109) <= sub_wire6(109); + sub_wire2(11, 110) <= sub_wire6(110); + sub_wire2(11, 111) <= sub_wire6(111); + sub_wire2(11, 112) <= sub_wire6(112); + sub_wire2(11, 113) <= sub_wire6(113); + sub_wire2(11, 114) <= sub_wire6(114); + sub_wire2(11, 115) <= sub_wire6(115); + sub_wire2(11, 116) <= sub_wire6(116); + sub_wire2(11, 117) <= sub_wire6(117); + sub_wire2(11, 118) <= sub_wire6(118); + sub_wire2(11, 119) <= sub_wire6(119); + sub_wire2(11, 120) <= sub_wire6(120); + sub_wire2(11, 121) <= sub_wire6(121); + sub_wire2(11, 122) <= sub_wire6(122); + sub_wire2(11, 123) <= sub_wire6(123); + sub_wire2(11, 124) <= sub_wire6(124); + sub_wire2(11, 125) <= sub_wire6(125); + sub_wire2(11, 126) <= sub_wire6(126); + sub_wire2(11, 127) <= sub_wire6(127); + sub_wire2(10, 0) <= sub_wire7(0); + sub_wire2(10, 1) <= sub_wire7(1); + sub_wire2(10, 2) <= sub_wire7(2); + sub_wire2(10, 3) <= sub_wire7(3); + sub_wire2(10, 4) <= sub_wire7(4); + sub_wire2(10, 5) <= sub_wire7(5); + sub_wire2(10, 6) <= sub_wire7(6); + sub_wire2(10, 7) <= sub_wire7(7); + sub_wire2(10, 8) <= sub_wire7(8); + sub_wire2(10, 9) <= sub_wire7(9); + sub_wire2(10, 10) <= sub_wire7(10); + sub_wire2(10, 11) <= sub_wire7(11); + sub_wire2(10, 12) <= sub_wire7(12); + sub_wire2(10, 13) <= sub_wire7(13); + sub_wire2(10, 14) <= sub_wire7(14); + sub_wire2(10, 15) <= sub_wire7(15); + sub_wire2(10, 16) <= sub_wire7(16); + sub_wire2(10, 17) <= sub_wire7(17); + sub_wire2(10, 18) <= sub_wire7(18); + sub_wire2(10, 19) <= sub_wire7(19); + sub_wire2(10, 20) <= sub_wire7(20); + sub_wire2(10, 21) <= sub_wire7(21); + sub_wire2(10, 22) <= sub_wire7(22); + sub_wire2(10, 23) <= sub_wire7(23); + sub_wire2(10, 24) <= sub_wire7(24); + sub_wire2(10, 25) <= sub_wire7(25); + sub_wire2(10, 26) <= sub_wire7(26); + sub_wire2(10, 27) <= sub_wire7(27); + sub_wire2(10, 28) <= sub_wire7(28); + sub_wire2(10, 29) <= sub_wire7(29); + sub_wire2(10, 30) <= sub_wire7(30); + sub_wire2(10, 31) <= sub_wire7(31); + sub_wire2(10, 32) <= sub_wire7(32); + sub_wire2(10, 33) <= sub_wire7(33); + sub_wire2(10, 34) <= sub_wire7(34); + sub_wire2(10, 35) <= sub_wire7(35); + sub_wire2(10, 36) <= sub_wire7(36); + sub_wire2(10, 37) <= sub_wire7(37); + sub_wire2(10, 38) <= sub_wire7(38); + sub_wire2(10, 39) <= sub_wire7(39); + sub_wire2(10, 40) <= sub_wire7(40); + sub_wire2(10, 41) <= sub_wire7(41); + sub_wire2(10, 42) <= sub_wire7(42); + sub_wire2(10, 43) <= sub_wire7(43); + sub_wire2(10, 44) <= sub_wire7(44); + sub_wire2(10, 45) <= sub_wire7(45); + sub_wire2(10, 46) <= sub_wire7(46); + sub_wire2(10, 47) <= sub_wire7(47); + sub_wire2(10, 48) <= sub_wire7(48); + sub_wire2(10, 49) <= sub_wire7(49); + sub_wire2(10, 50) <= sub_wire7(50); + sub_wire2(10, 51) <= sub_wire7(51); + sub_wire2(10, 52) <= sub_wire7(52); + sub_wire2(10, 53) <= sub_wire7(53); + sub_wire2(10, 54) <= sub_wire7(54); + sub_wire2(10, 55) <= sub_wire7(55); + sub_wire2(10, 56) <= sub_wire7(56); + sub_wire2(10, 57) <= sub_wire7(57); + sub_wire2(10, 58) <= sub_wire7(58); + sub_wire2(10, 59) <= sub_wire7(59); + sub_wire2(10, 60) <= sub_wire7(60); + sub_wire2(10, 61) <= sub_wire7(61); + sub_wire2(10, 62) <= sub_wire7(62); + sub_wire2(10, 63) <= sub_wire7(63); + sub_wire2(10, 64) <= sub_wire7(64); + sub_wire2(10, 65) <= sub_wire7(65); + sub_wire2(10, 66) <= sub_wire7(66); + sub_wire2(10, 67) <= sub_wire7(67); + sub_wire2(10, 68) <= sub_wire7(68); + sub_wire2(10, 69) <= sub_wire7(69); + sub_wire2(10, 70) <= sub_wire7(70); + sub_wire2(10, 71) <= sub_wire7(71); + sub_wire2(10, 72) <= sub_wire7(72); + sub_wire2(10, 73) <= sub_wire7(73); + sub_wire2(10, 74) <= sub_wire7(74); + sub_wire2(10, 75) <= sub_wire7(75); + sub_wire2(10, 76) <= sub_wire7(76); + sub_wire2(10, 77) <= sub_wire7(77); + sub_wire2(10, 78) <= sub_wire7(78); + sub_wire2(10, 79) <= sub_wire7(79); + sub_wire2(10, 80) <= sub_wire7(80); + sub_wire2(10, 81) <= sub_wire7(81); + sub_wire2(10, 82) <= sub_wire7(82); + sub_wire2(10, 83) <= sub_wire7(83); + sub_wire2(10, 84) <= sub_wire7(84); + sub_wire2(10, 85) <= sub_wire7(85); + sub_wire2(10, 86) <= sub_wire7(86); + sub_wire2(10, 87) <= sub_wire7(87); + sub_wire2(10, 88) <= sub_wire7(88); + sub_wire2(10, 89) <= sub_wire7(89); + sub_wire2(10, 90) <= sub_wire7(90); + sub_wire2(10, 91) <= sub_wire7(91); + sub_wire2(10, 92) <= sub_wire7(92); + sub_wire2(10, 93) <= sub_wire7(93); + sub_wire2(10, 94) <= sub_wire7(94); + sub_wire2(10, 95) <= sub_wire7(95); + sub_wire2(10, 96) <= sub_wire7(96); + sub_wire2(10, 97) <= sub_wire7(97); + sub_wire2(10, 98) <= sub_wire7(98); + sub_wire2(10, 99) <= sub_wire7(99); + sub_wire2(10, 100) <= sub_wire7(100); + sub_wire2(10, 101) <= sub_wire7(101); + sub_wire2(10, 102) <= sub_wire7(102); + sub_wire2(10, 103) <= sub_wire7(103); + sub_wire2(10, 104) <= sub_wire7(104); + sub_wire2(10, 105) <= sub_wire7(105); + sub_wire2(10, 106) <= sub_wire7(106); + sub_wire2(10, 107) <= sub_wire7(107); + sub_wire2(10, 108) <= sub_wire7(108); + sub_wire2(10, 109) <= sub_wire7(109); + sub_wire2(10, 110) <= sub_wire7(110); + sub_wire2(10, 111) <= sub_wire7(111); + sub_wire2(10, 112) <= sub_wire7(112); + sub_wire2(10, 113) <= sub_wire7(113); + sub_wire2(10, 114) <= sub_wire7(114); + sub_wire2(10, 115) <= sub_wire7(115); + sub_wire2(10, 116) <= sub_wire7(116); + sub_wire2(10, 117) <= sub_wire7(117); + sub_wire2(10, 118) <= sub_wire7(118); + sub_wire2(10, 119) <= sub_wire7(119); + sub_wire2(10, 120) <= sub_wire7(120); + sub_wire2(10, 121) <= sub_wire7(121); + sub_wire2(10, 122) <= sub_wire7(122); + sub_wire2(10, 123) <= sub_wire7(123); + sub_wire2(10, 124) <= sub_wire7(124); + sub_wire2(10, 125) <= sub_wire7(125); + sub_wire2(10, 126) <= sub_wire7(126); + sub_wire2(10, 127) <= sub_wire7(127); + sub_wire2(9, 0) <= sub_wire8(0); + sub_wire2(9, 1) <= sub_wire8(1); + sub_wire2(9, 2) <= sub_wire8(2); + sub_wire2(9, 3) <= sub_wire8(3); + sub_wire2(9, 4) <= sub_wire8(4); + sub_wire2(9, 5) <= sub_wire8(5); + sub_wire2(9, 6) <= sub_wire8(6); + sub_wire2(9, 7) <= sub_wire8(7); + sub_wire2(9, 8) <= sub_wire8(8); + sub_wire2(9, 9) <= sub_wire8(9); + sub_wire2(9, 10) <= sub_wire8(10); + sub_wire2(9, 11) <= sub_wire8(11); + sub_wire2(9, 12) <= sub_wire8(12); + sub_wire2(9, 13) <= sub_wire8(13); + sub_wire2(9, 14) <= sub_wire8(14); + sub_wire2(9, 15) <= sub_wire8(15); + sub_wire2(9, 16) <= sub_wire8(16); + sub_wire2(9, 17) <= sub_wire8(17); + sub_wire2(9, 18) <= sub_wire8(18); + sub_wire2(9, 19) <= sub_wire8(19); + sub_wire2(9, 20) <= sub_wire8(20); + sub_wire2(9, 21) <= sub_wire8(21); + sub_wire2(9, 22) <= sub_wire8(22); + sub_wire2(9, 23) <= sub_wire8(23); + sub_wire2(9, 24) <= sub_wire8(24); + sub_wire2(9, 25) <= sub_wire8(25); + sub_wire2(9, 26) <= sub_wire8(26); + sub_wire2(9, 27) <= sub_wire8(27); + sub_wire2(9, 28) <= sub_wire8(28); + sub_wire2(9, 29) <= sub_wire8(29); + sub_wire2(9, 30) <= sub_wire8(30); + sub_wire2(9, 31) <= sub_wire8(31); + sub_wire2(9, 32) <= sub_wire8(32); + sub_wire2(9, 33) <= sub_wire8(33); + sub_wire2(9, 34) <= sub_wire8(34); + sub_wire2(9, 35) <= sub_wire8(35); + sub_wire2(9, 36) <= sub_wire8(36); + sub_wire2(9, 37) <= sub_wire8(37); + sub_wire2(9, 38) <= sub_wire8(38); + sub_wire2(9, 39) <= sub_wire8(39); + sub_wire2(9, 40) <= sub_wire8(40); + sub_wire2(9, 41) <= sub_wire8(41); + sub_wire2(9, 42) <= sub_wire8(42); + sub_wire2(9, 43) <= sub_wire8(43); + sub_wire2(9, 44) <= sub_wire8(44); + sub_wire2(9, 45) <= sub_wire8(45); + sub_wire2(9, 46) <= sub_wire8(46); + sub_wire2(9, 47) <= sub_wire8(47); + sub_wire2(9, 48) <= sub_wire8(48); + sub_wire2(9, 49) <= sub_wire8(49); + sub_wire2(9, 50) <= sub_wire8(50); + sub_wire2(9, 51) <= sub_wire8(51); + sub_wire2(9, 52) <= sub_wire8(52); + sub_wire2(9, 53) <= sub_wire8(53); + sub_wire2(9, 54) <= sub_wire8(54); + sub_wire2(9, 55) <= sub_wire8(55); + sub_wire2(9, 56) <= sub_wire8(56); + sub_wire2(9, 57) <= sub_wire8(57); + sub_wire2(9, 58) <= sub_wire8(58); + sub_wire2(9, 59) <= sub_wire8(59); + sub_wire2(9, 60) <= sub_wire8(60); + sub_wire2(9, 61) <= sub_wire8(61); + sub_wire2(9, 62) <= sub_wire8(62); + sub_wire2(9, 63) <= sub_wire8(63); + sub_wire2(9, 64) <= sub_wire8(64); + sub_wire2(9, 65) <= sub_wire8(65); + sub_wire2(9, 66) <= sub_wire8(66); + sub_wire2(9, 67) <= sub_wire8(67); + sub_wire2(9, 68) <= sub_wire8(68); + sub_wire2(9, 69) <= sub_wire8(69); + sub_wire2(9, 70) <= sub_wire8(70); + sub_wire2(9, 71) <= sub_wire8(71); + sub_wire2(9, 72) <= sub_wire8(72); + sub_wire2(9, 73) <= sub_wire8(73); + sub_wire2(9, 74) <= sub_wire8(74); + sub_wire2(9, 75) <= sub_wire8(75); + sub_wire2(9, 76) <= sub_wire8(76); + sub_wire2(9, 77) <= sub_wire8(77); + sub_wire2(9, 78) <= sub_wire8(78); + sub_wire2(9, 79) <= sub_wire8(79); + sub_wire2(9, 80) <= sub_wire8(80); + sub_wire2(9, 81) <= sub_wire8(81); + sub_wire2(9, 82) <= sub_wire8(82); + sub_wire2(9, 83) <= sub_wire8(83); + sub_wire2(9, 84) <= sub_wire8(84); + sub_wire2(9, 85) <= sub_wire8(85); + sub_wire2(9, 86) <= sub_wire8(86); + sub_wire2(9, 87) <= sub_wire8(87); + sub_wire2(9, 88) <= sub_wire8(88); + sub_wire2(9, 89) <= sub_wire8(89); + sub_wire2(9, 90) <= sub_wire8(90); + sub_wire2(9, 91) <= sub_wire8(91); + sub_wire2(9, 92) <= sub_wire8(92); + sub_wire2(9, 93) <= sub_wire8(93); + sub_wire2(9, 94) <= sub_wire8(94); + sub_wire2(9, 95) <= sub_wire8(95); + sub_wire2(9, 96) <= sub_wire8(96); + sub_wire2(9, 97) <= sub_wire8(97); + sub_wire2(9, 98) <= sub_wire8(98); + sub_wire2(9, 99) <= sub_wire8(99); + sub_wire2(9, 100) <= sub_wire8(100); + sub_wire2(9, 101) <= sub_wire8(101); + sub_wire2(9, 102) <= sub_wire8(102); + sub_wire2(9, 103) <= sub_wire8(103); + sub_wire2(9, 104) <= sub_wire8(104); + sub_wire2(9, 105) <= sub_wire8(105); + sub_wire2(9, 106) <= sub_wire8(106); + sub_wire2(9, 107) <= sub_wire8(107); + sub_wire2(9, 108) <= sub_wire8(108); + sub_wire2(9, 109) <= sub_wire8(109); + sub_wire2(9, 110) <= sub_wire8(110); + sub_wire2(9, 111) <= sub_wire8(111); + sub_wire2(9, 112) <= sub_wire8(112); + sub_wire2(9, 113) <= sub_wire8(113); + sub_wire2(9, 114) <= sub_wire8(114); + sub_wire2(9, 115) <= sub_wire8(115); + sub_wire2(9, 116) <= sub_wire8(116); + sub_wire2(9, 117) <= sub_wire8(117); + sub_wire2(9, 118) <= sub_wire8(118); + sub_wire2(9, 119) <= sub_wire8(119); + sub_wire2(9, 120) <= sub_wire8(120); + sub_wire2(9, 121) <= sub_wire8(121); + sub_wire2(9, 122) <= sub_wire8(122); + sub_wire2(9, 123) <= sub_wire8(123); + sub_wire2(9, 124) <= sub_wire8(124); + sub_wire2(9, 125) <= sub_wire8(125); + sub_wire2(9, 126) <= sub_wire8(126); + sub_wire2(9, 127) <= sub_wire8(127); + sub_wire2(8, 0) <= sub_wire9(0); + sub_wire2(8, 1) <= sub_wire9(1); + sub_wire2(8, 2) <= sub_wire9(2); + sub_wire2(8, 3) <= sub_wire9(3); + sub_wire2(8, 4) <= sub_wire9(4); + sub_wire2(8, 5) <= sub_wire9(5); + sub_wire2(8, 6) <= sub_wire9(6); + sub_wire2(8, 7) <= sub_wire9(7); + sub_wire2(8, 8) <= sub_wire9(8); + sub_wire2(8, 9) <= sub_wire9(9); + sub_wire2(8, 10) <= sub_wire9(10); + sub_wire2(8, 11) <= sub_wire9(11); + sub_wire2(8, 12) <= sub_wire9(12); + sub_wire2(8, 13) <= sub_wire9(13); + sub_wire2(8, 14) <= sub_wire9(14); + sub_wire2(8, 15) <= sub_wire9(15); + sub_wire2(8, 16) <= sub_wire9(16); + sub_wire2(8, 17) <= sub_wire9(17); + sub_wire2(8, 18) <= sub_wire9(18); + sub_wire2(8, 19) <= sub_wire9(19); + sub_wire2(8, 20) <= sub_wire9(20); + sub_wire2(8, 21) <= sub_wire9(21); + sub_wire2(8, 22) <= sub_wire9(22); + sub_wire2(8, 23) <= sub_wire9(23); + sub_wire2(8, 24) <= sub_wire9(24); + sub_wire2(8, 25) <= sub_wire9(25); + sub_wire2(8, 26) <= sub_wire9(26); + sub_wire2(8, 27) <= sub_wire9(27); + sub_wire2(8, 28) <= sub_wire9(28); + sub_wire2(8, 29) <= sub_wire9(29); + sub_wire2(8, 30) <= sub_wire9(30); + sub_wire2(8, 31) <= sub_wire9(31); + sub_wire2(8, 32) <= sub_wire9(32); + sub_wire2(8, 33) <= sub_wire9(33); + sub_wire2(8, 34) <= sub_wire9(34); + sub_wire2(8, 35) <= sub_wire9(35); + sub_wire2(8, 36) <= sub_wire9(36); + sub_wire2(8, 37) <= sub_wire9(37); + sub_wire2(8, 38) <= sub_wire9(38); + sub_wire2(8, 39) <= sub_wire9(39); + sub_wire2(8, 40) <= sub_wire9(40); + sub_wire2(8, 41) <= sub_wire9(41); + sub_wire2(8, 42) <= sub_wire9(42); + sub_wire2(8, 43) <= sub_wire9(43); + sub_wire2(8, 44) <= sub_wire9(44); + sub_wire2(8, 45) <= sub_wire9(45); + sub_wire2(8, 46) <= sub_wire9(46); + sub_wire2(8, 47) <= sub_wire9(47); + sub_wire2(8, 48) <= sub_wire9(48); + sub_wire2(8, 49) <= sub_wire9(49); + sub_wire2(8, 50) <= sub_wire9(50); + sub_wire2(8, 51) <= sub_wire9(51); + sub_wire2(8, 52) <= sub_wire9(52); + sub_wire2(8, 53) <= sub_wire9(53); + sub_wire2(8, 54) <= sub_wire9(54); + sub_wire2(8, 55) <= sub_wire9(55); + sub_wire2(8, 56) <= sub_wire9(56); + sub_wire2(8, 57) <= sub_wire9(57); + sub_wire2(8, 58) <= sub_wire9(58); + sub_wire2(8, 59) <= sub_wire9(59); + sub_wire2(8, 60) <= sub_wire9(60); + sub_wire2(8, 61) <= sub_wire9(61); + sub_wire2(8, 62) <= sub_wire9(62); + sub_wire2(8, 63) <= sub_wire9(63); + sub_wire2(8, 64) <= sub_wire9(64); + sub_wire2(8, 65) <= sub_wire9(65); + sub_wire2(8, 66) <= sub_wire9(66); + sub_wire2(8, 67) <= sub_wire9(67); + sub_wire2(8, 68) <= sub_wire9(68); + sub_wire2(8, 69) <= sub_wire9(69); + sub_wire2(8, 70) <= sub_wire9(70); + sub_wire2(8, 71) <= sub_wire9(71); + sub_wire2(8, 72) <= sub_wire9(72); + sub_wire2(8, 73) <= sub_wire9(73); + sub_wire2(8, 74) <= sub_wire9(74); + sub_wire2(8, 75) <= sub_wire9(75); + sub_wire2(8, 76) <= sub_wire9(76); + sub_wire2(8, 77) <= sub_wire9(77); + sub_wire2(8, 78) <= sub_wire9(78); + sub_wire2(8, 79) <= sub_wire9(79); + sub_wire2(8, 80) <= sub_wire9(80); + sub_wire2(8, 81) <= sub_wire9(81); + sub_wire2(8, 82) <= sub_wire9(82); + sub_wire2(8, 83) <= sub_wire9(83); + sub_wire2(8, 84) <= sub_wire9(84); + sub_wire2(8, 85) <= sub_wire9(85); + sub_wire2(8, 86) <= sub_wire9(86); + sub_wire2(8, 87) <= sub_wire9(87); + sub_wire2(8, 88) <= sub_wire9(88); + sub_wire2(8, 89) <= sub_wire9(89); + sub_wire2(8, 90) <= sub_wire9(90); + sub_wire2(8, 91) <= sub_wire9(91); + sub_wire2(8, 92) <= sub_wire9(92); + sub_wire2(8, 93) <= sub_wire9(93); + sub_wire2(8, 94) <= sub_wire9(94); + sub_wire2(8, 95) <= sub_wire9(95); + sub_wire2(8, 96) <= sub_wire9(96); + sub_wire2(8, 97) <= sub_wire9(97); + sub_wire2(8, 98) <= sub_wire9(98); + sub_wire2(8, 99) <= sub_wire9(99); + sub_wire2(8, 100) <= sub_wire9(100); + sub_wire2(8, 101) <= sub_wire9(101); + sub_wire2(8, 102) <= sub_wire9(102); + sub_wire2(8, 103) <= sub_wire9(103); + sub_wire2(8, 104) <= sub_wire9(104); + sub_wire2(8, 105) <= sub_wire9(105); + sub_wire2(8, 106) <= sub_wire9(106); + sub_wire2(8, 107) <= sub_wire9(107); + sub_wire2(8, 108) <= sub_wire9(108); + sub_wire2(8, 109) <= sub_wire9(109); + sub_wire2(8, 110) <= sub_wire9(110); + sub_wire2(8, 111) <= sub_wire9(111); + sub_wire2(8, 112) <= sub_wire9(112); + sub_wire2(8, 113) <= sub_wire9(113); + sub_wire2(8, 114) <= sub_wire9(114); + sub_wire2(8, 115) <= sub_wire9(115); + sub_wire2(8, 116) <= sub_wire9(116); + sub_wire2(8, 117) <= sub_wire9(117); + sub_wire2(8, 118) <= sub_wire9(118); + sub_wire2(8, 119) <= sub_wire9(119); + sub_wire2(8, 120) <= sub_wire9(120); + sub_wire2(8, 121) <= sub_wire9(121); + sub_wire2(8, 122) <= sub_wire9(122); + sub_wire2(8, 123) <= sub_wire9(123); + sub_wire2(8, 124) <= sub_wire9(124); + sub_wire2(8, 125) <= sub_wire9(125); + sub_wire2(8, 126) <= sub_wire9(126); + sub_wire2(8, 127) <= sub_wire9(127); + sub_wire2(7, 0) <= sub_wire10(0); + sub_wire2(7, 1) <= sub_wire10(1); + sub_wire2(7, 2) <= sub_wire10(2); + sub_wire2(7, 3) <= sub_wire10(3); + sub_wire2(7, 4) <= sub_wire10(4); + sub_wire2(7, 5) <= sub_wire10(5); + sub_wire2(7, 6) <= sub_wire10(6); + sub_wire2(7, 7) <= sub_wire10(7); + sub_wire2(7, 8) <= sub_wire10(8); + sub_wire2(7, 9) <= sub_wire10(9); + sub_wire2(7, 10) <= sub_wire10(10); + sub_wire2(7, 11) <= sub_wire10(11); + sub_wire2(7, 12) <= sub_wire10(12); + sub_wire2(7, 13) <= sub_wire10(13); + sub_wire2(7, 14) <= sub_wire10(14); + sub_wire2(7, 15) <= sub_wire10(15); + sub_wire2(7, 16) <= sub_wire10(16); + sub_wire2(7, 17) <= sub_wire10(17); + sub_wire2(7, 18) <= sub_wire10(18); + sub_wire2(7, 19) <= sub_wire10(19); + sub_wire2(7, 20) <= sub_wire10(20); + sub_wire2(7, 21) <= sub_wire10(21); + sub_wire2(7, 22) <= sub_wire10(22); + sub_wire2(7, 23) <= sub_wire10(23); + sub_wire2(7, 24) <= sub_wire10(24); + sub_wire2(7, 25) <= sub_wire10(25); + sub_wire2(7, 26) <= sub_wire10(26); + sub_wire2(7, 27) <= sub_wire10(27); + sub_wire2(7, 28) <= sub_wire10(28); + sub_wire2(7, 29) <= sub_wire10(29); + sub_wire2(7, 30) <= sub_wire10(30); + sub_wire2(7, 31) <= sub_wire10(31); + sub_wire2(7, 32) <= sub_wire10(32); + sub_wire2(7, 33) <= sub_wire10(33); + sub_wire2(7, 34) <= sub_wire10(34); + sub_wire2(7, 35) <= sub_wire10(35); + sub_wire2(7, 36) <= sub_wire10(36); + sub_wire2(7, 37) <= sub_wire10(37); + sub_wire2(7, 38) <= sub_wire10(38); + sub_wire2(7, 39) <= sub_wire10(39); + sub_wire2(7, 40) <= sub_wire10(40); + sub_wire2(7, 41) <= sub_wire10(41); + sub_wire2(7, 42) <= sub_wire10(42); + sub_wire2(7, 43) <= sub_wire10(43); + sub_wire2(7, 44) <= sub_wire10(44); + sub_wire2(7, 45) <= sub_wire10(45); + sub_wire2(7, 46) <= sub_wire10(46); + sub_wire2(7, 47) <= sub_wire10(47); + sub_wire2(7, 48) <= sub_wire10(48); + sub_wire2(7, 49) <= sub_wire10(49); + sub_wire2(7, 50) <= sub_wire10(50); + sub_wire2(7, 51) <= sub_wire10(51); + sub_wire2(7, 52) <= sub_wire10(52); + sub_wire2(7, 53) <= sub_wire10(53); + sub_wire2(7, 54) <= sub_wire10(54); + sub_wire2(7, 55) <= sub_wire10(55); + sub_wire2(7, 56) <= sub_wire10(56); + sub_wire2(7, 57) <= sub_wire10(57); + sub_wire2(7, 58) <= sub_wire10(58); + sub_wire2(7, 59) <= sub_wire10(59); + sub_wire2(7, 60) <= sub_wire10(60); + sub_wire2(7, 61) <= sub_wire10(61); + sub_wire2(7, 62) <= sub_wire10(62); + sub_wire2(7, 63) <= sub_wire10(63); + sub_wire2(7, 64) <= sub_wire10(64); + sub_wire2(7, 65) <= sub_wire10(65); + sub_wire2(7, 66) <= sub_wire10(66); + sub_wire2(7, 67) <= sub_wire10(67); + sub_wire2(7, 68) <= sub_wire10(68); + sub_wire2(7, 69) <= sub_wire10(69); + sub_wire2(7, 70) <= sub_wire10(70); + sub_wire2(7, 71) <= sub_wire10(71); + sub_wire2(7, 72) <= sub_wire10(72); + sub_wire2(7, 73) <= sub_wire10(73); + sub_wire2(7, 74) <= sub_wire10(74); + sub_wire2(7, 75) <= sub_wire10(75); + sub_wire2(7, 76) <= sub_wire10(76); + sub_wire2(7, 77) <= sub_wire10(77); + sub_wire2(7, 78) <= sub_wire10(78); + sub_wire2(7, 79) <= sub_wire10(79); + sub_wire2(7, 80) <= sub_wire10(80); + sub_wire2(7, 81) <= sub_wire10(81); + sub_wire2(7, 82) <= sub_wire10(82); + sub_wire2(7, 83) <= sub_wire10(83); + sub_wire2(7, 84) <= sub_wire10(84); + sub_wire2(7, 85) <= sub_wire10(85); + sub_wire2(7, 86) <= sub_wire10(86); + sub_wire2(7, 87) <= sub_wire10(87); + sub_wire2(7, 88) <= sub_wire10(88); + sub_wire2(7, 89) <= sub_wire10(89); + sub_wire2(7, 90) <= sub_wire10(90); + sub_wire2(7, 91) <= sub_wire10(91); + sub_wire2(7, 92) <= sub_wire10(92); + sub_wire2(7, 93) <= sub_wire10(93); + sub_wire2(7, 94) <= sub_wire10(94); + sub_wire2(7, 95) <= sub_wire10(95); + sub_wire2(7, 96) <= sub_wire10(96); + sub_wire2(7, 97) <= sub_wire10(97); + sub_wire2(7, 98) <= sub_wire10(98); + sub_wire2(7, 99) <= sub_wire10(99); + sub_wire2(7, 100) <= sub_wire10(100); + sub_wire2(7, 101) <= sub_wire10(101); + sub_wire2(7, 102) <= sub_wire10(102); + sub_wire2(7, 103) <= sub_wire10(103); + sub_wire2(7, 104) <= sub_wire10(104); + sub_wire2(7, 105) <= sub_wire10(105); + sub_wire2(7, 106) <= sub_wire10(106); + sub_wire2(7, 107) <= sub_wire10(107); + sub_wire2(7, 108) <= sub_wire10(108); + sub_wire2(7, 109) <= sub_wire10(109); + sub_wire2(7, 110) <= sub_wire10(110); + sub_wire2(7, 111) <= sub_wire10(111); + sub_wire2(7, 112) <= sub_wire10(112); + sub_wire2(7, 113) <= sub_wire10(113); + sub_wire2(7, 114) <= sub_wire10(114); + sub_wire2(7, 115) <= sub_wire10(115); + sub_wire2(7, 116) <= sub_wire10(116); + sub_wire2(7, 117) <= sub_wire10(117); + sub_wire2(7, 118) <= sub_wire10(118); + sub_wire2(7, 119) <= sub_wire10(119); + sub_wire2(7, 120) <= sub_wire10(120); + sub_wire2(7, 121) <= sub_wire10(121); + sub_wire2(7, 122) <= sub_wire10(122); + sub_wire2(7, 123) <= sub_wire10(123); + sub_wire2(7, 124) <= sub_wire10(124); + sub_wire2(7, 125) <= sub_wire10(125); + sub_wire2(7, 126) <= sub_wire10(126); + sub_wire2(7, 127) <= sub_wire10(127); + sub_wire2(6, 0) <= sub_wire11(0); + sub_wire2(6, 1) <= sub_wire11(1); + sub_wire2(6, 2) <= sub_wire11(2); + sub_wire2(6, 3) <= sub_wire11(3); + sub_wire2(6, 4) <= sub_wire11(4); + sub_wire2(6, 5) <= sub_wire11(5); + sub_wire2(6, 6) <= sub_wire11(6); + sub_wire2(6, 7) <= sub_wire11(7); + sub_wire2(6, 8) <= sub_wire11(8); + sub_wire2(6, 9) <= sub_wire11(9); + sub_wire2(6, 10) <= sub_wire11(10); + sub_wire2(6, 11) <= sub_wire11(11); + sub_wire2(6, 12) <= sub_wire11(12); + sub_wire2(6, 13) <= sub_wire11(13); + sub_wire2(6, 14) <= sub_wire11(14); + sub_wire2(6, 15) <= sub_wire11(15); + sub_wire2(6, 16) <= sub_wire11(16); + sub_wire2(6, 17) <= sub_wire11(17); + sub_wire2(6, 18) <= sub_wire11(18); + sub_wire2(6, 19) <= sub_wire11(19); + sub_wire2(6, 20) <= sub_wire11(20); + sub_wire2(6, 21) <= sub_wire11(21); + sub_wire2(6, 22) <= sub_wire11(22); + sub_wire2(6, 23) <= sub_wire11(23); + sub_wire2(6, 24) <= sub_wire11(24); + sub_wire2(6, 25) <= sub_wire11(25); + sub_wire2(6, 26) <= sub_wire11(26); + sub_wire2(6, 27) <= sub_wire11(27); + sub_wire2(6, 28) <= sub_wire11(28); + sub_wire2(6, 29) <= sub_wire11(29); + sub_wire2(6, 30) <= sub_wire11(30); + sub_wire2(6, 31) <= sub_wire11(31); + sub_wire2(6, 32) <= sub_wire11(32); + sub_wire2(6, 33) <= sub_wire11(33); + sub_wire2(6, 34) <= sub_wire11(34); + sub_wire2(6, 35) <= sub_wire11(35); + sub_wire2(6, 36) <= sub_wire11(36); + sub_wire2(6, 37) <= sub_wire11(37); + sub_wire2(6, 38) <= sub_wire11(38); + sub_wire2(6, 39) <= sub_wire11(39); + sub_wire2(6, 40) <= sub_wire11(40); + sub_wire2(6, 41) <= sub_wire11(41); + sub_wire2(6, 42) <= sub_wire11(42); + sub_wire2(6, 43) <= sub_wire11(43); + sub_wire2(6, 44) <= sub_wire11(44); + sub_wire2(6, 45) <= sub_wire11(45); + sub_wire2(6, 46) <= sub_wire11(46); + sub_wire2(6, 47) <= sub_wire11(47); + sub_wire2(6, 48) <= sub_wire11(48); + sub_wire2(6, 49) <= sub_wire11(49); + sub_wire2(6, 50) <= sub_wire11(50); + sub_wire2(6, 51) <= sub_wire11(51); + sub_wire2(6, 52) <= sub_wire11(52); + sub_wire2(6, 53) <= sub_wire11(53); + sub_wire2(6, 54) <= sub_wire11(54); + sub_wire2(6, 55) <= sub_wire11(55); + sub_wire2(6, 56) <= sub_wire11(56); + sub_wire2(6, 57) <= sub_wire11(57); + sub_wire2(6, 58) <= sub_wire11(58); + sub_wire2(6, 59) <= sub_wire11(59); + sub_wire2(6, 60) <= sub_wire11(60); + sub_wire2(6, 61) <= sub_wire11(61); + sub_wire2(6, 62) <= sub_wire11(62); + sub_wire2(6, 63) <= sub_wire11(63); + sub_wire2(6, 64) <= sub_wire11(64); + sub_wire2(6, 65) <= sub_wire11(65); + sub_wire2(6, 66) <= sub_wire11(66); + sub_wire2(6, 67) <= sub_wire11(67); + sub_wire2(6, 68) <= sub_wire11(68); + sub_wire2(6, 69) <= sub_wire11(69); + sub_wire2(6, 70) <= sub_wire11(70); + sub_wire2(6, 71) <= sub_wire11(71); + sub_wire2(6, 72) <= sub_wire11(72); + sub_wire2(6, 73) <= sub_wire11(73); + sub_wire2(6, 74) <= sub_wire11(74); + sub_wire2(6, 75) <= sub_wire11(75); + sub_wire2(6, 76) <= sub_wire11(76); + sub_wire2(6, 77) <= sub_wire11(77); + sub_wire2(6, 78) <= sub_wire11(78); + sub_wire2(6, 79) <= sub_wire11(79); + sub_wire2(6, 80) <= sub_wire11(80); + sub_wire2(6, 81) <= sub_wire11(81); + sub_wire2(6, 82) <= sub_wire11(82); + sub_wire2(6, 83) <= sub_wire11(83); + sub_wire2(6, 84) <= sub_wire11(84); + sub_wire2(6, 85) <= sub_wire11(85); + sub_wire2(6, 86) <= sub_wire11(86); + sub_wire2(6, 87) <= sub_wire11(87); + sub_wire2(6, 88) <= sub_wire11(88); + sub_wire2(6, 89) <= sub_wire11(89); + sub_wire2(6, 90) <= sub_wire11(90); + sub_wire2(6, 91) <= sub_wire11(91); + sub_wire2(6, 92) <= sub_wire11(92); + sub_wire2(6, 93) <= sub_wire11(93); + sub_wire2(6, 94) <= sub_wire11(94); + sub_wire2(6, 95) <= sub_wire11(95); + sub_wire2(6, 96) <= sub_wire11(96); + sub_wire2(6, 97) <= sub_wire11(97); + sub_wire2(6, 98) <= sub_wire11(98); + sub_wire2(6, 99) <= sub_wire11(99); + sub_wire2(6, 100) <= sub_wire11(100); + sub_wire2(6, 101) <= sub_wire11(101); + sub_wire2(6, 102) <= sub_wire11(102); + sub_wire2(6, 103) <= sub_wire11(103); + sub_wire2(6, 104) <= sub_wire11(104); + sub_wire2(6, 105) <= sub_wire11(105); + sub_wire2(6, 106) <= sub_wire11(106); + sub_wire2(6, 107) <= sub_wire11(107); + sub_wire2(6, 108) <= sub_wire11(108); + sub_wire2(6, 109) <= sub_wire11(109); + sub_wire2(6, 110) <= sub_wire11(110); + sub_wire2(6, 111) <= sub_wire11(111); + sub_wire2(6, 112) <= sub_wire11(112); + sub_wire2(6, 113) <= sub_wire11(113); + sub_wire2(6, 114) <= sub_wire11(114); + sub_wire2(6, 115) <= sub_wire11(115); + sub_wire2(6, 116) <= sub_wire11(116); + sub_wire2(6, 117) <= sub_wire11(117); + sub_wire2(6, 118) <= sub_wire11(118); + sub_wire2(6, 119) <= sub_wire11(119); + sub_wire2(6, 120) <= sub_wire11(120); + sub_wire2(6, 121) <= sub_wire11(121); + sub_wire2(6, 122) <= sub_wire11(122); + sub_wire2(6, 123) <= sub_wire11(123); + sub_wire2(6, 124) <= sub_wire11(124); + sub_wire2(6, 125) <= sub_wire11(125); + sub_wire2(6, 126) <= sub_wire11(126); + sub_wire2(6, 127) <= sub_wire11(127); + sub_wire2(5, 0) <= sub_wire12(0); + sub_wire2(5, 1) <= sub_wire12(1); + sub_wire2(5, 2) <= sub_wire12(2); + sub_wire2(5, 3) <= sub_wire12(3); + sub_wire2(5, 4) <= sub_wire12(4); + sub_wire2(5, 5) <= sub_wire12(5); + sub_wire2(5, 6) <= sub_wire12(6); + sub_wire2(5, 7) <= sub_wire12(7); + sub_wire2(5, 8) <= sub_wire12(8); + sub_wire2(5, 9) <= sub_wire12(9); + sub_wire2(5, 10) <= sub_wire12(10); + sub_wire2(5, 11) <= sub_wire12(11); + sub_wire2(5, 12) <= sub_wire12(12); + sub_wire2(5, 13) <= sub_wire12(13); + sub_wire2(5, 14) <= sub_wire12(14); + sub_wire2(5, 15) <= sub_wire12(15); + sub_wire2(5, 16) <= sub_wire12(16); + sub_wire2(5, 17) <= sub_wire12(17); + sub_wire2(5, 18) <= sub_wire12(18); + sub_wire2(5, 19) <= sub_wire12(19); + sub_wire2(5, 20) <= sub_wire12(20); + sub_wire2(5, 21) <= sub_wire12(21); + sub_wire2(5, 22) <= sub_wire12(22); + sub_wire2(5, 23) <= sub_wire12(23); + sub_wire2(5, 24) <= sub_wire12(24); + sub_wire2(5, 25) <= sub_wire12(25); + sub_wire2(5, 26) <= sub_wire12(26); + sub_wire2(5, 27) <= sub_wire12(27); + sub_wire2(5, 28) <= sub_wire12(28); + sub_wire2(5, 29) <= sub_wire12(29); + sub_wire2(5, 30) <= sub_wire12(30); + sub_wire2(5, 31) <= sub_wire12(31); + sub_wire2(5, 32) <= sub_wire12(32); + sub_wire2(5, 33) <= sub_wire12(33); + sub_wire2(5, 34) <= sub_wire12(34); + sub_wire2(5, 35) <= sub_wire12(35); + sub_wire2(5, 36) <= sub_wire12(36); + sub_wire2(5, 37) <= sub_wire12(37); + sub_wire2(5, 38) <= sub_wire12(38); + sub_wire2(5, 39) <= sub_wire12(39); + sub_wire2(5, 40) <= sub_wire12(40); + sub_wire2(5, 41) <= sub_wire12(41); + sub_wire2(5, 42) <= sub_wire12(42); + sub_wire2(5, 43) <= sub_wire12(43); + sub_wire2(5, 44) <= sub_wire12(44); + sub_wire2(5, 45) <= sub_wire12(45); + sub_wire2(5, 46) <= sub_wire12(46); + sub_wire2(5, 47) <= sub_wire12(47); + sub_wire2(5, 48) <= sub_wire12(48); + sub_wire2(5, 49) <= sub_wire12(49); + sub_wire2(5, 50) <= sub_wire12(50); + sub_wire2(5, 51) <= sub_wire12(51); + sub_wire2(5, 52) <= sub_wire12(52); + sub_wire2(5, 53) <= sub_wire12(53); + sub_wire2(5, 54) <= sub_wire12(54); + sub_wire2(5, 55) <= sub_wire12(55); + sub_wire2(5, 56) <= sub_wire12(56); + sub_wire2(5, 57) <= sub_wire12(57); + sub_wire2(5, 58) <= sub_wire12(58); + sub_wire2(5, 59) <= sub_wire12(59); + sub_wire2(5, 60) <= sub_wire12(60); + sub_wire2(5, 61) <= sub_wire12(61); + sub_wire2(5, 62) <= sub_wire12(62); + sub_wire2(5, 63) <= sub_wire12(63); + sub_wire2(5, 64) <= sub_wire12(64); + sub_wire2(5, 65) <= sub_wire12(65); + sub_wire2(5, 66) <= sub_wire12(66); + sub_wire2(5, 67) <= sub_wire12(67); + sub_wire2(5, 68) <= sub_wire12(68); + sub_wire2(5, 69) <= sub_wire12(69); + sub_wire2(5, 70) <= sub_wire12(70); + sub_wire2(5, 71) <= sub_wire12(71); + sub_wire2(5, 72) <= sub_wire12(72); + sub_wire2(5, 73) <= sub_wire12(73); + sub_wire2(5, 74) <= sub_wire12(74); + sub_wire2(5, 75) <= sub_wire12(75); + sub_wire2(5, 76) <= sub_wire12(76); + sub_wire2(5, 77) <= sub_wire12(77); + sub_wire2(5, 78) <= sub_wire12(78); + sub_wire2(5, 79) <= sub_wire12(79); + sub_wire2(5, 80) <= sub_wire12(80); + sub_wire2(5, 81) <= sub_wire12(81); + sub_wire2(5, 82) <= sub_wire12(82); + sub_wire2(5, 83) <= sub_wire12(83); + sub_wire2(5, 84) <= sub_wire12(84); + sub_wire2(5, 85) <= sub_wire12(85); + sub_wire2(5, 86) <= sub_wire12(86); + sub_wire2(5, 87) <= sub_wire12(87); + sub_wire2(5, 88) <= sub_wire12(88); + sub_wire2(5, 89) <= sub_wire12(89); + sub_wire2(5, 90) <= sub_wire12(90); + sub_wire2(5, 91) <= sub_wire12(91); + sub_wire2(5, 92) <= sub_wire12(92); + sub_wire2(5, 93) <= sub_wire12(93); + sub_wire2(5, 94) <= sub_wire12(94); + sub_wire2(5, 95) <= sub_wire12(95); + sub_wire2(5, 96) <= sub_wire12(96); + sub_wire2(5, 97) <= sub_wire12(97); + sub_wire2(5, 98) <= sub_wire12(98); + sub_wire2(5, 99) <= sub_wire12(99); + sub_wire2(5, 100) <= sub_wire12(100); + sub_wire2(5, 101) <= sub_wire12(101); + sub_wire2(5, 102) <= sub_wire12(102); + sub_wire2(5, 103) <= sub_wire12(103); + sub_wire2(5, 104) <= sub_wire12(104); + sub_wire2(5, 105) <= sub_wire12(105); + sub_wire2(5, 106) <= sub_wire12(106); + sub_wire2(5, 107) <= sub_wire12(107); + sub_wire2(5, 108) <= sub_wire12(108); + sub_wire2(5, 109) <= sub_wire12(109); + sub_wire2(5, 110) <= sub_wire12(110); + sub_wire2(5, 111) <= sub_wire12(111); + sub_wire2(5, 112) <= sub_wire12(112); + sub_wire2(5, 113) <= sub_wire12(113); + sub_wire2(5, 114) <= sub_wire12(114); + sub_wire2(5, 115) <= sub_wire12(115); + sub_wire2(5, 116) <= sub_wire12(116); + sub_wire2(5, 117) <= sub_wire12(117); + sub_wire2(5, 118) <= sub_wire12(118); + sub_wire2(5, 119) <= sub_wire12(119); + sub_wire2(5, 120) <= sub_wire12(120); + sub_wire2(5, 121) <= sub_wire12(121); + sub_wire2(5, 122) <= sub_wire12(122); + sub_wire2(5, 123) <= sub_wire12(123); + sub_wire2(5, 124) <= sub_wire12(124); + sub_wire2(5, 125) <= sub_wire12(125); + sub_wire2(5, 126) <= sub_wire12(126); + sub_wire2(5, 127) <= sub_wire12(127); + sub_wire2(4, 0) <= sub_wire13(0); + sub_wire2(4, 1) <= sub_wire13(1); + sub_wire2(4, 2) <= sub_wire13(2); + sub_wire2(4, 3) <= sub_wire13(3); + sub_wire2(4, 4) <= sub_wire13(4); + sub_wire2(4, 5) <= sub_wire13(5); + sub_wire2(4, 6) <= sub_wire13(6); + sub_wire2(4, 7) <= sub_wire13(7); + sub_wire2(4, 8) <= sub_wire13(8); + sub_wire2(4, 9) <= sub_wire13(9); + sub_wire2(4, 10) <= sub_wire13(10); + sub_wire2(4, 11) <= sub_wire13(11); + sub_wire2(4, 12) <= sub_wire13(12); + sub_wire2(4, 13) <= sub_wire13(13); + sub_wire2(4, 14) <= sub_wire13(14); + sub_wire2(4, 15) <= sub_wire13(15); + sub_wire2(4, 16) <= sub_wire13(16); + sub_wire2(4, 17) <= sub_wire13(17); + sub_wire2(4, 18) <= sub_wire13(18); + sub_wire2(4, 19) <= sub_wire13(19); + sub_wire2(4, 20) <= sub_wire13(20); + sub_wire2(4, 21) <= sub_wire13(21); + sub_wire2(4, 22) <= sub_wire13(22); + sub_wire2(4, 23) <= sub_wire13(23); + sub_wire2(4, 24) <= sub_wire13(24); + sub_wire2(4, 25) <= sub_wire13(25); + sub_wire2(4, 26) <= sub_wire13(26); + sub_wire2(4, 27) <= sub_wire13(27); + sub_wire2(4, 28) <= sub_wire13(28); + sub_wire2(4, 29) <= sub_wire13(29); + sub_wire2(4, 30) <= sub_wire13(30); + sub_wire2(4, 31) <= sub_wire13(31); + sub_wire2(4, 32) <= sub_wire13(32); + sub_wire2(4, 33) <= sub_wire13(33); + sub_wire2(4, 34) <= sub_wire13(34); + sub_wire2(4, 35) <= sub_wire13(35); + sub_wire2(4, 36) <= sub_wire13(36); + sub_wire2(4, 37) <= sub_wire13(37); + sub_wire2(4, 38) <= sub_wire13(38); + sub_wire2(4, 39) <= sub_wire13(39); + sub_wire2(4, 40) <= sub_wire13(40); + sub_wire2(4, 41) <= sub_wire13(41); + sub_wire2(4, 42) <= sub_wire13(42); + sub_wire2(4, 43) <= sub_wire13(43); + sub_wire2(4, 44) <= sub_wire13(44); + sub_wire2(4, 45) <= sub_wire13(45); + sub_wire2(4, 46) <= sub_wire13(46); + sub_wire2(4, 47) <= sub_wire13(47); + sub_wire2(4, 48) <= sub_wire13(48); + sub_wire2(4, 49) <= sub_wire13(49); + sub_wire2(4, 50) <= sub_wire13(50); + sub_wire2(4, 51) <= sub_wire13(51); + sub_wire2(4, 52) <= sub_wire13(52); + sub_wire2(4, 53) <= sub_wire13(53); + sub_wire2(4, 54) <= sub_wire13(54); + sub_wire2(4, 55) <= sub_wire13(55); + sub_wire2(4, 56) <= sub_wire13(56); + sub_wire2(4, 57) <= sub_wire13(57); + sub_wire2(4, 58) <= sub_wire13(58); + sub_wire2(4, 59) <= sub_wire13(59); + sub_wire2(4, 60) <= sub_wire13(60); + sub_wire2(4, 61) <= sub_wire13(61); + sub_wire2(4, 62) <= sub_wire13(62); + sub_wire2(4, 63) <= sub_wire13(63); + sub_wire2(4, 64) <= sub_wire13(64); + sub_wire2(4, 65) <= sub_wire13(65); + sub_wire2(4, 66) <= sub_wire13(66); + sub_wire2(4, 67) <= sub_wire13(67); + sub_wire2(4, 68) <= sub_wire13(68); + sub_wire2(4, 69) <= sub_wire13(69); + sub_wire2(4, 70) <= sub_wire13(70); + sub_wire2(4, 71) <= sub_wire13(71); + sub_wire2(4, 72) <= sub_wire13(72); + sub_wire2(4, 73) <= sub_wire13(73); + sub_wire2(4, 74) <= sub_wire13(74); + sub_wire2(4, 75) <= sub_wire13(75); + sub_wire2(4, 76) <= sub_wire13(76); + sub_wire2(4, 77) <= sub_wire13(77); + sub_wire2(4, 78) <= sub_wire13(78); + sub_wire2(4, 79) <= sub_wire13(79); + sub_wire2(4, 80) <= sub_wire13(80); + sub_wire2(4, 81) <= sub_wire13(81); + sub_wire2(4, 82) <= sub_wire13(82); + sub_wire2(4, 83) <= sub_wire13(83); + sub_wire2(4, 84) <= sub_wire13(84); + sub_wire2(4, 85) <= sub_wire13(85); + sub_wire2(4, 86) <= sub_wire13(86); + sub_wire2(4, 87) <= sub_wire13(87); + sub_wire2(4, 88) <= sub_wire13(88); + sub_wire2(4, 89) <= sub_wire13(89); + sub_wire2(4, 90) <= sub_wire13(90); + sub_wire2(4, 91) <= sub_wire13(91); + sub_wire2(4, 92) <= sub_wire13(92); + sub_wire2(4, 93) <= sub_wire13(93); + sub_wire2(4, 94) <= sub_wire13(94); + sub_wire2(4, 95) <= sub_wire13(95); + sub_wire2(4, 96) <= sub_wire13(96); + sub_wire2(4, 97) <= sub_wire13(97); + sub_wire2(4, 98) <= sub_wire13(98); + sub_wire2(4, 99) <= sub_wire13(99); + sub_wire2(4, 100) <= sub_wire13(100); + sub_wire2(4, 101) <= sub_wire13(101); + sub_wire2(4, 102) <= sub_wire13(102); + sub_wire2(4, 103) <= sub_wire13(103); + sub_wire2(4, 104) <= sub_wire13(104); + sub_wire2(4, 105) <= sub_wire13(105); + sub_wire2(4, 106) <= sub_wire13(106); + sub_wire2(4, 107) <= sub_wire13(107); + sub_wire2(4, 108) <= sub_wire13(108); + sub_wire2(4, 109) <= sub_wire13(109); + sub_wire2(4, 110) <= sub_wire13(110); + sub_wire2(4, 111) <= sub_wire13(111); + sub_wire2(4, 112) <= sub_wire13(112); + sub_wire2(4, 113) <= sub_wire13(113); + sub_wire2(4, 114) <= sub_wire13(114); + sub_wire2(4, 115) <= sub_wire13(115); + sub_wire2(4, 116) <= sub_wire13(116); + sub_wire2(4, 117) <= sub_wire13(117); + sub_wire2(4, 118) <= sub_wire13(118); + sub_wire2(4, 119) <= sub_wire13(119); + sub_wire2(4, 120) <= sub_wire13(120); + sub_wire2(4, 121) <= sub_wire13(121); + sub_wire2(4, 122) <= sub_wire13(122); + sub_wire2(4, 123) <= sub_wire13(123); + sub_wire2(4, 124) <= sub_wire13(124); + sub_wire2(4, 125) <= sub_wire13(125); + sub_wire2(4, 126) <= sub_wire13(126); + sub_wire2(4, 127) <= sub_wire13(127); + sub_wire2(3, 0) <= sub_wire14(0); + sub_wire2(3, 1) <= sub_wire14(1); + sub_wire2(3, 2) <= sub_wire14(2); + sub_wire2(3, 3) <= sub_wire14(3); + sub_wire2(3, 4) <= sub_wire14(4); + sub_wire2(3, 5) <= sub_wire14(5); + sub_wire2(3, 6) <= sub_wire14(6); + sub_wire2(3, 7) <= sub_wire14(7); + sub_wire2(3, 8) <= sub_wire14(8); + sub_wire2(3, 9) <= sub_wire14(9); + sub_wire2(3, 10) <= sub_wire14(10); + sub_wire2(3, 11) <= sub_wire14(11); + sub_wire2(3, 12) <= sub_wire14(12); + sub_wire2(3, 13) <= sub_wire14(13); + sub_wire2(3, 14) <= sub_wire14(14); + sub_wire2(3, 15) <= sub_wire14(15); + sub_wire2(3, 16) <= sub_wire14(16); + sub_wire2(3, 17) <= sub_wire14(17); + sub_wire2(3, 18) <= sub_wire14(18); + sub_wire2(3, 19) <= sub_wire14(19); + sub_wire2(3, 20) <= sub_wire14(20); + sub_wire2(3, 21) <= sub_wire14(21); + sub_wire2(3, 22) <= sub_wire14(22); + sub_wire2(3, 23) <= sub_wire14(23); + sub_wire2(3, 24) <= sub_wire14(24); + sub_wire2(3, 25) <= sub_wire14(25); + sub_wire2(3, 26) <= sub_wire14(26); + sub_wire2(3, 27) <= sub_wire14(27); + sub_wire2(3, 28) <= sub_wire14(28); + sub_wire2(3, 29) <= sub_wire14(29); + sub_wire2(3, 30) <= sub_wire14(30); + sub_wire2(3, 31) <= sub_wire14(31); + sub_wire2(3, 32) <= sub_wire14(32); + sub_wire2(3, 33) <= sub_wire14(33); + sub_wire2(3, 34) <= sub_wire14(34); + sub_wire2(3, 35) <= sub_wire14(35); + sub_wire2(3, 36) <= sub_wire14(36); + sub_wire2(3, 37) <= sub_wire14(37); + sub_wire2(3, 38) <= sub_wire14(38); + sub_wire2(3, 39) <= sub_wire14(39); + sub_wire2(3, 40) <= sub_wire14(40); + sub_wire2(3, 41) <= sub_wire14(41); + sub_wire2(3, 42) <= sub_wire14(42); + sub_wire2(3, 43) <= sub_wire14(43); + sub_wire2(3, 44) <= sub_wire14(44); + sub_wire2(3, 45) <= sub_wire14(45); + sub_wire2(3, 46) <= sub_wire14(46); + sub_wire2(3, 47) <= sub_wire14(47); + sub_wire2(3, 48) <= sub_wire14(48); + sub_wire2(3, 49) <= sub_wire14(49); + sub_wire2(3, 50) <= sub_wire14(50); + sub_wire2(3, 51) <= sub_wire14(51); + sub_wire2(3, 52) <= sub_wire14(52); + sub_wire2(3, 53) <= sub_wire14(53); + sub_wire2(3, 54) <= sub_wire14(54); + sub_wire2(3, 55) <= sub_wire14(55); + sub_wire2(3, 56) <= sub_wire14(56); + sub_wire2(3, 57) <= sub_wire14(57); + sub_wire2(3, 58) <= sub_wire14(58); + sub_wire2(3, 59) <= sub_wire14(59); + sub_wire2(3, 60) <= sub_wire14(60); + sub_wire2(3, 61) <= sub_wire14(61); + sub_wire2(3, 62) <= sub_wire14(62); + sub_wire2(3, 63) <= sub_wire14(63); + sub_wire2(3, 64) <= sub_wire14(64); + sub_wire2(3, 65) <= sub_wire14(65); + sub_wire2(3, 66) <= sub_wire14(66); + sub_wire2(3, 67) <= sub_wire14(67); + sub_wire2(3, 68) <= sub_wire14(68); + sub_wire2(3, 69) <= sub_wire14(69); + sub_wire2(3, 70) <= sub_wire14(70); + sub_wire2(3, 71) <= sub_wire14(71); + sub_wire2(3, 72) <= sub_wire14(72); + sub_wire2(3, 73) <= sub_wire14(73); + sub_wire2(3, 74) <= sub_wire14(74); + sub_wire2(3, 75) <= sub_wire14(75); + sub_wire2(3, 76) <= sub_wire14(76); + sub_wire2(3, 77) <= sub_wire14(77); + sub_wire2(3, 78) <= sub_wire14(78); + sub_wire2(3, 79) <= sub_wire14(79); + sub_wire2(3, 80) <= sub_wire14(80); + sub_wire2(3, 81) <= sub_wire14(81); + sub_wire2(3, 82) <= sub_wire14(82); + sub_wire2(3, 83) <= sub_wire14(83); + sub_wire2(3, 84) <= sub_wire14(84); + sub_wire2(3, 85) <= sub_wire14(85); + sub_wire2(3, 86) <= sub_wire14(86); + sub_wire2(3, 87) <= sub_wire14(87); + sub_wire2(3, 88) <= sub_wire14(88); + sub_wire2(3, 89) <= sub_wire14(89); + sub_wire2(3, 90) <= sub_wire14(90); + sub_wire2(3, 91) <= sub_wire14(91); + sub_wire2(3, 92) <= sub_wire14(92); + sub_wire2(3, 93) <= sub_wire14(93); + sub_wire2(3, 94) <= sub_wire14(94); + sub_wire2(3, 95) <= sub_wire14(95); + sub_wire2(3, 96) <= sub_wire14(96); + sub_wire2(3, 97) <= sub_wire14(97); + sub_wire2(3, 98) <= sub_wire14(98); + sub_wire2(3, 99) <= sub_wire14(99); + sub_wire2(3, 100) <= sub_wire14(100); + sub_wire2(3, 101) <= sub_wire14(101); + sub_wire2(3, 102) <= sub_wire14(102); + sub_wire2(3, 103) <= sub_wire14(103); + sub_wire2(3, 104) <= sub_wire14(104); + sub_wire2(3, 105) <= sub_wire14(105); + sub_wire2(3, 106) <= sub_wire14(106); + sub_wire2(3, 107) <= sub_wire14(107); + sub_wire2(3, 108) <= sub_wire14(108); + sub_wire2(3, 109) <= sub_wire14(109); + sub_wire2(3, 110) <= sub_wire14(110); + sub_wire2(3, 111) <= sub_wire14(111); + sub_wire2(3, 112) <= sub_wire14(112); + sub_wire2(3, 113) <= sub_wire14(113); + sub_wire2(3, 114) <= sub_wire14(114); + sub_wire2(3, 115) <= sub_wire14(115); + sub_wire2(3, 116) <= sub_wire14(116); + sub_wire2(3, 117) <= sub_wire14(117); + sub_wire2(3, 118) <= sub_wire14(118); + sub_wire2(3, 119) <= sub_wire14(119); + sub_wire2(3, 120) <= sub_wire14(120); + sub_wire2(3, 121) <= sub_wire14(121); + sub_wire2(3, 122) <= sub_wire14(122); + sub_wire2(3, 123) <= sub_wire14(123); + sub_wire2(3, 124) <= sub_wire14(124); + sub_wire2(3, 125) <= sub_wire14(125); + sub_wire2(3, 126) <= sub_wire14(126); + sub_wire2(3, 127) <= sub_wire14(127); + sub_wire2(2, 0) <= sub_wire15(0); + sub_wire2(2, 1) <= sub_wire15(1); + sub_wire2(2, 2) <= sub_wire15(2); + sub_wire2(2, 3) <= sub_wire15(3); + sub_wire2(2, 4) <= sub_wire15(4); + sub_wire2(2, 5) <= sub_wire15(5); + sub_wire2(2, 6) <= sub_wire15(6); + sub_wire2(2, 7) <= sub_wire15(7); + sub_wire2(2, 8) <= sub_wire15(8); + sub_wire2(2, 9) <= sub_wire15(9); + sub_wire2(2, 10) <= sub_wire15(10); + sub_wire2(2, 11) <= sub_wire15(11); + sub_wire2(2, 12) <= sub_wire15(12); + sub_wire2(2, 13) <= sub_wire15(13); + sub_wire2(2, 14) <= sub_wire15(14); + sub_wire2(2, 15) <= sub_wire15(15); + sub_wire2(2, 16) <= sub_wire15(16); + sub_wire2(2, 17) <= sub_wire15(17); + sub_wire2(2, 18) <= sub_wire15(18); + sub_wire2(2, 19) <= sub_wire15(19); + sub_wire2(2, 20) <= sub_wire15(20); + sub_wire2(2, 21) <= sub_wire15(21); + sub_wire2(2, 22) <= sub_wire15(22); + sub_wire2(2, 23) <= sub_wire15(23); + sub_wire2(2, 24) <= sub_wire15(24); + sub_wire2(2, 25) <= sub_wire15(25); + sub_wire2(2, 26) <= sub_wire15(26); + sub_wire2(2, 27) <= sub_wire15(27); + sub_wire2(2, 28) <= sub_wire15(28); + sub_wire2(2, 29) <= sub_wire15(29); + sub_wire2(2, 30) <= sub_wire15(30); + sub_wire2(2, 31) <= sub_wire15(31); + sub_wire2(2, 32) <= sub_wire15(32); + sub_wire2(2, 33) <= sub_wire15(33); + sub_wire2(2, 34) <= sub_wire15(34); + sub_wire2(2, 35) <= sub_wire15(35); + sub_wire2(2, 36) <= sub_wire15(36); + sub_wire2(2, 37) <= sub_wire15(37); + sub_wire2(2, 38) <= sub_wire15(38); + sub_wire2(2, 39) <= sub_wire15(39); + sub_wire2(2, 40) <= sub_wire15(40); + sub_wire2(2, 41) <= sub_wire15(41); + sub_wire2(2, 42) <= sub_wire15(42); + sub_wire2(2, 43) <= sub_wire15(43); + sub_wire2(2, 44) <= sub_wire15(44); + sub_wire2(2, 45) <= sub_wire15(45); + sub_wire2(2, 46) <= sub_wire15(46); + sub_wire2(2, 47) <= sub_wire15(47); + sub_wire2(2, 48) <= sub_wire15(48); + sub_wire2(2, 49) <= sub_wire15(49); + sub_wire2(2, 50) <= sub_wire15(50); + sub_wire2(2, 51) <= sub_wire15(51); + sub_wire2(2, 52) <= sub_wire15(52); + sub_wire2(2, 53) <= sub_wire15(53); + sub_wire2(2, 54) <= sub_wire15(54); + sub_wire2(2, 55) <= sub_wire15(55); + sub_wire2(2, 56) <= sub_wire15(56); + sub_wire2(2, 57) <= sub_wire15(57); + sub_wire2(2, 58) <= sub_wire15(58); + sub_wire2(2, 59) <= sub_wire15(59); + sub_wire2(2, 60) <= sub_wire15(60); + sub_wire2(2, 61) <= sub_wire15(61); + sub_wire2(2, 62) <= sub_wire15(62); + sub_wire2(2, 63) <= sub_wire15(63); + sub_wire2(2, 64) <= sub_wire15(64); + sub_wire2(2, 65) <= sub_wire15(65); + sub_wire2(2, 66) <= sub_wire15(66); + sub_wire2(2, 67) <= sub_wire15(67); + sub_wire2(2, 68) <= sub_wire15(68); + sub_wire2(2, 69) <= sub_wire15(69); + sub_wire2(2, 70) <= sub_wire15(70); + sub_wire2(2, 71) <= sub_wire15(71); + sub_wire2(2, 72) <= sub_wire15(72); + sub_wire2(2, 73) <= sub_wire15(73); + sub_wire2(2, 74) <= sub_wire15(74); + sub_wire2(2, 75) <= sub_wire15(75); + sub_wire2(2, 76) <= sub_wire15(76); + sub_wire2(2, 77) <= sub_wire15(77); + sub_wire2(2, 78) <= sub_wire15(78); + sub_wire2(2, 79) <= sub_wire15(79); + sub_wire2(2, 80) <= sub_wire15(80); + sub_wire2(2, 81) <= sub_wire15(81); + sub_wire2(2, 82) <= sub_wire15(82); + sub_wire2(2, 83) <= sub_wire15(83); + sub_wire2(2, 84) <= sub_wire15(84); + sub_wire2(2, 85) <= sub_wire15(85); + sub_wire2(2, 86) <= sub_wire15(86); + sub_wire2(2, 87) <= sub_wire15(87); + sub_wire2(2, 88) <= sub_wire15(88); + sub_wire2(2, 89) <= sub_wire15(89); + sub_wire2(2, 90) <= sub_wire15(90); + sub_wire2(2, 91) <= sub_wire15(91); + sub_wire2(2, 92) <= sub_wire15(92); + sub_wire2(2, 93) <= sub_wire15(93); + sub_wire2(2, 94) <= sub_wire15(94); + sub_wire2(2, 95) <= sub_wire15(95); + sub_wire2(2, 96) <= sub_wire15(96); + sub_wire2(2, 97) <= sub_wire15(97); + sub_wire2(2, 98) <= sub_wire15(98); + sub_wire2(2, 99) <= sub_wire15(99); + sub_wire2(2, 100) <= sub_wire15(100); + sub_wire2(2, 101) <= sub_wire15(101); + sub_wire2(2, 102) <= sub_wire15(102); + sub_wire2(2, 103) <= sub_wire15(103); + sub_wire2(2, 104) <= sub_wire15(104); + sub_wire2(2, 105) <= sub_wire15(105); + sub_wire2(2, 106) <= sub_wire15(106); + sub_wire2(2, 107) <= sub_wire15(107); + sub_wire2(2, 108) <= sub_wire15(108); + sub_wire2(2, 109) <= sub_wire15(109); + sub_wire2(2, 110) <= sub_wire15(110); + sub_wire2(2, 111) <= sub_wire15(111); + sub_wire2(2, 112) <= sub_wire15(112); + sub_wire2(2, 113) <= sub_wire15(113); + sub_wire2(2, 114) <= sub_wire15(114); + sub_wire2(2, 115) <= sub_wire15(115); + sub_wire2(2, 116) <= sub_wire15(116); + sub_wire2(2, 117) <= sub_wire15(117); + sub_wire2(2, 118) <= sub_wire15(118); + sub_wire2(2, 119) <= sub_wire15(119); + sub_wire2(2, 120) <= sub_wire15(120); + sub_wire2(2, 121) <= sub_wire15(121); + sub_wire2(2, 122) <= sub_wire15(122); + sub_wire2(2, 123) <= sub_wire15(123); + sub_wire2(2, 124) <= sub_wire15(124); + sub_wire2(2, 125) <= sub_wire15(125); + sub_wire2(2, 126) <= sub_wire15(126); + sub_wire2(2, 127) <= sub_wire15(127); + sub_wire2(1, 0) <= sub_wire16(0); + sub_wire2(1, 1) <= sub_wire16(1); + sub_wire2(1, 2) <= sub_wire16(2); + sub_wire2(1, 3) <= sub_wire16(3); + sub_wire2(1, 4) <= sub_wire16(4); + sub_wire2(1, 5) <= sub_wire16(5); + sub_wire2(1, 6) <= sub_wire16(6); + sub_wire2(1, 7) <= sub_wire16(7); + sub_wire2(1, 8) <= sub_wire16(8); + sub_wire2(1, 9) <= sub_wire16(9); + sub_wire2(1, 10) <= sub_wire16(10); + sub_wire2(1, 11) <= sub_wire16(11); + sub_wire2(1, 12) <= sub_wire16(12); + sub_wire2(1, 13) <= sub_wire16(13); + sub_wire2(1, 14) <= sub_wire16(14); + sub_wire2(1, 15) <= sub_wire16(15); + sub_wire2(1, 16) <= sub_wire16(16); + sub_wire2(1, 17) <= sub_wire16(17); + sub_wire2(1, 18) <= sub_wire16(18); + sub_wire2(1, 19) <= sub_wire16(19); + sub_wire2(1, 20) <= sub_wire16(20); + sub_wire2(1, 21) <= sub_wire16(21); + sub_wire2(1, 22) <= sub_wire16(22); + sub_wire2(1, 23) <= sub_wire16(23); + sub_wire2(1, 24) <= sub_wire16(24); + sub_wire2(1, 25) <= sub_wire16(25); + sub_wire2(1, 26) <= sub_wire16(26); + sub_wire2(1, 27) <= sub_wire16(27); + sub_wire2(1, 28) <= sub_wire16(28); + sub_wire2(1, 29) <= sub_wire16(29); + sub_wire2(1, 30) <= sub_wire16(30); + sub_wire2(1, 31) <= sub_wire16(31); + sub_wire2(1, 32) <= sub_wire16(32); + sub_wire2(1, 33) <= sub_wire16(33); + sub_wire2(1, 34) <= sub_wire16(34); + sub_wire2(1, 35) <= sub_wire16(35); + sub_wire2(1, 36) <= sub_wire16(36); + sub_wire2(1, 37) <= sub_wire16(37); + sub_wire2(1, 38) <= sub_wire16(38); + sub_wire2(1, 39) <= sub_wire16(39); + sub_wire2(1, 40) <= sub_wire16(40); + sub_wire2(1, 41) <= sub_wire16(41); + sub_wire2(1, 42) <= sub_wire16(42); + sub_wire2(1, 43) <= sub_wire16(43); + sub_wire2(1, 44) <= sub_wire16(44); + sub_wire2(1, 45) <= sub_wire16(45); + sub_wire2(1, 46) <= sub_wire16(46); + sub_wire2(1, 47) <= sub_wire16(47); + sub_wire2(1, 48) <= sub_wire16(48); + sub_wire2(1, 49) <= sub_wire16(49); + sub_wire2(1, 50) <= sub_wire16(50); + sub_wire2(1, 51) <= sub_wire16(51); + sub_wire2(1, 52) <= sub_wire16(52); + sub_wire2(1, 53) <= sub_wire16(53); + sub_wire2(1, 54) <= sub_wire16(54); + sub_wire2(1, 55) <= sub_wire16(55); + sub_wire2(1, 56) <= sub_wire16(56); + sub_wire2(1, 57) <= sub_wire16(57); + sub_wire2(1, 58) <= sub_wire16(58); + sub_wire2(1, 59) <= sub_wire16(59); + sub_wire2(1, 60) <= sub_wire16(60); + sub_wire2(1, 61) <= sub_wire16(61); + sub_wire2(1, 62) <= sub_wire16(62); + sub_wire2(1, 63) <= sub_wire16(63); + sub_wire2(1, 64) <= sub_wire16(64); + sub_wire2(1, 65) <= sub_wire16(65); + sub_wire2(1, 66) <= sub_wire16(66); + sub_wire2(1, 67) <= sub_wire16(67); + sub_wire2(1, 68) <= sub_wire16(68); + sub_wire2(1, 69) <= sub_wire16(69); + sub_wire2(1, 70) <= sub_wire16(70); + sub_wire2(1, 71) <= sub_wire16(71); + sub_wire2(1, 72) <= sub_wire16(72); + sub_wire2(1, 73) <= sub_wire16(73); + sub_wire2(1, 74) <= sub_wire16(74); + sub_wire2(1, 75) <= sub_wire16(75); + sub_wire2(1, 76) <= sub_wire16(76); + sub_wire2(1, 77) <= sub_wire16(77); + sub_wire2(1, 78) <= sub_wire16(78); + sub_wire2(1, 79) <= sub_wire16(79); + sub_wire2(1, 80) <= sub_wire16(80); + sub_wire2(1, 81) <= sub_wire16(81); + sub_wire2(1, 82) <= sub_wire16(82); + sub_wire2(1, 83) <= sub_wire16(83); + sub_wire2(1, 84) <= sub_wire16(84); + sub_wire2(1, 85) <= sub_wire16(85); + sub_wire2(1, 86) <= sub_wire16(86); + sub_wire2(1, 87) <= sub_wire16(87); + sub_wire2(1, 88) <= sub_wire16(88); + sub_wire2(1, 89) <= sub_wire16(89); + sub_wire2(1, 90) <= sub_wire16(90); + sub_wire2(1, 91) <= sub_wire16(91); + sub_wire2(1, 92) <= sub_wire16(92); + sub_wire2(1, 93) <= sub_wire16(93); + sub_wire2(1, 94) <= sub_wire16(94); + sub_wire2(1, 95) <= sub_wire16(95); + sub_wire2(1, 96) <= sub_wire16(96); + sub_wire2(1, 97) <= sub_wire16(97); + sub_wire2(1, 98) <= sub_wire16(98); + sub_wire2(1, 99) <= sub_wire16(99); + sub_wire2(1, 100) <= sub_wire16(100); + sub_wire2(1, 101) <= sub_wire16(101); + sub_wire2(1, 102) <= sub_wire16(102); + sub_wire2(1, 103) <= sub_wire16(103); + sub_wire2(1, 104) <= sub_wire16(104); + sub_wire2(1, 105) <= sub_wire16(105); + sub_wire2(1, 106) <= sub_wire16(106); + sub_wire2(1, 107) <= sub_wire16(107); + sub_wire2(1, 108) <= sub_wire16(108); + sub_wire2(1, 109) <= sub_wire16(109); + sub_wire2(1, 110) <= sub_wire16(110); + sub_wire2(1, 111) <= sub_wire16(111); + sub_wire2(1, 112) <= sub_wire16(112); + sub_wire2(1, 113) <= sub_wire16(113); + sub_wire2(1, 114) <= sub_wire16(114); + sub_wire2(1, 115) <= sub_wire16(115); + sub_wire2(1, 116) <= sub_wire16(116); + sub_wire2(1, 117) <= sub_wire16(117); + sub_wire2(1, 118) <= sub_wire16(118); + sub_wire2(1, 119) <= sub_wire16(119); + sub_wire2(1, 120) <= sub_wire16(120); + sub_wire2(1, 121) <= sub_wire16(121); + sub_wire2(1, 122) <= sub_wire16(122); + sub_wire2(1, 123) <= sub_wire16(123); + sub_wire2(1, 124) <= sub_wire16(124); + sub_wire2(1, 125) <= sub_wire16(125); + sub_wire2(1, 126) <= sub_wire16(126); + sub_wire2(1, 127) <= sub_wire16(127); + sub_wire2(0, 0) <= sub_wire17(0); + sub_wire2(0, 1) <= sub_wire17(1); + sub_wire2(0, 2) <= sub_wire17(2); + sub_wire2(0, 3) <= sub_wire17(3); + sub_wire2(0, 4) <= sub_wire17(4); + sub_wire2(0, 5) <= sub_wire17(5); + sub_wire2(0, 6) <= sub_wire17(6); + sub_wire2(0, 7) <= sub_wire17(7); + sub_wire2(0, 8) <= sub_wire17(8); + sub_wire2(0, 9) <= sub_wire17(9); + sub_wire2(0, 10) <= sub_wire17(10); + sub_wire2(0, 11) <= sub_wire17(11); + sub_wire2(0, 12) <= sub_wire17(12); + sub_wire2(0, 13) <= sub_wire17(13); + sub_wire2(0, 14) <= sub_wire17(14); + sub_wire2(0, 15) <= sub_wire17(15); + sub_wire2(0, 16) <= sub_wire17(16); + sub_wire2(0, 17) <= sub_wire17(17); + sub_wire2(0, 18) <= sub_wire17(18); + sub_wire2(0, 19) <= sub_wire17(19); + sub_wire2(0, 20) <= sub_wire17(20); + sub_wire2(0, 21) <= sub_wire17(21); + sub_wire2(0, 22) <= sub_wire17(22); + sub_wire2(0, 23) <= sub_wire17(23); + sub_wire2(0, 24) <= sub_wire17(24); + sub_wire2(0, 25) <= sub_wire17(25); + sub_wire2(0, 26) <= sub_wire17(26); + sub_wire2(0, 27) <= sub_wire17(27); + sub_wire2(0, 28) <= sub_wire17(28); + sub_wire2(0, 29) <= sub_wire17(29); + sub_wire2(0, 30) <= sub_wire17(30); + sub_wire2(0, 31) <= sub_wire17(31); + sub_wire2(0, 32) <= sub_wire17(32); + sub_wire2(0, 33) <= sub_wire17(33); + sub_wire2(0, 34) <= sub_wire17(34); + sub_wire2(0, 35) <= sub_wire17(35); + sub_wire2(0, 36) <= sub_wire17(36); + sub_wire2(0, 37) <= sub_wire17(37); + sub_wire2(0, 38) <= sub_wire17(38); + sub_wire2(0, 39) <= sub_wire17(39); + sub_wire2(0, 40) <= sub_wire17(40); + sub_wire2(0, 41) <= sub_wire17(41); + sub_wire2(0, 42) <= sub_wire17(42); + sub_wire2(0, 43) <= sub_wire17(43); + sub_wire2(0, 44) <= sub_wire17(44); + sub_wire2(0, 45) <= sub_wire17(45); + sub_wire2(0, 46) <= sub_wire17(46); + sub_wire2(0, 47) <= sub_wire17(47); + sub_wire2(0, 48) <= sub_wire17(48); + sub_wire2(0, 49) <= sub_wire17(49); + sub_wire2(0, 50) <= sub_wire17(50); + sub_wire2(0, 51) <= sub_wire17(51); + sub_wire2(0, 52) <= sub_wire17(52); + sub_wire2(0, 53) <= sub_wire17(53); + sub_wire2(0, 54) <= sub_wire17(54); + sub_wire2(0, 55) <= sub_wire17(55); + sub_wire2(0, 56) <= sub_wire17(56); + sub_wire2(0, 57) <= sub_wire17(57); + sub_wire2(0, 58) <= sub_wire17(58); + sub_wire2(0, 59) <= sub_wire17(59); + sub_wire2(0, 60) <= sub_wire17(60); + sub_wire2(0, 61) <= sub_wire17(61); + sub_wire2(0, 62) <= sub_wire17(62); + sub_wire2(0, 63) <= sub_wire17(63); + sub_wire2(0, 64) <= sub_wire17(64); + sub_wire2(0, 65) <= sub_wire17(65); + sub_wire2(0, 66) <= sub_wire17(66); + sub_wire2(0, 67) <= sub_wire17(67); + sub_wire2(0, 68) <= sub_wire17(68); + sub_wire2(0, 69) <= sub_wire17(69); + sub_wire2(0, 70) <= sub_wire17(70); + sub_wire2(0, 71) <= sub_wire17(71); + sub_wire2(0, 72) <= sub_wire17(72); + sub_wire2(0, 73) <= sub_wire17(73); + sub_wire2(0, 74) <= sub_wire17(74); + sub_wire2(0, 75) <= sub_wire17(75); + sub_wire2(0, 76) <= sub_wire17(76); + sub_wire2(0, 77) <= sub_wire17(77); + sub_wire2(0, 78) <= sub_wire17(78); + sub_wire2(0, 79) <= sub_wire17(79); + sub_wire2(0, 80) <= sub_wire17(80); + sub_wire2(0, 81) <= sub_wire17(81); + sub_wire2(0, 82) <= sub_wire17(82); + sub_wire2(0, 83) <= sub_wire17(83); + sub_wire2(0, 84) <= sub_wire17(84); + sub_wire2(0, 85) <= sub_wire17(85); + sub_wire2(0, 86) <= sub_wire17(86); + sub_wire2(0, 87) <= sub_wire17(87); + sub_wire2(0, 88) <= sub_wire17(88); + sub_wire2(0, 89) <= sub_wire17(89); + sub_wire2(0, 90) <= sub_wire17(90); + sub_wire2(0, 91) <= sub_wire17(91); + sub_wire2(0, 92) <= sub_wire17(92); + sub_wire2(0, 93) <= sub_wire17(93); + sub_wire2(0, 94) <= sub_wire17(94); + sub_wire2(0, 95) <= sub_wire17(95); + sub_wire2(0, 96) <= sub_wire17(96); + sub_wire2(0, 97) <= sub_wire17(97); + sub_wire2(0, 98) <= sub_wire17(98); + sub_wire2(0, 99) <= sub_wire17(99); + sub_wire2(0, 100) <= sub_wire17(100); + sub_wire2(0, 101) <= sub_wire17(101); + sub_wire2(0, 102) <= sub_wire17(102); + sub_wire2(0, 103) <= sub_wire17(103); + sub_wire2(0, 104) <= sub_wire17(104); + sub_wire2(0, 105) <= sub_wire17(105); + sub_wire2(0, 106) <= sub_wire17(106); + sub_wire2(0, 107) <= sub_wire17(107); + sub_wire2(0, 108) <= sub_wire17(108); + sub_wire2(0, 109) <= sub_wire17(109); + sub_wire2(0, 110) <= sub_wire17(110); + sub_wire2(0, 111) <= sub_wire17(111); + sub_wire2(0, 112) <= sub_wire17(112); + sub_wire2(0, 113) <= sub_wire17(113); + sub_wire2(0, 114) <= sub_wire17(114); + sub_wire2(0, 115) <= sub_wire17(115); + sub_wire2(0, 116) <= sub_wire17(116); + sub_wire2(0, 117) <= sub_wire17(117); + sub_wire2(0, 118) <= sub_wire17(118); + sub_wire2(0, 119) <= sub_wire17(119); + sub_wire2(0, 120) <= sub_wire17(120); + sub_wire2(0, 121) <= sub_wire17(121); + sub_wire2(0, 122) <= sub_wire17(122); + sub_wire2(0, 123) <= sub_wire17(123); + sub_wire2(0, 124) <= sub_wire17(124); + sub_wire2(0, 125) <= sub_wire17(125); + sub_wire2(0, 126) <= sub_wire17(126); + sub_wire2(0, 127) <= sub_wire17(127); + + lpm_mux_component : lpm_mux + GENERIC MAP ( + lpm_size => 16, + lpm_type => "LPM_MUX", + lpm_width => 128, + lpm_widths => 4 + ) + PORT MAP ( + sel => sel, + data => sub_wire2, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4" +-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0] +-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0] +-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0] +-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0] +-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0] +-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0] +-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0] +-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0] +-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0] +-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0] +-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0] +-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0] +-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0] +-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0] +-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0] +-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0] +-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0] +-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0] +-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0 +-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0 +-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.bsf new file mode 100644 index 0000000..fb70a4b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.bsf @@ -0,0 +1,70 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 128) + (text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "load" (rect 0 0 23 14)(font "Arial" (font_size 8))) + (text "load" (rect 20 26 41 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 144 72) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8))) + (line (pt 144 72)(pt 128 72)(line_width 1)) + ) + (drawing + (text "left shift" (rect 92 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 112)(line_width 1)) + (line (pt 128 112)(pt 16 112)(line_width 1)) + (line (pt 16 112)(pt 16 16)(line_width 1)) + (line (pt 16 74)(pt 22 80)(line_width 1)) + (line (pt 22 80)(pt 16 86)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.cmp new file mode 100644 index 0000000..c0613d5 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg0 + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + load : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.inc b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.inc new file mode 100644 index 0000000..1c0c4a2 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.inc @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg0 +( + clock, + data[15..0], + load, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.qip new file mode 100644 index 0000000..a233319 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.vhd new file mode 100644 index 0000000..6e5d954 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg0.vhd @@ -0,0 +1,135 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg0.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg0 IS + PORT + ( + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + load : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg0; + + +ARCHITECTURE SYN OF lpm_shiftreg0 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + load : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "LEFT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 16 + ) + PORT MAP ( + load => load, + clock => clock, + data => data, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "1" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "1" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.bsf new file mode 100644 index 0000000..aa20405 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "left shift" (rect 92 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.cmp new file mode 100644 index 0000000..1a7ae1c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg1 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.qip new file mode 100644 index 0000000..8a8e8a5 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.vhd new file mode 100644 index 0000000..781fe1b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg1.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg1.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg1 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) + ); +END lpm_shiftreg1; + + +ARCHITECTURE SYN OF lpm_shiftreg1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (1 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(1 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "LEFT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 2 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "1" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.bsf new file mode 100644 index 0000000..0caa084 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.cmp new file mode 100644 index 0000000..e7c1030 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg2 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.qip new file mode 100644 index 0000000..3c5305b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.vhd new file mode 100644 index 0000000..ca02c26 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg2.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg2.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg2 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg2; + + +ARCHITECTURE SYN OF lpm_shiftreg2 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 4 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.bsf new file mode 100644 index 0000000..d18b388 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.cmp new file mode 100644 index 0000000..4cc6db7 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg3 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.inc b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.inc new file mode 100644 index 0000000..4f70ce5 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg3 +( + clock, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.qip new file mode 100644 index 0000000..783fdea --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.vhd new file mode 100644 index 0000000..b87c221 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg3.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg3.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg3 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg3; + + +ARCHITECTURE SYN OF lpm_shiftreg3 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 2 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "2" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.bsf new file mode 100644 index 0000000..658958d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 1)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.cmp new file mode 100644 index 0000000..83fb9e5 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg4 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.inc b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.inc new file mode 100644 index 0000000..322863a --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg4 +( + clock, + shiftin +) + +RETURNS ( + shiftout +); diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.qip new file mode 100644 index 0000000..363cd59 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.vhd new file mode 100644 index 0000000..3d8f5d1 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg4.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg4.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg4 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC + ); +END lpm_shiftreg4; + + +ARCHITECTURE SYN OF lpm_shiftreg4 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + shiftout : OUT STD_LOGIC ; + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + shiftout <= sub_wire0; + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + shiftout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.bsf new file mode 100644 index 0000000..a528c96 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.cmp new file mode 100644 index 0000000..638f12e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg5 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.inc b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.inc new file mode 100644 index 0000000..431ed2c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg5 +( + clock, + shiftin +) + +RETURNS ( + q[4..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.qip new file mode 100644 index 0000000..9b71f4b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.vhd new file mode 100644 index 0000000..71a1232 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg5.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg5.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg5 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_shiftreg5; + + +ARCHITECTURE SYN OF lpm_shiftreg5 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(4 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.bsf b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.bsf new file mode 100644 index 0000000..aa0296b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 80) + (text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 144 48) + (output) + (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) + (line (pt 144 48)(pt 128 48)(line_width 3)) + ) + (drawing + (text "right shift" (rect 88 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 64)(line_width 1)) + (line (pt 128 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.cmp b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.cmp new file mode 100644 index 0000000..c9f7a9b --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_shiftreg6 + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.inc b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.inc new file mode 100644 index 0000000..7767c57 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_shiftreg6 +( + clock, + shiftin +) + +RETURNS ( + q[4..0] +); diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.qip b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.qip new file mode 100644 index 0000000..adb4909 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"] diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.vhd b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.vhd new file mode 100644 index 0000000..773243e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/lpm_shiftreg6.vhd @@ -0,0 +1,125 @@ +-- megafunction wizard: %LPM_SHIFTREG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_shiftreg + +-- ============================================================ +-- File Name: lpm_shiftreg6.vhd +-- Megafunction Name(s): +-- lpm_shiftreg +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_shiftreg6 IS + PORT + ( + clock : IN STD_LOGIC ; + shiftin : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); +END lpm_shiftreg6; + + +ARCHITECTURE SYN OF lpm_shiftreg6 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + + + + COMPONENT lpm_shiftreg + GENERIC ( + lpm_direction : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + shiftin : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(4 DOWNTO 0); + + lpm_shiftreg_component : lpm_shiftreg + GENERIC MAP ( + lpm_direction => "RIGHT", + lpm_type => "LPM_SHIFTREG", + lpm_width => 5 + ) + PORT MAP ( + clock => clock, + shiftin => shiftin, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LeftShift NUMERIC "0" +-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0" +-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1" +-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0] +-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0 +-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/altddio_out0.bsf b/FPGA_Quartus_13.1/altddio_out0.bsf new file mode 100644 index 0000000..9889d79 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out0.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altddio_out0.cmp b/FPGA_Quartus_13.1/altddio_out0.cmp new file mode 100644 index 0000000..6e98c39 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out0.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out0 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altddio_out0.inc b/FPGA_Quartus_13.1/altddio_out0.inc new file mode 100644 index 0000000..030b327 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out0.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out0 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/FPGA_Quartus_13.1/altddio_out0.ppf b/FPGA_Quartus_13.1/altddio_out0.ppf new file mode 100644 index 0000000..4379977 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out0.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altddio_out0.qip b/FPGA_Quartus_13.1/altddio_out0.qip new file mode 100644 index 0000000..8193856 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"] diff --git a/FPGA_Quartus_13.1/altddio_out0.vhd b/FPGA_Quartus_13.1/altddio_out0.vhd new file mode 100644 index 0000000..ea6d708 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out0.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out0.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out0 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out0; + + +ARCHITECTURE SYN OF altddio_out0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altddio_out3.bsf b/FPGA_Quartus_13.1/altddio_out3.bsf new file mode 100644 index 0000000..ba8c153 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out3.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 232 120) + (text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 104 25 116)(font "Arial" )) + (port + (pt 0 24) + (input) + (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) + (line (pt 0 24)(pt 88 24)(line_width 1)) + ) + (port + (pt 0 40) + (input) + (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 88 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) + (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 88 56)(line_width 1)) + ) + (port + (pt 232 24) + (output) + (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (line (pt 232 24)(pt 152 24)(line_width 1)) + ) + (drawing + (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) + (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) + (text "power up" (rect 92 74 129 86)(font "Arial" )) + (text "low" (rect 92 84 105 96)(font "Arial" )) + (line (pt 88 16)(pt 152 16)(line_width 1)) + (line (pt 152 16)(pt 152 96)(line_width 1)) + (line (pt 152 96)(pt 88 96)(line_width 1)) + (line (pt 88 96)(pt 88 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altddio_out3.cmp b/FPGA_Quartus_13.1/altddio_out3.cmp new file mode 100644 index 0000000..ce5862c --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out3.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altddio_out3 + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altddio_out3.inc b/FPGA_Quartus_13.1/altddio_out3.inc new file mode 100644 index 0000000..f6b4097 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out3.inc @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altddio_out3 +( + datain_h, + datain_l, + outclock +) + +RETURNS ( + dataout +); diff --git a/FPGA_Quartus_13.1/altddio_out3.ppf b/FPGA_Quartus_13.1/altddio_out3.ppf new file mode 100644 index 0000000..e914df8 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out3.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altddio_out3.qip b/FPGA_Quartus_13.1/altddio_out3.qip new file mode 100644 index 0000000..8f94ee3 --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out3.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"] diff --git a/FPGA_Quartus_13.1/altddio_out3.vhd b/FPGA_Quartus_13.1/altddio_out3.vhd new file mode 100644 index 0000000..e55160f --- /dev/null +++ b/FPGA_Quartus_13.1/altddio_out3.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %ALTDDIO_OUT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altddio_out + +-- ============================================================ +-- File Name: altddio_out3.vhd +-- Megafunction Name(s): +-- altddio_out +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altddio_out3 IS + PORT + ( + datain_h : IN STD_LOGIC ; + datain_l : IN STD_LOGIC ; + outclock : IN STD_LOGIC ; + dataout : OUT STD_LOGIC + ); +END altddio_out3; + + +ARCHITECTURE SYN OF altddio_out3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altddio_out + GENERIC ( + extend_oe_disable : STRING; + intended_device_family : STRING; + invert_output : STRING; + lpm_type : STRING; + oe_reg : STRING; + power_up_high : STRING; + width : NATURAL + ); + PORT ( + dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); + outclock : IN STD_LOGIC ; + datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire1 <= sub_wire0(0); + dataout <= sub_wire1; + sub_wire2 <= datain_h; + sub_wire3(0) <= sub_wire2; + sub_wire4 <= datain_l; + sub_wire5(0) <= sub_wire4; + + altddio_out_component : altddio_out + GENERIC MAP ( + extend_oe_disable => "UNUSED", + intended_device_family => "Cyclone III", + invert_output => "OFF", + lpm_type => "altddio_out", + oe_reg => "UNUSED", + power_up_high => "OFF", + width => 1 + ) + PORT MAP ( + outclock => outclock, + datain_h => sub_wire3, + datain_l => sub_wire5, + dataout => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: OE NUMERIC "0" +-- Retrieval info: PRIVATE: OE_REG NUMERIC "0" +-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0" +-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: WIDTH NUMERIC "1" +-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out" +-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED" +-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH NUMERIC "1" +-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h +-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l +-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout +-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock +-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0 +-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0 +-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0 +-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll0.bsf b/FPGA_Quartus_13.1/altpll0.bsf new file mode 100644 index 0000000..b9a2853 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 280 248) + (text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 229 31 244)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 280 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8))) + (line (pt 280 72)(pt 248 72)(line_width 1)) + ) + (port + (pt 280 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8))) + (line (pt 280 96)(pt 248 96)(line_width 1)) + ) + (port + (pt 280 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8))) + (line (pt 280 120)(pt 248 120)(line_width 1)) + ) + (port + (pt 280 144) + (output) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8))) + (line (pt 280 144)(pt 248 144)(line_width 1)) + ) + (port + (pt 280 168) + (output) + (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8))) + (line (pt 280 168)(pt 248 168)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 205 230 253 244)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 90 111 114 125)(font "Arial" )) + (text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) + (text "DC (%)" (rect 173 111 208 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "16/11" (rect 89 129 116 143)(font "Arial" )) + (text "0.00" (rect 136 129 157 143)(font "Arial" )) + (text "50.00" (rect 178 129 205 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "50/11" (rect 89 147 116 161)(font "Arial" )) + (text "0.00" (rect 136 147 157 161)(font "Arial" )) + (text "50.00" (rect 178 147 205 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "40/11" (rect 89 165 116 179)(font "Arial" )) + (text "0.00" (rect 136 165 157 179)(font "Arial" )) + (text "50.00" (rect 178 165 205 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "109/33" (rect 85 183 118 197)(font "Arial" )) + (text "0.00" (rect 136 183 157 197)(font "Arial" )) + (text "50.00" (rect 178 183 205 197)(font "Arial" )) + (text "c4" (rect 63 201 75 215)(font "Arial" )) + (text "109/39" (rect 85 201 118 215)(font "Arial" )) + (text "0.00" (rect 136 201 157 215)(font "Arial" )) + (text "50.00" (rect 178 201 205 215)(font "Arial" )) + (line (pt 0 0)(pt 281 0)(line_width 1)) + (line (pt 281 0)(pt 281 249)(line_width 1)) + (line (pt 0 249)(pt 281 249)(line_width 1)) + (line (pt 0 0)(pt 0 249)(line_width 1)) + (line (pt 56 108)(pt 215 108)(line_width 1)) + (line (pt 56 125)(pt 215 125)(line_width 1)) + (line (pt 56 143)(pt 215 143)(line_width 1)) + (line (pt 56 161)(pt 215 161)(line_width 1)) + (line (pt 56 179)(pt 215 179)(line_width 1)) + (line (pt 56 197)(pt 215 197)(line_width 1)) + (line (pt 56 215)(pt 215 215)(line_width 1)) + (line (pt 56 108)(pt 56 215)(line_width 1)) + (line (pt 82 108)(pt 82 215)(line_width 3)) + (line (pt 125 108)(pt 125 215)(line_width 3)) + (line (pt 170 108)(pt 170 215)(line_width 3)) + (line (pt 214 108)(pt 214 215)(line_width 1)) + (line (pt 48 56)(pt 248 56)(line_width 1)) + (line (pt 248 56)(pt 248 232)(line_width 1)) + (line (pt 48 232)(pt 248 232)(line_width 1)) + (line (pt 48 56)(pt 48 232)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll0.cmp b/FPGA_Quartus_13.1/altpll0.cmp new file mode 100644 index 0000000..5097275 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll0 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll0.inc b/FPGA_Quartus_13.1/altpll0.inc new file mode 100644 index 0000000..933af49 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0.inc @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll0 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3, + c4 +); diff --git a/FPGA_Quartus_13.1/altpll0.ppf b/FPGA_Quartus_13.1/altpll0.ppf new file mode 100644 index 0000000..521a742 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll0.qip b/FPGA_Quartus_13.1/altpll0.qip new file mode 100644 index 0000000..1b4cd11 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"] diff --git a/FPGA_Quartus_13.1/altpll0.vhd b/FPGA_Quartus_13.1/altpll0.vhd new file mode 100644 index 0000000..b035bf5 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0.vhd @@ -0,0 +1,477 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll0.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll0 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +END altpll0; + + +ARCHITECTURE SYN OF altpll0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + clk4_divide_by : NATURAL; + clk4_duty_cycle : NATURAL; + clk4_multiply_by : NATURAL; + clk4_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(4); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + c4 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 11, + clk0_duty_cycle => 50, + clk0_multiply_by => 16, + clk0_phase_shift => "0", + clk1_divide_by => 11, + clk1_duty_cycle => 50, + clk1_multiply_by => 50, + clk1_phase_shift => "0", + clk2_divide_by => 11, + clk2_duty_cycle => 50, + clk2_multiply_by => 40, + clk2_phase_shift => "0", + clk3_divide_by => 33, + clk3_duty_cycle => 50, + clk3_multiply_by => 109, + clk3_phase_shift => "0", + clk4_divide_by => 39, + clk4_duty_cycle => 50, + clk4_multiply_by => 109, + clk4_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_USED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "75" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "36" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "39" +-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "39" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "120.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "109.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "92.230766" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "109" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "120.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "109.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "92.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK4 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "39" +-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "109" +-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll0_waveforms.html b/FPGA_Quartus_13.1/altpll0_waveforms.html new file mode 100644 index 0000000..80e236a --- /dev/null +++ b/FPGA_Quartus_13.1/altpll0_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll0.vhd" + + +

Sample behavioral waveforms for design file "altpll0.vhd"

+

+

+ + diff --git a/FPGA_Quartus_13.1/altpll1.bsf b/FPGA_Quartus_13.1/altpll1.bsf new file mode 100644 index 0000000..d1e4a9e --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1.bsf @@ -0,0 +1,100 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 328 216) + (text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 197 31 212)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 328 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8))) + (line (pt 328 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 328 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8))) + (line (pt 328 96)(pt 272 96)(line_width 1)) + ) + (port + (pt 328 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8))) + (line (pt 328 120)(pt 272 120)(line_width 1)) + ) + (port + (pt 328 144) + (output) + (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) + (text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8))) + (line (pt 328 144)(pt 272 144)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 253 198 301 212)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 90 111 114 125)(font "Arial" )) + (text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) + (text "DC (%)" (rect 173 111 208 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "1/66" (rect 92 129 113 143)(font "Arial" )) + (text "0.00" (rect 136 129 157 143)(font "Arial" )) + (text "50.00" (rect 178 129 205 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "67/900" (rect 85 147 118 161)(font "Arial" )) + (text "0.00" (rect 136 147 157 161)(font "Arial" )) + (text "50.00" (rect 178 147 205 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "67/90" (rect 89 165 116 179)(font "Arial" )) + (text "0.00" (rect 136 165 157 179)(font "Arial" )) + (text "50.00" (rect 178 165 205 179)(font "Arial" )) + (line (pt 0 0)(pt 329 0)(line_width 1)) + (line (pt 329 0)(pt 329 217)(line_width 1)) + (line (pt 0 217)(pt 329 217)(line_width 1)) + (line (pt 0 0)(pt 0 217)(line_width 1)) + (line (pt 56 108)(pt 215 108)(line_width 1)) + (line (pt 56 125)(pt 215 125)(line_width 1)) + (line (pt 56 143)(pt 215 143)(line_width 1)) + (line (pt 56 161)(pt 215 161)(line_width 1)) + (line (pt 56 179)(pt 215 179)(line_width 1)) + (line (pt 56 108)(pt 56 179)(line_width 1)) + (line (pt 82 108)(pt 82 179)(line_width 3)) + (line (pt 125 108)(pt 125 179)(line_width 3)) + (line (pt 170 108)(pt 170 179)(line_width 3)) + (line (pt 214 108)(pt 214 179)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 200)(line_width 1)) + (line (pt 48 200)(pt 272 200)(line_width 1)) + (line (pt 48 56)(pt 48 200)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll1.cmp b/FPGA_Quartus_13.1/altpll1.cmp new file mode 100644 index 0000000..300576d --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll1 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll1.inc b/FPGA_Quartus_13.1/altpll1.inc new file mode 100644 index 0000000..0923ad2 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1.inc @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll1 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + locked +); diff --git a/FPGA_Quartus_13.1/altpll1.ppf b/FPGA_Quartus_13.1/altpll1.ppf new file mode 100644 index 0000000..0f38a28 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll1.qip b/FPGA_Quartus_13.1/altpll1.qip new file mode 100644 index 0000000..ec03f05 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] diff --git a/FPGA_Quartus_13.1/altpll1.vhd b/FPGA_Quartus_13.1/altpll1.vhd new file mode 100644 index 0000000..ab9bfaf --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1.vhd @@ -0,0 +1,423 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll1.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll1 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END altpll1; + + +ARCHITECTURE SYN OF altpll1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + locked <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 66, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 900, + clk1_duty_cycle => 50, + clk1_multiply_by => 67, + clk1_phase_shift => "0", + clk2_divide_by => 90, + clk2_duty_cycle => 50, + clk2_multiply_by => 67, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire4 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll1_waveforms.html b/FPGA_Quartus_13.1/altpll1_waveforms.html new file mode 100644 index 0000000..1382a12 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll1_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll1.vhd" + + +

Sample behavioral waveforms for design file "altpll1.vhd"

+

+

+ + diff --git a/FPGA_Quartus_13.1/altpll2.bsf b/FPGA_Quartus_13.1/altpll2.bsf new file mode 100644 index 0000000..79679d7 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2.bsf @@ -0,0 +1,117 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 304 248) + (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 229 31 244)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 304 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 304 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) + (line (pt 304 96)(pt 272 96)(line_width 1)) + ) + (port + (pt 304 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) + (line (pt 304 120)(pt 272 120)(line_width 1)) + ) + (port + (pt 304 144) + (output) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) + (line (pt 304 144)(pt 272 144)(line_width 1)) + ) + (port + (pt 304 168) + (output) + (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8))) + (line (pt 304 168)(pt 272 168)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 229 230 277 244)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 85 111 109 125)(font "Arial" )) + (text "Ph (dg)" (rect 119 111 154 125)(font "Arial" )) + (text "DC (%)" (rect 164 111 199 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "4/1" (rect 91 129 106 143)(font "Arial" )) + (text "240.00" (rect 120 129 153 143)(font "Arial" )) + (text "50.00" (rect 169 129 196 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "4/1" (rect 91 147 106 161)(font "Arial" )) + (text "0.00" (rect 127 147 148 161)(font "Arial" )) + (text "50.00" (rect 169 147 196 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "4/1" (rect 91 165 106 179)(font "Arial" )) + (text "180.00" (rect 120 165 153 179)(font "Arial" )) + (text "50.00" (rect 169 165 196 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "4/1" (rect 91 183 106 197)(font "Arial" )) + (text "105.00" (rect 120 183 153 197)(font "Arial" )) + (text "50.00" (rect 169 183 196 197)(font "Arial" )) + (text "c4" (rect 63 201 75 215)(font "Arial" )) + (text "2/1" (rect 91 201 106 215)(font "Arial" )) + (text "270.00" (rect 120 201 153 215)(font "Arial" )) + (text "50.00" (rect 169 201 196 215)(font "Arial" )) + (line (pt 0 0)(pt 305 0)(line_width 1)) + (line (pt 305 0)(pt 305 249)(line_width 1)) + (line (pt 0 249)(pt 305 249)(line_width 1)) + (line (pt 0 0)(pt 0 249)(line_width 1)) + (line (pt 56 108)(pt 206 108)(line_width 1)) + (line (pt 56 125)(pt 206 125)(line_width 1)) + (line (pt 56 143)(pt 206 143)(line_width 1)) + (line (pt 56 161)(pt 206 161)(line_width 1)) + (line (pt 56 179)(pt 206 179)(line_width 1)) + (line (pt 56 197)(pt 206 197)(line_width 1)) + (line (pt 56 215)(pt 206 215)(line_width 1)) + (line (pt 56 108)(pt 56 215)(line_width 1)) + (line (pt 82 108)(pt 82 215)(line_width 3)) + (line (pt 116 108)(pt 116 215)(line_width 3)) + (line (pt 161 108)(pt 161 215)(line_width 3)) + (line (pt 205 108)(pt 205 215)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 232)(line_width 1)) + (line (pt 48 232)(pt 272 232)(line_width 1)) + (line (pt 48 56)(pt 48 232)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll2.cmp b/FPGA_Quartus_13.1/altpll2.cmp new file mode 100644 index 0000000..c6fe758 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll2 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll2.inc b/FPGA_Quartus_13.1/altpll2.inc new file mode 100644 index 0000000..e75913b --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2.inc @@ -0,0 +1,27 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll2 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3, + c4 +); diff --git a/FPGA_Quartus_13.1/altpll2.ppf b/FPGA_Quartus_13.1/altpll2.ppf new file mode 100644 index 0000000..b1c71cc --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2.ppf @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll2.qip b/FPGA_Quartus_13.1/altpll2.qip new file mode 100644 index 0000000..74cc641 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] diff --git a/FPGA_Quartus_13.1/altpll2.vhd b/FPGA_Quartus_13.1/altpll2.vhd new file mode 100644 index 0000000..2c55f08 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2.vhd @@ -0,0 +1,477 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll2.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll2 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +END altpll2; + + +ARCHITECTURE SYN OF altpll2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + clk4_divide_by : NATURAL; + clk4_duty_cycle : NATURAL; + clk4_multiply_by : NATURAL; + clk4_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(4); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + c4 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "5051", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 1, + clk2_duty_cycle => 50, + clk2_multiply_by => 4, + clk2_phase_shift => "3788", + clk3_divide_by => 1, + clk3_duty_cycle => 50, + clk3_multiply_by => 4, + clk3_phase_shift => "2210", + clk4_divide_by => 1, + clk4_duty_cycle => 50, + clk4_multiply_by => 2, + clk4_phase_shift => "11364", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_USED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK4 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210" +-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll2_waveforms.html b/FPGA_Quartus_13.1/altpll2_waveforms.html new file mode 100644 index 0000000..1932527 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll2_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll2.vhd" + + +

Sample behavioral waveforms for design file "altpll2.vhd"

+

+

+ + diff --git a/FPGA_Quartus_13.1/altpll3.bsf b/FPGA_Quartus_13.1/altpll3.bsf new file mode 100644 index 0000000..da30b0c --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3.bsf @@ -0,0 +1,105 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 304 232) + (text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 213 31 228)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 304 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)(line_width 1)) + ) + (port + (pt 304 96) + (output) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) + (line (pt 304 96)(pt 272 96)(line_width 1)) + ) + (port + (pt 304 120) + (output) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) + (line (pt 304 120)(pt 272 120)(line_width 1)) + ) + (port + (pt 304 144) + (output) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) + (line (pt 304 144)(pt 272 144)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 229 214 277 228)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 86 111 110 125)(font "Arial" )) + (text "Ph (dg)" (rect 121 111 156 125)(font "Arial" )) + (text "DC (%)" (rect 166 111 201 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "2/33" (rect 88 129 109 143)(font "Arial" )) + (text "0.00" (rect 129 129 150 143)(font "Arial" )) + (text "50.00" (rect 171 129 198 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "16/33" (rect 85 147 112 161)(font "Arial" )) + (text "0.00" (rect 129 147 150 161)(font "Arial" )) + (text "50.00" (rect 171 147 198 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "25/33" (rect 85 165 112 179)(font "Arial" )) + (text "0.00" (rect 129 165 150 179)(font "Arial" )) + (text "50.00" (rect 171 165 198 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "16/11" (rect 85 183 112 197)(font "Arial" )) + (text "0.00" (rect 129 183 150 197)(font "Arial" )) + (text "50.00" (rect 171 183 198 197)(font "Arial" )) + (line (pt 0 0)(pt 305 0)(line_width 1)) + (line (pt 305 0)(pt 305 233)(line_width 1)) + (line (pt 0 233)(pt 305 233)(line_width 1)) + (line (pt 0 0)(pt 0 233)(line_width 1)) + (line (pt 56 108)(pt 208 108)(line_width 1)) + (line (pt 56 125)(pt 208 125)(line_width 1)) + (line (pt 56 143)(pt 208 143)(line_width 1)) + (line (pt 56 161)(pt 208 161)(line_width 1)) + (line (pt 56 179)(pt 208 179)(line_width 1)) + (line (pt 56 197)(pt 208 197)(line_width 1)) + (line (pt 56 108)(pt 56 197)(line_width 1)) + (line (pt 82 108)(pt 82 197)(line_width 3)) + (line (pt 118 108)(pt 118 197)(line_width 3)) + (line (pt 163 108)(pt 163 197)(line_width 3)) + (line (pt 207 108)(pt 207 197)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 216)(line_width 1)) + (line (pt 48 216)(pt 272 216)(line_width 1)) + (line (pt 48 56)(pt 48 216)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll3.cmp b/FPGA_Quartus_13.1/altpll3.cmp new file mode 100644 index 0000000..44b3f2e --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll3 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll3.inc b/FPGA_Quartus_13.1/altpll3.inc new file mode 100644 index 0000000..160ecad --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3.inc @@ -0,0 +1,26 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll3 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3 +); diff --git a/FPGA_Quartus_13.1/altpll3.ppf b/FPGA_Quartus_13.1/altpll3.ppf new file mode 100644 index 0000000..2a7b695 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll3.qip b/FPGA_Quartus_13.1/altpll3.qip new file mode 100644 index 0000000..8dd2955 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"] diff --git a/FPGA_Quartus_13.1/altpll3.vhd b/FPGA_Quartus_13.1/altpll3.vhd new file mode 100644 index 0000000..6ead1f5 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3.vhd @@ -0,0 +1,445 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll3.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll3 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END altpll3; + + +ARCHITECTURE SYN OF altpll3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 33, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 33, + clk1_duty_cycle => 50, + clk1_multiply_by => 16, + clk1_phase_shift => "0", + clk2_divide_by => 33, + clk2_duty_cycle => 50, + clk2_multiply_by => 25, + clk2_phase_shift => "0", + clk3_divide_by => 11, + clk3_duty_cycle => 50, + clk3_multiply_by => 16, + clk3_phase_shift => "0", + compensate_clock => "CLK1", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll3_waveforms.html b/FPGA_Quartus_13.1/altpll3_waveforms.html new file mode 100644 index 0000000..3f6367c --- /dev/null +++ b/FPGA_Quartus_13.1/altpll3_waveforms.html @@ -0,0 +1,10 @@ + + +Sample Waveforms for "altpll3.vhd" + + +

Sample behavioral waveforms for design file "altpll3.vhd"

+

+

+ + diff --git a/FPGA_Quartus_13.1/altpll4.bsf b/FPGA_Quartus_13.1/altpll4.bsf new file mode 100644 index 0000000..e071d43 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.bsf @@ -0,0 +1,125 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 376 232) + (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 213 31 228)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 88 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) + (text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 88 96)(line_width 1)) + ) + (port + (pt 0 120) + (input) + (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 88 120)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 88 144)(line_width 1)) + ) + (port + (pt 0 168) + (input) + (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 88 168)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 88 192)(line_width 1)) + ) + (port + (pt 376 72) + (output) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) + (line (pt 376 72)(pt 288 72)(line_width 1)) + ) + (port + (pt 376 96) + (output) + (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) + (text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) + (line (pt 376 96)(pt 288 96)(line_width 1)) + ) + (port + (pt 376 120) + (output) + (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) + (line (pt 376 120)(pt 288 120)(line_width 1)) + ) + (port + (pt 376 144) + (output) + (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) + (text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) + (line (pt 376 144)(pt 288 144)(line_width 1)) + ) + (drawing + (text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) + (text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) + (text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) + (text "Clk " (rect 99 167 116 181)(font "Arial" )) + (text "Ratio" (rect 125 167 149 181)(font "Arial" )) + (text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) + (text "DC (%)" (rect 204 167 239 181)(font "Arial" )) + (text "c0" (rect 103 185 115 199)(font "Arial" )) + (text "2/1" (rect 131 185 146 199)(font "Arial" )) + (text "0.00" (rect 167 185 188 199)(font "Arial" )) + (text "50.00" (rect 209 185 236 199)(font "Arial" )) + (line (pt 0 0)(pt 377 0)(line_width 1)) + (line (pt 377 0)(pt 377 233)(line_width 1)) + (line (pt 0 233)(pt 377 233)(line_width 1)) + (line (pt 0 0)(pt 0 233)(line_width 1)) + (line (pt 96 164)(pt 246 164)(line_width 1)) + (line (pt 96 181)(pt 246 181)(line_width 1)) + (line (pt 96 199)(pt 246 199)(line_width 1)) + (line (pt 96 164)(pt 96 199)(line_width 1)) + (line (pt 122 164)(pt 122 199)(line_width 3)) + (line (pt 156 164)(pt 156 199)(line_width 3)) + (line (pt 201 164)(pt 201 199)(line_width 3)) + (line (pt 245 164)(pt 245 199)(line_width 1)) + (line (pt 88 56)(pt 288 56)(line_width 1)) + (line (pt 288 56)(pt 288 216)(line_width 1)) + (line (pt 88 216)(pt 288 216)(line_width 1)) + (line (pt 88 56)(pt 88 216)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll4.cmp b/FPGA_Quartus_13.1/altpll4.cmp new file mode 100644 index 0000000..83b3c1e --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.cmp @@ -0,0 +1,30 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll4 + PORT + ( + areset : IN STD_LOGIC := '0'; + configupdate : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + scanclk : IN STD_LOGIC := '1'; + scanclkena : IN STD_LOGIC := '0'; + scandata : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ; + scandataout : OUT STD_LOGIC ; + scandone : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll4.inc b/FPGA_Quartus_13.1/altpll4.inc new file mode 100644 index 0000000..39f54c9 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.inc @@ -0,0 +1,31 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll4 +( + areset, + configupdate, + inclk0, + scanclk, + scanclkena, + scandata +) + +RETURNS ( + c0, + locked, + scandataout, + scandone +); diff --git a/FPGA_Quartus_13.1/altpll4.mif b/FPGA_Quartus_13.1/altpll4.mif new file mode 100644 index 0000000..e50eda2 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.mif @@ -0,0 +1,174 @@ +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- MIF file representing initial state of PLL Scan Chain +-- Device Family: Cyclone III +-- Device Part: - +-- Device Speed Grade: 8 +-- PLL Scan Chain: Fast PLL (144 bits) +-- File Name: C:\FireBee\FPGA\altpll4.mif +-- Generated: Mon Dec 06 01:47:24 2010 + +WIDTH=1; +DEPTH=144; + +ADDRESS_RADIX=UNS; +DATA_RADIX=UNS; + +CONTENT BEGIN + 0 : 0; -- Reserved Bits = 0 (1 bit(s)) + 1 : 0; -- Reserved Bits = 0 (1 bit(s)) + 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) + 3 : 0; + 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) + 5 : 1; + 6 : 0; + 7 : 1; + 8 : 1; + 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) + 10 : 0; -- Reserved Bits = 0 (5 bit(s)) + 11 : 0; + 12 : 0; + 13 : 0; + 14 : 0; + 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) + 16 : 0; + 17 : 1; + 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) + 19 : 0; -- N counter: High Count = 0 (8 bit(s)) + 20 : 0; + 21 : 0; + 22 : 0; + 23 : 0; + 24 : 0; + 25 : 0; + 26 : 0; + 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) + 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) + 29 : 0; + 30 : 0; + 31 : 0; + 32 : 0; + 33 : 0; + 34 : 0; + 35 : 0; + 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) + 37 : 0; -- M counter: High Count = 6 (8 bit(s)) + 38 : 0; + 39 : 0; + 40 : 0; + 41 : 0; + 42 : 1; + 43 : 1; + 44 : 0; + 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) + 46 : 0; -- M counter: Low Count = 6 (8 bit(s)) + 47 : 0; + 48 : 0; + 49 : 0; + 50 : 0; + 51 : 1; + 52 : 1; + 53 : 0; + 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) + 55 : 0; -- clk0 counter: High Count = 3 (8 bit(s)) + 56 : 0; + 57 : 0; + 58 : 0; + 59 : 0; + 60 : 0; + 61 : 1; + 62 : 1; + 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) + 64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s)) + 65 : 0; + 66 : 0; + 67 : 0; + 68 : 0; + 69 : 0; + 70 : 1; + 71 : 1; + 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 74 : 0; + 75 : 0; + 76 : 0; + 77 : 0; + 78 : 0; + 79 : 0; + 80 : 0; + 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 83 : 0; + 84 : 0; + 85 : 0; + 86 : 0; + 87 : 0; + 88 : 0; + 89 : 0; + 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) + 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) + 92 : 0; + 93 : 0; + 94 : 0; + 95 : 0; + 96 : 0; + 97 : 0; + 98 : 0; + 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) + 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) + 101 : 0; + 102 : 0; + 103 : 0; + 104 : 0; + 105 : 0; + 106 : 0; + 107 : 0; + 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) + 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) + 110 : 0; + 111 : 0; + 112 : 0; + 113 : 0; + 114 : 0; + 115 : 0; + 116 : 0; + 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) + 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) + 119 : 0; + 120 : 0; + 121 : 0; + 122 : 0; + 123 : 0; + 124 : 0; + 125 : 0; + 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) + 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) + 128 : 0; + 129 : 0; + 130 : 0; + 131 : 0; + 132 : 0; + 133 : 0; + 134 : 0; + 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) + 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) + 137 : 0; + 138 : 0; + 139 : 0; + 140 : 0; + 141 : 0; + 142 : 0; + 143 : 0; +END; diff --git a/FPGA_Quartus_13.1/altpll4.ppf b/FPGA_Quartus_13.1/altpll4.ppf new file mode 100644 index 0000000..541ce91 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.ppf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll4.qip b/FPGA_Quartus_13.1/altpll4.qip new file mode 100644 index 0000000..f44acdc --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] diff --git a/FPGA_Quartus_13.1/altpll4.tdf b/FPGA_Quartus_13.1/altpll4.tdf new file mode 100644 index 0000000..3ec77d4 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll4.tdf @@ -0,0 +1,298 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll4.tdf +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + +INCLUDE "altpll.inc"; + + + +SUBDESIGN altpll4 +( + areset : INPUT = GND; + configupdate : INPUT = GND; + inclk0 : INPUT = GND; + scanclk : INPUT = VCC; + scanclkena : INPUT = GND; + scandata : INPUT = GND; + c0 : OUTPUT; + locked : OUTPUT; + scandataout : OUTPUT; + scandone : OUTPUT; +) + +VARIABLE + + altpll_component : altpll WITH ( + BANDWIDTH_TYPE = "AUTO", + CLK0_DIVIDE_BY = 1, + CLK0_DUTY_CYCLE = 50, + CLK0_MULTIPLY_BY = 2, + CLK0_PHASE_SHIFT = "0", + COMPENSATE_CLOCK = "CLK0", + INCLK0_INPUT_FREQUENCY = 20833, + INTENDED_DEVICE_FAMILY = "Cyclone III", + LPM_TYPE = "altpll", + OPERATION_MODE = "NORMAL", + PLL_TYPE = "AUTO", + PORT_ACTIVECLOCK = "PORT_UNUSED", + PORT_ARESET = "PORT_USED", + PORT_CLKBAD0 = "PORT_UNUSED", + PORT_CLKBAD1 = "PORT_UNUSED", + PORT_CLKLOSS = "PORT_UNUSED", + PORT_CLKSWITCH = "PORT_UNUSED", + PORT_CONFIGUPDATE = "PORT_USED", + PORT_FBIN = "PORT_UNUSED", + PORT_INCLK0 = "PORT_USED", + PORT_INCLK1 = "PORT_UNUSED", + PORT_LOCKED = "PORT_USED", + PORT_PFDENA = "PORT_UNUSED", + PORT_PHASECOUNTERSELECT = "PORT_UNUSED", + PORT_PHASEDONE = "PORT_UNUSED", + PORT_PHASESTEP = "PORT_UNUSED", + PORT_PHASEUPDOWN = "PORT_UNUSED", + PORT_PLLENA = "PORT_UNUSED", + PORT_SCANACLR = "PORT_UNUSED", + PORT_SCANCLK = "PORT_USED", + PORT_SCANCLKENA = "PORT_USED", + PORT_SCANDATA = "PORT_USED", + PORT_SCANDATAOUT = "PORT_USED", + PORT_SCANDONE = "PORT_USED", + PORT_SCANREAD = "PORT_UNUSED", + PORT_SCANWRITE = "PORT_UNUSED", + PORT_clk0 = "PORT_USED", + PORT_clk1 = "PORT_UNUSED", + PORT_clk2 = "PORT_UNUSED", + PORT_clk3 = "PORT_UNUSED", + PORT_clk4 = "PORT_UNUSED", + PORT_clk5 = "PORT_UNUSED", + PORT_clkena0 = "PORT_UNUSED", + PORT_clkena1 = "PORT_UNUSED", + PORT_clkena2 = "PORT_UNUSED", + PORT_clkena3 = "PORT_UNUSED", + PORT_clkena4 = "PORT_UNUSED", + PORT_clkena5 = "PORT_UNUSED", + PORT_extclk0 = "PORT_UNUSED", + PORT_extclk1 = "PORT_UNUSED", + PORT_extclk2 = "PORT_UNUSED", + PORT_extclk3 = "PORT_UNUSED", + SELF_RESET_ON_LOSS_LOCK = "OFF", + WIDTH_CLOCK = 5, + scan_chain_mif_file = "altpll4.mif" + ); + +BEGIN + + c0 = altpll_component.clk[0..0]; + scandone = altpll_component.scandone; + scandataout = altpll_component.scandataout; + locked = altpll_component.locked; + altpll_component.scanclkena = scanclkena; + altpll_component.inclk[0..0] = inclk0; + altpll_component.inclk[1..1] = GND; + altpll_component.scandata = scandata; + altpll_component.areset = areset; + altpll_component.scanclk = scanclk; + altpll_component.configupdate = configupdate; +END; + + + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" +-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" +-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" +-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" +-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll_reconfig0.bsf b/FPGA_Quartus_13.1/altpll_reconfig0.bsf new file mode 100644 index 0000000..452f320 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig0.bsf @@ -0,0 +1,162 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 216 296) + (text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 277 31 292)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) + (text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) + (text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) + (text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8))) + (text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8))) + (text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8))) + (text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 16 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8))) + (text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 16 184)(line_width 1)) + ) + (port + (pt 0 208) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8))) + (line (pt 0 208)(pt 16 208)(line_width 1)) + ) + (port + (pt 0 224) + (input) + (text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8))) + (line (pt 0 224)(pt 16 224)(line_width 1)) + ) + (port + (pt 0 248) + (input) + (text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 16 248)(line_width 1)) + ) + (port + (pt 216 40) + (output) + (text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8))) + (text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8))) + (line (pt 216 40)(pt 200 40)(line_width 1)) + ) + (port + (pt 216 96) + (output) + (text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8))) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (port + (pt 216 152) + (output) + (text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8))) + (line (pt 216 152)(pt 200 152)(line_width 1)) + ) + (port + (pt 216 168) + (output) + (text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8))) + (line (pt 216 168)(pt 200 168)(line_width 1)) + ) + (port + (pt 216 200) + (output) + (text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8))) + (line (pt 216 200)(pt 200 200)(line_width 1)) + ) + (port + (pt 216 216) + (output) + (text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8))) + (line (pt 216 216)(pt 200 216)(line_width 1)) + ) + (port + (pt 216 248) + (output) + (text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8))) + (line (pt 216 248)(pt 200 248)(line_width 1)) + ) + (drawing + (line (pt 0 0)(pt 217 0)(line_width 1)) + (line (pt 217 0)(pt 217 297)(line_width 1)) + (line (pt 0 297)(pt 217 297)(line_width 1)) + (line (pt 0 0)(pt 0 297)(line_width 1)) + (line (pt 16 24)(pt 201 24)(line_width 1)) + (line (pt 201 24)(pt 201 273)(line_width 1)) + (line (pt 16 273)(pt 201 273)(line_width 1)) + (line (pt 16 24)(pt 16 273)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll_reconfig0.qip b/FPGA_Quartus_13.1/altpll_reconfig0.qip new file mode 100644 index 0000000..3194459 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.cmp"] diff --git a/FPGA_Quartus_13.1/altpll_reconfig1.bsf b/FPGA_Quartus_13.1/altpll_reconfig1.bsf new file mode 100644 index 0000000..f896607 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1.bsf @@ -0,0 +1,162 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 216 296) + (text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 277 31 292)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 16 40)(line_width 1)) + ) + (port + (pt 0 56) + (input) + (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) + (text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 16 56)(line_width 1)) + ) + (port + (pt 0 72) + (input) + (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) + (text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 16 72)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) + (text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 0 112) + (input) + (text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8))) + (text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)(line_width 3)) + ) + (port + (pt 0 128) + (input) + (text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8))) + (text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 16 128)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8))) + (text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 16 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8))) + (text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 16 184)(line_width 1)) + ) + (port + (pt 0 208) + (input) + (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) + (text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8))) + (line (pt 0 208)(pt 16 208)(line_width 1)) + ) + (port + (pt 0 224) + (input) + (text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8))) + (text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8))) + (line (pt 0 224)(pt 16 224)(line_width 1)) + ) + (port + (pt 0 248) + (input) + (text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8))) + (line (pt 0 248)(pt 16 248)(line_width 1)) + ) + (port + (pt 216 40) + (output) + (text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8))) + (text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8))) + (line (pt 216 40)(pt 200 40)(line_width 1)) + ) + (port + (pt 216 96) + (output) + (text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8))) + (line (pt 216 96)(pt 200 96)(line_width 3)) + ) + (port + (pt 216 152) + (output) + (text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8))) + (line (pt 216 152)(pt 200 152)(line_width 1)) + ) + (port + (pt 216 168) + (output) + (text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8))) + (line (pt 216 168)(pt 200 168)(line_width 1)) + ) + (port + (pt 216 200) + (output) + (text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8))) + (line (pt 216 200)(pt 200 200)(line_width 1)) + ) + (port + (pt 216 216) + (output) + (text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8))) + (line (pt 216 216)(pt 200 216)(line_width 1)) + ) + (port + (pt 216 248) + (output) + (text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8))) + (line (pt 216 248)(pt 200 248)(line_width 1)) + ) + (drawing + (line (pt 0 0)(pt 217 0)(line_width 1)) + (line (pt 217 0)(pt 217 297)(line_width 1)) + (line (pt 0 297)(pt 217 297)(line_width 1)) + (line (pt 0 0)(pt 0 297)(line_width 1)) + (line (pt 16 24)(pt 201 24)(line_width 1)) + (line (pt 201 24)(pt 201 273)(line_width 1)) + (line (pt 16 273)(pt 201 273)(line_width 1)) + (line (pt 16 24)(pt 16 273)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll_reconfig1.cmp b/FPGA_Quartus_13.1/altpll_reconfig1.cmp new file mode 100644 index 0000000..7d409d0 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1.cmp @@ -0,0 +1,38 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll_reconfig1 + PORT + ( + clock : IN STD_LOGIC ; + counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset_in : IN STD_LOGIC := '0'; + pll_scandataout : IN STD_LOGIC ; + pll_scandone : IN STD_LOGIC ; + read_param : IN STD_LOGIC ; + reconfig : IN STD_LOGIC ; + reset : IN STD_LOGIC ; + write_param : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset : OUT STD_LOGIC ; + pll_configupdate : OUT STD_LOGIC ; + pll_scanclk : OUT STD_LOGIC ; + pll_scanclkena : OUT STD_LOGIC ; + pll_scandata : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll_reconfig1.inc b/FPGA_Quartus_13.1/altpll_reconfig1.inc new file mode 100644 index 0000000..c1a6e65 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1.inc @@ -0,0 +1,39 @@ +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll_reconfig1 +( + clock, + counter_param[2..0], + counter_type[3..0], + data_in[8..0], + pll_areset_in, + pll_scandataout, + pll_scandone, + read_param, + reconfig, + reset, + write_param +) + +RETURNS ( + busy, + data_out[8..0], + pll_areset, + pll_configupdate, + pll_scanclk, + pll_scanclkena, + pll_scandata +); diff --git a/FPGA_Quartus_13.1/altpll_reconfig1.qip b/FPGA_Quartus_13.1/altpll_reconfig1.qip new file mode 100644 index 0000000..713a3c3 --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.cmp"] diff --git a/FPGA_Quartus_13.1/altpll_reconfig1.tdf b/FPGA_Quartus_13.1/altpll_reconfig1.tdf new file mode 100644 index 0000000..82ad4ff --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1.tdf @@ -0,0 +1,144 @@ +-- megafunction wizard: %ALTPLL_RECONFIG% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll_reconfig + +-- ============================================================ +-- File Name: altpll_reconfig1.tdf +-- Megafunction Name(s): +-- altpll_reconfig +-- +-- Simulation Library Files(s): +-- altera_mf;cycloneiii;lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2010 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + +-- Clearbox generated function header +FUNCTION altpll_reconfig1_pllrcfg_t4q (clock, counter_param[2..0], counter_type[3..0], data_in[8..0], pll_areset_in, pll_scandataout, pll_scandone, read_param, reconfig, reset, write_param) +RETURNS ( busy, data_out[8..0], pll_areset, pll_configupdate, pll_scanclk, pll_scanclkena, pll_scandata); + + + + +SUBDESIGN altpll_reconfig1 +( + clock : INPUT; + counter_param[2..0] : INPUT; + counter_type[3..0] : INPUT; + data_in[8..0] : INPUT; + pll_areset_in : INPUT = GND; + pll_scandataout : INPUT; + pll_scandone : INPUT; + read_param : INPUT; + reconfig : INPUT; + reset : INPUT; + write_param : INPUT; + busy : OUTPUT; + data_out[8..0] : OUTPUT; + pll_areset : OUTPUT; + pll_configupdate : OUTPUT; + pll_scanclk : OUTPUT; + pll_scanclkena : OUTPUT; + pll_scandata : OUTPUT; +) + +VARIABLE + + altpll_reconfig1_pllrcfg_t4q_component : altpll_reconfig1_pllrcfg_t4q; + +BEGIN + + pll_areset = altpll_reconfig1_pllrcfg_t4q_component.pll_areset; + pll_scanclkena = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclkena; + pll_scanclk = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclk; + busy = altpll_reconfig1_pllrcfg_t4q_component.busy; + data_out[8..0] = altpll_reconfig1_pllrcfg_t4q_component.data_out[8..0]; + pll_scandata = altpll_reconfig1_pllrcfg_t4q_component.pll_scandata; + pll_configupdate = altpll_reconfig1_pllrcfg_t4q_component.pll_configupdate; + altpll_reconfig1_pllrcfg_t4q_component.reconfig = reconfig; + altpll_reconfig1_pllrcfg_t4q_component.counter_type[3..0] = counter_type[3..0]; + altpll_reconfig1_pllrcfg_t4q_component.pll_scandone = pll_scandone; + altpll_reconfig1_pllrcfg_t4q_component.pll_scandataout = pll_scandataout; + altpll_reconfig1_pllrcfg_t4q_component.pll_areset_in = pll_areset_in; + altpll_reconfig1_pllrcfg_t4q_component.read_param = read_param; + altpll_reconfig1_pllrcfg_t4q_component.reset = reset; + altpll_reconfig1_pllrcfg_t4q_component.data_in[8..0] = data_in[8..0]; + altpll_reconfig1_pllrcfg_t4q_component.clock = clock; + altpll_reconfig1_pllrcfg_t4q_component.counter_param[2..0] = counter_param[2..0]; + altpll_reconfig1_pllrcfg_t4q_component.write_param = write_param; +END; + + + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./altpll4.mif" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]" +-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]" +-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]" +-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]" +-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset" +-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in" +-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate" +-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk" +-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena" +-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata" +-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout" +-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone" +-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param" +-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig" +-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset" +-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param" +-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0 +-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0 +-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0 +-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0 +-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0 +-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0 +-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0 +-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0 +-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0 +-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0 +-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0 +-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0 +-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0 +-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.tdf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_inst.tdf FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: LIB_FILE: cycloneiii +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/altpll_reconfig1_pllrcfg_bju.tdf b/FPGA_Quartus_13.1/altpll_reconfig1_pllrcfg_bju.tdf new file mode 100644 index 0000000..81695ae --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1_pllrcfg_bju.tdf @@ -0,0 +1,583 @@ +--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./altpll4.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param +--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END + + +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +include "altsyncram.inc"; +FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS) +RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]); +FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT) +RETURNS ( aeb, agb, ageb, alb, aleb, aneb); +FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown) +WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width) +RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]); +FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable) +WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH) +RETURNS ( eq[LPM_DECODES-1..0]); + +--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 +OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW"; + +SUBDESIGN altpll_reconfig1_pllrcfg_bju +( + busy : output; + clock : input; + counter_param[2..0] : input; + counter_type[3..0] : input; + data_in[8..0] : input; + data_out[8..0] : output; + pll_areset : output; + pll_areset_in : input; + pll_configupdate : output; + pll_scanclk : output; + pll_scanclkena : output; + pll_scandata : output; + pll_scandataout : input; + pll_scandone : input; + read_param : input; + reconfig : input; + reset : input; + write_param : input; +) +VARIABLE + altsyncram4 : altsyncram + WITH ( + INIT_FILE = "./altpll4.mif", + NUMWORDS_A = 144, + OPERATION_MODE = "SINGLE_PORT", + WIDTH_A = 1, + WIDTH_BYTEENA_A = 1, + WIDTHAD_A = 8 + ); + le_comb10 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "F0F0", + SUM_LUTC_INPUT = "datac" + ); + le_comb8 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "AAAA", + SUM_LUTC_INPUT = "datac" + ); + le_comb9 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "CCCC", + SUM_LUTC_INPUT = "datac" + ); + areset_init_state_1 : dffe; + areset_state : dffe; + C0_data_state : dffe; + C0_ena_state : dffe; + C1_data_state : dffe; + C1_ena_state : dffe; + C2_data_state : dffe; + C2_ena_state : dffe; + C3_data_state : dffe; + C3_ena_state : dffe; + C4_data_state : dffe; + C4_ena_state : dffe; + configupdate2_state : dffe; + configupdate3_state : dffe; + configupdate_state : dffe; + counter_param_latch_reg[2..0] : dffe; + counter_type_latch_reg[3..0] : dffe; + idle_state : dffe + WITH ( + power_up = "low" + ); + nominal_data[17..0] : dffe; + read_data_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_data_state : dffe + WITH ( + power_up = "low" + ); + read_first_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_first_state : dffe + WITH ( + power_up = "low" + ); + read_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_init_state : dffe + WITH ( + power_up = "low" + ); + read_last_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_last_state : dffe + WITH ( + power_up = "low" + ); + reconfig_counter_state : dffe + WITH ( + power_up = "low" + ); + reconfig_init_state : dffe + WITH ( + power_up = "low" + ); + reconfig_post_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_data_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_ena_state : dffe + WITH ( + power_up = "low" + ); + reconfig_wait_state : dffe + WITH ( + power_up = "low" + ); + reset_state : dffe + WITH ( + power_up = "high" + ); + shift_reg[17..0] : dffeas; + tmp_nominal_data_out_state : dffe; + tmp_seq_ena_state : dffe; + write_data_state : dffe + WITH ( + power_up = "low" + ); + write_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + write_init_state : dffe + WITH ( + power_up = "low" + ); + write_nominal_state : dffe + WITH ( + power_up = "low" + ); + add_sub5 : lpm_add_sub + WITH ( + LPM_WIDTH = 9 + ); + add_sub6 : lpm_add_sub + WITH ( + LPM_WIDTH = 8 + ); + cmpr7 : lpm_compare + WITH ( + LPM_WIDTH = 8 + ); + cntr1 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr12 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr13 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 6 + ); + cntr14 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + cntr15 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr2 : lpm_counter + WITH ( + lpm_direction = "UP", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr3 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + decode11 : lpm_decode + WITH ( + LPM_DECODES = 5, + LPM_WIDTH = 3 + ); + addr_counter_enable : WIRE; + addr_counter_out[7..0] : WIRE; + addr_counter_sload : WIRE; + addr_counter_sload_value[7..0] : WIRE; + addr_decoder_out[7..0] : WIRE; + c0_wire[7..0] : WIRE; + c1_wire[7..0] : WIRE; + c2_wire[7..0] : WIRE; + c3_wire[7..0] : WIRE; + c4_wire[7..0] : WIRE; + counter_param_latch[2..0] : WIRE; + counter_type_latch[3..0] : WIRE; + cuda_combout_wire[2..0] : WIRE; + dummy_scandataout : WIRE; + encode_out[2..0] : WIRE; + input_latch_enable : WIRE; + power_up : WIRE; + read_addr_counter_enable : WIRE; + read_addr_counter_out[7..0] : WIRE; + read_addr_counter_sload : WIRE; + read_addr_counter_sload_value[7..0] : WIRE; + read_addr_decoder_out[7..0] : WIRE; + read_nominal_out : WIRE; + reconfig_addr_counter_enable : WIRE; + reconfig_addr_counter_out[7..0] : WIRE; + reconfig_addr_counter_sload : WIRE; + reconfig_addr_counter_sload_value[7..0] : WIRE; + reconfig_done : WIRE; + reconfig_post_done : WIRE; + reconfig_width_counter_done : WIRE; + reconfig_width_counter_enable : WIRE; + reconfig_width_counter_sload : WIRE; + reconfig_width_counter_sload_value[5..0] : WIRE; + rotate_addr_counter_enable : WIRE; + rotate_addr_counter_out[7..0] : WIRE; + rotate_addr_counter_sload : WIRE; + rotate_addr_counter_sload_value[7..0] : WIRE; + rotate_decoder_wires[4..0] : WIRE; + rotate_width_counter_done : WIRE; + rotate_width_counter_enable : WIRE; + rotate_width_counter_sload : WIRE; + rotate_width_counter_sload_value[4..0] : WIRE; + scan_cache_address[7..0] : WIRE; + scan_cache_in : WIRE; + scan_cache_out : WIRE; + scan_cache_write_enable : WIRE; + sel_param_bypass_LF_unused : WIRE; + sel_param_c : WIRE; + sel_param_high_i_postscale : WIRE; + sel_param_low_r : WIRE; + sel_param_nominal_count : WIRE; + sel_param_odd_CP_unused : WIRE; + sel_type_c0 : WIRE; + sel_type_c1 : WIRE; + sel_type_c2 : WIRE; + sel_type_c3 : WIRE; + sel_type_c4 : WIRE; + sel_type_cplf : WIRE; + sel_type_m : WIRE; + sel_type_n : WIRE; + sel_type_vco : WIRE; + seq_addr_wire[7..0] : WIRE; + seq_sload_value[5..0] : WIRE; + shift_reg_clear : WIRE; + shift_reg_load_enable : WIRE; + shift_reg_load_nominal_enable : WIRE; + shift_reg_serial_in : WIRE; + shift_reg_serial_out : WIRE; + shift_reg_shift_enable : WIRE; + shift_reg_shift_nominal_enable : WIRE; + shift_reg_width_select[7..0] : WIRE; + w1565w : WIRE; + w1592w : WIRE; + w64w : WIRE; + width_counter_done : WIRE; + width_counter_enable : WIRE; + width_counter_sload : WIRE; + width_counter_sload_value[4..0] : WIRE; + width_decoder_out[4..0] : WIRE; + width_decoder_select[7..0] : WIRE; + write_from_rom : NODE; + +BEGIN + altsyncram4.address_a[] = scan_cache_address[]; + altsyncram4.clock0 = clock; + altsyncram4.data_a[] = ( scan_cache_in); + altsyncram4.wren_a = scan_cache_write_enable; + le_comb10.dataa = encode_out[0..0]; + le_comb10.datab = encode_out[1..1]; + le_comb10.datac = encode_out[2..2]; + le_comb8.dataa = encode_out[0..0]; + le_comb8.datab = encode_out[1..1]; + le_comb8.datac = encode_out[2..2]; + le_comb9.dataa = encode_out[0..0]; + le_comb9.datab = encode_out[1..1]; + le_comb9.datac = encode_out[2..2]; + areset_init_state_1.clk = clock; + areset_init_state_1.d = pll_scandone; + areset_state.clk = clock; + areset_state.d = (areset_init_state_1.q & (! reset)); + C0_data_state.clk = clock; + C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done))); + C0_ena_state.clk = clock; + C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done); + C1_data_state.clk = clock; + C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done))); + C1_ena_state.clk = clock; + C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done); + C2_data_state.clk = clock; + C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done))); + C2_ena_state.clk = clock; + C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done); + C3_data_state.clk = clock; + C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done))); + C3_ena_state.clk = clock; + C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done); + C4_data_state.clk = clock; + C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done))); + C4_ena_state.clk = clock; + C4_ena_state.d = reconfig_init_state.q; + configupdate2_state.clk = clock; + configupdate2_state.d = configupdate_state.q; + configupdate3_state.clk = (! clock); + configupdate3_state.d = configupdate2_state.q; + configupdate_state.clk = clock; + configupdate_state.d = reconfig_post_state.q; + counter_param_latch_reg[].clk = clock; + counter_param_latch_reg[].clrn = (! reset); + counter_param_latch_reg[].d = counter_param[]; + counter_param_latch_reg[].ena = input_latch_enable; + counter_type_latch_reg[].clk = clock; + counter_type_latch_reg[].clrn = (! reset); + counter_type_latch_reg[].d = counter_type[]; + counter_type_latch_reg[].ena = input_latch_enable; + idle_state.clk = clock; + idle_state.clrn = (! reset); + idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q); + nominal_data[].clk = clock; + nominal_data[].clrn = (! reset); + nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]); + read_data_nominal_state.clk = clock; + read_data_nominal_state.clrn = (! reset); + read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done))); + read_data_state.clk = clock; + read_data_state.clrn = (! reset); + read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done))); + read_first_nominal_state.clk = clock; + read_first_nominal_state.clrn = (! reset); + read_first_nominal_state.d = read_init_nominal_state.q; + read_first_state.clk = clock; + read_first_state.clrn = (! reset); + read_first_state.d = read_init_state.q; + read_init_nominal_state.clk = clock; + read_init_nominal_state.clrn = (! reset); + read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + read_init_state.clk = clock; + read_init_state.clrn = (! reset); + read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + read_last_nominal_state.clk = clock; + read_last_nominal_state.clrn = (! reset); + read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done)); + read_last_state.clk = clock; + read_last_state.clrn = (! reset); + read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done)); + reconfig_counter_state.clk = clock; + reconfig_counter_state.clrn = (! reset); + reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + reconfig_init_state.clk = clock; + reconfig_init_state.clrn = (! reset); + reconfig_init_state.d = (idle_state.q & reconfig); + reconfig_post_state.clk = clock; + reconfig_post_state.clrn = (! reset); + reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done))); + reconfig_seq_data_state.clk = clock; + reconfig_seq_data_state.clrn = (! reset); + reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done))); + reconfig_seq_ena_state.clk = clock; + reconfig_seq_ena_state.clrn = (! reset); + reconfig_seq_ena_state.d = tmp_seq_ena_state.q; + reconfig_wait_state.clk = clock; + reconfig_wait_state.clrn = (! reset); + reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done))); + reset_state.clk = clock; + reset_state.d = power_up; + reset_state.prn = (! reset); + shift_reg[].clk = clock; + shift_reg[].clrn = (! reset); + shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in))); + shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear); + shift_reg[].sclr = shift_reg_clear; + tmp_nominal_data_out_state.clk = clock; + tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q)); + tmp_seq_ena_state.clk = clock; + tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done)); + write_data_state.clk = clock; + write_data_state.clrn = (! reset); + write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done))); + write_init_nominal_state.clk = clock; + write_init_nominal_state.clrn = (! reset); + write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + write_init_state.clk = clock; + write_init_state.clrn = (! reset); + write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + write_nominal_state.clk = clock; + write_nominal_state.clrn = (! reset); + write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done))); + add_sub5.cin = B"0"; + add_sub5.dataa[] = ( B"0", shift_reg[8..1].q); + add_sub5.datab[] = ( B"0", shift_reg[17..10].q); + add_sub6.cin = data_in[0..0]; + add_sub6.dataa[] = ( data_in[8..1]); + cmpr7.dataa[] = ( data_in[7..0]); + cmpr7.datab[] = B"00000001"; + cntr1.clock = clock; + cntr1.cnt_en = addr_counter_enable; + cntr1.data[] = addr_counter_sload_value[]; + cntr1.sload = addr_counter_sload; + cntr12.clock = clock; + cntr12.cnt_en = reconfig_addr_counter_enable; + cntr12.data[] = reconfig_addr_counter_sload_value[]; + cntr12.sload = reconfig_addr_counter_sload; + cntr13.clock = clock; + cntr13.cnt_en = reconfig_width_counter_enable; + cntr13.data[] = reconfig_width_counter_sload_value[]; + cntr13.sload = reconfig_width_counter_sload; + cntr14.clock = clock; + cntr14.cnt_en = rotate_width_counter_enable; + cntr14.data[] = rotate_width_counter_sload_value[]; + cntr14.sload = rotate_width_counter_sload; + cntr15.clock = clock; + cntr15.cnt_en = rotate_addr_counter_enable; + cntr15.data[] = rotate_addr_counter_sload_value[]; + cntr15.sload = rotate_addr_counter_sload; + cntr2.clock = clock; + cntr2.cnt_en = read_addr_counter_enable; + cntr2.data[] = read_addr_counter_sload_value[]; + cntr2.sload = read_addr_counter_sload; + cntr3.clock = clock; + cntr3.cnt_en = width_counter_enable; + cntr3.data[] = width_counter_sload_value[]; + cntr3.sload = width_counter_sload; + decode11.data[] = cuda_combout_wire[]; + addr_counter_enable = (write_data_state.q # write_nominal_state.q); + addr_counter_out[] = cntr1.q[]; + addr_counter_sload = (write_init_state.q # write_init_nominal_state.q); + addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q)); + addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r))); + busy = ((! idle_state.q) # areset_state.q); + c0_wire[] = B"01000111"; + c1_wire[] = B"01011001"; + c2_wire[] = B"01101011"; + c3_wire[] = B"01111101"; + c4_wire[] = B"10001111"; + counter_param_latch[] = counter_param_latch_reg[].q; + counter_type_latch[] = counter_type_latch_reg[].q; + cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout); + data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out))); + dummy_scandataout = pll_scandataout; + encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q)); + input_latch_enable = (idle_state.q & (write_param # read_param)); + pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q)); + pll_configupdate = (configupdate_state.q & (! configupdate3_state.q)); + pll_scanclk = clock; + pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q); + pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q)); + power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q)); + read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q); + read_addr_counter_out[] = cntr2.q[]; + read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q); + read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q)); + read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0")); + read_nominal_out = tmp_nominal_data_out_state.q; + reconfig_addr_counter_enable = reconfig_seq_data_state.q; + reconfig_addr_counter_out[] = cntr12.q[]; + reconfig_addr_counter_sload = reconfig_seq_ena_state.q; + reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]); + reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout))); + reconfig_post_done = pll_scandone; + reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5])); + reconfig_width_counter_enable = reconfig_seq_data_state.q; + reconfig_width_counter_sload = reconfig_seq_ena_state.q; + reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]); + rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_addr_counter_out[] = cntr15.q[]; + rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4])); + rotate_decoder_wires[] = decode11.eq[]; + rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4])); + rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_width_counter_sload_value[] = B"10010"; + scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable)); + scan_cache_in = shift_reg_serial_out; + scan_cache_out = altsyncram4.q_a[0..0]; + scan_cache_write_enable = (write_data_state.q # write_nominal_state.q); + sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2])); + sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]); + sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]); + sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + seq_addr_wire[] = B"00110101"; + seq_sload_value[] = B"110110"; + shift_reg_clear = (read_init_state.q # read_init_nominal_state.q); + shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + shift_reg_serial_in = scan_cache_out; + shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7])); + shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q); + shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q); + shift_reg_width_select[] = width_decoder_select[]; + w1565w = B"0"; + w1592w = B"0"; + w64w = B"0"; + width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4])); + width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q); + width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q); + width_counter_sload_value[] = width_decoder_out[]; + width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0")); + width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused))); + write_from_rom = GND; +END; +--VALID FILE diff --git a/FPGA_Quartus_13.1/altpll_reconfig1_pllrcfg_t4q.tdf b/FPGA_Quartus_13.1/altpll_reconfig1_pllrcfg_t4q.tdf new file mode 100644 index 0000000..fae939f --- /dev/null +++ b/FPGA_Quartus_13.1/altpll_reconfig1_pllrcfg_t4q.tdf @@ -0,0 +1,582 @@ +--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param +--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END + + +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +include "altsyncram.inc"; +FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad) +WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT) +RETURNS ( combout, cout); +FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS) +RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]); +FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0]) +WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT) +RETURNS ( aeb, agb, ageb, alb, aleb, aneb); +FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown) +WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width) +RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]); +FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable) +WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH) +RETURNS ( eq[LPM_DECODES-1..0]); + +--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 +OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW"; + +SUBDESIGN altpll_reconfig1_pllrcfg_t4q +( + busy : output; + clock : input; + counter_param[2..0] : input; + counter_type[3..0] : input; + data_in[8..0] : input; + data_out[8..0] : output; + pll_areset : output; + pll_areset_in : input; + pll_configupdate : output; + pll_scanclk : output; + pll_scanclkena : output; + pll_scandata : output; + pll_scandataout : input; + pll_scandone : input; + read_param : input; + reconfig : input; + reset : input; + write_param : input; +) +VARIABLE + altsyncram4 : altsyncram + WITH ( + NUMWORDS_A = 144, + OPERATION_MODE = "SINGLE_PORT", + WIDTH_A = 1, + WIDTH_BYTEENA_A = 1, + WIDTHAD_A = 8 + ); + le_comb10 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "F0F0", + SUM_LUTC_INPUT = "datac" + ); + le_comb8 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "AAAA", + SUM_LUTC_INPUT = "datac" + ); + le_comb9 : cycloneiii_lcell_comb + WITH ( + DONT_TOUCH = "on", + LUT_MASK = "CCCC", + SUM_LUTC_INPUT = "datac" + ); + areset_init_state_1 : dffe; + areset_state : dffe; + C0_data_state : dffe; + C0_ena_state : dffe; + C1_data_state : dffe; + C1_ena_state : dffe; + C2_data_state : dffe; + C2_ena_state : dffe; + C3_data_state : dffe; + C3_ena_state : dffe; + C4_data_state : dffe; + C4_ena_state : dffe; + configupdate2_state : dffe; + configupdate3_state : dffe; + configupdate_state : dffe; + counter_param_latch_reg[2..0] : dffe; + counter_type_latch_reg[3..0] : dffe; + idle_state : dffe + WITH ( + power_up = "low" + ); + nominal_data[17..0] : dffe; + read_data_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_data_state : dffe + WITH ( + power_up = "low" + ); + read_first_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_first_state : dffe + WITH ( + power_up = "low" + ); + read_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_init_state : dffe + WITH ( + power_up = "low" + ); + read_last_nominal_state : dffe + WITH ( + power_up = "low" + ); + read_last_state : dffe + WITH ( + power_up = "low" + ); + reconfig_counter_state : dffe + WITH ( + power_up = "low" + ); + reconfig_init_state : dffe + WITH ( + power_up = "low" + ); + reconfig_post_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_data_state : dffe + WITH ( + power_up = "low" + ); + reconfig_seq_ena_state : dffe + WITH ( + power_up = "low" + ); + reconfig_wait_state : dffe + WITH ( + power_up = "low" + ); + reset_state : dffe + WITH ( + power_up = "high" + ); + shift_reg[17..0] : dffeas; + tmp_nominal_data_out_state : dffe; + tmp_seq_ena_state : dffe; + write_data_state : dffe + WITH ( + power_up = "low" + ); + write_init_nominal_state : dffe + WITH ( + power_up = "low" + ); + write_init_state : dffe + WITH ( + power_up = "low" + ); + write_nominal_state : dffe + WITH ( + power_up = "low" + ); + add_sub5 : lpm_add_sub + WITH ( + LPM_WIDTH = 9 + ); + add_sub6 : lpm_add_sub + WITH ( + LPM_WIDTH = 8 + ); + cmpr7 : lpm_compare + WITH ( + LPM_WIDTH = 8 + ); + cntr1 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr12 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr13 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 6 + ); + cntr14 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + cntr15 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_modulus = 144, + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr2 : lpm_counter + WITH ( + lpm_direction = "UP", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 8 + ); + cntr3 : lpm_counter + WITH ( + lpm_direction = "DOWN", + lpm_port_updown = "PORT_UNUSED", + lpm_width = 5 + ); + decode11 : lpm_decode + WITH ( + LPM_DECODES = 5, + LPM_WIDTH = 3 + ); + addr_counter_enable : WIRE; + addr_counter_out[7..0] : WIRE; + addr_counter_sload : WIRE; + addr_counter_sload_value[7..0] : WIRE; + addr_decoder_out[7..0] : WIRE; + c0_wire[7..0] : WIRE; + c1_wire[7..0] : WIRE; + c2_wire[7..0] : WIRE; + c3_wire[7..0] : WIRE; + c4_wire[7..0] : WIRE; + counter_param_latch[2..0] : WIRE; + counter_type_latch[3..0] : WIRE; + cuda_combout_wire[2..0] : WIRE; + dummy_scandataout : WIRE; + encode_out[2..0] : WIRE; + input_latch_enable : WIRE; + power_up : WIRE; + read_addr_counter_enable : WIRE; + read_addr_counter_out[7..0] : WIRE; + read_addr_counter_sload : WIRE; + read_addr_counter_sload_value[7..0] : WIRE; + read_addr_decoder_out[7..0] : WIRE; + read_nominal_out : WIRE; + reconfig_addr_counter_enable : WIRE; + reconfig_addr_counter_out[7..0] : WIRE; + reconfig_addr_counter_sload : WIRE; + reconfig_addr_counter_sload_value[7..0] : WIRE; + reconfig_done : WIRE; + reconfig_post_done : WIRE; + reconfig_width_counter_done : WIRE; + reconfig_width_counter_enable : WIRE; + reconfig_width_counter_sload : WIRE; + reconfig_width_counter_sload_value[5..0] : WIRE; + rotate_addr_counter_enable : WIRE; + rotate_addr_counter_out[7..0] : WIRE; + rotate_addr_counter_sload : WIRE; + rotate_addr_counter_sload_value[7..0] : WIRE; + rotate_decoder_wires[4..0] : WIRE; + rotate_width_counter_done : WIRE; + rotate_width_counter_enable : WIRE; + rotate_width_counter_sload : WIRE; + rotate_width_counter_sload_value[4..0] : WIRE; + scan_cache_address[7..0] : WIRE; + scan_cache_in : WIRE; + scan_cache_out : WIRE; + scan_cache_write_enable : WIRE; + sel_param_bypass_LF_unused : WIRE; + sel_param_c : WIRE; + sel_param_high_i_postscale : WIRE; + sel_param_low_r : WIRE; + sel_param_nominal_count : WIRE; + sel_param_odd_CP_unused : WIRE; + sel_type_c0 : WIRE; + sel_type_c1 : WIRE; + sel_type_c2 : WIRE; + sel_type_c3 : WIRE; + sel_type_c4 : WIRE; + sel_type_cplf : WIRE; + sel_type_m : WIRE; + sel_type_n : WIRE; + sel_type_vco : WIRE; + seq_addr_wire[7..0] : WIRE; + seq_sload_value[5..0] : WIRE; + shift_reg_clear : WIRE; + shift_reg_load_enable : WIRE; + shift_reg_load_nominal_enable : WIRE; + shift_reg_serial_in : WIRE; + shift_reg_serial_out : WIRE; + shift_reg_shift_enable : WIRE; + shift_reg_shift_nominal_enable : WIRE; + shift_reg_width_select[7..0] : WIRE; + w1565w : WIRE; + w1592w : WIRE; + w64w : WIRE; + width_counter_done : WIRE; + width_counter_enable : WIRE; + width_counter_sload : WIRE; + width_counter_sload_value[4..0] : WIRE; + width_decoder_out[4..0] : WIRE; + width_decoder_select[7..0] : WIRE; + write_from_rom : NODE; + +BEGIN + altsyncram4.address_a[] = scan_cache_address[]; + altsyncram4.clock0 = clock; + altsyncram4.data_a[] = ( scan_cache_in); + altsyncram4.wren_a = scan_cache_write_enable; + le_comb10.dataa = encode_out[0..0]; + le_comb10.datab = encode_out[1..1]; + le_comb10.datac = encode_out[2..2]; + le_comb8.dataa = encode_out[0..0]; + le_comb8.datab = encode_out[1..1]; + le_comb8.datac = encode_out[2..2]; + le_comb9.dataa = encode_out[0..0]; + le_comb9.datab = encode_out[1..1]; + le_comb9.datac = encode_out[2..2]; + areset_init_state_1.clk = clock; + areset_init_state_1.d = pll_scandone; + areset_state.clk = clock; + areset_state.d = (areset_init_state_1.q & (! reset)); + C0_data_state.clk = clock; + C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done))); + C0_ena_state.clk = clock; + C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done); + C1_data_state.clk = clock; + C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done))); + C1_ena_state.clk = clock; + C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done); + C2_data_state.clk = clock; + C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done))); + C2_ena_state.clk = clock; + C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done); + C3_data_state.clk = clock; + C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done))); + C3_ena_state.clk = clock; + C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done); + C4_data_state.clk = clock; + C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done))); + C4_ena_state.clk = clock; + C4_ena_state.d = reconfig_init_state.q; + configupdate2_state.clk = clock; + configupdate2_state.d = configupdate_state.q; + configupdate3_state.clk = (! clock); + configupdate3_state.d = configupdate2_state.q; + configupdate_state.clk = clock; + configupdate_state.d = reconfig_post_state.q; + counter_param_latch_reg[].clk = clock; + counter_param_latch_reg[].clrn = (! reset); + counter_param_latch_reg[].d = counter_param[]; + counter_param_latch_reg[].ena = input_latch_enable; + counter_type_latch_reg[].clk = clock; + counter_type_latch_reg[].clrn = (! reset); + counter_type_latch_reg[].d = counter_type[]; + counter_type_latch_reg[].ena = input_latch_enable; + idle_state.clk = clock; + idle_state.clrn = (! reset); + idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q); + nominal_data[].clk = clock; + nominal_data[].clrn = (! reset); + nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]); + read_data_nominal_state.clk = clock; + read_data_nominal_state.clrn = (! reset); + read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done))); + read_data_state.clk = clock; + read_data_state.clrn = (! reset); + read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done))); + read_first_nominal_state.clk = clock; + read_first_nominal_state.clrn = (! reset); + read_first_nominal_state.d = read_init_nominal_state.q; + read_first_state.clk = clock; + read_first_state.clrn = (! reset); + read_first_state.d = read_init_state.q; + read_init_nominal_state.clk = clock; + read_init_nominal_state.clrn = (! reset); + read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + read_init_state.clk = clock; + read_init_state.clrn = (! reset); + read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + read_last_nominal_state.clk = clock; + read_last_nominal_state.clrn = (! reset); + read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done)); + read_last_state.clk = clock; + read_last_state.clrn = (! reset); + read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done)); + reconfig_counter_state.clk = clock; + reconfig_counter_state.clrn = (! reset); + reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + reconfig_init_state.clk = clock; + reconfig_init_state.clrn = (! reset); + reconfig_init_state.d = (idle_state.q & reconfig); + reconfig_post_state.clk = clock; + reconfig_post_state.clrn = (! reset); + reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done))); + reconfig_seq_data_state.clk = clock; + reconfig_seq_data_state.clrn = (! reset); + reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done))); + reconfig_seq_ena_state.clk = clock; + reconfig_seq_ena_state.clrn = (! reset); + reconfig_seq_ena_state.d = tmp_seq_ena_state.q; + reconfig_wait_state.clk = clock; + reconfig_wait_state.clrn = (! reset); + reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done))); + reset_state.clk = clock; + reset_state.d = power_up; + reset_state.prn = (! reset); + shift_reg[].clk = clock; + shift_reg[].clrn = (! reset); + shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in))); + shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear); + shift_reg[].sclr = shift_reg_clear; + tmp_nominal_data_out_state.clk = clock; + tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q)); + tmp_seq_ena_state.clk = clock; + tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done)); + write_data_state.clk = clock; + write_data_state.clrn = (! reset); + write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done))); + write_init_nominal_state.clk = clock; + write_init_nominal_state.clrn = (! reset); + write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + write_init_state.clk = clock; + write_init_state.clrn = (! reset); + write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + write_nominal_state.clk = clock; + write_nominal_state.clrn = (! reset); + write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done))); + add_sub5.cin = B"0"; + add_sub5.dataa[] = ( B"0", shift_reg[8..1].q); + add_sub5.datab[] = ( B"0", shift_reg[17..10].q); + add_sub6.cin = data_in[0..0]; + add_sub6.dataa[] = ( data_in[8..1]); + cmpr7.dataa[] = ( data_in[7..0]); + cmpr7.datab[] = B"00000001"; + cntr1.clock = clock; + cntr1.cnt_en = addr_counter_enable; + cntr1.data[] = addr_counter_sload_value[]; + cntr1.sload = addr_counter_sload; + cntr12.clock = clock; + cntr12.cnt_en = reconfig_addr_counter_enable; + cntr12.data[] = reconfig_addr_counter_sload_value[]; + cntr12.sload = reconfig_addr_counter_sload; + cntr13.clock = clock; + cntr13.cnt_en = reconfig_width_counter_enable; + cntr13.data[] = reconfig_width_counter_sload_value[]; + cntr13.sload = reconfig_width_counter_sload; + cntr14.clock = clock; + cntr14.cnt_en = rotate_width_counter_enable; + cntr14.data[] = rotate_width_counter_sload_value[]; + cntr14.sload = rotate_width_counter_sload; + cntr15.clock = clock; + cntr15.cnt_en = rotate_addr_counter_enable; + cntr15.data[] = rotate_addr_counter_sload_value[]; + cntr15.sload = rotate_addr_counter_sload; + cntr2.clock = clock; + cntr2.cnt_en = read_addr_counter_enable; + cntr2.data[] = read_addr_counter_sload_value[]; + cntr2.sload = read_addr_counter_sload; + cntr3.clock = clock; + cntr3.cnt_en = width_counter_enable; + cntr3.data[] = width_counter_sload_value[]; + cntr3.sload = width_counter_sload; + decode11.data[] = cuda_combout_wire[]; + addr_counter_enable = (write_data_state.q # write_nominal_state.q); + addr_counter_out[] = cntr1.q[]; + addr_counter_sload = (write_init_state.q # write_init_nominal_state.q); + addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q)); + addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r))); + busy = ((! idle_state.q) # areset_state.q); + c0_wire[] = B"01000111"; + c1_wire[] = B"01011001"; + c2_wire[] = B"01101011"; + c3_wire[] = B"01111101"; + c4_wire[] = B"10001111"; + counter_param_latch[] = counter_param_latch_reg[].q; + counter_type_latch[] = counter_type_latch_reg[].q; + cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout); + data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out))); + dummy_scandataout = pll_scandataout; + encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q)); + input_latch_enable = (idle_state.q & (write_param # read_param)); + pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q)); + pll_configupdate = (configupdate_state.q & (! configupdate3_state.q)); + pll_scanclk = clock; + pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q); + pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q)); + power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q)); + read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q); + read_addr_counter_out[] = cntr2.q[]; + read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q); + read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q)); + read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0")); + read_nominal_out = tmp_nominal_data_out_state.q; + reconfig_addr_counter_enable = reconfig_seq_data_state.q; + reconfig_addr_counter_out[] = cntr12.q[]; + reconfig_addr_counter_sload = reconfig_seq_ena_state.q; + reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]); + reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout))); + reconfig_post_done = pll_scandone; + reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5])); + reconfig_width_counter_enable = reconfig_seq_data_state.q; + reconfig_width_counter_sload = reconfig_seq_ena_state.q; + reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]); + rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_addr_counter_out[] = cntr15.q[]; + rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4])); + rotate_decoder_wires[] = decode11.eq[]; + rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4])); + rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q); + rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q); + rotate_width_counter_sload_value[] = B"10010"; + scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable)); + scan_cache_in = shift_reg_serial_out; + scan_cache_out = altsyncram4.q_a[0..0]; + scan_cache_write_enable = (write_data_state.q # write_nominal_state.q); + sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2])); + sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2])); + sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]); + sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]); + sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3])); + sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]); + sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3])); + seq_addr_wire[] = B"00110101"; + seq_sload_value[] = B"110110"; + shift_reg_clear = (read_init_state.q # read_init_nominal_state.q); + shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]))); + shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])); + shift_reg_serial_in = scan_cache_out; + shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7])); + shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q); + shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q); + shift_reg_width_select[] = width_decoder_select[]; + w1565w = B"0"; + w1592w = B"0"; + w64w = B"0"; + width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4])); + width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q); + width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q); + width_counter_sload_value[] = width_decoder_out[]; + width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0")); + width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused))); + write_from_rom = GND; +END; +--VALID FILE diff --git a/FPGA_Quartus_13.1/firebee1.asm.rpt b/FPGA_Quartus_13.1/firebee1.asm.rpt new file mode 100644 index 0000000..7ffb13e --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.asm.rpt @@ -0,0 +1,128 @@ +Assembler report for firebee1 +Wed Dec 15 02:25:13 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof + 6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Wed Dec 15 02:25:13 2010 ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Device ; EP3C40F484C6 ; ++-----------------------+---------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+------------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+------------+---------------+ +; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ; +; Hexadecimal Output File start address ; 0XE0700000 ; 0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; Off ; Off ; +; Use configuration device ; Off ; Off ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Enable OCT_DONE ; Off ; Off ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+------------+---------------+ + + ++------------------------------+ +; Assembler Generated Files ; ++------------------------------+ +; File Name ; ++------------------------------+ +; C:/FireBee/FPGA/firebee1.sof ; +; C:/FireBee/FPGA/firebee1.rbf ; ++------------------------------+ + + ++--------------------------------------------------------+ +; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ; ++----------------+---------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------+ +; Device ; EP3C40F484C6 ; +; JTAG usercode ; 0xFFFFFFFF ; +; Checksum ; 0x0085E8C6 ; ++----------------+---------------------------------------+ + + ++--------------------------------------------------------+ +; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ; ++---------------------+----------------------------------+ +; Option ; Setting ; ++---------------------+----------------------------------+ +; Raw Binary File ; ; +; Compression Ratio ; 2 ; ++---------------------+----------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II Assembler + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:25:08 2010 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +Info: Writing out detailed assembly data for power analysis +Info: Assembler is generating device programming files +Info: Quartus II Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 291 megabytes + Info: Processing ended: Wed Dec 15 02:25:13 2010 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:05 + + diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf new file mode 100644 index 0000000..46507a2 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -0,0 +1,5837 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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192 680) +) +(connector + (pt 536 720) + (pt 408 720) +) +(connector + (pt 1064 808) + (pt 1064 616) +) +(connector + (pt 1072 816) + (pt 1072 592) +) +(connector + (pt 472 672) + (pt 472 664) +) +(connector + (pt 472 640) + (pt 472 616) +) +(connector + (pt 512 624) + (pt 512 640) +) +(connector + (pt 536 720) + (pt 536 592) +) +(connector + (pt 536 592) + (pt 608 592) +) +(connector + (pt 472 616) + (pt 608 616) +) +(connector + (pt 512 640) + (pt 608 640) +) +(connector + (pt 472 664) + (pt 608 664) +) +(connector + (pt 408 688) + (pt 608 688) +) +(connector + (pt 984 592) + (pt 1072 592) +) +(connector + (pt 984 616) + (pt 1064 616) +) +(connector + (text "FB_ADR[5..2]" (rect 82 568 168 583)(font "Arial" )) + (pt 192 584) + (pt 72 584) + (bus) +) +(connector + (pt 1064 808) + (pt 80 808) +) +(connector + (pt 192 656) + (pt 80 656) +) +(connector + (pt 80 656) + (pt 80 808) +) +(connector + (pt 1072 816) + (pt 72 816) +) +(connector + (pt 192 640) + (pt 72 640) +) +(connector + (pt 72 640) + (pt 72 816) +) +(connector + (text "FB_ADR[8..6]" (rect 82 584 168 599)(font "Arial" )) + (pt 192 600) + (pt 72 600) + (bus) +) +(connector + (text "VR_RD" (rect 98 512 146 527)(font "Arial" )) + (pt 64 528) + (pt 192 528) +) +(connector + (text "VR_WR" (rect 98 528 148 543)(font "Arial" )) + (pt 64 544) + (pt 192 544) +) +(connector + (text "VR_D[8..0]" (rect 1170 464 1238 479)(font "Arial" )) + (pt 1144 480) + (pt 1264 480) + (bus) +) +(connector + (text "VDQS[3..0]" (rect 1674 504 1743 519)(font "Arial" )) + (pt 2040 544) + (pt 1960 544) + (bus) +) +(connector + (pt 1672 544) + (pt 1888 544) + (bus) +) +(connector + (pt 1888 544) + (pt 1888 568) + (bus) +) +(connector + (text "VDM[3..0]" (rect 1682 528 1742 543)(font "Arial" )) + (pt 1944 568) + (pt 1888 568) + (bus) +) +(connector + (pt 1672 520) + (pt 1960 520) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 520) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1674 560 1799 575)(font "Arial" )) + (pt 1672 576) + (pt 1792 576) +) +(connector + (text "VR_WR" (rect 1698 592 1748 607)(font "Arial" )) + (pt 1672 608) + (pt 1792 608) +) +(connector + (text "VR_BUSY" (rect 418 496 482 511)(font "Arial" )) + (pt 408 512) + (pt 480 512) +) +(connector + (text "VR_BUSY" (rect 1170 448 1234 463)(font "Arial" )) + (pt 1144 464) + (pt 1264 464) +) +(connector + (text "VR_RD" (rect 1698 576 1746 591)(font "Arial" )) + (pt 1792 592) + (pt 1672 592) +) +(connector + (text "nRSTO" (rect -86 680 -39 695)(font "Arial" )) + (pt -96 696) + (pt -16 696) +) +(connector + (pt 32 696) + (pt 192 696) +) +(connector + (text "FB_AD[24..16]" (rect 82 552 174 567)(font "Arial" )) + (pt 72 568) + (pt 192 568) + (bus) +) +(connector + (text "CLK48M" (rect 538 552 593 567)(font "Arial" )) + (pt 528 568) + (pt 608 568) +) +(connector + (text "CLK_VIDEO" (rect 1162 552 1241 567)(font "Arial" )) + (pt 984 568) + (pt 1264 568) +) +(connector + (text "CLK33M" (rect 1202 584 1257 599)(font "Arial" )) + (pt 1264 600) + (pt 1192 600) +) +(connector + (text "CLK500k" (rect 802 232 862 247)(font "Arial" )) + (pt 768 248) + (pt 864 248) +) +(connector + (text "CLK2M4576" (rect 802 256 882 271)(font "Arial" )) + (pt 768 272) + (pt 864 272) +) +(connector + (text "CLK24M576" (rect 802 280 882 295)(font "Arial" )) + (pt 768 296) + (pt 864 296) +) +(connector + (text "nRSTO" (rect 1018 424 1065 439)(font "Arial" )) + (pt 1008 440) + (pt 1096 440) +) +(connector + (pt 768 320) + (pt 872 320) +) +(connector + (pt 872 432) + (pt 944 432) +) +(connector + (pt 840 448) + (pt 944 448) +) +(connector + (pt 872 320) + (pt 872 432) +) +(connector + (text "HSYNC" (rect 2314 -96 2363 -81)(font "Arial" )) + (pt 2304 -80) + (pt 2424 -80) +) +(connector + (pt 2424 -80) + (pt 2464 -80) +) +(connector + (text "VSYNC" (rect 1746 -80 1793 -65)(font "Arial" )) + (pt 1736 -64) + (pt 1856 -64) +) +(junction (pt 2504 760)) +(junction (pt 400 248)) +(junction (pt 1856 -64)) +(junction (pt 2424 -80)) diff --git a/FPGA_Quartus_13.1/firebee1.done b/FPGA_Quartus_13.1/firebee1.done new file mode 100644 index 0000000..1674c93 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.done @@ -0,0 +1 @@ +Wed Dec 15 02:25:24 2010 diff --git a/FPGA_Quartus_13.1/firebee1.dpf b/FPGA_Quartus_13.1/firebee1.dpf new file mode 100644 index 0000000..f0b3ecc --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.dpf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/firebee1.fit.rpt b/FPGA_Quartus_13.1/firebee1.fit.rpt new file mode 100644 index 0000000..e3df129 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.fit.rpt @@ -0,0 +1,6866 @@ +Fitter report for firebee1 +Wed Dec 15 02:25:03 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. I/O Assignment Warnings + 6. Fitter Netlist Optimizations + 7. Ignored Assignments + 8. Incremental Compilation Preservation Summary + 9. Incremental Compilation Partition Settings + 10. Incremental Compilation Placement Preservation + 11. Pin-Out File + 12. Fitter Resource Usage Summary + 13. Input Pins + 14. Output Pins + 15. Bidir Pins + 16. Dual Purpose and Dedicated Pins + 17. I/O Bank Usage + 18. All Package Pins + 19. PLL Summary + 20. PLL Usage + 21. Output Pin Default Load For Reported TCO + 22. Fitter Resource Utilization by Entity + 23. Delay Chain Summary + 24. Pad To Core Delay Chain Fanout + 25. Control Signals + 26. Global & Other Fast Signals + 27. Non-Global High Fan-Out Signals + 28. Fitter RAM Summary + 29. Fitter DSP Block Usage Summary + 30. DSP Block Details + 31. Interconnect Usage Summary + 32. LAB Logic Elements + 33. LAB-wide Signals + 34. LAB Signals Sourced + 35. LAB Signals Sourced Out + 36. LAB Distinct Inputs + 37. I/O Rules Summary + 38. I/O Rules Details + 39. I/O Rules Matrix + 40. Fitter Device Options + 41. Operating Settings and Conditions + 42. Estimated Delay Added for Hold Timing + 43. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Wed Dec 15 02:25:02 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Device ; EP3C40F484C6 ; +; Timing Models ; Final ; +; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; +; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ; +; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; +; Total registers ; 4749 ; +; Total pins ; 295 / 332 ( 89 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; +; Total PLLs ; 4 / 4 ( 100 % ) ; ++------------------------------------+----------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ +; Device ; EP3C40F484C6 ; ; +; Use TimeQuest Timing Analyzer ; Off ; On ; +; Nominal Core Supply Voltage ; 1.2V ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVTTL ; ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ; +; Perform Register Duplication for Performance ; On ; Off ; +; Physical Synthesis Effort Level ; Fast ; Normal ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Optimize Hold Timing ; All Paths ; All Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; SSN Optimization ; Off ; Off ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; +; Treat Bidirectional Pin as Output Pin ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Synchronizer Identification ; Off ; Off ; +; Enable Beneficial Skew Optimization ; On ; On ; +; Optimize Design for Metastability ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Use Best Effort Settings for Compilation ; Off ; Off ; ++----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++------------------------------------------------------+ +; I/O Assignment Warnings ; ++---------------+--------------------------------------+ +; Pin Name ; Reason ; ++---------------+--------------------------------------+ +; LP_STR ; Missing drive strength ; +; nACSI_ACK ; Missing drive strength ; +; nACSI_RESET ; Missing drive strength ; +; nACSI_CS ; Missing drive strength ; +; ACSI_DIR ; Missing drive strength ; +; ACSI_A1 ; Missing drive strength ; +; nSCSI_ACK ; Missing drive strength ; +; nSCSI_ATN ; Missing drive strength ; +; SCSI_DIR ; Missing drive strength ; +; MIDI_OLR ; Missing drive strength ; +; MIDI_TLR ; Missing drive strength ; +; TxD ; Missing drive strength ; +; RTS ; Missing drive strength ; +; DTR ; Missing drive strength ; +; IDE_RES ; Missing drive strength ; +; nIDE_CS0 ; Missing drive strength ; +; nIDE_CS1 ; Missing drive strength ; +; nIDE_WR ; Missing drive strength ; +; nIDE_RD ; Missing drive strength ; +; nCF_CS0 ; Missing drive strength ; +; nCF_CS1 ; Missing drive strength ; +; nROM3 ; Missing drive strength ; +; nROM4 ; Missing drive strength ; +; nRP_UDS ; Missing drive strength ; +; nRP_LDS ; Missing drive strength ; +; nSDSEL ; Missing drive strength ; +; nWR_GATE ; Missing drive strength ; +; nWR ; Missing drive strength ; +; YM_QA ; Missing drive strength ; +; YM_QB ; Missing drive strength ; +; YM_QC ; Missing drive strength ; +; SD_CLK ; Missing drive strength ; +; DSA_D ; Missing drive strength ; +; nVWE ; Missing slew rate ; +; nVCAS ; Missing slew rate ; +; nVRAS ; Missing slew rate ; +; nVCS ; Missing slew rate ; +; TIN0 ; Missing drive strength ; +; nDREQ1 ; Missing drive strength ; +; LED_FPGA_OK ; Missing slew rate ; +; VCKE ; Missing slew rate ; +; nFB_TA ; Missing drive strength ; +; nDDR_CLK ; Missing slew rate ; +; DDR_CLK ; Missing slew rate ; +; VSYNC_PAD ; Missing slew rate ; +; HSYNC_PAD ; Missing slew rate ; +; nBLANK_PAD ; Missing slew rate ; +; PIXEL_CLK_PAD ; Missing slew rate ; +; nSYNC ; Missing slew rate ; +; nMOT_ON ; Missing drive strength ; +; nSTEP_DIR ; Missing drive strength ; +; nSTEP ; Missing drive strength ; +; LPDIR ; Missing drive strength ; +; BA[1] ; Missing slew rate ; +; BA[0] ; Missing slew rate ; +; nIRQ[7] ; Missing drive strength ; +; nIRQ[6] ; Missing drive strength ; +; nIRQ[5] ; Missing drive strength ; +; nIRQ[4] ; Missing drive strength and slew rate ; +; nIRQ[3] ; Missing drive strength and slew rate ; +; nIRQ[2] ; Missing drive strength and slew rate ; +; VA[12] ; Missing slew rate ; +; VA[11] ; Missing slew rate ; +; VA[10] ; Missing slew rate ; +; VA[9] ; Missing slew rate ; +; VA[8] ; Missing slew rate ; +; VA[7] ; Missing slew rate ; +; VA[6] ; Missing slew rate ; +; VA[5] ; Missing slew rate ; +; VA[4] ; Missing slew rate ; +; VA[3] ; Missing slew rate ; +; VA[2] ; Missing slew rate ; +; VA[1] ; Missing slew rate ; +; VA[0] ; Missing slew rate ; +; VB[7] ; Missing slew rate ; +; VB[6] ; Missing slew rate ; +; VB[5] ; Missing slew rate ; +; VB[4] ; Missing slew rate ; +; VB[3] ; Missing slew rate ; +; VB[2] ; Missing slew rate ; +; VB[1] ; Missing slew rate ; +; VB[0] ; Missing slew rate ; +; VDM[3] ; Missing slew rate ; +; VDM[2] ; Missing slew rate ; +; VDM[1] ; Missing slew rate ; +; VDM[0] ; Missing slew rate ; +; VG[7] ; Missing slew rate ; +; VG[6] ; Missing slew rate ; +; VG[5] ; Missing slew rate ; +; VG[4] ; Missing slew rate ; +; VG[3] ; Missing slew rate ; +; VG[2] ; Missing slew rate ; +; VG[1] ; Missing slew rate ; +; VG[0] ; Missing slew rate ; +; VR[7] ; Missing slew rate ; +; VR[6] ; Missing slew rate ; +; VR[5] ; Missing slew rate ; +; VR[4] ; Missing slew rate ; +; VR[3] ; Missing slew rate ; +; VR[2] ; Missing slew rate ; +; VR[1] ; Missing slew rate ; +; VR[0] ; Missing slew rate ; +; VD[31] ; Missing slew rate ; +; VD[30] ; Missing slew rate ; +; VD[29] ; Missing slew rate ; +; VD[28] ; Missing slew rate ; +; VD[27] ; Missing slew rate ; +; VD[26] ; Missing slew rate ; +; VD[25] ; Missing slew rate ; +; VD[24] ; Missing slew rate ; +; VD[23] ; Missing slew rate ; +; VD[22] ; Missing slew rate ; +; VD[21] ; Missing slew rate ; +; VD[20] ; Missing slew rate ; +; VD[19] ; Missing slew rate ; +; VD[18] ; Missing slew rate ; +; VD[17] ; Missing slew rate ; +; VD[16] ; Missing slew rate ; +; VD[15] ; Missing slew rate ; +; VD[14] ; Missing slew rate ; +; VD[13] ; Missing slew rate ; +; VD[12] ; Missing slew rate ; +; VD[11] ; Missing slew rate ; +; VD[10] ; Missing slew rate ; +; VD[9] ; Missing slew rate ; +; VD[8] ; Missing slew rate ; +; VD[7] ; Missing slew rate ; +; VD[6] ; Missing slew rate ; +; VD[5] ; Missing slew rate ; +; VD[4] ; Missing slew rate ; +; VD[3] ; Missing slew rate ; +; VD[2] ; Missing slew rate ; +; VD[1] ; Missing slew rate ; +; VD[0] ; Missing slew rate ; +; VDQS[3] ; Missing slew rate ; +; VDQS[2] ; Missing slew rate ; +; VDQS[1] ; Missing slew rate ; +; VDQS[0] ; Missing slew rate ; +; SCSI_PAR ; Missing drive strength ; +; nSCSI_SEL ; Missing drive strength ; +; nSCSI_BUSY ; Missing drive strength ; +; nSCSI_RST ; Missing drive strength ; +; SD_CD_DATA3 ; Missing drive strength ; +; SD_CMD_D1 ; Missing drive strength ; +; ACSI_D[7] ; Missing drive strength ; +; ACSI_D[6] ; Missing drive strength ; +; ACSI_D[5] ; Missing drive strength ; +; ACSI_D[4] ; Missing drive strength ; +; ACSI_D[3] ; Missing drive strength ; +; ACSI_D[2] ; Missing drive strength ; +; ACSI_D[1] ; Missing drive strength ; +; ACSI_D[0] ; Missing drive strength ; +; LP_D[7] ; Missing drive strength ; +; LP_D[6] ; Missing drive strength ; +; LP_D[5] ; Missing drive strength ; +; LP_D[4] ; Missing drive strength ; +; LP_D[3] ; Missing drive strength ; +; LP_D[2] ; Missing drive strength ; +; LP_D[1] ; Missing drive strength ; +; LP_D[0] ; Missing drive strength ; +; SCSI_D[7] ; Missing drive strength ; +; SCSI_D[6] ; Missing drive strength ; +; SCSI_D[5] ; Missing drive strength ; +; SCSI_D[4] ; Missing drive strength ; +; SCSI_D[3] ; Missing drive strength ; +; SCSI_D[2] ; Missing drive strength ; +; SCSI_D[1] ; Missing drive strength ; +; SCSI_D[0] ; Missing drive strength ; ++---------------+--------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Netlist Optimizations ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSTEP_DIR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nMOT_ON~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSTEP~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nWR_GATE~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; Packed Register ; Register Packing ; PLL Source Synchronous assignment ; Q ; ; nRD_DATA~input ; O ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nWR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSDSEL~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; DSA_D~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; RTS~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; DTR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_STR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LPDIR~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[0]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[1]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[2]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[3]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[4]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[5]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[6]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[7]~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_OUTn ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSCSI_BUSY~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0_Duplicate_1 ; Q ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nIDE_RD~output ; I ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0SLOAD_MUX ; Created ; Register Packing ; Timing optimization ; COMBOUT ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Q ; ; +; Video:Fredi_Aschwanden|inst90 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[3]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Q ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[2]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Q ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[1]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Q ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[0]~output ; OE ; ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[28]~input ; O ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[29]~input ; O ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[30]~input ; O ; ; +; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[31]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[0]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[1]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[2]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[3]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[4]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[5]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[6]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[7]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[8]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[9]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[10]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[11]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[12]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[13]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[14]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[15]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[16]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[17]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[18]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[19]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[20]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[21]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[22]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[23]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[24]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[25]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[26]~input ; O ; ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[27]~input ; O ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~53 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~168 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~177 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~178 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~368 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~358 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22_BDD23 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector96~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~30 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~31 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_01_STRB~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_10_STRB~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add1~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add3~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add5~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~17 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add10~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add11~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_CLK~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan6~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan7~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan8~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux84~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux92~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux100~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_A[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~162 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163_RESYN8_BDD9 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~3 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|STRB_LOCK~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:STRB_LOCK~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[6]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG~13 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|STRB_LOCK~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:STRB_LOCK~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0_RESYN30_BDD31 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28_BDD29 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_END[10] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[1]~19 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[10]~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28_RESYN32_BDD33 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~29 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~32 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~17 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~29 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~32 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~43 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_26~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_27~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_28~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_30~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_31~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~472 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~478 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~479 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~481 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|_~482 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~10 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42_BDD43 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN44_BDD45 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN46_BDD47 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34_BDD35 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN36_BDD37 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN38_BDD39 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; +; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Ignored Assignments ; ++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ +; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; ++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ +; DDIO_INPUT_REGISTER ; altddio_bidir ; ; input_cell_H ; HIGH ; Compiler or HDL Assignment ; +; DDIO_INPUT_REGISTER ; altddio_bidir ; ; input_cell_L ; LOW ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_0hh1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_3fh1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; +; Synchronizer Identification ; dcfifo_8fi1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; ++-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ + + ++------------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+----------------------+ +; Type ; Value ; ++-------------------------+----------------------+ +; Netlist ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; +; ; ; +; Placement ; ; +; -- Requested ; 0 / 13829 ( 0.00 % ) ; +; -- Achieved ; 0 / 13829 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+----------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 13829 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/FireBee/FPGA/firebee1.pin. + + ++----------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+------------------------------+ +; Resource ; Usage ; ++---------------------------------------------+------------------------------+ +; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; +; -- Combinational with no register ; 4963 ; +; -- Register only ; 1465 ; +; -- Combinational with a register ; 3098 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 4959 ; +; -- 3 input functions ; 1861 ; +; -- <=2 input functions ; 1241 ; +; -- Register only ; 1465 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 7262 ; +; -- arithmetic mode ; 799 ; +; ; ; +; Total registers* ; 4,749 / 41,185 ( 12 % ) ; +; -- Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; +; -- I/O registers ; 186 / 1,585 ( 12 % ) ; +; ; ; +; Total LABs: partially or completely used ; 756 / 2,475 ( 31 % ) ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 295 / 332 ( 89 % ) ; +; -- Clock pins ; 7 / 8 ( 88 % ) ; +; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; +; Global signals ; 20 ; +; M9Ks ; 23 / 126 ( 18 % ) ; +; Total block memory bits ; 109,344 / 1,161,216 ( 9 % ) ; +; Total block memory implementation bits ; 211,968 / 1,161,216 ( 18 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; +; PLLs ; 4 / 4 ( 100 % ) ; +; Global clocks ; 20 / 20 ( 100 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; Impedance control blocks ; 0 / 4 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 15% / 14% / 16% ; +; Peak interconnect usage (total/H/V) ; 59% / 54% / 65% ; +; Maximum fan-out node ; MAIN_CLK~input ; +; Maximum fan-out ; 2272 ; +; Highest non-global fan-out signal ; MAIN_CLK~input ; +; Highest non-global fan-out ; 2272 ; +; Total fan-out ; 44654 ; +; Average fan-out ; 3.02 ; ++---------------------------------------------+------------------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; ++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ +; AMKB_RX ; Y2 ; 2 ; 0 ; 10 ; 21 ; 10 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; CLK33M ; AB12 ; 4 ; 36 ; 0 ; 0 ; 16 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; CTS ; H14 ; 7 ; 61 ; 43 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; DCD ; A19 ; 7 ; 56 ; 43 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; DVI_INT ; A11 ; 8 ; 34 ; 43 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; E0_INT ; G21 ; 6 ; 67 ; 22 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FB_ALE ; R7 ; 2 ; 0 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FB_SIZE0 ; U8 ; 3 ; 3 ; 0 ; 21 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; FB_SIZE1 ; Y4 ; 3 ; 3 ; 0 ; 14 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; HD_DD ; F16 ; 7 ; 65 ; 43 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; IDE_INT ; G22 ; 6 ; 67 ; 22 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; IDE_RDY ; Y1 ; 2 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; LP_BUSY ; G7 ; 8 ; 3 ; 43 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; MAIN_CLK ; G2 ; 1 ; 0 ; 21 ; 0 ; 2272 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; MIDI_IN ; E12 ; 7 ; 36 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; PIC_AMKB_RX ; L7 ; 2 ; 0 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; PIC_INT ; AA2 ; 2 ; 0 ; 7 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; RI ; B19 ; 7 ; 56 ; 43 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; RxD ; H15 ; 7 ; 61 ; 43 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_CARD_DEDECT ; M20 ; 5 ; 67 ; 19 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_DATA0 ; B16 ; 7 ; 50 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_DATA1 ; A16 ; 7 ; 50 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_DATA2 ; B17 ; 7 ; 50 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; SD_WP ; M19 ; 5 ; 67 ; 19 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; TOUT0 ; T22 ; 5 ; 67 ; 22 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; TRACK00 ; C19 ; 7 ; 61 ; 43 ; 28 ; 11 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; WP_CF_CARD ; T1 ; 2 ; 0 ; 21 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nACSI_DRQ ; K7 ; 1 ; 0 ; 30 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nACSI_INT ; J4 ; 1 ; 0 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nDACK0 ; B12 ; 7 ; 34 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nDACK1 ; A12 ; 7 ; 34 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nDCHG ; C17 ; 7 ; 56 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_BURST ; T3 ; 2 ; 0 ; 7 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_CS1 ; T8 ; 3 ; 14 ; 0 ; 28 ; 59 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_CS2 ; T9 ; 3 ; 14 ; 0 ; 21 ; 95 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_CS3 ; V6 ; 3 ; 1 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_OE ; R6 ; 2 ; 0 ; 3 ; 0 ; 101 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nFB_WR ; T5 ; 2 ; 0 ; 4 ; 0 ; 235 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nINDEX ; E16 ; 7 ; 65 ; 43 ; 28 ; 14 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nMASTER ; T21 ; 5 ; 67 ; 22 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTA ; AA1 ; 2 ; 0 ; 6 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTB ; V4 ; 2 ; 0 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTC ; V3 ; 2 ; 0 ; 5 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nPCI_INTD ; P6 ; 2 ; 0 ; 5 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nRD_DATA ; A20 ; 7 ; 59 ; 43 ; 7 ; 0 ; 2 ; no ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nRSTO_MCF ; B11 ; 8 ; 34 ; 43 ; 21 ; 27 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_C_D ; H1 ; 1 ; 0 ; 28 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_DRQ ; U1 ; 2 ; 0 ; 15 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_I_O ; J3 ; 1 ; 0 ; 28 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nSCSI_MSG ; H2 ; 1 ; 0 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; +; nWP ; D19 ; 7 ; 59 ; 43 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; ++----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ +; ACSI_A1 ; M6 ; 2 ; 0 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; ACSI_DIR ; L6 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; AMKB_TX ; N1 ; 2 ; 0 ; 19 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; BA[0] ; W19 ; 5 ; 67 ; 5 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; BA[1] ; AA19 ; 4 ; 56 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; CLK24M576 ; AB10 ; 3 ; 34 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; CLK25M ; T4 ; 2 ; 0 ; 4 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; CLKUSB ; J1 ; 1 ; 0 ; 28 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; DDR_CLK ; AB17 ; 4 ; 54 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; DSA_D ; F15 ; 7 ; 63 ; 43 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; DTR ; D15 ; 7 ; 54 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; HSYNC_PAD ; K21 ; 6 ; 67 ; 27 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; IDE_RES ; M5 ; 2 ; 0 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; LED_FPGA_OK ; N19 ; 5 ; 67 ; 15 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 4mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; LPDIR ; E5 ; 8 ; 1 ; 43 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; LP_STR ; E6 ; 8 ; 1 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; MIDI_OLR ; H5 ; 1 ; 0 ; 31 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; MIDI_TLR ; B2 ; 1 ; 0 ; 41 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; PIXEL_CLK_PAD ; F19 ; 6 ; 67 ; 37 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; RTS ; B18 ; 7 ; 54 ; 43 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; SCSI_DIR ; J7 ; 1 ; 0 ; 30 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; SD_CLK ; C15 ; 7 ; 50 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; TIN0 ; R5 ; 2 ; 0 ; 4 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; TxD ; A18 ; 7 ; 54 ; 43 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[0] ; W20 ; 5 ; 67 ; 3 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[10] ; V21 ; 5 ; 67 ; 10 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[11] ; U19 ; 5 ; 67 ; 7 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[12] ; AA18 ; 4 ; 54 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[1] ; W22 ; 5 ; 67 ; 7 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[2] ; W21 ; 5 ; 67 ; 8 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[3] ; Y22 ; 5 ; 67 ; 6 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[4] ; AA22 ; 5 ; 67 ; 2 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[5] ; Y21 ; 5 ; 67 ; 7 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[6] ; AA21 ; 5 ; 67 ; 2 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[7] ; AA20 ; 4 ; 61 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[8] ; AB20 ; 4 ; 61 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VA[9] ; AB19 ; 4 ; 59 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[0] ; G18 ; 6 ; 67 ; 37 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[1] ; H17 ; 6 ; 67 ; 38 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[2] ; C22 ; 6 ; 67 ; 38 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[3] ; C21 ; 6 ; 67 ; 38 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[4] ; B22 ; 6 ; 67 ; 39 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[5] ; B21 ; 6 ; 67 ; 39 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[6] ; C20 ; 6 ; 67 ; 39 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VB[7] ; D20 ; 6 ; 67 ; 40 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VCKE ; U15 ; 4 ; 50 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[0] ; AA16 ; 4 ; 45 ; 0 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[1] ; V16 ; 4 ; 61 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[2] ; U20 ; 5 ; 67 ; 7 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VDM[3] ; T17 ; 5 ; 67 ; 3 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[0] ; H19 ; 6 ; 67 ; 34 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[1] ; E22 ; 6 ; 67 ; 34 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[2] ; E21 ; 6 ; 67 ; 34 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[3] ; H18 ; 6 ; 67 ; 35 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[4] ; J17 ; 6 ; 67 ; 36 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[5] ; H16 ; 6 ; 67 ; 36 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[6] ; D22 ; 6 ; 67 ; 36 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VG[7] ; D21 ; 6 ; 67 ; 36 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[0] ; J22 ; 6 ; 67 ; 28 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[1] ; J21 ; 6 ; 67 ; 28 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[2] ; H22 ; 6 ; 67 ; 28 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[3] ; H21 ; 6 ; 67 ; 28 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[4] ; K17 ; 6 ; 67 ; 29 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[5] ; K18 ; 6 ; 67 ; 30 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[6] ; J18 ; 6 ; 67 ; 31 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VR[7] ; F22 ; 6 ; 67 ; 31 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; VSYNC_PAD ; K19 ; 6 ; 67 ; 26 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; YM_QA ; A17 ; 7 ; 52 ; 43 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; YM_QB ; G13 ; 7 ; 52 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; YM_QC ; E15 ; 7 ; 54 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nACSI_ACK ; M4 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nACSI_CS ; M2 ; 2 ; 0 ; 20 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nACSI_RESET ; M1 ; 2 ; 0 ; 20 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nBLANK_PAD ; G17 ; 6 ; 67 ; 41 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nCF_CS0 ; W2 ; 2 ; 0 ; 10 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nCF_CS1 ; W1 ; 2 ; 0 ; 10 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nDDR_CLK ; AA17 ; 4 ; 54 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nDREQ1 ; E11 ; 7 ; 36 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nFB_TA ; T7 ; 2 ; 0 ; 2 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_CS0 ; R2 ; 2 ; 0 ; 16 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_CS1 ; R1 ; 2 ; 0 ; 16 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_RD ; P1 ; 2 ; 0 ; 17 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIDE_WR ; P2 ; 2 ; 0 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[2] ; F21 ; 6 ; 67 ; 31 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[3] ; H20 ; 6 ; 67 ; 34 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[4] ; F20 ; 6 ; 67 ; 37 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[5] ; P5 ; 2 ; 0 ; 12 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[6] ; P7 ; 2 ; 0 ; 7 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nIRQ[7] ; N7 ; 2 ; 0 ; 7 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nMOT_ON ; G16 ; 7 ; 63 ; 43 ; 7 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nPD_VGA ; V1 ; 2 ; 0 ; 13 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nROM3 ; P3 ; 2 ; 0 ; 15 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nROM4 ; U2 ; 2 ; 0 ; 15 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nRP_LDS ; N5 ; 2 ; 0 ; 16 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nRP_UDS ; P4 ; 2 ; 0 ; 16 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSCSI_ACK ; N2 ; 2 ; 0 ; 19 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSCSI_ATN ; M3 ; 2 ; 0 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSDSEL ; B20 ; 7 ; 59 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRBHE ; B4 ; 8 ; 7 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRBLE ; A4 ; 8 ; 9 ; 43 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRCS ; B8 ; 8 ; 25 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSROE ; F11 ; 7 ; 36 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSRWE ; F8 ; 8 ; 7 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSTEP ; F14 ; 7 ; 63 ; 43 ; 28 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSTEP_DIR ; G15 ; 7 ; 63 ; 43 ; 21 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nSYNC ; F17 ; 6 ; 67 ; 41 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVCAS ; AB18 ; 4 ; 52 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVCS ; T18 ; 5 ; 67 ; 3 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVRAS ; W17 ; 4 ; 59 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nVWE ; Y17 ; 4 ; 61 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nWR ; G14 ; 7 ; 54 ; 43 ; 28 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; +; nWR_GATE ; D17 ; 7 ; 61 ; 43 ; 14 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; ++---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ +; ACSI_D[0] ; B1 ; 1 ; 0 ; 40 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[1] ; G5 ; 1 ; 0 ; 40 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[2] ; E3 ; 1 ; 0 ; 39 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[3] ; C2 ; 1 ; 0 ; 38 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[4] ; C1 ; 1 ; 0 ; 38 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[5] ; D2 ; 1 ; 0 ; 37 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[6] ; H7 ; 1 ; 0 ; 37 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; ACSI_D[7] ; H6 ; 1 ; 0 ; 37 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; FB_AD[0] ; Y3 ; 3 ; 3 ; 0 ; 7 ; 21 ; 25 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[10] ; W7 ; 3 ; 14 ; 0 ; 14 ; 19 ; 27 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[11] ; Y7 ; 3 ; 14 ; 0 ; 7 ; 19 ; 14 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[12] ; U9 ; 3 ; 16 ; 0 ; 21 ; 21 ; 8 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[13] ; V8 ; 3 ; 16 ; 0 ; 14 ; 21 ; 13 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[14] ; W8 ; 3 ; 16 ; 0 ; 7 ; 20 ; 13 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[15] ; AA7 ; 3 ; 16 ; 0 ; 0 ; 19 ; 11 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[16] ; AB7 ; 3 ; 18 ; 0 ; 21 ; 142 ; 10 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted) ; - ; +; FB_AD[17] ; Y8 ; 3 ; 18 ; 0 ; 14 ; 144 ; 9 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted) ; - ; +; FB_AD[18] ; V9 ; 3 ; 20 ; 0 ; 21 ; 144 ; 9 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[19] ; V10 ; 3 ; 20 ; 0 ; 14 ; 142 ; 5 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted) ; - ; +; FB_AD[1] ; Y6 ; 3 ; 5 ; 0 ; 14 ; 20 ; 158 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[20] ; T10 ; 3 ; 18 ; 0 ; 7 ; 143 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[21] ; U10 ; 3 ; 22 ; 0 ; 14 ; 142 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[22] ; AA8 ; 3 ; 22 ; 0 ; 7 ; 139 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; +; FB_AD[23] ; AB8 ; 3 ; 22 ; 0 ; 0 ; 136 ; 2 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted) ; - ; +; FB_AD[24] ; T11 ; 3 ; 18 ; 0 ; 0 ; 62 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted) ; - ; +; FB_AD[25] ; AA9 ; 3 ; 27 ; 0 ; 7 ; 58 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted) ; - ; +; FB_AD[26] ; AB9 ; 3 ; 27 ; 0 ; 0 ; 56 ; 11 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 (inverted) ; - ; +; FB_AD[27] ; U11 ; 3 ; 29 ; 0 ; 28 ; 47 ; 5 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[28] ; V11 ; 3 ; 34 ; 0 ; 28 ; 36 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[29] ; W10 ; 3 ; 34 ; 0 ; 21 ; 32 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[2] ; AA3 ; 3 ; 7 ; 0 ; 28 ; 20 ; 120 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[30] ; Y10 ; 3 ; 34 ; 0 ; 14 ; 36 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[31] ; AA10 ; 3 ; 34 ; 0 ; 7 ; 35 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; +; FB_AD[3] ; AB3 ; 3 ; 7 ; 0 ; 21 ; 20 ; 97 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[4] ; W6 ; 3 ; 7 ; 0 ; 14 ; 20 ; 83 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[5] ; V7 ; 3 ; 7 ; 0 ; 7 ; 20 ; 161 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[6] ; AA4 ; 3 ; 9 ; 0 ; 28 ; 19 ; 27 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[7] ; AB4 ; 3 ; 9 ; 0 ; 21 ; 18 ; 26 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[8] ; AA5 ; 3 ; 9 ; 0 ; 14 ; 20 ; 34 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; FB_AD[9] ; AB5 ; 3 ; 9 ; 0 ; 7 ; 20 ; 22 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; +; IO[0] ; A8 ; 8 ; 25 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[10] ; B15 ; 7 ; 45 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[11] ; C13 ; 7 ; 45 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[12] ; D13 ; 7 ; 45 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[13] ; E13 ; 7 ; 41 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[14] ; A14 ; 7 ; 41 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[15] ; B14 ; 7 ; 38 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[16] ; A13 ; 7 ; 38 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[17] ; B13 ; 7 ; 38 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[1] ; A7 ; 8 ; 25 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[2] ; B7 ; 8 ; 25 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[3] ; A6 ; 8 ; 25 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[4] ; B6 ; 8 ; 22 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[5] ; E9 ; 8 ; 22 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[6] ; C8 ; 8 ; 20 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[7] ; C7 ; 8 ; 20 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[8] ; G10 ; 8 ; 11 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; IO[9] ; A15 ; 7 ; 45 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; LP_D[0] ; F7 ; 8 ; 3 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[1] ; C4 ; 8 ; 3 ; 43 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[2] ; C3 ; 8 ; 5 ; 43 ; 28 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[3] ; E7 ; 8 ; 5 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[4] ; D6 ; 8 ; 5 ; 43 ; 14 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[5] ; B3 ; 8 ; 5 ; 43 ; 7 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[6] ; A3 ; 8 ; 5 ; 43 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; LP_D[7] ; G8 ; 8 ; 7 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; +; SCSI_D[0] ; J6 ; 1 ; 0 ; 36 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[1] ; E1 ; 1 ; 0 ; 36 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[2] ; F2 ; 1 ; 0 ; 35 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[3] ; F1 ; 1 ; 0 ; 35 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[4] ; G4 ; 1 ; 0 ; 41 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[5] ; G3 ; 1 ; 0 ; 41 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[6] ; L8 ; 1 ; 0 ; 31 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_D[7] ; K8 ; 1 ; 0 ; 30 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SCSI_PAR ; M7 ; 2 ; 0 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SD_CD_DATA3 ; F13 ; 7 ; 45 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SD_CMD_D1 ; E14 ; 7 ; 48 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; SRD[0] ; B5 ; 8 ; 11 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[10] ; A9 ; 8 ; 32 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[11] ; B10 ; 8 ; 32 ; 43 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[12] ; D10 ; 8 ; 32 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[13] ; F10 ; 8 ; 9 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[14] ; G9 ; 8 ; 1 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[15] ; H10 ; 8 ; 18 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[1] ; A5 ; 8 ; 14 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[2] ; C6 ; 8 ; 9 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[3] ; G11 ; 8 ; 27 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[4] ; C10 ; 8 ; 29 ; 43 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[5] ; F9 ; 8 ; 1 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[6] ; E10 ; 8 ; 32 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[7] ; H11 ; 8 ; 20 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[8] ; B9 ; 8 ; 29 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; SRD[9] ; A10 ; 8 ; 32 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; +; VDQS[0] ; AA15 ; 4 ; 43 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; - ; +; VDQS[1] ; W15 ; 4 ; 52 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; - ; +; VDQS[2] ; U22 ; 5 ; 67 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; - ; +; VDQS[3] ; T16 ; 4 ; 63 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90 ; - ; +; VD[0] ; M22 ; 5 ; 67 ; 18 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[10] ; P17 ; 5 ; 67 ; 10 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[11] ; R21 ; 5 ; 67 ; 13 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[12] ; N17 ; 5 ; 67 ; 17 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[13] ; P20 ; 5 ; 67 ; 14 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[14] ; R22 ; 5 ; 67 ; 13 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[15] ; N20 ; 5 ; 67 ; 15 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[16] ; T12 ; 4 ; 45 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[17] ; Y13 ; 4 ; 43 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[18] ; AA13 ; 4 ; 38 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[19] ; V14 ; 4 ; 50 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[1] ; M21 ; 5 ; 67 ; 18 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[20] ; U13 ; 4 ; 50 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[21] ; V15 ; 4 ; 50 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[22] ; W14 ; 4 ; 48 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[23] ; AB16 ; 4 ; 45 ; 0 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[24] ; AB15 ; 4 ; 43 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[25] ; AA14 ; 4 ; 38 ; 0 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[26] ; AB14 ; 4 ; 38 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[27] ; V13 ; 4 ; 48 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[28] ; W13 ; 4 ; 43 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[29] ; AB13 ; 4 ; 38 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[2] ; P22 ; 5 ; 67 ; 14 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[30] ; V12 ; 4 ; 41 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[31] ; U12 ; 4 ; 43 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[3] ; R20 ; 5 ; 67 ; 11 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[4] ; P21 ; 5 ; 67 ; 14 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[5] ; R17 ; 5 ; 67 ; 10 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[6] ; R19 ; 5 ; 67 ; 12 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[7] ; U21 ; 5 ; 67 ; 11 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[8] ; V22 ; 5 ; 67 ; 10 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; VD[9] ; R18 ; 5 ; 67 ; 12 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; +; nSCSI_BUSY ; N8 ; 2 ; 0 ; 11 ; 14 ; 0 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; nSCSI_RST ; N6 ; 2 ; 0 ; 12 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; +; nSCSI_SEL ; M8 ; 2 ; 0 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; ++-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------+ +; Dual Purpose and Dedicated Pins ; ++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ +; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; ++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ +; D1 ; DIFFIO_L8n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; +; E2 ; DIFFIO_L10p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; +; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; +; K2 ; DCLK ; As input tri-stated ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; +; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; +; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; +; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; +; N22 ; DIFFIO_R32n, DEV_OE ; Reserved as secondary function ; ~ALTERA_DEV_OE~ ; Dual Purpose Pin ; +; N21 ; DIFFIO_R32p, DEV_CLRn ; Reserved as secondary function ; ~ALTERA_DEV_CLRn~ ; Dual Purpose Pin ; +; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; +; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; +; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; +; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; +; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; +; K22 ; DIFFIO_R24n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; +; K21 ; DIFFIO_R24p, CLKUSR ; Use as general purpose IO ; HSYNC_PAD ; Dual Purpose Pin ; +; E22 ; DIFFIO_R12n, nWE ; Use as regular IO ; VG[1] ; Dual Purpose Pin ; +; E21 ; DIFFIO_R12p, nOE ; Use as regular IO ; VG[2] ; Dual Purpose Pin ; +; F20 ; DIFFIO_R8n, nAVD ; Use as regular IO ; nIRQ[4] ; Dual Purpose Pin ; +; F19 ; DIFFIO_R8n, nAVD ; - ; PIXEL_CLK_PAD ; Dual Purpose Pin ; +; G18 ; DIFFIO_R7n, PADD23 ; Use as regular IO ; VB[0] ; Dual Purpose Pin ; +; B22 ; DIFFIO_R5n, PADD22 ; Use as regular IO ; VB[4] ; Dual Purpose Pin ; +; B21 ; DIFFIO_R5p, PADD21 ; Use as regular IO ; VB[5] ; Dual Purpose Pin ; +; C20 ; DIFFIO_R4n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO ; VB[6] ; Dual Purpose Pin ; +; B18 ; DIFFIO_T45p, PADD0 ; Use as regular IO ; RTS ; Dual Purpose Pin ; +; A17 ; DIFFIO_T41n, PADD1 ; Use as regular IO ; YM_QA ; Dual Purpose Pin ; +; B17 ; DIFFIO_T41p, PADD2 ; Use as regular IO ; SD_DATA2 ; Dual Purpose Pin ; +; E14 ; DIFFIO_T38n, PADD3 ; Use as regular IO ; SD_CMD_D1 ; Dual Purpose Pin ; +; F13 ; DIFFIO_T37p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; SD_CD_DATA3 ; Dual Purpose Pin ; +; A15 ; DIFFIO_T36n, PADD5 ; Use as regular IO ; IO[9] ; Dual Purpose Pin ; +; B15 ; DIFFIO_T36p, PADD6 ; Use as regular IO ; IO[10] ; Dual Purpose Pin ; +; C13 ; DIFFIO_T35n, PADD7 ; Use as regular IO ; IO[11] ; Dual Purpose Pin ; +; D13 ; DIFFIO_T35p, PADD8 ; Use as regular IO ; IO[12] ; Dual Purpose Pin ; +; A14 ; DIFFIO_T31n, PADD9 ; Use as regular IO ; IO[14] ; Dual Purpose Pin ; +; B14 ; DIFFIO_T31p, PADD10 ; Use as regular IO ; IO[15] ; Dual Purpose Pin ; +; A13 ; DIFFIO_T29n, PADD11 ; Use as regular IO ; IO[16] ; Dual Purpose Pin ; +; B13 ; DIFFIO_T29p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; IO[17] ; Dual Purpose Pin ; +; E11 ; DIFFIO_T27n, PADD13 ; Use as regular IO ; nDREQ1 ; Dual Purpose Pin ; +; F11 ; DIFFIO_T27p, PADD14 ; Use as regular IO ; nSROE ; Dual Purpose Pin ; +; B10 ; DIFFIO_T25p, PADD15 ; Use as regular IO ; SRD[11] ; Dual Purpose Pin ; +; A9 ; DIFFIO_T24n, PADD16 ; Use as regular IO ; SRD[10] ; Dual Purpose Pin ; +; B9 ; DIFFIO_T24p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; SRD[8] ; Dual Purpose Pin ; +; A8 ; DIFFIO_T20n, DATA2 ; Use as regular IO ; IO[0] ; Dual Purpose Pin ; +; B8 ; DIFFIO_T20p, DATA3 ; Use as regular IO ; nSRCS ; Dual Purpose Pin ; +; A7 ; DIFFIO_T19n, PADD18 ; Use as regular IO ; IO[1] ; Dual Purpose Pin ; +; B7 ; DIFFIO_T19p, DATA4 ; Use as regular IO ; IO[2] ; Dual Purpose Pin ; +; A6 ; DIFFIO_T18n, PADD19 ; Use as regular IO ; IO[3] ; Dual Purpose Pin ; +; B6 ; DIFFIO_T18p, DATA15 ; Use as regular IO ; IO[4] ; Dual Purpose Pin ; +; C8 ; DIFFIO_T16n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO ; IO[6] ; Dual Purpose Pin ; +; C7 ; DIFFIO_T16p, DATA13 ; Use as regular IO ; IO[7] ; Dual Purpose Pin ; +; A5 ; DIFFIO_T11p, DATA5 ; Use as regular IO ; SRD[1] ; Dual Purpose Pin ; +; F10 ; DIFFIO_T8p, DATA6 ; Use as regular IO ; SRD[13] ; Dual Purpose Pin ; +; C6 ; DIFFIO_T7n, DATA7 ; Use as regular IO ; SRD[2] ; Dual Purpose Pin ; +; B4 ; DIFFIO_T6p, DATA8 ; Use as regular IO ; nSRBHE ; Dual Purpose Pin ; +; F8 ; DIFFIO_T5n, DATA9 ; Use as regular IO ; nSRWE ; Dual Purpose Pin ; +; A3 ; DIFFIO_T4n, DATA10 ; Use as regular IO ; LP_D[6] ; Dual Purpose Pin ; +; B3 ; DIFFIO_T4p, DATA11 ; Use as regular IO ; LP_D[5] ; Dual Purpose Pin ; +; C4 ; DIFFIO_T3p, DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; LP_D[1] ; Dual Purpose Pin ; ++----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ + + ++-------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-------------------+---------------+--------------+ +; 1 ; 30 / 36 ( 83 % ) ; 3.3V ; -- ; +; 2 ; 44 / 46 ( 96 % ) ; 3.3V ; -- ; +; 3 ; 38 / 42 ( 90 % ) ; 3.3V ; -- ; +; 4 ; 33 / 43 ( 77 % ) ; 2.5V ; -- ; +; 5 ; 37 / 42 ( 88 % ) ; 2.5V ; -- ; +; 6 ; 35 / 37 ( 95 % ) ; 3.0V ; -- ; +; 7 ; 43 / 43 ( 100 % ) ; 3.3V ; -- ; +; 8 ; 42 / 43 ( 98 % ) ; 3.3V ; -- ; ++----------+-------------------+---------------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 534 ; 8 ; LP_D[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A4 ; 529 ; 8 ; nSRBLE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A5 ; 518 ; 8 ; SRD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A6 ; 501 ; 8 ; IO[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A7 ; 499 ; 8 ; IO[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A8 ; 497 ; 8 ; IO[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A9 ; 487 ; 8 ; SRD[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A10 ; 485 ; 8 ; SRD[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A11 ; 481 ; 8 ; DVI_INT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A12 ; 479 ; 7 ; nDACK1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A13 ; 473 ; 7 ; IO[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A14 ; 469 ; 7 ; IO[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A15 ; 458 ; 7 ; IO[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A16 ; 448 ; 7 ; SD_DATA1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A17 ; 446 ; 7 ; YM_QA ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A18 ; 437 ; 7 ; TxD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A19 ; 435 ; 7 ; DCD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A20 ; 430 ; 7 ; nRD_DATA ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; A21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; 125 ; 2 ; nPCI_INTA ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AA2 ; 124 ; 2 ; PIC_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; AA3 ; 154 ; 3 ; FB_AD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA4 ; 158 ; 3 ; FB_AD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA5 ; 160 ; 3 ; FB_AD[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA7 ; 173 ; 3 ; FB_AD[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA8 ; 183 ; 3 ; FB_AD[22] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA9 ; 189 ; 3 ; FB_AD[25] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA10 ; 202 ; 3 ; FB_AD[31] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AA11 ; 204 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA12 ; 206 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AA13 ; 208 ; 4 ; VD[18] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA14 ; 210 ; 4 ; VD[25] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA15 ; 220 ; 4 ; VDQS[0] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA16 ; 224 ; 4 ; VDM[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA17 ; 243 ; 4 ; nDDR_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA18 ; 245 ; 4 ; VA[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA19 ; 252 ; 4 ; BA[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA20 ; 259 ; 4 ; VA[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AA21 ; 274 ; 5 ; VA[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AA22 ; 273 ; 5 ; VA[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 155 ; 3 ; FB_AD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB4 ; 159 ; 3 ; FB_AD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB5 ; 161 ; 3 ; FB_AD[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB7 ; 174 ; 3 ; FB_AD[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB8 ; 184 ; 3 ; FB_AD[23] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB9 ; 190 ; 3 ; FB_AD[26] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB10 ; 203 ; 3 ; CLK24M576 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB11 ; 205 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; AB12 ; 207 ; 4 ; CLK33M ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; AB13 ; 209 ; 4 ; VD[29] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB14 ; 211 ; 4 ; VD[26] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB15 ; 221 ; 4 ; VD[24] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB16 ; 225 ; 4 ; VD[23] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB17 ; 244 ; 4 ; DDR_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB18 ; 242 ; 4 ; nVCAS ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB19 ; 253 ; 4 ; VA[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB20 ; 260 ; 4 ; VA[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; 4 ; 1 ; ACSI_D[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B2 ; 3 ; 1 ; MIDI_TLR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B3 ; 535 ; 8 ; LP_D[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B4 ; 530 ; 8 ; nSRBHE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B5 ; 523 ; 8 ; SRD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B6 ; 502 ; 8 ; IO[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B7 ; 500 ; 8 ; IO[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B8 ; 498 ; 8 ; nSRCS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B9 ; 488 ; 8 ; SRD[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B10 ; 486 ; 8 ; SRD[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B11 ; 482 ; 8 ; nRSTO_MCF ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B12 ; 480 ; 7 ; nDACK0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B13 ; 474 ; 7 ; IO[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B14 ; 470 ; 7 ; IO[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B15 ; 459 ; 7 ; IO[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B16 ; 449 ; 7 ; SD_DATA0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B17 ; 447 ; 7 ; SD_DATA2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B18 ; 438 ; 7 ; RTS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B19 ; 434 ; 7 ; RI ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B20 ; 431 ; 7 ; nSDSEL ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; B21 ; 404 ; 6 ; VB[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; B22 ; 403 ; 6 ; VB[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C1 ; 15 ; 1 ; ACSI_D[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C2 ; 14 ; 1 ; ACSI_D[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C3 ; 538 ; 8 ; LP_D[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C4 ; 539 ; 8 ; LP_D[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; 526 ; 8 ; SRD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C7 ; 508 ; 8 ; IO[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C8 ; 507 ; 8 ; IO[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C10 ; 491 ; 8 ; SRD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C13 ; 460 ; 7 ; IO[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C15 ; 450 ; 7 ; SD_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C17 ; 433 ; 7 ; nDCHG ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C19 ; 428 ; 7 ; TRACK00 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; C20 ; 405 ; 6 ; VB[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C21 ; 401 ; 6 ; VB[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; C22 ; 400 ; 6 ; VB[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D1 ; 17 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D2 ; 16 ; 1 ; ACSI_D[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D6 ; 536 ; 8 ; LP_D[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D7 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D10 ; 483 ; 8 ; SRD[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D13 ; 461 ; 7 ; IO[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D15 ; 439 ; 7 ; DTR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D17 ; 426 ; 7 ; nWR_GATE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D19 ; 429 ; 7 ; nWP ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; D20 ; 407 ; 6 ; VB[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D21 ; 395 ; 6 ; VG[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; D22 ; 394 ; 6 ; VG[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E1 ; 22 ; 1 ; SCSI_D[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E2 ; 21 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; E3 ; 9 ; 1 ; ACSI_D[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E4 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; E5 ; 546 ; 8 ; LPDIR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E6 ; 545 ; 8 ; LP_STR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E7 ; 537 ; 8 ; LP_D[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E8 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E9 ; 506 ; 8 ; IO[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E10 ; 484 ; 8 ; SRD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E11 ; 477 ; 7 ; nDREQ1 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E12 ; 476 ; 7 ; MIDI_IN ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E13 ; 468 ; 7 ; IO[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E14 ; 453 ; 7 ; SD_CMD_D1 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E15 ; 440 ; 7 ; YM_QC ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E16 ; 418 ; 7 ; nINDEX ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; E21 ; 388 ; 6 ; VG[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; E22 ; 387 ; 6 ; VG[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F1 ; 26 ; 1 ; SCSI_D[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F2 ; 25 ; 1 ; SCSI_D[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F7 ; 542 ; 8 ; LP_D[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F8 ; 531 ; 8 ; nSRWE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F9 ; 544 ; 8 ; SRD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F10 ; 525 ; 8 ; SRD[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F11 ; 478 ; 7 ; nSROE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F13 ; 457 ; 7 ; SD_CD_DATA3 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F14 ; 423 ; 7 ; nSTEP ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F15 ; 419 ; 7 ; DSA_D ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F16 ; 417 ; 7 ; HD_DD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; F17 ; 410 ; 6 ; nSYNC ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; F19 ; 397 ; 6 ; PIXEL_CLK_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; F20 ; 396 ; 6 ; nIRQ[4] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; F21 ; 376 ; 6 ; nIRQ[2] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; F22 ; 375 ; 6 ; VR[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G1 ; 67 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; G2 ; 66 ; 1 ; MAIN_CLK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G3 ; 1 ; 1 ; SCSI_D[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G4 ; 0 ; 1 ; SCSI_D[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G5 ; 5 ; 1 ; ACSI_D[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; G7 ; 543 ; 8 ; LP_BUSY ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G8 ; 532 ; 8 ; LP_D[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G9 ; 547 ; 8 ; SRD[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G10 ; 524 ; 8 ; IO[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G11 ; 492 ; 8 ; SRD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G13 ; 444 ; 7 ; YM_QB ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G14 ; 441 ; 7 ; nWR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G15 ; 422 ; 7 ; nSTEP_DIR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G16 ; 420 ; 7 ; nMOT_ON ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; G17 ; 411 ; 6 ; nBLANK_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G18 ; 398 ; 6 ; VB[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G21 ; 345 ; 6 ; E0_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; G22 ; 344 ; 6 ; IDE_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H1 ; 52 ; 1 ; nSCSI_C_D ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H2 ; 51 ; 1 ; nSCSI_MSG ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H5 ; 42 ; 1 ; MIDI_OLR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H6 ; 19 ; 1 ; ACSI_D[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H7 ; 18 ; 1 ; ACSI_D[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H8 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; H9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H10 ; 512 ; 8 ; SRD[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H11 ; 511 ; 8 ; SRD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H14 ; 425 ; 7 ; CTS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H15 ; 424 ; 7 ; RxD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; H16 ; 393 ; 6 ; VG[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H17 ; 399 ; 6 ; VB[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H18 ; 391 ; 6 ; VG[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H19 ; 386 ; 6 ; VG[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H20 ; 385 ; 6 ; nIRQ[3] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; H21 ; 365 ; 6 ; VR[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; H22 ; 364 ; 6 ; VR[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J1 ; 55 ; 1 ; CLKUSB ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J2 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J3 ; 53 ; 1 ; nSCSI_I_O ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J4 ; 50 ; 1 ; nACSI_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J5 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J6 ; 20 ; 1 ; SCSI_D[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J7 ; 45 ; 1 ; SCSI_DIR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J8 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J17 ; 392 ; 6 ; VG[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J18 ; 374 ; 6 ; VR[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J20 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; J21 ; 363 ; 6 ; VR[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; J22 ; 362 ; 6 ; VR[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K1 ; 59 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K2 ; 58 ; 1 ; ~ALTERA_DCLK~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K5 ; 60 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; K6 ; 41 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; K7 ; 46 ; 1 ; nACSI_DRQ ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K8 ; 44 ; 1 ; SCSI_D[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; 369 ; 6 ; VR[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K18 ; 370 ; 6 ; VR[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K19 ; 357 ; 6 ; VSYNC_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K20 ; 350 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; K21 ; 361 ; 6 ; HSYNC_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; K22 ; 360 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 3.0-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L1 ; 63 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; L2 ; 62 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; L3 ; 65 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; L4 ; 64 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L5 ; 61 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; L6 ; 70 ; 2 ; ACSI_DIR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L7 ; 79 ; 2 ; PIC_AMKB_RX ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L8 ; 43 ; 1 ; SCSI_D[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L17 ; 349 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 348 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; +; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L21 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; L22 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M1 ; 73 ; 2 ; nACSI_RESET ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M2 ; 72 ; 2 ; nACSI_CS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M3 ; 75 ; 2 ; nSCSI_ATN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M4 ; 74 ; 2 ; nACSI_ACK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M5 ; 80 ; 2 ; IDE_RES ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M6 ; 71 ; 2 ; ACSI_A1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M7 ; 105 ; 2 ; SCSI_PAR ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M8 ; 106 ; 2 ; nSCSI_SEL ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M16 ; 337 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; M17 ; 347 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 346 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; M19 ; 336 ; 5 ; SD_WP ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M20 ; 335 ; 5 ; SD_CARD_DEDECT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; M21 ; 334 ; 5 ; VD[1] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; M22 ; 333 ; 5 ; VD[0] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N1 ; 77 ; 2 ; AMKB_TX ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; N2 ; 76 ; 2 ; nSCSI_ACK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N5 ; 87 ; 2 ; nRP_LDS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N6 ; 104 ; 2 ; nSCSI_RST ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N7 ; 122 ; 2 ; nIRQ[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N8 ; 107 ; 2 ; nSCSI_BUSY ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N16 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N17 ; 329 ; 5 ; VD[12] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N18 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; N19 ; 324 ; 5 ; LED_FPGA_OK ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N20 ; 323 ; 5 ; VD[15] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; N21 ; 332 ; 5 ; ~ALTERA_DEV_CLRn~ / RESERVED_INPUT ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; N22 ; 331 ; 5 ; ~ALTERA_DEV_OE~ / RESERVED_INPUT ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; +; P1 ; 84 ; 2 ; nIDE_RD ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P2 ; 83 ; 2 ; nIDE_WR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P3 ; 89 ; 2 ; nROM3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P4 ; 88 ; 2 ; nRP_UDS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P5 ; 103 ; 2 ; nIRQ[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P6 ; 131 ; 2 ; nPCI_INTD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P7 ; 123 ; 2 ; nIRQ[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P15 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P16 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; P17 ; 302 ; 5 ; VD[10] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P20 ; 317 ; 5 ; VD[13] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P21 ; 320 ; 5 ; VD[4] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; P22 ; 319 ; 5 ; VD[2] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R1 ; 86 ; 2 ; nIDE_CS1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R2 ; 85 ; 2 ; nIDE_CS0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R5 ; 135 ; 2 ; TIN0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R6 ; 136 ; 2 ; nFB_OE ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R7 ; 137 ; 2 ; FB_ALE ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; R8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R14 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R15 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R16 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; R17 ; 301 ; 5 ; VD[5] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R18 ; 309 ; 5 ; VD[9] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R19 ; 310 ; 5 ; VD[6] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R20 ; 305 ; 5 ; VD[3] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R21 ; 316 ; 5 ; VD[11] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; R22 ; 315 ; 5 ; VD[14] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T1 ; 69 ; 2 ; WP_CF_CARD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T2 ; 68 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; T3 ; 121 ; 2 ; nFB_BURST ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T4 ; 134 ; 2 ; CLK25M ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T5 ; 133 ; 2 ; nFB_WR ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T7 ; 138 ; 2 ; nFB_TA ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T8 ; 166 ; 3 ; nFB_CS1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T9 ; 167 ; 3 ; nFB_CS2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T10 ; 176 ; 3 ; FB_AD[20] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T11 ; 177 ; 3 ; FB_AD[24] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; T12 ; 226 ; 4 ; VD[16] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T13 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T14 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T15 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; T16 ; 266 ; 4 ; VDQS[3] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; T17 ; 277 ; 5 ; VDM[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T18 ; 278 ; 5 ; nVCS ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 343 ; 5 ; nMASTER ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; T22 ; 342 ; 5 ; TOUT0 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U1 ; 92 ; 2 ; nSCSI_DRQ ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U2 ; 91 ; 2 ; nROM4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; U4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U8 ; 146 ; 3 ; FB_SIZE0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U9 ; 170 ; 3 ; FB_AD[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U10 ; 182 ; 3 ; FB_AD[21] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U11 ; 191 ; 3 ; FB_AD[27] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; U12 ; 222 ; 4 ; VD[31] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; U13 ; 233 ; 4 ; VD[20] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; U14 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U15 ; 236 ; 4 ; VCKE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; U16 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U17 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; U19 ; 291 ; 5 ; VA[11] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U20 ; 290 ; 5 ; VDM[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U21 ; 308 ; 5 ; VD[7] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; U22 ; 307 ; 5 ; VDQS[2] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; V1 ; 98 ; 2 ; nPD_VGA ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; +; V3 ; 130 ; 2 ; nPCI_INTC ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V4 ; 129 ; 2 ; nPCI_INTB ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; V5 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; +; V6 ; 141 ; 3 ; nFB_CS3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V7 ; 157 ; 3 ; FB_AD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V8 ; 171 ; 3 ; FB_AD[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V9 ; 178 ; 3 ; FB_AD[18] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V10 ; 179 ; 3 ; FB_AD[19] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V11 ; 199 ; 3 ; FB_AD[28] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; V12 ; 213 ; 4 ; VD[30] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V13 ; 228 ; 4 ; VD[27] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V14 ; 234 ; 4 ; VD[19] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V15 ; 237 ; 4 ; VD[21] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V16 ; 261 ; 4 ; VDM[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V21 ; 304 ; 5 ; VA[10] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; V22 ; 303 ; 5 ; VD[8] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W1 ; 111 ; 2 ; nCF_CS1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W2 ; 110 ; 2 ; nCF_CS0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W6 ; 156 ; 3 ; FB_AD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W7 ; 168 ; 3 ; FB_AD[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W8 ; 172 ; 3 ; FB_AD[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W10 ; 200 ; 3 ; FB_AD[29] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; W11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W13 ; 218 ; 4 ; VD[28] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W14 ; 229 ; 4 ; VD[22] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W15 ; 239 ; 4 ; VDQS[1] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W17 ; 257 ; 4 ; nVRAS ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; W19 ; 285 ; 5 ; BA[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W20 ; 280 ; 5 ; VA[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W21 ; 293 ; 5 ; VA[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; W22 ; 292 ; 5 ; VA[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y1 ; 113 ; 2 ; IDE_RDY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y2 ; 112 ; 2 ; AMKB_RX ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; +; Y3 ; 148 ; 3 ; FB_AD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y4 ; 147 ; 3 ; FB_SIZE1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y6 ; 152 ; 3 ; FB_AD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y7 ; 169 ; 3 ; FB_AD[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y8 ; 175 ; 3 ; FB_AD[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y10 ; 201 ; 3 ; FB_AD[30] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; +; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y13 ; 219 ; 4 ; VD[17] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y17 ; 258 ; 4 ; nVWE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; +; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; +; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y21 ; 289 ; 5 ; VA[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; +; Y22 ; 288 ; 5 ; VA[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; ++----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Summary ; ++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ +; Name ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 ; ++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ +; SDC pin name ; inst|altpll_component|auto_generated|pll1 ; inst13|altpll_component|auto_generated|pll1 ; inst12|altpll_component|auto_generated|pll1 ; inst22|altpll_component|auto_generated|pll1 ; +; PLL mode ; Source Synchronous ; Source Synchronous ; Source Synchronous ; Normal ; +; Compensate clock ; clock0 ; clock1 ; clock0 ; clock0 ; +; Compensated input/output pins ; -- ; nRD_DATA ; MAIN_CLK ; -- ; +; Switchover type ; -- ; -- ; -- ; -- ; +; Input frequency 0 ; 33.0 MHz ; 33.0 MHz ; 33.0 MHz ; 48.0 MHz ; +; Input frequency 1 ; -- ; -- ; -- ; -- ; +; Nominal PFD frequency ; 5.5 MHz ; 11.0 MHz ; 33.0 MHz ; 48.0 MHz ; +; Nominal VCO frequency ; 368.5 MHz ; 1199.0 MHz ; 396.0 MHz ; 576.0 MHz ; +; VCO post scale ; 2 ; -- ; 2 ; 2 ; +; VCO frequency control ; Auto ; Auto ; Auto ; Auto ; +; VCO phase shift step ; 339 ps ; 104 ps ; 315 ps ; 217 ps ; +; VCO multiply ; -- ; -- ; -- ; -- ; +; VCO divide ; -- ; -- ; -- ; -- ; +; Freq min lock ; 32.4 MHz ; 16.8 MHz ; 25.0 MHz ; 25.0 MHz ; +; Freq max lock ; 58.23 MHz ; 35.79 MHz ; 54.18 MHz ; 54.18 MHz ; +; M VCO Tap ; 0 ; 0 ; 0 ; 0 ; +; M Initial ; 1 ; 1 ; 1 ; 1 ; +; M value ; 67 ; 109 ; 12 ; 12 ; +; N value ; 6 ; 3 ; 1 ; 1 ; +; Charge pump current ; setting 1 ; setting 1 ; setting 1 ; setting 1 ; +; Loop filter resistance ; setting 16 ; setting 19 ; setting 27 ; setting 27 ; +; Loop filter capacitance ; setting 0 ; setting 0 ; setting 0 ; setting 0 ; +; Bandwidth ; 340 kHz to 540 kHz ; 450 kHz to 560 kHz ; 680 kHz to 980 kHz ; 680 kHz to 980 kHz ; +; Real time reconfigurable ; Off ; Off ; Off ; On ; +; Scan chain MIF file ; -- ; -- ; -- ; altpll4.mif ; +; Preserve PLL counter order ; Off ; Off ; Off ; Off ; +; PLL location ; PLL_3 ; PLL_4 ; PLL_1 ; PLL_2 ; +; Inclk0 signal ; CLK33M ; CLK33M ; MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; +; Inclk1 signal ; -- ; -- ; -- ; -- ; +; Inclk0 signal type ; Global Clock ; Dedicated Pin ; Dedicated Pin ; Global Clock ; +; Inclk1 signal type ; -- ; -- ; -- ; -- ; ++-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; PLL Usage ; ++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ +; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; ++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; clock0 ; 1 ; 66 ; 0.5 MHz ; 0 (0 ps) ; 0.67 (339 ps) ; 50/50 ; C1 ; 67 ; 34/33 Odd ; C0 ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[0] ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; clock1 ; 67 ; 900 ; 2.46 MHz ; 0 (0 ps) ; 0.30 (339 ps) ; 50/50 ; C2 ; 150 ; 75/75 Even ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[1] ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; clock2 ; 67 ; 90 ; 24.57 MHz ; 0 (0 ps) ; 3.00 (339 ps) ; 50/50 ; C3 ; 15 ; 8/7 Odd ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[2] ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 11 ; 5/6 Odd ; -- ; 1 ; 0 ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; clock0 ; 109 ; 1800 ; 2.0 MHz ; 0 (0 ps) ; 0.15 (104 ps) ; 50/50 ; C1 ; 300 ; 150/150 Even ; C0 ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[0] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; clock1 ; 109 ; 225 ; 15.99 MHz ; 0 (0 ps) ; 0.60 (104 ps) ; 50/50 ; C2 ; 75 ; 38/37 Odd ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[1] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; clock2 ; 109 ; 144 ; 24.98 MHz ; 0 (0 ps) ; 0.94 (104 ps) ; 50/50 ; C3 ; 48 ; 24/24 Even ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[2] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; clock3 ; 109 ; 75 ; 47.96 MHz ; 0 (0 ps) ; 1.80 (104 ps) ; 50/50 ; C4 ; 25 ; 13/12 Odd ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[3] ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 2 ; 1/1 Even ; -- ; 1 ; 0 ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; clock0 ; 4 ; 1 ; 132.0 MHz ; 240 (5051 ps) ; 15.00 (315 ps) ; 50/50 ; C0 ; 3 ; 2/1 Odd ; -- ; 3 ; 0 ; inst12|altpll_component|auto_generated|pll1|clk[0] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; clock1 ; 4 ; 1 ; 132.0 MHz ; 0 (0 ps) ; 15.00 (315 ps) ; 50/50 ; C3 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; inst12|altpll_component|auto_generated|pll1|clk[1] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; clock2 ; 4 ; 1 ; 132.0 MHz ; 180 (3788 ps) ; 15.00 (315 ps) ; 50/50 ; C2 ; 3 ; 2/1 Odd ; -- ; 2 ; 4 ; inst12|altpll_component|auto_generated|pll1|clk[2] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; clock3 ; 4 ; 1 ; 132.0 MHz ; 105 (2210 ps) ; 15.00 (315 ps) ; 50/50 ; C4 ; 3 ; 2/1 Odd ; -- ; 1 ; 7 ; inst12|altpll_component|auto_generated|pll1|clk[3] ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; clock4 ; 2 ; 1 ; 66.0 MHz ; 270 (11364 ps) ; 7.50 (315 ps) ; 50/50 ; C1 ; 6 ; 3/3 Even ; -- ; 5 ; 4 ; inst12|altpll_component|auto_generated|pll1|clk[4] ; +; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; clock0 ; 2 ; 1 ; 96.0 MHz ; 0 (0 ps) ; 7.50 (217 ps) ; 50/50 ; C0 ; 6 ; 3/3 Even ; -- ; 1 ; 0 ; inst22|altpll_component|auto_generated|pll1|clk[0] ; ++-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.0-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.0-V LVCMOS ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 3.0-V PCI ; 10 pF ; Not Available ; +; 3.0-V PCI-X ; 10 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 1.2 V ; 0 pF ; Not Available ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 2.5-V SSTL Class I ; 0 pF ; (See SSTL-2) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; 1.2-V HSTL Class I ; 0 pF ; Not Available ; +; Differential 1.2-V HSTL Class I ; 0 pF ; Not Available ; +; 1.2-V HSTL Class II ; 0 pF ; Not Available ; +; Differential 1.2-V HSTL Class II ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; LVDS_E_3R ; 0 pF ; Not Available ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS_E_1R ; 0 pF ; Not Available ; +; RSDS_E_3R ; 0 pF ; Not Available ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS_E_3R ; 0 pF ; Not Available ; +; PPDS ; 0 pF ; Not Available ; +; PPDS_E_3R ; 0 pF ; Not Available ; +; Bus LVDS ; 0 pF ; Not Available ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |firebee1 ; 9526 (10) ; 4563 (0) ; 186 (186) ; 109344 ; 23 ; 6 ; 0 ; 3 ; 295 ; 0 ; 4963 (10) ; 1465 (0) ; 3098 (0) ; |firebee1 ; work ; +; |DSP:Mathias_Alles| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |firebee1|DSP:Mathias_Alles ; ; +; |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden| ; 4093 (640) ; 1616 (114) ; 0 (0) ; 16384 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2414 (465) ; 291 (10) ; 1388 (177) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden ; ; +; |WF1772IP_TOP_SOC:I_FDC| ; 976 (17) ; 403 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 565 (9) ; 33 (0) ; 378 (15) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC ; ; +; |WF1772IP_AM_DETECTOR:I_AM_DETECTOR| ; 40 (40) ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 1 (1) ; 26 (26) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR ; ; +; |WF1772IP_CONTROL:I_CONTROL| ; 545 (545) ; 196 (196) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 344 (344) ; 12 (12) ; 189 (189) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL ; ; +; |WF1772IP_CRC_LOGIC:I_CRC_LOGIC| ; 51 (51) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (35) ; 11 (11) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC ; ; +; |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL| ; 103 (103) ; 37 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 66 (66) ; 0 (0) ; 37 (37) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ; +; |WF1772IP_REGISTERS:I_REGISTERS| ; 105 (105) ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (57) ; 7 (7) ; 41 (41) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS ; ; +; |WF1772IP_TRANSCEIVER:I_TRANSCEIVER| ; 120 (120) ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 2 (2) ; 77 (77) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER ; ; +; |WF2149IP_TOP_SOC:I_SOUND| ; 490 (36) ; 197 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 293 (20) ; 37 (2) ; 160 (18) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND ; ; +; |WF2149IP_WAVE:I_PSG_WAVE| ; 461 (461) ; 181 (181) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 273 (273) ; 35 (35) ; 153 (153) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE ; ; +; |WF5380_TOP_SOC:I_SCSI| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI ; ; +; |WF5380_CONTROL:I_CONTROL| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL ; ; +; |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD| ; 208 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 106 (1) ; 1 (0) ; 101 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 21 (21) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 1 (1) ; 10 (10) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 101 (101) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 54 (54) ; 0 (0) ; 47 (47) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 0 (0) ; 46 (46) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF6850IP_TOP_SOC:I_ACIA_MIDI| ; 218 (2) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 116 (2) ; 10 (0) ; 92 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 27 (27) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 6 (6) ; 9 (9) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 101 (101) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (53) ; 3 (3) ; 45 (45) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 88 (88) ; 39 (39) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 1 (1) ; 38 (38) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF68901IP_TOP_SOC:I_MFP| ; 1261 (110) ; 460 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 797 (107) ; 70 (0) ; 394 (71) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP ; ; +; |WF68901IP_GPIO:I_GPIO| ; 49 (49) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 9 (9) ; 17 (17) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO ; ; +; |WF68901IP_INTERRUPTS:I_INTERRUPTS| ; 290 (290) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 159 (159) ; 5 (5) ; 126 (126) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS ; ; +; |WF68901IP_TIMERS:I_TIMERS| ; 501 (501) ; 166 (166) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 332 (332) ; 44 (44) ; 125 (125) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS ; ; +; |WF68901IP_USART_TOP:I_USART| ; 316 (3) ; 140 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (3) ; 12 (0) ; 128 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART ; ; +; |WF68901IP_USART_CTRL:I_USART_CTRL| ; 77 (77) ; 49 (49) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 9 (9) ; 40 (40) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL ; ; +; |WF68901IP_USART_RX:I_USART_RECEIVE| ; 160 (160) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 2 (2) ; 58 (58) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE ; ; +; |WF68901IP_USART_TX:I_USART_TRANSMIT| ; 87 (87) ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 45 (45) ; 1 (1) ; 41 (41) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT ; ; +; |dcfifo0:RDF| ; 156 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 60 (0) ; 66 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 156 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 60 (0) ; 66 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_0hh1:auto_generated| ; 156 (55) ; 124 (42) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (4) ; 60 (27) ; 66 (13) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ; +; |a_gray2bin_lfb:wrptr_g_gray2bin| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin ; ; +; |a_gray2bin_lfb:ws_dgrp_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin ; ; +; |a_graycounter_fic:wrptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 1 (1) ; 13 (13) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ; +; |a_graycounter_k47:rdptr_g1p| ; 18 (18) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ; +; |alt_synch_pipe_ikd:rs_dgwp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (0) ; 4 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ; +; |dffpipe_hd9:dffpipe12| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (14) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ; +; |alt_synch_pipe_jkd:ws_dgrp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (0) ; 1 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ; +; |dffpipe_id9:dffpipe17| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (17) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ; +; |altsyncram_bi31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cmpr_156:wrfull_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:ws_brp| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ; +; |dffpipe_pe9:ws_bwp| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (10) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |dcfifo1:WRF| ; 166 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 70 (0) ; 54 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 166 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 70 (0) ; 54 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_3fh1:auto_generated| ; 166 (58) ; 124 (42) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (6) ; 70 (34) ; 54 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ; +; |a_gray2bin_lfb:rdptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin ; ; +; |a_gray2bin_lfb:rs_dgwp_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin ; ; +; |a_graycounter_gic:wrptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ; +; |a_graycounter_j47:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ; +; |alt_synch_pipe_kkd:rs_dgwp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (0) ; 3 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ; +; |dffpipe_jd9:dffpipe12| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (15) ; 3 (3) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ; +; |alt_synch_pipe_lkd:ws_dgrp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (0) ; 2 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ; +; |dffpipe_kd9:dffpipe15| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ; +; |altsyncram_ci31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:rs_bwp| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 6 (6) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ; +; |dffpipe_pe9:rs_brp| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 9 (9) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 3 (3) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |Video:Fredi_Aschwanden| ; 4088 (14) ; 2168 (4) ; 0 (0) ; 92816 ; 20 ; 6 ; 0 ; 3 ; 0 ; 0 ; 1920 (10) ; 916 (4) ; 1252 (0) ; |firebee1|Video:Fredi_Aschwanden ; ; +; |DDR_CTR:DDR_CTR| ; 374 (342) ; 158 (158) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (180) ; 20 (20) ; 143 (140) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR ; ; +; |lpm_bustri_BYT:$00002| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 31 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (0) ; 0 (0) ; 3 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 0 (0) ; 3 (3) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR| ; 1420 (1292) ; 529 (529) ; 0 (0) ; 0 ; 0 ; 6 ; 0 ; 3 ; 0 ; 0 ; 891 (763) ; 158 (158) ; 371 (252) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR ; ; +; |lpm_bustri_WORD:$00000| ; 187 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (0) ; 0 (0) ; 75 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 187 (187) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (112) ; 0 (0) ; 75 (75) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_WORD:$00002| ; 60 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 44 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 60 (60) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 44 (44) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_mult:op_12| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated ; ; +; |lpm_mult:op_14| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ; +; |mult_cat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated ; ; +; |lpm_mult:op_6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated ; ; +; |altddio_bidir0:inst1| ; 96 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1 ; ; +; |altddio_bidir:altddio_bidir_component| ; 96 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ; +; |ddio_bidir_3jl:auto_generated| ; 96 (96) ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (96) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ; +; |altddio_out0:inst2| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ; +; |ddio_out_are:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ; +; |altddio_out2:inst5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_o2f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ; +; |altdpram0:ST_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_RED| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_RED| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM54| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM55| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |lpm_bustri_LONG:inst119| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119 ; ; +; |lpm_bustri:lpm_bustri_component| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ; +; |lpm_ff0:inst13| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 23 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 23 (23) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst14| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 31 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 31 (31) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst15| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 25 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 25 (25) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst16| ; 28 (0) ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (0) ; 2 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16 ; ; +; |lpm_ff:lpm_ff_component| ; 28 (28) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 2 (2) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst17| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 31 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 31 (31) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst18| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 30 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 30 (30) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst19| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst12| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (0) ; 2 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (30) ; 2 (2) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst20| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 28 (0) ; 4 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 28 (28) ; 4 (4) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst3| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst4| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (0) ; 6 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4 ; ; +; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst9| ; 24 (0) ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (0) ; 12 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9 ; ; +; |lpm_ff:lpm_ff_component| ; 24 (24) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 12 (12) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst46| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46 ; ; +; |lpm_ff:lpm_ff_component| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst47| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47 ; ; +; |lpm_ff:lpm_ff_component| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst49| ; 9 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49 ; ; +; |lpm_ff:lpm_ff_component| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst52| ; 9 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52 ; ; +; |lpm_ff:lpm_ff_component| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ; +; |lpm_ff4:inst10| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (0) ; 4 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10 ; ; +; |lpm_ff:lpm_ff_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 4 (4) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst11| ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11 ; ; +; |lpm_ff:lpm_ff_component| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst97| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97 ; ; +; |lpm_ff:lpm_ff_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst71| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 87 (0) ; 41 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71 ; ; +; |lpm_ff:lpm_ff_component| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 87 (87) ; 41 (41) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst94| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 85 (0) ; 43 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94 ; ; +; |lpm_ff:lpm_ff_component| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 85 (85) ; 43 (43) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ; +; |lpm_fifoDZ:inst63| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63 ; ; +; |scfifo:scfifo_component| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ; +; |scfifo_lk21:auto_generated| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated ; ; +; |a_dpfifo_oq21:dpfifo| ; 22 (9) ; 21 (8) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 21 (8) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo ; ; +; |altsyncram_gj81:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ; +; |cntr_omb:rd_ptr_msb| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb ; ; +; |cntr_pmb:wr_ptr| ; 7 (7) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr ; ; +; |lpm_fifo_dc0:inst| ; 118 (0) ; 98 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 51 (0) ; 47 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst ; ; +; |dcfifo:dcfifo_component| ; 118 (0) ; 98 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 51 (0) ; 47 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ; +; |dcfifo_8fi1:auto_generated| ; 118 (31) ; 98 (20) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (2) ; 51 (16) ; 47 (10) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; ; +; |a_graycounter_njc:wrptr_gp| ; 18 (18) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 13 (13) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ; +; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 14 (14) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ; +; |alt_synch_pipe_sld:ws_dgrp| ; 30 (0) ; 30 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ; +; |dffpipe_re9:dffpipe22| ; 30 (30) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (30) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ; +; |altsyncram_tl31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ; +; |dffpipe_9d9:wraclr| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ; +; |dffpipe_oe9:ws_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ; +; |dffpipe_oe9:ws_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ; +; |lpm_latch0:inst27| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27 ; ; +; |lpm_latch:lpm_latch_component| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ; +; |lpm_mux0:inst21| ; 120 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 71 (0) ; 27 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21 ; ; +; |lpm_mux:lpm_mux_component| ; 120 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 71 (0) ; 27 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component ; ; +; |mux_gpe:auto_generated| ; 120 (120) ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 71 (71) ; 27 (27) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated ; ; +; |lpm_mux1:inst24| ; 113 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 33 (0) ; 48 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24 ; ; +; |lpm_mux:lpm_mux_component| ; 113 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 33 (0) ; 48 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component ; ; +; |mux_npe:auto_generated| ; 113 (113) ; 81 (81) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 33 (33) ; 48 (48) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated ; ; +; |lpm_mux2:inst25| ; 81 (0) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (0) ; 1 (0) ; 40 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25 ; ; +; |lpm_mux:lpm_mux_component| ; 81 (0) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (0) ; 1 (0) ; 40 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component ; ; +; |mux_mpe:auto_generated| ; 81 (81) ; 41 (41) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 1 (1) ; 40 (40) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated ; ; +; |lpm_mux3:inst102| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102 ; ; +; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component ; ; +; |mux_96e:auto_generated| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated ; ; +; |lpm_mux4:inst81| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81 ; ; +; |lpm_mux:lpm_mux_component| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component ; ; +; |mux_f6e:auto_generated| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated ; ; +; |lpm_mux5:inst22| ; 64 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 60 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22 ; ; +; |lpm_mux:lpm_mux_component| ; 64 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 60 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component ; ; +; |mux_58e:auto_generated| ; 64 (64) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 60 (60) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated ; ; +; |lpm_mux6:inst7| ; 91 (0) ; 67 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 1 (0) ; 82 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7 ; ; +; |lpm_mux:lpm_mux_component| ; 91 (0) ; 67 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 1 (0) ; 82 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component ; ; +; |mux_kpe:auto_generated| ; 91 (91) ; 67 (67) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 1 (1) ; 82 (82) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated ; ; +; |lpm_muxDZ:inst62| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62 ; ; +; |lpm_mux:lpm_mux_component| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component ; ; +; |mux_dcf:auto_generated| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (128) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated ; ; +; |lpm_muxVDM:inst100| ; 736 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (0) ; 0 (0) ; 96 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100 ; ; +; |lpm_mux:lpm_mux_component| ; 736 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (0) ; 0 (0) ; 96 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component ; ; +; |mux_bbe:auto_generated| ; 736 (736) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (640) ; 0 (0) ; 96 (96) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated ; ; +; |lpm_shiftreg0:sr0| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr1| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr2| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr3| ; 17 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 17 (17) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr4| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr5| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr6| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr7| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg4:inst26| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg6:inst92| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ; +; |mux41:inst40| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40 ; ; +; |mux41:inst41| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41 ; ; +; |mux41:inst42| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42 ; ; +; |mux41:inst43| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43 ; ; +; |mux41:inst44| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44 ; ; +; |mux41:inst45| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45 ; ; +; |altddio_out3:inst5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst8| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst9| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9 ; work ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component ; work ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; work ; +; |altpll1:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst ; ; +; |altpll:altpll_component| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst|altpll:altpll_component ; ; +; |altpll_pul2:auto_generated| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated ; ; +; |altpll2:inst12| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12|altpll:altpll_component ; ; +; |altpll_isv2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated ; ; +; |altpll3:inst13| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13|altpll:altpll_component ; ; +; |altpll_41p2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated ; ; +; |altpll4:inst22| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22|altpll:altpll_component ; ; +; |altpll_c6j2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ; +; |altpll_reconfig1:inst7| ; 334 (0) ; 128 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 206 (0) ; 22 (0) ; 106 (0) ; |firebee1|altpll_reconfig1:inst7 ; ; +; |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 334 (237) ; 128 (80) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 206 (157) ; 22 (22) ; 106 (57) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ; +; |altsyncram:altsyncram4| ; 0 (0) ; 0 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ; +; |altsyncram_46r:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ; +; |lpm_compare:cmpr7| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 1 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ; +; |cmpr_tnd:auto_generated| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated ; ; +; |lpm_counter:cntr12| ; 10 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ; +; |cntr_30l:auto_generated| ; 10 (10) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr13| ; 7 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 6 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ; +; |cntr_qij:auto_generated| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated ; ; +; |lpm_counter:cntr14| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated ; ; +; |lpm_counter:cntr15| ; 18 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ; +; |cntr_30l:auto_generated| ; 18 (18) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr1| ; 41 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ; +; |cntr_30l:auto_generated| ; 41 (41) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr2| ; 9 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ; +; |cntr_9cj:auto_generated| ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated ; ; +; |lpm_counter:cntr3| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated ; ; +; |interrupt_handler:nobody| ; 1037 (999) ; 633 (633) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 401 (363) ; 235 (235) ; 401 (355) ; |firebee1|interrupt_handler:nobody ; ; +; |lpm_bustri_BYT:$00000| ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 9 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 9 (9) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00002| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 8 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 8 (8) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 14 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 14 (14) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00006| ; 22 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 15 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006 ; ; +; |lpm_bustri:lpm_bustri_component| ; 22 (22) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 15 (15) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ; +; |lpm_counter0:inst18| ; 19 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 17 (0) ; |firebee1|lpm_counter0:inst18 ; ; +; |lpm_counter:lpm_counter_component| ; 19 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 17 (0) ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ; +; |cntr_mph:auto_generated| ; 19 (19) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 17 (17) ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated ; ; +; |lpm_ff0:inst1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|lpm_ff0:inst1 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ; ++-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------------+----------+---------------+---------------+-----------------------+----------+----------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; ++----------------+----------+---------------+---------------+-----------------------+----------+----------+ +; CLK24M576 ; Output ; -- ; -- ; -- ; -- ; -- ; +; LP_STR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nFB_BURST ; Input ; -- ; -- ; -- ; -- ; -- ; +; nACSI_DRQ ; Input ; -- ; -- ; -- ; -- ; -- ; +; nACSI_INT ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_DRQ ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_MSG ; Input ; -- ; -- ; -- ; -- ; -- ; +; nDCHG ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_DATA0 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_DATA1 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_DATA2 ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_CARD_DEDECT ; Input ; -- ; -- ; -- ; -- ; -- ; +; SD_WP ; Input ; -- ; -- ; -- ; -- ; -- ; +; nDACK0 ; Input ; -- ; -- ; -- ; -- ; -- ; +; WP_CF_CARD ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_C_D ; Input ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_I_O ; Input ; -- ; -- ; -- ; -- ; -- ; +; nFB_CS3 ; Input ; -- ; -- ; -- ; -- ; -- ; +; CLK25M ; Output ; -- ; -- ; -- ; -- ; -- ; +; nACSI_ACK ; Output ; -- ; -- ; -- ; -- ; -- ; +; nACSI_RESET ; Output ; -- ; -- ; -- ; -- ; -- ; +; nACSI_CS ; Output ; -- ; -- ; -- ; -- ; -- ; +; ACSI_DIR ; Output ; -- ; -- ; -- ; -- ; -- ; +; ACSI_A1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_ACK ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_ATN ; Output ; -- ; -- ; -- ; -- ; -- ; +; SCSI_DIR ; Output ; -- ; -- ; -- ; -- ; -- ; +; MIDI_OLR ; Output ; -- ; -- ; -- ; -- ; -- ; +; MIDI_TLR ; Output ; -- ; -- ; -- ; -- ; -- ; +; TxD ; Output ; -- ; -- ; -- ; -- ; -- ; +; RTS ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; DTR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; AMKB_TX ; Output ; -- ; -- ; -- ; -- ; -- ; +; IDE_RES ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_CS0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_CS1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_WR ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIDE_RD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nCF_CS0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nCF_CS1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nROM3 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nROM4 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nRP_UDS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nRP_LDS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSDSEL ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nWR_GATE ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nWR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; YM_QA ; Output ; -- ; -- ; -- ; -- ; -- ; +; YM_QB ; Output ; -- ; -- ; -- ; -- ; -- ; +; YM_QC ; Output ; -- ; -- ; -- ; -- ; -- ; +; SD_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; DSA_D ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nVWE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nVCAS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nVRAS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nVCS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nPD_VGA ; Output ; -- ; -- ; -- ; -- ; -- ; +; TIN0 ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRCS ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRBLE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRBHE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSRWE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nDREQ1 ; Output ; -- ; -- ; -- ; -- ; -- ; +; LED_FPGA_OK ; Output ; -- ; -- ; -- ; -- ; -- ; +; nSROE ; Output ; -- ; -- ; -- ; -- ; -- ; +; VCKE ; Output ; -- ; -- ; -- ; -- ; -- ; +; nFB_TA ; Output ; -- ; -- ; -- ; -- ; -- ; +; nDDR_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; DDR_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; +; VSYNC_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; HSYNC_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nBLANK_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; PIXEL_CLK_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSYNC ; Output ; -- ; -- ; -- ; -- ; -- ; +; nMOT_ON ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSTEP_DIR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSTEP ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; CLKUSB ; Output ; -- ; -- ; -- ; -- ; -- ; +; LPDIR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; BA[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; BA[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; nIRQ[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[12] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[11] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[10] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[9] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[8] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[7] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[6] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[5] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[4] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[3] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[2] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[1] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VA[0] ; Output ; -- ; -- ; -- ; -- ; -- ; +; VB[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VB[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VDM[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VG[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; VR[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; TOUT0 ; Input ; -- ; -- ; -- ; -- ; -- ; +; nMASTER ; Input ; -- ; -- ; -- ; -- ; -- ; +; FB_AD[31] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[30] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[29] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[28] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[27] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[26] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[25] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[24] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[23] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[22] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[21] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[20] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[19] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[18] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[17] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[16] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[15] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[14] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[13] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[12] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[11] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[10] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[9] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[8] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[7] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[6] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[5] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[4] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[3] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[2] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[1] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; FB_AD[0] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; +; VD[31] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[30] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[29] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[28] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[27] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[26] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[25] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[24] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[23] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[22] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[21] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[20] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[19] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[18] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[17] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; +; VD[16] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[15] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[14] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[13] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[12] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[11] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; +; VD[10] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[9] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[8] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[7] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[6] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[5] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[4] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; VD[3] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; +; VD[2] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; +; VD[1] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VD[0] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; VDQS[3] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; VDQS[2] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; VDQS[1] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; VDQS[0] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; +; IO[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; IO[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SRD[15] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[14] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[13] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[12] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[11] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[10] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[9] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[8] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[7] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[6] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[5] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[4] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[3] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[2] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SRD[1] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; SRD[0] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; SCSI_PAR ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_SEL ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; nSCSI_BUSY ; Bidir ; -- ; -- ; -- ; (0) 0 ps ; -- ; +; nSCSI_RST ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SD_CD_DATA3 ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SD_CMD_D1 ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; ACSI_D[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; LP_D[7] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; LP_D[6] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[5] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[4] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[3] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; LP_D[2] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; +; LP_D[1] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; LP_D[0] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; +; SCSI_D[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; SCSI_D[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; +; nRSTO_MCF ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nFB_WR ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nFB_CS1 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; FB_SIZE1 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; FB_SIZE0 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; FB_ALE ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nFB_CS2 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; MAIN_CLK ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nDACK1 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nFB_OE ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; IDE_RDY ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; CLK33M ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; HD_DD ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nINDEX ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; RxD ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; nWP ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; LP_BUSY ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; DCD ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; CTS ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; TRACK00 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; IDE_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; RI ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; +; nPCI_INTD ; Input ; (6) 2223 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nPCI_INTC ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; +; nPCI_INTB ; Input ; (6) 2223 ps ; (0) 0 ps ; -- ; -- ; -- ; +; nPCI_INTA ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; +; DVI_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; E0_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; +; PIC_INT ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; +; PIC_AMKB_RX ; Input ; (1) 663 ps ; -- ; -- ; -- ; -- ; +; MIDI_IN ; Input ; -- ; (1) 634 ps ; -- ; -- ; -- ; +; nRD_DATA ; Input ; -- ; -- ; (0) 0 ps ; -- ; -- ; +; AMKB_RX ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; ++----------------+----------+---------------+---------------+-----------------------+----------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ +; nFB_BURST ; ; ; +; nACSI_DRQ ; ; ; +; nACSI_INT ; ; ; +; nSCSI_DRQ ; ; ; +; nSCSI_MSG ; ; ; +; nDCHG ; ; ; +; SD_DATA0 ; ; ; +; SD_DATA1 ; ; ; +; SD_DATA2 ; ; ; +; SD_CARD_DEDECT ; ; ; +; SD_WP ; ; ; +; nDACK0 ; ; ; +; WP_CF_CARD ; ; ; +; nSCSI_C_D ; ; ; +; nSCSI_I_O ; ; ; +; nFB_CS3 ; ; ; +; TOUT0 ; ; ; +; nMASTER ; ; ; +; FB_AD[31] ; ; ; +; - SRD[15]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~32 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[31] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[15] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[31]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[30] ; ; ; +; - SRD[14]~output ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[30] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[30]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[14] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[30] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[30] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[30]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[29] ; ; ; +; - SRD[13]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[29] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[29] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[29]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[29] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[29] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[29]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[29]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[28] ; ; ; +; - SRD[12]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[28] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[28]~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[12] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[12] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[28]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[28]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[28]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[27] ; ; ; +; - SRD[11]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[27]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[27] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[27] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[11]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[27]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[26] ; ; ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - SRD[10]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[12]~53 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[26]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[26] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[26] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[10]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[25] ; ; ; +; - SRD[9]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[11]~55 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[9] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[25]~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[25] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[25] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[25]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[24] ; ; ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]~22 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - SRD[8]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[10]~58 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[24]~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[24] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[24] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[24] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]~29 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[24]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]~feeder ; 1 ; 0 ; +; FB_AD[23] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]~20 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[7]~0 ; 1 ; 0 ; +; - SRD[7]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[9]~60 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[23]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[23] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][10] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][20] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][34] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][37] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][42] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][45] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][54] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][57] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[7] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][0]~73 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][2]~74 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][4]~75 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~10 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[7] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~24 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~24 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][60]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][43]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][40]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][55]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][51]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][19]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][12]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][47]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][8]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[22] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]~18 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[6]~0 ; 1 ; 0 ; +; - SRD[6]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[8]~62 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[6] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[22] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[22] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][11] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][25] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][33] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][38] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][41] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][53] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][57] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][62] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[6] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][0]~78 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][2]~79 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][4]~80 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[6]~12 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[6] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~30 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~30 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][51]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][43]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][60]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][63]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][40]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][32]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][35]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][30]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][26]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][56]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][12]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[6][18]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[22]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[5]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[21] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[5]~1 ; 1 ; 0 ; +; - SRD[5]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[7]~64 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[21] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[21] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[5] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][2]~82 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][4]~83 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][0]~85 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[5]~15 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[5] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~36 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~36 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][8]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][20]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][45]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[5]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][46]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][50]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][26]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][21]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][23]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[5][61]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[20] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]~2 ; 1 ; 0 ; +; - SRD[4]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[6]~66 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]~11 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[20] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[20] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[20] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[20] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[4] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][2]~86 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][4]~87 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][0]~89 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[4]~18 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~42 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~42 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]~27 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][58]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][22]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[4]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][50]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][61]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][46]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][26]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[4]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[4][21]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[19] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[3]~3 ; 1 ; 0 ; +; - SRD[3]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[5]~68 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[19] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[19] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][10] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][8] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][7] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[3] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[3]~21 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][2]~90 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][4]~91 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][0]~93 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~47 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~47 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]~24 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[19]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[19]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[3]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][61]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][58]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][27]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][26]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][21]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][46]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][11]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][22]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][5]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[3][50]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[18] ; ; ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[2]~4 ; 1 ; 0 ; +; - SRD[2]~output ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[4]~70 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[18] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]~13 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[18] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[18] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][24] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][27] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][33] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][35] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][37] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][39] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][41] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][49] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][54] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][57] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][59] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~6 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][0]~69 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][2]~70 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][4]~71 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[2]~9 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~18 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~18 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]~21 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[2]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][60]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][47]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][30]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][40]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][43]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[2]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][55]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][58]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][34]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][36]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][42]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][52]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[2][22]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[2]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[17] ; ; ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[1]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[1] ; 1 ; 0 ; +; - SRD[1]~output ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[3]~72 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[17] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[17] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[17] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][12] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][13] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][15] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][19] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][21] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][23] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][27] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][29] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][31] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][34] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][37] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][42] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][43] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][47] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][49] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][51] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][53] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][55] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][62] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~7 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][0]~65 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][2]~66 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][4]~67 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[1]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~12 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]~18 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[1]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][59]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][50]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][48]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][30]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[1]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][20]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][22]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[1]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][56]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][63]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][44]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][54]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][52]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][38]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][32]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][35]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][24]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][39]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[1][33]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]~feeder ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[16] ; ; ; +; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[0]~6 ; 1 ; 0 ; +; - SRD[0]~output ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VWE ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[16] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[2]~74 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[16] ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][1] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][3] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][5] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][6] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][9] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][10] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][14] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][16] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][18] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][20] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][22] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][24] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][26] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][27] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][28] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][30] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][32] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][34] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][36] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][38] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][40] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][42] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][44] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][46] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][48] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][50] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][52] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][54] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][56] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][58] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][60] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][61] ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][63] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][2]~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][4]~6 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][13]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~6 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~15 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8] ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][59]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][12]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][51]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][17]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][7]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][37]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][25]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][29]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][41]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][35]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[16]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][31]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][57]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][43]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][47]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][23]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][39]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][49]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][33]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][45]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][62]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][53]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][55]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[16]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[0]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][21]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][19]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[0]~feeder ; 1 ; 0 ; +; FB_AD[15] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[1]~76 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[15] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[14] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[0]~78 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[14] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[14] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[13] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[1]~9 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[13] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[13] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[13] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[13] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[12] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[0]~11 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[12] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[11] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]~2 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[11] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[11] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[11] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[11] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[10] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[10] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[10] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[9] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[9]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[9] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[9] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[9]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; FB_AD[8] ; ; ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]~13 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]~23 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[8]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[8] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[8] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[8]~feeder ; 1 ; 0 ; +; FB_AD[7] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~16 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]~24 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[7] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[6] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]~23 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[6]~25 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[6]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[6] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[6] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[6]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[5] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]~26 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[5]~26 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[5]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[5] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[5] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[4] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]~29 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[4]~27 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[4]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[4] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[3] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]~32 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[3]~28 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[3]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[3] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[3] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[3]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[2] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]~35 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[2]~29 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[2]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[2] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[2] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[1] ; ; ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]~41 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]~30 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[1]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[1] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[1] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]~feeder ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; FB_AD[0] ; ; ; +; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]~43 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[0]~31 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[0]~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[0] ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~5 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[0]~feeder ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]~feeder ; 1 ; 0 ; +; VD[31] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]~feeder ; 0 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]~feeder ; 0 ; 1 ; +; VD[30] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]~feeder ; 1 ; 1 ; +; VD[29] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]~feeder ; 1 ; 1 ; +; VD[28] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]~feeder ; 1 ; 1 ; +; VD[27] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]~feeder ; 1 ; 1 ; +; VD[26] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]~feeder ; 1 ; 0 ; +; VD[25] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]~feeder ; 0 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]~feeder ; 0 ; 1 ; +; VD[24] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]~feeder ; 1 ; 1 ; +; VD[23] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]~feeder ; 0 ; 0 ; +; VD[22] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]~feeder ; 1 ; 1 ; +; VD[21] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]~feeder ; 1 ; 1 ; +; VD[20] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]~feeder ; 1 ; 1 ; +; VD[19] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]~feeder ; 0 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]~feeder ; 0 ; 1 ; +; VD[18] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]~feeder ; 0 ; 0 ; +; VD[17] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]~feeder ; 1 ; 1 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]~feeder ; 1 ; 1 ; +; VD[16] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]~feeder ; 0 ; 0 ; +; VD[15] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]~feeder ; 0 ; 2 ; +; VD[14] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]~feeder ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]~feeder ; 1 ; 0 ; +; VD[13] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]~feeder ; 0 ; 2 ; +; VD[12] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]~feeder ; 0 ; 2 ; +; VD[11] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]~feeder ; 1 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]~feeder ; 1 ; 2 ; +; VD[10] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]~feeder ; 0 ; 2 ; +; VD[9] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]~feeder ; 0 ; 2 ; +; VD[8] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]~feeder ; 0 ; 0 ; +; VD[7] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]~feeder ; 0 ; 0 ; +; VD[6] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]~feeder ; 0 ; 2 ; +; VD[5] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]~feeder ; 0 ; 0 ; +; VD[4] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]~feeder ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]~feeder ; 0 ; 0 ; +; VD[3] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]~feeder ; 1 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]~feeder ; 1 ; 2 ; +; VD[2] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]~feeder ; 1 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]~feeder ; 1 ; 2 ; +; VD[1] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]~feeder ; 0 ; 2 ; +; VD[0] ; ; ; +; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]~feeder ; 0 ; 2 ; +; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]~feeder ; 0 ; 2 ; +; VDQS[3] ; ; ; +; VDQS[2] ; ; ; +; VDQS[1] ; ; ; +; VDQS[0] ; ; ; +; IO[17] ; ; ; +; IO[16] ; ; ; +; IO[15] ; ; ; +; IO[14] ; ; ; +; IO[13] ; ; ; +; IO[12] ; ; ; +; IO[11] ; ; ; +; IO[10] ; ; ; +; IO[9] ; ; ; +; IO[8] ; ; ; +; IO[7] ; ; ; +; IO[6] ; ; ; +; IO[5] ; ; ; +; IO[4] ; ; ; +; IO[3] ; ; ; +; IO[2] ; ; ; +; IO[1] ; ; ; +; IO[0] ; ; ; +; SRD[15] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~156 ; 1 ; 0 ; +; SRD[14] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~131 ; 1 ; 0 ; +; SRD[13] ; ; ; +; - DSP:Mathias_Alles|FB_AD[29]~3 ; 0 ; 0 ; +; SRD[12] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369 ; 0 ; 0 ; +; SRD[11] ; ; ; +; - DSP:Mathias_Alles|FB_AD[27]~4 ; 0 ; 0 ; +; SRD[10] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~197 ; 1 ; 0 ; +; SRD[9] ; ; ; +; - DSP:Mathias_Alles|FB_AD[25]~0 ; 1 ; 0 ; +; SRD[8] ; ; ; +; - DSP:Mathias_Alles|FB_AD[24]~1 ; 1 ; 0 ; +; SRD[7] ; ; ; +; - DSP:Mathias_Alles|FB_AD[23]~2 ; 0 ; 0 ; +; SRD[6] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~269 ; 1 ; 0 ; +; SRD[5] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~285 ; 0 ; 0 ; +; SRD[4] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~301 ; 1 ; 0 ; +; SRD[3] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~319 ; 1 ; 0 ; +; SRD[2] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~172 ; 0 ; 0 ; +; SRD[1] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~86 ; 1 ; 0 ; +; SRD[0] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54 ; 0 ; 0 ; +; SCSI_PAR ; ; ; +; nSCSI_SEL ; ; ; +; nSCSI_BUSY ; ; ; +; nSCSI_RST ; ; ; +; SD_CD_DATA3 ; ; ; +; SD_CMD_D1 ; ; ; +; ACSI_D[7] ; ; ; +; ACSI_D[6] ; ; ; +; ACSI_D[5] ; ; ; +; ACSI_D[4] ; ; ; +; ACSI_D[3] ; ; ; +; ACSI_D[2] ; ; ; +; ACSI_D[1] ; ; ; +; ACSI_D[0] ; ; ; +; LP_D[7] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~142 ; 1 ; 0 ; +; LP_D[6] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~112 ; 0 ; 0 ; +; LP_D[5] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~339 ; 0 ; 0 ; +; LP_D[4] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~378 ; 0 ; 0 ; +; LP_D[3] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~383 ; 1 ; 0 ; +; LP_D[2] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~186 ; 1 ; 0 ; +; LP_D[1] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~206 ; 0 ; 0 ; +; LP_D[0] ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~227 ; 0 ; 0 ; +; SCSI_D[7] ; ; ; +; SCSI_D[6] ; ; ; +; SCSI_D[5] ; ; ; +; SCSI_D[4] ; ; ; +; SCSI_D[3] ; ; ; +; SCSI_D[2] ; ; ; +; SCSI_D[1] ; ; ; +; SCSI_D[0] ; ; ; +; nRSTO_MCF ; ; ; +; nFB_WR ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SUB_BUS~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|TIN0~0 ; 1 ; 0 ; +; - DSP:Mathias_Alles|nSRWE~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPIO_REGISTERS~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[31]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector0~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~11 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[31]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|Selector1~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~19 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CONTROL~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~11 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~15 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT_EN~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR_READ~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR_READ~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_EN~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|Mux1~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DATA_EN~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[9]~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[8]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[6]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[5]~3 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[4]~4 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[3]~5 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[2]~6 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[1]~7 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR[0]~8 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~4 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~6 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT~5 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~14 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~17 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~218 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~42 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~238 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~35 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~37 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~40 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~350 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[3]~1 ; 0 ; 0 ; +; - DSP:Mathias_Alles|nSRWE~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nFDC_WR~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[23]~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[23]~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|RTC_ADR[5]~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[23]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~491 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[0][0]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][1]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~492 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][3]~5 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~496 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][5]~9 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~503 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~504 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~505 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~506 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][10]~10 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][12]~11 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][13]~13 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][14]~15 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][15]~16 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][16]~17 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][17]~18 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][18]~19 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][19]~20 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][20]~21 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][21]~22 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][22]~23 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][23]~24 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][24]~25 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][25]~26 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][26]~27 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][27]~28 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][28]~29 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][29]~30 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][30]~31 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][31]~32 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][32]~33 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][33]~34 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][34]~35 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][35]~36 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][36]~37 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][37]~38 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][38]~39 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][39]~40 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][40]~41 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][41]~42 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][42]~43 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][43]~44 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][44]~45 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][45]~46 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][46]~47 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][47]~48 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][48]~49 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][49]~50 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][50]~51 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][51]~52 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][52]~53 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][53]~54 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][54]~55 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][55]~56 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][56]~57 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][57]~58 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][58]~59 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][59]~60 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][60]~61 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][61]~62 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][62]~63 ; 0 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][63]~64 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15]~2 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[31]~3 ; 0 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~4 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[7]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_WR~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_RECONFIG~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|WERTE[7][11]~77 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3 ; 1 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[7]~4 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_2~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4 ; 0 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state~2 ; 1 ; 0 ; +; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state~0 ; 1 ; 0 ; +; nFB_CS1 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|TIN0~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE_CS ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT_CS~2 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF_CS ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW_CS~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|UHR_DS~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|MFP_CS~1 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|NEXT_CMD_STATE.T1~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector2~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~28 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~32 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_M ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_H ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~6 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~8 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~36 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~37 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~38 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~39 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~27 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~40 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~41 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[9]~81 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~43 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~38 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~44 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~45 ; 1 ; 0 ; +; - interrupt_handler:nobody|TIN0~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_L ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~46 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~47 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~48 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~49 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~50 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~51 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~52 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~53 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~54 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~55 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~34 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~35 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[2]~36 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS ; 1 ; 0 ; +; FB_SIZE1 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[0]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~22 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|UHR_AS~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|UHR_DS~6 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~194 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[2]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; 1 ; 0 ; +; FB_SIZE0 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[0]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~22 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|UHR_AS~0 ; 1 ; 0 ; +; - interrupt_handler:nobody|UHR_DS~6 ; 1 ; 0 ; +; - interrupt_handler:nobody|_~194 ; 1 ; 0 ; +; - interrupt_handler:nobody|FB_B[2]~1 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0] ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; 0 ; 0 ; +; FB_ALE ; ; ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; 0 ; 0 ; +; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5 ; 1 ; 0 ; +; nFB_CS2 ; ; ; +; - DSP:Mathias_Alles|nSRCS~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~4 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_RECONFIG_CS~0 ; 0 ; 0 ; +; - inst2~3 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[31]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_CONFIG_CS~0 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|_~23 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|_~25 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~13 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~14 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~147 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~148 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR_CS ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CLEAR_CS ; 0 ; 0 ; +; - interrupt_handler:nobody|_~195 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~196 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~198 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~199 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~200 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~201 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~24 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~25 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~246 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~247 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~35 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~41 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~42 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~248 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~46 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~47 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~295 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~53 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~54 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~338 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~339 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~60 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~61 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~382 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~383 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~67 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~68 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~426 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~427 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~470 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~471 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~473 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~474 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~71 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~475 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~476 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~73 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~74 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~477 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~75 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~76 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~480 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~77 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~78 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~79 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~80 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~483 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~484 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~485 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~486 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~487 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~488 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~489 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~490 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[23]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_CTR[15]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|INT_ENA[15]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[15]~3 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2 ; 0 ; 0 ; +; - interrupt_handler:nobody|ACP_CONF[7]~4 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~508 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42 ; 0 ; 0 ; +; MAIN_CLK ; ; ; +; nDACK1 ; ; ; +; nFB_OE ; ; ; +; - DSP:Mathias_Alles|nSROE~0 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~39 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~40 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~43 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[0]~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~45 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~47 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~48 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_RD ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_RD ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~51 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[3]~2 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[0]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~55 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~56 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[1]~4 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[2]~5 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~59 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~60 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~61 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~65 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~10 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~67 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~70 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~72 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~77 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[3]~28 ; 1 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[1]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~85 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~89 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~94 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~111 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~124 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~127 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~129 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDH ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[14]~34 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[15]~40 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~154 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~160 ; 1 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[2]~6 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDL~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~170 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~175 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~176 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~179 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~181 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~182 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~193 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~195 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~211 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[25]~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~215 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~220 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[24]~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~235 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~240 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[7]~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~250 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[23]~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~255 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[6]~12 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~267 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~272 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[5]~15 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~283 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~288 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[4]~18 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~299 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~304 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~308 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~312 ; 0 ; 0 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[3]~21 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~317 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[15]~327 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~352 ; 0 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[29]~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~356 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[13]~173 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~366 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~375 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~388 ; 1 ; 0 ; +; - DSP:Mathias_Alles|FB_AD[27]~4 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~392 ; 1 ; 0 ; +; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[11]~186 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~411 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~415 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~420 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~424 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[7]~432 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[6]~437 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[5]~445 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[4]~453 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[3]~461 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[2]~469 ; 0 ; 0 ; +; - interrupt_handler:nobody|_~508 ; 0 ; 0 ; +; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~490 ; 1 ; 0 ; +; IDE_RDY ; ; ; +; - inst2~1 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~0 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_TA~0 ; 1 ; 0 ; +; CLK33M ; ; ; +; HD_DD ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|HD_DD_OUT~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~62 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PHASE_DECODER~0 ; 1 ; 0 ; +; nINDEX ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~78 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOCK~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~113 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~173 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_COUNTER~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ~4 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~205 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DRQ_IPn~0 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_INDEX_MARK:LOCK~0 ; 0 ; 0 ; +; - nINDEX~_wirecell ; 0 ; 0 ; +; RxD ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|SDATA_IN_I~1 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SDATA_IN_I~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_SAMPLE~6 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_START_BIT~0 ; 0 ; 0 ; +; nWP ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~85 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~168 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~176 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR~0 ; 1 ; 0 ; +; LP_BUSY ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[0]~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~15 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~15 ; 0 ; 0 ; +; DCD ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[1]~43 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~10 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~10 ; 0 ; 0 ; +; CTS ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[2]~63 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~9 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~9 ; 1 ; 0 ; +; TRACK00 ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TR_CLR ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~18 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~20 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~22 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~24 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~26 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~28 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~103 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~2 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~3 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30 ; 0 ; 0 ; +; IDE_INT ; ; ; +; RI ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~11 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT~104 ; 1 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~11 ; 1 ; 0 ; +; nPCI_INTD ; ; ; +; - interrupt_handler:nobody|INT_LATCH[6]~11 ; 0 ; 6 ; +; - interrupt_handler:nobody|_~484 ; 1 ; 0 ; +; nPCI_INTC ; ; ; +; - interrupt_handler:nobody|INT_LATCH[5]~12 ; 1 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[5]~5 ; 0 ; 0 ; +; nPCI_INTB ; ; ; +; - interrupt_handler:nobody|INT_LATCH[4]~13 ; 0 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[4]~8 ; 1 ; 0 ; +; nPCI_INTA ; ; ; +; - interrupt_handler:nobody|INT_LATCH[3]~14 ; 1 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[3]~11 ; 0 ; 0 ; +; DVI_INT ; ; ; +; E0_INT ; ; ; +; PIC_INT ; ; ; +; - interrupt_handler:nobody|INT_LATCH[0]~17 ; 1 ; 6 ; +; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[0]~20 ; 0 ; 0 ; +; - interrupt_handler:nobody|PIC_INT_SYNC[0] ; 0 ; 0 ; +; PIC_AMKB_RX ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|KEYB_RxD ; 0 ; 1 ; +; MIDI_IN ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_I~feeder ; 1 ; 1 ; +; nRD_DATA ; ; ; +; AMKB_RX ; ; ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~11 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]~9 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]~7 ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; 0 ; 0 ; +; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13 ; 1 ; 0 ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ +; CLK33M ; PIN_AB12 ; 12 ; Clock ; yes ; Global Clock ; GCLK15 ; -- ; +; CLK33M ; PIN_AB12 ; 5 ; Clock ; no ; -- ; -- ; -- ; +; DSP:Mathias_Alles|nSRWE~1 ; LCCOMB_X23_Y8_N20 ; 16 ; Output enable ; no ; -- ; -- ; -- ; +; FB_ALE ; PIN_R7 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13 ; LCCOMB_X1_Y10_N14 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO ; LCCOMB_X26_Y22_N16 ; 250 ; Async. clear ; yes ; Global Clock ; GCLK7 ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1 ; LCCOMB_X18_Y17_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1 ; LCCOMB_X22_Y14_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1 ; LCCOMB_X22_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~0 ; LCCOMB_X16_Y14_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]~1 ; LCCOMB_X16_Y14_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 ; LCCOMB_X21_Y12_N8 ; 16 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 ; LCCOMB_X22_Y13_N12 ; 2 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 ; LCCOMB_X22_Y13_N30 ; 4 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 ; LCCOMB_X22_Y13_N4 ; 2 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 ; LCCOMB_X22_Y13_N16 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 ; LCCOMB_X22_Y13_N10 ; 2 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 ; LCCOMB_X33_Y1_N4 ; 5 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector4~1 ; LCCOMB_X23_Y18_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~1 ; LCCOMB_X22_Y13_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|Equal0~4 ; LCCOMB_X22_Y28_N30 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]~1 ; LCCOMB_X21_Y28_N6 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]~3 ; LCCOMB_X21_Y28_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SHFT ; FF_X34_Y29_N7 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SHFT_LOAD_ND~0 ; LCCOMB_X28_Y27_N8 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47 ; LCCOMB_X35_Y25_N2 ; 88 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector78~0 ; LCCOMB_X32_Y25_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor2~5 ; LCCOMB_X36_Y28_N0 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor8 ; LCCOMB_X28_Y27_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]~1 ; LCCOMB_X32_Y27_N4 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]~37 ; LCCOMB_X27_Y26_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT~27 ; LCCOMB_X30_Y30_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE ; FF_X30_Y32_N13 ; 18 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]~1 ; LCCOMB_X27_Y32_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7] ; FF_X32_Y25_N31 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]~1 ; LCCOMB_X32_Y25_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Equal3~2 ; LCCOMB_X27_Y25_N14 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~1 ; LCCOMB_X29_Y25_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]~9 ; LCCOMB_X28_Y27_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG~8 ; LCCOMB_X30_Y28_N22 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~1 ; LCCOMB_X30_Y26_N20 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]~3 ; LCCOMB_X30_Y26_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT~1 ; LCCOMB_X28_Y30_N28 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT~12 ; LCCOMB_X36_Y29_N10 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK~0 ; LCCOMB_X25_Y29_N26 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]~0 ; LCCOMB_X25_Y27_N6 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1 ; LCCOMB_X18_Y19_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0 ; LCCOMB_X15_Y14_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; FF_X4_Y41_N5 ; 8 ; Output enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0 ; LCCOMB_X7_Y39_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0 ; LCCOMB_X19_Y23_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WAV_STRB ; FF_X9_Y21_N23 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0 ; LCCOMB_X17_Y22_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET ; FF_X18_Y22_N21 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0 ; LCCOMB_X18_Y22_N20 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0 ; LCCOMB_X18_Y24_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB~1 ; LCCOMB_X18_Y23_N8 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal14~3 ; LCCOMB_X20_Y21_N28 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal16~3 ; LCCOMB_X19_Y24_N20 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal18~3 ; LCCOMB_X18_Y20_N28 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0 ; LCCOMB_X15_Y14_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1 ; LCCOMB_X20_Y23_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0 ; LCCOMB_X19_Y24_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1 ; LCCOMB_X20_Y20_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0 ; LCCOMB_X18_Y20_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1 ; LCCOMB_X17_Y18_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0 ; LCCOMB_X17_Y25_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0 ; LCCOMB_X20_Y22_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0 ; LCCOMB_X21_Y27_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0 ; LCCOMB_X17_Y19_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT~1 ; LCCOMB_X17_Y25_N24 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]~12 ; LCCOMB_X18_Y25_N10 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]~0 ; LCCOMB_X16_Y24_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]~0 ; LCCOMB_X16_Y24_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]~2 ; LCCOMB_X16_Y24_N24 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]~0 ; LCCOMB_X6_Y18_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1 ; LCCOMB_X4_Y19_N12 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]~1 ; LCCOMB_X5_Y18_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0 ; LCCOMB_X2_Y21_N28 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]~1 ; LCCOMB_X5_Y17_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]~1 ; LCCOMB_X1_Y18_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1 ; LCCOMB_X1_Y19_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]~1 ; LCCOMB_X3_Y19_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]~1 ; LCCOMB_X2_Y19_N2 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE ; FF_X1_Y20_N15 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]~3 ; LCCOMB_X1_Y20_N26 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]~1 ; LCCOMB_X7_Y18_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1 ; LCCOMB_X4_Y19_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]~1 ; LCCOMB_X5_Y16_N14 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0 ; LCCOMB_X3_Y17_N26 ; 6 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]~1 ; LCCOMB_X4_Y17_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]~1 ; LCCOMB_X3_Y17_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1 ; LCCOMB_X5_Y20_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]~1 ; LCCOMB_X4_Y21_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]~1 ; LCCOMB_X5_Y21_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE ; FF_X6_Y19_N27 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]~1 ; LCCOMB_X6_Y19_N28 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0 ; LCCOMB_X14_Y18_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0 ; LCCOMB_X14_Y14_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0 ; LCCOMB_X14_Y15_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0 ; LCCOMB_X14_Y16_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0 ; LCCOMB_X14_Y16_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0 ; LCCOMB_X16_Y19_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0 ; LCCOMB_X16_Y19_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[9]~5 ; LCCOMB_X17_Y21_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST ; FF_X16_Y17_N3 ; 23 ; Sync. clear ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[0]~7 ; LCCOMB_X17_Y17_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]~0 ; LCCOMB_X16_Y16_N4 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_A~0 ; LCCOMB_X6_Y20_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_B~0 ; LCCOMB_X6_Y20_N8 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_C~0 ; LCCOMB_X3_Y20_N0 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_D~0 ; LCCOMB_X9_Y17_N6 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0 ; LCCOMB_X12_Y16_N22 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~0 ; LCCOMB_X8_Y20_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0 ; LCCOMB_X10_Y18_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~0 ; LCCOMB_X7_Y17_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0 ; LCCOMB_X12_Y18_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~0 ; LCCOMB_X10_Y15_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]~0 ; LCCOMB_X4_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERC~1 ; LCCOMB_X10_Y15_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERD~1 ; LCCOMB_X3_Y15_N4 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[0]~0 ; LCCOMB_X10_Y18_N16 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[0]~3 ; LCCOMB_X12_Y17_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[0]~1 ; LCCOMB_X11_Y18_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[0]~1 ; LCCOMB_X11_Y18_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL_STRB ; FF_X3_Y20_N7 ; 44 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]~0 ; LCCOMB_X14_Y19_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]~0 ; LCCOMB_X14_Y22_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]~1 ; LCCOMB_X14_Y19_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]~0 ; LCCOMB_X12_Y16_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7] ; FF_X14_Y20_N1 ; 19 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~3 ; LCCOMB_X11_Y19_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]~2 ; LCCOMB_X10_Y24_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]~1 ; LCCOMB_X10_Y22_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[0]~0 ; LCCOMB_X3_Y27_N20 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT~1 ; LCCOMB_X14_Y23_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|CLK_STRB ; FF_X2_Y27_N7 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFTREG~0 ; LCCOMB_X12_Y21_N12 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]~8 ; LCCOMB_X12_Y23_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TX_END ; FF_X12_Y23_N17 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|_~0 ; LCCOMB_X21_Y9_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1 ; LCCOMB_X23_Y7_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_wrreq~1 ; LCCOMB_X18_Y18_N20 ; 18 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|_~0 ; LCCOMB_X22_Y22_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_rdreq~1 ; LCCOMB_X22_Y22_N4 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_wrreq~0 ; LCCOMB_X26_Y24_N4 ; 22 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0 ; LCCOMB_X20_Y16_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0 ; LCCOMB_X20_Y16_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 ; LCCOMB_X26_Y22_N14 ; 32 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ; +; MAIN_CLK ; PIN_G2 ; 2272 ; Clock ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT ; FF_X23_Y12_N17 ; 26 ; Sync. load ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]~1 ; LCCOMB_X27_Y6_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4 ; LCCOMB_X22_Y2_N22 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2 ; LCCOMB_X34_Y2_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3 ; LCCOMB_X21_Y4_N10 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3] ; LCCOMB_X34_Y2_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]~40 ; LCCOMB_X26_Y8_N24 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0 ; LCCOMB_X26_Y11_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0 ; LCCOMB_X26_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; LCCOMB_X25_Y11_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0 ; LCCOMB_X23_Y11_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[1] ; LCCOMB_X25_Y16_N22 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[2] ; LCCOMB_X25_Y14_N26 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[3] ; LCCOMB_X25_Y16_N0 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3 ; LCCOMB_X22_Y19_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0 ; LCCOMB_X23_Y12_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2 ; LCCOMB_X27_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1 ; LCCOMB_X23_Y18_N22 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6 ; LCCOMB_X28_Y18_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1 ; LCCOMB_X21_Y19_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0 ; LCCOMB_X29_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2 ; LCCOMB_X23_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3 ; LCCOMB_X23_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1 ; LCCOMB_X23_Y19_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0 ; LCCOMB_X28_Y15_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2 ; LCCOMB_X25_Y17_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3 ; LCCOMB_X22_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1 ; LCCOMB_X21_Y19_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0 ; LCCOMB_X28_Y15_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2 ; LCCOMB_X28_Y17_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3 ; LCCOMB_X28_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1 ; LCCOMB_X23_Y19_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0 ; LCCOMB_X29_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2 ; LCCOMB_X25_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3 ; LCCOMB_X25_Y17_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1 ; LCCOMB_X22_Y18_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0 ; LCCOMB_X29_Y18_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2 ; LCCOMB_X23_Y18_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; FF_X33_Y18_N13 ; 54 ; Sync. load ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; FF_X33_Y18_N15 ; 54 ; Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; FF_X29_Y21_N3 ; 34 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_FIFO_CLR ; FF_X36_Y17_N25 ; 21 ; Async. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0] ; LCCOMB_X23_Y16_N24 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[1] ; LCCOMB_X23_Y16_N8 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[3] ; LCCOMB_X23_Y16_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3 ; LCCOMB_X28_Y16_N22 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1 ; LCCOMB_X28_Y16_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; FF_X37_Y20_N27 ; 141 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; FF_X33_Y12_N25 ; 30 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 3 ; Clock ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 850 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0] ; LCCOMB_X26_Y13_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[1] ; LCCOMB_X21_Y13_N14 ; 1 ; Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; LCCOMB_X29_Y17_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[6]~7 ; LCCOMB_X35_Y17_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX ; FF_X34_Y14_N13 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0 ; LCCOMB_X26_Y16_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]~1 ; LCCOMB_X30_Y13_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]~0 ; LCCOMB_X30_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~1 ; LCCOMB_X30_Y10_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]~0 ; LCCOMB_X29_Y10_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]~1 ; LCCOMB_X30_Y10_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]~0 ; LCCOMB_X29_Y10_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]~1 ; LCCOMB_X33_Y13_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]~0 ; LCCOMB_X33_Y13_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]~1 ; LCCOMB_X30_Y12_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]~0 ; LCCOMB_X30_Y12_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]~1 ; LCCOMB_X29_Y14_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]~0 ; LCCOMB_X26_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1 ; LCCOMB_X26_Y17_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0 ; LCCOMB_X27_Y15_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3 ; LCCOMB_X26_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2 ; LCCOMB_X26_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]~1 ; LCCOMB_X30_Y15_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~0 ; LCCOMB_X29_Y15_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]~1 ; LCCOMB_X25_Y13_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~0 ; LCCOMB_X30_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0 ; LCCOMB_X26_Y18_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1 ; LCCOMB_X26_Y13_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]~1 ; LCCOMB_X29_Y14_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]~0 ; LCCOMB_X29_Y13_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]~1 ; LCCOMB_X30_Y15_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]~0 ; LCCOMB_X29_Y16_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]~1 ; LCCOMB_X26_Y14_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]~0 ; LCCOMB_X27_Y16_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0 ; LCCOMB_X25_Y18_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1 ; LCCOMB_X27_Y18_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0 ; LCCOMB_X26_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~3 ; LCCOMB_X27_Y18_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~92 ; LCCOMB_X28_Y20_N4 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst37 ; LCCOMB_X66_Y4_N2 ; 32 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst65~0 ; LCCOMB_X37_Y20_N28 ; 34 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst67 ; LCCOMB_X37_Y17_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90 ; DDIOOECELL_X63_Y0_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; DDIOOECELL_X67_Y11_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; DDIOOECELL_X52_Y0_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; DDIOOECELL_X43_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|inst95 ; FF_X39_Y18_N21 ; 128 ; Sync. load ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|_~0 ; LCCOMB_X36_Y20_N2 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21 ; 72 ; Async. clear ; yes ; Global Clock ; GCLK9 ; -- ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0 ; LCCOMB_X57_Y17_N14 ; 14 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; FF_X45_Y15_N1 ; 258 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; FF_X18_Y13_N29 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; +; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; FF_X18_Y13_N3 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; PLL_3 ; 52 ; Clock ; yes ; Global Clock ; GCLK14 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; PLL_1 ; 691 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; PLL_1 ; 96 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; PLL_1 ; 5 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; PLL_1 ; 41 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; PLL_1 ; 189 ; Clock, Latch enable ; yes ; Global Clock ; GCLK4 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; PLL_4 ; 7 ; Clock ; yes ; Global Clock ; GCLK16 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; PLL_4 ; 585 ; Clock ; yes ; Global Clock ; GCLK17 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; PLL_4 ; 4 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; PLL_4 ; 2 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~1 ; LCCOMB_X23_Y26_N8 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|busy ; LCCOMB_X22_Y25_N2 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|input_latch_enable~0 ; LCCOMB_X22_Y26_N10 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X14_Y25_N0 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|_~0 ; LCCOMB_X19_Y28_N4 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X21_Y29_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|_~9 ; LCCOMB_X21_Y27_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X18_Y29_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|_~0 ; LCCOMB_X21_Y26_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~4 ; LCCOMB_X21_Y26_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~5 ; LCCOMB_X21_Y27_N12 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~0 ; LCCOMB_X21_Y29_N6 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~1 ; LCCOMB_X18_Y29_N24 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state ; FF_X22_Y29_N31 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|scan_cache_write_enable~0 ; LCCOMB_X20_Y26_N4 ; 3 ; Write enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~3 ; LCCOMB_X22_Y23_N2 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg_clear~0 ; LCCOMB_X22_Y27_N28 ; 35 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state ; FF_X21_Y25_N29 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; +; inst25 ; LCCOMB_X15_Y23_N20 ; 1027 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK10 ; -- ; +; inst25 ; LCCOMB_X15_Y23_N20 ; 119 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACHTELSEKUNDEN[2]~0 ; LCCOMB_X1_Y13_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[15]~3 ; LCCOMB_X16_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[23]~1 ; LCCOMB_X11_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[31]~0 ; LCCOMB_X16_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|ACP_CONF[7]~4 ; LCCOMB_X15_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[0] ; FF_X17_Y10_N9 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[1] ; FF_X17_Y10_N31 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[2] ; FF_X17_Y10_N1 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[3] ; FF_X17_Y10_N23 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[4] ; FF_X17_Y10_N21 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[5] ; FF_X17_Y10_N11 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[6] ; FF_X17_Y10_N25 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[8] ; FF_X17_Y10_N15 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CLEAR[9] ; FF_X17_Y10_N29 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[15]~2 ; LCCOMB_X15_Y15_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[23]~1 ; LCCOMB_X12_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[31]~3 ; LCCOMB_X18_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_CTR[7]~0 ; LCCOMB_X15_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[15]~2 ; LCCOMB_X15_Y15_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[23]~1 ; LCCOMB_X12_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[31]~0 ; LCCOMB_X16_Y13_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_ENA[7]~3 ; LCCOMB_X15_Y13_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[0]~26 ; LCCOMB_X14_Y13_N30 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[1]~25 ; LCCOMB_X15_Y11_N22 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[2]~24 ; LCCOMB_X15_Y11_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[3]~23 ; LCCOMB_X15_Y10_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[4]~22 ; LCCOMB_X14_Y13_N20 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[5]~21 ; LCCOMB_X15_Y11_N0 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[6]~20 ; LCCOMB_X15_Y12_N26 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[8]~19 ; LCCOMB_X15_Y15_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|INT_LATCH[9]~18 ; LCCOMB_X15_Y15_N16 ; 1 ; Clock ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|RTC_ADR[5]~0 ; LCCOMB_X8_Y12_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[0][0]~1 ; LCCOMB_X6_Y15_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[0][13]~14 ; LCCOMB_X4_Y14_N22 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[0][2]~4 ; LCCOMB_X7_Y15_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][10]~10 ; LCCOMB_X7_Y14_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][11]~77 ; LCCOMB_X1_Y13_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][12]~11 ; LCCOMB_X8_Y13_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][13]~13 ; LCCOMB_X6_Y14_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][14]~15 ; LCCOMB_X7_Y14_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][15]~16 ; LCCOMB_X11_Y13_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][16]~17 ; LCCOMB_X4_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][17]~18 ; LCCOMB_X3_Y11_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][18]~19 ; LCCOMB_X2_Y14_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][19]~20 ; LCCOMB_X2_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][1]~2 ; LCCOMB_X7_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][20]~21 ; LCCOMB_X2_Y13_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][21]~22 ; LCCOMB_X3_Y14_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][22]~23 ; LCCOMB_X2_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][23]~24 ; LCCOMB_X3_Y10_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][24]~25 ; LCCOMB_X3_Y10_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][25]~26 ; LCCOMB_X2_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][26]~27 ; LCCOMB_X2_Y12_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][27]~28 ; LCCOMB_X4_Y9_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][28]~29 ; LCCOMB_X4_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][29]~30 ; LCCOMB_X3_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][30]~31 ; LCCOMB_X3_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][31]~32 ; LCCOMB_X5_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][32]~33 ; LCCOMB_X4_Y10_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][33]~34 ; LCCOMB_X8_Y10_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][34]~35 ; LCCOMB_X8_Y10_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][35]~36 ; LCCOMB_X4_Y10_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][36]~37 ; LCCOMB_X2_Y10_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][37]~38 ; LCCOMB_X2_Y10_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][38]~39 ; LCCOMB_X7_Y10_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][39]~40 ; LCCOMB_X4_Y10_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][3]~5 ; LCCOMB_X6_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][40]~41 ; LCCOMB_X6_Y9_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][41]~42 ; LCCOMB_X5_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][42]~43 ; LCCOMB_X6_Y9_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][43]~44 ; LCCOMB_X9_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][44]~45 ; LCCOMB_X10_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][45]~46 ; LCCOMB_X10_Y10_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][46]~47 ; LCCOMB_X10_Y10_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][47]~48 ; LCCOMB_X9_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][48]~49 ; LCCOMB_X9_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][49]~50 ; LCCOMB_X9_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][50]~51 ; LCCOMB_X9_Y10_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][51]~52 ; LCCOMB_X8_Y9_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][52]~53 ; LCCOMB_X7_Y9_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][53]~54 ; LCCOMB_X11_Y9_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][54]~55 ; LCCOMB_X10_Y9_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][55]~56 ; LCCOMB_X10_Y11_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][56]~57 ; LCCOMB_X10_Y9_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][57]~58 ; LCCOMB_X8_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][58]~59 ; LCCOMB_X8_Y12_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][59]~60 ; LCCOMB_X9_Y12_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][5]~9 ; LCCOMB_X6_Y14_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][60]~61 ; LCCOMB_X5_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][61]~62 ; LCCOMB_X5_Y12_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][62]~63 ; LCCOMB_X12_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|WERTE[7][63]~64 ; LCCOMB_X11_Y12_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~503 ; LCCOMB_X6_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~504 ; LCCOMB_X5_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~505 ; LCCOMB_X4_Y14_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; +; interrupt_handler:nobody|_~506 ; LCCOMB_X7_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ +; CLK33M ; PIN_AB12 ; 12 ; 0 ; Global Clock ; GCLK15 ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO ; LCCOMB_X26_Y22_N16 ; 250 ; 0 ; Global Clock ; GCLK7 ; -- ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 ; LCCOMB_X26_Y22_N14 ; 32 ; 0 ; Global Clock ; GCLK5 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; FF_X29_Y21_N3 ; 34 ; 0 ; Global Clock ; GCLK11 ; -- ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 850 ; 0 ; Global Clock ; GCLK6 ; -- ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21 ; 72 ; 0 ; Global Clock ; GCLK9 ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; PLL_3 ; 52 ; 0 ; Global Clock ; GCLK14 ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; PLL_3 ; 1 ; 0 ; Global Clock ; GCLK12 ; -- ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; PLL_3 ; 1 ; 0 ; Global Clock ; GCLK13 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; PLL_1 ; 691 ; 0 ; Global Clock ; GCLK3 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; PLL_1 ; 96 ; 0 ; Global Clock ; GCLK1 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; PLL_1 ; 5 ; 0 ; Global Clock ; GCLK0 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; PLL_1 ; 41 ; 0 ; Global Clock ; GCLK2 ; -- ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; PLL_1 ; 189 ; 0 ; Global Clock ; GCLK4 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; PLL_4 ; 7 ; 0 ; Global Clock ; GCLK16 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; PLL_4 ; 585 ; 0 ; Global Clock ; GCLK17 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; PLL_4 ; 4 ; 0 ; Global Clock ; GCLK18 ; -- ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; PLL_4 ; 2 ; 0 ; Global Clock ; GCLK19 ; -- ; +; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ; +; inst25 ; LCCOMB_X15_Y23_N20 ; 1027 ; 0 ; Global Clock ; GCLK10 ; -- ; ++---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++-----------------------------------------------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++-----------------------------------------------------------------------------------------------------------------------------------+---------+ +; MAIN_CLK~input ; 2272 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; 385 ; +; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; 258 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; 257 ; +; nFB_WR~input ; 235 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; 225 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; 208 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; 161 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; 158 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; 156 ; +; FB_AD[17]~input ; 145 ; +; FB_AD[18]~input ; 145 ; +; FB_AD[20]~input ; 144 ; +; FB_AD[16]~input ; 143 ; +; FB_AD[19]~input ; 143 ; +; FB_AD[21]~input ; 143 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; 141 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; 141 ; +; FB_AD[22]~input ; 140 ; +; FB_AD[23]~input ; 137 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; 132 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; 132 ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; 129 ; +; Video:Fredi_Aschwanden|inst95 ; 128 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; 120 ; +; inst25 ; 118 ; +; nFB_OE~input ; 101 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; 97 ; +; nFB_CS2~input ; 95 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47 ; 88 ; +; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; 83 ; +; interrupt_handler:nobody|RTC_ADR[4] ; 80 ; +; interrupt_handler:nobody|RTC_ADR[5] ; 79 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ROLL_OVER ; 78 ; +; interrupt_handler:nobody|UHR_DS~5 ; 71 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1 ; 68 ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; 66 ; +; interrupt_handler:nobody|UHR_DS~6 ; 66 ; +; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; 65 ; +; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; 64 ; +; FB_AD[24]~input ; 63 ; +; interrupt_handler:nobody|RTC_ADR[3] ; 62 ; +; interrupt_handler:nobody|RTC_ADR[2] ; 62 ; +; interrupt_handler:nobody|RTC_ADR[1] ; 62 ; +; interrupt_handler:nobody|RTC_ADR[0] ; 62 ; +; ~GND ; 61 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; 60 ; +; nFB_CS1~input ; 59 ; +; FB_AD[25]~input ; 59 ; +; FB_AD[26]~input ; 57 ; ++-----------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 8 ; 256 ; 32 ; yes ; no ; yes ; yes ; 8192 ; 1024 ; 8 ; 256 ; 32 ; 8192 ; 1 ; None ; M9K_X24_Y11_N0 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 256 ; 32 ; 1024 ; 8 ; yes ; no ; yes ; yes ; 8192 ; 256 ; 32 ; 1024 ; 8 ; 8192 ; 1 ; None ; M9K_X24_Y21_N0 ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y15_N0 ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y15_N0 ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y13_N0 ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y20_N0 ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y19_N0 ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y17_N0 ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y14_N0 ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y16_N0 ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y18_N0 ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 128 ; 128 ; 128 ; yes ; no ; yes ; no ; 16384 ; 128 ; 128 ; 128 ; 128 ; 16384 ; 4 ; None ; M9K_X40_Y19_N0, M9K_X40_Y20_N0, M9K_X40_Y21_N0, M9K_X40_Y22_N0 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 128 ; 512 ; 128 ; yes ; no ; yes ; yes ; 65536 ; 512 ; 128 ; 512 ; 128 ; 65536 ; 8 ; None ; M9K_X40_Y16_N0, M9K_X40_Y15_N0, M9K_X58_Y16_N0, M9K_X58_Y17_N0, M9K_X40_Y17_N0, M9K_X40_Y14_N0, M9K_X40_Y13_N0, M9K_X40_Y18_N0 ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 144 ; 1 ; -- ; -- ; yes ; no ; -- ; -- ; 144 ; 144 ; 1 ; -- ; -- ; 144 ; 1 ; None ; M9K_X24_Y25_N0 ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++-----------------------------------------------------------------------------------------------+ +; Fitter DSP Block Usage Summary ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Statistic ; Number Used ; Available per Block ; Maximum Available ; ++---------------------------------------+-------------+---------------------+-------------------+ +; Simple Multipliers (9-bit) ; 0 ; 2 ; 252 ; +; Simple Multipliers (18-bit) ; 3 ; 1 ; 126 ; +; Embedded Multiplier Blocks ; 3 ; -- ; 126 ; +; Embedded Multiplier 9-bit elements ; 6 ; 2 ; 252 ; +; Signed Embedded Multipliers ; 0 ; -- ; -- ; +; Unsigned Embedded Multipliers ; 3 ; -- ; -- ; +; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ; +; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ; ++---------------------------------------+-------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; DSP Block Details ; ++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ; ++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y14_N2 ; ; No ; ; ; ; no ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y14_N0 ; Unsigned ; ; no ; no ; no ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y10_N2 ; ; No ; ; ; ; no ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y10_N0 ; Unsigned ; ; no ; no ; no ; ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y12_N2 ; ; No ; ; ; ; no ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y12_N0 ; Unsigned ; ; no ; no ; no ; ; ++------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ + + ++--------------------------------------------------------+ +; Interconnect Usage Summary ; ++----------------------------+---------------------------+ +; Interconnect Resource Type ; Usage ; ++----------------------------+---------------------------+ +; Block interconnects ; 16,358 / 116,715 ( 14 % ) ; +; C16 interconnects ; 749 / 3,886 ( 19 % ) ; +; C4 interconnects ; 10,626 / 73,752 ( 14 % ) ; +; Direct links ; 2,046 / 116,715 ( 2 % ) ; +; Global clocks ; 20 / 20 ( 100 % ) ; +; Local interconnects ; 4,734 / 39,600 ( 12 % ) ; +; R24 interconnects ; 882 / 3,777 ( 23 % ) ; +; R4 interconnects ; 11,442 / 99,858 ( 11 % ) ; ++----------------------------+---------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Logic Elements ; ++---------------------------------------------+-------------------------------+ +; Number of Logic Elements (Average = 12.60) ; Number of LABs (Total = 756) ; ++---------------------------------------------+-------------------------------+ +; 1 ; 41 ; +; 2 ; 20 ; +; 3 ; 22 ; +; 4 ; 11 ; +; 5 ; 13 ; +; 6 ; 12 ; +; 7 ; 15 ; +; 8 ; 13 ; +; 9 ; 13 ; +; 10 ; 30 ; +; 11 ; 23 ; +; 12 ; 32 ; +; 13 ; 29 ; +; 14 ; 47 ; +; 15 ; 59 ; +; 16 ; 376 ; ++---------------------------------------------+-------------------------------+ + + ++--------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-------------------------------+ +; LAB-wide Signals (Average = 1.78) ; Number of LABs (Total = 756) ; ++------------------------------------+-------------------------------+ +; 1 Async. clear ; 239 ; +; 1 Clock ; 631 ; +; 1 Clock enable ; 289 ; +; 1 Sync. clear ; 20 ; +; 1 Sync. load ; 26 ; +; 2 Async. clears ; 12 ; +; 2 Clock enables ; 84 ; +; 2 Clocks ; 41 ; ++------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-------------------------------+ +; Number of Signals Sourced (Average = 18.19) ; Number of LABs (Total = 756) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 19 ; +; 2 ; 26 ; +; 3 ; 12 ; +; 4 ; 16 ; +; 5 ; 8 ; +; 6 ; 14 ; +; 7 ; 5 ; +; 8 ; 11 ; +; 9 ; 8 ; +; 10 ; 14 ; +; 11 ; 9 ; +; 12 ; 20 ; +; 13 ; 17 ; +; 14 ; 15 ; +; 15 ; 30 ; +; 16 ; 49 ; +; 17 ; 41 ; +; 18 ; 43 ; +; 19 ; 30 ; +; 20 ; 42 ; +; 21 ; 35 ; +; 22 ; 49 ; +; 23 ; 45 ; +; 24 ; 31 ; +; 25 ; 31 ; +; 26 ; 27 ; +; 27 ; 28 ; +; 28 ; 20 ; +; 29 ; 17 ; +; 30 ; 18 ; +; 31 ; 10 ; +; 32 ; 16 ; ++----------------------------------------------+-------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-------------------------------+ +; Number of Signals Sourced Out (Average = 8.27) ; Number of LABs (Total = 756) ; ++-------------------------------------------------+-------------------------------+ +; 0 ; 1 ; +; 1 ; 61 ; +; 2 ; 48 ; +; 3 ; 47 ; +; 4 ; 43 ; +; 5 ; 40 ; +; 6 ; 51 ; +; 7 ; 50 ; +; 8 ; 53 ; +; 9 ; 71 ; +; 10 ; 46 ; +; 11 ; 45 ; +; 12 ; 51 ; +; 13 ; 46 ; +; 14 ; 26 ; +; 15 ; 25 ; +; 16 ; 19 ; +; 17 ; 5 ; +; 18 ; 9 ; +; 19 ; 6 ; +; 20 ; 4 ; +; 21 ; 1 ; +; 22 ; 2 ; +; 23 ; 0 ; +; 24 ; 3 ; +; 25 ; 2 ; +; 26 ; 0 ; +; 27 ; 1 ; ++-------------------------------------------------+-------------------------------+ + + ++------------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+-------------------------------+ +; Number of Distinct Inputs (Average = 18.51) ; Number of LABs (Total = 756) ; ++----------------------------------------------+-------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 22 ; +; 3 ; 24 ; +; 4 ; 30 ; +; 5 ; 15 ; +; 6 ; 15 ; +; 7 ; 23 ; +; 8 ; 16 ; +; 9 ; 20 ; +; 10 ; 17 ; +; 11 ; 19 ; +; 12 ; 16 ; +; 13 ; 20 ; +; 14 ; 18 ; +; 15 ; 17 ; +; 16 ; 19 ; +; 17 ; 34 ; +; 18 ; 26 ; +; 19 ; 19 ; +; 20 ; 27 ; +; 21 ; 33 ; +; 22 ; 35 ; +; 23 ; 33 ; +; 24 ; 33 ; +; 25 ; 30 ; +; 26 ; 30 ; +; 27 ; 21 ; +; 28 ; 15 ; +; 29 ; 16 ; +; 30 ; 26 ; +; 31 ; 28 ; +; 32 ; 29 ; +; 33 ; 25 ; +; 34 ; 4 ; ++----------------------------------------------+-------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 30 ; +; Number of I/O Rules Passed ; 17 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 13 ; ++----------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ +; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; ++--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ +; Total Pass ; 295 ; 121 ; 295 ; 0 ; 0 ; 295 ; 295 ; 0 ; 295 ; 295 ; 168 ; 3 ; 0 ; 0 ; 183 ; 168 ; 3 ; 183 ; 0 ; 0 ; 11 ; 3 ; 171 ; 0 ; 0 ; 0 ; 0 ; 295 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 0 ; 174 ; 0 ; 295 ; 295 ; 0 ; 0 ; 295 ; 0 ; 0 ; 127 ; 292 ; 295 ; 295 ; 112 ; 127 ; 292 ; 112 ; 295 ; 295 ; 284 ; 292 ; 124 ; 295 ; 295 ; 295 ; 295 ; 0 ; 295 ; 295 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CLK24M576 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_STR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_BURST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_DRQ ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_DRQ ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_MSG ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDCHG ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_DATA0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_DATA1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_DATA2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CARD_DEDECT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_WP ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDACK0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; WP_CF_CARD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_C_D ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_I_O ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_CS3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLK25M ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_ACK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_RESET ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nACSI_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_DIR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_A1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_ACK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_ATN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_DIR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MIDI_OLR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MIDI_TLR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TxD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; RTS ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DTR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; AMKB_TX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IDE_RES ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_CS0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_WR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIDE_RD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nCF_CS0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nCF_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nROM3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nROM4 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRP_UDS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRP_LDS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSDSEL ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWR_GATE ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; YM_QA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; YM_QB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; YM_QC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DSA_D ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVCAS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVRAS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nVCS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPD_VGA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TIN0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRCS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRBLE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRBHE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSRWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDREQ1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LED_FPGA_OK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSROE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VCKE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_TA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDDR_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DDR_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VSYNC_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HSYNC_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nBLANK_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PIXEL_CLK_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSYNC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nMOT_ON ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSTEP_DIR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSTEP ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLKUSB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LPDIR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; BA[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; BA[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nIRQ[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VA[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VB[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDM[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VG[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VR[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TOUT0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nMASTER ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[31] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[30] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[29] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[28] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[27] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[26] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[25] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[24] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[23] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[22] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[21] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[20] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[19] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[18] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[17] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[16] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_AD[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[31] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[30] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[29] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[28] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[27] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[26] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[25] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[24] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[23] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[22] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[21] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[20] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[19] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[18] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[17] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[16] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VD[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; VDQS[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IO[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SRD[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_PAR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_SEL ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_BUSY ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nSCSI_RST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CD_DATA3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SD_CMD_D1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; ACSI_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_D[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; SCSI_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRSTO_MCF ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_WR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_SIZE1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_SIZE0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; FB_ALE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_CS2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MAIN_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nDACK1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nFB_OE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IDE_RDY ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CLK33M ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; HD_DD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nINDEX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; RxD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nWP ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; LP_BUSY ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DCD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; CTS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; TRACK00 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; IDE_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; RI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nPCI_INTA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; DVI_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; E0_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PIC_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; PIC_AMKB_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; MIDI_IN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; nRD_DATA ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; +; AMKB_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; ++--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; On ; +; Enable device-wide output enable (DEV_OE) ; On ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Error detection CRC ; Off ; +; Enable Open Drain on CRC Error pin ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; On ; +; nCEO ; As output driving ground ; +; Data[0] ; As input tri-stated ; +; Data[1]/ASDO ; As input tri-stated ; +; Data[7..2] ; Unreserved ; +; FLASH_nCE/nCSO ; As input tri-stated ; +; Other Active Parallel pins ; Unreserved ; +; DCLK ; As input tri-stated ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +; I/O ; MAIN_CLK ; 245.886 ; +; MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 444.109 ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 1092.93 ; ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ +Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. +This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:21:57 2010 +Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +Info: Selected device EP3C40F484C6 for design "firebee1" +Info: Core supply voltage is 1.2V +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Implemented PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 1, clock division of 66, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 67, clock division of 900, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 67, clock division of 90, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] port +Info: None of the inputs fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input + Info: Input "nRD_DATA" that is fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input +Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings + Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109 + Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75 + Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port + Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port +Info: None of the inputs fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input + Info: Input "MAIN_CLK" that is fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input +Info: Implemented PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 240 degrees (5051 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 180 degrees (3788 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] port + Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 105 degrees (2210 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] port + Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 270 degrees (11364 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] port +Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port +Critical Warning: The input clock frequency specification of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is different from the output clock frequency specification of the source PLLs that are driving it + Critical Warning: Input port inclk[0] of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" and its source clk[3] (the output port of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1") have different specified frequencies, 48.0 MHz and 48.0 MHz respectively +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature. +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP3C16F484C6 is compatible + Info: Device EP3C55F484C6 is compatible + Info: Device EP3C80F484C6 is compatible +Info: Fitter converted 7 user pins into dedicated programming pins + Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 + Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 + Info: Pin ~ALTERA_DCLK~ is reserved at location K2 + Info: Pin ~ALTERA_DATA0~ is reserved at location K1 + Info: Pin ~ALTERA_DEV_OE~ is reserved at location N22 + Info: Pin ~ALTERA_DEV_CLRn~ is reserved at location N21 + Info: Pin ~ALTERA_nCEO~ is reserved at location K22 +Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Warning: The parameters of the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 and the PLL altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged + Info: The values of the parameter "M" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "M" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 67 + Info: The value of the parameter "M" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 109 + Info: The values of the parameter "N" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "N" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 6 + Info: The value of the parameter "N" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 3 + Info: The values of the parameter "LOOP FILTER R" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 12000 + Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 10000 + Info: The values of the parameter "VCO POST SCALE" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 2 + Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1 + Info: The values of the parameter "Min VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Min VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538 + Info: The value of the parameter "Min VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769 + Info: The values of the parameter "Max VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Max VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 3333 + Info: The value of the parameter "Max VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1666 + Info: The values of the parameter "Center VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Center VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538 + Info: The value of the parameter "Center VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769 + Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Min Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 17174 + Info: The value of the parameter "Min Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 27940 + Info: The values of the parameter "Max Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Max Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 30864 + Info: The value of the parameter "Max Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 59523 + Info: The values of the parameter "Compensate Clock" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 + Info: The value of the parameter "Compensate Clock" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is clock0 + Info: The value of the parameter "Compensate Clock" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is clock1 +Warning: The input ports of the PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 and the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 are mismatched, preventing the PLLs to be merged + Warning: Input clock frequency of PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 differs from input clock frequency of PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 +Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings + Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109 + Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75 + Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port + Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port + Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port + Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port +Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type + Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port +Critical Warning: Input pin "CLK33M" feeds inclk port of PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" by global clock - I/O timing will be affected +Info: Timing-driven compilation is using the Classic Timing Analyzer +Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements +Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] (placed in counter C1 of PLL_3) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14 +Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] (placed in counter C2 of PLL_3) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12 +Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] (placed in counter C3 of PLL_3) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G13 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] (placed in counter C0 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] (placed in counter C3 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] (placed in counter C2 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] (placed in counter C4 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 +Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] (placed in counter C1 of PLL_1) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] (placed in counter C1 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G16 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] (placed in counter C2 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] (placed in counter C3 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 +Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] (placed in counter C4 of PLL_4) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 +Info: Automatically promoted node altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] (placed in counter C0 of PLL_2) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8 +Info: Automatically promoted node CLK33M~input (placed in PIN AB12 (CLK12, DIFFCLK_7n)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0 + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3 + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M +Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC + Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC +Info: Automatically promoted node inst25 + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_WR~reg0 + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DTACK_OUTn + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[10] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[14] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[15] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[12] + Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[13] + Info: Non-global destination nodes limited to 10 nodes +Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO + Info: Automatically promoted destinations to use location or clock signal Global Clock +Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC +Info: Automatically promoted node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] + Info: Automatically promoted destinations to use location or clock signal Global Clock + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|_~0 + Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0 +Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 + Info: Automatically promoted destinations to use location or clock signal Global Clock +Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[31]~input" is constrained to location IOIBUF_X43_Y0_N1 to improve DDIO timing + Info: Node "VD[31]" is constrained to location PIN U12 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing + Info: Node "VD[30]~input" is constrained to location IOIBUF_X41_Y0_N29 to improve DDIO timing + Info: Node "VD[30]" is constrained to location PIN V12 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[29]~input" is constrained to location IOIBUF_X38_Y0_N22 to improve DDIO timing + Info: Node "VD[29]" is constrained to location PIN AB13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[28]~input" is constrained to location IOIBUF_X43_Y0_N29 to improve DDIO timing + Info: Node "VD[28]" is constrained to location PIN W13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "VD[27]~input" is constrained to location IOIBUF_X48_Y0_N29 to improve DDIO timing + Info: Node "VD[27]" is constrained to location PIN V13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[26]~input" is constrained to location IOIBUF_X38_Y0_N8 to improve DDIO timing + Info: Node "VD[26]" is constrained to location PIN AB14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[25]~input" is constrained to location IOIBUF_X38_Y0_N15 to improve DDIO timing + Info: Node "VD[25]" is constrained to location PIN AA14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[24]~input" is constrained to location IOIBUF_X43_Y0_N8 to improve DDIO timing + Info: Node "VD[24]" is constrained to location PIN AB15 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "VD[23]~input" is constrained to location IOIBUF_X45_Y0_N15 to improve DDIO timing + Info: Node "VD[23]" is constrained to location PIN AB16 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing + Info: Node "VD[22]~input" is constrained to location IOIBUF_X48_Y0_N22 to improve DDIO timing + Info: Node "VD[22]" is constrained to location PIN W14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "VD[21]~input" is constrained to location IOIBUF_X50_Y0_N1 to improve DDIO timing + Info: Node "VD[21]" is constrained to location PIN V15 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "VD[20]~input" is constrained to location IOIBUF_X50_Y0_N29 to improve DDIO timing + Info: Node "VD[20]" is constrained to location PIN U13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing + Info: Node "VD[19]~input" is constrained to location IOIBUF_X50_Y0_N22 to improve DDIO timing + Info: Node "VD[19]" is constrained to location PIN V14 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing + Info: Node "VD[18]~input" is constrained to location IOIBUF_X38_Y0_N29 to improve DDIO timing + Info: Node "VD[18]" is constrained to location PIN AA13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing + Info: Node "VD[17]~input" is constrained to location IOIBUF_X43_Y0_N22 to improve DDIO timing + Info: Node "VD[17]" is constrained to location PIN Y13 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing + Info: Node "VD[16]~input" is constrained to location IOIBUF_X45_Y0_N8 to improve DDIO timing + Info: Node "VD[16]" is constrained to location PIN T12 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing + Info: Node "VD[15]~input" is constrained to location IOIBUF_X67_Y15_N8 to improve DDIO timing + Info: Node "VD[15]" is constrained to location PIN N20 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "VD[14]~input" is constrained to location IOIBUF_X67_Y13_N8 to improve DDIO timing + Info: Node "VD[14]" is constrained to location PIN R22 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "VD[13]~input" is constrained to location IOIBUF_X67_Y14_N22 to improve DDIO timing + Info: Node "VD[13]" is constrained to location PIN P20 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing + Info: Node "VD[12]~input" is constrained to location IOIBUF_X67_Y17_N22 to improve DDIO timing + Info: Node "VD[12]" is constrained to location PIN N17 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing + Info: Node "VD[11]~input" is constrained to location IOIBUF_X67_Y13_N1 to improve DDIO timing + Info: Node "VD[11]" is constrained to location PIN R21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "VD[10]~input" is constrained to location IOIBUF_X67_Y10_N15 to improve DDIO timing + Info: Node "VD[10]" is constrained to location PIN P17 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "VD[9]~input" is constrained to location IOIBUF_X67_Y12_N22 to improve DDIO timing + Info: Node "VD[9]" is constrained to location PIN R18 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "VD[8]~input" is constrained to location IOIBUF_X67_Y10_N8 to improve DDIO timing + Info: Node "VD[8]" is constrained to location PIN V22 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "VD[7]~input" is constrained to location IOIBUF_X67_Y11_N1 to improve DDIO timing + Info: Node "VD[7]" is constrained to location PIN U21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing + Info: Node "VD[6]~input" is constrained to location IOIBUF_X67_Y12_N15 to improve DDIO timing + Info: Node "VD[6]" is constrained to location PIN R19 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing + Info: Node "VD[5]~input" is constrained to location IOIBUF_X67_Y10_N22 to improve DDIO timing + Info: Node "VD[5]" is constrained to location PIN R17 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "VD[4]~input" is constrained to location IOIBUF_X67_Y14_N1 to improve DDIO timing + Info: Node "VD[4]" is constrained to location PIN P21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing + Info: Node "VD[3]~input" is constrained to location IOIBUF_X67_Y11_N22 to improve DDIO timing + Info: Node "VD[3]" is constrained to location PIN R20 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing + Info: Node "VD[2]~input" is constrained to location IOIBUF_X67_Y14_N8 to improve DDIO timing + Info: Node "VD[2]" is constrained to location PIN P22 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "VD[1]~input" is constrained to location IOIBUF_X67_Y18_N1 to improve DDIO timing + Info: Node "VD[1]" is constrained to location PIN M21 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing + Info: Node "VD[0]~input" is constrained to location IOIBUF_X67_Y18_N8 to improve DDIO timing + Info: Node "VD[0]" is constrained to location PIN M22 to improve DDIO timing +Info: Starting register packing +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] to I/O pin + Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] and I/O node MAIN_CLK -- I/O node is a dedicated I/O pin +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks +Info: Finished register packing + Extra Info: Packed 33 registers into blocks of type I/O Input Buffer + Extra Info: Packed 25 registers into blocks of type I/O Output Buffer + Extra Info: Created 9 register duplicates +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input + Info: Input port INCLK[0] of node "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" is driven by CLK33M~inputclkctrl which is OUTCLK output port of Clock control block type node CLK33M~inputclkctrl +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" output port clk[2] feeds output pin "CLK24M576~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[2] feeds output pin "CLK25M~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[3] feeds output pin "CLKUSB~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[3]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[2]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "nDDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "DDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance +Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input + Info: Input port INCLK[0] of node "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is driven by altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl +Info: Starting physical synthesis optimizations for speed +Info: Starting physical synthesis algorithm combinational resynthesis using boolean division +Info: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 2208 ps +Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:23 +Info: Fitter preparation operations ending: elapsed time is 00:00:47 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:18 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:01:10 +Info: Starting physical synthesis optimizations for speed +Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:05 +Info: Estimated most critical path is register to pin delay of 5.130 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12_N0; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[9]' + Info: 2: + IC(0.161 ns) + CELL(0.369 ns) = 0.530 ns; Loc. = LAB_X16_Y12_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15' + Info: 3: + IC(0.528 ns) + CELL(0.243 ns) = 1.301 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359' + Info: 4: + IC(0.172 ns) + CELL(0.130 ns) = 1.603 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~360' + Info: 5: + IC(1.521 ns) + CELL(2.006 ns) = 5.130 ns; Loc. = IOOBUF_X34_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[29]~output' + Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 5.130 ns; Loc. = PIN_W10; Fanout = 0; PIN Node = 'FB_AD[29]' + Info: Total cell delay = 2.748 ns ( 53.57 % ) + Info: Total interconnect delay = 2.382 ns ( 46.43 % ) +Info: Fitter routing operations beginning +Info: 2 (of 32134) connections in the design require a large routing delay to satisfy hold requirements. Refer to the Fitter report for a summary of the relevant clock transfers. Also, check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks. +Info: Average interconnect usage is 13% of the available device resources + Info: Peak interconnect usage is 51% of the available device resources in the region that extends from location X22_Y11 to location X33_Y21 +Info: Fitter routing operations ending: elapsed time is 00:01:18 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped +Info: Started post-fitting delay annotation +Info: Delay annotation completed successfully +Info: Auto delay chain can't change the delay chain setting on I/O pin nRD_DATA since it's a PLL compensated pin +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register +Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. +Warning: Total number of single-ended output or bi-directional pins in bank 4 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition. + Info: There are 32 output pin(s) with I/O standard 2.5 V and current strength 12mA + Info: Location AA13 (pad PAD_208): Pin VD[18] of type bi-directional uses 2.5 V I/O standard + Info: Location AB13 (pad PAD_209): Pin VD[29] of type bi-directional uses 2.5 V I/O standard + Info: Location AA14 (pad PAD_210): Pin VD[25] of type bi-directional uses 2.5 V I/O standard + Info: Location AB14 (pad PAD_211): Pin VD[26] of type bi-directional uses 2.5 V I/O standard + Info: Location V12 (pad PAD_213): Pin VD[30] of type bi-directional uses 2.5 V I/O standard + Info: Location W13 (pad PAD_218): Pin VD[28] of type bi-directional uses 2.5 V I/O standard + Info: Location Y13 (pad PAD_219): Pin VD[17] of type bi-directional uses 2.5 V I/O standard + Info: Location AA15 (pad PAD_220): Pin VDQS[0] of type bi-directional uses 2.5 V I/O standard + Info: Location AB15 (pad PAD_221): Pin VD[24] of type bi-directional uses 2.5 V I/O standard + Info: Location U12 (pad PAD_222): Pin VD[31] of type bi-directional uses 2.5 V I/O standard + Info: Location AA16 (pad PAD_224): Pin VDM[0] of type output uses 2.5 V I/O standard + Info: Location AB16 (pad PAD_225): Pin VD[23] of type bi-directional uses 2.5 V I/O standard + Info: Location T12 (pad PAD_226): Pin VD[16] of type bi-directional uses 2.5 V I/O standard + Info: Location V13 (pad PAD_228): Pin VD[27] of type bi-directional uses 2.5 V I/O standard + Info: Location W14 (pad PAD_229): Pin VD[22] of type bi-directional uses 2.5 V I/O standard + Info: Location U13 (pad PAD_233): Pin VD[20] of type bi-directional uses 2.5 V I/O standard + Info: Location V14 (pad PAD_234): Pin VD[19] of type bi-directional uses 2.5 V I/O standard + Info: Location U15 (pad PAD_236): Pin VCKE of type output uses 2.5 V I/O standard + Info: Location V15 (pad PAD_237): Pin VD[21] of type bi-directional uses 2.5 V I/O standard + Info: Location W15 (pad PAD_239): Pin VDQS[1] of type bi-directional uses 2.5 V I/O standard + Info: Location AB18 (pad PAD_242): Pin nVCAS of type output uses 2.5 V I/O standard + Info: Location AA17 (pad PAD_243): Pin nDDR_CLK of type output uses 2.5 V I/O standard + Info: Location AB17 (pad PAD_244): Pin DDR_CLK of type output uses 2.5 V I/O standard + Info: Location AA18 (pad PAD_245): Pin VA[12] of type output uses 2.5 V I/O standard + Info: Location AA19 (pad PAD_252): Pin BA[1] of type output uses 2.5 V I/O standard + Info: Location AB19 (pad PAD_253): Pin VA[9] of type output uses 2.5 V I/O standard + Info: Location W17 (pad PAD_257): Pin nVRAS of type output uses 2.5 V I/O standard + Info: Location Y17 (pad PAD_258): Pin nVWE of type output uses 2.5 V I/O standard + Info: Location AA20 (pad PAD_259): Pin VA[7] of type output uses 2.5 V I/O standard + Info: Location AB20 (pad PAD_260): Pin VA[8] of type output uses 2.5 V I/O standard + Info: Location V16 (pad PAD_261): Pin VDM[1] of type output uses 2.5 V I/O standard + Info: Location T16 (pad PAD_266): Pin VDQS[3] of type bi-directional uses 2.5 V I/O standard +Warning: Total number of single-ended output or bi-directional pins in bank 5 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition. + Info: There are 30 output pin(s) with I/O standard 2.5 V and current strength 12mA + Info: Location AA22 (pad PAD_273): Pin VA[4] of type output uses 2.5 V I/O standard + Info: Location AA21 (pad PAD_274): Pin VA[6] of type output uses 2.5 V I/O standard + Info: Location T17 (pad PAD_277): Pin VDM[3] of type output uses 2.5 V I/O standard + Info: Location T18 (pad PAD_278): Pin nVCS of type output uses 2.5 V I/O standard + Info: Location W20 (pad PAD_280): Pin VA[0] of type output uses 2.5 V I/O standard + Info: Location W19 (pad PAD_285): Pin BA[0] of type output uses 2.5 V I/O standard + Info: Location Y22 (pad PAD_288): Pin VA[3] of type output uses 2.5 V I/O standard + Info: Location Y21 (pad PAD_289): Pin VA[5] of type output uses 2.5 V I/O standard + Info: Location U20 (pad PAD_290): Pin VDM[2] of type output uses 2.5 V I/O standard + Info: Location U19 (pad PAD_291): Pin VA[11] of type output uses 2.5 V I/O standard + Info: Location W22 (pad PAD_292): Pin VA[1] of type output uses 2.5 V I/O standard + Info: Location W21 (pad PAD_293): Pin VA[2] of type output uses 2.5 V I/O standard + Info: Location R17 (pad PAD_301): Pin VD[5] of type bi-directional uses 2.5 V I/O standard + Info: Location P17 (pad PAD_302): Pin VD[10] of type bi-directional uses 2.5 V I/O standard + Info: Location V22 (pad PAD_303): Pin VD[8] of type bi-directional uses 2.5 V I/O standard + Info: Location V21 (pad PAD_304): Pin VA[10] of type output uses 2.5 V I/O standard + Info: Location R20 (pad PAD_305): Pin VD[3] of type bi-directional uses 2.5 V I/O standard + Info: Location U22 (pad PAD_307): Pin VDQS[2] of type bi-directional uses 2.5 V I/O standard + Info: Location U21 (pad PAD_308): Pin VD[7] of type bi-directional uses 2.5 V I/O standard + Info: Location R18 (pad PAD_309): Pin VD[9] of type bi-directional uses 2.5 V I/O standard + Info: Location R19 (pad PAD_310): Pin VD[6] of type bi-directional uses 2.5 V I/O standard + Info: Location R22 (pad PAD_315): Pin VD[14] of type bi-directional uses 2.5 V I/O standard + Info: Location R21 (pad PAD_316): Pin VD[11] of type bi-directional uses 2.5 V I/O standard + Info: Location P20 (pad PAD_317): Pin VD[13] of type bi-directional uses 2.5 V I/O standard + Info: Location P22 (pad PAD_319): Pin VD[2] of type bi-directional uses 2.5 V I/O standard + Info: Location P21 (pad PAD_320): Pin VD[4] of type bi-directional uses 2.5 V I/O standard + Info: Location N20 (pad PAD_323): Pin VD[15] of type bi-directional uses 2.5 V I/O standard + Info: Location N17 (pad PAD_329): Pin VD[12] of type bi-directional uses 2.5 V I/O standard + Info: Location M22 (pad PAD_333): Pin VD[0] of type bi-directional uses 2.5 V I/O standard + Info: Location M21 (pad PAD_334): Pin VD[1] of type bi-directional uses 2.5 V I/O standard +Warning: 145 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems). + Info: Pin nFB_BURST uses I/O standard 3.3-V LVTTL at T3 + Info: Pin nACSI_DRQ uses I/O standard 3.3-V LVTTL at K7 + Info: Pin nACSI_INT uses I/O standard 3.3-V LVTTL at J4 + Info: Pin nSCSI_DRQ uses I/O standard 3.3-V LVTTL at U1 + Info: Pin nSCSI_MSG uses I/O standard 3.3-V LVTTL at H2 + Info: Pin nDCHG uses I/O standard 3.3-V LVTTL at C17 + Info: Pin SD_DATA0 uses I/O standard 3.3-V LVTTL at B16 + Info: Pin SD_DATA1 uses I/O standard 3.3-V LVTTL at A16 + Info: Pin SD_DATA2 uses I/O standard 3.3-V LVTTL at B17 + Info: Pin SD_CARD_DEDECT uses I/O standard 3.3-V LVTTL at M20 + Info: Pin SD_WP uses I/O standard 3.3-V LVTTL at M19 + Info: Pin nDACK0 uses I/O standard 3.3-V LVTTL at B12 + Info: Pin WP_CF_CARD uses I/O standard 3.3-V LVTTL at T1 + Info: Pin nSCSI_C_D uses I/O standard 3.3-V LVTTL at H1 + Info: Pin nSCSI_I_O uses I/O standard 3.3-V LVTTL at J3 + Info: Pin nFB_CS3 uses I/O standard 3.3-V LVTTL at V6 + Info: Pin TOUT0 uses I/O standard 3.3-V LVTTL at T22 + Info: Pin nMASTER uses I/O standard 3.3-V LVTTL at T21 + Info: Pin FB_AD[31] uses I/O standard 3.3-V LVTTL at AA10 + Info: Pin FB_AD[30] uses I/O standard 3.3-V LVTTL at Y10 + Info: Pin FB_AD[29] uses I/O standard 3.3-V LVTTL at W10 + Info: Pin FB_AD[28] uses I/O standard 3.3-V LVTTL at V11 + Info: Pin FB_AD[27] uses I/O standard 3.3-V LVTTL at U11 + Info: Pin FB_AD[26] uses I/O standard 3.3-V LVTTL at AB9 + Info: Pin FB_AD[25] uses I/O standard 3.3-V LVTTL at AA9 + Info: Pin FB_AD[24] uses I/O standard 3.3-V LVTTL at T11 + Info: Pin FB_AD[23] uses I/O standard 3.3-V LVTTL at AB8 + Info: Pin FB_AD[22] uses I/O standard 3.3-V LVTTL at AA8 + Info: Pin FB_AD[21] uses I/O standard 3.3-V LVTTL at U10 + Info: Pin FB_AD[20] uses I/O standard 3.3-V LVTTL at T10 + Info: Pin FB_AD[19] uses I/O standard 3.3-V LVTTL at V10 + Info: Pin FB_AD[18] uses I/O standard 3.3-V LVTTL at V9 + Info: Pin FB_AD[17] uses I/O standard 3.3-V LVTTL at Y8 + Info: Pin FB_AD[16] uses I/O standard 3.3-V LVTTL at AB7 + Info: Pin FB_AD[15] uses I/O standard 3.3-V LVTTL at AA7 + Info: Pin FB_AD[14] uses I/O standard 3.3-V LVTTL at W8 + Info: Pin FB_AD[13] uses I/O standard 3.3-V LVTTL at V8 + Info: Pin FB_AD[12] uses I/O standard 3.3-V LVTTL at U9 + Info: Pin FB_AD[11] uses I/O standard 3.3-V LVTTL at Y7 + Info: Pin FB_AD[10] uses I/O standard 3.3-V LVTTL at W7 + Info: Pin FB_AD[9] uses I/O standard 3.3-V LVTTL at AB5 + Info: Pin FB_AD[8] uses I/O standard 3.3-V LVTTL at AA5 + Info: Pin FB_AD[7] uses I/O standard 3.3-V LVTTL at AB4 + Info: Pin FB_AD[6] uses I/O standard 3.3-V LVTTL at AA4 + Info: Pin FB_AD[5] uses I/O standard 3.3-V LVTTL at V7 + Info: Pin FB_AD[4] uses I/O standard 3.3-V LVTTL at W6 + Info: Pin FB_AD[3] uses I/O standard 3.3-V LVTTL at AB3 + Info: Pin FB_AD[2] uses I/O standard 3.3-V LVTTL at AA3 + Info: Pin FB_AD[1] uses I/O standard 3.3-V LVTTL at Y6 + Info: Pin FB_AD[0] uses I/O standard 3.3-V LVTTL at Y3 + Info: Pin IO[17] uses I/O standard 3.3-V LVTTL at B13 + Info: Pin IO[16] uses I/O standard 3.3-V LVTTL at A13 + Info: Pin IO[15] uses I/O standard 3.3-V LVTTL at B14 + Info: Pin IO[14] uses I/O standard 3.3-V LVTTL at A14 + Info: Pin IO[13] uses I/O standard 3.3-V LVTTL at E13 + Info: Pin IO[12] uses I/O standard 3.3-V LVTTL at D13 + Info: Pin IO[11] uses I/O standard 3.3-V LVTTL at C13 + Info: Pin IO[10] uses I/O standard 3.3-V LVTTL at B15 + Info: Pin IO[9] uses I/O standard 3.3-V LVTTL at A15 + Info: Pin IO[8] uses I/O standard 3.3-V LVTTL at G10 + Info: Pin IO[7] uses I/O standard 3.3-V LVTTL at C7 + Info: Pin IO[6] uses I/O standard 3.3-V LVTTL at C8 + Info: Pin IO[5] uses I/O standard 3.3-V LVTTL at E9 + Info: Pin IO[4] uses I/O standard 3.3-V LVTTL at B6 + Info: Pin IO[3] uses I/O standard 3.3-V LVTTL at A6 + Info: Pin IO[2] uses I/O standard 3.3-V LVTTL at B7 + Info: Pin IO[1] uses I/O standard 3.3-V LVTTL at A7 + Info: Pin IO[0] uses I/O standard 3.3-V LVTTL at A8 + Info: Pin SRD[15] uses I/O standard 3.3-V LVTTL at H10 + Info: Pin SRD[14] uses I/O standard 3.3-V LVTTL at G9 + Info: Pin SRD[13] uses I/O standard 3.3-V LVTTL at F10 + Info: Pin SRD[12] uses I/O standard 3.3-V LVTTL at D10 + Info: Pin SRD[11] uses I/O standard 3.3-V LVTTL at B10 + Info: Pin SRD[10] uses I/O standard 3.3-V LVTTL at A9 + Info: Pin SRD[9] uses I/O standard 3.3-V LVTTL at A10 + Info: Pin SRD[8] uses I/O standard 3.3-V LVTTL at B9 + Info: Pin SRD[7] uses I/O standard 3.3-V LVTTL at H11 + Info: Pin SRD[6] uses I/O standard 3.3-V LVTTL at E10 + Info: Pin SRD[5] uses I/O standard 3.3-V LVTTL at F9 + Info: Pin SRD[4] uses I/O standard 3.3-V LVTTL at C10 + Info: Pin SRD[3] uses I/O standard 3.3-V LVTTL at G11 + Info: Pin SRD[2] uses I/O standard 3.3-V LVTTL at C6 + Info: Pin SRD[1] uses I/O standard 3.3-V LVTTL at A5 + Info: Pin SRD[0] uses I/O standard 3.3-V LVTTL at B5 + Info: Pin SCSI_PAR uses I/O standard 3.3-V LVTTL at M7 + Info: Pin nSCSI_SEL uses I/O standard 3.3-V LVTTL at M8 + Info: Pin nSCSI_BUSY uses I/O standard 3.3-V LVTTL at N8 + Info: Pin nSCSI_RST uses I/O standard 3.3-V LVTTL at N6 + Info: Pin SD_CD_DATA3 uses I/O standard 3.3-V LVTTL at F13 + Info: Pin SD_CMD_D1 uses I/O standard 3.3-V LVTTL at E14 + Info: Pin ACSI_D[7] uses I/O standard 3.3-V LVTTL at H6 + Info: Pin ACSI_D[6] uses I/O standard 3.3-V LVTTL at H7 + Info: Pin ACSI_D[5] uses I/O standard 3.3-V LVTTL at D2 + Info: Pin ACSI_D[4] uses I/O standard 3.3-V LVTTL at C1 + Info: Pin ACSI_D[3] uses I/O standard 3.3-V LVTTL at C2 + Info: Pin ACSI_D[2] uses I/O standard 3.3-V LVTTL at E3 + Info: Pin ACSI_D[1] uses I/O standard 3.3-V LVTTL at G5 + Info: Pin ACSI_D[0] uses I/O standard 3.3-V LVTTL at B1 + Info: Pin LP_D[7] uses I/O standard 3.3-V LVTTL at G8 + Info: Pin LP_D[6] uses I/O standard 3.3-V LVTTL at A3 + Info: Pin LP_D[5] uses I/O standard 3.3-V LVTTL at B3 + Info: Pin LP_D[4] uses I/O standard 3.3-V LVTTL at D6 + Info: Pin LP_D[3] uses I/O standard 3.3-V LVTTL at E7 + Info: Pin LP_D[2] uses I/O standard 3.3-V LVTTL at C3 + Info: Pin LP_D[1] uses I/O standard 3.3-V LVTTL at C4 + Info: Pin LP_D[0] uses I/O standard 3.3-V LVTTL at F7 + Info: Pin SCSI_D[7] uses I/O standard 3.3-V LVTTL at K8 + Info: Pin SCSI_D[6] uses I/O standard 3.3-V LVTTL at L8 + Info: Pin SCSI_D[5] uses I/O standard 3.3-V LVTTL at G3 + Info: Pin SCSI_D[4] uses I/O standard 3.3-V LVTTL at G4 + Info: Pin SCSI_D[3] uses I/O standard 3.3-V LVTTL at F1 + Info: Pin SCSI_D[2] uses I/O standard 3.3-V LVTTL at F2 + Info: Pin SCSI_D[1] uses I/O standard 3.3-V LVTTL at E1 + Info: Pin SCSI_D[0] uses I/O standard 3.3-V LVTTL at J6 + Info: Pin nRSTO_MCF uses I/O standard 3.3-V LVTTL at B11 + Info: Pin nFB_WR uses I/O standard 3.3-V LVTTL at T5 + Info: Pin nFB_CS1 uses I/O standard 3.3-V LVTTL at T8 + Info: Pin FB_SIZE1 uses I/O standard 3.3-V LVTTL at Y4 + Info: Pin FB_SIZE0 uses I/O standard 3.3-V LVTTL at U8 + Info: Pin FB_ALE uses I/O standard 3.3-V LVTTL at R7 + Info: Pin nFB_CS2 uses I/O standard 3.3-V LVTTL at T9 + Info: Pin MAIN_CLK uses I/O standard 3.3-V LVTTL at G2 + Info: Pin nDACK1 uses I/O standard 3.3-V LVTTL at A12 + Info: Pin nFB_OE uses I/O standard 3.3-V LVTTL at R6 + Info: Pin IDE_RDY uses I/O standard 3.3-V LVTTL at Y1 + Info: Pin CLK33M uses I/O standard 3.3-V LVTTL at AB12 + Info: Pin HD_DD uses I/O standard 3.3-V LVTTL at F16 + Info: Pin nINDEX uses I/O standard 3.3-V LVTTL at E16 + Info: Pin RxD uses I/O standard 3.3-V LVTTL at H15 + Info: Pin nWP uses I/O standard 3.3-V LVTTL at D19 + Info: Pin LP_BUSY uses I/O standard 3.3-V LVTTL at G7 + Info: Pin DCD uses I/O standard 3.3-V LVTTL at A19 + Info: Pin CTS uses I/O standard 3.3-V LVTTL at H14 + Info: Pin TRACK00 uses I/O standard 3.3-V LVTTL at C19 + Info: Pin RI uses I/O standard 3.3-V LVTTL at B19 + Info: Pin nPCI_INTD uses I/O standard 3.3-V LVTTL at P6 + Info: Pin nPCI_INTC uses I/O standard 3.3-V LVTTL at V3 + Info: Pin nPCI_INTB uses I/O standard 3.3-V LVTTL at V4 + Info: Pin nPCI_INTA uses I/O standard 3.3-V LVTTL at AA1 + Info: Pin DVI_INT uses I/O standard 3.3-V LVTTL at A11 + Info: Pin PIC_INT uses I/O standard 3.3-V LVTTL at AA2 + Info: Pin PIC_AMKB_RX uses I/O standard 3.3-V LVTTL at L7 + Info: Pin MIDI_IN uses I/O standard 3.3-V LVTTL at E12 + Info: Pin nRD_DATA uses I/O standard 3.3-V LVTTL at A20 + Info: Pin AMKB_RX uses I/O standard 3.3-V LVTTL at Y2 +Warning: Following 40 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results + Info: Pin IO[17] has a permanently enabled output enable + Info: Pin IO[16] has a permanently enabled output enable + Info: Pin IO[15] has a permanently enabled output enable + Info: Pin IO[14] has a permanently enabled output enable + Info: Pin IO[13] has a permanently enabled output enable + Info: Pin IO[12] has a permanently enabled output enable + Info: Pin IO[11] has a permanently enabled output enable + Info: Pin IO[10] has a permanently enabled output enable + Info: Pin IO[9] has a permanently enabled output enable + Info: Pin IO[8] has a permanently enabled output enable + Info: Pin IO[7] has a permanently enabled output enable + Info: Pin IO[6] has a permanently enabled output enable + Info: Pin IO[5] has a permanently enabled output enable + Info: Pin IO[4] has a permanently enabled output enable + Info: Pin IO[3] has a permanently enabled output enable + Info: Pin IO[2] has a permanently enabled output enable + Info: Pin IO[1] has a permanently enabled output enable + Info: Pin IO[0] has a permanently enabled output enable + Info: Pin SCSI_PAR has a permanently disabled output enable + Info: Pin nSCSI_SEL has a permanently enabled output enable + Info: Pin nSCSI_BUSY has a permanently enabled output enable + Info: Pin nSCSI_RST has a permanently disabled output enable + Info: Pin SD_CD_DATA3 has a permanently disabled output enable + Info: Pin SD_CMD_D1 has a permanently disabled output enable + Info: Pin ACSI_D[7] has a permanently disabled output enable + Info: Pin ACSI_D[6] has a permanently disabled output enable + Info: Pin ACSI_D[5] has a permanently disabled output enable + Info: Pin ACSI_D[4] has a permanently disabled output enable + Info: Pin ACSI_D[3] has a permanently disabled output enable + Info: Pin ACSI_D[2] has a permanently disabled output enable + Info: Pin ACSI_D[1] has a permanently disabled output enable + Info: Pin ACSI_D[0] has a permanently disabled output enable + Info: Pin SCSI_D[7] has a permanently disabled output enable + Info: Pin SCSI_D[6] has a permanently disabled output enable + Info: Pin SCSI_D[5] has a permanently disabled output enable + Info: Pin SCSI_D[4] has a permanently disabled output enable + Info: Pin SCSI_D[3] has a permanently disabled output enable + Info: Pin SCSI_D[2] has a permanently disabled output enable + Info: Pin SCSI_D[1] has a permanently disabled output enable + Info: Pin SCSI_D[0] has a permanently disabled output enable +Info: Quartus II Fitter was successful. 0 errors, 34 warnings + Info: Peak virtual memory: 334 megabytes + Info: Processing ended: Wed Dec 15 02:25:07 2010 + Info: Elapsed time: 00:03:10 + Info: Total CPU time (on all processors): 00:03:11 + + diff --git a/FPGA_Quartus_13.1/firebee1.fit.summary b/FPGA_Quartus_13.1/firebee1.fit.summary new file mode 100644 index 0000000..f177099 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Wed Dec 15 02:25:02 2010 +Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +Revision Name : firebee1 +Top-level Entity Name : firebee1 +Family : Cyclone III +Device : EP3C40F484C6 +Timing Models : Final +Total logic elements : 9,526 / 39,600 ( 24 % ) + Total combinational functions : 8,061 / 39,600 ( 20 % ) + Dedicated logic registers : 4,563 / 39,600 ( 12 % ) +Total registers : 4749 +Total pins : 295 / 332 ( 89 % ) +Total virtual pins : 0 +Total memory bits : 109,344 / 1,161,216 ( 9 % ) +Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % ) +Total PLLs : 4 / 4 ( 100 % ) diff --git a/FPGA_Quartus_13.1/firebee1.flow.rpt b/FPGA_Quartus_13.1/firebee1.flow.rpt new file mode 100644 index 0000000..297d7a0 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.flow.rpt @@ -0,0 +1,380 @@ +Flow report for firebee1 +Wed Dec 15 02:25:22 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+----------------------------------------------+ +; Flow Status ; Successful - Wed Dec 15 02:25:21 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Device ; EP3C40F484C6 ; +; Timing Models ; Final ; +; Met timing requirements ; No ; +; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; +; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ; +; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; +; Total registers ; 4749 ; +; Total pins ; 295 / 332 ( 89 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ; +; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; +; Total PLLs ; 4 / 4 ( 100 % ) ; ++------------------------------------+----------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 12/15/2010 02:20:37 ; +; Main task ; Compilation ; +; Revision Name ; firebee1 ; ++-------------------+---------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-----------------------------------------+------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-----------------------------------------+------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 150661768621.129237603704664 ; -- ; -- ; -- ; +; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ; +; FMAX_REQUIREMENT ; 30 ns ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_LATCH ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_COMPARE ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_BIDIR ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL_RECONFIG ; -- ; -- ; -- ; +; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; MISC_FILE ; C:/firebee/FPGA/firebee1.dpf ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll1.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll2.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll3.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll0.ppf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_counter0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_counter0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux2.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram2.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altdpram2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_bustri6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_latch1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_latch1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant4.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_constant4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_compare1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_compare1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_compare1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_LONG.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_LONG.inc ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_LONG.cmp ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_BYT.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_BYT.inc ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_BYT.cmp ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_WORD.bsf ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_WORD.inc ; -- ; -- ; -- ; +; MISC_FILE ; lpm_bustri_WORD.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff4.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff5.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff5.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff5.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff6.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_ff6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg3.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_bidir0.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out0.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux5.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux5.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux5.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg5.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg5.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg5.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg6.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg4.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_shiftreg4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out1.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/altddio_out2.ppf ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.inc ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altddio_out3.ppf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux6.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux6.inc ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_mux6.cmp ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxDZ.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxDZ.cmp ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxVDM.bsf ; -- ; -- ; -- ; +; MISC_FILE ; Video/lpm_muxVDM.cmp ; -- ; -- ; -- ; +; MISC_FILE ; C:/FireBee/FPGA/firebee1.dpf ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.tdf ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll_reconfig1.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.tdf ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.bsf ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.inc ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.cmp ; -- ; -- ; -- ; +; MISC_FILE ; altpll4.ppf ; -- ; -- ; -- ; +; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ; +; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ; +; PHYSICAL_SYNTHESIS_EFFORT ; Fast ; Normal ; -- ; -- ; +; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ; +; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ; +; TCO_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; TH_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; TPD_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; TSU_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; +; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; +; USE_TIMEQUEST_TIMING_ANALYZER ; Off ; On ; -- ; -- ; ++-----------------------------------------+------------------------------------+---------------+-------------+----------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:01:16 ; 1.0 ; 347 MB ; 00:01:17 ; +; Fitter ; 00:03:05 ; 1.0 ; 334 MB ; 00:03:07 ; +; Assembler ; 00:00:05 ; 1.0 ; 291 MB ; 00:00:04 ; +; Classic Timing Analyzer ; 00:00:07 ; 1.0 ; 227 MB ; 00:00:09 ; +; Total ; 00:04:33 ; -- ; -- ; 00:04:37 ; ++-------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++-------------------------+------------------+---------------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++-------------------------+------------------+---------------+------------+----------------+ +; Analysis & Synthesis ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; +; Fitter ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; +; Assembler ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; +; Classic Timing Analyzer ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; ++-------------------------+------------------+---------------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 +quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 +quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only + + + diff --git a/FPGA_Quartus_13.1/firebee1.map.rpt b/FPGA_Quartus_13.1/firebee1.map.rpt new file mode 100644 index 0000000..11a1ac1 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.map.rpt @@ -0,0 +1,8590 @@ +Analysis & Synthesis report for firebee1 +Wed Dec 15 02:21:56 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis RAM Summary + 9. Analysis & Synthesis DSP Block Usage Summary + 10. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR + 11. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM + 12. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE + 13. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE + 14. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE + 15. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE + 16. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE + 17. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE + 18. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE + 19. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE + 20. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE + 21. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE + 22. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE + 23. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP + 24. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE + 25. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE + 26. Registers Protected by Synthesis + 27. User-Specified and Inferred Latches + 28. Registers Removed During Synthesis + 29. Removed Registers Triggering Further Register Optimizations + 30. General Register Statistics + 31. Inverted Register Statistics + 32. Multiplexer Restructuring Statistics (Restructuring Performed) + 33. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated + 34. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p + 35. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p + 36. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram + 37. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp + 38. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 + 39. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp + 40. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp + 41. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp + 42. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 + 43. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated + 44. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p + 45. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p + 46. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram + 47. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp + 48. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp + 49. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp + 50. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 + 51. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp + 52. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 + 53. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component + 54. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated + 55. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p + 56. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p + 57. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp + 58. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram + 59. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp + 60. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 + 61. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr + 62. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp + 63. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp + 64. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp + 65. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 + 66. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component + 67. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated + 68. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated + 69. Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram + 70. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated + 71. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated + 72. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated + 73. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated + 74. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated + 75. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated + 76. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated + 77. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated + 78. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component + 79. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated + 80. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component + 81. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated + 82. Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated + 83. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component + 84. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated + 85. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 + 86. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 + 87. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 + 88. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 + 89. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 + 90. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 + 91. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 + 92. Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component + 93. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component + 94. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated + 95. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component + 96. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated + 97. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component + 98. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated + 99. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component +100. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated +101. Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component +102. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component +103. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component +104. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL +105. Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component +106. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component +107. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component +108. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component +109. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component +110. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component +111. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component +112. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component +113. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component +114. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component +115. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component +116. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component +117. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component +118. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component +119. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component +120. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component +121. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component +122. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component +123. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component +124. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component +125. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component +126. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component +127. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component +128. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component +129. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component +130. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component +131. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component +132. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component +133. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component +134. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component +135. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component +136. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component +137. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component +138. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component +139. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component +140. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component +141. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component +142. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component +143. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component +144. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component +145. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component +146. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component +147. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component +148. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component +149. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component +150. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component +151. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component +152. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component +153. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component +154. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component +155. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component +156. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component +157. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component +158. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component +159. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component +160. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component +161. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component +162. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component +163. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component +164. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component +165. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component +166. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component +167. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component +168. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component +169. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component +170. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component +171. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component +172. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component +173. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component +174. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component +175. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component +176. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component +177. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component +178. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component +179. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component +180. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component +181. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component +182. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component +183. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component +184. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component +185. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component +186. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component +187. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component +188. Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component +189. Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component +190. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component +191. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 +192. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 +193. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 +194. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 +195. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 +196. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 +197. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 +198. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 +199. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 +200. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 +201. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 +202. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 +203. Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component +204. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component +205. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component +206. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component +207. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component +208. Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component +209. Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component +210. Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component +211. Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component +212. Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component +213. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 +214. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 +215. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 +216. altpll Parameter Settings by Entity Instance +217. lpm_shiftreg Parameter Settings by Entity Instance +218. dcfifo Parameter Settings by Entity Instance +219. scfifo Parameter Settings by Entity Instance +220. altsyncram Parameter Settings by Entity Instance +221. lpm_mult Parameter Settings by Entity Instance +222. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" +223. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" +224. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" +225. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" +226. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" +227. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" +228. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" +229. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Dec 15 02:21:55 2010 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; firebee1 ; +; Top-level Entity Name ; firebee1 ; +; Family ; Cyclone III ; +; Total logic elements ; 10,706 ; +; Total combinational functions ; 8,060 ; +; Dedicated logic registers ; 4,612 ; +; Total registers ; 4740 ; +; Total pins ; 295 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 109,344 ; +; Embedded Multiplier 9-bit elements ; 6 ; +; Total PLLs ; 4 ; ++------------------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP3C40F484C6 ; ; +; Top-level entity name ; firebee1 ; firebee1 ; +; Family name ; Cyclone III ; Stratix II ; +; State Machine Processing ; One-Hot ; Auto ; +; Optimization Technique ; Speed ; Balanced ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; On ; On ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd ; +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd ; +; FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd ; +; FalconIO_SDCard_IDE_CF/dcfifo0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo0.vhd ; +; Video/DDR_CTR.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Video/DDR_CTR.tdf ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd ; +; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd ; +; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd ; +; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd ; +; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd ; +; lpm_latch0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_latch0.vhd ; +; altpll1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll1.vhd ; +; Video/lpm_fifoDZ.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_fifoDZ.vhd ; +; altpll2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll2.vhd ; +; altpll3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll3.vhd ; +; Video/altdpram0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram0.vhd ; +; Video/lpm_muxDZ.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_muxDZ.vhd ; +; Video/lpm_bustri3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_bustri3.vhd ; +; Video/lpm_ff0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff0.vhd ; +; Video/lpm_ff1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff1.vhd ; +; Video/lpm_ff3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff3.vhd ; +; Video/VIDEO_MOD_MUX_CLUTCTR.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Video/VIDEO_MOD_MUX_CLUTCTR.tdf ; +; Video/lpm_fifo_dc0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_fifo_dc0.vhd ; +; Video/Video.bdf ; yes ; User Block Diagram/Schematic File ; C:/FireBee/FPGA/Video/Video.bdf ; +; firebee1.bdf ; yes ; User Block Diagram/Schematic File ; C:/FireBee/FPGA/firebee1.bdf ; +; lpm_counter0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_counter0.vhd ; +; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd ; +; DSP/DSP.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/DSP/DSP.vhd ; +; Video/lpm_shiftreg0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg0.vhd ; +; Video/lpm_bustri1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_bustri1.vhd ; +; Video/altdpram1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram1.vhd ; +; Video/lpm_constant0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant0.vhd ; +; Video/lpm_constant1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant1.vhd ; +; Video/lpm_mux0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux0.vhd ; +; Video/lpm_mux1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux1.vhd ; +; Video/lpm_mux2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux2.vhd ; +; Video/lpm_constant2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant2.vhd ; +; Video/altdpram2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram2.vhd ; +; Video/lpm_mux3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux3.vhd ; +; Video/lpm_mux4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux4.vhd ; +; Video/lpm_constant3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant3.vhd ; +; Interrupt_Handler/interrupt_handler.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Interrupt_Handler/interrupt_handler.tdf ; +; lpm_bustri_LONG.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_LONG.vhd ; +; lpm_bustri_BYT.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_BYT.vhd ; +; lpm_bustri_WORD.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_WORD.vhd ; +; Video/lpm_ff4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff4.vhd ; +; Video/lpm_ff5.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff5.vhd ; +; Video/lpm_ff6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff6.vhd ; +; Video/altddio_bidir0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_bidir0.vhd ; +; Video/altddio_out0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_out0.vhd ; +; Video/lpm_mux5.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux5.vhd ; +; Video/BLITTER/BLITTER.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/Video/BLITTER/BLITTER.vhd ; +; Video/lpm_shiftreg6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg6.vhd ; +; Video/lpm_shiftreg4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg4.vhd ; +; Video/altddio_out2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_out2.vhd ; +; altddio_out3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altddio_out3.vhd ; +; Video/lpm_mux6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux6.vhd ; +; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd ; +; FalconIO_SDCard_IDE_CF/dcfifo1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo1.vhd ; +; Video/lpm_muxVDM.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_muxVDM.vhd ; +; lpm_bustri_byt.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_byt.inc ; +; lpm_bustri_word.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_word.inc ; +; lpm_bustri_long.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_long.inc ; +; altpll.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.tdf ; +; db/altpll_pul2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_pul2.tdf ; +; dcfifo_mixed_widths.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf ; +; db/dcfifo_0hh1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_0hh1.tdf ; +; db/a_gray2bin_lfb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_gray2bin_lfb.tdf ; +; db/a_graycounter_k47.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_k47.tdf ; +; db/a_graycounter_fic.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_fic.tdf ; +; db/altsyncram_bi31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_bi31.tdf ; +; db/alt_synch_pipe_ikd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_ikd.tdf ; +; db/dffpipe_hd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_hd9.tdf ; +; db/dffpipe_gd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_gd9.tdf ; +; db/dffpipe_pe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_pe9.tdf ; +; db/alt_synch_pipe_jkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_jkd.tdf ; +; db/dffpipe_id9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_id9.tdf ; +; db/cmpr_256.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_256.tdf ; +; db/cmpr_156.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_156.tdf ; +; db/cntr_t2e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_t2e.tdf ; +; db/mux_a18.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_a18.tdf ; +; db/dcfifo_3fh1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_3fh1.tdf ; +; db/a_graycounter_j47.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_j47.tdf ; +; db/a_graycounter_gic.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_gic.tdf ; +; db/altsyncram_ci31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_ci31.tdf ; +; db/alt_synch_pipe_kkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_kkd.tdf ; +; db/dffpipe_jd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_jd9.tdf ; +; db/alt_synch_pipe_lkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_lkd.tdf ; +; db/dffpipe_kd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_kd9.tdf ; +; db/altpll_41p2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_41p2.tdf ; +; lpm_bustri.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_bustri.tdf ; +; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; +; dcfifo.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo.tdf ; +; db/dcfifo_8fi1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_8fi1.tdf ; +; db/a_gray2bin_tgb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_gray2bin_tgb.tdf ; +; db/a_graycounter_s57.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_s57.tdf ; +; db/a_graycounter_ojc.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_ojc.tdf ; +; db/a_graycounter_njc.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_njc.tdf ; +; db/altsyncram_tl31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_tl31.tdf ; +; db/alt_synch_pipe_rld.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_rld.tdf ; +; db/dffpipe_qe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_qe9.tdf ; +; db/dffpipe_9d9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_9d9.tdf ; +; db/dffpipe_oe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_oe9.tdf ; +; db/alt_synch_pipe_sld.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_sld.tdf ; +; db/dffpipe_re9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_re9.tdf ; +; lpm_mux.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mux.tdf ; +; db/mux_bbe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_bbe.tdf ; +; lpm_ff.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_ff.tdf ; +; altddio_bidir.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_bidir.tdf ; +; db/ddio_bidir_3jl.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_bidir_3jl.tdf ; +; db/mux_58e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_58e.tdf ; +; lpm_latch.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_latch.tdf ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.tdf ; +; db/altsyncram_lf92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_lf92.tdf ; +; mux41.bdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/others/maxplus2/mux41.bdf ; +; db/mux_dcf.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_dcf.tdf ; +; scfifo.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/scfifo.tdf ; +; db/scfifo_lk21.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/scfifo_lk21.tdf ; +; db/a_dpfifo_oq21.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_dpfifo_oq21.tdf ; +; db/altsyncram_gj81.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_gj81.tdf ; +; db/cmpr_br8.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_br8.tdf ; +; db/cntr_omb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_omb.tdf ; +; db/cntr_5n7.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_5n7.tdf ; +; db/cntr_pmb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_pmb.tdf ; +; db/altsyncram_rb92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_rb92.tdf ; +; db/altsyncram_pf92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_pf92.tdf ; +; db/mux_96e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_96e.tdf ; +; db/mux_mpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_mpe.tdf ; +; db/mux_f6e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_f6e.tdf ; +; lpm_constant.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_constant.tdf ; +; altddio_out.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_out.tdf ; +; db/ddio_out_o2f.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_o2f.tdf ; +; db/mux_kpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_kpe.tdf ; +; db/mux_npe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_npe.tdf ; +; db/mux_gpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_gpe.tdf ; +; db/ddio_out_are.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_are.tdf ; +; db/altpll_isv2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_isv2.tdf ; +; altpll4.tdf ; yes ; Auto-Found Wizard-Generated File ; C:/FireBee/FPGA/altpll4.tdf ; +; altpll.inc ; yes ; Auto-Found AHDL File ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.inc ; +; db/altpll_c6j2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_c6j2.tdf ; +; altpll_reconfig1.tdf ; yes ; Auto-Found Wizard-Generated File ; C:/FireBee/FPGA/altpll_reconfig1.tdf ; +; altpll_reconfig1_pllrcfg_t4q.tdf ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/altpll_reconfig1_pllrcfg_t4q.tdf ; +; altsyncram.inc ; yes ; Auto-Found AHDL File ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.inc ; +; db/altsyncram_46r.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_46r.tdf ; +; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf ; +; db/add_sub_hpa.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/add_sub_hpa.tdf ; +; db/add_sub_k8a.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/add_sub_k8a.tdf ; +; lpm_compare.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_compare.tdf ; +; db/cmpr_tnd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_tnd.tdf ; +; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_counter.tdf ; +; db/cntr_30l.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_30l.tdf ; +; db/cntr_qij.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_qij.tdf ; +; db/cntr_pij.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_pij.tdf ; +; db/cntr_9cj.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_9cj.tdf ; +; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_decode.tdf ; +; db/decode_2af.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/decode_2af.tdf ; +; db/cntr_mph.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_mph.tdf ; +; db/ddio_out_31f.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_31f.tdf ; +; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mult.tdf ; +; db/mult_cat.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mult_cat.tdf ; +; db/mult_aat.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mult_aat.tdf ; ++----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+----------------+ +; Resource ; Usage ; ++---------------------------------------------+----------------+ +; Estimated Total logic elements ; 10,706 ; +; ; ; +; Total combinational functions ; 8060 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 4947 ; +; -- 3 input functions ; 1867 ; +; -- <=2 input functions ; 1246 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 7261 ; +; -- arithmetic mode ; 799 ; +; ; ; +; Total registers ; 4740 ; +; -- Dedicated logic registers ; 4612 ; +; -- I/O registers ; 256 ; +; ; ; +; I/O pins ; 295 ; +; Total memory bits ; 109344 ; +; Embedded Multiplier 9-bit elements ; 6 ; +; Total PLLs ; 4 ; +; Maximum fan-out node ; MAIN_CLK~input ; +; Maximum fan-out ; 2327 ; +; Total fan-out ; 49317 ; +; Average fan-out ; 3.57 ; ++---------------------------------------------+----------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +; |firebee1 ; 8060 (10) ; 4612 (0) ; 109344 ; 6 ; 0 ; 3 ; 295 ; 0 ; |firebee1 ; work ; +; |DSP:Mathias_Alles| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|DSP:Mathias_Alles ; ; +; |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden| ; 3814 (634) ; 1633 (114) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden ; ; +; |WF1772IP_TOP_SOC:I_FDC| ; 944 (24) ; 406 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC ; ; +; |WF1772IP_AM_DETECTOR:I_AM_DETECTOR| ; 39 (39) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR ; ; +; |WF1772IP_CONTROL:I_CONTROL| ; 533 (533) ; 197 (197) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL ; ; +; |WF1772IP_CRC_LOGIC:I_CRC_LOGIC| ; 40 (40) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC ; ; +; |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL| ; 104 (104) ; 38 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ; +; |WF1772IP_REGISTERS:I_REGISTERS| ; 86 (86) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS ; ; +; |WF1772IP_TRANSCEIVER:I_TRANSCEIVER| ; 118 (118) ; 80 (80) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER ; ; +; |WF2149IP_TOP_SOC:I_SOUND| ; 445 (32) ; 210 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND ; ; +; |WF2149IP_WAVE:I_PSG_WAVE| ; 413 (413) ; 181 (181) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE ; ; +; |WF5380_TOP_SOC:I_SCSI| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI ; ; +; |WF5380_CONTROL:I_CONTROL| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL ; ; +; |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD| ; 199 (2) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 16 (16) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 94 (94) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF6850IP_TOP_SOC:I_ACIA_MIDI| ; 203 (2) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI ; ; +; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 20 (20) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; +; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 94 (94) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; +; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; +; |WF68901IP_TOP_SOC:I_MFP| ; 1199 (178) ; 460 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP ; ; +; |WF68901IP_GPIO:I_GPIO| ; 25 (25) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO ; ; +; |WF68901IP_INTERRUPTS:I_INTERRUPTS| ; 273 (273) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS ; ; +; |WF68901IP_TIMERS:I_TIMERS| ; 434 (434) ; 166 (166) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS ; ; +; |WF68901IP_USART_TOP:I_USART| ; 289 (4) ; 140 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART ; ; +; |WF68901IP_USART_CTRL:I_USART_CTRL| ; 38 (38) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL ; ; +; |WF68901IP_USART_RX:I_USART_RECEIVE| ; 159 (159) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE ; ; +; |WF68901IP_USART_TX:I_USART_TRANSMIT| ; 88 (88) ; 35 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT ; ; +; |dcfifo0:RDF| ; 94 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 94 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_0hh1:auto_generated| ; 94 (17) ; 124 (42) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ; +; |a_gray2bin_lfb:wrptr_g_gray2bin| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin ; ; +; |a_gray2bin_lfb:ws_dgrp_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin ; ; +; |a_graycounter_fic:wrptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ; +; |a_graycounter_k47:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ; +; |alt_synch_pipe_ikd:rs_dgwp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ; +; |dffpipe_hd9:dffpipe12| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ; +; |alt_synch_pipe_jkd:ws_dgrp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ; +; |dffpipe_id9:dffpipe17| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ; +; |altsyncram_bi31:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cmpr_156:wrfull_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:ws_brp| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ; +; |dffpipe_pe9:ws_bwp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |dcfifo1:WRF| ; 96 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF ; ; +; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 96 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; +; |dcfifo_3fh1:auto_generated| ; 96 (18) ; 124 (42) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ; +; |a_gray2bin_lfb:rdptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin ; ; +; |a_gray2bin_lfb:rs_dgwp_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin ; ; +; |a_graycounter_gic:wrptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ; +; |a_graycounter_j47:rdptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ; +; |alt_synch_pipe_kkd:rs_dgwp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ; +; |dffpipe_jd9:dffpipe12| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ; +; |alt_synch_pipe_lkd:ws_dgrp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ; +; |dffpipe_kd9:dffpipe15| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ; +; |altsyncram_ci31:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ; +; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; +; |cntr_t2e:cntr_b| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b ; ; +; |dffpipe_gd9:rs_bwp| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ; +; |dffpipe_pe9:rs_brp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ; +; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; +; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; +; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; +; |mux_a18:wrfull_eq_comp_msb_mux| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; +; |Video:Fredi_Aschwanden| ; 3109 (10) ; 2172 (4) ; 92816 ; 6 ; 0 ; 3 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden ; ; +; |DDR_CTR:DDR_CTR| ; 348 (314) ; 158 (158) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR ; ; +; |lpm_bustri_BYT:$00002| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR| ; 1260 (1013) ; 529 (529) ; 0 ; 6 ; 0 ; 3 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR ; ; +; |lpm_bustri_WORD:$00000| ; 187 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 187 (187) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_WORD:$00002| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_mult:op_12| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated ; ; +; |lpm_mult:op_14| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ; +; |mult_cat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated ; ; +; |lpm_mult:op_6| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ; +; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated ; ; +; |altddio_bidir0:inst1| ; 0 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1 ; ; +; |altddio_bidir:altddio_bidir_component| ; 0 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ; +; |ddio_bidir_3jl:auto_generated| ; 0 (0) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ; +; |altddio_out0:inst2| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ; +; |ddio_out_are:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ; +; |altddio_out2:inst5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_o2f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ; +; |altdpram0:ST_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram0:ST_CLUT_RED| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram1:FALCON_CLUT_RED| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ; +; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM54| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM55| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55 ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |altdpram2:ACP_CLUT_RAM| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM ; ; +; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ; +; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; +; |lpm_bustri_LONG:inst119| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119 ; ; +; |lpm_bustri:lpm_bustri_component| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ; +; |lpm_ff0:inst13| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst14| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst15| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst16| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst17| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst18| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ; +; |lpm_ff0:inst19| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst12| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst20| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst3| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst4| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ; +; |lpm_ff1:inst9| ; 0 (0) ; 24 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst46| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst47| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst49| ; 0 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ; +; |lpm_ff3:inst52| ; 0 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ; +; |lpm_ff4:inst10| ; 0 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst11| ; 0 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ; +; |lpm_ff5:inst97| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst71| ; 0 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ; +; |lpm_ff6:inst94| ; 0 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ; +; |lpm_fifoDZ:inst63| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63 ; ; +; |scfifo:scfifo_component| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ; +; |scfifo_lk21:auto_generated| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated ; ; +; |a_dpfifo_oq21:dpfifo| ; 22 (9) ; 21 (8) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo ; ; +; |altsyncram_gj81:FIFOram| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ; +; |cntr_omb:rd_ptr_msb| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb ; ; +; |cntr_pmb:wr_ptr| ; 7 (7) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr ; ; +; |lpm_fifo_dc0:inst| ; 66 (0) ; 98 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst ; ; +; |dcfifo:dcfifo_component| ; 66 (0) ; 98 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ; +; |dcfifo_8fi1:auto_generated| ; 66 (12) ; 98 (20) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ; +; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; ; +; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; ; +; |a_graycounter_njc:wrptr_gp| ; 17 (17) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ; +; |a_graycounter_s57:rdptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ; +; |alt_synch_pipe_sld:ws_dgrp| ; 0 (0) ; 30 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ; +; |dffpipe_re9:dffpipe22| ; 0 (0) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ; +; |altsyncram_tl31:fifo_ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ; +; |dffpipe_9d9:wraclr| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ; +; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ; +; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ; +; |lpm_latch0:inst27| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27 ; ; +; |lpm_latch:lpm_latch_component| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ; +; |lpm_mux0:inst21| ; 48 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21 ; ; +; |lpm_mux:lpm_mux_component| ; 48 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component ; ; +; |mux_gpe:auto_generated| ; 48 (48) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated ; ; +; |lpm_mux1:inst24| ; 80 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24 ; ; +; |lpm_mux:lpm_mux_component| ; 80 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component ; ; +; |mux_npe:auto_generated| ; 80 (80) ; 81 (81) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated ; ; +; |lpm_mux2:inst25| ; 80 (0) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25 ; ; +; |lpm_mux:lpm_mux_component| ; 80 (0) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component ; ; +; |mux_mpe:auto_generated| ; 80 (80) ; 41 (41) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated ; ; +; |lpm_mux3:inst102| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102 ; ; +; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component ; ; +; |mux_96e:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated ; ; +; |lpm_mux4:inst81| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81 ; ; +; |lpm_mux:lpm_mux_component| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component ; ; +; |mux_f6e:auto_generated| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated ; ; +; |lpm_mux5:inst22| ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22 ; ; +; |lpm_mux:lpm_mux_component| ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component ; ; +; |mux_58e:auto_generated| ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated ; ; +; |lpm_mux6:inst7| ; 90 (0) ; 67 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7 ; ; +; |lpm_mux:lpm_mux_component| ; 90 (0) ; 67 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component ; ; +; |mux_kpe:auto_generated| ; 90 (90) ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated ; ; +; |lpm_muxDZ:inst62| ; 128 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62 ; ; +; |lpm_mux:lpm_mux_component| ; 128 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component ; ; +; |mux_dcf:auto_generated| ; 128 (128) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated ; ; +; |lpm_muxVDM:inst100| ; 736 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100 ; ; +; |lpm_mux:lpm_mux_component| ; 736 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component ; ; +; |mux_bbe:auto_generated| ; 736 (736) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated ; ; +; |lpm_shiftreg0:sr0| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr1| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr2| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr3| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr4| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr5| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr6| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg0:sr7| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg4:inst26| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ; +; |lpm_shiftreg6:inst92| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92 ; ; +; |lpm_shiftreg:lpm_shiftreg_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ; +; |mux41:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40 ; ; +; |mux41:inst41| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41 ; ; +; |mux41:inst42| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42 ; ; +; |mux41:inst43| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43 ; ; +; |mux41:inst44| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44 ; ; +; |mux41:inst45| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45 ; ; +; |altddio_out3:inst5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst6| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst8| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8 ; ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component ; ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; +; |altddio_out3:inst9| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9 ; work ; +; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component ; work ; +; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; work ; +; |altpll1:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst ; ; +; |altpll:altpll_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst|altpll:altpll_component ; ; +; |altpll_pul2:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated ; ; +; |altpll2:inst12| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12|altpll:altpll_component ; ; +; |altpll_isv2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated ; ; +; |altpll3:inst13| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13|altpll:altpll_component ; ; +; |altpll_41p2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated ; ; +; |altpll4:inst22| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22 ; ; +; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22|altpll:altpll_component ; ; +; |altpll_c6j2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ; +; |altpll_reconfig1:inst7| ; 309 (0) ; 128 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7 ; ; +; |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 309 (211) ; 128 (80) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ; +; |altsyncram:altsyncram4| ; 0 (0) ; 0 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ; +; |altsyncram_46r:auto_generated| ; 0 (0) ; 0 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ; +; |lpm_compare:cmpr7| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ; +; |cmpr_tnd:auto_generated| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated ; ; +; |lpm_counter:cntr12| ; 10 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ; +; |cntr_30l:auto_generated| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr13| ; 7 (0) ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ; +; |cntr_qij:auto_generated| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated ; ; +; |lpm_counter:cntr14| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated ; ; +; |lpm_counter:cntr15| ; 18 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ; +; |cntr_30l:auto_generated| ; 18 (18) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr1| ; 41 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ; +; |cntr_30l:auto_generated| ; 41 (41) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated ; ; +; |lpm_counter:cntr2| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ; +; |cntr_9cj:auto_generated| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated ; ; +; |lpm_counter:cntr3| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ; +; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated ; ; +; |interrupt_handler:nobody| ; 789 (711) ; 633 (633) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody ; ; +; |lpm_bustri_BYT:$00000| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000 ; ; +; |lpm_bustri:lpm_bustri_component| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00002| ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002 ; ; +; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00004| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004 ; ; +; |lpm_bustri:lpm_bustri_component| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; +; |lpm_bustri_BYT:$00006| ; 22 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006 ; ; +; |lpm_bustri:lpm_bustri_component| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ; +; |lpm_counter0:inst18| ; 18 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18 ; ; +; |lpm_counter:lpm_counter_component| ; 18 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ; +; |cntr_mph:auto_generated| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated ; ; +; |lpm_ff0:inst1| ; 0 (0) ; 28 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_ff0:inst1 ; ; +; |lpm_ff:lpm_ff_component| ; 0 (0) ; 28 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ; ++-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 8 ; 256 ; 32 ; 8192 ; None ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 32 ; 1024 ; 8 ; 8192 ; None ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; +; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; +; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; +; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 128 ; 128 ; 128 ; 16384 ; None ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 128 ; 512 ; 128 ; 65536 ; None ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 144 ; 1 ; -- ; -- ; 144 ; None ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis DSP Block Usage Summary ; ++---------------------------------------+-------------+ +; Statistic ; Number Used ; ++---------------------------------------+-------------+ +; Simple Multipliers (9-bit) ; 0 ; +; Simple Multipliers (18-bit) ; 3 ; +; Embedded Multiplier Blocks ; -- ; +; Embedded Multiplier 9-bit elements ; 6 ; +; Signed Embedded Multipliers ; 0 ; +; Unsigned Embedded Multipliers ; 3 ; +; Mixed Sign Embedded Multipliers ; 0 ; +; Variable Sign Embedded Multipliers ; 0 ; +; Dedicated Input Shift Register Chains ; 0 ; ++---------------------------------------+-------------+ +Note: number of Embedded Multiplier Blocks used is only available after a successful fit. + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------+ +; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR ; ++---------+-------+-------+-------+-------+----------------------------------+ +; Name ; FR_S3 ; FR_S2 ; FR_S1 ; FR_S0 ; FR_WAIT ; ++---------+-------+-------+-------+-------+----------------------------------+ +; FR_WAIT ; 0 ; 0 ; 0 ; 0 ; 0 ; +; FR_S0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; FR_S1 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; FR_S2 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; FR_S3 ; 1 ; 0 ; 0 ; 0 ; 1 ; ++---------+-------+-------+-------+-------+----------------------------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM ; ++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ +; Name ; DS_R6 ; DS_R5 ; DS_R4 ; DS_R3 ; DS_R2 ; DS_CB8 ; DS_CB6 ; DS_T10F ; DS_T9F ; DS_T8F ; DS_T7F ; DS_T6F ; DS_T5F ; DS_T4F ; DS_T9W ; DS_T8W ; DS_T7W ; DS_T6W ; DS_T5W ; DS_T4W ; DS_T5R ; DS_T4R ; DS_C7 ; DS_C6 ; DS_C5 ; DS_C4 ; DS_C3 ; DS_C2 ; DS_N8 ; DS_N7 ; DS_N6 ; DS_N5 ; DS_T3 ; DS_T2B ; DS_T2A ; DS_T1 ; ++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ +; DS_T1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DS_T2A ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; DS_T2B ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; DS_T3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; DS_N5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; DS_N6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_N7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_N8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_C7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T4R ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T5R ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T4W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T5W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T6W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T7W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T8W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T9W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T4F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T5F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T6F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T7F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T8F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T9F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_T10F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_CB6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_CB8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R4 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R5 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; DS_R6 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE ; ++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ +; Name ; FCF_STATE.FCF_T7 ; FCF_STATE.FCF_T6 ; FCF_STATE.FCF_T3 ; FCF_STATE.FCF_T2 ; FCF_STATE.FCF_T1 ; FCF_STATE.FCF_T0 ; FCF_STATE.FCF_IDLE ; ++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ +; FCF_STATE.FCF_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; FCF_STATE.FCF_T0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; FCF_STATE.FCF_T1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; FCF_STATE.FCF_T2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; FCF_STATE.FCF_T3 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; FCF_STATE.FCF_T6 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; FCF_STATE.FCF_T7 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE ; ++----------------+--------------+--------------+--------------+-------------------------------------+ +; Name ; CMD_STATE.T7 ; CMD_STATE.T6 ; CMD_STATE.T1 ; CMD_STATE.IDLE ; ++----------------+--------------+--------------+--------------+-------------------------------------+ +; CMD_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; +; CMD_STATE.T1 ; 0 ; 0 ; 1 ; 1 ; +; CMD_STATE.T6 ; 0 ; 1 ; 0 ; 1 ; +; CMD_STATE.T7 ; 1 ; 0 ; 0 ; 1 ; ++----------------+--------------+--------------+--------------+-------------------------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE ; ++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ +; Name ; INT_STATE.VECTOR_OUT ; INT_STATE.REQUEST ; INT_STATE.SCAN ; ++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ +; INT_STATE.SCAN ; 0 ; 0 ; 0 ; +; INT_STATE.REQUEST ; 0 ; 1 ; 1 ; +; INT_STATE.VECTOR_OUT ; 1 ; 0 ; 1 ; ++----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE ; ++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ +; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.CHECK_BREAK ; TR_STATE.IDLE ; ++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ +; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; TR_STATE.CHECK_BREAK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ + + +Encoding Type: One-Hot ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ +; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ +; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ +; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ +; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ +; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ +; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ +; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ +; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ +; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ +; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ + + +Encoding Type: One-Hot ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE ; ++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ +; Name ; DMA_STATE.DMA_STEP_4 ; DMA_STATE.DMA_STEP_3 ; DMA_STATE.DMA_STEP_2 ; DMA_STATE.DMA_STEP_1 ; DMA_STATE.IDLE ; ++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ +; DMA_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; +; DMA_STATE.DMA_STEP_1 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; DMA_STATE.DMA_STEP_2 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; DMA_STATE.DMA_STEP_3 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; DMA_STATE.DMA_STEP_4 ; 1 ; 0 ; 0 ; 0 ; 1 ; ++----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ + + +Encoding Type: One-Hot ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE ; ++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ +; Name ; CTRL_STATE.DMA_INIT_RCV ; CTRL_STATE.DMA_TARG_RCV ; CTRL_STATE.DMA_SEND ; CTRL_STATE.WAIT_2200ns ; CTRL_STATE.WAIT_800ns ; CTRL_STATE.IDLE ; ++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ +; CTRL_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CTRL_STATE.WAIT_800ns ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; CTRL_STATE.WAIT_2200ns ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; CTRL_STATE.DMA_SEND ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; CTRL_STATE.DMA_TARG_RCV ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; CTRL_STATE.DMA_INIT_RCV ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ + + +Encoding Type: One-Hot ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP ; ++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ +; Name ; PRECOMP.LATE ; PRECOMP.EARLY ; PRECOMP.NOMINAL ; ++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ +; PRECOMP.NOMINAL ; 0 ; 0 ; 0 ; +; PRECOMP.EARLY ; 0 ; 1 ; 1 ; +; PRECOMP.LATE ; 1 ; 0 ; 1 ; ++-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE ; ++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ +; Name ; MFM_STATE.C_10 ; MFM_STATE.B_01 ; MFM_STATE.A_00 ; ++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ +; MFM_STATE.A_00 ; 0 ; 0 ; 0 ; +; MFM_STATE.B_01 ; 0 ; 1 ; 1 ; +; MFM_STATE.C_10 ; 1 ; 0 ; 1 ; ++----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ + + +Encoding Type: One-Hot ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; ++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ +; Name ; CMD_STATE.T3_VERIFY_CRC ; CMD_STATE.T3_LOAD_SR ; CMD_STATE.T3_CHECK_RD ; CMD_STATE.T3_SET_DRQ_2 ; CMD_STATE.T3_LOAD_DATA_2 ; CMD_STATE.T3_SHIFT_ADR ; CMD_STATE.T3_VERIFY_AM ; CMD_STATE.T3_RD_ADR ; CMD_STATE.T3_SET_DRQ_1 ; CMD_STATE.T3_LOAD_DATA_1 ; CMD_STATE.T3_CHECK_DR ; CMD_STATE.T3_CHECK_BYTE ; CMD_STATE.T3_DETECT_AM ; CMD_STATE.T3_CHECK_INDEX_3 ; CMD_STATE.T3_SHIFT ; CMD_STATE.T3_RD_TRACK ; CMD_STATE.T3_DATALOST ; CMD_STATE.T3_CHECK_INDEX_2 ; CMD_STATE.T3_WR_DATA ; CMD_STATE.T3_LOAD_SHFT ; CMD_STATE.T3_CHECK_INDEX_1 ; CMD_STATE.T3_VERIFY_DRQ ; CMD_STATE.T3_DELAY_B3 ; CMD_STATE.T3_WR ; CMD_STATE.T2_WR_FF ; CMD_STATE.T2_WR_CRC ; CMD_STATE.T2_WRSTAT ; CMD_STATE.T2_DATALOST ; CMD_STATE.T2_VERIFY_DRQ_3 ; CMD_STATE.T2_WR_BYTE ; CMD_STATE.T2_LOAD_SHFT ; CMD_STATE.T2_WR_AM ; CMD_STATE.T2_WR_LEADIN ; CMD_STATE.T2_DELAY_B11 ; CMD_STATE.T2_CHECK_MODE ; CMD_STATE.T2_DELAY_B1 ; CMD_STATE.T2_VERIFY_DRQ_2 ; CMD_STATE.T2_DELAY_B8 ; CMD_STATE.T2_SET_DRQ ; CMD_STATE.T2_DELAY_B2 ; CMD_STATE.T2_MULTISECT ; CMD_STATE.T2_VERIFY_CRC_2 ; CMD_STATE.T2_RDSTAT ; CMD_STATE.T2_VERIFY_DRQ_1 ; CMD_STATE.T2_NEXTBYTE ; CMD_STATE.T2_LOAD_DATA ; CMD_STATE.T2_FIRSTBYTE ; CMD_STATE.T2_VERIFY_AM ; CMD_STATE.T2_VERIFY_CRC_1 ; CMD_STATE.T2_SCAN_LEN ; CMD_STATE.T2_SCAN_SECT ; CMD_STATE.T2_SCAN_TRACK ; CMD_STATE.T2_INIT ; CMD_STATE.T2_RD_WR_SECT ; CMD_STATE.T1_VERIFY_CRC ; CMD_STATE.T1_VERIFY_DELAY ; CMD_STATE.T1_SCAN_CRC ; CMD_STATE.T1_SCAN_TRACK ; CMD_STATE.T1_SPINDOWN ; CMD_STATE.T1_STEP_DELAY ; CMD_STATE.T1_TRAP ; CMD_STATE.T1_STEP ; CMD_STATE.T1_HEAD_CTRL ; CMD_STATE.T1_CHECK_DIR ; CMD_STATE.T1_COMP_TR_DSR ; CMD_STATE.T1_LOAD_SHFT ; CMD_STATE.T1_STEPPING ; CMD_STATE.T1_SEEK_RESTORE ; CMD_STATE.DECODE ; CMD_STATE.DELAY_15MS ; CMD_STATE.SPINUP ; CMD_STATE.INIT ; CMD_STATE.IDLE ; ++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ +; CMD_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; CMD_STATE.INIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; +; CMD_STATE.SPINUP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; +; CMD_STATE.DELAY_15MS ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; +; CMD_STATE.DECODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SEEK_RESTORE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_STEPPING ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_COMP_TR_DSR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_CHECK_DIR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_HEAD_CTRL ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_STEP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_TRAP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_STEP_DELAY ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SPINDOWN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SCAN_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_SCAN_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_VERIFY_DELAY ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T1_VERIFY_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_RD_WR_SECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_INIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SCAN_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SCAN_SECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SCAN_LEN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_CRC_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_FIRSTBYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_LOAD_DATA ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_NEXTBYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_DRQ_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_RDSTAT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_CRC_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_MULTISECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_SET_DRQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_DRQ_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_CHECK_MODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DELAY_B11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_LEADIN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_VERIFY_DRQ_3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_DATALOST ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WRSTAT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T2_WR_FF ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_WR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_DELAY_B3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_VERIFY_DRQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_INDEX_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_WR_DATA ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_INDEX_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_DATALOST ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_RD_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SHIFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_INDEX_3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_DETECT_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_DR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_DATA_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SET_DRQ_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_RD_ADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_VERIFY_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SHIFT_ADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_DATA_2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_SET_DRQ_2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_CHECK_RD ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_LOAD_SR ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; +; CMD_STATE.T3_VERIFY_CRC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; ++----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Protected by Synthesis ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1 ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate3_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[8] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[17] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_nominal_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_init_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_ena_state ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate2_state ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; no ; yes ; +; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8] ; no ; yes ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_seq_ena_state ; no ; yes ; ++----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; User-Specified and Inferred Latches ; ++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ +; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ; ++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; +; Number of user-specified and inferred latches = 32 ; ; ; ++------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ +Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations. + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; interrupt_handler:nobody|INT_LATCH[31] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[31] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[30] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[30] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[29] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[29] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[28] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[28] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[27] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[27] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[26] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[26] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[25] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[25] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[24] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[24] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[23] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[23] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[22] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[22] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[21] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[21] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[20] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[20] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[19] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[19] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[18] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[18] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[17] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[17] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[16] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[16] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[15] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[15] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[14] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[14] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[13] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[13] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[12] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[12] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[11] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[11] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[10] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[10] ; Lost fanout ; +; interrupt_handler:nobody|INT_LATCH[7] ; Stuck at GND due to stuck port clock ; +; interrupt_handler:nobody|INT_CLEAR[7] ; Lost fanout ; +; interrupt_handler:nobody|WERTE[7][13] ; Stuck at VCC due to stuck port data_in ; +; interrupt_handler:nobody|WERTE[6][10] ; Stuck at GND due to stuck port clear ; +; interrupt_handler:nobody|WERTE[2][11] ; Stuck at VCC due to stuck port data_in ; +; interrupt_handler:nobody|WERTE[1][11] ; Stuck at VCC due to stuck port data_in ; +; interrupt_handler:nobody|WERTE[0][11] ; Stuck at VCC due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_REQ ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0..6] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0..5] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0..7] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[6] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0,2..5,7] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[0..2] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[0..7] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SPER ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0..2] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6..7] ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9] ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10] ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8] ; Lost fanout ; +; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[2] ; Merged with Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_OUT ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|OE ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\OVERRUN:FIRST_READ ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[6] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[7] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[0..3] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_DRQ:LOCK ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_ACTIVE_I ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4,7] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[1] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe18 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe2 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe20 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe34 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe36 ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe4 ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|INT ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DRQ ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[0..7] ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDRWR_D_SEL ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[0..2] ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; +; Video:Fredi_Aschwanden|inst88 ; Merged with Video:Fredi_Aschwanden|inst90 ; +; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[0..2] ; Merged with Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; +; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_AC ; Stuck at GND due to stuck port data_in ; +; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[2] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00 ; Lost fanout ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DELAY_800ns ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[0..3] ; Stuck at GND due to stuck port data_in ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[0] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12] ; Lost fanout ; +; Total Number of Removed Registers = 223 ; ; ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Removed Registers Triggering Further Register Optimizations ; ++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Register name ; Reason for Removal ; Registers Removed due to This Register ; ++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN, ; +; ; due to stuck port data_in ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[2] ; +; interrupt_handler:nobody|INT_LATCH[30] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[30] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[29] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[29] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[28] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[28] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[27] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[27] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[26] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[26] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[25] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[25] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[24] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[24] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[23] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[23] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[22] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[22] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[21] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[21] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[20] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[20] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[19] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[19] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[18] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[18] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[17] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[17] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[16] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[16] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[15] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[15] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[14] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[14] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[13] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[13] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[12] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[12] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[11] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[11] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[10] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[10] ; +; ; due to stuck port clock ; ; +; interrupt_handler:nobody|INT_LATCH[7] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[7] ; +; ; due to stuck port clock ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[17] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[17] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[16] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[16] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[9] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[9] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[8] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[8] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[1] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[1] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[20] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[20] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[19] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[19] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[18] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[18] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[17] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[17] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[16] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[16] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[12] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[12] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[11] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[11] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[10] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[10] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[9] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[9] ; +; ; due to stuck port data_in ; ; +; interrupt_handler:nobody|INT_LATCH[31] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[31] ; +; ; due to stuck port clock ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[4] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[4] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[3] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[3] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[2] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[2] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[1] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[1] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0] ; +; ; due to stuck port data_in ; ; +; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[8] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[8] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2] ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0] ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[2] ; +; ; due to stuck port data_in ; ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; +; ; due to stuck port data_in ; ; ++-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 4612 ; +; Number of registers using Synchronous Clear ; 156 ; +; Number of registers using Synchronous Load ; 204 ; +; Number of registers using Asynchronous Clear ; 1431 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 2735 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Inverted Register Statistics ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; Inverted Register ; Fan out ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; 4 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[2] ; 5 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[1] ; 5 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0] ; 4 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT[7] ; 7 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE ; 7 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE ; 7 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IRQ_ACIAn ; 2 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0 ; 8 ; +; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state ; 2 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_lsb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_msb_aeb ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6 ; 4 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|counter8a0 ; 8 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|parity9 ; 4 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; 1 ; +; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; 1 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; +; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 3 ; +; Total number of inverted registers = 22 ; ; ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[7] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4] ; +; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7] ; +; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4] ; +; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[4] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[4] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[7] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[6] ; +; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3] ; +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2] ; +; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT[0] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[0] ; +; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:CLK_DIVCNT[0] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_START_BIT:TMP[0] ; +; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:LOW_FLT[0] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[3] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[0] ; +; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1] ; +; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0] ; +; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0] ; +; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2] ; +; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[7] ; +; 5:1 ; 21 bits ; 63 LEs ; 42 LEs ; 21 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; +; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[19] ; +; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1] ; +; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0] ; +; 4:1 ; 31 bits ; 62 LEs ; 62 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; +; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:TIMER[1] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[5] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[2] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[1] ; +; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[5] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3] ; +; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0] ; +; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2] ; +; 7:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4] ; +; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4] ; +; 7:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5] ; +; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6] ; +; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; +; 7:1 ; 13 bits ; 52 LEs ; 52 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[10] ; +; 6:1 ; 20 bits ; 80 LEs ; 20 LEs ; 60 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; +; 11:1 ; 2 bits ; 14 LEs ; 10 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1] ; +; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0] ; +; 9:1 ; 2 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5] ; +; 14:1 ; 5 bits ; 45 LEs ; 10 LEs ; 35 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3] ; +; 11:1 ; 8 bits ; 56 LEs ; 16 LEs ; 40 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B[1] ; +; 11:1 ; 8 bits ; 56 LEs ; 16 LEs ; 40 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A[1] ; +; 17:1 ; 4 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[2] ; +; 17:1 ; 4 bits ; 44 LEs ; 0 LEs ; 44 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5] ; +; 3:1 ; 24 bits ; 48 LEs ; 48 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; +; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0] ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_NEXT_STATE ; +; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEXCNT ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21] ; +; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|DATA_OUT[4] ; +; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[1] ; +; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE ; +; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE ; +; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|NEXT_CMD_STATE ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_A[1] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_B[2] ; +; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_C[1] ; +; 16:1 ; 8 bits ; 80 LEs ; 24 LEs ; 56 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|DATA_OUT[2] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ADDER_IN[1] ; +; 64:1 ; 3 bits ; 126 LEs ; 126 LEs ; 0 LEs ; No ; |firebee1|interrupt_handler:nobody|_ ; +; 17:1 ; 3 bits ; 33 LEs ; 18 LEs ; 15 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[7] ; +; 18:1 ; 4 bits ; 48 LEs ; 44 LEs ; 4 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[2] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; wrptr_g ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; +; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe17|dffe18a ; +; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe17|dffe18a* ; - ; - ; +; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; +; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a* ; - ; - ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; sub_parity9a0 ; +; POWER_UP_LEVEL ; LOW ; - ; parity8 ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; wrptr_g ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; +; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe15|dffe16a ; +; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a* ; - ; - ; +; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; +; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a* ; - ; - ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; sub_parity6a0 ; +; POWER_UP_LEVEL ; LOW ; - ; parity5 ; ++----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ++---------------------------------+-------+------+----------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+----------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+----------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; +; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 4 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; R105 ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; +; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; +; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe22|dffe23a ; +; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe22|dffe23a* ; - ; - ; +; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a ; +; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe15|dffe16a* ; - ; - ; ++---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ +; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; ++----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p ; ++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; +; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; ++---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; +; POWER_UP_LEVEL ; HIGH ; - ; sub_parity12a0 ; +; POWER_UP_LEVEL ; LOW ; - ; parity11 ; ++---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ +; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; +; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; ++-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; ++---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ++---------------------------+-------------+------+---------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+---------------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; DDIO_INPUT_REGISTER ; LOW ; - ; input_cell_L ; +; DDIO_INPUT_REGISTER ; HIGH ; - ; input_cell_H ; +; SUPPRESS_DA_RULE_INTERNAL ; D101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; D103 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; D102 ; - ; - ; ++---------------------------+-------------+------+---------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; +; DDIO_INPUT_REGISTER ; HIGH ; - ; input_cell_h ; +; DDIO_INPUT_REGISTER ; LOW ; - ; input_cell_l ; +; MEGAFUNCTION_GENERATED_TRI ; ON ; - ; tri_buf1a ; ++-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ++---------------------------------+--------------------+------+--------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+--------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+--------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+---------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+-----------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+---------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+---------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+---------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+---------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+---------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+-----------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------+ +; Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ++---------------------------+-------+------+-----------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; ++---------------------------+-------+------+-----------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ++---------------------------------------+-------------+------+------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------------+-------------+------+------------------------------------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; +; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 2 ; - ; le_comb10 ; +; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 0 ; - ; le_comb8 ; +; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 1 ; - ; le_comb9 ; +; POWER_UP_LEVEL ; LOW ; - ; idle_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_data_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_data_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_first_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_first_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_init_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_init_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_last_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; read_last_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_counter_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_init_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_post_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_seq_data_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_seq_ena_state ; +; POWER_UP_LEVEL ; LOW ; - ; reconfig_wait_state ; +; POWER_UP_LEVEL ; HIGH ; - ; reset_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_data_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_init_nominal_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_init_state ; +; POWER_UP_LEVEL ; LOW ; - ; write_nominal_state ; ++---------------------------------------+-------------+------+------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------+ +; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+------------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------+ +; Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ++---------------------------+-------+------+-----------------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------+------+-----------------------------------+ +; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; ++---------------------------+-------+------+-----------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component ; ++---------------------------+-------------+------+----------------------------+ +; Assignment ; Value ; From ; To ; ++---------------------------+-------------+------+----------------------------+ +; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; +; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; +; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; +; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; +; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; ++---------------------------+-------------+------+----------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; Assignment ; Value ; From ; To ; ++-----------------------------+-------+------+------------------------------------------------------------+ +; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; ++-----------------------------+-------+------+------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component ; ++-------------------------------+--------------------+------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------+------------------------------+ +; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 67 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 67 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 1 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 90 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 900 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 66 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_pul2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------+------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; ACF_DISABLE_MLAB_RAM_USE ; FALSE ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; LPM_NUMWORDS ; 1024 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_WIDTH_R ; 32 ; Signed Integer ; +; LPM_WIDTHU ; 10 ; Signed Integer ; +; LPM_WIDTHU_R ; 8 ; Signed Integer ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; RDSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; WRSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; CBXI_PARAMETER ; dcfifo_0hh1 ; Untyped ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +; ACF_DISABLE_MLAB_RAM_USE ; FALSE ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; LPM_NUMWORDS ; 256 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_WIDTH_R ; 8 ; Signed Integer ; +; LPM_WIDTHU ; 8 ; Signed Integer ; +; LPM_WIDTHU_R ; 10 ; Signed Integer ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; OVERFLOW_CHECKING ; ON ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; RDSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; UNDERFLOW_CHECKING ; ON ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; WRITE_ACLR_SYNCH ; OFF ; Untyped ; +; WRSYNC_DELAYPIPE ; 5 ; Signed Integer ; +; CBXI_PARAMETER ; dcfifo_3fh1 ; Untyped ; ++--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +; TOP ; 152 ; Signed Integer ; +; BOTTOM ; 104 ; Signed Integer ; +; PHASE_CORR ; 75 ; Signed Integer ; ++----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component ; ++-------------------------------+--------------------+--------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------+--------------------------------+ +; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK1 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 16 ; Signed Integer ; +; CLK2_MULTIPLY_BY ; 25 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 16 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 11 ; Signed Integer ; +; CLK2_DIVIDE_BY ; 33 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 33 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 33 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_USED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_41p2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------+--------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_DIRECTION ; RIGHT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; WIDTH_BYTEENA ; 1 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_NUMWORDS ; 512 ; Signed Integer ; +; LPM_WIDTHU ; 9 ; Signed Integer ; +; LPM_SHOWAHEAD ; OFF ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; DELAY_RDUSEDW ; 1 ; Untyped ; +; DELAY_WRUSEDW ; 1 ; Untyped ; +; RDSYNC_DELAYPIPE ; 6 ; Signed Integer ; +; WRSYNC_DELAYPIPE ; 6 ; Signed Integer ; +; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; +; WRITE_ACLR_SYNCH ; ON ; Untyped ; +; CBXI_PARAMETER ; dcfifo_8fi1 ; Untyped ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_DIRECTION ; RIGHT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+---------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_SIZE ; 16 ; Signed Integer ; +; LPM_WIDTHS ; 4 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_bbe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ++------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ++------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ++--------------------------+----------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------------+----------------+------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 32 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; IMPLEMENT_INPUT_IN_LCELL ; ON ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_bidir_3jl ; Untyped ; ++--------------------------+----------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 64 ; Signed Integer ; +; LPM_SIZE ; 4 ; Signed Integer ; +; LPM_WIDTHS ; 2 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_58e ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ++----------------+--------+-------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+--------+-------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; ++----------------+--------+-------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_DIRECTION ; RIGHT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 6 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 6 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; ++------------------------------------+-----------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 128 ; Signed Integer ; +; LPM_SIZE ; 2 ; Signed Integer ; +; LPM_WIDTHS ; 1 ; Signed Integer ; +; LPM_PIPELINE ; 1 ; Signed Integer ; +; CBXI_PARAMETER ; mux_dcf ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; lpm_width ; 128 ; Signed Integer ; +; LPM_NUMWORDS ; 128 ; Signed Integer ; +; LPM_WIDTHU ; 7 ; Signed Integer ; +; LPM_SHOWAHEAD ; ON ; Untyped ; +; UNDERFLOW_CHECKING ; OFF ; Untyped ; +; OVERFLOW_CHECKING ; OFF ; Untyped ; +; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; +; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; +; ALMOST_FULL_VALUE ; 0 ; Untyped ; +; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; +; USE_EAB ; ON ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; CBXI_PARAMETER ; scfifo_lk21 ; Untyped ; ++-------------------------+-------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_DIRECTION ; LEFT ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+--------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+--------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 6 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 6 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; ++------------------------------------+-----------------+--------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 6 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+-------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 6 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 6 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; ++------------------------------------+-----------------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+--------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 3 ; Signed Integer ; +; WIDTHAD_A ; 4 ; Signed Integer ; +; NUMWORDS_A ; 16 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 3 ; Signed Integer ; +; WIDTHAD_B ; 4 ; Signed Integer ; +; NUMWORDS_B ; 16 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; ++------------------------------------+-----------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+----------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 3 ; Signed Integer ; +; WIDTHAD_A ; 4 ; Signed Integer ; +; NUMWORDS_A ; 16 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 3 ; Signed Integer ; +; WIDTHAD_B ; 4 ; Signed Integer ; +; NUMWORDS_B ; 16 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; ++------------------------------------+-----------------+----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Signed Integer ; ++----------------+-------+-----------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 3 ; Signed Integer ; +; WIDTHAD_A ; 4 ; Signed Integer ; +; NUMWORDS_A ; 16 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 3 ; Signed Integer ; +; WIDTHAD_B ; 4 ; Signed Integer ; +; NUMWORDS_B ; 16 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 1 ; Signed Integer ; +; LPM_SIZE ; 2 ; Signed Integer ; +; LPM_WIDTHS ; 1 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_96e ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+-------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_SIZE ; 16 ; Signed Integer ; +; LPM_WIDTHS ; 4 ; Signed Integer ; +; LPM_PIPELINE ; 2 ; Signed Integer ; +; CBXI_PARAMETER ; mux_mpe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 7 ; Signed Integer ; +; LPM_SIZE ; 2 ; Signed Integer ; +; LPM_WIDTHS ; 1 ; Signed Integer ; +; LPM_PIPELINE ; 0 ; Signed Integer ; +; CBXI_PARAMETER ; mux_f6e ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 7 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_pf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; ++------------------------------------+-----------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+--------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; +; WIDTH_A ; 8 ; Signed Integer ; +; WIDTHAD_A ; 8 ; Signed Integer ; +; NUMWORDS_A ; 256 ; Signed Integer ; +; OUTDATA_REG_A ; CLOCK0 ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 8 ; Signed Integer ; +; WIDTHAD_B ; 8 ; Signed Integer ; +; NUMWORDS_B ; 256 ; Signed Integer ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; CLOCK1 ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; +; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; ++------------------------------------+-----------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 24 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_o2f ; Untyped ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+-----------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-----------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_SIZE ; 8 ; Signed Integer ; +; LPM_WIDTHS ; 3 ; Signed Integer ; +; LPM_PIPELINE ; 2 ; Signed Integer ; +; CBXI_PARAMETER ; mux_kpe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+-----------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 5 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 24 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 2 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 2 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 2 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 16 ; Signed Integer ; +; LPM_SIZE ; 8 ; Signed Integer ; +; LPM_WIDTHS ; 3 ; Signed Integer ; +; LPM_PIPELINE ; 4 ; Signed Integer ; +; CBXI_PARAMETER ; mux_npe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_CVALUE ; 0 ; Signed Integer ; +; ENABLE_RUNTIME_MOD ; NO ; Untyped ; +; CBXI_PARAMETER ; lpm_constant_qf6 ; Untyped ; ++--------------------+------------------+--------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ++------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component ; ++------------------------+-------------+------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_SIZE ; 4 ; Signed Integer ; +; LPM_WIDTHS ; 2 ; Signed Integer ; +; LPM_PIPELINE ; 4 ; Signed Integer ; +; CBXI_PARAMETER ; mux_gpe ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; ++------------------------+-------------+------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 4 ; Signed Integer ; +; POWER_UP_HIGH ; ON ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_are ; Untyped ; ++------------------------+--------------+----------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component ; ++-------------------------------+--------------------+--------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+--------------------+--------------------------------+ +; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 2 ; Signed Integer ; +; CLK3_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK2_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK1_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK3_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK2_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK1_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 11364 ; Untyped ; +; CLK3_PHASE_SHIFT ; 2210 ; Untyped ; +; CLK2_PHASE_SHIFT ; 3788 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 5051 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_USED ; Untyped ; +; PORT_CLK2 ; PORT_USED ; Untyped ; +; PORT_CLK3 ; PORT_USED ; Untyped ; +; PORT_CLK4 ; PORT_USED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; +; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_UNUSED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_UNUSED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_isv2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Signed Integer ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+--------------------+--------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component ; ++-------------------------------+-------------------+---------------------------------+ +; Parameter Name ; Value ; Type ; ++-------------------------------+-------------------+---------------------------------+ +; OPERATION_MODE ; NORMAL ; Untyped ; +; PLL_TYPE ; AUTO ; Untyped ; +; QUALIFY_CONF_DONE ; OFF ; Untyped ; +; COMPENSATE_CLOCK ; CLK0 ; Untyped ; +; SCAN_CHAIN ; LONG ; Untyped ; +; PRIMARY_CLOCK ; INCLK0 ; Untyped ; +; INCLK0_INPUT_FREQUENCY ; 20833 ; Untyped ; +; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; +; GATE_LOCK_SIGNAL ; NO ; Untyped ; +; GATE_LOCK_COUNTER ; 0 ; Untyped ; +; LOCK_HIGH ; 1 ; Untyped ; +; LOCK_LOW ; 1 ; Untyped ; +; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; +; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; +; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; +; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; +; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; +; SKIP_VCO ; OFF ; Untyped ; +; SWITCH_OVER_COUNTER ; 0 ; Untyped ; +; SWITCH_OVER_TYPE ; AUTO ; Untyped ; +; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; +; BANDWIDTH ; 0 ; Untyped ; +; BANDWIDTH_TYPE ; AUTO ; Untyped ; +; SPREAD_FREQUENCY ; 0 ; Untyped ; +; DOWN_SPREAD ; 0 ; Untyped ; +; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; +; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; +; CLK9_MULTIPLY_BY ; 0 ; Untyped ; +; CLK8_MULTIPLY_BY ; 0 ; Untyped ; +; CLK7_MULTIPLY_BY ; 0 ; Untyped ; +; CLK6_MULTIPLY_BY ; 0 ; Untyped ; +; CLK5_MULTIPLY_BY ; 1 ; Untyped ; +; CLK4_MULTIPLY_BY ; 1 ; Untyped ; +; CLK3_MULTIPLY_BY ; 1 ; Untyped ; +; CLK2_MULTIPLY_BY ; 1 ; Untyped ; +; CLK1_MULTIPLY_BY ; 1 ; Untyped ; +; CLK0_MULTIPLY_BY ; 2 ; Untyped ; +; CLK9_DIVIDE_BY ; 0 ; Untyped ; +; CLK8_DIVIDE_BY ; 0 ; Untyped ; +; CLK7_DIVIDE_BY ; 0 ; Untyped ; +; CLK6_DIVIDE_BY ; 0 ; Untyped ; +; CLK5_DIVIDE_BY ; 1 ; Untyped ; +; CLK4_DIVIDE_BY ; 1 ; Untyped ; +; CLK3_DIVIDE_BY ; 1 ; Untyped ; +; CLK2_DIVIDE_BY ; 1 ; Untyped ; +; CLK1_DIVIDE_BY ; 1 ; Untyped ; +; CLK0_DIVIDE_BY ; 1 ; Untyped ; +; CLK9_PHASE_SHIFT ; 0 ; Untyped ; +; CLK8_PHASE_SHIFT ; 0 ; Untyped ; +; CLK7_PHASE_SHIFT ; 0 ; Untyped ; +; CLK6_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_PHASE_SHIFT ; 0 ; Untyped ; +; CLK4_PHASE_SHIFT ; 0 ; Untyped ; +; CLK3_PHASE_SHIFT ; 0 ; Untyped ; +; CLK2_PHASE_SHIFT ; 0 ; Untyped ; +; CLK1_PHASE_SHIFT ; 0 ; Untyped ; +; CLK0_PHASE_SHIFT ; 0 ; Untyped ; +; CLK5_TIME_DELAY ; 0 ; Untyped ; +; CLK4_TIME_DELAY ; 0 ; Untyped ; +; CLK3_TIME_DELAY ; 0 ; Untyped ; +; CLK2_TIME_DELAY ; 0 ; Untyped ; +; CLK1_TIME_DELAY ; 0 ; Untyped ; +; CLK0_TIME_DELAY ; 0 ; Untyped ; +; CLK9_DUTY_CYCLE ; 50 ; Untyped ; +; CLK8_DUTY_CYCLE ; 50 ; Untyped ; +; CLK7_DUTY_CYCLE ; 50 ; Untyped ; +; CLK6_DUTY_CYCLE ; 50 ; Untyped ; +; CLK5_DUTY_CYCLE ; 50 ; Untyped ; +; CLK4_DUTY_CYCLE ; 50 ; Untyped ; +; CLK3_DUTY_CYCLE ; 50 ; Untyped ; +; CLK2_DUTY_CYCLE ; 50 ; Untyped ; +; CLK1_DUTY_CYCLE ; 50 ; Untyped ; +; CLK0_DUTY_CYCLE ; 50 ; Untyped ; +; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; +; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; +; LOCK_WINDOW_UI ; 0.05 ; Untyped ; +; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; +; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; +; DPA_MULTIPLY_BY ; 0 ; Untyped ; +; DPA_DIVIDE_BY ; 1 ; Untyped ; +; DPA_DIVIDER ; 0 ; Untyped ; +; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; +; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; +; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; +; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; +; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; +; VCO_MULTIPLY_BY ; 0 ; Untyped ; +; VCO_DIVIDE_BY ; 0 ; Untyped ; +; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; +; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; +; VCO_MIN ; 0 ; Untyped ; +; VCO_MAX ; 0 ; Untyped ; +; VCO_CENTER ; 0 ; Untyped ; +; PFD_MIN ; 0 ; Untyped ; +; PFD_MAX ; 0 ; Untyped ; +; M_INITIAL ; 0 ; Untyped ; +; M ; 0 ; Untyped ; +; N ; 1 ; Untyped ; +; M2 ; 1 ; Untyped ; +; N2 ; 1 ; Untyped ; +; SS ; 1 ; Untyped ; +; C0_HIGH ; 0 ; Untyped ; +; C1_HIGH ; 0 ; Untyped ; +; C2_HIGH ; 0 ; Untyped ; +; C3_HIGH ; 0 ; Untyped ; +; C4_HIGH ; 0 ; Untyped ; +; C5_HIGH ; 0 ; Untyped ; +; C6_HIGH ; 0 ; Untyped ; +; C7_HIGH ; 0 ; Untyped ; +; C8_HIGH ; 0 ; Untyped ; +; C9_HIGH ; 0 ; Untyped ; +; C0_LOW ; 0 ; Untyped ; +; C1_LOW ; 0 ; Untyped ; +; C2_LOW ; 0 ; Untyped ; +; C3_LOW ; 0 ; Untyped ; +; C4_LOW ; 0 ; Untyped ; +; C5_LOW ; 0 ; Untyped ; +; C6_LOW ; 0 ; Untyped ; +; C7_LOW ; 0 ; Untyped ; +; C8_LOW ; 0 ; Untyped ; +; C9_LOW ; 0 ; Untyped ; +; C0_INITIAL ; 0 ; Untyped ; +; C1_INITIAL ; 0 ; Untyped ; +; C2_INITIAL ; 0 ; Untyped ; +; C3_INITIAL ; 0 ; Untyped ; +; C4_INITIAL ; 0 ; Untyped ; +; C5_INITIAL ; 0 ; Untyped ; +; C6_INITIAL ; 0 ; Untyped ; +; C7_INITIAL ; 0 ; Untyped ; +; C8_INITIAL ; 0 ; Untyped ; +; C9_INITIAL ; 0 ; Untyped ; +; C0_MODE ; BYPASS ; Untyped ; +; C1_MODE ; BYPASS ; Untyped ; +; C2_MODE ; BYPASS ; Untyped ; +; C3_MODE ; BYPASS ; Untyped ; +; C4_MODE ; BYPASS ; Untyped ; +; C5_MODE ; BYPASS ; Untyped ; +; C6_MODE ; BYPASS ; Untyped ; +; C7_MODE ; BYPASS ; Untyped ; +; C8_MODE ; BYPASS ; Untyped ; +; C9_MODE ; BYPASS ; Untyped ; +; C0_PH ; 0 ; Untyped ; +; C1_PH ; 0 ; Untyped ; +; C2_PH ; 0 ; Untyped ; +; C3_PH ; 0 ; Untyped ; +; C4_PH ; 0 ; Untyped ; +; C5_PH ; 0 ; Untyped ; +; C6_PH ; 0 ; Untyped ; +; C7_PH ; 0 ; Untyped ; +; C8_PH ; 0 ; Untyped ; +; C9_PH ; 0 ; Untyped ; +; L0_HIGH ; 1 ; Untyped ; +; L1_HIGH ; 1 ; Untyped ; +; G0_HIGH ; 1 ; Untyped ; +; G1_HIGH ; 1 ; Untyped ; +; G2_HIGH ; 1 ; Untyped ; +; G3_HIGH ; 1 ; Untyped ; +; E0_HIGH ; 1 ; Untyped ; +; E1_HIGH ; 1 ; Untyped ; +; E2_HIGH ; 1 ; Untyped ; +; E3_HIGH ; 1 ; Untyped ; +; L0_LOW ; 1 ; Untyped ; +; L1_LOW ; 1 ; Untyped ; +; G0_LOW ; 1 ; Untyped ; +; G1_LOW ; 1 ; Untyped ; +; G2_LOW ; 1 ; Untyped ; +; G3_LOW ; 1 ; Untyped ; +; E0_LOW ; 1 ; Untyped ; +; E1_LOW ; 1 ; Untyped ; +; E2_LOW ; 1 ; Untyped ; +; E3_LOW ; 1 ; Untyped ; +; L0_INITIAL ; 1 ; Untyped ; +; L1_INITIAL ; 1 ; Untyped ; +; G0_INITIAL ; 1 ; Untyped ; +; G1_INITIAL ; 1 ; Untyped ; +; G2_INITIAL ; 1 ; Untyped ; +; G3_INITIAL ; 1 ; Untyped ; +; E0_INITIAL ; 1 ; Untyped ; +; E1_INITIAL ; 1 ; Untyped ; +; E2_INITIAL ; 1 ; Untyped ; +; E3_INITIAL ; 1 ; Untyped ; +; L0_MODE ; BYPASS ; Untyped ; +; L1_MODE ; BYPASS ; Untyped ; +; G0_MODE ; BYPASS ; Untyped ; +; G1_MODE ; BYPASS ; Untyped ; +; G2_MODE ; BYPASS ; Untyped ; +; G3_MODE ; BYPASS ; Untyped ; +; E0_MODE ; BYPASS ; Untyped ; +; E1_MODE ; BYPASS ; Untyped ; +; E2_MODE ; BYPASS ; Untyped ; +; E3_MODE ; BYPASS ; Untyped ; +; L0_PH ; 0 ; Untyped ; +; L1_PH ; 0 ; Untyped ; +; G0_PH ; 0 ; Untyped ; +; G1_PH ; 0 ; Untyped ; +; G2_PH ; 0 ; Untyped ; +; G3_PH ; 0 ; Untyped ; +; E0_PH ; 0 ; Untyped ; +; E1_PH ; 0 ; Untyped ; +; E2_PH ; 0 ; Untyped ; +; E3_PH ; 0 ; Untyped ; +; M_PH ; 0 ; Untyped ; +; C1_USE_CASC_IN ; OFF ; Untyped ; +; C2_USE_CASC_IN ; OFF ; Untyped ; +; C3_USE_CASC_IN ; OFF ; Untyped ; +; C4_USE_CASC_IN ; OFF ; Untyped ; +; C5_USE_CASC_IN ; OFF ; Untyped ; +; C6_USE_CASC_IN ; OFF ; Untyped ; +; C7_USE_CASC_IN ; OFF ; Untyped ; +; C8_USE_CASC_IN ; OFF ; Untyped ; +; C9_USE_CASC_IN ; OFF ; Untyped ; +; CLK0_COUNTER ; G0 ; Untyped ; +; CLK1_COUNTER ; G0 ; Untyped ; +; CLK2_COUNTER ; G0 ; Untyped ; +; CLK3_COUNTER ; G0 ; Untyped ; +; CLK4_COUNTER ; G0 ; Untyped ; +; CLK5_COUNTER ; G0 ; Untyped ; +; CLK6_COUNTER ; E0 ; Untyped ; +; CLK7_COUNTER ; E1 ; Untyped ; +; CLK8_COUNTER ; E2 ; Untyped ; +; CLK9_COUNTER ; E3 ; Untyped ; +; L0_TIME_DELAY ; 0 ; Untyped ; +; L1_TIME_DELAY ; 0 ; Untyped ; +; G0_TIME_DELAY ; 0 ; Untyped ; +; G1_TIME_DELAY ; 0 ; Untyped ; +; G2_TIME_DELAY ; 0 ; Untyped ; +; G3_TIME_DELAY ; 0 ; Untyped ; +; E0_TIME_DELAY ; 0 ; Untyped ; +; E1_TIME_DELAY ; 0 ; Untyped ; +; E2_TIME_DELAY ; 0 ; Untyped ; +; E3_TIME_DELAY ; 0 ; Untyped ; +; M_TIME_DELAY ; 0 ; Untyped ; +; N_TIME_DELAY ; 0 ; Untyped ; +; EXTCLK3_COUNTER ; E3 ; Untyped ; +; EXTCLK2_COUNTER ; E2 ; Untyped ; +; EXTCLK1_COUNTER ; E1 ; Untyped ; +; EXTCLK0_COUNTER ; E0 ; Untyped ; +; ENABLE0_COUNTER ; L0 ; Untyped ; +; ENABLE1_COUNTER ; L0 ; Untyped ; +; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; +; LOOP_FILTER_R ; 1.000000 ; Untyped ; +; LOOP_FILTER_C ; 5 ; Untyped ; +; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; +; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; +; VCO_POST_SCALE ; 0 ; Untyped ; +; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; +; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; +; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; +; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK0 ; PORT_USED ; Untyped ; +; PORT_CLK1 ; PORT_UNUSED ; Untyped ; +; PORT_CLK2 ; PORT_UNUSED ; Untyped ; +; PORT_CLK3 ; PORT_UNUSED ; Untyped ; +; PORT_CLK4 ; PORT_UNUSED ; Untyped ; +; PORT_CLK5 ; PORT_UNUSED ; Untyped ; +; PORT_CLK6 ; PORT_UNUSED ; Untyped ; +; PORT_CLK7 ; PORT_UNUSED ; Untyped ; +; PORT_CLK8 ; PORT_UNUSED ; Untyped ; +; PORT_CLK9 ; PORT_UNUSED ; Untyped ; +; PORT_SCANDATA ; PORT_USED ; Untyped ; +; PORT_SCANDATAOUT ; PORT_USED ; Untyped ; +; PORT_SCANDONE ; PORT_USED ; Untyped ; +; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; +; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; +; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; +; PORT_INCLK0 ; PORT_USED ; Untyped ; +; PORT_FBIN ; PORT_UNUSED ; Untyped ; +; PORT_PLLENA ; PORT_UNUSED ; Untyped ; +; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; +; PORT_ARESET ; PORT_USED ; Untyped ; +; PORT_PFDENA ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLK ; PORT_USED ; Untyped ; +; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; +; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; +; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; +; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; +; PORT_LOCKED ; PORT_USED ; Untyped ; +; PORT_CONFIGUPDATE ; PORT_USED ; Untyped ; +; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; +; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; +; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; +; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; +; PORT_SCANCLKENA ; PORT_USED ; Untyped ; +; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; +; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; +; M_TEST_SOURCE ; 5 ; Untyped ; +; C0_TEST_SOURCE ; 5 ; Untyped ; +; C1_TEST_SOURCE ; 5 ; Untyped ; +; C2_TEST_SOURCE ; 5 ; Untyped ; +; C3_TEST_SOURCE ; 5 ; Untyped ; +; C4_TEST_SOURCE ; 5 ; Untyped ; +; C5_TEST_SOURCE ; 5 ; Untyped ; +; C6_TEST_SOURCE ; 5 ; Untyped ; +; C7_TEST_SOURCE ; 5 ; Untyped ; +; C8_TEST_SOURCE ; 5 ; Untyped ; +; C9_TEST_SOURCE ; 5 ; Untyped ; +; CBXI_PARAMETER ; altpll_c6j2 ; Untyped ; +; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; +; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; +; WIDTH_CLOCK ; 5 ; Untyped ; +; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; +; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; SCAN_CHAIN_MIF_FILE ; altpll4.mif ; Untyped ; +; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++-------------------------------+-------------------+---------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ++-----------------+-------+---------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++-----------------+-------+---------------------------------------------------------------------------------------------------------------+ +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; ++-----------------+-------+---------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; SINGLE_PORT ; Untyped ; +; WIDTH_A ; 1 ; Untyped ; +; WIDTHAD_A ; 8 ; Untyped ; +; NUMWORDS_A ; 144 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 1 ; Untyped ; +; WIDTHAD_B ; 1 ; Untyped ; +; NUMWORDS_B ; 1 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; AUTO ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; UNUSED ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; altsyncram_46r ; Untyped ; ++------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 9 ; Untyped ; +; LPM_REPRESENTATION ; SIGNED ; Untyped ; +; LPM_DIRECTION ; DEFAULT ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; REGISTERED_AT_END ; 0 ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; USE_CS_BUFFERS ; 1 ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; USE_WYS ; OFF ; Untyped ; +; STYLE ; FAST ; Untyped ; +; CBXI_PARAMETER ; add_sub_hpa ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_REPRESENTATION ; SIGNED ; Untyped ; +; LPM_DIRECTION ; DEFAULT ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; REGISTERED_AT_END ; 0 ; Untyped ; +; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; +; USE_CS_BUFFERS ; 1 ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; USE_WYS ; OFF ; Untyped ; +; STYLE ; FAST ; Untyped ; +; CBXI_PARAMETER ; add_sub_k8a ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; lpm_width ; 8 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; CHAIN_SIZE ; 8 ; Untyped ; +; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CASCADE_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; CASCADE_CHAIN_LENGTH ; 2 ; CASCADE_CHAIN_LENGTH ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; cmpr_tnd ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 144 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_30l ; Untyped ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 144 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_30l ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 6 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_qij ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 5 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_pij ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 144 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_30l ; Untyped ; ++------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 8 ; Untyped ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_9cj ; Untyped ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 5 ; Untyped ; +; LPM_DIRECTION ; DOWN ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_pij ; Untyped ; ++------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 ; ++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 3 ; Untyped ; +; LPM_DECODES ; 5 ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; CASCADE_CHAIN ; MANUAL ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; decode_2af ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ++------------------------+-------------+---------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+---------------------------------------------+ +; LPM_WIDTH ; 32 ; Signed Integer ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_FFTYPE ; DFF ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; NOTHING ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; ++------------------------+-------------+---------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +; LPM_WIDTH ; 8 ; Signed Integer ; ++----------------+-------+----------------------------------------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++----------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ++------------------------+-------------+-------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+-------------+-------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTH ; 18 ; Signed Integer ; +; LPM_DIRECTION ; UP ; Untyped ; +; LPM_MODULUS ; 0 ; Untyped ; +; LPM_AVALUE ; UNUSED ; Untyped ; +; LPM_SVALUE ; UNUSED ; Untyped ; +; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; +; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; +; CARRY_CNT_EN ; SMART ; Untyped ; +; LABWIDE_SCLR ; ON ; Untyped ; +; USE_NEW_VERSION ; TRUE ; Untyped ; +; CBXI_PARAMETER ; cntr_mph ; Untyped ; ++------------------------+-------------+-------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++---------------------------------------------------------------------------------------------------+ +; Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component ; ++------------------------+--------------+-----------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------+--------------+-----------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH ; 1 ; Signed Integer ; +; POWER_UP_HIGH ; OFF ; Untyped ; +; OE_REG ; UNUSED ; Untyped ; +; extend_oe_disable ; UNUSED ; Untyped ; +; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; ++------------------------+--------------+-----------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 12 ; Untyped ; +; LPM_WIDTHB ; 6 ; Untyped ; +; LPM_WIDTHP ; 18 ; Untyped ; +; LPM_WIDTHR ; 18 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_cat ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++-----------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ++------------------------------------------------+-------------+--------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-------------+--------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 12 ; Untyped ; +; LPM_WIDTHB ; 5 ; Untyped ; +; LPM_WIDTHP ; 17 ; Untyped ; +; LPM_WIDTHR ; 17 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_aat ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-------------+--------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; LPM_WIDTHA ; 12 ; Untyped ; +; LPM_WIDTHB ; 5 ; Untyped ; +; LPM_WIDTHP ; 17 ; Untyped ; +; LPM_WIDTHR ; 17 ; Untyped ; +; LPM_WIDTHS ; 1 ; Untyped ; +; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; +; LPM_PIPELINE ; 0 ; Untyped ; +; LATENCY ; 0 ; Untyped ; +; INPUT_A_IS_CONSTANT ; NO ; Untyped ; +; INPUT_B_IS_CONSTANT ; NO ; Untyped ; +; USE_EAB ; OFF ; Untyped ; +; MAXIMIZE_SPEED ; 5 ; Untyped ; +; DEVICE_FAMILY ; Cyclone III ; Untyped ; +; CARRY_CHAIN ; MANUAL ; Untyped ; +; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; +; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; +; CBXI_PARAMETER ; mult_aat ; Untyped ; +; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; +; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; +; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; ++------------------------------------------------+-------------+---------------------------------------------------------------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------------+ +; altpll Parameter Settings by Entity Instance ; ++-------------------------------+----------------------------------------+ +; Name ; Value ; ++-------------------------------+----------------------------------------+ +; Number of entity instances ; 4 ; +; Entity Instance ; altpll1:inst|altpll:altpll_component ; +; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30303 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; altpll3:inst13|altpll:altpll_component ; +; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30303 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; altpll2:inst12|altpll:altpll_component ; +; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 30303 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; +; Entity Instance ; altpll4:inst22|altpll:altpll_component ; +; -- OPERATION_MODE ; NORMAL ; +; -- PLL_TYPE ; AUTO ; +; -- PRIMARY_CLOCK ; INCLK0 ; +; -- INCLK0_INPUT_FREQUENCY ; 20833 ; +; -- INCLK1_INPUT_FREQUENCY ; 0 ; +; -- VCO_MULTIPLY_BY ; 0 ; +; -- VCO_DIVIDE_BY ; 0 ; ++-------------------------------+----------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------+ +; lpm_shiftreg Parameter Settings by Entity Instance ; ++----------------------------+---------------------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+---------------------------------------------------------------------------------+ +; Number of entity instances ; 11 ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 5 ; +; -- LPM_DIRECTION ; RIGHT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 5 ; +; -- LPM_DIRECTION ; RIGHT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 5 ; +; -- LPM_DIRECTION ; RIGHT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; +; -- LPM_WIDTH ; 16 ; +; -- LPM_DIRECTION ; LEFT ; ++----------------------------+---------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; dcfifo Parameter Settings by Entity Instance ; ++----------------------------+------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+------------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; +; -- FIFO Type ; Dual Clock ; +; -- LPM_WIDTH ; 128 ; +; -- LPM_NUMWORDS ; 512 ; +; -- LPM_SHOWAHEAD ; OFF ; +; -- USE_EAB ; ON ; ++----------------------------+------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------+ +; scfifo Parameter Settings by Entity Instance ; ++----------------------------+------------------------------------------------------------------+ +; Name ; Value ; ++----------------------------+------------------------------------------------------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; +; -- FIFO Type ; Single Clock ; +; -- lpm_width ; 128 ; +; -- LPM_NUMWORDS ; 128 ; +; -- LPM_SHOWAHEAD ; ON ; +; -- USE_EAB ; ON ; ++----------------------------+------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ +; Name ; Value ; ++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ +; Number of entity instances ; 10 ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 6 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 6 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 6 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 6 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 6 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 6 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 3 ; +; -- NUMWORDS_A ; 16 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 3 ; +; -- NUMWORDS_B ; 16 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 3 ; +; -- NUMWORDS_A ; 16 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 3 ; +; -- NUMWORDS_B ; 16 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 3 ; +; -- NUMWORDS_A ; 16 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 3 ; +; -- NUMWORDS_B ; 16 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; +; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; +; -- WIDTH_A ; 8 ; +; -- NUMWORDS_A ; 256 ; +; -- OUTDATA_REG_A ; CLOCK0 ; +; -- WIDTH_B ; 8 ; +; -- NUMWORDS_B ; 256 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; CLOCK1 ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; +; Entity Instance ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; +; -- OPERATION_MODE ; SINGLE_PORT ; +; -- WIDTH_A ; 1 ; +; -- NUMWORDS_A ; 144 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; AUTO ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------+ +; lpm_mult Parameter Settings by Entity Instance ; ++---------------------------------------+-----------------------------------------------------------------------------------+ +; Name ; Value ; ++---------------------------------------+-----------------------------------------------------------------------------------+ +; Number of entity instances ; 3 ; +; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; +; -- LPM_WIDTHA ; 12 ; +; -- LPM_WIDTHB ; 6 ; +; -- LPM_WIDTHP ; 18 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; +; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; +; -- LPM_WIDTHA ; 12 ; +; -- LPM_WIDTHB ; 5 ; +; -- LPM_WIDTHP ; 17 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; +; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; +; -- LPM_WIDTHA ; 12 ; +; -- LPM_WIDTHB ; 5 ; +; -- LPM_WIDTHP ; 17 ; +; -- LPM_REPRESENTATION ; UNSIGNED ; +; -- INPUT_A_IS_CONSTANT ; NO ; +; -- INPUT_B_IS_CONSTANT ; NO ; +; -- USE_EAB ; OFF ; +; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; +; -- INPUT_A_FIXED_VALUE ; Bx ; +; -- INPUT_B_FIXED_VALUE ; Bx ; ++---------------------------------------+-----------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" ; ++-------------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++-------------+--------+----------+-------------------------------------------------------------------------------------+ +; seln ; Input ; Info ; Stuck at VCC ; +; bc2 ; Input ; Info ; Stuck at VCC ; +; a9n ; Input ; Info ; Stuck at GND ; +; a8 ; Input ; Info ; Stuck at VCC ; +; da_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_a_in ; Input ; Info ; Stuck at GND ; +; io_a_out[2] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_a_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_b_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++-------------+--------+----------+-------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; gpip_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; gpip_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; iein ; Input ; Info ; Stuck at GND ; +; ieon ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tai ; Input ; Info ; Stuck at GND ; +; tao ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tbo ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; tco ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; so_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; rrn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; trn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" ; ++---------+--------+----------+------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+------------------------------------------------------------------------------------------+ +; cs2n ; Input ; Info ; Stuck at GND ; +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ctsn ; Input ; Info ; Stuck at GND ; +; dcdn ; Input ; Info ; Stuck at GND ; +; rtsn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" ; ++---------+--------+----------+----------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+----------------------------------------------------------------------------------------------+ +; cs1 ; Input ; Info ; Stuck at VCC ; +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ctsn ; Input ; Info ; Stuck at GND ; +; dcdn ; Input ; Info ; Stuck at GND ; +; rtsn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++---------+--------+----------+----------------------------------------------------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ +; icr_out[7] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; icr_out[5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; csn ; Input ; Info ; Stuck at VCC ; +; eopn ; Input ; Info ; Stuck at VCC ; +; ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ack_inn ; Input ; Info ; Stuck at VCC ; +; ack_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; atn_inn ; Input ; Info ; Stuck at VCC ; +; atn_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; req_outn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; req_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; ion_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; io_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; cdn_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; cd_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; msg_outn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; msg_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++----------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ +; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +; dden ; Input ; Info ; Stuck at GND ; ++---------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:20:37 2010 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_control.vhd + Info: Found design unit 1: WF5380_CONTROL-BEHAVIOUR + Info: Found entity 1: WF5380_CONTROL +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_pkg.vhd + Info: Found design unit 1: WF5380_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_registers.vhd + Info: Found design unit 1: WF5380_REGISTERS-BEHAVIOUR + Info: Found entity 1: WF5380_REGISTERS +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_soc_top.vhd + Info: Found design unit 1: WF5380_TOP_SOC-STRUCTURE + Info: Found entity 1: WF5380_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_top.vhd + Info: Found design unit 1: WF5380_TOP-STRUCTURE + Info: Found entity 1: WF5380_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_am_detector.vhd + Info: Found design unit 1: WF1772IP_AM_DETECTOR-BEHAVIOR + Info: Found entity 1: WF1772IP_AM_DETECTOR +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo0.vhd + Info: Found design unit 1: dcfifo0-SYN + Info: Found entity 1: dcfifo0 +Info: Found 1 design units, including 1 entities, in source file video/ddr_ctr.tdf + Info: Found entity 1: DDR_CTR +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri0.vhd + Info: Found design unit 1: lpm_bustri0-SYN + Info: Found entity 1: lpm_bustri0 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_control.vhd + Info: Found design unit 1: WF1772IP_CONTROL-BEHAVIOR + Info: Found entity 1: WF1772IP_CONTROL +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_crc_logic.vhd + Info: Found design unit 1: WF1772IP_CRC_LOGIC-BEHAVIOR + Info: Found entity 1: WF1772IP_CRC_LOGIC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_digital_pll.vhd + Info: Found design unit 1: WF1772IP_DIGITAL_PLL-BEHAVIOR + Info: Found entity 1: WF1772IP_DIGITAL_PLL +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_pkg.vhd + Info: Found design unit 1: WF1772IP_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_registers.vhd + Info: Found design unit 1: WF1772IP_REGISTERS-BEHAVIOR + Info: Found entity 1: WF1772IP_REGISTERS +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top.vhd + Info: Found design unit 1: WF1772IP_TOP-STRUCTURE + Info: Found entity 1: WF1772IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top_soc.vhd + Info: Found design unit 1: WF1772IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF1772IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_transceiver.vhd + Info: Found design unit 1: WF1772IP_TRANSCEIVER-BEHAVIOR + Info: Found entity 1: WF1772IP_TRANSCEIVER +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri5.vhd + Info: Found design unit 1: lpm_bustri5-SYN + Info: Found entity 1: lpm_bustri5 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_ctrl_status.vhd + Info: Found design unit 1: WF6850IP_CTRL_STATUS-BEHAVIOR + Info: Found entity 1: WF6850IP_CTRL_STATUS +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri7.vhd + Info: Found design unit 1: lpm_bustri7-SYN + Info: Found entity 1: lpm_bustri7 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_receive.vhd + Info: Found design unit 1: WF6850IP_RECEIVE-BEHAVIOR + Info: Found entity 1: WF6850IP_RECEIVE +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top.vhd + Info: Found design unit 1: WF6850IP_TOP-STRUCTURE + Info: Found entity 1: WF6850IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top_soc.vhd + Info: Found design unit 1: WF6850IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF6850IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_transmit.vhd + Info: Found design unit 1: WF6850IP_TRANSMIT-BEHAVIOR + Info: Found entity 1: WF6850IP_TRANSMIT +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_gpio.vhd + Info: Found design unit 1: WF68901IP_GPIO-BEHAVIOR + Info: Found entity 1: WF68901IP_GPIO +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_interrupts.vhd + Info: Found design unit 1: WF68901IP_INTERRUPTS-BEHAVIOR + Info: Found entity 1: WF68901IP_INTERRUPTS +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_pkg.vhd + Info: Found design unit 1: WF68901IP_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_timers.vhd + Info: Found design unit 1: WF68901IP_TIMERS-BEHAVIOR + Info: Found entity 1: WF68901IP_TIMERS +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top.vhd + Info: Found design unit 1: WF68901IP_TOP-STRUCTURE + Info: Found entity 1: WF68901IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top_soc.vhd + Info: Found design unit 1: WF68901IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF68901IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_ctrl.vhd + Info: Found design unit 1: WF68901IP_USART_CTRL-BEHAVIOR + Info: Found entity 1: WF68901IP_USART_CTRL +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_rx.vhd + Info: Found design unit 1: WF68901IP_USART_RX-BEHAVIOR + Info: Found entity 1: WF68901IP_USART_RX +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_top.vhd + Info: Found design unit 1: WF68901IP_USART_TOP-STRUCTURE + Info: Found entity 1: WF68901IP_USART_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_tx.vhd + Info: Found design unit 1: WF68901IP_USART_TX-BEHAVIOR + Info: Found entity 1: WF68901IP_USART_TX +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_pkg.vhd + Info: Found design unit 1: WF2149IP_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top.vhd + Info: Found design unit 1: WF2149IP_TOP-STRUCTURE + Info: Found entity 1: WF2149IP_TOP +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top_soc.vhd + Info: Found design unit 1: WF2149IP_TOP_SOC-STRUCTURE + Info: Found entity 1: WF2149IP_TOP_SOC +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_wave.vhd + Info: Found design unit 1: WF2149IP_WAVE-BEHAVIOR + Info: Found entity 1: WF2149IP_WAVE +Info: Found 2 design units, including 1 entities, in source file lpm_latch0.vhd + Info: Found design unit 1: lpm_latch0-SYN + Info: Found entity 1: lpm_latch0 +Info: Found 2 design units, including 1 entities, in source file altpll1.vhd + Info: Found design unit 1: altpll1-SYN + Info: Found entity 1: altpll1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_fifodz.vhd + Info: Found design unit 1: lpm_fifodz-SYN + Info: Found entity 1: lpm_fifoDZ +Info: Found 2 design units, including 1 entities, in source file altpll2.vhd + Info: Found design unit 1: altpll2-SYN + Info: Found entity 1: altpll2 +Info: Found 2 design units, including 1 entities, in source file altpll3.vhd + Info: Found design unit 1: altpll3-SYN + Info: Found entity 1: altpll3 +Info: Found 2 design units, including 1 entities, in source file video/altdpram0.vhd + Info: Found design unit 1: altdpram0-SYN + Info: Found entity 1: altdpram0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz2.vhd + Info: Found design unit 1: lpm_muxdz2-SYN + Info: Found entity 1: lpm_muxDZ2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz.vhd + Info: Found design unit 1: lpm_muxdz-SYN + Info: Found entity 1: lpm_muxDZ +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri3.vhd + Info: Found design unit 1: lpm_bustri3-SYN + Info: Found entity 1: lpm_bustri3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff0.vhd + Info: Found design unit 1: lpm_ff0-SYN + Info: Found entity 1: lpm_ff0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff1.vhd + Info: Found design unit 1: lpm_ff1-SYN + Info: Found entity 1: lpm_ff1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff3.vhd + Info: Found design unit 1: lpm_ff3-SYN + Info: Found entity 1: lpm_ff3 +Info: Found 1 design units, including 1 entities, in source file video/video_mod_mux_clutctr.tdf + Info: Found entity 1: VIDEO_MOD_MUX_CLUTCTR +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff2.vhd + Info: Found design unit 1: lpm_ff2-SYN + Info: Found entity 1: lpm_ff2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_fifo_dc0.vhd + Info: Found design unit 1: lpm_fifo_dc0-SYN + Info: Found entity 1: lpm_fifo_dc0 +Info: Found 1 design units, including 1 entities, in source file video/video.bdf + Info: Found entity 1: Video +Info: Found 1 design units, including 1 entities, in source file firebee1.bdf + Info: Found entity 1: firebee1 +Info: Found 2 design units, including 1 entities, in source file altpll0.vhd + Info: Found design unit 1: altpll0-SYN + Info: Found entity 1: altpll0 +Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd + Info: Found design unit 1: lpm_counter0-SYN + Info: Found entity 1: lpm_counter0 +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf.vhd + Info: Found design unit 1: FalconIO_SDCard_IDE_CF-FalconIO_SDCard_IDE_CF_architecture + Info: Found entity 1: FalconIO_SDCard_IDE_CF +Info: Found 2 design units, including 1 entities, in source file dsp/dsp.vhd + Info: Found design unit 1: DSP-DSP_architecture + Info: Found entity 1: DSP +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg0.vhd + Info: Found design unit 1: lpm_shiftreg0-SYN + Info: Found entity 1: lpm_shiftreg0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri1.vhd + Info: Found design unit 1: lpm_bustri1-SYN + Info: Found entity 1: lpm_bustri1 +Info: Found 2 design units, including 1 entities, in source file video/altdpram1.vhd + Info: Found design unit 1: altdpram1-SYN + Info: Found entity 1: altdpram1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri2.vhd + Info: Found design unit 1: lpm_bustri2-SYN + Info: Found entity 1: lpm_bustri2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri4.vhd + Info: Found design unit 1: lpm_bustri4-SYN + Info: Found entity 1: lpm_bustri4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant0.vhd + Info: Found design unit 1: lpm_constant0-SYN + Info: Found entity 1: lpm_constant0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant1.vhd + Info: Found design unit 1: lpm_constant1-SYN + Info: Found entity 1: lpm_constant1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux0.vhd + Info: Found design unit 1: lpm_mux0-SYN + Info: Found entity 1: lpm_mux0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux1.vhd + Info: Found design unit 1: lpm_mux1-SYN + Info: Found entity 1: lpm_mux1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux2.vhd + Info: Found design unit 1: lpm_mux2-SYN + Info: Found entity 1: lpm_mux2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant2.vhd + Info: Found design unit 1: lpm_constant2-SYN + Info: Found entity 1: lpm_constant2 +Info: Found 2 design units, including 1 entities, in source file video/altdpram2.vhd + Info: Found design unit 1: altdpram2-SYN + Info: Found entity 1: altdpram2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri6.vhd + Info: Found design unit 1: lpm_bustri6-SYN + Info: Found entity 1: lpm_bustri6 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux3.vhd + Info: Found design unit 1: lpm_mux3-SYN + Info: Found entity 1: lpm_mux3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux4.vhd + Info: Found design unit 1: lpm_mux4-SYN + Info: Found entity 1: lpm_mux4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant3.vhd + Info: Found design unit 1: lpm_constant3-SYN + Info: Found entity 1: lpm_constant3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg1.vhd + Info: Found design unit 1: lpm_shiftreg1-SYN + Info: Found entity 1: lpm_shiftreg1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_latch1.vhd + Info: Found design unit 1: lpm_latch1-SYN + Info: Found entity 1: lpm_latch1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_constant4.vhd + Info: Found design unit 1: lpm_constant4-SYN + Info: Found entity 1: lpm_constant4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg2.vhd + Info: Found design unit 1: lpm_shiftreg2-SYN + Info: Found entity 1: lpm_shiftreg2 +Info: Found 2 design units, including 1 entities, in source file video/lpm_compare1.vhd + Info: Found design unit 1: lpm_compare1-SYN + Info: Found entity 1: lpm_compare1 +Info: Found 1 design units, including 1 entities, in source file interrupt_handler/interrupt_handler.tdf + Info: Found entity 1: interrupt_handler +Info: Found 2 design units, including 1 entities, in source file lpm_bustri_long.vhd + Info: Found design unit 1: lpm_bustri_long-SYN + Info: Found entity 1: lpm_bustri_LONG +Info: Found 2 design units, including 1 entities, in source file lpm_bustri_byt.vhd + Info: Found design unit 1: lpm_bustri_byt-SYN + Info: Found entity 1: lpm_bustri_BYT +Info: Found 2 design units, including 1 entities, in source file lpm_bustri_word.vhd + Info: Found design unit 1: lpm_bustri_word-SYN + Info: Found entity 1: lpm_bustri_WORD +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff4.vhd + Info: Found design unit 1: lpm_ff4-SYN + Info: Found entity 1: lpm_ff4 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff5.vhd + Info: Found design unit 1: lpm_ff5-SYN + Info: Found entity 1: lpm_ff5 +Info: Found 2 design units, including 1 entities, in source file video/lpm_ff6.vhd + Info: Found design unit 1: lpm_ff6-SYN + Info: Found entity 1: lpm_ff6 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg3.vhd + Info: Found design unit 1: lpm_shiftreg3-SYN + Info: Found entity 1: lpm_shiftreg3 +Info: Found 2 design units, including 1 entities, in source file video/altddio_bidir0.vhd + Info: Found design unit 1: altddio_bidir0-SYN + Info: Found entity 1: altddio_bidir0 +Info: Found 2 design units, including 1 entities, in source file video/altddio_out0.vhd + Info: Found design unit 1: altddio_out0-SYN + Info: Found entity 1: altddio_out0 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux5.vhd + Info: Found design unit 1: lpm_mux5-SYN + Info: Found entity 1: lpm_mux5 +Info: Found 2 design units, including 1 entities, in source file video/blitter/blitter.vhd + Info: Found design unit 1: BLITTER-BLITTER_architecture + Info: Found entity 1: BLITTER +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg5.vhd + Info: Found design unit 1: lpm_shiftreg5-SYN + Info: Found entity 1: lpm_shiftreg5 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg6.vhd + Info: Found design unit 1: lpm_shiftreg6-SYN + Info: Found entity 1: lpm_shiftreg6 +Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg4.vhd + Info: Found design unit 1: lpm_shiftreg4-SYN + Info: Found entity 1: lpm_shiftreg4 +Info: Found 2 design units, including 1 entities, in source file video/altddio_out1.vhd + Info: Found design unit 1: altddio_out1-SYN + Info: Found entity 1: altddio_out1 +Info: Found 2 design units, including 1 entities, in source file video/altddio_out2.vhd + Info: Found design unit 1: altddio_out2-SYN + Info: Found entity 1: altddio_out2 +Info: Found 2 design units, including 1 entities, in source file altddio_out3.vhd + Info: Found design unit 1: altddio_out3-SYN + Info: Found entity 1: altddio_out3 +Info: Found 2 design units, including 1 entities, in source file video/lpm_mux6.vhd + Info: Found design unit 1: lpm_mux6-SYN + Info: Found entity 1: lpm_mux6 +Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf_pgk.vhd + Info: Found design unit 1: FalconIO_SDCard_IDE_CF_PKG +Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo1.vhd + Info: Found design unit 1: dcfifo1-SYN + Info: Found entity 1: dcfifo1 +Info: Found 2 design units, including 1 entities, in source file video/lpm_muxvdm.vhd + Info: Found design unit 1: lpm_muxvdm-SYN + Info: Found entity 1: lpm_muxVDM +Info: Elaborating entity "firebee1" for the top level hierarchy +Warning: Pin "TOUT0" not connected +Warning: Pin "nMASTER" not connected +Info: Elaborating entity "altpll1" for hierarchy "altpll1:inst" +Info: Elaborating entity "altpll" for hierarchy "altpll1:inst|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll1:inst|altpll:altpll_component" +Info: Instantiated megafunction "altpll1:inst|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "66" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "1" + Info: Parameter "clk0_phase_shift" = "0" + Info: Parameter "clk1_divide_by" = "900" + Info: Parameter "clk1_duty_cycle" = "50" + Info: Parameter "clk1_multiply_by" = "67" + Info: Parameter "clk1_phase_shift" = "0" + Info: Parameter "clk2_divide_by" = "90" + Info: Parameter "clk2_duty_cycle" = "50" + Info: Parameter "clk2_multiply_by" = "67" + Info: Parameter "clk2_phase_shift" = "0" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "inclk0_input_frequency" = "30303" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_USED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_UNUSED" + Info: Parameter "port_scanclkena" = "PORT_UNUSED" + Info: Parameter "port_scandata" = "PORT_UNUSED" + Info: Parameter "port_scandataout" = "PORT_UNUSED" + Info: Parameter "port_scandone" = "PORT_UNUSED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_USED" + Info: Parameter "port_clk2" = "PORT_USED" + Info: Parameter "port_clk3" = "PORT_UNUSED" + Info: Parameter "port_clk4" = "PORT_UNUSED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "self_reset_on_loss_lock" = "OFF" + Info: Parameter "width_clock" = "5" +Info: Found 1 design units, including 1 entities, in source file db/altpll_pul2.tdf + Info: Found entity 1: altpll_pul2 +Info: Elaborating entity "altpll_pul2" for hierarchy "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated" +Info: Elaborating entity "FalconIO_SDCard_IDE_CF" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden" +Warning (10036): Verilog HDL or VHDL warning at FalconIO_SDCard_IDE_CF.vhd(244): object "SCSI_CSn" assigned a value but never read +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(303): signal "nIDE_RD" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(304): signal "nIDE_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(313): signal "IDE_CF_CS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(314): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(315): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(324): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(325): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(335): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(336): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list +Critical Warning (10920): VHDL Incomplete Partial Association warning at FalconIO_SDCard_IDE_CF.vhd(928): port or argument "IO_A_OUT" has 1/8 unassociated elements +Info: Elaborating entity "dcfifo0" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF" +Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "1024" + Info: Parameter "lpm_showahead" = "OFF" + Info: Parameter "lpm_type" = "dcfifo" + Info: Parameter "lpm_width" = "8" + Info: Parameter "lpm_widthu" = "10" + Info: Parameter "lpm_widthu_r" = "8" + Info: Parameter "lpm_width_r" = "32" + Info: Parameter "overflow_checking" = "ON" + Info: Parameter "rdsync_delaypipe" = "5" + Info: Parameter "underflow_checking" = "ON" + Info: Parameter "use_eab" = "ON" + Info: Parameter "write_aclr_synch" = "OFF" + Info: Parameter "wrsync_delaypipe" = "5" +Info: Found 1 design units, including 1 entities, in source file db/dcfifo_0hh1.tdf + Info: Found entity 1: dcfifo_0hh1 +Info: Elaborating entity "dcfifo_0hh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_lfb.tdf + Info: Found entity 1: a_gray2bin_lfb +Info: Elaborating entity "a_gray2bin_lfb" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_k47.tdf + Info: Found entity 1: a_graycounter_k47 +Info: Elaborating entity "a_graycounter_k47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_fic.tdf + Info: Found entity 1: a_graycounter_fic +Info: Elaborating entity "a_graycounter_fic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bi31.tdf + Info: Found entity 1: altsyncram_bi31 +Info: Elaborating entity "altsyncram_bi31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf + Info: Found entity 1: alt_synch_pipe_ikd +Info: Elaborating entity "alt_synch_pipe_ikd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf + Info: Found entity 1: dffpipe_hd9 +Info: Elaborating entity "dffpipe_hd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf + Info: Found entity 1: dffpipe_gd9 +Info: Elaborating entity "dffpipe_gd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf + Info: Found entity 1: dffpipe_pe9 +Info: Elaborating entity "dffpipe_pe9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jkd.tdf + Info: Found entity 1: alt_synch_pipe_jkd +Info: Elaborating entity "alt_synch_pipe_jkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf + Info: Found entity 1: dffpipe_id9 +Info: Elaborating entity "dffpipe_id9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_256.tdf + Info: Found entity 1: cmpr_256 +Info: Elaborating entity "cmpr_256" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_256:rdempty_eq_comp1_lsb" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_156.tdf + Info: Found entity 1: cmpr_156 +Info: Elaborating entity "cmpr_156" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb" +Info: Found 1 design units, including 1 entities, in source file db/cntr_t2e.tdf + Info: Found entity 1: cntr_t2e +Info: Elaborating entity "cntr_t2e" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b" +Info: Found 1 design units, including 1 entities, in source file db/mux_a18.tdf + Info: Found entity 1: mux_a18 +Info: Elaborating entity "mux_a18" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux" +Info: Elaborating entity "dcfifo1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF" +Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" +Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "256" + Info: Parameter "lpm_showahead" = "OFF" + Info: Parameter "lpm_type" = "dcfifo" + Info: Parameter "lpm_width" = "32" + Info: Parameter "lpm_widthu" = "8" + Info: Parameter "lpm_widthu_r" = "10" + Info: Parameter "lpm_width_r" = "8" + Info: Parameter "overflow_checking" = "ON" + Info: Parameter "rdsync_delaypipe" = "5" + Info: Parameter "underflow_checking" = "ON" + Info: Parameter "use_eab" = "ON" + Info: Parameter "write_aclr_synch" = "OFF" + Info: Parameter "wrsync_delaypipe" = "5" +Info: Found 1 design units, including 1 entities, in source file db/dcfifo_3fh1.tdf + Info: Found entity 1: dcfifo_3fh1 +Info: Elaborating entity "dcfifo_3fh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j47.tdf + Info: Found entity 1: a_graycounter_j47 +Info: Elaborating entity "a_graycounter_j47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_gic.tdf + Info: Found entity 1: a_graycounter_gic +Info: Elaborating entity "a_graycounter_gic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ci31.tdf + Info: Found entity 1: altsyncram_ci31 +Info: Elaborating entity "altsyncram_ci31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_kkd.tdf + Info: Found entity 1: alt_synch_pipe_kkd +Info: Elaborating entity "alt_synch_pipe_kkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_jd9.tdf + Info: Found entity 1: dffpipe_jd9 +Info: Elaborating entity "dffpipe_jd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_lkd.tdf + Info: Found entity 1: alt_synch_pipe_lkd +Info: Elaborating entity "alt_synch_pipe_lkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_kd9.tdf + Info: Found entity 1: dffpipe_kd9 +Info: Elaborating entity "dffpipe_kd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15" +Info: Elaborating entity "WF1772IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" +Info: Elaborating entity "WF1772IP_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL" +Info: Elaborating entity "WF1772IP_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS" +Info: Elaborating entity "WF1772IP_DIGITAL_PLL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL" +Info: Elaborating entity "WF1772IP_AM_DETECTOR" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR" +Info: Elaborating entity "WF1772IP_CRC_LOGIC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC" +Info: Elaborating entity "WF1772IP_TRANSCEIVER" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER" +Info: Elaborating entity "WF5380_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" +Info: Elaborating entity "WF5380_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" +Info: Elaborating entity "WF5380_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL" +Info: Elaborating entity "WF6850IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" +Info: Elaborating entity "WF6850IP_CTRL_STATUS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS" +Info: Elaborating entity "WF6850IP_RECEIVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE" +Info: Elaborating entity "WF6850IP_TRANSMIT" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT" +Info: Elaborating entity "WF68901IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" +Info: Elaborating entity "WF68901IP_USART_TOP" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART" +Info: Elaborating entity "WF68901IP_USART_CTRL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL" +Info: Elaborating entity "WF68901IP_USART_RX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE" +Info: Elaborating entity "WF68901IP_USART_TX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT" +Info: Elaborating entity "WF68901IP_INTERRUPTS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS" +Info: Elaborating entity "WF68901IP_GPIO" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO" +Info: Elaborating entity "WF68901IP_TIMERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS" +Info: Elaborating entity "WF2149IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" +Info: Elaborating entity "WF2149IP_WAVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE" +Info: Elaborating entity "altpll3" for hierarchy "altpll3:inst13" +Info: Elaborating entity "altpll" for hierarchy "altpll3:inst13|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll3:inst13|altpll:altpll_component" +Info: Instantiated megafunction "altpll3:inst13|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "33" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "2" + Info: Parameter "clk0_phase_shift" = "0" + Info: Parameter "clk1_divide_by" = "33" + Info: Parameter "clk1_duty_cycle" = "50" + Info: Parameter "clk1_multiply_by" = "16" + Info: Parameter "clk1_phase_shift" = "0" + Info: Parameter "clk2_divide_by" = "33" + Info: Parameter "clk2_duty_cycle" = "50" + Info: Parameter "clk2_multiply_by" = "25" + Info: Parameter "clk2_phase_shift" = "0" + Info: Parameter "clk3_divide_by" = "11" + Info: Parameter "clk3_duty_cycle" = "50" + Info: Parameter "clk3_multiply_by" = "16" + Info: Parameter "clk3_phase_shift" = "0" + Info: Parameter "compensate_clock" = "CLK1" + Info: Parameter "inclk0_input_frequency" = "30303" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_UNUSED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_UNUSED" + Info: Parameter "port_scanclkena" = "PORT_UNUSED" + Info: Parameter "port_scandata" = "PORT_UNUSED" + Info: Parameter "port_scandataout" = "PORT_UNUSED" + Info: Parameter "port_scandone" = "PORT_UNUSED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_USED" + Info: Parameter "port_clk2" = "PORT_USED" + Info: Parameter "port_clk3" = "PORT_USED" + Info: Parameter "port_clk4" = "PORT_UNUSED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "width_clock" = "5" +Info: Found 1 design units, including 1 entities, in source file db/altpll_41p2.tdf + Info: Found entity 1: altpll_41p2 +Info: Elaborating entity "altpll_41p2" for hierarchy "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated" +Info: Elaborating entity "Video" for hierarchy "Video:Fredi_Aschwanden" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ADR[31..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "MAIN_CLK" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS1" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS2" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS3" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_WR" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE0" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE1" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nRSTO" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_OE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ALE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDRCLK[3..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDR_SYNC_66M" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK33M" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK25M" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK_VIDEO" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_D[8..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_BUSY" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VG[7..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VB[7..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR[7..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nBLANK" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VA[12..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVWE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCAS" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVRAS" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCS" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDM[3..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nPD_VGA" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VCKE" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VSYNC" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "HSYNC" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nSYNC" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_TA" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "PIXEL_CLK" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "BA[1..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_RECONFIG" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_WR" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_RD" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDQS[3..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_AD[31..0]" +Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VD[31..0]" +Info: Elaborating entity "VIDEO_MOD_MUX_CLUTCTR" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR" +Warning: Variable or input pin "nRSTO" is defined but never used +Warning: Variable or input pin "nFB_CS3" is defined but never used +Warning: Variable or input pin "nFB_BURST" is defined but never used +Info: Elaborating entity "lpm_bustri_WORD" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "16" +Info: Elaborating entity "BLITTER" for hierarchy "Video:Fredi_Aschwanden|BLITTER:BLITTER" +Info: Elaborating entity "lpm_shiftreg6" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89" +Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: + Info: Parameter "lpm_direction" = "RIGHT" + Info: Parameter "lpm_type" = "LPM_SHIFTREG" + Info: Parameter "lpm_width" = "5" +Info: Elaborating entity "DDR_CTR" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR" +Warning: Variable or input pin "nFB_CS2" is defined but never used +Warning: Variable or input pin "nFB_CS3" is defined but never used +Warning: Variable or input pin "nRSTO" is defined but never used +Info: Elaborating entity "lpm_bustri_BYT" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "8" +Info: Elaborating entity "lpm_fifo_dc0" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst" +Info: Elaborating entity "dcfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" with the following parameter: + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "512" + Info: Parameter "lpm_showahead" = "OFF" + Info: Parameter "lpm_type" = "dcfifo" + Info: Parameter "lpm_width" = "128" + Info: Parameter "lpm_widthu" = "9" + Info: Parameter "overflow_checking" = "OFF" + Info: Parameter "rdsync_delaypipe" = "6" + Info: Parameter "underflow_checking" = "OFF" + Info: Parameter "use_eab" = "ON" + Info: Parameter "write_aclr_synch" = "ON" + Info: Parameter "wrsync_delaypipe" = "6" +Info: Found 1 design units, including 1 entities, in source file db/dcfifo_8fi1.tdf + Info: Found entity 1: dcfifo_8fi1 +Info: Elaborating entity "dcfifo_8fi1" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf + Info: Found entity 1: a_gray2bin_tgb +Info: Elaborating entity "a_gray2bin_tgb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf + Info: Found entity 1: a_graycounter_s57 +Info: Elaborating entity "a_graycounter_s57" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf + Info: Found entity 1: a_graycounter_ojc +Info: Elaborating entity "a_graycounter_ojc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p" +Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_njc.tdf + Info: Found entity 1: a_graycounter_njc +Info: Elaborating entity "a_graycounter_njc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tl31.tdf + Info: Found entity 1: altsyncram_tl31 +Info: Elaborating entity "altsyncram_tl31" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf + Info: Found entity 1: alt_synch_pipe_rld +Info: Elaborating entity "alt_synch_pipe_rld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf + Info: Found entity 1: dffpipe_qe9 +Info: Elaborating entity "dffpipe_qe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_9d9.tdf + Info: Found entity 1: dffpipe_9d9 +Info: Elaborating entity "dffpipe_9d9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf + Info: Found entity 1: dffpipe_oe9 +Info: Elaborating entity "dffpipe_oe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp" +Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf + Info: Found entity 1: alt_synch_pipe_sld +Info: Elaborating entity "alt_synch_pipe_sld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp" +Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf + Info: Found entity 1: dffpipe_re9 +Info: Elaborating entity "dffpipe_re9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22" +Info: Elaborating entity "lpm_shiftreg4" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26" +Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: + Info: Parameter "lpm_direction" = "RIGHT" + Info: Parameter "lpm_type" = "LPM_SHIFTREG" + Info: Parameter "lpm_width" = "5" +Info: Elaborating entity "lpm_muxVDM" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "128" + Info: Parameter "LPM_SIZE" = "16" + Info: Parameter "LPM_WIDTHS" = "4" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_bbe.tdf + Info: Found entity 1: mux_bbe +Info: Elaborating entity "mux_bbe" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component|mux_bbe:auto_generated" +Info: Elaborating entity "lpm_ff6" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "128" +Info: Elaborating entity "lpm_ff1" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "altddio_bidir0" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1" +Info: Elaborating entity "altddio_bidir" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "implement_input_in_lcell" = "ON" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "OFF" + Info: Parameter "lpm_type" = "altddio_bidir" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "OFF" + Info: Parameter "width" = "32" +Info: Found 1 design units, including 1 entities, in source file db/ddio_bidir_3jl.tdf + Info: Found entity 1: ddio_bidir_3jl +Info: Elaborating entity "ddio_bidir_3jl" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated" +Info: Elaborating entity "lpm_mux5" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "64" + Info: Parameter "LPM_SIZE" = "4" + Info: Parameter "LPM_WIDTHS" = "2" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_58e.tdf + Info: Found entity 1: mux_58e +Info: Elaborating entity "mux_58e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component|mux_58e:auto_generated" +Info: Elaborating entity "lpm_ff0" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "lpm_bustri_LONG" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "lpm_latch0" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27" +Info: Elaborating entity "lpm_latch" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_LATCH" + Info: Parameter "lpm_width" = "32" +Info: Elaborating entity "lpm_bustri3" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "6" +Info: Elaborating entity "altdpram1" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED" +Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" with the following parameter: + Info: Parameter "address_reg_b" = "CLOCK1" + Info: Parameter "clock_enable_input_a" = "BYPASS" + Info: Parameter "clock_enable_input_b" = "BYPASS" + Info: Parameter "clock_enable_output_a" = "BYPASS" + Info: Parameter "clock_enable_output_b" = "BYPASS" + Info: Parameter "indata_reg_b" = "CLOCK1" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altsyncram" + Info: Parameter "numwords_a" = "256" + Info: Parameter "numwords_b" = "256" + Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info: Parameter "outdata_aclr_a" = "NONE" + Info: Parameter "outdata_aclr_b" = "NONE" + Info: Parameter "outdata_reg_a" = "CLOCK0" + Info: Parameter "outdata_reg_b" = "CLOCK1" + Info: Parameter "power_up_uninitialized" = "FALSE" + Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" + Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" + Info: Parameter "widthad_a" = "8" + Info: Parameter "widthad_b" = "8" + Info: Parameter "width_a" = "6" + Info: Parameter "width_b" = "6" + Info: Parameter "width_byteena_a" = "1" + Info: Parameter "width_byteena_b" = "1" + Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lf92.tdf + Info: Found entity 1: altsyncram_lf92 +Info: Elaborating entity "altsyncram_lf92" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated" +Info: Elaborating entity "lpm_shiftreg0" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0" +Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: + Info: Parameter "lpm_direction" = "LEFT" + Info: Parameter "lpm_type" = "LPM_SHIFTREG" + Info: Parameter "lpm_width" = "16" +Info: Elaborating entity "MUX41" for hierarchy "Video:Fredi_Aschwanden|MUX41:inst45" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|MUX41:inst45" +Info: Elaborating entity "lpm_muxDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "128" + Info: Parameter "LPM_SIZE" = "2" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_PIPELINE" = "1" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_dcf.tdf + Info: Found entity 1: mux_dcf +Info: Elaborating entity "mux_dcf" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component|mux_dcf:auto_generated" +Info: Elaborating entity "lpm_fifoDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63" +Info: Elaborating entity "scfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" with the following parameter: + Info: Parameter "add_ram_output_register" = "OFF" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_numwords" = "128" + Info: Parameter "lpm_showahead" = "ON" + Info: Parameter "lpm_type" = "scfifo" + Info: Parameter "lpm_width" = "128" + Info: Parameter "lpm_widthu" = "7" + Info: Parameter "overflow_checking" = "OFF" + Info: Parameter "underflow_checking" = "OFF" + Info: Parameter "use_eab" = "ON" +Info: Found 1 design units, including 1 entities, in source file db/scfifo_lk21.tdf + Info: Found entity 1: scfifo_lk21 +Info: Elaborating entity "scfifo_lk21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated" +Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_oq21.tdf + Info: Found entity 1: a_dpfifo_oq21 +Info: Elaborating entity "a_dpfifo_oq21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gj81.tdf + Info: Found entity 1: altsyncram_gj81 +Info: Elaborating entity "altsyncram_gj81" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_br8.tdf + Info: Found entity 1: cmpr_br8 +Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:almost_full_comparer" +Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:three_comparison" +Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf + Info: Found entity 1: cntr_omb +Info: Elaborating entity "cntr_omb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb" +Info: Found 1 design units, including 1 entities, in source file db/cntr_5n7.tdf + Info: Found entity 1: cntr_5n7 +Info: Elaborating entity "cntr_5n7" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter" +Info: Found 1 design units, including 1 entities, in source file db/cntr_pmb.tdf + Info: Found entity 1: cntr_pmb +Info: Elaborating entity "cntr_pmb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr" +Info: Elaborating entity "lpm_bustri1" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51" +Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" with the following parameter: + Info: Parameter "lpm_type" = "LPM_BUSTRI" + Info: Parameter "lpm_width" = "3" +Info: Elaborating entity "altdpram0" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED" +Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" with the following parameter: + Info: Parameter "address_reg_b" = "CLOCK1" + Info: Parameter "clock_enable_input_a" = "BYPASS" + Info: Parameter "clock_enable_input_b" = "BYPASS" + Info: Parameter "clock_enable_output_a" = "BYPASS" + Info: Parameter "clock_enable_output_b" = "BYPASS" + Info: Parameter "indata_reg_b" = "CLOCK1" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altsyncram" + Info: Parameter "numwords_a" = "16" + Info: Parameter "numwords_b" = "16" + Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info: Parameter "outdata_aclr_a" = "NONE" + Info: Parameter "outdata_aclr_b" = "NONE" + Info: Parameter "outdata_reg_a" = "CLOCK0" + Info: Parameter "outdata_reg_b" = "CLOCK1" + Info: Parameter "power_up_uninitialized" = "FALSE" + Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" + Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" + Info: Parameter "widthad_a" = "4" + Info: Parameter "widthad_b" = "4" + Info: Parameter "width_a" = "3" + Info: Parameter "width_b" = "3" + Info: Parameter "width_byteena_a" = "1" + Info: Parameter "width_byteena_b" = "1" + Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rb92.tdf + Info: Found entity 1: altsyncram_rb92 +Info: Elaborating entity "altsyncram_rb92" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated" +Info: Elaborating entity "altdpram2" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55" +Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" with the following parameter: + Info: Parameter "address_reg_b" = "CLOCK1" + Info: Parameter "clock_enable_input_a" = "BYPASS" + Info: Parameter "clock_enable_input_b" = "BYPASS" + Info: Parameter "clock_enable_output_a" = "BYPASS" + Info: Parameter "clock_enable_output_b" = "BYPASS" + Info: Parameter "indata_reg_b" = "CLOCK1" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altsyncram" + Info: Parameter "numwords_a" = "256" + Info: Parameter "numwords_b" = "256" + Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" + Info: Parameter "outdata_aclr_a" = "NONE" + Info: Parameter "outdata_aclr_b" = "NONE" + Info: Parameter "outdata_reg_a" = "CLOCK0" + Info: Parameter "outdata_reg_b" = "CLOCK1" + Info: Parameter "power_up_uninitialized" = "FALSE" + Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" + Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" + Info: Parameter "widthad_a" = "8" + Info: Parameter "widthad_b" = "8" + Info: Parameter "width_a" = "8" + Info: Parameter "width_b" = "8" + Info: Parameter "width_byteena_a" = "1" + Info: Parameter "width_byteena_b" = "1" + Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pf92.tdf + Info: Found entity 1: altsyncram_pf92 +Info: Elaborating entity "altsyncram_pf92" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated" +Info: Elaborating entity "lpm_mux3" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "1" + Info: Parameter "LPM_SIZE" = "2" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_96e.tdf + Info: Found entity 1: mux_96e +Info: Elaborating entity "mux_96e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component|mux_96e:auto_generated" +Info: Elaborating entity "lpm_ff5" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "8" +Info: Elaborating entity "lpm_mux2" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" + Info: Parameter "LPM_SIZE" = "16" + Info: Parameter "LPM_WIDTHS" = "4" + Info: Parameter "LPM_PIPELINE" = "2" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_mpe.tdf + Info: Found entity 1: mux_mpe +Info: Elaborating entity "mux_mpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component|mux_mpe:auto_generated" +Info: Elaborating entity "lpm_mux4" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "7" + Info: Parameter "LPM_SIZE" = "2" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_PIPELINE" = "0" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_f6e.tdf + Info: Found entity 1: mux_f6e +Info: Elaborating entity "mux_f6e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component|mux_f6e:auto_generated" +Info: Elaborating entity "lpm_constant3" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "7" +Info: Elaborating entity "altddio_out2" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5" +Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "OFF" + Info: Parameter "lpm_type" = "altddio_out" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "OFF" + Info: Parameter "width" = "24" +Info: Found 1 design units, including 1 entities, in source file db/ddio_out_o2f.tdf + Info: Found entity 1: ddio_out_o2f +Info: Elaborating entity "ddio_out_o2f" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated" +Info: Elaborating entity "lpm_mux6" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "24" + Info: Parameter "LPM_SIZE" = "8" + Info: Parameter "LPM_WIDTHS" = "3" + Info: Parameter "LPM_PIPELINE" = "2" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_kpe.tdf + Info: Found entity 1: mux_kpe +Info: Elaborating entity "mux_kpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component|mux_kpe:auto_generated" +Info: Elaborating entity "lpm_ff3" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "24" +Info: Elaborating entity "lpm_constant0" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "5" +Info: Elaborating entity "lpm_constant1" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "2" +Info: Elaborating entity "lpm_ff4" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10" +Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" with the following parameter: + Info: Parameter "lpm_fftype" = "DFF" + Info: Parameter "lpm_type" = "LPM_FF" + Info: Parameter "lpm_width" = "16" +Info: Elaborating entity "lpm_mux1" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" +Info: Assertion information: Value of LPM_PIPELINE parameter (4) should be lower -- use 1 for best performance/utilization +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "16" + Info: Parameter "LPM_SIZE" = "8" + Info: Parameter "LPM_WIDTHS" = "3" + Info: Parameter "LPM_PIPELINE" = "4" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Assertion information: Value of LPM_PIPELINE parameter 4 should be lower -- use 1 for best performance/utilization +Info: Found 1 design units, including 1 entities, in source file db/mux_npe.tdf + Info: Found entity 1: mux_npe +Info: Elaborating entity "mux_npe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component|mux_npe:auto_generated" +Info: Elaborating entity "lpm_constant2" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23" +Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" with the following parameter: + Info: Parameter "lpm_cvalue" = "0" + Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" + Info: Parameter "lpm_type" = "LPM_CONSTANT" + Info: Parameter "lpm_width" = "8" +Info: Elaborating entity "lpm_mux0" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21" +Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" with the following parameter: + Info: Parameter "LPM_WIDTH" = "32" + Info: Parameter "LPM_SIZE" = "4" + Info: Parameter "LPM_WIDTHS" = "2" + Info: Parameter "LPM_PIPELINE" = "4" + Info: Parameter "LPM_TYPE" = "LPM_MUX" + Info: Parameter "LPM_HINT" = "UNUSED" +Info: Found 1 design units, including 1 entities, in source file db/mux_gpe.tdf + Info: Found entity 1: mux_gpe +Info: Elaborating entity "mux_gpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component|mux_gpe:auto_generated" +Info: Elaborating entity "altddio_out0" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2" +Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "ON" + Info: Parameter "lpm_type" = "altddio_out" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "ON" + Info: Parameter "width" = "4" +Info: Found 1 design units, including 1 entities, in source file db/ddio_out_are.tdf + Info: Found entity 1: ddio_out_are +Info: Elaborating entity "ddio_out_are" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated" +Info: Elaborating entity "altpll2" for hierarchy "altpll2:inst12" +Info: Elaborating entity "altpll" for hierarchy "altpll2:inst12|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll2:inst12|altpll:altpll_component" +Info: Instantiated megafunction "altpll2:inst12|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "1" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "4" + Info: Parameter "clk0_phase_shift" = "5051" + Info: Parameter "clk1_divide_by" = "1" + Info: Parameter "clk1_duty_cycle" = "50" + Info: Parameter "clk1_multiply_by" = "4" + Info: Parameter "clk1_phase_shift" = "0" + Info: Parameter "clk2_divide_by" = "1" + Info: Parameter "clk2_duty_cycle" = "50" + Info: Parameter "clk2_multiply_by" = "4" + Info: Parameter "clk2_phase_shift" = "3788" + Info: Parameter "clk3_divide_by" = "1" + Info: Parameter "clk3_duty_cycle" = "50" + Info: Parameter "clk3_multiply_by" = "4" + Info: Parameter "clk3_phase_shift" = "2210" + Info: Parameter "clk4_divide_by" = "1" + Info: Parameter "clk4_duty_cycle" = "50" + Info: Parameter "clk4_multiply_by" = "2" + Info: Parameter "clk4_phase_shift" = "11364" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "inclk0_input_frequency" = "30303" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_UNUSED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_UNUSED" + Info: Parameter "port_scanclkena" = "PORT_UNUSED" + Info: Parameter "port_scandata" = "PORT_UNUSED" + Info: Parameter "port_scandataout" = "PORT_UNUSED" + Info: Parameter "port_scandone" = "PORT_UNUSED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_USED" + Info: Parameter "port_clk2" = "PORT_USED" + Info: Parameter "port_clk3" = "PORT_USED" + Info: Parameter "port_clk4" = "PORT_USED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "width_clock" = "5" +Info: Found 1 design units, including 1 entities, in source file db/altpll_isv2.tdf + Info: Found entity 1: altpll_isv2 +Info: Elaborating entity "altpll_isv2" for hierarchy "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated" +Warning: Using design file altpll4.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: altpll4 +Info: Elaborating entity "altpll4" for hierarchy "altpll4:inst22" +Info: Elaborating entity "altpll" for hierarchy "altpll4:inst22|altpll:altpll_component" +Info: Elaborated megafunction instantiation "altpll4:inst22|altpll:altpll_component" +Info: Instantiated megafunction "altpll4:inst22|altpll:altpll_component" with the following parameter: + Info: Parameter "bandwidth_type" = "AUTO" + Info: Parameter "clk0_divide_by" = "1" + Info: Parameter "clk0_duty_cycle" = "50" + Info: Parameter "clk0_multiply_by" = "2" + Info: Parameter "clk0_phase_shift" = "0" + Info: Parameter "compensate_clock" = "CLK0" + Info: Parameter "inclk0_input_frequency" = "20833" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "lpm_type" = "altpll" + Info: Parameter "operation_mode" = "NORMAL" + Info: Parameter "pll_type" = "AUTO" + Info: Parameter "port_activeclock" = "PORT_UNUSED" + Info: Parameter "port_areset" = "PORT_USED" + Info: Parameter "port_clk0" = "PORT_USED" + Info: Parameter "port_clk1" = "PORT_UNUSED" + Info: Parameter "port_clk2" = "PORT_UNUSED" + Info: Parameter "port_clk3" = "PORT_UNUSED" + Info: Parameter "port_clk4" = "PORT_UNUSED" + Info: Parameter "port_clk5" = "PORT_UNUSED" + Info: Parameter "port_clkbad0" = "PORT_UNUSED" + Info: Parameter "port_clkbad1" = "PORT_UNUSED" + Info: Parameter "port_clkena0" = "PORT_UNUSED" + Info: Parameter "port_clkena1" = "PORT_UNUSED" + Info: Parameter "port_clkena2" = "PORT_UNUSED" + Info: Parameter "port_clkena3" = "PORT_UNUSED" + Info: Parameter "port_clkena4" = "PORT_UNUSED" + Info: Parameter "port_clkena5" = "PORT_UNUSED" + Info: Parameter "port_clkloss" = "PORT_UNUSED" + Info: Parameter "port_clkswitch" = "PORT_UNUSED" + Info: Parameter "port_configupdate" = "PORT_USED" + Info: Parameter "port_extclk0" = "PORT_UNUSED" + Info: Parameter "port_extclk1" = "PORT_UNUSED" + Info: Parameter "port_extclk2" = "PORT_UNUSED" + Info: Parameter "port_extclk3" = "PORT_UNUSED" + Info: Parameter "port_fbin" = "PORT_UNUSED" + Info: Parameter "port_inclk0" = "PORT_USED" + Info: Parameter "port_inclk1" = "PORT_UNUSED" + Info: Parameter "port_locked" = "PORT_USED" + Info: Parameter "port_pfdena" = "PORT_UNUSED" + Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" + Info: Parameter "port_phasedone" = "PORT_UNUSED" + Info: Parameter "port_phasestep" = "PORT_UNUSED" + Info: Parameter "port_phaseupdown" = "PORT_UNUSED" + Info: Parameter "port_pllena" = "PORT_UNUSED" + Info: Parameter "port_scanaclr" = "PORT_UNUSED" + Info: Parameter "port_scanclk" = "PORT_USED" + Info: Parameter "port_scanclkena" = "PORT_USED" + Info: Parameter "port_scandata" = "PORT_USED" + Info: Parameter "port_scandataout" = "PORT_USED" + Info: Parameter "port_scandone" = "PORT_USED" + Info: Parameter "port_scanread" = "PORT_UNUSED" + Info: Parameter "port_scanwrite" = "PORT_UNUSED" + Info: Parameter "scan_chain_mif_file" = "altpll4.mif" + Info: Parameter "self_reset_on_loss_lock" = "OFF" + Info: Parameter "width_clock" = "5" + Info: Parameter "width_phasecounterselect" = "4" +Info: Found 1 design units, including 1 entities, in source file db/altpll_c6j2.tdf + Info: Found entity 1: altpll_c6j2 +Info: Elaborating entity "altpll_c6j2" for hierarchy "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated" +Warning: Using design file altpll_reconfig1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: altpll_reconfig1 +Info: Elaborating entity "altpll_reconfig1" for hierarchy "altpll_reconfig1:inst7" +Warning: Using design file altpll_reconfig1_pllrcfg_t4q.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project + Info: Found entity 1: altpll_reconfig1_pllrcfg_t4q +Info: Elaborating entity "altpll_reconfig1_pllrcfg_t4q" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component" +Info: Elaborating entity "altsyncram" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" with the following parameter: + Info: Parameter "OPERATION_MODE" = "SINGLE_PORT" + Info: Parameter "WIDTH_A" = "1" + Info: Parameter "WIDTHAD_A" = "8" + Info: Parameter "NUMWORDS_A" = "144" + Info: Parameter "WIDTH_BYTEENA_A" = "1" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_46r.tdf + Info: Found entity 1: altsyncram_46r +Info: Elaborating entity "altsyncram_46r" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated" +Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" with the following parameter: + Info: Parameter "LPM_WIDTH" = "9" +Info: Found 1 design units, including 1 entities, in source file db/add_sub_hpa.tdf + Info: Found entity 1: add_sub_hpa +Info: Elaborating entity "add_sub_hpa" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5|add_sub_hpa:auto_generated" +Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/add_sub_k8a.tdf + Info: Found entity 1: add_sub_k8a +Info: Elaborating entity "add_sub_k8a" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6|add_sub_k8a:auto_generated" +Info: Elaborating entity "lpm_compare" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" with the following parameter: + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/cmpr_tnd.tdf + Info: Found entity 1: cmpr_tnd +Info: Elaborating entity "cmpr_tnd" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "DOWN" + Info: Parameter "lpm_modulus" = "144" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/cntr_30l.tdf + Info: Found entity 1: cntr_30l +Info: Elaborating entity "cntr_30l" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "DOWN" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "6" +Info: Found 1 design units, including 1 entities, in source file db/cntr_qij.tdf + Info: Found entity 1: cntr_qij +Info: Elaborating entity "cntr_qij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "DOWN" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "5" +Info: Found 1 design units, including 1 entities, in source file db/cntr_pij.tdf + Info: Found entity 1: cntr_pij +Info: Elaborating entity "cntr_pij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated" +Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" with the following parameter: + Info: Parameter "LPM_DIRECTION" = "UP" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "LPM_WIDTH" = "8" +Info: Found 1 design units, including 1 entities, in source file db/cntr_9cj.tdf + Info: Found entity 1: cntr_9cj +Info: Elaborating entity "cntr_9cj" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated" +Info: Elaborating entity "lpm_decode" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" +Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" +Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" with the following parameter: + Info: Parameter "LPM_DECODES" = "5" + Info: Parameter "LPM_WIDTH" = "3" +Info: Found 1 design units, including 1 entities, in source file db/decode_2af.tdf + Info: Found entity 1: decode_2af +Info: Elaborating entity "decode_2af" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11|decode_2af:auto_generated" +Info: Elaborating entity "DSP" for hierarchy "DSP:Mathias_Alles" +Info: Elaborating entity "interrupt_handler" for hierarchy "interrupt_handler:nobody" +Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst18" +Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component" +Info: Elaborated megafunction instantiation "lpm_counter0:inst18|lpm_counter:lpm_counter_component" +Info: Instantiated megafunction "lpm_counter0:inst18|lpm_counter:lpm_counter_component" with the following parameter: + Info: Parameter "lpm_direction" = "UP" + Info: Parameter "lpm_port_updown" = "PORT_UNUSED" + Info: Parameter "lpm_type" = "LPM_COUNTER" + Info: Parameter "lpm_width" = "18" +Info: Found 1 design units, including 1 entities, in source file db/cntr_mph.tdf + Info: Found entity 1: cntr_mph +Info: Elaborating entity "cntr_mph" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated" +Info: Elaborating entity "altddio_out3" for hierarchy "altddio_out3:inst5" +Info: Elaborating entity "altddio_out" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component" +Info: Elaborated megafunction instantiation "altddio_out3:inst5|altddio_out:altddio_out_component" +Info: Instantiated megafunction "altddio_out3:inst5|altddio_out:altddio_out_component" with the following parameter: + Info: Parameter "extend_oe_disable" = "UNUSED" + Info: Parameter "intended_device_family" = "Cyclone III" + Info: Parameter "invert_output" = "OFF" + Info: Parameter "lpm_type" = "altddio_out" + Info: Parameter "oe_reg" = "UNUSED" + Info: Parameter "power_up_high" = "OFF" + Info: Parameter "width" = "1" +Info: Found 1 design units, including 1 entities, in source file db/ddio_out_31f.tdf + Info: Found entity 1: ddio_out_31f +Info: Elaborating entity "ddio_out_31f" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated" +Warning: Timing-Driven Synthesis is skipped because the Classic Timing Analyzer is turned on +Info: Inferred 3 megafunctions from design logic + Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_14" + Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_6" + Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_12" +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" with the following parameter: + Info: Parameter "LPM_WIDTHA" = "12" + Info: Parameter "LPM_WIDTHB" = "6" + Info: Parameter "LPM_WIDTHP" = "18" + Info: Parameter "LPM_WIDTHR" = "18" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info: Parameter "INPUT_A_IS_CONSTANT" = "NO" + Info: Parameter "INPUT_B_IS_CONSTANT" = "NO" + Info: Parameter "MAXIMIZE_SPEED" = "5" +Info: Found 1 design units, including 1 entities, in source file db/mult_cat.tdf + Info: Found entity 1: mult_cat +Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" +Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" with the following parameter: + Info: Parameter "LPM_WIDTHA" = "12" + Info: Parameter "LPM_WIDTHB" = "5" + Info: Parameter "LPM_WIDTHP" = "17" + Info: Parameter "LPM_WIDTHR" = "17" + Info: Parameter "LPM_WIDTHS" = "1" + Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" + Info: Parameter "INPUT_A_IS_CONSTANT" = "NO" + Info: Parameter "INPUT_B_IS_CONSTANT" = "NO" + Info: Parameter "MAXIMIZE_SPEED" = "5" +Info: Found 1 design units, including 1 entities, in source file db/mult_aat.tdf + Info: Found entity 1: mult_aat +Warning: The following nodes have both tri-state and non-tri-state drivers + Warning: Inserted always-enabled tri-state buffer between "IO[17]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[16]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[15]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[14]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[13]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[12]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[11]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[10]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[9]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[8]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[7]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[6]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[5]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[4]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[3]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[2]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[1]" and its non-tri-state driver. + Warning: Inserted always-enabled tri-state buffer between "IO[0]" and its non-tri-state driver. +Info: Registers with preset signals will power-up high +Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back +Warning: TRI or OPNDRN buffers permanently disabled + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_PAR~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_RST~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[7]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[6]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[5]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[4]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[3]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[2]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[1]~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[0]~synth" +Warning: TRI or OPNDRN buffers permanently enabled + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "IO~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_SEL~synth" + Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_BUSY~synth" +Warning: Output pins are stuck at VCC or GND + Warning (13410): Pin "nACSI_ACK" is stuck at VCC + Warning (13410): Pin "nACSI_CS" is stuck at VCC + Warning (13410): Pin "ACSI_DIR" is stuck at GND + Warning (13410): Pin "nSCSI_ACK" is stuck at VCC + Warning (13410): Pin "nSCSI_ATN" is stuck at VCC + Warning (13410): Pin "SCSI_DIR" is stuck at VCC + Warning (13410): Pin "nSYNC" is stuck at GND +Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below. + Info: Register "interrupt_handler:nobody|INT_CLEAR[31]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[30]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[29]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[28]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[27]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[26]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[25]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[24]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[23]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[22]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[21]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[20]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[19]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[18]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[17]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[16]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[15]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[14]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[13]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[12]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[11]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[10]" lost all its fanouts during netlist optimizations. + Info: Register "interrupt_handler:nobody|INT_CLEAR[7]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[6]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[5]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[4]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[3]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[2]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[1]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[5]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[4]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[3]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[2]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[1]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[7]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[6]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[5]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[4]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[3]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[2]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[1]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[2]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[1]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[7]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]" lost all its fanouts during netlist optimizations. + Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" lost all its fanouts during netlist optimizations. + Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]" lost all its fanouts during netlist optimizations. +Info: Found the following redundant logic cells in design + Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[0]" + Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[1]" + Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[2]" +Warning: Design contains 18 input pin(s) that do not drive logic + Warning (15610): No output dependent on input pin "nFB_BURST" + Warning (15610): No output dependent on input pin "nACSI_DRQ" + Warning (15610): No output dependent on input pin "nACSI_INT" + Warning (15610): No output dependent on input pin "nSCSI_DRQ" + Warning (15610): No output dependent on input pin "nSCSI_MSG" + Warning (15610): No output dependent on input pin "nDCHG" + Warning (15610): No output dependent on input pin "SD_DATA0" + Warning (15610): No output dependent on input pin "SD_DATA1" + Warning (15610): No output dependent on input pin "SD_DATA2" + Warning (15610): No output dependent on input pin "SD_CARD_DEDECT" + Warning (15610): No output dependent on input pin "SD_WP" + Warning (15610): No output dependent on input pin "nDACK0" + Warning (15610): No output dependent on input pin "WP_CF_CARD" + Warning (15610): No output dependent on input pin "nSCSI_C_D" + Warning (15610): No output dependent on input pin "nSCSI_I_O" + Warning (15610): No output dependent on input pin "nFB_CS3" + Warning (15610): No output dependent on input pin "TOUT0" + Warning (15610): No output dependent on input pin "nMASTER" +Info: Implemented 11489 device resources after synthesis - the final resource count might be different + Info: Implemented 51 input pins + Info: Implemented 112 output pins + Info: Implemented 132 bidirectional pins + Info: Implemented 10796 logic cells + Info: Implemented 324 RAM segments + Info: Implemented 4 PLLs + Info: Implemented 6 DSP elements +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 143 warnings + Info: Peak virtual memory: 347 megabytes + Info: Processing ended: Wed Dec 15 02:21:56 2010 + Info: Elapsed time: 00:01:19 + Info: Total CPU time (on all processors): 00:01:20 + + diff --git a/FPGA_Quartus_13.1/firebee1.map.summary b/FPGA_Quartus_13.1/firebee1.map.summary new file mode 100644 index 0000000..f8da91e --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010 +Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +Revision Name : firebee1 +Top-level Entity Name : firebee1 +Family : Cyclone III +Total logic elements : 10,706 + Total combinational functions : 8,060 + Dedicated logic registers : 4,612 +Total registers : 4740 +Total pins : 295 +Total virtual pins : 0 +Total memory bits : 109,344 +Embedded Multiplier 9-bit elements : 6 +Total PLLs : 4 diff --git a/FPGA_Quartus_13.1/firebee1.pin b/FPGA_Quartus_13.1/firebee1.pin new file mode 100644 index 0000000..50b8dd7 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.pin @@ -0,0 +1,557 @@ + -- Copyright (C) 1991-2010 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 2.5V + -- Bank 5: 2.5V + -- Bank 6: 3.0V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +CHIP "firebee1" ASSIGNED TO AN: EP3C40F484C6 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO8 : A2 : power : : 3.3V : 8 : +LP_D[6] : A3 : bidir : 3.3-V LVTTL : : 8 : Y +nSRBLE : A4 : output : 3.3-V LVTTL : : 8 : Y +SRD[1] : A5 : bidir : 3.3-V LVTTL : : 8 : Y +IO[3] : A6 : bidir : 3.3-V LVTTL : : 8 : Y +IO[1] : A7 : bidir : 3.3-V LVTTL : : 8 : Y +IO[0] : A8 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[10] : A9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[9] : A10 : bidir : 3.3-V LVTTL : : 8 : Y +DVI_INT : A11 : input : 3.3-V LVTTL : : 8 : Y +nDACK1 : A12 : input : 3.3-V LVTTL : : 7 : Y +IO[16] : A13 : bidir : 3.3-V LVTTL : : 7 : Y +IO[14] : A14 : bidir : 3.3-V LVTTL : : 7 : Y +IO[9] : A15 : bidir : 3.3-V LVTTL : : 7 : Y +SD_DATA1 : A16 : input : 3.3-V LVTTL : : 7 : Y +YM_QA : A17 : output : 3.3-V LVTTL : : 7 : Y +TxD : A18 : output : 3.3-V LVTTL : : 7 : Y +DCD : A19 : input : 3.3-V LVTTL : : 7 : Y +nRD_DATA : A20 : input : 3.3-V LVTTL : : 7 : Y +VCCIO7 : A21 : power : : 3.3V : 7 : +GND : A22 : gnd : : : : +nPCI_INTA : AA1 : input : 3.3-V LVTTL : : 2 : Y +PIC_INT : AA2 : input : 3.3-V LVTTL : : 2 : Y +FB_AD[2] : AA3 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[6] : AA4 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[8] : AA5 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AA6 : power : : 3.3V : 3 : +FB_AD[15] : AA7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[22] : AA8 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[25] : AA9 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[31] : AA10 : bidir : 3.3-V LVTTL : : 3 : Y +GND+ : AA11 : : : : 3 : +GND+ : AA12 : : : : 4 : +VD[18] : AA13 : bidir : 2.5 V : : 4 : Y +VD[25] : AA14 : bidir : 2.5 V : : 4 : Y +VDQS[0] : AA15 : bidir : 2.5 V : : 4 : Y +VDM[0] : AA16 : output : 2.5 V : : 4 : Y +nDDR_CLK : AA17 : output : 2.5 V : : 4 : Y +VA[12] : AA18 : output : 2.5 V : : 4 : Y +BA[1] : AA19 : output : 2.5 V : : 4 : Y +VA[7] : AA20 : output : 2.5 V : : 4 : Y +VA[6] : AA21 : output : 2.5 V : : 5 : Y +VA[4] : AA22 : output : 2.5 V : : 5 : Y +GND : AB1 : gnd : : : : +VCCIO3 : AB2 : power : : 3.3V : 3 : +FB_AD[3] : AB3 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[7] : AB4 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[9] : AB5 : bidir : 3.3-V LVTTL : : 3 : Y +GND : AB6 : gnd : : : : +FB_AD[16] : AB7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[23] : AB8 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[26] : AB9 : bidir : 3.3-V LVTTL : : 3 : Y +CLK24M576 : AB10 : output : 3.3-V LVTTL : : 3 : Y +GND+ : AB11 : : : : 3 : +CLK33M : AB12 : input : 3.3-V LVTTL : : 4 : Y +VD[29] : AB13 : bidir : 2.5 V : : 4 : Y +VD[26] : AB14 : bidir : 2.5 V : : 4 : Y +VD[24] : AB15 : bidir : 2.5 V : : 4 : Y +VD[23] : AB16 : bidir : 2.5 V : : 4 : Y +DDR_CLK : AB17 : output : 2.5 V : : 4 : Y +nVCAS : AB18 : output : 2.5 V : : 4 : Y +VA[9] : AB19 : output : 2.5 V : : 4 : Y +VA[8] : AB20 : output : 2.5 V : : 4 : Y +VCCIO4 : AB21 : power : : 2.5V : 4 : +GND : AB22 : gnd : : : : +ACSI_D[0] : B1 : bidir : 3.3-V LVTTL : : 1 : Y +MIDI_TLR : B2 : output : 3.3-V LVTTL : : 1 : Y +LP_D[5] : B3 : bidir : 3.3-V LVTTL : : 8 : Y +nSRBHE : B4 : output : 3.3-V LVTTL : : 8 : Y +SRD[0] : B5 : bidir : 3.3-V LVTTL : : 8 : Y +IO[4] : B6 : bidir : 3.3-V LVTTL : : 8 : Y +IO[2] : B7 : bidir : 3.3-V LVTTL : : 8 : Y +nSRCS : B8 : output : 3.3-V LVTTL : : 8 : Y +SRD[8] : B9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[11] : B10 : bidir : 3.3-V LVTTL : : 8 : Y +nRSTO_MCF : B11 : input : 3.3-V LVTTL : : 8 : Y +nDACK0 : B12 : input : 3.3-V LVTTL : : 7 : Y +IO[17] : B13 : bidir : 3.3-V LVTTL : : 7 : Y +IO[15] : B14 : bidir : 3.3-V LVTTL : : 7 : Y +IO[10] : B15 : bidir : 3.3-V LVTTL : : 7 : Y +SD_DATA0 : B16 : input : 3.3-V LVTTL : : 7 : Y +SD_DATA2 : B17 : input : 3.3-V LVTTL : : 7 : Y +RTS : B18 : output : 3.3-V LVTTL : : 7 : Y +RI : B19 : input : 3.3-V LVTTL : : 7 : Y +nSDSEL : B20 : output : 3.3-V LVTTL : : 7 : Y +VB[5] : B21 : output : 3.0-V LVTTL : : 6 : Y +VB[4] : B22 : output : 3.0-V LVTTL : : 6 : Y +ACSI_D[4] : C1 : bidir : 3.3-V LVTTL : : 1 : Y +ACSI_D[3] : C2 : bidir : 3.3-V LVTTL : : 1 : Y +LP_D[2] : C3 : bidir : 3.3-V LVTTL : : 8 : Y +LP_D[1] : C4 : bidir : 3.3-V LVTTL : : 8 : Y +GND : C5 : gnd : : : : +SRD[2] : C6 : bidir : 3.3-V LVTTL : : 8 : Y +IO[7] : C7 : bidir : 3.3-V LVTTL : : 8 : Y +IO[6] : C8 : bidir : 3.3-V LVTTL : : 8 : Y +GND : C9 : gnd : : : : +SRD[4] : C10 : bidir : 3.3-V LVTTL : : 8 : Y +GND : C11 : gnd : : : : +GND : C12 : gnd : : : : +IO[11] : C13 : bidir : 3.3-V LVTTL : : 7 : Y +GND : C14 : gnd : : : : +SD_CLK : C15 : output : 3.3-V LVTTL : : 7 : Y +GND : C16 : gnd : : : : +nDCHG : C17 : input : 3.3-V LVTTL : : 7 : Y +GND : C18 : gnd : : : : +TRACK00 : C19 : input : 3.3-V LVTTL : : 7 : Y +VB[6] : C20 : output : 3.0-V LVTTL : : 6 : Y +VB[3] : C21 : output : 3.0-V LVTTL : : 6 : Y +VB[2] : C22 : output : 3.0-V LVTTL : : 6 : Y +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT : D1 : input : 3.3-V LVTTL : : 1 : N +ACSI_D[5] : D2 : bidir : 3.3-V LVTTL : : 1 : Y +GND : D3 : gnd : : : : +VCCIO1 : D4 : power : : 3.3V : 1 : +VCCIO8 : D5 : power : : 3.3V : 8 : +LP_D[4] : D6 : bidir : 3.3-V LVTTL : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : +GND : D8 : gnd : : : : +VCCIO8 : D9 : power : : 3.3V : 8 : +SRD[12] : D10 : bidir : 3.3-V LVTTL : : 8 : Y +VCCIO8 : D11 : power : : 3.3V : 8 : +VCCIO7 : D12 : power : : 3.3V : 7 : +IO[12] : D13 : bidir : 3.3-V LVTTL : : 7 : Y +VCCIO7 : D14 : power : : 3.3V : 7 : +DTR : D15 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : D16 : power : : 3.3V : 7 : +nWR_GATE : D17 : output : 3.3-V LVTTL : : 7 : Y +VCCIO7 : D18 : power : : 3.3V : 7 : +nWP : D19 : input : 3.3-V LVTTL : : 7 : Y +VB[7] : D20 : output : 3.0-V LVTTL : : 6 : Y +VG[7] : D21 : output : 3.0-V LVTTL : : 6 : Y +VG[6] : D22 : output : 3.0-V LVTTL : : 6 : Y +SCSI_D[1] : E1 : bidir : 3.3-V LVTTL : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2 : input : 3.3-V LVTTL : : 1 : N +ACSI_D[2] : E3 : bidir : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1 : +LPDIR : E5 : output : 3.3-V LVTTL : : 8 : Y +LP_STR : E6 : output : 3.3-V LVTTL : : 8 : Y +LP_D[3] : E7 : bidir : 3.3-V LVTTL : : 8 : Y +VCCIO8 : E8 : power : : 3.3V : 8 : +IO[5] : E9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[6] : E10 : bidir : 3.3-V LVTTL : : 8 : Y +nDREQ1 : E11 : output : 3.3-V LVTTL : : 7 : Y +MIDI_IN : E12 : input : 3.3-V LVTTL : : 7 : Y +IO[13] : E13 : bidir : 3.3-V LVTTL : : 7 : Y +SD_CMD_D1 : E14 : bidir : 3.3-V LVTTL : : 7 : Y +YM_QC : E15 : output : 3.3-V LVTTL : : 7 : Y +nINDEX : E16 : input : 3.3-V LVTTL : : 7 : Y +VCCD_PLL2 : E17 : power : : 1.2V : : +GNDA2 : E18 : gnd : : : : +VCCIO6 : E19 : power : : 3.0V : 6 : +GND : E20 : gnd : : : : +VG[2] : E21 : output : 3.0-V LVTTL : : 6 : Y +VG[1] : E22 : output : 3.0-V LVTTL : : 6 : Y +SCSI_D[3] : F1 : bidir : 3.3-V LVTTL : : 1 : Y +SCSI_D[2] : F2 : bidir : 3.3-V LVTTL : : 1 : Y +GND : F3 : gnd : : : : +VCCIO1 : F4 : power : : 3.3V : 1 : +GNDA3 : F5 : gnd : : : : +VCCD_PLL3 : F6 : power : : 1.2V : : +LP_D[0] : F7 : bidir : 3.3-V LVTTL : : 8 : Y +nSRWE : F8 : output : 3.3-V LVTTL : : 8 : Y +SRD[5] : F9 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[13] : F10 : bidir : 3.3-V LVTTL : : 8 : Y +nSROE : F11 : output : 3.3-V LVTTL : : 7 : Y +GND : F12 : gnd : : : : +SD_CD_DATA3 : F13 : bidir : 3.3-V LVTTL : : 7 : Y +nSTEP : F14 : output : 3.3-V LVTTL : : 7 : Y +DSA_D : F15 : output : 3.3-V LVTTL : : 7 : Y +HD_DD : F16 : input : 3.3-V LVTTL : : 7 : Y +nSYNC : F17 : output : 3.0-V LVCMOS : : 6 : Y +VCCA2 : F18 : power : : 2.5V : : +PIXEL_CLK_PAD : F19 : output : 3.0-V LVTTL : : 6 : Y +nIRQ[4] : F20 : output : 3.0-V LVCMOS : : 6 : Y +nIRQ[2] : F21 : output : 3.0-V LVCMOS : : 6 : Y +VR[7] : F22 : output : 3.0-V LVTTL : : 6 : Y +GND+ : G1 : : : : 1 : +MAIN_CLK : G2 : input : 3.3-V LVTTL : : 1 : Y +SCSI_D[5] : G3 : bidir : 3.3-V LVTTL : : 1 : Y +SCSI_D[4] : G4 : bidir : 3.3-V LVTTL : : 1 : Y +ACSI_D[1] : G5 : bidir : 3.3-V LVTTL : : 1 : Y +VCCA3 : G6 : power : : 2.5V : : +LP_BUSY : G7 : input : 3.3-V LVTTL : : 8 : Y +LP_D[7] : G8 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[14] : G9 : bidir : 3.3-V LVTTL : : 8 : Y +IO[8] : G10 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[3] : G11 : bidir : 3.3-V LVTTL : : 8 : Y +VCCINT : G12 : power : : 1.2V : : +YM_QB : G13 : output : 3.3-V LVTTL : : 7 : Y +nWR : G14 : output : 3.3-V LVTTL : : 7 : Y +nSTEP_DIR : G15 : output : 3.3-V LVTTL : : 7 : Y +nMOT_ON : G16 : output : 3.3-V LVTTL : : 7 : Y +nBLANK_PAD : G17 : output : 3.0-V LVTTL : : 6 : Y +VB[0] : G18 : output : 3.0-V LVTTL : : 6 : Y +VCCIO6 : G19 : power : : 3.0V : 6 : +GND : G20 : gnd : : : : +E0_INT : G21 : input : 3.3-V LVTTL : : 6 : Y +IDE_INT : G22 : input : 3.3-V LVTTL : : 6 : Y +nSCSI_C_D : H1 : input : 3.3-V LVTTL : : 1 : Y +nSCSI_MSG : H2 : input : 3.3-V LVTTL : : 1 : Y +GND : H3 : gnd : : : : +VCCIO1 : H4 : power : : 3.3V : 1 : +MIDI_OLR : H5 : output : 3.3-V LVTTL : : 1 : Y +ACSI_D[7] : H6 : bidir : 3.3-V LVTTL : : 1 : Y +ACSI_D[6] : H7 : bidir : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 1 : +VCCINT : H9 : power : : 1.2V : : +SRD[15] : H10 : bidir : 3.3-V LVTTL : : 8 : Y +SRD[7] : H11 : bidir : 3.3-V LVTTL : : 8 : Y +GND : H12 : gnd : : : : +GND : H13 : gnd : : : : +CTS : H14 : input : 3.3-V LVTTL : : 7 : Y +RxD : H15 : input : 3.3-V LVTTL : : 7 : Y +VG[5] : H16 : output : 3.0-V LVTTL : : 6 : Y +VB[1] : H17 : output : 3.0-V LVTTL : : 6 : Y +VG[3] : H18 : output : 3.0-V LVTTL : : 6 : Y +VG[0] : H19 : output : 3.0-V LVTTL : : 6 : Y +nIRQ[3] : H20 : output : 3.0-V LVCMOS : : 6 : Y +VR[3] : H21 : output : 3.0-V LVTTL : : 6 : Y +VR[2] : H22 : output : 3.0-V LVTTL : : 6 : Y +CLKUSB : J1 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 : +nSCSI_I_O : J3 : input : 3.3-V LVTTL : : 1 : Y +nACSI_INT : J4 : input : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 : +SCSI_D[0] : J6 : bidir : 3.3-V LVTTL : : 1 : Y +SCSI_DIR : J7 : output : 3.3-V LVTTL : : 1 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1 : +GND : J9 : gnd : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +VCCINT : J14 : power : : 1.2V : : +GND : J15 : gnd : : : : +VCCINT : J16 : power : : 1.2V : : +VG[4] : J17 : output : 3.0-V LVTTL : : 6 : Y +VR[6] : J18 : output : 3.0-V LVTTL : : 6 : Y +GND : J19 : gnd : : : : +VCCIO6 : J20 : power : : 3.0V : 6 : +VR[1] : J21 : output : 3.0-V LVTTL : : 6 : Y +VR[0] : J22 : output : 3.0-V LVTTL : : 6 : Y +~ALTERA_DATA0~ / RESERVED_INPUT : K1 : input : 3.3-V LVTTL : : 1 : N +~ALTERA_DCLK~ / RESERVED_INPUT : K2 : input : 3.3-V LVTTL : : 1 : N +GND : K3 : gnd : : : : +VCCIO1 : K4 : power : : 3.3V : 1 : +nCONFIG : K5 : : : : 1 : +nSTATUS : K6 : : : : 1 : +nACSI_DRQ : K7 : input : 3.3-V LVTTL : : 1 : Y +SCSI_D[7] : K8 : bidir : 3.3-V LVTTL : : 1 : Y +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +VCCINT : K15 : power : : 1.2V : : +GND : K16 : gnd : : : : +VR[4] : K17 : output : 3.0-V LVTTL : : 6 : Y +VR[5] : K18 : output : 3.0-V LVTTL : : 6 : Y +VSYNC_PAD : K19 : output : 3.0-V LVTTL : : 6 : Y +MSEL3 : K20 : : : : 6 : +HSYNC_PAD : K21 : output : 3.0-V LVTTL : : 6 : Y +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 3.0-V LVTTL : : 6 : N +TMS : L1 : input : : : 1 : +TCK : L2 : input : : : 1 : +nCE : L3 : : : : 1 : +TDO : L4 : output : : : 1 : +TDI : L5 : input : : : 1 : +ACSI_DIR : L6 : output : 3.3-V LVTTL : : 2 : Y +PIC_AMKB_RX : L7 : input : 3.3-V LVTTL : : 2 : Y +SCSI_D[6] : L8 : bidir : 3.3-V LVTTL : : 1 : Y +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +GND : L15 : gnd : : : : +VCCINT : L16 : power : : 1.2V : : +MSEL2 : L17 : : : : 6 : +MSEL1 : L18 : : : : 6 : +VCCIO6 : L19 : power : : 3.0V : 6 : +GND : L20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +nACSI_RESET : M1 : output : 3.3-V LVTTL : : 2 : Y +nACSI_CS : M2 : output : 3.3-V LVTTL : : 2 : Y +nSCSI_ATN : M3 : output : 3.3-V LVTTL : : 2 : Y +nACSI_ACK : M4 : output : 3.3-V LVTTL : : 2 : Y +IDE_RES : M5 : output : 3.3-V LVTTL : : 2 : Y +ACSI_A1 : M6 : output : 3.3-V LVTTL : : 2 : Y +SCSI_PAR : M7 : bidir : 3.3-V LVTTL : : 2 : Y +nSCSI_SEL : M8 : bidir : 3.3-V LVTTL : : 2 : Y +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +VCCINT : M15 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : +MSEL0 : M17 : : : : 6 : +CONF_DONE : M18 : : : : 6 : +SD_WP : M19 : input : 3.3-V LVTTL : : 5 : Y +SD_CARD_DEDECT : M20 : input : 3.3-V LVTTL : : 5 : Y +VD[1] : M21 : bidir : 2.5 V : : 5 : Y +VD[0] : M22 : bidir : 2.5 V : : 5 : Y +AMKB_TX : N1 : output : 3.3-V LVCMOS : : 2 : Y +nSCSI_ACK : N2 : output : 3.3-V LVTTL : : 2 : Y +GND : N3 : gnd : : : : +VCCIO2 : N4 : power : : 3.3V : 2 : +nRP_LDS : N5 : output : 3.3-V LVTTL : : 2 : Y +nSCSI_RST : N6 : bidir : 3.3-V LVTTL : : 2 : Y +nIRQ[7] : N7 : output : 3.3-V LVTTL : : 2 : Y +nSCSI_BUSY : N8 : bidir : 3.3-V LVTTL : : 2 : Y +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND : N15 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : +VD[12] : N17 : bidir : 2.5 V : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : +LED_FPGA_OK : N19 : output : 2.5 V : : 5 : Y +VD[15] : N20 : bidir : 2.5 V : : 5 : Y +~ALTERA_DEV_CLRn~ / RESERVED_INPUT : N21 : input : 2.5 V : : 5 : N +~ALTERA_DEV_OE~ / RESERVED_INPUT : N22 : input : 2.5 V : : 5 : N +nIDE_RD : P1 : output : 3.3-V LVTTL : : 2 : Y +nIDE_WR : P2 : output : 3.3-V LVTTL : : 2 : Y +nROM3 : P3 : output : 3.3-V LVTTL : : 2 : Y +nRP_UDS : P4 : output : 3.3-V LVTTL : : 2 : Y +nIRQ[5] : P5 : output : 3.3-V LVTTL : : 2 : Y +nPCI_INTD : P6 : input : 3.3-V LVTTL : : 2 : Y +nIRQ[6] : P7 : output : 3.3-V LVTTL : : 2 : Y +GND : P8 : gnd : : : : +VCCINT : P9 : power : : 1.2V : : +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +VCCINT : P14 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : +VD[10] : P17 : bidir : 2.5 V : : 5 : Y +VCCIO5 : P18 : power : : 2.5V : 5 : +GND : P19 : gnd : : : : +VD[13] : P20 : bidir : 2.5 V : : 5 : Y +VD[4] : P21 : bidir : 2.5 V : : 5 : Y +VD[2] : P22 : bidir : 2.5 V : : 5 : Y +nIDE_CS1 : R1 : output : 3.3-V LVTTL : : 2 : Y +nIDE_CS0 : R2 : output : 3.3-V LVTTL : : 2 : Y +GND : R3 : gnd : : : : +VCCIO2 : R4 : power : : 3.3V : 2 : +TIN0 : R5 : output : 3.3-V LVTTL : : 2 : Y +nFB_OE : R6 : input : 3.3-V LVTTL : : 2 : Y +FB_ALE : R7 : input : 3.3-V LVTTL : : 2 : Y +VCCINT : R8 : power : : 1.2V : : +GND : R9 : gnd : : : : +VCCINT : R10 : power : : 1.2V : : +GND : R11 : gnd : : : : +VCCINT : R12 : power : : 1.2V : : +GND : R13 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : +VD[5] : R17 : bidir : 2.5 V : : 5 : Y +VD[9] : R18 : bidir : 2.5 V : : 5 : Y +VD[6] : R19 : bidir : 2.5 V : : 5 : Y +VD[3] : R20 : bidir : 2.5 V : : 5 : Y +VD[11] : R21 : bidir : 2.5 V : : 5 : Y +VD[14] : R22 : bidir : 2.5 V : : 5 : Y +WP_CF_CARD : T1 : input : 3.3-V LVTTL : : 2 : Y +GND+ : T2 : : : : 2 : +nFB_BURST : T3 : input : 3.3-V LVTTL : : 2 : Y +CLK25M : T4 : output : 3.3-V LVTTL : : 2 : Y +nFB_WR : T5 : input : 3.3-V LVTTL : : 2 : Y +VCCA1 : T6 : power : : 2.5V : : +nFB_TA : T7 : output : 3.3-V LVTTL : : 2 : Y +nFB_CS1 : T8 : input : 3.3-V LVTTL : : 3 : Y +nFB_CS2 : T9 : input : 3.3-V LVTTL : : 3 : Y +FB_AD[20] : T10 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[24] : T11 : bidir : 3.3-V LVTTL : : 3 : Y +VD[16] : T12 : bidir : 2.5 V : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : +VDQS[3] : T16 : bidir : 2.5 V : : 4 : Y +VDM[3] : T17 : output : 2.5 V : : 5 : Y +nVCS : T18 : output : 2.5 V : : 5 : Y +VCCIO5 : T19 : power : : 2.5V : 5 : +GND : T20 : gnd : : : : +nMASTER : T21 : input : 3.3-V LVTTL : : 5 : Y +TOUT0 : T22 : input : 3.3-V LVTTL : : 5 : Y +nSCSI_DRQ : U1 : input : 3.3-V LVTTL : : 2 : Y +nROM4 : U2 : output : 3.3-V LVTTL : : 2 : Y +GND : U3 : gnd : : : : +VCCIO2 : U4 : power : : 3.3V : 2 : +GNDA1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : +FB_SIZE0 : U8 : input : 3.3-V LVTTL : : 3 : Y +FB_AD[12] : U9 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[21] : U10 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[27] : U11 : bidir : 3.3-V LVTTL : : 3 : Y +VD[31] : U12 : bidir : 2.5 V : : 4 : Y +VD[20] : U13 : bidir : 2.5 V : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : +VCKE : U15 : output : 2.5 V : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4 : +VCCA4 : U18 : power : : 2.5V : : +VA[11] : U19 : output : 2.5 V : : 5 : Y +VDM[2] : U20 : output : 2.5 V : : 5 : Y +VD[7] : U21 : bidir : 2.5 V : : 5 : Y +VDQS[2] : U22 : bidir : 2.5 V : : 5 : Y +nPD_VGA : V1 : output : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : +nPCI_INTC : V3 : input : 3.3-V LVTTL : : 2 : Y +nPCI_INTB : V4 : input : 3.3-V LVTTL : : 2 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : +nFB_CS3 : V6 : input : 3.3-V LVTTL : : 3 : Y +FB_AD[5] : V7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[13] : V8 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[18] : V9 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[19] : V10 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[28] : V11 : bidir : 3.3-V LVTTL : : 3 : Y +VD[30] : V12 : bidir : 2.5 V : : 4 : Y +VD[27] : V13 : bidir : 2.5 V : : 4 : Y +VD[19] : V14 : bidir : 2.5 V : : 4 : Y +VD[21] : V15 : bidir : 2.5 V : : 4 : Y +VDM[1] : V16 : output : 2.5 V : : 4 : Y +VCCD_PLL4 : V17 : power : : 1.2V : : +GNDA4 : V18 : gnd : : : : +VCCIO5 : V19 : power : : 2.5V : 5 : +GND : V20 : gnd : : : : +VA[10] : V21 : output : 2.5 V : : 5 : Y +VD[8] : V22 : bidir : 2.5 V : : 5 : Y +nCF_CS1 : W1 : output : 3.3-V LVTTL : : 2 : Y +nCF_CS0 : W2 : output : 3.3-V LVTTL : : 2 : Y +GND : W3 : gnd : : : : +VCCIO2 : W4 : power : : 3.3V : 2 : +VCCIO3 : W5 : power : : 3.3V : 3 : +FB_AD[4] : W6 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[10] : W7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[14] : W8 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : W9 : power : : 3.3V : 3 : +FB_AD[29] : W10 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : W11 : power : : 3.3V : 3 : +VCCIO4 : W12 : power : : 2.5V : 4 : +VD[28] : W13 : bidir : 2.5 V : : 4 : Y +VD[22] : W14 : bidir : 2.5 V : : 4 : Y +VDQS[1] : W15 : bidir : 2.5 V : : 4 : Y +VCCIO4 : W16 : power : : 2.5V : 4 : +nVRAS : W17 : output : 2.5 V : : 4 : Y +VCCIO4 : W18 : power : : 2.5V : 4 : +BA[0] : W19 : output : 2.5 V : : 5 : Y +VA[0] : W20 : output : 2.5 V : : 5 : Y +VA[2] : W21 : output : 2.5 V : : 5 : Y +VA[1] : W22 : output : 2.5 V : : 5 : Y +IDE_RDY : Y1 : input : 3.3-V LVTTL : : 2 : Y +AMKB_RX : Y2 : input : 3.3-V LVTTL : : 2 : Y +FB_AD[0] : Y3 : bidir : 3.3-V LVTTL : : 3 : Y +FB_SIZE1 : Y4 : input : 3.3-V LVTTL : : 3 : Y +GND : Y5 : gnd : : : : +FB_AD[1] : Y6 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[11] : Y7 : bidir : 3.3-V LVTTL : : 3 : Y +FB_AD[17] : Y8 : bidir : 3.3-V LVTTL : : 3 : Y +GND : Y9 : gnd : : : : +FB_AD[30] : Y10 : bidir : 3.3-V LVTTL : : 3 : Y +GND : Y11 : gnd : : : : +GND : Y12 : gnd : : : : +VD[17] : Y13 : bidir : 2.5 V : : 4 : Y +VCCIO4 : Y14 : power : : 2.5V : 4 : +GND : Y15 : gnd : : : : +GND : Y16 : gnd : : : : +nVWE : Y17 : output : 2.5 V : : 4 : Y +GND : Y18 : gnd : : : : +VCCIO5 : Y19 : power : : 2.5V : 5 : +GND : Y20 : gnd : : : : +VA[5] : Y21 : output : 2.5 V : : 5 : Y +VA[3] : Y22 : output : 2.5 V : : 5 : Y diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf new file mode 100644 index 0000000..86e8842 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -0,0 +1,740 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 12:45:00 November 06, 2010 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# firebee1_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +# Project-Wide Assignments +# ======================== +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd" +set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd" +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf" +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\Video\\BLITTER\\BLITTER.vhd" +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt + +# Pin & Location Assignments +# ========================== +set_location_assignment PIN_AB12 -to CLK33M +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_E12 -to MIDI_IN +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON + +# Classic Timing Assignments +# ========================== +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF + +# Analysis & Synthesis Assignments +# ================================ +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" + +# Fitter Assignments +# ================== +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX + +# Assembler Assignments +# ===================== +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 + +# Simulator Assignments +# ===================== +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf + +# start EDA_TOOL_SETTINGS(eda_blast_fpga) +# --------------------------------------- + + # Analysis & Synthesis Assignments + # ================================ +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga + +# end EDA_TOOL_SETTINGS(eda_blast_fpga) +# ------------------------------------- + +# start CLOCK(fast) +# ----------------- + + # Classic Timing Assignments + # ========================== +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast + +# end CLOCK(fast) +# --------------- + +# start ASSIGNMENT_GROUP(fast) +# ---------------------------- + + # Assignment Group Assignments + # ============================ +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast + +# end ASSIGNMENT_GROUP(fast) +# -------------------------- + +# ---------------------- +# start ENTITY(firebee1) + + # Classic Timing Assignments + # ========================== +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA + + # Fitter Assignments + # ================== +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX + + # Simulator Assignments + # ===================== +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 + + # start LOGICLOCK_REGION(Root Region) + # ----------------------------------- + + # LogicLock Region Assignments + # ============================ +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" + + # end LOGICLOCK_REGION(Root Region) + # --------------------------------- + + # start DESIGN_PARTITION(Top) + # --------------------------- + + # Incremental Compilation Assignments + # =================================== +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + + # end DESIGN_PARTITION(Top) + # ------------------------- + +# end ENTITY(firebee1) +# -------------------- +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name QIP_FILE altpll4.qip +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws new file mode 100644 index 0000000..ed1a121 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.qws @@ -0,0 +1,4 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames diff --git a/FPGA_Quartus_13.1/firebee1.rbf b/FPGA_Quartus_13.1/firebee1.rbf new file mode 100644 index 0000000000000000000000000000000000000000..63c16f1d687e91f02187b06b1c5e3ecfe12b2e04 GIT binary patch literal 428953 zcmeFaeY_l3dFNSGw>q^PJ~A=Q+=L>QwvdU;pNC;{O8v_HQ5i>SJI1 z>SK?7KE_}MWPghUnf^XK()0I74dyC*(z%gHMK0c4%0Pz+m zu6pz3u53PZbrcHb%UoRfPuI_Ux#F(veE8q9j%appAw3t;;nJ$_=yiDtT|Ww4{*%>n zWiI?y>ZtB~zpkwd)yF*k3+p}|4p)D^p5m7Q4u|Vs`A=5g)l=x|&ev1E+6ok(2i1GB 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z&ivBL;$AaWm!s)BK01PB+8#-XzlduP=Kt@Fr^OfFcmos7{E=(o@E@FsQDXV}8~5EW zCVz~H=G(tABbPy8!2j_TqMYFDnR^`S&t6DSj>`y+VDU`Qg{kYAd+ryv{>7M1%*6kC z;>b55v*LLpwk6cW5HHe$AA5@px}ftlB+I=+>Bmgwt`=*WPw>#q?l=V zf&yc#1gReHApt1zfJ=#ouARAGoc$vrt(aKCqD2LZ6m%(`C4fE(!|qCM-epD^9e}*B>bgqP1uDUK6uxXOKdNs%I53 z<^qDCYcwlZaVhFTmxJI%aaMog%*BU4@|!RH+>a>nTYqPKVfv(-Jn14tH{w{lA5Q5d&*4QlX9~@Z zdJZ4_DaB4JeG5XE|LJM8>_o1csmUxmT)Nykl!!!2Mmq1hwaj>GrbxHig>|S^Bw7BV zhN9U@DcdFV4{lGS(0Yt+wYONJaPeU=n=e0q@l^>DUVEYs!Erd6Ek>B$KL5_qd9epH z-i~C(G$+rA_!4>@#x!?pIPZT4Go?dWF2S@bGLS2bX*(*s;QblFbQYBSZ?@gnD z%Vq+yRnuBsv7nh2W0bKNrEsF4hqFa5jub%>KX-2m$Qk6HbwQ=PDAatKK1_r&C)gu literal 0 HcmV?d00001 diff --git a/FPGA_Quartus_13.1/firebee1.tan.rpt b/FPGA_Quartus_13.1/firebee1.tan.rpt new file mode 100644 index 0000000..b84e104 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.tan.rpt @@ -0,0 +1,6936 @@ +Classic Timing Analyzer report for firebee1 +Wed Dec 15 02:25:22 2010 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Parallel Compilation + 6. Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + 7. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + 8. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + 9. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + 10. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + 11. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + 12. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + 13. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + 14. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + 15. Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + 16. Clock Setup: 'CLK33M' + 17. Clock Setup: 'MAIN_CLK' + 18. Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + 19. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + 20. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + 21. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + 22. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + 23. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + 24. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + 25. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + 26. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + 27. Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + 28. Clock Hold: 'CLK33M' + 29. Clock Hold: 'MAIN_CLK' + 30. tsu + 31. tco + 32. tpd + 33. th + 34. Board Trace Model Assignments + 35. Input Transition Times + 36. Slow Corner Signal Integrity Metrics + 37. Fast Corner Signal Integrity Metrics + 38. Ignored Timing Assignments + 39. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ +; Worst-case tsu ; -4.528 ns ; 1.000 ns ; 5.528 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; -- ; MAIN_CLK ; 6867 ; +; Worst-case tco ; -14.840 ns ; 1.000 ns ; 15.840 ns ; interrupt_handler:nobody|INT_LATCH[8] ; nIRQ[5] ; MAIN_CLK ; -- ; 4976 ; +; Worst-case tpd ; -11.944 ns ; 1.000 ns ; 12.944 ns ; nFB_CS1 ; FB_AD[18] ; -- ; -- ; 514 ; +; Worst-case th ; -0.401 ns ; 1.000 ns ; 1.401 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; -- ; MAIN_CLK ; 117 ; +; Clock Setup: 'CLK33M' ; -5.966 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 3741 ; +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -4.615 ns ; 24.98 MHz ( period = 40.033 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 3741 ; +; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -4.294 ns ; 95.92 MHz ( period = 10.425 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 3741 ; +; Clock Setup: 'MAIN_CLK' ; -4.261 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 27347 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -2.673 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 86 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -1.712 ns ; 66.00 MHz ( period = 15.151 ns ) ; N/A ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 29 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 1.672 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 2.965 ns ; 132.01 MHz ( period = 7.575 ns ) ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0 ; +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 5.299 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0 ; +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 28.590 ns ; 15.99 MHz ( period = 62.552 ns ) ; 186.15 MHz ( period = 5.372 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0 ; +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 498.663 ns ; 2.00 MHz ( period = 500.416 ns ) ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0 ; +; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; 1997.239 ns ; 0.50 MHz ( period = 1999.998 ns ) ; 362.45 MHz ( period = 2.759 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'MAIN_CLK' ; -3.786 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 108 ; +; Clock Hold: 'CLK33M' ; -0.687 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; CLK33M ; CLK33M ; 26 ; +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -0.454 ns ; 24.98 MHz ( period = 40.033 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 26 ; +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 0.502 ns ; 15.99 MHz ( period = 62.552 ns ) ; N/A ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; 0.502 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; 0.502 ns ; 95.92 MHz ( period = 10.425 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 0.564 ns ; 2.00 MHz ( period = 500.416 ns ) ; N/A ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; 0.825 ns ; 0.50 MHz ( period = 1999.998 ns ) ; N/A ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 1.825 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; 2.664 ns ; 66.00 MHz ( period = 15.151 ns ) ; N/A ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 3.263 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0 ; +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 4.336 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 51319 ; ++-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ +; Device Name ; EP3C40F484C6 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; tpd Requirement ; 1 ns ; ; ; ; +; th Requirement ; 1 ns ; ; ; ; +; tsu Requirement ; 1 ns ; ; ; ; +; tco Requirement ; 1 ns ; ; ; ; +; fmax Requirement ; 30 ns ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Nominal Core Supply Voltage ; 1.2V ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; +; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; On ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; +; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_0hh1 ; +; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe17|dffe18a ; dcfifo_0hh1 ; +; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_3fh1 ; +; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe15|dffe16a ; dcfifo_3fh1 ; +; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe22|dffe23a ; dcfifo_8fi1 ; +; Input Maximum Delay ; 4 ns ; * ; FB_ALE ; ; +; Maximum Delay ; 5 ns ; FB_AD ; BA ; ; +; Maximum Delay ; 5 ns ; FB_AD ; VA ; ; +; Maximum Delay ; 5 ns ; FB_AD ; nVRAS ; ; ++------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; ; PLL output ; 0.5 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 1 ; 66 ; -9.578 ns ; ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; ; PLL output ; 2.46 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 67 ; 900 ; -9.578 ns ; ; +; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; ; PLL output ; 24.57 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 67 ; 90 ; -9.578 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; ; PLL output ; 2.0 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 1800 ; -1.864 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; ; PLL output ; 15.99 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 225 ; -1.864 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; ; PLL output ; 24.98 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 144 ; -1.864 ns ; ; +; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; ; PLL output ; 47.96 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 75 ; -1.864 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; -3.620 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; -1.094 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; 2.693 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; 1.115 ns ; ; +; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; ; PLL output ; 66.0 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 2 ; 1 ; -4.884 ns ; ; +; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; ; PLL output ; 95.92 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 218 ; 75 ; -2.843 ns ; ; +; CLK33M ; ; User Pin ; 33.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; +; MAIN_CLK ; ; User Pin ; 33.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; ++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 1997.239 ns ; 362.45 MHz ( period = 2.759 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.574 ns ; +; 1997.297 ns ; 370.23 MHz ( period = 2.701 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.516 ns ; +; 1997.355 ns ; 378.36 MHz ( period = 2.643 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.458 ns ; +; 1997.413 ns ; 386.85 MHz ( period = 2.585 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.400 ns ; +; 1997.476 ns ; 396.51 MHz ( period = 2.522 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.337 ns ; +; 1997.531 ns ; 405.35 MHz ( period = 2.467 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.282 ns ; +; 1997.593 ns ; 415.80 MHz ( period = 2.405 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.220 ns ; +; 1997.626 ns ; 421.59 MHz ( period = 2.372 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.187 ns ; +; 1997.647 ns ; 425.35 MHz ( period = 2.351 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.166 ns ; +; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.129 ns ; +; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.129 ns ; +; 1997.709 ns ; 436.87 MHz ( period = 2.289 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.104 ns ; +; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; +; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; +; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; +; 1997.765 ns ; 447.83 MHz ( period = 2.233 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 2.049 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; +; 1997.822 ns ; 459.56 MHz ( period = 2.176 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.992 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; +; 1997.863 ns ; 468.38 MHz ( period = 2.135 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.950 ns ; +; 1997.880 ns ; 472.14 MHz ( period = 2.118 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.934 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; +; 1997.918 ns ; 480.77 MHz ( period = 2.080 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.895 ns ; +; 1997.921 ns ; 481.46 MHz ( period = 2.077 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.892 ns ; +; 1997.941 ns ; 486.14 MHz ( period = 2.057 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.873 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; +; 1997.976 ns ; 494.56 MHz ( period = 2.022 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.837 ns ; +; 1997.979 ns ; 495.29 MHz ( period = 2.019 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.834 ns ; +; 1997.980 ns ; 495.54 MHz ( period = 2.018 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.833 ns ; +; 1997.995 ns ; 499.25 MHz ( period = 2.003 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.819 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; +; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.779 ns ; +; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.779 ns ; +; 1998.037 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.776 ns ; +; 1998.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.775 ns ; +; 1998.055 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.759 ns ; +; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; +; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; +; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; +; 1998.091 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.723 ns ; +; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.721 ns ; +; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.721 ns ; +; 1998.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.718 ns ; +; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.717 ns ; +; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.717 ns ; +; 1998.113 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.701 ns ; +; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.665 ns ; +; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.665 ns ; +; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.665 ns ; +; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.665 ns ; +; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.663 ns ; +; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.663 ns ; +; 1998.152 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.662 ns ; +; 1998.153 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.660 ns ; +; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.659 ns ; +; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.659 ns ; +; 1998.167 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.647 ns ; +; 1998.206 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.607 ns ; +; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; +; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; +; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; +; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.605 ns ; +; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.605 ns ; +; 1998.209 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.605 ns ; +; 1998.210 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.604 ns ; +; 1998.211 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.602 ns ; +; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.601 ns ; +; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.601 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; +; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.547 ns ; +; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.547 ns ; +; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.547 ns ; +; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.547 ns ; +; 1998.268 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.546 ns ; +; 1998.269 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.544 ns ; +; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.543 ns ; +; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.543 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; +; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.489 ns ; +; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.489 ns ; +; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.489 ns ; +; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.489 ns ; +; 1998.326 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.488 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.486 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.485 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.485 ns ; +; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.486 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; +; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.432 ns ; +; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.431 ns ; +; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; +; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; +; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; +; 1998.384 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.430 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.428 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.427 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.427 ns ; +; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.428 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; +; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.374 ns ; +; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.373 ns ; +; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; +; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; +; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; +; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.372 ns ; +; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.372 ns ; +; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.370 ns ; +; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.369 ns ; +; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.370 ns ; +; 1998.445 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.369 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; +; 1998.498 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.316 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; +; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; +; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; +; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; +; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.312 ns ; +; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.311 ns ; +; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.312 ns ; +; 1998.503 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.311 ns ; +; 1998.671 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.143 ns ; +; 1999.023 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.791 ns ; +; 1999.024 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.790 ns ; +; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.789 ns ; +; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.789 ns ; +; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; +; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; +; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; +; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.786 ns ; +; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.786 ns ; +; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.785 ns ; +; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.785 ns ; +; 1999.031 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.783 ns ; ++-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; ++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; +; 498.729 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.503 ns ; +; 498.743 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.489 ns ; +; 498.787 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.445 ns ; +; 498.800 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.432 ns ; +; 498.801 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.431 ns ; +; 498.858 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.374 ns ; +; 498.859 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.373 ns ; +; 498.894 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.338 ns ; +; 498.916 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.316 ns ; +; 498.917 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.315 ns ; +; 499.319 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.913 ns ; +; 499.422 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.810 ns ; +; 499.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.788 ns ; +; 499.449 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.783 ns ; ++------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 28.590 ns ; 186.15 MHz ( period = 5.372 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns ; 31.135 ns ; 2.545 ns ; +; 28.759 ns ; 198.65 MHz ( period = 5.034 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns ; 31.135 ns ; 2.376 ns ; +; 54.429 ns ; 123.11 MHz ( period = 8.123 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.941 ns ; +; 54.452 ns ; 123.46 MHz ( period = 8.100 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.920 ns ; +; 54.563 ns ; 125.17 MHz ( period = 7.989 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.803 ns ; +; 54.586 ns ; 125.53 MHz ( period = 7.966 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.782 ns ; +; 54.600 ns ; 125.75 MHz ( period = 7.952 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.766 ns ; +; 54.623 ns ; 126.12 MHz ( period = 7.929 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.745 ns ; +; 54.812 ns ; 129.20 MHz ( period = 7.740 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.551 ns ; +; 54.822 ns ; 129.37 MHz ( period = 7.730 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.550 ns ; +; 54.835 ns ; 129.58 MHz ( period = 7.717 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.530 ns ; +; 54.845 ns ; 129.75 MHz ( period = 7.707 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.374 ns ; 7.529 ns ; +; 54.868 ns ; 130.14 MHz ( period = 7.684 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.491 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.474 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; +; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; +; 54.910 ns ; 130.86 MHz ( period = 7.642 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.456 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.453 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; +; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; +; 54.933 ns ; 131.25 MHz ( period = 7.619 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.435 ns ; +; 54.944 ns ; 131.44 MHz ( period = 7.608 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.417 ns ; +; 54.947 ns ; 131.49 MHz ( period = 7.605 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.414 ns ; +; 54.948 ns ; 131.51 MHz ( period = 7.604 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.413 ns ; +; 54.948 ns ; 131.51 MHz ( period = 7.604 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.413 ns ; +; 54.967 ns ; 131.84 MHz ( period = 7.585 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.396 ns ; +; 54.970 ns ; 131.89 MHz ( period = 7.582 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.393 ns ; +; 54.971 ns ; 131.91 MHz ( period = 7.581 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.392 ns ; +; 54.971 ns ; 131.91 MHz ( period = 7.581 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.392 ns ; +; 54.979 ns ; 132.05 MHz ( period = 7.573 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.382 ns ; +; 54.981 ns ; 132.08 MHz ( period = 7.571 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.387 ns ; +; 54.996 ns ; 132.35 MHz ( period = 7.556 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.374 ns ; +; 55.002 ns ; 132.45 MHz ( period = 7.550 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.361 ns ; +; 55.002 ns ; 132.45 MHz ( period = 7.550 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.353 ns ; +; 55.010 ns ; 132.59 MHz ( period = 7.542 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.362 ns ; +; 55.035 ns ; 133.03 MHz ( period = 7.517 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.326 ns ; +; 55.039 ns ; 133.10 MHz ( period = 7.513 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.316 ns ; +; 55.047 ns ; 133.24 MHz ( period = 7.505 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.312 ns ; +; 55.078 ns ; 133.80 MHz ( period = 7.474 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.291 ns ; +; 55.090 ns ; 134.01 MHz ( period = 7.462 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.270 ns ; +; 55.094 ns ; 134.08 MHz ( period = 7.458 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.266 ns ; +; 55.101 ns ; 134.21 MHz ( period = 7.451 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.371 ns ; 7.270 ns ; +; 55.102 ns ; 134.23 MHz ( period = 7.450 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.259 ns ; +; 55.104 ns ; 134.26 MHz ( period = 7.448 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.257 ns ; +; 55.113 ns ; 134.43 MHz ( period = 7.439 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.249 ns ; +; 55.113 ns ; 134.43 MHz ( period = 7.439 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.248 ns ; +; 55.115 ns ; 134.46 MHz ( period = 7.437 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.249 ns ; +; 55.117 ns ; 134.50 MHz ( period = 7.435 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.245 ns ; +; 55.125 ns ; 134.64 MHz ( period = 7.427 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.238 ns ; +; 55.127 ns ; 134.68 MHz ( period = 7.425 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.236 ns ; +; 55.127 ns ; 134.68 MHz ( period = 7.425 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.243 ns ; +; 55.130 ns ; 134.73 MHz ( period = 7.422 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.236 ns ; +; 55.136 ns ; 134.84 MHz ( period = 7.416 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.227 ns ; +; 55.140 ns ; 134.92 MHz ( period = 7.412 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.232 ns ; +; 55.144 ns ; 134.99 MHz ( period = 7.408 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.224 ns ; +; 55.152 ns ; 135.14 MHz ( period = 7.400 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.212 ns ; +; 55.152 ns ; 135.14 MHz ( period = 7.400 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.218 ns ; +; 55.161 ns ; 135.30 MHz ( period = 7.391 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.208 ns ; +; 55.167 ns ; 135.41 MHz ( period = 7.385 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.199 ns ; +; 55.169 ns ; 135.45 MHz ( period = 7.383 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.357 ns ; 7.188 ns ; +; 55.181 ns ; 135.67 MHz ( period = 7.371 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.174 ns ; +; 55.181 ns ; 135.67 MHz ( period = 7.371 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.187 ns ; +; 55.190 ns ; 135.83 MHz ( period = 7.362 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.169 ns ; +; 55.204 ns ; 136.09 MHz ( period = 7.348 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.166 ns ; +; 55.206 ns ; 136.13 MHz ( period = 7.346 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.357 ns ; 7.151 ns ; +; 55.218 ns ; 136.35 MHz ( period = 7.334 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.137 ns ; +; 55.227 ns ; 136.52 MHz ( period = 7.325 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.145 ns ; +; 55.251 ns ; 136.97 MHz ( period = 7.301 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 7.101 ns ; +; 55.261 ns ; 137.16 MHz ( period = 7.291 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.105 ns ; +; 55.261 ns ; 137.16 MHz ( period = 7.291 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.100 ns ; +; 55.272 ns ; 137.36 MHz ( period = 7.280 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.097 ns ; +; 55.274 ns ; 137.40 MHz ( period = 7.278 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.094 ns ; +; 55.278 ns ; 137.48 MHz ( period = 7.274 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.274 ns ; 6.996 ns ; +; 55.286 ns ; 137.63 MHz ( period = 7.266 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.080 ns ; +; 55.288 ns ; 137.67 MHz ( period = 7.264 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.084 ns ; +; 55.294 ns ; 137.78 MHz ( period = 7.258 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.076 ns ; +; 55.295 ns ; 137.80 MHz ( period = 7.257 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.070 ns ; +; 55.298 ns ; 137.85 MHz ( period = 7.254 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.068 ns ; +; 55.299 ns ; 137.87 MHz ( period = 7.253 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.065 ns ; +; 55.300 ns ; 137.89 MHz ( period = 7.252 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.068 ns ; +; 55.303 ns ; 137.95 MHz ( period = 7.249 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.061 ns ; +; 55.311 ns ; 138.10 MHz ( period = 7.241 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.057 ns ; +; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.045 ns ; +; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.045 ns ; +; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.052 ns ; +; 55.317 ns ; 138.22 MHz ( period = 7.235 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.044 ns ; +; 55.319 ns ; 138.26 MHz ( period = 7.233 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.042 ns ; +; 55.322 ns ; 138.31 MHz ( period = 7.230 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.044 ns ; +; 55.323 ns ; 138.33 MHz ( period = 7.229 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.043 ns ; +; 55.323 ns ; 138.33 MHz ( period = 7.229 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.047 ns ; +; 55.324 ns ; 138.35 MHz ( period = 7.228 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.031 ns ; +; 55.326 ns ; 138.39 MHz ( period = 7.226 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.040 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 7.024 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; +; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; +; 55.331 ns ; 138.48 MHz ( period = 7.221 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.032 ns ; +; 55.331 ns ; 138.48 MHz ( period = 7.221 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.029 ns ; +; 55.332 ns ; 138.50 MHz ( period = 7.220 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.028 ns ; +; 55.332 ns ; 138.50 MHz ( period = 7.220 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.033 ns ; +; 55.333 ns ; 138.52 MHz ( period = 7.219 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.027 ns ; +; 55.333 ns ; 138.52 MHz ( period = 7.219 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.027 ns ; +; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.024 ns ; +; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.024 ns ; +; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.031 ns ; +; 55.340 ns ; 138.66 MHz ( period = 7.212 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.023 ns ; +; 55.341 ns ; 138.68 MHz ( period = 7.211 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.019 ns ; +; 55.342 ns ; 138.70 MHz ( period = 7.210 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.021 ns ; +; 55.344 ns ; 138.73 MHz ( period = 7.208 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.016 ns ; +; 55.344 ns ; 138.73 MHz ( period = 7.208 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.022 ns ; +; 55.349 ns ; 138.83 MHz ( period = 7.203 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.006 ns ; +; 55.354 ns ; 138.93 MHz ( period = 7.198 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.011 ns ; +; 55.354 ns ; 138.93 MHz ( period = 7.198 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.008 ns ; +; 55.355 ns ; 138.95 MHz ( period = 7.197 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.007 ns ; +; 55.356 ns ; 138.97 MHz ( period = 7.196 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.006 ns ; +; 55.356 ns ; 138.97 MHz ( period = 7.196 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.006 ns ; +; 55.361 ns ; 139.06 MHz ( period = 7.191 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 6.994 ns ; +; 55.364 ns ; 139.12 MHz ( period = 7.188 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.997 ns ; +; 55.364 ns ; 139.12 MHz ( period = 7.188 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 6.998 ns ; +; 55.367 ns ; 139.18 MHz ( period = 7.185 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 6.995 ns ; +; 55.367 ns ; 139.18 MHz ( period = 7.185 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.001 ns ; +; 55.374 ns ; 139.31 MHz ( period = 7.178 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.996 ns ; +; 55.376 ns ; 139.35 MHz ( period = 7.176 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.987 ns ; +; 55.379 ns ; 139.41 MHz ( period = 7.173 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.984 ns ; +; 55.383 ns ; 139.49 MHz ( period = 7.169 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.980 ns ; +; 55.383 ns ; 139.49 MHz ( period = 7.169 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.967 ns ; +; 55.384 ns ; 139.51 MHz ( period = 7.168 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.986 ns ; +; 55.386 ns ; 139.55 MHz ( period = 7.166 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.964 ns ; +; 55.386 ns ; 139.55 MHz ( period = 7.166 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.982 ns ; +; 55.387 ns ; 139.57 MHz ( period = 7.165 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.963 ns ; +; 55.387 ns ; 139.57 MHz ( period = 7.165 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.963 ns ; +; 55.389 ns ; 139.61 MHz ( period = 7.163 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.983 ns ; +; 55.393 ns ; 139.68 MHz ( period = 7.159 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.972 ns ; +; 55.399 ns ; 139.80 MHz ( period = 7.153 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.966 ns ; +; 55.403 ns ; 139.88 MHz ( period = 7.149 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.374 ns ; 6.971 ns ; +; 55.406 ns ; 139.94 MHz ( period = 7.146 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.959 ns ; +; 55.406 ns ; 139.94 MHz ( period = 7.146 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.959 ns ; +; 55.408 ns ; 139.98 MHz ( period = 7.144 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.739 ns ; 7.331 ns ; +; 55.409 ns ; 140.00 MHz ( period = 7.143 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.961 ns ; +; 55.415 ns ; 140.11 MHz ( period = 7.137 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.944 ns ; +; 55.418 ns ; 140.17 MHz ( period = 7.134 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.354 ns ; 6.936 ns ; +; 55.418 ns ; 140.17 MHz ( period = 7.134 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.932 ns ; +; 55.422 ns ; 140.25 MHz ( period = 7.130 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.946 ns ; +; 55.428 ns ; 140.37 MHz ( period = 7.124 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.938 ns ; +; 55.428 ns ; 140.37 MHz ( period = 7.124 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.935 ns ; +; 55.430 ns ; 140.41 MHz ( period = 7.122 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 6.922 ns ; +; 55.440 ns ; 140.61 MHz ( period = 7.112 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.921 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.920 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; +; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.918 ns ; +; 55.443 ns ; 140.67 MHz ( period = 7.109 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.922 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.907 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; +; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; +; 55.459 ns ; 140.98 MHz ( period = 7.093 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.909 ns ; +; 55.462 ns ; 141.04 MHz ( period = 7.090 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.902 ns ; +; 55.463 ns ; 141.06 MHz ( period = 7.089 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.901 ns ; +; 55.465 ns ; 141.10 MHz ( period = 7.087 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.901 ns ; +; 55.467 ns ; 141.14 MHz ( period = 7.085 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.897 ns ; +; 55.469 ns ; 141.18 MHz ( period = 7.083 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.895 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.895 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; +; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; +; 55.471 ns ; 141.22 MHz ( period = 7.081 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.893 ns ; +; 55.477 ns ; 141.34 MHz ( period = 7.075 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.889 ns ; +; 55.478 ns ; 141.36 MHz ( period = 7.074 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.890 ns ; +; 55.480 ns ; 141.40 MHz ( period = 7.072 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.888 ns ; +; 55.483 ns ; 141.46 MHz ( period = 7.069 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.885 ns ; +; 55.486 ns ; 141.52 MHz ( period = 7.066 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.880 ns ; +; 55.487 ns ; 141.54 MHz ( period = 7.065 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.883 ns ; +; 55.490 ns ; 141.60 MHz ( period = 7.062 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.278 ns ; 6.788 ns ; +; 55.490 ns ; 141.60 MHz ( period = 7.062 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.876 ns ; +; 55.491 ns ; 141.62 MHz ( period = 7.061 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.877 ns ; +; 55.492 ns ; 141.64 MHz ( period = 7.060 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.874 ns ; +; 55.494 ns ; 141.68 MHz ( period = 7.058 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.872 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.354 ns ; 6.859 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; +; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; +; 55.496 ns ; 141.72 MHz ( period = 7.056 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.863 ns ; +; 55.497 ns ; 141.74 MHz ( period = 7.055 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.866 ns ; +; 55.499 ns ; 141.78 MHz ( period = 7.053 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.860 ns ; +; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.859 ns ; +; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.861 ns ; +; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.859 ns ; +; 55.501 ns ; 141.82 MHz ( period = 7.051 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.869 ns ; +; 55.503 ns ; 141.86 MHz ( period = 7.049 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.867 ns ; +; 55.506 ns ; 141.92 MHz ( period = 7.046 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.864 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 6.845 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.856 ns ; +; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; +; 55.508 ns ; 141.96 MHz ( period = 7.044 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.855 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -4.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.928 ns ; 3.687 ns ; +; -4.573 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.921 ns ; 3.652 ns ; +; -4.568 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.642 ns ; +; -4.562 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.915 ns ; 3.647 ns ; +; -4.553 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.635 ns ; +; -4.549 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.631 ns ; +; -4.541 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.928 ns ; 3.613 ns ; +; -4.533 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.610 ns ; +; -4.526 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.608 ns ; +; -4.479 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.898 ns ; +; -4.440 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.141 ns ; +; -4.440 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.517 ns ; +; -4.413 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.114 ns ; +; -4.409 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.486 ns ; +; -4.407 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.916 ns ; 3.491 ns ; +; -4.406 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.914 ns ; 3.492 ns ; +; -4.394 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.468 ns ; +; -4.391 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.465 ns ; +; -4.391 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.466 ns ; +; -4.386 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.461 ns ; +; -4.381 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.458 ns ; +; -4.378 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.455 ns ; +; -4.372 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.447 ns ; +; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.447 ns ; +; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.447 ns ; +; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.445 ns ; +; -4.369 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 4.068 ns ; +; -4.367 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.444 ns ; +; -4.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.441 ns ; +; -4.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.441 ns ; +; -4.364 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.441 ns ; +; -4.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 4.063 ns ; +; -4.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.440 ns ; +; -4.361 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.436 ns ; +; -4.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.434 ns ; +; -4.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.435 ns ; +; -4.357 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.431 ns ; +; -4.356 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.433 ns ; +; -4.353 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.428 ns ; +; -4.353 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.428 ns ; +; -4.351 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.931 ns ; 3.420 ns ; +; -4.348 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.426 ns ; +; -4.318 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.916 ns ; 3.402 ns ; +; -4.316 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.919 ns ; 3.397 ns ; +; -4.308 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 4.008 ns ; +; -4.306 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.725 ns ; +; -4.305 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.379 ns ; +; -4.301 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.002 ns ; +; -4.299 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.376 ns ; +; -4.298 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.924 ns ; 3.374 ns ; +; -4.297 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.374 ns ; +; -4.294 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.372 ns ; +; -4.293 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.370 ns ; +; -4.293 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.371 ns ; +; -4.290 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.365 ns ; +; -4.289 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.366 ns ; +; -4.289 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.364 ns ; +; -4.288 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.363 ns ; +; -4.279 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.356 ns ; +; -4.278 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.355 ns ; +; -4.277 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.354 ns ; +; -4.273 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.347 ns ; +; -4.271 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.972 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.970 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.343 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.346 ns ; +; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.346 ns ; +; -4.268 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.345 ns ; +; -4.268 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.345 ns ; +; -4.267 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.344 ns ; +; -4.266 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.343 ns ; +; -4.264 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.341 ns ; +; -4.264 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.341 ns ; +; -4.262 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.339 ns ; +; -4.262 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.339 ns ; +; -4.259 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.960 ns ; +; -4.259 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.334 ns ; +; -4.258 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.332 ns ; +; -4.256 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.333 ns ; +; -4.256 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.333 ns ; +; -4.255 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.329 ns ; +; -4.255 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.330 ns ; +; -4.253 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.330 ns ; +; -4.253 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.327 ns ; +; -4.251 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.328 ns ; +; -4.248 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.325 ns ; +; -4.247 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.324 ns ; +; -4.246 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.323 ns ; +; -4.245 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.319 ns ; +; -4.243 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.944 ns ; +; -4.241 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.316 ns ; +; -4.236 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.310 ns ; +; -4.230 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.929 ns ; +; -4.229 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.928 ns ; +; -4.219 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.919 ns ; +; -4.217 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.292 ns ; +; -4.215 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.916 ns ; +; -4.203 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.904 ns ; +; -4.199 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.899 ns ; +; -4.195 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.614 ns ; +; -4.194 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.269 ns ; +; -4.190 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.257 ns ; +; -4.188 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.887 ns ; +; -4.188 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.624 ns ; 3.564 ns ; +; -4.179 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.931 ns ; 3.248 ns ; +; -4.175 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.876 ns ; +; -4.172 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.591 ns ; +; -4.156 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.855 ns ; +; -4.154 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.551 ns ; +; -4.149 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.850 ns ; +; -4.148 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.847 ns ; +; -4.143 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.540 ns ; +; -4.142 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.612 ns ; 3.530 ns ; +; -4.140 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.624 ns ; 3.516 ns ; +; -4.139 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.216 ns ; +; -4.138 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.838 ns ; +; -4.137 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.211 ns ; +; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; +; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; +; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; +; -4.134 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.211 ns ; +; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.210 ns ; +; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.208 ns ; +; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.208 ns ; +; -4.130 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.204 ns ; +; -4.130 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.205 ns ; +; -4.128 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.205 ns ; +; -4.127 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.202 ns ; +; -4.125 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.199 ns ; +; -4.124 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.191 ns ; +; -4.113 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.190 ns ; +; -4.113 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.190 ns ; +; -4.113 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.616 ns ; 3.497 ns ; +; -4.109 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.186 ns ; +; -4.108 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.505 ns ; +; -4.104 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.171 ns ; +; -4.102 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.176 ns ; +; -4.101 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.802 ns ; +; -4.100 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.519 ns ; +; -4.098 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.936 ns ; 3.162 ns ; +; -4.098 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.495 ns ; +; -4.097 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.796 ns ; +; -4.092 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.793 ns ; +; -4.088 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.507 ns ; +; -4.083 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.480 ns ; +; -4.078 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.779 ns ; +; -4.069 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.306 ns ; 3.763 ns ; +; -4.068 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.612 ns ; 3.456 ns ; +; -4.068 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.306 ns ; 3.762 ns ; +; -4.064 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.307 ns ; 3.757 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.613 ns ; 3.436 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.442 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.442 ns ; +; -4.041 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.308 ns ; 3.733 ns ; +; -4.038 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.615 ns ; 3.423 ns ; +; -4.034 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.938 ns ; 3.096 ns ; +; -4.034 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.943 ns ; 3.091 ns ; +; -4.034 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.734 ns ; +; -4.024 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.613 ns ; 3.411 ns ; +; -4.019 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.438 ns ; +; -4.016 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.093 ns ; +; -4.015 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.092 ns ; +; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.091 ns ; +; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.091 ns ; +; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.089 ns ; +; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; +; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; +; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; +; -4.011 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.088 ns ; +; -4.011 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.085 ns ; +; -4.009 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.084 ns ; +; -4.006 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.080 ns ; +; -4.006 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.403 ns ; +; -4.005 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.080 ns ; +; -4.004 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.703 ns ; +; -4.000 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.419 ns ; +; -3.998 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.075 ns ; +; -3.998 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.699 ns ; +; -3.996 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.073 ns ; +; -3.995 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.392 ns ; +; -3.993 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.070 ns ; +; -3.991 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.068 ns ; +; -3.989 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.938 ns ; 3.051 ns ; +; -3.989 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.610 ns ; 3.379 ns ; +; -3.988 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.065 ns ; +; -3.986 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.061 ns ; +; -3.986 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.061 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.060 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.059 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.059 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.060 ns ; +; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.058 ns ; +; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.059 ns ; +; -3.983 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.057 ns ; +; -3.982 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.056 ns ; +; -3.981 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.055 ns ; +; -3.972 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.369 ns ; +; -3.970 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.037 ns ; +; -3.966 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.666 ns ; +; -3.954 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.935 ns ; 3.019 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -2.673 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.814 ns ; 3.487 ns ; +; -2.447 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 3.530 ns ; +; -2.348 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_BANK_OK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.155 ns ; +; -2.346 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.153 ns ; +; -2.275 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.082 ns ; +; -2.254 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.061 ns ; +; -2.243 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.138 ns ; 3.381 ns ; +; -2.194 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.100 ns ; 3.294 ns ; +; -2.187 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 3.262 ns ; +; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.239 ns ; +; -2.024 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.169 ns ; +; -2.006 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.151 ns ; +; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.132 ns ; 3.125 ns ; +; -1.990 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_FIFO_WRE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.797 ns ; +; -1.911 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.140 ns ; 3.051 ns ; +; -1.896 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 2.986 ns ; +; -1.895 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 2.985 ns ; +; -1.873 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7F ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.680 ns ; +; -1.871 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.678 ns ; +; -1.838 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; -1.306 ns ; 0.532 ns ; +; -1.834 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.131 ns ; 2.965 ns ; +; -1.828 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.907 ns ; +; -1.827 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.906 ns ; +; -1.824 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.903 ns ; +; -1.800 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.131 ns ; 2.931 ns ; +; -1.800 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.879 ns ; +; -1.765 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.910 ns ; +; -1.763 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.132 ns ; 2.895 ns ; +; -1.755 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.136 ns ; 2.891 ns ; +; -1.647 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.133 ns ; 2.780 ns ; +; -1.646 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.133 ns ; 2.779 ns ; +; -1.641 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.770 ns ; +; -1.610 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.739 ns ; +; -1.593 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.152 ns ; 2.745 ns ; +; -1.556 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.134 ns ; 2.690 ns ; +; -1.553 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.682 ns ; +; -1.470 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.612 ns ; +; -1.465 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.594 ns ; +; -1.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.127 ns ; 2.590 ns ; +; -1.451 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.596 ns ; +; -1.441 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.586 ns ; +; -1.436 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.136 ns ; 2.572 ns ; +; -1.413 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.555 ns ; +; -1.361 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.506 ns ; +; -1.341 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.486 ns ; +; -1.329 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.404 ns ; +; -1.327 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.410 ns ; +; -1.326 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.410 ns ; +; -1.302 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.385 ns ; +; -1.298 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.126 ns ; 2.424 ns ; +; -1.271 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 2.348 ns ; +; -1.252 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.335 ns ; +; -1.216 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.358 ns ; +; -1.202 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.277 ns ; +; -1.202 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.277 ns ; +; -1.181 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.264 ns ; +; -1.167 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_CB8 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.246 ns ; +; -1.162 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8F ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.241 ns ; +; -1.139 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.130 ns ; 2.269 ns ; +; -1.102 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.186 ns ; +; -1.077 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.140 ns ; 2.217 ns ; +; -1.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.151 ns ; 2.199 ns ; +; -1.047 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.131 ns ; +; -0.910 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.123 ns ; 2.033 ns ; +; -0.901 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.992 ns ; +; -0.827 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.917 ns ; +; -0.750 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.841 ns ; +; -0.750 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.841 ns ; +; -0.741 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.832 ns ; +; -0.642 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.730 ns ; +; -0.623 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.711 ns ; +; -0.616 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.704 ns ; +; -0.600 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.688 ns ; +; -0.596 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.087 ns ; 1.683 ns ; +; -0.413 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 1.490 ns ; +; -0.410 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 1.487 ns ; +; -0.199 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.289 ns ; +; -0.193 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2B ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.283 ns ; +; -0.191 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.282 ns ; +; -0.186 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.175 ns ; 4.361 ns ; +; -0.183 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.274 ns ; +; -0.102 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 3.040 ns ; 3.142 ns ; +; -0.068 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.171 ns ; 4.239 ns ; +; -0.062 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.175 ns ; 4.237 ns ; +; -0.041 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.162 ns ; 4.203 ns ; +; -0.024 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.181 ns ; 4.205 ns ; +; 0.003 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.168 ns ; 4.165 ns ; +; 0.039 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.173 ns ; 4.134 ns ; +; 0.059 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.032 ns ; +; 0.073 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.171 ns ; 4.098 ns ; +; 0.080 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.167 ns ; 4.087 ns ; +; 0.108 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.181 ns ; 4.073 ns ; +; 0.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.168 ns ; 4.045 ns ; +; 0.165 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.182 ns ; 4.017 ns ; +; 0.166 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.173 ns ; 4.007 ns ; +; 0.194 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.167 ns ; 3.973 ns ; +; 0.201 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.162 ns ; 3.961 ns ; +; 0.250 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.464 ns ; 4.214 ns ; +; 0.301 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.522 ns ; 4.221 ns ; +; 0.306 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.483 ns ; 4.177 ns ; +; 0.375 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.514 ns ; 4.139 ns ; +; 0.401 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.475 ns ; 4.074 ns ; +; 0.451 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.182 ns ; 3.731 ns ; +; 0.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.477 ns ; 4.023 ns ; +; 0.467 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.473 ns ; 4.006 ns ; +; 0.509 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.503 ns ; 3.994 ns ; +; 0.514 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.469 ns ; 3.955 ns ; +; 0.539 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.484 ns ; 3.945 ns ; +; 0.568 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.823 ns ; +; 0.576 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.470 ns ; 3.894 ns ; +; 0.579 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.804 ns ; +; 0.580 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.408 ns ; 3.828 ns ; +; 0.619 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.768 ns ; +; 0.677 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.516 ns ; 3.839 ns ; +; 0.695 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.508 ns ; 3.813 ns ; +; 0.773 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.512 ns ; 3.739 ns ; +; 0.800 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.587 ns ; +; 0.805 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.582 ns ; +; 0.810 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.509 ns ; 3.699 ns ; +; 0.818 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.523 ns ; 3.705 ns ; +; 0.834 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.212 ns ; 3.378 ns ; +; 0.838 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.545 ns ; +; 0.840 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.551 ns ; +; 0.841 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.551 ns ; +; 0.933 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.454 ns ; +; 0.965 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.418 ns ; +; 0.965 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.418 ns ; +; 1.026 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.365 ns ; +; 1.038 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 3.347 ns ; +; 1.057 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.334 ns ; +; 1.110 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.057 ns ; 2.947 ns ; +; 1.120 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.272 ns ; +; 1.147 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.244 ns ; +; 1.153 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 3.245 ns ; +; 1.207 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.185 ns ; +; 1.266 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 3.133 ns ; +; 1.344 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.057 ns ; 2.713 ns ; +; 1.374 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 3.024 ns ; +; 1.417 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.982 ns ; +; 1.417 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.982 ns ; +; 1.426 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.973 ns ; +; 1.426 ns ; 162.63 MHz ( period = 6.149 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.936 ns ; +; 1.427 ns ; 162.65 MHz ( period = 6.148 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.935 ns ; +; 1.481 ns ; 164.10 MHz ( period = 6.094 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.881 ns ; +; 1.482 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 2.916 ns ; +; 1.484 ns ; 164.18 MHz ( period = 6.091 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.878 ns ; +; 1.526 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 3.055 ns ; 1.529 ns ; +; 1.527 ns ; 165.34 MHz ( period = 6.048 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.835 ns ; +; 1.540 ns ; 165.70 MHz ( period = 6.035 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.822 ns ; +; 1.543 ns ; 165.78 MHz ( period = 6.032 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.819 ns ; +; 1.582 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.858 ns ; 3.276 ns ; +; 1.589 ns ; 167.06 MHz ( period = 5.986 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.773 ns ; +; 1.598 ns ; 167.31 MHz ( period = 5.977 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.764 ns ; +; 1.601 ns ; 167.39 MHz ( period = 5.974 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.761 ns ; +; 1.656 ns ; 168.95 MHz ( period = 5.919 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.706 ns ; +; 1.676 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.850 ns ; 3.174 ns ; +; 1.677 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.147 ns ; +; 1.679 ns ; 169.61 MHz ( period = 5.896 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.700 ns ; +; 1.680 ns ; 169.64 MHz ( period = 5.895 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.699 ns ; +; 1.686 ns ; 169.81 MHz ( period = 5.889 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.668 ns ; +; 1.687 ns ; 169.84 MHz ( period = 5.888 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.667 ns ; +; 1.714 ns ; 170.62 MHz ( period = 5.861 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.648 ns ; +; 1.734 ns ; 171.20 MHz ( period = 5.841 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.645 ns ; +; 1.737 ns ; 171.29 MHz ( period = 5.838 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.642 ns ; +; 1.738 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.841 ns ; 3.103 ns ; +; 1.741 ns ; 171.41 MHz ( period = 5.834 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.613 ns ; +; 1.744 ns ; 171.50 MHz ( period = 5.831 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.610 ns ; +; 1.746 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.841 ns ; 3.095 ns ; +; 1.747 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.865 ns ; 3.118 ns ; +; 1.750 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.866 ns ; 3.116 ns ; +; 1.756 ns ; 171.85 MHz ( period = 5.819 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[6] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.606 ns ; +; 1.760 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.865 ns ; 3.105 ns ; +; 1.779 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.045 ns ; +; 1.780 ns ; 172.56 MHz ( period = 5.795 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.599 ns ; +; 1.787 ns ; 172.77 MHz ( period = 5.788 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.567 ns ; +; 1.792 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.032 ns ; +; 1.793 ns ; 172.95 MHz ( period = 5.782 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.586 ns ; +; 1.796 ns ; 173.04 MHz ( period = 5.779 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.583 ns ; +; 1.800 ns ; 173.16 MHz ( period = 5.775 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.554 ns ; +; 1.803 ns ; 173.25 MHz ( period = 5.772 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.551 ns ; +; 1.805 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 2.580 ns ; +; 1.808 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 2.577 ns ; +; 1.812 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.831 ns ; 3.019 ns ; +; 1.829 ns ; 174.03 MHz ( period = 5.746 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.525 ns ; +; 1.830 ns ; 174.06 MHz ( period = 5.745 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.524 ns ; +; 1.840 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.559 ns ; +; 1.842 ns ; 174.43 MHz ( period = 5.733 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.537 ns ; +; 1.842 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.557 ns ; +; 1.842 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 2.982 ns ; +; 1.845 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.847 ns ; 3.002 ns ; +; 1.847 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.847 ns ; 3.000 ns ; +; 1.849 ns ; 174.64 MHz ( period = 5.726 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.505 ns ; +; 1.851 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 2.547 ns ; +; 1.851 ns ; 174.70 MHz ( period = 5.724 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.528 ns ; +; 1.854 ns ; 174.79 MHz ( period = 5.721 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.525 ns ; +; 1.858 ns ; 174.92 MHz ( period = 5.717 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.496 ns ; +; 1.861 ns ; 175.01 MHz ( period = 5.714 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.493 ns ; +; 1.865 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.826 ns ; 2.961 ns ; +; 1.873 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.829 ns ; 2.956 ns ; +; 1.881 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.829 ns ; 2.948 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; ++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 2.965 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.639 ns ; +; 2.966 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.638 ns ; +; 2.967 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.637 ns ; +; 2.968 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.636 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; +; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; +; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; +; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; +; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; ++----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; ++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 5.299 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.118 ns ; 0.819 ns ; +; 5.479 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.637 ns ; +; 5.480 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.636 ns ; +; 5.606 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.510 ns ; +; 5.608 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.508 ns ; ++----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; 1.672 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 3.636 ns ; +; 1.683 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.304 ns ; 3.621 ns ; +; 1.703 ns ; 170.30 MHz ( period = 5.872 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 5.190 ns ; +; 1.806 ns ; 173.34 MHz ( period = 5.769 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.887 ns ; 5.081 ns ; +; 1.842 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.327 ns ; 3.485 ns ; +; 1.881 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.428 ns ; +; 1.904 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.325 ns ; 3.421 ns ; +; 1.914 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.395 ns ; +; 1.923 ns ; 176.93 MHz ( period = 5.652 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 4.970 ns ; +; 2.000 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 3.308 ns ; +; 2.018 ns ; 179.95 MHz ( period = 5.557 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.883 ns ; 4.865 ns ; +; 2.034 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.321 ns ; 3.287 ns ; +; 2.040 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 3.253 ns ; +; 2.068 ns ; 181.59 MHz ( period = 5.507 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.887 ns ; 4.819 ns ; +; 2.105 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.302 ns ; 3.197 ns ; +; 2.112 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.488 ns ; 2.376 ns ; +; 2.131 ns ; 183.69 MHz ( period = 5.444 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.896 ns ; 4.765 ns ; +; 2.141 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 3.175 ns ; +; 2.151 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.307 ns ; 3.156 ns ; +; 2.155 ns ; 184.50 MHz ( period = 5.420 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.900 ns ; 4.745 ns ; +; 2.159 ns ; 184.64 MHz ( period = 5.416 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.891 ns ; 4.732 ns ; +; 2.166 ns ; 184.88 MHz ( period = 5.409 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.712 ns ; +; 2.178 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.131 ns ; +; 2.202 ns ; 186.12 MHz ( period = 5.373 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 4.691 ns ; +; 2.203 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 3.109 ns ; +; 2.207 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.335 ns ; 3.128 ns ; +; 2.238 ns ; 187.37 MHz ( period = 5.337 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.640 ns ; +; 2.242 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.317 ns ; 3.075 ns ; +; 2.260 ns ; 188.15 MHz ( period = 5.315 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.891 ns ; 4.631 ns ; +; 2.265 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.428 ns ; 2.163 ns ; +; 2.273 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.492 ns ; 2.219 ns ; +; 2.298 ns ; 189.50 MHz ( period = 5.277 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.901 ns ; 4.603 ns ; +; 2.325 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.991 ns ; +; 2.338 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.383 ns ; 3.045 ns ; +; 2.357 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.321 ns ; 2.964 ns ; +; 2.370 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.302 ns ; 2.932 ns ; +; 2.376 ns ; 192.34 MHz ( period = 5.199 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.883 ns ; 4.507 ns ; +; 2.385 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 3.250 ns ; +; 2.410 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.906 ns ; +; 2.417 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.307 ns ; 2.890 ns ; +; 2.434 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.373 ns ; 2.939 ns ; +; 2.445 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.495 ns ; 2.050 ns ; +; 2.447 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 2.865 ns ; +; 2.470 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.175 ns ; +; 2.502 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.652 ns ; 3.150 ns ; +; 2.509 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 3.134 ns ; +; 2.516 ns ; 197.67 MHz ( period = 5.059 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.725 ns ; +; 2.517 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 2.791 ns ; +; 2.520 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 2.773 ns ; +; 2.523 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.122 ns ; +; 2.531 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 3.108 ns ; +; 2.548 ns ; 198.93 MHz ( period = 5.027 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.248 ns ; 4.700 ns ; +; 2.549 ns ; 198.97 MHz ( period = 5.026 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.329 ns ; +; 2.550 ns ; 199.00 MHz ( period = 5.025 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.901 ns ; 4.351 ns ; +; 2.550 ns ; 199.00 MHz ( period = 5.025 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.239 ns ; 4.689 ns ; +; 2.561 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 2.814 ns ; +; 2.567 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.290 ns ; 2.723 ns ; +; 2.569 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.317 ns ; 2.748 ns ; +; 2.569 ns ; 199.76 MHz ( period = 5.006 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.231 ns ; 4.662 ns ; +; 2.570 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 2.805 ns ; +; 2.571 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 3.072 ns ; +; 2.572 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.306 ns ; 2.734 ns ; +; 2.597 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.719 ns ; +; 2.603 ns ; 201.13 MHz ( period = 4.972 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.638 ns ; +; 2.614 ns ; 201.57 MHz ( period = 4.961 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.239 ns ; 4.625 ns ; +; 2.616 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.377 ns ; 2.761 ns ; +; 2.622 ns ; 201.90 MHz ( period = 4.953 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 4.325 ns ; +; 2.641 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.004 ns ; +; 2.685 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.330 ns ; 2.645 ns ; +; 2.690 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.949 ns ; +; 2.695 ns ; 204.92 MHz ( period = 4.880 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.254 ns ; +; 2.697 ns ; 205.00 MHz ( period = 4.878 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.529 ns ; +; 2.708 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.648 ns ; 2.940 ns ; +; 2.716 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 2.596 ns ; +; 2.717 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.913 ns ; +; 2.718 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.912 ns ; +; 2.724 ns ; 206.14 MHz ( period = 4.851 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.517 ns ; +; 2.733 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.356 ns ; 2.623 ns ; +; 2.734 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.911 ns ; +; 2.734 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.381 ns ; 2.647 ns ; +; 2.734 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.559 ns ; 1.825 ns ; +; 2.751 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.377 ns ; 2.626 ns ; +; 2.758 ns ; 207.60 MHz ( period = 4.817 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.244 ns ; 4.486 ns ; +; 2.761 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.874 ns ; +; 2.761 ns ; 207.73 MHz ( period = 4.814 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.188 ns ; +; 2.764 ns ; 207.86 MHz ( period = 4.811 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.185 ns ; +; 2.768 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.652 ns ; 2.884 ns ; +; 2.771 ns ; 208.16 MHz ( period = 4.804 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.235 ns ; 4.464 ns ; +; 2.776 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 2.867 ns ; +; 2.778 ns ; 208.46 MHz ( period = 4.797 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.948 ns ; 4.170 ns ; +; 2.780 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.855 ns ; +; 2.793 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.852 ns ; +; 2.793 ns ; 209.12 MHz ( period = 4.782 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.433 ns ; +; 2.797 ns ; 209.29 MHz ( period = 4.778 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.429 ns ; +; 2.798 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.378 ns ; 2.580 ns ; +; 2.807 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.779 ns ; 2.972 ns ; +; 2.808 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.374 ns ; 2.566 ns ; +; 2.815 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.373 ns ; 2.558 ns ; +; 2.821 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.818 ns ; +; 2.838 ns ; 211.10 MHz ( period = 4.737 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.231 ns ; 4.393 ns ; +; 2.839 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 2.804 ns ; +; 2.846 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 2.447 ns ; +; 2.851 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.334 ns ; 2.483 ns ; +; 2.862 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.454 ns ; +; 2.909 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.736 ns ; +; 2.935 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.423 ns ; +; 2.937 ns ; 215.61 MHz ( period = 4.638 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 4.006 ns ; +; 2.951 ns ; 216.26 MHz ( period = 4.624 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 3.998 ns ; +; 2.954 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.685 ns ; +; 2.960 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.655 ns ; 2.695 ns ; +; 2.963 ns ; 216.83 MHz ( period = 4.612 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 3.980 ns ; +; 2.969 ns ; 217.11 MHz ( period = 4.606 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.978 ns ; +; 2.977 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.648 ns ; 2.671 ns ; +; 2.983 ns ; 217.77 MHz ( period = 4.592 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.235 ns ; 4.252 ns ; +; 2.984 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.646 ns ; +; 2.985 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.645 ns ; +; 2.988 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.779 ns ; 2.791 ns ; +; 3.004 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 2.358 ns ; +; 3.005 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.364 ns ; 2.359 ns ; +; 3.010 ns ; 219.06 MHz ( period = 4.565 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.292 ns ; 4.282 ns ; +; 3.018 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.653 ns ; 2.635 ns ; +; 3.027 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.608 ns ; +; 3.042 ns ; 220.60 MHz ( period = 4.533 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.294 ns ; 4.252 ns ; +; 3.047 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.729 ns ; 2.682 ns ; +; 3.051 ns ; 221.04 MHz ( period = 4.524 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.249 ns ; 4.198 ns ; +; 3.058 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.354 ns ; 2.296 ns ; +; 3.061 ns ; 221.53 MHz ( period = 4.514 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.249 ns ; 4.188 ns ; +; 3.074 ns ; 222.17 MHz ( period = 4.501 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.946 ns ; 3.872 ns ; +; 3.096 ns ; 223.26 MHz ( period = 4.479 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.851 ns ; +; 3.115 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.246 ns ; +; 3.127 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.234 ns ; +; 3.131 ns ; 225.02 MHz ( period = 4.444 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 3.812 ns ; +; 3.141 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.325 ns ; 2.184 ns ; +; 3.143 ns ; 225.63 MHz ( period = 4.432 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 4.152 ns ; +; 3.151 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.479 ns ; +; 3.158 ns ; 226.40 MHz ( period = 4.417 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.292 ns ; 4.134 ns ; +; 3.159 ns ; 226.45 MHz ( period = 4.416 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.132 ns ; +; 3.162 ns ; 226.60 MHz ( period = 4.413 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 4.133 ns ; +; 3.163 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.780 ns ; 2.617 ns ; +; 3.173 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.680 ns ; 2.507 ns ; +; 3.181 ns ; 227.58 MHz ( period = 4.394 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.944 ns ; 3.763 ns ; +; 3.192 ns ; 228.15 MHz ( period = 4.383 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.755 ns ; +; 3.199 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.431 ns ; +; 3.207 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.671 ns ; 2.464 ns ; +; 3.208 ns ; 228.99 MHz ( period = 4.367 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.946 ns ; 3.738 ns ; +; 3.209 ns ; 229.04 MHz ( period = 4.366 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.944 ns ; 3.735 ns ; +; 3.225 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.470 ns ; +; 3.226 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.655 ns ; 2.429 ns ; +; 3.233 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 2.126 ns ; +; 3.236 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.125 ns ; +; 3.251 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.107 ns ; +; 3.253 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.355 ns ; 2.102 ns ; +; 3.261 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.097 ns ; +; 3.262 ns ; 231.86 MHz ( period = 4.313 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 4.035 ns ; +; 3.263 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.363 ns ; 2.100 ns ; +; 3.266 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.363 ns ; 2.097 ns ; +; 3.271 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 2.091 ns ; +; 3.277 ns ; 232.67 MHz ( period = 4.298 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.014 ns ; +; 3.279 ns ; 232.77 MHz ( period = 4.296 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.012 ns ; +; 3.282 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.653 ns ; 2.371 ns ; +; 3.307 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.383 ns ; 2.076 ns ; +; 3.346 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.352 ns ; +; 3.351 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.344 ns ; +; 3.365 ns ; 237.53 MHz ( period = 4.210 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.296 ns ; 3.931 ns ; +; 3.387 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 1.974 ns ; +; 3.390 ns ; 238.95 MHz ( period = 4.185 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.294 ns ; 3.904 ns ; +; 3.410 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 1.952 ns ; +; 3.415 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.283 ns ; +; 3.429 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 1.929 ns ; +; 3.438 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 1.937 ns ; +; 3.450 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.700 ns ; 2.250 ns ; +; 3.458 ns ; 242.90 MHz ( period = 4.117 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 3.837 ns ; +; 3.459 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.239 ns ; +; 3.461 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.781 ns ; 2.320 ns ; +; 3.474 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.380 ns ; 1.906 ns ; +; 3.477 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 1.882 ns ; +; 3.492 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.203 ns ; +; 3.495 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.700 ns ; 2.205 ns ; +; 3.499 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 1.860 ns ; +; 3.504 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 1.857 ns ; +; 3.558 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.141 ns ; +; 3.575 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 2.122 ns ; +; 3.602 ns ; 251.70 MHz ( period = 3.973 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 3.693 ns ; +; 3.610 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.089 ns ; +; 3.614 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.084 ns ; +; 3.616 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.701 ns ; 2.085 ns ; +; 3.617 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.696 ns ; 2.079 ns ; +; 3.620 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 2.077 ns ; +; 3.625 ns ; 253.16 MHz ( period = 3.950 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 3.672 ns ; +; 3.640 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.059 ns ; +; 3.649 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.726 ns ; 2.077 ns ; +; 3.657 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.042 ns ; +; 3.663 ns ; 255.62 MHz ( period = 3.912 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 3.634 ns ; +; 3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.696 ns ; 2.032 ns ; +; 3.673 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.703 ns ; 2.030 ns ; +; 3.675 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.024 ns ; +; 3.708 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.702 ns ; 1.994 ns ; +; 3.720 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.703 ns ; 1.983 ns ; +; 3.738 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 1.959 ns ; +; 3.825 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 1.874 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -1.712 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 1.118 ns ; 2.830 ns ; +; -1.664 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.656 ns ; +; -1.597 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.589 ns ; +; -1.597 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.589 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; +; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; +; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; +; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; +; -1.333 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.319 ns ; +; -1.333 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.319 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; +; -1.278 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.264 ns ; +; -1.278 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.264 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; +; -1.248 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.989 ns ; 2.237 ns ; +; -1.243 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.989 ns ; 2.232 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; +; 4.485 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 6.311 ns ; 6.117 ns ; 1.632 ns ; +; 6.612 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.393 ns ; 3.781 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; +; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; +; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; +; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; +; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; +; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; +; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; +; 6.843 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.545 ns ; 3.702 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; +; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; +; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; +; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; +; 7.011 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.390 ns ; 3.379 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; +; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; +; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; +; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; +; 7.111 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.514 ns ; 3.403 ns ; +; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; +; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; +; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; +; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; +; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; +; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; +; 7.264 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.548 ns ; 3.284 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; +; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; +; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; +; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ +; -4.294 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.607 ns ; 3.687 ns ; +; -4.252 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.600 ns ; 3.652 ns ; +; -4.247 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.642 ns ; +; -4.241 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.594 ns ; 3.647 ns ; +; -4.232 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.635 ns ; +; -4.228 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.631 ns ; +; -4.220 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.607 ns ; 3.613 ns ; +; -4.212 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.610 ns ; +; -4.205 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.608 ns ; +; -4.158 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.898 ns ; +; -4.119 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.141 ns ; +; -4.119 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.517 ns ; +; -4.092 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.114 ns ; +; -4.088 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.486 ns ; +; -4.086 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.595 ns ; 3.491 ns ; +; -4.085 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.593 ns ; 3.492 ns ; +; -4.073 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.468 ns ; +; -4.070 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.465 ns ; +; -4.070 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.466 ns ; +; -4.065 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.461 ns ; +; -4.060 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.458 ns ; +; -4.057 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.455 ns ; +; -4.051 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.447 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.447 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.447 ns ; +; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.445 ns ; +; -4.048 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 4.068 ns ; +; -4.046 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.444 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.441 ns ; +; -4.045 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.441 ns ; +; -4.043 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.441 ns ; +; -4.042 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 4.063 ns ; +; -4.042 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.440 ns ; +; -4.040 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.436 ns ; +; -4.039 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.434 ns ; +; -4.039 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.435 ns ; +; -4.036 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.431 ns ; +; -4.035 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.433 ns ; +; -4.032 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.428 ns ; +; -4.032 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.428 ns ; +; -4.030 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.610 ns ; 3.420 ns ; +; -4.027 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.426 ns ; +; -3.997 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.595 ns ; 3.402 ns ; +; -3.995 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.598 ns ; 3.397 ns ; +; -3.987 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 4.008 ns ; +; -3.985 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.725 ns ; +; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.379 ns ; +; -3.980 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.002 ns ; +; -3.978 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.376 ns ; +; -3.977 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.603 ns ; 3.374 ns ; +; -3.976 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.374 ns ; +; -3.973 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.372 ns ; +; -3.972 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.370 ns ; +; -3.972 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.371 ns ; +; -3.969 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.365 ns ; +; -3.968 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.366 ns ; +; -3.968 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.364 ns ; +; -3.967 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.363 ns ; +; -3.958 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.356 ns ; +; -3.957 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.355 ns ; +; -3.956 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.354 ns ; +; -3.952 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.347 ns ; +; -3.950 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.972 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.970 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.343 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.346 ns ; +; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.346 ns ; +; -3.947 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.345 ns ; +; -3.947 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.345 ns ; +; -3.946 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.344 ns ; +; -3.945 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.343 ns ; +; -3.943 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.341 ns ; +; -3.943 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.341 ns ; +; -3.941 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.339 ns ; +; -3.941 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.339 ns ; +; -3.938 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.960 ns ; +; -3.938 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.334 ns ; +; -3.937 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.332 ns ; +; -3.935 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.333 ns ; +; -3.935 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.333 ns ; +; -3.934 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.329 ns ; +; -3.934 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.330 ns ; +; -3.932 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.330 ns ; +; -3.932 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.327 ns ; +; -3.930 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.328 ns ; +; -3.927 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.325 ns ; +; -3.926 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.324 ns ; +; -3.925 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.323 ns ; +; -3.924 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.319 ns ; +; -3.922 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.944 ns ; +; -3.920 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.316 ns ; +; -3.915 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.310 ns ; +; -3.909 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.929 ns ; +; -3.908 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.928 ns ; +; -3.898 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.919 ns ; +; -3.896 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.292 ns ; +; -3.894 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.916 ns ; +; -3.882 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.904 ns ; +; -3.878 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.899 ns ; +; -3.874 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.614 ns ; +; -3.873 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.269 ns ; +; -3.869 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.257 ns ; +; -3.867 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.887 ns ; +; -3.867 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.303 ns ; 3.564 ns ; +; -3.858 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.610 ns ; 3.248 ns ; +; -3.854 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.876 ns ; +; -3.851 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.591 ns ; +; -3.835 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.855 ns ; +; -3.833 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.551 ns ; +; -3.828 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.850 ns ; +; -3.827 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.847 ns ; +; -3.822 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.540 ns ; +; -3.821 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.291 ns ; 3.530 ns ; +; -3.819 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.303 ns ; 3.516 ns ; +; -3.818 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.216 ns ; +; -3.817 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.838 ns ; +; -3.816 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.211 ns ; +; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; +; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; +; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; +; -3.813 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.211 ns ; +; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.210 ns ; +; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.208 ns ; +; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.208 ns ; +; -3.809 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.204 ns ; +; -3.809 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.205 ns ; +; -3.807 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.205 ns ; +; -3.806 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.202 ns ; +; -3.804 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.199 ns ; +; -3.803 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.191 ns ; +; -3.792 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.190 ns ; +; -3.792 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.190 ns ; +; -3.792 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.295 ns ; 3.497 ns ; +; -3.788 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.186 ns ; +; -3.787 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.505 ns ; +; -3.783 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.171 ns ; +; -3.781 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.176 ns ; +; -3.780 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.802 ns ; +; -3.779 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.519 ns ; +; -3.777 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.615 ns ; 3.162 ns ; +; -3.777 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.495 ns ; +; -3.776 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.796 ns ; +; -3.771 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.793 ns ; +; -3.767 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.507 ns ; +; -3.762 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.480 ns ; +; -3.757 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.779 ns ; +; -3.748 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.015 ns ; 3.763 ns ; +; -3.747 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.291 ns ; 3.456 ns ; +; -3.747 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.015 ns ; 3.762 ns ; +; -3.743 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.014 ns ; 3.757 ns ; +; -3.728 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.292 ns ; 3.436 ns ; +; -3.724 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.442 ns ; +; -3.724 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.442 ns ; +; -3.720 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.013 ns ; 3.733 ns ; +; -3.717 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.294 ns ; 3.423 ns ; +; -3.713 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.617 ns ; 3.096 ns ; +; -3.713 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.622 ns ; 3.091 ns ; +; -3.713 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.734 ns ; +; -3.703 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.292 ns ; 3.411 ns ; +; -3.698 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.438 ns ; +; -3.695 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.093 ns ; +; -3.694 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.092 ns ; +; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.091 ns ; +; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.091 ns ; +; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.089 ns ; +; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; +; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; +; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; +; -3.690 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.088 ns ; +; -3.690 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.085 ns ; +; -3.688 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.084 ns ; +; -3.685 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.080 ns ; +; -3.685 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.403 ns ; +; -3.684 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.080 ns ; +; -3.683 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.703 ns ; +; -3.679 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.419 ns ; +; -3.677 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.075 ns ; +; -3.677 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.699 ns ; +; -3.675 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.073 ns ; +; -3.674 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.392 ns ; +; -3.672 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.070 ns ; +; -3.670 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.068 ns ; +; -3.668 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.617 ns ; 3.051 ns ; +; -3.668 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.289 ns ; 3.379 ns ; +; -3.667 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.065 ns ; +; -3.665 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.061 ns ; +; -3.665 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.061 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.060 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.059 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.059 ns ; +; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.060 ns ; +; -3.663 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.058 ns ; +; -3.663 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.059 ns ; +; -3.662 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.057 ns ; +; -3.661 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.056 ns ; +; -3.660 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.055 ns ; +; -3.651 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.369 ns ; +; -3.649 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.037 ns ; +; -3.645 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.666 ns ; +; -3.633 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.614 ns ; 3.019 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'CLK33M' ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; -5.966 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.279 ns ; 3.687 ns ; +; -5.924 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.272 ns ; 3.652 ns ; +; -5.919 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.642 ns ; +; -5.913 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.266 ns ; 3.647 ns ; +; -5.904 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.635 ns ; +; -5.900 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.631 ns ; +; -5.892 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.279 ns ; 3.613 ns ; +; -5.884 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.610 ns ; +; -5.877 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.608 ns ; +; -5.830 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.898 ns ; +; -5.791 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.141 ns ; +; -5.791 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.517 ns ; +; -5.764 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.114 ns ; +; -5.760 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.486 ns ; +; -5.758 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.267 ns ; 3.491 ns ; +; -5.757 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.265 ns ; 3.492 ns ; +; -5.745 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.468 ns ; +; -5.742 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.465 ns ; +; -5.742 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.466 ns ; +; -5.737 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.461 ns ; +; -5.732 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.458 ns ; +; -5.729 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.455 ns ; +; -5.723 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.447 ns ; +; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.447 ns ; +; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.447 ns ; +; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.445 ns ; +; -5.720 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 4.068 ns ; +; -5.718 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.444 ns ; +; -5.717 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.441 ns ; +; -5.717 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.441 ns ; +; -5.715 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.441 ns ; +; -5.714 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 4.063 ns ; +; -5.714 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.440 ns ; +; -5.712 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.436 ns ; +; -5.711 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.434 ns ; +; -5.711 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.435 ns ; +; -5.708 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.431 ns ; +; -5.707 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.433 ns ; +; -5.704 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.428 ns ; +; -5.704 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.428 ns ; +; -5.702 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.282 ns ; 3.420 ns ; +; -5.699 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.426 ns ; +; -5.669 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.267 ns ; 3.402 ns ; +; -5.667 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.270 ns ; 3.397 ns ; +; -5.659 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 4.008 ns ; +; -5.657 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.725 ns ; +; -5.656 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.379 ns ; +; -5.652 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.002 ns ; +; -5.650 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.376 ns ; +; -5.649 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.275 ns ; 3.374 ns ; +; -5.648 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.374 ns ; +; -5.645 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.372 ns ; +; -5.644 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.370 ns ; +; -5.644 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.371 ns ; +; -5.641 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.365 ns ; +; -5.640 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.366 ns ; +; -5.640 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.364 ns ; +; -5.639 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.363 ns ; +; -5.630 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.356 ns ; +; -5.629 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.355 ns ; +; -5.628 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.354 ns ; +; -5.624 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.347 ns ; +; -5.622 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.972 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.970 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.343 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.346 ns ; +; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.346 ns ; +; -5.619 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.345 ns ; +; -5.619 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.345 ns ; +; -5.618 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.344 ns ; +; -5.617 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.343 ns ; +; -5.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.341 ns ; +; -5.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.341 ns ; +; -5.613 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.339 ns ; +; -5.613 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.339 ns ; +; -5.610 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.960 ns ; +; -5.610 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.334 ns ; +; -5.609 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.332 ns ; +; -5.607 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.333 ns ; +; -5.607 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.333 ns ; +; -5.606 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.329 ns ; +; -5.606 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.330 ns ; +; -5.604 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.330 ns ; +; -5.604 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.327 ns ; +; -5.602 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.328 ns ; +; -5.599 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.325 ns ; +; -5.598 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.324 ns ; +; -5.597 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.323 ns ; +; -5.596 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.319 ns ; +; -5.594 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.944 ns ; +; -5.592 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.316 ns ; +; -5.587 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.310 ns ; +; -5.581 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.929 ns ; +; -5.580 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.928 ns ; +; -5.570 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.919 ns ; +; -5.568 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.292 ns ; +; -5.566 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.916 ns ; +; -5.554 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.904 ns ; +; -5.550 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.899 ns ; +; -5.546 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.614 ns ; +; -5.545 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.269 ns ; +; -5.541 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.257 ns ; +; -5.539 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.887 ns ; +; -5.539 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.975 ns ; 3.564 ns ; +; -5.530 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.282 ns ; 3.248 ns ; +; -5.526 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.876 ns ; +; -5.523 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.591 ns ; +; -5.507 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.855 ns ; +; -5.505 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.551 ns ; +; -5.500 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.850 ns ; +; -5.499 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.847 ns ; +; -5.494 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.540 ns ; +; -5.493 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.963 ns ; 3.530 ns ; +; -5.491 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.975 ns ; 3.516 ns ; +; -5.490 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.216 ns ; +; -5.489 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.838 ns ; +; -5.488 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.211 ns ; +; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; +; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; +; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; +; -5.485 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.211 ns ; +; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.210 ns ; +; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.208 ns ; +; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.208 ns ; +; -5.481 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.204 ns ; +; -5.481 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.205 ns ; +; -5.479 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.205 ns ; +; -5.478 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.202 ns ; +; -5.476 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.199 ns ; +; -5.475 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.191 ns ; +; -5.464 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.190 ns ; +; -5.464 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.190 ns ; +; -5.464 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.967 ns ; 3.497 ns ; +; -5.460 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.186 ns ; +; -5.459 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.505 ns ; +; -5.455 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.171 ns ; +; -5.453 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.176 ns ; +; -5.452 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.802 ns ; +; -5.451 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.519 ns ; +; -5.449 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.287 ns ; 3.162 ns ; +; -5.449 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.495 ns ; +; -5.448 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.796 ns ; +; -5.443 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.793 ns ; +; -5.439 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.507 ns ; +; -5.434 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.480 ns ; +; -5.429 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.779 ns ; +; -5.420 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.657 ns ; 3.763 ns ; +; -5.419 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.963 ns ; 3.456 ns ; +; -5.419 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.657 ns ; 3.762 ns ; +; -5.415 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.658 ns ; 3.757 ns ; +; -5.400 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.964 ns ; 3.436 ns ; +; -5.396 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.442 ns ; +; -5.396 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.442 ns ; +; -5.392 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.659 ns ; 3.733 ns ; +; -5.389 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.966 ns ; 3.423 ns ; +; -5.385 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.289 ns ; 3.096 ns ; +; -5.385 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.294 ns ; 3.091 ns ; +; -5.385 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.734 ns ; +; -5.375 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.964 ns ; 3.411 ns ; +; -5.370 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.438 ns ; +; -5.367 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.093 ns ; +; -5.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.092 ns ; +; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.091 ns ; +; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.091 ns ; +; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.089 ns ; +; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; +; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; +; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; +; -5.362 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.088 ns ; +; -5.362 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.085 ns ; +; -5.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.084 ns ; +; -5.357 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.080 ns ; +; -5.357 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.403 ns ; +; -5.356 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.080 ns ; +; -5.355 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.703 ns ; +; -5.351 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.419 ns ; +; -5.349 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.075 ns ; +; -5.349 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.699 ns ; +; -5.347 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.073 ns ; +; -5.346 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.392 ns ; +; -5.344 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.070 ns ; +; -5.342 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.068 ns ; +; -5.340 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.289 ns ; 3.051 ns ; +; -5.340 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.961 ns ; 3.379 ns ; +; -5.339 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.065 ns ; +; -5.337 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.061 ns ; +; -5.337 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.061 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.060 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.059 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.059 ns ; +; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.060 ns ; +; -5.335 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.058 ns ; +; -5.335 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.059 ns ; +; -5.334 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.057 ns ; +; -5.333 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.056 ns ; +; -5.332 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.055 ns ; +; -5.323 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.369 ns ; +; -5.321 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.037 ns ; +; -5.317 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.666 ns ; +; -5.305 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.286 ns ; 3.019 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'MAIN_CLK' ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ +; -4.261 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.318 ns ; +; -4.260 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a8 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.317 ns ; +; -4.258 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.315 ns ; +; -4.239 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.296 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; +; -4.071 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~portb_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.225 ns ; 4.296 ns ; +; -4.023 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.012 ns ; 4.035 ns ; +; -4.023 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.012 ns ; 4.035 ns ; +; -3.979 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.272 ns ; 4.251 ns ; +; -3.910 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.967 ns ; +; -3.907 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.964 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; +; -3.546 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.603 ns ; +; -3.544 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.601 ns ; +; -3.541 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.096 ns ; 3.637 ns ; +; -3.426 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; -0.013 ns ; 3.413 ns ; +; -3.055 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.360 ns ; 3.415 ns ; +; -3.039 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WRF_WRE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; -0.013 ns ; 3.026 ns ; +; -2.598 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.205 ns ; 2.803 ns ; +; -2.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.530 ns ; +; -2.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.530 ns ; +; -2.375 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 7.143 ns ; +; -2.355 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.341 ns ; +; -2.320 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.304 ns ; +; -2.317 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.384 ns ; +; -2.317 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.384 ns ; +; -2.290 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 7.056 ns ; +; -2.250 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.317 ns ; +; -2.250 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.317 ns ; +; -2.246 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 6.245 ns ; +; -2.239 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.307 ns ; +; -2.239 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.307 ns ; +; -2.229 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.997 ns ; +; -2.209 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.195 ns ; +; -2.199 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.317 ns ; +; -2.199 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.317 ns ; +; -2.183 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.129 ns ; 6.312 ns ; +; -2.177 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.390 ns ; +; -2.177 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.390 ns ; +; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.769 ns ; 6.920 ns ; +; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.270 ns ; +; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.270 ns ; +; -2.147 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.265 ns ; +; -2.147 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.265 ns ; +; -2.146 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.120 ns ; 6.266 ns ; +; -2.146 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.120 ns ; 6.266 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.260 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.261 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.260 ns ; +; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.261 ns ; +; -2.139 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 6.905 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; +; -2.133 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.119 ns ; +; -2.132 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.116 ns ; +; -2.131 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.987 ns ; 6.118 ns ; +; -2.129 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.248 ns ; +; -2.129 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.248 ns ; +; -2.122 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.187 ns ; +; -2.122 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.187 ns ; +; -2.118 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.186 ns ; +; -2.118 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.186 ns ; +; -2.100 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 6.099 ns ; +; -2.098 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.215 ns ; +; -2.098 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.215 ns ; +; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.159 ns ; +; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.159 ns ; +; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; +; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; +; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; +; -2.083 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.620 ns ; +; -2.062 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.830 ns ; +; -2.060 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.828 ns ; +; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; +; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; +; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; +; -2.045 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 6.811 ns ; +; -2.045 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|UE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.701 ns ; 5.746 ns ; +; -2.037 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.129 ns ; 6.166 ns ; +; -2.035 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.573 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[3][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[4][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[5][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; +; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.017 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.568 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.244 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.244 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.144 ns ; +; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.144 ns ; +; -2.030 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.769 ns ; 6.799 ns ; +; -2.030 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.539 ns ; 6.569 ns ; +; -2.026 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.563 ns ; +; -2.026 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.564 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.000 ns ; 6.022 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; +; -2.013 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.551 ns ; +; -2.010 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.987 ns ; 5.997 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; +; -2.002 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.986 ns ; +; -2.001 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.985 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; +; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 5.997 ns ; +; -1.997 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.981 ns ; +; -1.996 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.064 ns ; 6.060 ns ; +; -1.996 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.064 ns ; 6.060 ns ; +; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.106 ns ; +; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.106 ns ; +; -1.991 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.050 ns ; 6.041 ns ; +; -1.991 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.050 ns ; 6.041 ns ; +; -1.990 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.109 ns ; +; -1.990 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.109 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.106 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.106 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; ++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.825 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.783 ns ; +; 0.827 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.785 ns ; +; 0.827 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.785 ns ; +; 0.828 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.786 ns ; +; 0.828 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.786 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; +; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.831 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.789 ns ; +; 0.831 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.789 ns ; +; 0.832 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.790 ns ; +; 0.833 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.791 ns ; +; 1.185 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.143 ns ; +; 1.353 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.311 ns ; +; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.312 ns ; +; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.311 ns ; +; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.312 ns ; +; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; +; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; +; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.358 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.316 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; +; 1.411 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.369 ns ; +; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.370 ns ; +; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.369 ns ; +; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.370 ns ; +; 1.414 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.372 ns ; +; 1.414 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.372 ns ; +; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.416 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.374 ns ; +; 1.416 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.373 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.428 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.427 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.427 ns ; +; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.428 ns ; +; 1.472 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.430 ns ; +; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.474 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.432 ns ; +; 1.474 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.431 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.486 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.485 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.485 ns ; +; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.486 ns ; +; 1.530 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.488 ns ; +; 1.531 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; +; 1.531 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; +; 1.532 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.489 ns ; +; 1.532 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.489 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; +; 1.586 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.543 ns ; +; 1.586 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.543 ns ; +; 1.587 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.544 ns ; +; 1.588 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.546 ns ; +; 1.589 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.547 ns ; +; 1.589 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.547 ns ; +; 1.590 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.547 ns ; +; 1.590 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.547 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; +; 1.644 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.601 ns ; +; 1.644 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.601 ns ; +; 1.645 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.602 ns ; +; 1.646 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.604 ns ; +; 1.647 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.605 ns ; +; 1.648 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.605 ns ; +; 1.648 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.605 ns ; +; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; +; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; +; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; +; 1.650 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.607 ns ; +; 1.689 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.647 ns ; +; 1.702 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.659 ns ; +; 1.702 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.659 ns ; +; 1.703 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.660 ns ; +; 1.704 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.662 ns ; +; 1.706 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.663 ns ; +; 1.706 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.663 ns ; +; 1.707 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.665 ns ; +; 1.707 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.665 ns ; +; 1.708 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.665 ns ; +; 1.708 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.665 ns ; +; 1.743 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.701 ns ; +; 1.760 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.717 ns ; +; 1.760 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.717 ns ; +; 1.761 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.718 ns ; +; 1.764 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.721 ns ; +; 1.764 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.721 ns ; +; 1.765 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.723 ns ; +; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; +; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; +; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; +; 1.801 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.759 ns ; +; 1.818 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.775 ns ; +; 1.819 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.776 ns ; +; 1.822 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.779 ns ; +; 1.822 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.779 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; +; 1.861 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.819 ns ; +; 1.876 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.833 ns ; +; 1.877 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.834 ns ; +; 1.880 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.837 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; +; 1.915 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.873 ns ; +; 1.935 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.892 ns ; +; 1.938 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.895 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; +; 1.976 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.934 ns ; +; 1.993 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.950 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; +; 2.034 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.992 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; +; 2.091 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 2.049 ns ; +; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; +; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; +; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; +; 2.147 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.104 ns ; +; 2.172 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.129 ns ; +; 2.172 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.129 ns ; +; 2.209 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.166 ns ; +; 2.230 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.187 ns ; +; 2.263 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.220 ns ; +; 2.325 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.282 ns ; +; 2.380 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.337 ns ; +; 2.443 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.400 ns ; +; 2.501 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.458 ns ; +; 2.559 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.516 ns ; +; 2.617 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.574 ns ; ++---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; ++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.564 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.522 ns ; +; 0.825 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.783 ns ; +; 0.830 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; +; 0.852 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.810 ns ; +; 0.955 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.913 ns ; +; 1.357 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; +; 1.358 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.316 ns ; +; 1.380 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.338 ns ; +; 1.415 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; +; 1.416 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.374 ns ; +; 1.473 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; +; 1.474 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.432 ns ; +; 1.487 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.445 ns ; +; 1.531 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; +; 1.545 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.503 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; +; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; ++---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; ++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.547 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.505 ns ; +; 0.549 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\ADRMARK_STROBES:DDATA_AM_LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|DDATA_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.559 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.562 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.563 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; +; 0.569 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.569 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.571 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.572 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; +; 0.572 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; +; 0.573 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.577 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.535 ns ; +; 0.580 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.538 ns ; +; 0.582 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.540 ns ; +; 0.584 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.542 ns ; +; 0.591 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.549 ns ; +; 0.592 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.550 ns ; +; 0.593 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.551 ns ; +; 0.608 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.566 ns ; +; 0.609 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.567 ns ; +; 0.610 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.568 ns ; +; 0.610 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.568 ns ; +; 0.614 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.572 ns ; +; 0.614 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.572 ns ; +; 0.616 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.574 ns ; +; 0.616 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.574 ns ; +; 0.625 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.583 ns ; +; 0.626 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.584 ns ; +; 0.627 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.585 ns ; +; 0.667 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[23] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.625 ns ; +; 0.668 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.626 ns ; +; 0.669 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.627 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[21] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; +; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; +; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; +; 0.673 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.631 ns ; +; 0.675 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.633 ns ; +; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.679 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.639 ns ; +; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.681 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.639 ns ; +; 0.683 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.641 ns ; +; 0.683 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.641 ns ; +; 0.689 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.649 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.691 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.693 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.652 ns ; +; 0.698 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; 0.330 ns ; 1.028 ns ; +; 0.699 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; +; 0.700 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.704 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.662 ns ; +; 0.704 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.662 ns ; +; 0.706 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.664 ns ; +; 0.708 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.666 ns ; +; 0.711 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.669 ns ; +; 0.712 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.043 ns ; 0.669 ns ; +; 0.712 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.670 ns ; +; 0.714 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.673 ns ; +; 0.715 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.673 ns ; +; 0.715 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.673 ns ; +; 0.720 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_PRES ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.678 ns ; +; 0.724 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.682 ns ; +; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; 0.330 ns ; 1.056 ns ; +; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.685 ns ; +; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_g[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.684 ns ; +; 0.728 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.686 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.531 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.443 ns ; +; 0.536 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.403 ns ; 2.939 ns ; +; 0.538 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.450 ns ; +; 0.538 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.450 ns ; +; 0.541 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.453 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.908 ns ; 1.459 ns ; +; 0.556 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.503 ns ; +; 0.557 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.960 ns ; 1.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.471 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.935 ns ; 1.494 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.583 ns ; 1.143 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.476 ns ; +; 0.561 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.478 ns ; +; 0.564 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.570 ns ; 1.134 ns ; +; 0.567 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.514 ns ; +; 0.570 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.486 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.905 ns ; 1.478 ns ; +; 0.576 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.929 ns ; 1.505 ns ; +; 0.578 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.490 ns ; +; 0.579 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.493 ns ; +; 0.580 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.864 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.919 ns ; 1.502 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.584 ns ; 1.167 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.494 ns ; +; 0.584 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.551 ns ; +; 0.585 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.496 ns ; +; 0.586 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.500 ns ; +; 0.588 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.504 ns ; +; 0.589 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.495 ns ; +; 0.589 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.909 ns ; 1.498 ns ; +; 0.590 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.504 ns ; +; 0.591 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.875 ns ; +; 0.592 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.507 ns ; +; 0.592 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.929 ns ; 1.521 ns ; +; 0.597 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.511 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.517 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.524 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.521 ns ; +; 0.600 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.282 ns ; 1.882 ns ; +; 0.601 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.513 ns ; +; 0.601 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.926 ns ; 1.527 ns ; +; 0.604 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.551 ns ; +; 0.608 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.524 ns ; +; 0.608 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.522 ns ; +; 0.609 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.401 ns ; 3.010 ns ; +; 0.610 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.894 ns ; +; 0.611 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.528 ns ; +; 0.613 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.527 ns ; +; 0.613 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.530 ns ; +; 0.613 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.580 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.526 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.526 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.531 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.561 ns ; +; 0.614 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.531 ns ; +; 0.617 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.534 ns ; +; 0.618 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.962 ns ; 1.580 ns ; +; 0.619 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.540 ns ; +; 0.620 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.541 ns ; +; 0.620 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.534 ns ; +; 0.620 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.541 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.542 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.539 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.546 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.597 ns ; 1.219 ns ; +; 0.622 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.528 ns ; +; 0.623 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.537 ns ; +; 0.623 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.544 ns ; +; 0.623 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.283 ns ; 1.906 ns ; +; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.547 ns ; +; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.550 ns ; +; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.550 ns ; +; 0.627 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.548 ns ; +; 0.627 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.551 ns ; +; 0.627 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.544 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.543 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.543 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.912 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.545 ns ; +; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.541 ns ; +; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.550 ns ; +; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.550 ns ; +; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.553 ns ; +; 0.630 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.544 ns ; +; 0.630 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.554 ns ; +; 0.631 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.545 ns ; +; 0.632 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.588 ns ; 1.220 ns ; +; 0.633 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.546 ns ; +; 0.633 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.549 ns ; +; 0.636 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.909 ns ; 1.545 ns ; +; 0.637 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.551 ns ; +; 0.637 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.551 ns ; +; 0.638 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.555 ns ; +; 0.638 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.549 ns ; +; 0.638 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.552 ns ; +; 0.639 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.556 ns ; +; 0.639 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.555 ns ; +; 0.641 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.558 ns ; +; 0.641 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.555 ns ; +; 0.642 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.558 ns ; +; 0.643 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.557 ns ; +; 0.644 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.558 ns ; +; 0.644 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.611 ns ; +; 0.645 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.557 ns ; +; 0.646 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.560 ns ; +; 0.646 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.586 ns ; 1.232 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.561 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.907 ns ; 1.555 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.577 ns ; 1.225 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.560 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.907 ns ; 1.555 ns ; +; 0.648 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.562 ns ; +; 0.649 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.566 ns ; +; 0.649 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.567 ns ; +; 0.649 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.563 ns ; +; 0.650 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.568 ns ; +; 0.650 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.570 ns ; 1.220 ns ; +; 0.651 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.577 ns ; 1.228 ns ; +; 0.651 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.404 ns ; 3.055 ns ; +; 0.652 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.576 ns ; +; 0.653 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.567 ns ; +; 0.653 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.567 ns ; +; 0.655 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.602 ns ; +; 0.656 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.585 ns ; 1.241 ns ; +; 0.656 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.282 ns ; 1.938 ns ; +; 0.657 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.581 ns ; +; 0.657 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.571 ns ; +; 0.658 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.905 ns ; 1.563 ns ; +; 0.658 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.572 ns ; +; 0.659 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.565 ns ; +; 0.660 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.627 ns ; +; 0.661 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.608 ns ; +; 0.661 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.575 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.577 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.574 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.576 ns ; +; 0.662 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.580 ns ; +; 0.663 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.579 ns ; +; 0.663 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.610 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.575 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.930 ns ; 1.594 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.570 ns ; +; 0.664 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.584 ns ; +; 0.665 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.582 ns ; +; 0.665 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.579 ns ; +; 0.665 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.578 ns ; +; 0.666 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.580 ns ; +; 0.666 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.580 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.581 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.581 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.587 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.580 ns ; +; 0.667 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.634 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.585 ns ; 1.254 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.582 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.953 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.636 ns ; +; 0.669 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.583 ns ; +; 0.670 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.584 ns ; +; 0.670 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.587 ns ; +; 0.671 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.586 ns ; +; 0.671 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.908 ns ; 1.579 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; ++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[75] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[99] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[65] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[81] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[87] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[105] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[110] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[94] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[124] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[123] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[66] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[126] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe19a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[102] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[86] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[118] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[67] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[83] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.552 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[125] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[92] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[73] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[121] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.553 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_DDR_SYNC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; +; 0.554 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[120] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.512 ns ; +; 0.554 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.512 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[42] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[56] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[32] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; +; 0.561 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[39] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.519 ns ; +; 0.561 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.519 ns ; +; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; +; 0.563 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[52] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; +; 0.563 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[57] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; +; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; +; 0.570 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.528 ns ; +; 0.570 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.528 ns ; +; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; +; 0.572 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[84] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[84] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[95] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[95] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[46] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.573 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; +; 0.574 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.532 ns ; +; 0.582 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[70] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[70] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.540 ns ; +; 0.583 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.541 ns ; +; 0.592 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.550 ns ; +; 0.593 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.551 ns ; +; 0.595 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.553 ns ; +; 0.601 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.559 ns ; +; 0.604 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.562 ns ; +; 0.605 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.563 ns ; +; 0.605 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.563 ns ; +; 0.643 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.340 ns ; 0.983 ns ; +; 0.647 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.332 ns ; 0.979 ns ; +; 0.654 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 0.988 ns ; +; 0.670 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.332 ns ; 1.002 ns ; +; 0.671 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; +; 0.673 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 1.007 ns ; +; 0.675 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[90] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.633 ns ; +; 0.676 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C2 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.634 ns ; +; 0.677 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.677 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[88] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; +; 0.678 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[97] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.678 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[85] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[100] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.679 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; +; 0.680 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[93] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.680 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[114] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.680 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; +; 0.681 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[98] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.639 ns ; +; 0.687 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.645 ns ; +; 0.687 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.645 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[41] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[49] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[44] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[33] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[61] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.690 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[43] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[54] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[91] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.649 ns ; +; 0.692 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_N5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; +; 0.693 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.651 ns ; +; 0.694 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 1.028 ns ; +; 0.695 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[106] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[45] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[77] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[109] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.655 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; +; 0.698 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 0.657 ns ; +; 0.699 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; +; 0.699 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[78] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[78] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[53] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[82] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.700 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7W ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8W ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T4W ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T5W ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; +; 0.703 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.661 ns ; +; 0.703 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.661 ns ; +; 0.704 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.031 ns ; +; 0.705 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.341 ns ; 1.046 ns ; +; 0.706 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.033 ns ; +; 0.707 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[51] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.665 ns ; +; 0.710 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 0.669 ns ; +; 0.712 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[40] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.669 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; ++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; +; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; +; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; +; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; +; 4.465 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.636 ns ; +; 4.466 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.637 ns ; +; 4.467 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.638 ns ; +; 4.468 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.639 ns ; ++---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; ++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 1.825 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.508 ns ; +; 1.827 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.510 ns ; +; 1.953 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.636 ns ; +; 1.954 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.637 ns ; +; 2.134 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.315 ns ; 0.819 ns ; ++---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; ++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 3.263 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.570 ns ; +; 3.273 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.580 ns ; +; 3.460 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.363 ns ; +; 3.511 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.818 ns ; +; 3.539 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 1.845 ns ; +; 3.543 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 1.857 ns ; +; 3.548 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 1.860 ns ; +; 3.569 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 1.874 ns ; +; 3.570 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 1.882 ns ; +; 3.573 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.667 ns ; 1.906 ns ; +; 3.609 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 1.937 ns ; +; 3.618 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 1.929 ns ; +; 3.637 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 1.952 ns ; +; 3.656 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 1.959 ns ; +; 3.660 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 1.974 ns ; +; 3.674 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 1.983 ns ; +; 3.686 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.692 ns ; 1.994 ns ; +; 3.719 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.024 ns ; +; 3.721 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 2.030 ns ; +; 3.730 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.698 ns ; 2.032 ns ; +; 3.731 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.634 ns ; +; 3.737 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.042 ns ; +; 3.740 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.664 ns ; 2.076 ns ; +; 3.745 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.668 ns ; 2.077 ns ; +; 3.754 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.059 ns ; +; 3.769 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.672 ns ; +; 3.774 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 2.077 ns ; +; 3.776 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 2.091 ns ; +; 3.777 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.698 ns ; 2.079 ns ; +; 3.778 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 2.085 ns ; +; 3.780 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.084 ns ; +; 3.781 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.684 ns ; 2.097 ns ; +; 3.784 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.089 ns ; +; 3.784 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.684 ns ; 2.100 ns ; +; 3.786 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.097 ns ; +; 3.792 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 3.693 ns ; +; 3.794 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.692 ns ; 2.102 ns ; +; 3.796 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.107 ns ; +; 3.811 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.125 ns ; +; 3.814 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 2.126 ns ; +; 3.819 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 2.122 ns ; +; 3.836 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.141 ns ; +; 3.838 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 3.735 ns ; +; 3.839 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.101 ns ; 3.738 ns ; +; 3.855 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.755 ns ; +; 3.866 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 3.763 ns ; +; 3.899 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 2.205 ns ; +; 3.902 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.203 ns ; +; 3.906 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.722 ns ; 2.184 ns ; +; 3.916 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 3.812 ns ; +; 3.920 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.234 ns ; +; 3.932 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.246 ns ; +; 3.933 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.613 ns ; 2.320 ns ; +; 3.935 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.239 ns ; +; 3.936 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 3.837 ns ; +; 3.944 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 2.250 ns ; +; 3.951 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.851 ns ; +; 3.973 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.101 ns ; 3.872 ns ; +; 3.979 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.283 ns ; +; 3.989 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 2.296 ns ; +; 4.004 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.904 ns ; +; 4.029 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 3.931 ns ; +; 4.042 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.683 ns ; 2.359 ns ; +; 4.043 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 2.358 ns ; +; 4.043 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.344 ns ; +; 4.048 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.352 ns ; +; 4.078 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.978 ns ; +; 4.084 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 3.980 ns ; +; 4.096 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 3.998 ns ; +; 4.110 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 4.006 ns ; +; 4.112 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.371 ns ; +; 4.112 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.423 ns ; +; 4.115 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.012 ns ; +; 4.117 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.014 ns ; +; 4.132 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 4.035 ns ; +; 4.168 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.429 ns ; +; 4.169 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.470 ns ; +; 4.185 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.454 ns ; +; 4.187 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.723 ns ; 2.464 ns ; +; 4.195 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.431 ns ; +; 4.196 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.713 ns ; 2.483 ns ; +; 4.201 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 2.447 ns ; +; 4.221 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.714 ns ; 2.507 ns ; +; 4.231 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.614 ns ; 2.617 ns ; +; 4.232 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.133 ns ; +; 4.232 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.674 ns ; 2.558 ns ; +; 4.235 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.132 ns ; +; 4.236 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.102 ns ; 4.134 ns ; +; 4.239 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.673 ns ; 2.566 ns ; +; 4.243 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.479 ns ; +; 4.249 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.669 ns ; 2.580 ns ; +; 4.251 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.152 ns ; +; 4.269 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.170 ns ; +; 4.283 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.185 ns ; +; 4.286 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.188 ns ; +; 4.296 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.670 ns ; 2.626 ns ; +; 4.313 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.666 ns ; 2.647 ns ; +; 4.314 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 2.623 ns ; +; 4.331 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 2.596 ns ; +; 4.333 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.145 ns ; 4.188 ns ; +; 4.343 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.145 ns ; 4.198 ns ; +; 4.347 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.665 ns ; 2.682 ns ; +; 4.352 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.254 ns ; +; 4.352 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 4.252 ns ; +; 4.362 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.717 ns ; 2.645 ns ; +; 4.367 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.608 ns ; +; 4.376 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.635 ns ; +; 4.384 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.102 ns ; 4.282 ns ; +; 4.406 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.615 ns ; 2.791 ns ; +; 4.409 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.645 ns ; +; 4.410 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.646 ns ; +; 4.411 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.159 ns ; 4.252 ns ; +; 4.417 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.746 ns ; 2.671 ns ; +; 4.425 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 4.325 ns ; +; 4.431 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.670 ns ; 2.761 ns ; +; 4.434 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.695 ns ; +; 4.440 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.685 ns ; +; 4.450 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.719 ns ; +; 4.475 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.734 ns ; +; 4.477 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 2.805 ns ; +; 4.478 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.730 ns ; 2.748 ns ; +; 4.480 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.757 ns ; 2.723 ns ; +; 4.485 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.736 ns ; +; 4.486 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 2.814 ns ; +; 4.497 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.351 ns ; +; 4.498 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.329 ns ; +; 4.527 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 2.773 ns ; +; 4.530 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.791 ns ; +; 4.555 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 2.804 ns ; +; 4.556 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.163 ns ; 4.393 ns ; +; 4.573 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.818 ns ; +; 4.587 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.615 ns ; 2.972 ns ; +; 4.597 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.429 ns ; +; 4.600 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 2.865 ns ; +; 4.601 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.852 ns ; +; 4.601 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.433 ns ; +; 4.613 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.674 ns ; 2.939 ns ; +; 4.614 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.855 ns ; +; 4.618 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 2.867 ns ; +; 4.623 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.159 ns ; 4.464 ns ; +; 4.626 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.742 ns ; 2.884 ns ; +; 4.630 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.740 ns ; 2.890 ns ; +; 4.633 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.874 ns ; +; 4.636 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.150 ns ; 4.486 ns ; +; 4.637 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.906 ns ; +; 4.660 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.911 ns ; +; 4.670 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.517 ns ; +; 4.671 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.164 ns ; 4.507 ns ; +; 4.676 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.912 ns ; +; 4.677 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.745 ns ; 2.932 ns ; +; 4.677 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.913 ns ; +; 4.686 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.746 ns ; 2.940 ns ; +; 4.690 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.726 ns ; 2.964 ns ; +; 4.697 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.529 ns ; +; 4.699 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.874 ns ; 1.825 ns ; +; 4.704 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.949 ns ; +; 4.709 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.664 ns ; 3.045 ns ; +; 4.722 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.991 ns ; +; 4.749 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.603 ns ; +; 4.753 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.004 ns ; +; 4.780 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.155 ns ; 4.625 ns ; +; 4.787 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.156 ns ; 4.631 ns ; +; 4.791 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.638 ns ; +; 4.805 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.730 ns ; 3.075 ns ; +; 4.809 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.640 ns ; +; 4.823 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 3.072 ns ; +; 4.825 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.163 ns ; 4.662 ns ; +; 4.840 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.712 ns ; 3.128 ns ; +; 4.844 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 3.109 ns ; +; 4.844 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.155 ns ; 4.689 ns ; +; 4.845 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.154 ns ; 4.691 ns ; +; 4.846 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.700 ns ; +; 4.863 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 3.108 ns ; +; 4.869 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.131 ns ; +; 4.871 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.122 ns ; +; 4.878 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.725 ns ; +; 4.881 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.712 ns ; +; 4.885 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 3.134 ns ; +; 4.888 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.156 ns ; 4.732 ns ; +; 4.892 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.147 ns ; 4.745 ns ; +; 4.892 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.742 ns ; 3.150 ns ; +; 4.896 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.740 ns ; 3.156 ns ; +; 4.906 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 3.175 ns ; +; 4.916 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.866 ns ; 2.050 ns ; +; 4.916 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.151 ns ; 4.765 ns ; +; 4.924 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.175 ns ; +; 4.942 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.745 ns ; 3.197 ns ; +; 4.979 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.160 ns ; 4.819 ns ; +; 5.007 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 3.253 ns ; +; 5.009 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 3.250 ns ; +; 5.013 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.726 ns ; 3.287 ns ; +; 5.029 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.164 ns ; 4.865 ns ; +; 5.047 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 3.308 ns ; +; 5.088 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.869 ns ; 2.219 ns ; +; 5.096 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.933 ns ; 2.163 ns ; +; 5.124 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.154 ns ; 4.970 ns ; +; 5.133 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.395 ns ; +; 5.143 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.722 ns ; 3.421 ns ; +; 5.166 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.428 ns ; +; 5.205 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.720 ns ; 3.485 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; ++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; +; 2.679 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.447 ns ; 2.232 ns ; +; 2.684 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.447 ns ; 2.237 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; +; 2.714 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.264 ns ; +; 2.714 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.264 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; +; 2.769 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.319 ns ; +; 2.769 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.319 ns ; +; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; +; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; +; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; +; 2.948 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -1.264 ns ; -1.316 ns ; 1.632 ns ; +; 3.033 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.589 ns ; +; 3.033 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.589 ns ; +; 3.088 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.042 ns ; 3.046 ns ; +; 3.100 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.656 ns ; +; 3.146 ns ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.316 ns ; 2.830 ns ; +; 6.237 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.309 ns ; 1.928 ns ; +; 6.282 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.386 ns ; 1.896 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; +; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; +; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; +; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; +; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; +; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; +; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; +; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; +; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; +; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; +; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; +; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; +; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; +; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; +; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; +; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; +; 7.218 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.355 ns ; 2.863 ns ; +; 7.413 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.650 ns ; 2.763 ns ; +; 7.427 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.650 ns ; 2.777 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; +; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; +; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; +; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; +; 7.686 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.470 ns ; 3.216 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; +; 1.487 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.443 ns ; +; 1.492 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.447 ns ; 2.939 ns ; +; 1.494 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.450 ns ; +; 1.494 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.450 ns ; +; 1.497 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.453 ns ; +; 1.507 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.048 ns ; 1.459 ns ; +; 1.512 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.503 ns ; +; 1.513 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.004 ns ; 1.517 ns ; +; 1.515 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.471 ns ; +; 1.515 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.021 ns ; 1.494 ns ; +; 1.516 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.373 ns ; 1.143 ns ; +; 1.516 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.476 ns ; +; 1.517 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.478 ns ; +; 1.520 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.386 ns ; 1.134 ns ; +; 1.523 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.514 ns ; +; 1.526 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.486 ns ; +; 1.529 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.051 ns ; 1.478 ns ; +; 1.532 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.027 ns ; 1.505 ns ; +; 1.534 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.490 ns ; +; 1.535 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.493 ns ; +; 1.536 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.864 ns ; +; 1.539 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.037 ns ; 1.502 ns ; +; 1.539 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.372 ns ; 1.167 ns ; +; 1.539 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.494 ns ; +; 1.540 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.551 ns ; +; 1.541 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.496 ns ; +; 1.542 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.500 ns ; +; 1.544 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.504 ns ; +; 1.545 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.495 ns ; +; 1.545 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.047 ns ; 1.498 ns ; +; 1.546 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.504 ns ; +; 1.547 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.875 ns ; +; 1.548 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.507 ns ; +; 1.548 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.027 ns ; 1.521 ns ; +; 1.553 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.511 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.517 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.524 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.521 ns ; +; 1.556 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.326 ns ; 1.882 ns ; +; 1.557 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.513 ns ; +; 1.557 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.030 ns ; 1.527 ns ; +; 1.560 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.551 ns ; +; 1.564 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.524 ns ; +; 1.564 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.522 ns ; +; 1.565 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.445 ns ; 3.010 ns ; +; 1.566 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.894 ns ; +; 1.567 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.528 ns ; +; 1.569 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.527 ns ; +; 1.569 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.530 ns ; +; 1.569 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.580 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.526 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.526 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.531 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.561 ns ; +; 1.570 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.531 ns ; +; 1.573 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.534 ns ; +; 1.574 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.006 ns ; 1.580 ns ; +; 1.575 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.540 ns ; +; 1.576 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.541 ns ; +; 1.576 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.534 ns ; +; 1.576 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.541 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.542 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.539 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.546 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.359 ns ; 1.219 ns ; +; 1.578 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.528 ns ; +; 1.579 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.537 ns ; +; 1.579 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.544 ns ; +; 1.579 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.906 ns ; +; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.547 ns ; +; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.550 ns ; +; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.550 ns ; +; 1.583 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.548 ns ; +; 1.583 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.551 ns ; +; 1.583 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.544 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.543 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.543 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.912 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.545 ns ; +; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.541 ns ; +; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.550 ns ; +; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.550 ns ; +; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.553 ns ; +; 1.586 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.544 ns ; +; 1.586 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.554 ns ; +; 1.587 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.545 ns ; +; 1.588 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.368 ns ; 1.220 ns ; +; 1.589 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.546 ns ; +; 1.589 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.549 ns ; +; 1.592 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.047 ns ; 1.545 ns ; +; 1.593 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.551 ns ; +; 1.593 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.551 ns ; +; 1.594 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.555 ns ; +; 1.594 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.549 ns ; +; 1.594 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.552 ns ; +; 1.595 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.556 ns ; +; 1.595 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.555 ns ; +; 1.597 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.558 ns ; +; 1.597 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.555 ns ; +; 1.598 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.558 ns ; +; 1.599 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.557 ns ; +; 1.600 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.558 ns ; +; 1.600 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.611 ns ; +; 1.601 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.557 ns ; +; 1.602 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.560 ns ; +; 1.602 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.370 ns ; 1.232 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.561 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.049 ns ; 1.555 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.379 ns ; 1.225 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.560 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.049 ns ; 1.555 ns ; +; 1.604 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.562 ns ; +; 1.605 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.566 ns ; +; 1.605 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.567 ns ; +; 1.605 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.563 ns ; +; 1.606 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.568 ns ; +; 1.606 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.386 ns ; 1.220 ns ; +; 1.607 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.379 ns ; 1.228 ns ; +; 1.607 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.448 ns ; 3.055 ns ; +; 1.608 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.576 ns ; +; 1.609 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.567 ns ; +; 1.609 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.567 ns ; +; 1.611 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.602 ns ; +; 1.612 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.371 ns ; 1.241 ns ; +; 1.612 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.326 ns ; 1.938 ns ; +; 1.613 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.581 ns ; +; 1.613 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.571 ns ; +; 1.614 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.051 ns ; 1.563 ns ; +; 1.614 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.572 ns ; +; 1.615 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.565 ns ; +; 1.616 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.627 ns ; +; 1.617 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.608 ns ; +; 1.617 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.575 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.577 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.574 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.576 ns ; +; 1.618 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.580 ns ; +; 1.619 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.579 ns ; +; 1.619 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.610 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.575 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.026 ns ; 1.594 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.570 ns ; +; 1.620 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.584 ns ; +; 1.621 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.582 ns ; +; 1.621 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.579 ns ; +; 1.621 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.578 ns ; +; 1.622 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.580 ns ; +; 1.622 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.580 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.581 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.581 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.587 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.580 ns ; +; 1.623 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.634 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.371 ns ; 1.254 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.582 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.953 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.636 ns ; +; 1.625 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.583 ns ; +; 1.626 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.584 ns ; +; 1.626 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.587 ns ; +; 1.627 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.586 ns ; +; 1.627 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.048 ns ; 1.579 ns ; +; 1.627 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.585 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'CLK33M' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; +; 0.298 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.443 ns ; +; 0.303 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; CLK33M ; CLK33M ; 0.000 ns ; 2.636 ns ; 2.939 ns ; +; 0.305 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.450 ns ; +; 0.305 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.450 ns ; +; 0.308 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.453 ns ; +; 0.318 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; CLK33M ; CLK33M ; 0.000 ns ; 1.141 ns ; 1.459 ns ; +; 0.323 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.503 ns ; +; 0.324 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.193 ns ; 1.517 ns ; +; 0.326 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.471 ns ; +; 0.326 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; CLK33M ; CLK33M ; 0.000 ns ; 1.168 ns ; 1.494 ns ; +; 0.327 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; CLK33M ; CLK33M ; 0.000 ns ; 0.816 ns ; 1.143 ns ; +; 0.327 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.476 ns ; +; 0.328 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.478 ns ; +; 0.331 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 0.803 ns ; 1.134 ns ; +; 0.334 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.514 ns ; +; 0.337 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.486 ns ; +; 0.340 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.138 ns ; 1.478 ns ; +; 0.343 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.162 ns ; 1.505 ns ; +; 0.345 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.490 ns ; +; 0.346 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.493 ns ; +; 0.347 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.864 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.152 ns ; 1.502 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 0.817 ns ; 1.167 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.494 ns ; +; 0.351 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.551 ns ; +; 0.352 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.496 ns ; +; 0.353 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.500 ns ; +; 0.355 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.504 ns ; +; 0.356 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.495 ns ; +; 0.356 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; CLK33M ; CLK33M ; 0.000 ns ; 1.142 ns ; 1.498 ns ; +; 0.357 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.504 ns ; +; 0.358 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.875 ns ; +; 0.359 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.507 ns ; +; 0.359 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; CLK33M ; CLK33M ; 0.000 ns ; 1.162 ns ; 1.521 ns ; +; 0.364 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.511 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.517 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.524 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.521 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.515 ns ; 1.882 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.513 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.159 ns ; 1.527 ns ; +; 0.371 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.551 ns ; +; 0.375 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.524 ns ; +; 0.375 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.522 ns ; +; 0.376 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; CLK33M ; CLK33M ; 0.000 ns ; 2.634 ns ; 3.010 ns ; +; 0.377 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.894 ns ; +; 0.378 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.528 ns ; +; 0.380 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.527 ns ; +; 0.380 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.530 ns ; +; 0.380 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.580 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.526 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.526 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.531 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.561 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.531 ns ; +; 0.384 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.534 ns ; +; 0.385 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.195 ns ; 1.580 ns ; +; 0.386 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.540 ns ; +; 0.387 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.541 ns ; +; 0.387 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.534 ns ; +; 0.387 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.541 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.542 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.539 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.546 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; CLK33M ; CLK33M ; 0.000 ns ; 0.830 ns ; 1.219 ns ; +; 0.389 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.528 ns ; +; 0.390 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.537 ns ; +; 0.390 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.544 ns ; +; 0.390 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.516 ns ; 1.906 ns ; +; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.547 ns ; +; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.550 ns ; +; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.550 ns ; +; 0.394 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.548 ns ; +; 0.394 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.551 ns ; +; 0.394 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.544 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.543 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.543 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.912 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.545 ns ; +; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.541 ns ; +; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.550 ns ; +; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.550 ns ; +; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.553 ns ; +; 0.397 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.544 ns ; +; 0.397 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.554 ns ; +; 0.398 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.545 ns ; +; 0.399 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; CLK33M ; CLK33M ; 0.000 ns ; 0.821 ns ; 1.220 ns ; +; 0.400 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.546 ns ; +; 0.400 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.549 ns ; +; 0.403 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; CLK33M ; CLK33M ; 0.000 ns ; 1.142 ns ; 1.545 ns ; +; 0.404 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.551 ns ; +; 0.404 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.551 ns ; +; 0.405 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.555 ns ; +; 0.405 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.549 ns ; +; 0.405 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.552 ns ; +; 0.406 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.556 ns ; +; 0.406 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.555 ns ; +; 0.408 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.558 ns ; +; 0.408 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.555 ns ; +; 0.409 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.558 ns ; +; 0.410 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.557 ns ; +; 0.411 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.558 ns ; +; 0.411 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.611 ns ; +; 0.412 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.557 ns ; +; 0.413 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.560 ns ; +; 0.413 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; CLK33M ; CLK33M ; 0.000 ns ; 0.819 ns ; 1.232 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.561 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.140 ns ; 1.555 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 0.810 ns ; 1.225 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.560 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.140 ns ; 1.555 ns ; +; 0.415 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.562 ns ; +; 0.416 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.566 ns ; +; 0.416 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.567 ns ; +; 0.416 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.563 ns ; +; 0.417 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.568 ns ; +; 0.417 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; CLK33M ; CLK33M ; 0.000 ns ; 0.803 ns ; 1.220 ns ; +; 0.418 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 0.810 ns ; 1.228 ns ; +; 0.418 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; CLK33M ; CLK33M ; 0.000 ns ; 2.637 ns ; 3.055 ns ; +; 0.419 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.576 ns ; +; 0.420 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.567 ns ; +; 0.420 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.567 ns ; +; 0.422 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.602 ns ; +; 0.423 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; CLK33M ; CLK33M ; 0.000 ns ; 0.818 ns ; 1.241 ns ; +; 0.423 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.515 ns ; 1.938 ns ; +; 0.424 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.581 ns ; +; 0.424 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.571 ns ; +; 0.425 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.138 ns ; 1.563 ns ; +; 0.425 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.572 ns ; +; 0.426 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.565 ns ; +; 0.427 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.627 ns ; +; 0.428 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.608 ns ; +; 0.428 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.575 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.577 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.574 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.576 ns ; +; 0.429 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.580 ns ; +; 0.430 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.579 ns ; +; 0.430 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.610 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.575 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 1.163 ns ; 1.594 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.570 ns ; +; 0.431 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.584 ns ; +; 0.432 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.582 ns ; +; 0.432 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.579 ns ; +; 0.432 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.578 ns ; +; 0.433 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.580 ns ; +; 0.433 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.580 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.581 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.581 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.587 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.580 ns ; +; 0.434 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.634 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 0.818 ns ; 1.254 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.582 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.953 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.636 ns ; +; 0.436 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.583 ns ; +; 0.437 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.584 ns ; +; 0.437 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.587 ns ; +; 0.438 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.586 ns ; +; 0.438 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.141 ns ; 1.579 ns ; +; 0.438 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.585 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Hold: 'MAIN_CLK' ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ +; -3.786 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.716 ns ; 1.930 ns ; +; -3.611 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.756 ns ; 2.145 ns ; +; -3.448 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.709 ns ; 2.261 ns ; +; -3.293 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.327 ns ; 1.034 ns ; +; -3.012 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 2.694 ns ; +; -2.912 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 2.794 ns ; +; -2.048 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.740 ns ; 1.692 ns ; +; -1.996 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.143 ns ; 1.147 ns ; +; -1.985 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.371 ns ; +; -1.961 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.104 ns ; 1.143 ns ; +; -1.958 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.142 ns ; 1.184 ns ; +; -1.934 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.422 ns ; +; -1.923 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.433 ns ; +; -1.867 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.143 ns ; 1.276 ns ; +; -1.842 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.514 ns ; +; -1.835 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.390 ns ; 1.555 ns ; +; -1.795 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.392 ns ; 1.597 ns ; +; -1.749 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.390 ns ; 1.641 ns ; +; -1.745 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.392 ns ; 1.647 ns ; +; -1.641 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.348 ns ; 1.707 ns ; +; -1.595 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.204 ns ; 1.609 ns ; +; -1.569 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.142 ns ; 1.573 ns ; +; -1.508 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.111 ns ; 1.603 ns ; +; -1.350 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe31 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.398 ns ; 2.048 ns ; +; -1.326 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.623 ns ; 2.297 ns ; +; -1.242 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.145 ns ; 1.903 ns ; +; -1.234 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.973 ns ; 0.739 ns ; +; -1.159 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 1.922 ns ; +; -1.152 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe35 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 1.989 ns ; +; -1.113 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.740 ns ; 2.627 ns ; +; -1.095 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 2.046 ns ; +; -1.072 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe19 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.362 ns ; 2.290 ns ; +; -1.055 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 2.086 ns ; +; -1.001 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.966 ns ; 0.965 ns ; +; -0.993 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 1.310 ns ; +; -0.961 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 2.120 ns ; +; -0.918 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.364 ns ; 2.446 ns ; +; -0.893 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.350 ns ; 1.457 ns ; +; -0.849 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.714 ns ; +; -0.825 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.091 ns ; 2.266 ns ; +; -0.819 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe5 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.080 ns ; 2.261 ns ; +; -0.770 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe3 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.080 ns ; 2.310 ns ; +; -0.743 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.179 ns ; 1.436 ns ; +; -0.742 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.179 ns ; 1.437 ns ; +; -0.692 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.089 ns ; 2.397 ns ; +; -0.675 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.521 ns ; 2.846 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; +; -0.668 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 2.975 ns ; +; -0.658 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.905 ns ; +; -0.655 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.908 ns ; +; -0.591 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 2.490 ns ; +; -0.569 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.731 ns ; +; -0.553 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.296 ns ; 1.743 ns ; +; -0.530 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 2.033 ns ; +; -0.447 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.350 ns ; 1.903 ns ; +; -0.441 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.090 ns ; 1.649 ns ; +; -0.422 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.878 ns ; +; -0.420 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.880 ns ; +; -0.407 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe7 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.091 ns ; 2.684 ns ; +; -0.353 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 2.210 ns ; +; -0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.980 ns ; +; -0.319 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.981 ns ; +; -0.198 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.328 ns ; +; -0.184 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.709 ns ; 5.525 ns ; +; -0.155 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.216 ns ; 3.061 ns ; +; -0.143 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 3.990 ns ; +; -0.133 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.718 ns ; 5.585 ns ; +; -0.126 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.007 ns ; +; -0.126 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.685 ns ; 5.559 ns ; +; -0.125 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.004 ns ; +; -0.116 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.017 ns ; +; -0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 5.593 ns ; +; -0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.314 ns ; +; -0.092 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.037 ns ; +; -0.070 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.885 ns ; 3.815 ns ; +; -0.067 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.214 ns ; 3.147 ns ; +; -0.065 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 3.784 ns ; +; -0.060 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.917 ns ; 3.857 ns ; +; -0.059 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe21 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.363 ns ; 3.304 ns ; +; -0.046 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.311 ns ; 4.265 ns ; +; -0.025 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 5.665 ns ; +; -0.022 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.389 ns ; +; -0.006 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.036 ns ; 2.030 ns ; +; 0.007 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.760 ns ; 3.767 ns ; +; 0.026 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.689 ns ; 5.715 ns ; +; 0.067 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.593 ns ; +; 0.072 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.598 ns ; +; 0.091 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.637 ns ; 3.728 ns ; +; 0.093 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.885 ns ; 3.978 ns ; +; 0.093 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.961 ns ; 1.054 ns ; +; 0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.036 ns ; 2.133 ns ; +; 0.104 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.718 ns ; 5.822 ns ; +; 0.118 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 3.761 ns ; +; 0.119 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.422 ns ; +; 0.119 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.422 ns ; +; 0.121 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.598 ns ; 4.719 ns ; +; 0.123 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 3.972 ns ; +; 0.132 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.083 ns ; 2.215 ns ; +; 0.150 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.815 ns ; 3.965 ns ; +; 0.151 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.280 ns ; +; 0.158 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.228 ns ; 1.386 ns ; +; 0.167 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.470 ns ; +; 0.168 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.817 ns ; 3.985 ns ; +; 0.177 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.357 ns ; 2.534 ns ; +; 0.181 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.689 ns ; 5.870 ns ; +; 0.184 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.017 ns ; 6.201 ns ; +; 0.186 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.615 ns ; 3.801 ns ; +; 0.188 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 4.037 ns ; +; 0.191 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.323 ns ; +; 0.192 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.324 ns ; +; 0.195 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.693 ns ; +; 0.216 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.685 ns ; 3.901 ns ; +; 0.226 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.598 ns ; 4.824 ns ; +; 0.231 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.707 ns ; 5.938 ns ; +; 0.235 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.013 ns ; 6.248 ns ; +; 0.243 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.459 ns ; 3.702 ns ; +; 0.261 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.916 ns ; 2.177 ns ; +; 0.262 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.916 ns ; 2.178 ns ; +; 0.265 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.397 ns ; +; 0.266 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.707 ns ; 5.973 ns ; +; 0.291 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.917 ns ; 4.208 ns ; +; 0.311 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.722 ns ; +; 0.313 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.443 ns ; +; 0.314 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.447 ns ; +; 0.315 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.813 ns ; +; 0.315 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.033 ns ; 2.348 ns ; +; 0.318 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.621 ns ; 2.939 ns ; +; 0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.450 ns ; +; 0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.450 ns ; +; 0.323 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.453 ns ; +; 0.324 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.768 ns ; 6.092 ns ; +; 0.333 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.126 ns ; 1.459 ns ; +; 0.338 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.165 ns ; 1.503 ns ; +; 0.339 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.178 ns ; 1.517 ns ; +; 0.341 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.471 ns ; +; 0.341 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.153 ns ; 1.494 ns ; +; 0.342 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.801 ns ; 1.143 ns ; +; 0.342 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.476 ns ; +; 0.343 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.135 ns ; 1.478 ns ; +; 0.344 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.637 ns ; 3.981 ns ; +; 0.346 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.788 ns ; 1.134 ns ; +; 0.347 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 3.990 ns ; +; 0.349 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.165 ns ; 1.514 ns ; +; 0.350 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.653 ns ; +; 0.352 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.486 ns ; +; 0.354 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.067 ns ; 6.421 ns ; +; 0.355 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.123 ns ; 1.478 ns ; +; 0.355 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.853 ns ; +; 0.358 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.147 ns ; 1.505 ns ; +; 0.360 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.490 ns ; +; 0.360 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.771 ns ; +; 0.361 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.493 ns ; +; 0.362 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.502 ns ; 1.864 ns ; +; 0.365 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.137 ns ; 1.502 ns ; +; 0.365 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.802 ns ; 1.167 ns ; +; 0.365 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.129 ns ; 1.494 ns ; +; 0.366 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.185 ns ; 1.551 ns ; +; 0.366 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.747 ns ; 6.113 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.129 ns ; 1.496 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.868 ns ; 1.235 ns ; +; 0.367 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.746 ns ; 6.113 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.500 ns ; +; 0.368 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.264 ns ; 4.632 ns ; +; 0.370 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.504 ns ; +; 0.371 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.124 ns ; 1.495 ns ; +; 0.371 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.127 ns ; 1.498 ns ; +; 0.372 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.504 ns ; +; 0.373 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.502 ns ; 1.875 ns ; +; 0.374 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.133 ns ; 1.507 ns ; +; 0.374 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 6.080 ns ; +; 0.374 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.147 ns ; 1.521 ns ; +; 0.376 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 6.066 ns ; +; 0.379 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.511 ns ; +; 0.381 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.460 ns ; 3.841 ns ; +; 0.382 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.135 ns ; 1.517 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tsu ; ++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; -4.528 ns ; 1.000 ns ; 5.528 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; MAIN_CLK ; +; -4.169 ns ; 1.000 ns ; 5.169 ns ; VD[19] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; MAIN_CLK ; +; -4.134 ns ; 1.000 ns ; 5.134 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -4.083 ns ; 1.000 ns ; 5.083 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.956 ns ; 1.000 ns ; 4.956 ns ; VD[27] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; MAIN_CLK ; +; -3.930 ns ; 1.000 ns ; 4.930 ns ; nINDEX ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; CLK33M ; +; -3.930 ns ; 1.000 ns ; 4.930 ns ; VD[31] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; MAIN_CLK ; +; -3.927 ns ; 1.000 ns ; 4.927 ns ; VD[1] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; MAIN_CLK ; +; -3.927 ns ; 1.000 ns ; 4.927 ns ; VD[9] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; MAIN_CLK ; +; -3.913 ns ; 1.000 ns ; 4.913 ns ; VD[2] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; MAIN_CLK ; +; -3.912 ns ; 1.000 ns ; 4.912 ns ; VD[12] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -3.885 ns ; 1.000 ns ; 4.885 ns ; VD[20] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; MAIN_CLK ; +; -3.883 ns ; 1.000 ns ; 4.883 ns ; VD[25] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.859 ns ; 1.000 ns ; 4.859 ns ; VD[28] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; MAIN_CLK ; +; -3.855 ns ; 1.000 ns ; 4.855 ns ; VD[22] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; MAIN_CLK ; +; -3.851 ns ; 1.000 ns ; 4.851 ns ; VD[17] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -3.827 ns ; 1.000 ns ; 4.827 ns ; VD[11] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.804 ns ; 1.000 ns ; 4.804 ns ; VD[0] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; MAIN_CLK ; +; -3.801 ns ; 1.000 ns ; 4.801 ns ; VD[10] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; MAIN_CLK ; +; -3.796 ns ; 1.000 ns ; 4.796 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state ; MAIN_CLK ; +; -3.794 ns ; 1.000 ns ; 4.794 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1 ; MAIN_CLK ; +; -3.794 ns ; 1.000 ns ; 4.794 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state ; MAIN_CLK ; +; -3.783 ns ; 1.000 ns ; 4.783 ns ; VD[14] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; MAIN_CLK ; +; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.765 ns ; 1.000 ns ; 4.765 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; CLK33M ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; +; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; +; -3.752 ns ; 1.000 ns ; 4.752 ns ; VD[6] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; MAIN_CLK ; +; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; +; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; +; -3.744 ns ; 1.000 ns ; 4.744 ns ; VD[21] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; MAIN_CLK ; +; -3.742 ns ; 1.000 ns ; 4.742 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.740 ns ; 1.000 ns ; 4.740 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.740 ns ; 1.000 ns ; 4.740 ns ; VD[16] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; MAIN_CLK ; +; -3.739 ns ; 1.000 ns ; 4.739 ns ; VD[29] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; MAIN_CLK ; +; -3.735 ns ; 1.000 ns ; 4.735 ns ; VD[15] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; MAIN_CLK ; +; -3.708 ns ; 1.000 ns ; 4.708 ns ; VD[26] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; MAIN_CLK ; +; -3.707 ns ; 1.000 ns ; 4.707 ns ; VD[13] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.703 ns ; 1.000 ns ; 4.703 ns ; VD[3] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; MAIN_CLK ; +; -3.699 ns ; 1.000 ns ; 4.699 ns ; VD[30] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; MAIN_CLK ; +; -3.694 ns ; 1.000 ns ; 4.694 ns ; VD[24] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.684 ns ; 1.000 ns ; 4.684 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.684 ns ; 1.000 ns ; 4.684 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.680 ns ; 1.000 ns ; 4.680 ns ; FB_AD[30] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; +; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; +; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; +; -3.634 ns ; 1.000 ns ; 4.634 ns ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; +; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; +; -3.471 ns ; 1.000 ns ; 4.471 ns ; VD[4] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; +; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; +; -3.386 ns ; 1.000 ns ; 4.386 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; MAIN_CLK ; +; -3.339 ns ; 1.000 ns ; 4.339 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; +; -3.334 ns ; 1.000 ns ; 4.334 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE ; CLK33M ; +; -3.324 ns ; 1.000 ns ; 4.324 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.290 ns ; 1.000 ns ; 4.290 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.272 ns ; 1.000 ns ; 4.272 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; +; -3.248 ns ; 1.000 ns ; 4.248 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; CLK33M ; +; -3.245 ns ; 1.000 ns ; 4.245 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.236 ns ; 1.000 ns ; 4.236 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.226 ns ; 1.000 ns ; 4.226 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.226 ns ; 1.000 ns ; 4.226 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; +; -3.218 ns ; 1.000 ns ; 4.218 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; +; -3.214 ns ; 1.000 ns ; 4.214 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.214 ns ; 1.000 ns ; 4.214 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; +; -3.211 ns ; 1.000 ns ; 4.211 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; MAIN_CLK ; +; -3.208 ns ; 1.000 ns ; 4.208 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.206 ns ; 1.000 ns ; 4.206 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.203 ns ; 1.000 ns ; 4.203 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.199 ns ; 1.000 ns ; 4.199 ns ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; +; -3.197 ns ; 1.000 ns ; 4.197 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; +; -3.194 ns ; 1.000 ns ; 4.194 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; +; -3.193 ns ; 1.000 ns ; 4.193 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.190 ns ; 1.000 ns ; 4.190 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; +; -3.187 ns ; 1.000 ns ; 4.187 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; +; -3.182 ns ; 1.000 ns ; 4.182 ns ; HD_DD ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[1] ; CLK33M ; +; -3.181 ns ; 1.000 ns ; 4.181 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.174 ns ; 1.000 ns ; 4.174 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; +; -3.173 ns ; 1.000 ns ; 4.173 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; +; -3.172 ns ; 1.000 ns ; 4.172 ns ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; +; -3.171 ns ; 1.000 ns ; 4.171 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; +; -3.167 ns ; 1.000 ns ; 4.167 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; +; -3.162 ns ; 1.000 ns ; 4.162 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; +; -3.160 ns ; 1.000 ns ; 4.160 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; MAIN_CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tco ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ +; -14.840 ns ; 1.000 ns ; 15.840 ns ; interrupt_handler:nobody|INT_LATCH[8] ; nIRQ[5] ; MAIN_CLK ; +; -14.829 ns ; 1.000 ns ; 15.829 ns ; interrupt_handler:nobody|INT_LATCH[9] ; nIRQ[5] ; MAIN_CLK ; +; -13.764 ns ; 1.000 ns ; 14.764 ns ; interrupt_handler:nobody|INT_LATCH[8] ; FB_AD[8] ; MAIN_CLK ; +; -13.654 ns ; 1.000 ns ; 14.654 ns ; interrupt_handler:nobody|INT_LATCH[9] ; FB_AD[9] ; MAIN_CLK ; +; -13.587 ns ; 1.000 ns ; 14.587 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.587 ns ; 1.000 ns ; 14.587 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.587 ns ; 1.000 ns ; 14.587 ns ; interrupt_handler:nobody|INT_LATCH[8] ; FB_AD[29] ; MAIN_CLK ; +; -13.575 ns ; 1.000 ns ; 14.575 ns ; interrupt_handler:nobody|INT_LATCH[9] ; FB_AD[29] ; MAIN_CLK ; +; -13.493 ns ; 1.000 ns ; 14.493 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[18] ; MAIN_CLK ; +; -13.477 ns ; 1.000 ns ; 14.477 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[18] ; MAIN_CLK ; +; -13.457 ns ; 1.000 ns ; 14.457 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; FB_AD[18] ; MAIN_CLK ; +; -13.418 ns ; 1.000 ns ; 14.418 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.386 ns ; 1.000 ns ; 14.386 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; FB_AD[7] ; MAIN_CLK ; +; -13.358 ns ; 1.000 ns ; 14.358 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[18] ; MAIN_CLK ; +; -13.358 ns ; 1.000 ns ; 14.358 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[18] ; MAIN_CLK ; +; -13.309 ns ; 1.000 ns ; 14.309 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[27] ; MAIN_CLK ; +; -13.294 ns ; 1.000 ns ; 14.294 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; FB_AD[27] ; MAIN_CLK ; +; -13.259 ns ; 1.000 ns ; 14.259 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.250 ns ; 1.000 ns ; 14.250 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.227 ns ; 1.000 ns ; 14.227 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.207 ns ; 1.000 ns ; 14.207 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[18] ; MAIN_CLK ; +; -13.171 ns ; 1.000 ns ; 14.171 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.170 ns ; 1.000 ns ; 14.170 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; FB_AD[27] ; MAIN_CLK ; +; -13.157 ns ; 1.000 ns ; 14.157 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2] ; FB_AD[18] ; MAIN_CLK ; +; -13.028 ns ; 1.000 ns ; 14.028 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[27] ; MAIN_CLK ; +; -13.015 ns ; 1.000 ns ; 14.015 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2] ; FB_AD[27] ; MAIN_CLK ; +; -12.999 ns ; 1.000 ns ; 13.999 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.921 ns ; 1.000 ns ; 13.921 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.886 ns ; 1.000 ns ; 13.886 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.876 ns ; 1.000 ns ; 13.876 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.861 ns ; 1.000 ns ; 13.861 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] ; FB_AD[27] ; MAIN_CLK ; +; -12.846 ns ; 1.000 ns ; 13.846 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; FB_AD[27] ; MAIN_CLK ; +; -12.836 ns ; 1.000 ns ; 13.836 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18] ; FB_AD[18] ; MAIN_CLK ; +; -12.823 ns ; 1.000 ns ; 13.823 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.817 ns ; 1.000 ns ; 13.817 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0] ; FB_AD[27] ; MAIN_CLK ; +; -12.784 ns ; 1.000 ns ; 13.784 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[27] ; MAIN_CLK ; +; -12.732 ns ; 1.000 ns ; 13.732 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[5] ; FB_AD[7] ; MAIN_CLK ; +; -12.620 ns ; 1.000 ns ; 13.620 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.567 ns ; 1.000 ns ; 13.567 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3] ; FB_AD[27] ; MAIN_CLK ; +; -12.434 ns ; 1.000 ns ; 13.434 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.425 ns ; 1.000 ns ; 13.425 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[7] ; MAIN_CLK ; +; -12.404 ns ; 1.000 ns ; 13.404 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; FB_AD[8] ; MAIN_CLK ; +; -12.403 ns ; 1.000 ns ; 13.403 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.361 ns ; 1.000 ns ; 13.361 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; FB_AD[23] ; MAIN_CLK ; +; -12.361 ns ; 1.000 ns ; 13.361 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; FB_AD[27] ; MAIN_CLK ; +; -12.302 ns ; 1.000 ns ; 13.302 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4] ; FB_AD[7] ; MAIN_CLK ; +; -12.301 ns ; 1.000 ns ; 13.301 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27] ; FB_AD[27] ; MAIN_CLK ; +; -12.300 ns ; 1.000 ns ; 13.300 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.286 ns ; 1.000 ns ; 13.286 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; FB_AD[18] ; MAIN_CLK ; +; -12.285 ns ; 1.000 ns ; 13.285 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.283 ns ; 1.000 ns ; 13.283 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; FB_AD[7] ; CLK33M ; +; -12.260 ns ; 1.000 ns ; 13.260 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.241 ns ; 1.000 ns ; 13.241 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[5] ; FB_AD[7] ; MAIN_CLK ; +; -12.219 ns ; 1.000 ns ; 13.219 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.211 ns ; 1.000 ns ; 13.211 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.205 ns ; 1.000 ns ; 13.205 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[27] ; MAIN_CLK ; +; -12.200 ns ; 1.000 ns ; 13.200 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; FB_AD[7] ; MAIN_CLK ; +; -12.186 ns ; 1.000 ns ; 13.186 ns ; interrupt_handler:nobody|WERTE[2][0] ; FB_AD[18] ; MAIN_CLK ; +; -12.182 ns ; 1.000 ns ; 13.182 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; FB_AD[22] ; MAIN_CLK ; +; -12.177 ns ; 1.000 ns ; 13.177 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[18] ; MAIN_CLK ; +; -12.175 ns ; 1.000 ns ; 13.175 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.173 ns ; 1.000 ns ; 13.173 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[17] ; MAIN_CLK ; +; -12.166 ns ; 1.000 ns ; 13.166 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; FB_AD[18] ; MAIN_CLK ; +; -12.158 ns ; 1.000 ns ; 13.158 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.157 ns ; 1.000 ns ; 13.157 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[17] ; MAIN_CLK ; +; -12.082 ns ; 1.000 ns ; 13.082 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.055 ns ; 1.000 ns ; 13.055 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; FB_AD[21] ; MAIN_CLK ; +; -12.052 ns ; 1.000 ns ; 13.052 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; FB_AD[17] ; MAIN_CLK ; +; -12.039 ns ; 1.000 ns ; 13.039 ns ; interrupt_handler:nobody|ACP_CONF[28] ; FB_AD[7] ; MAIN_CLK ; +; -12.038 ns ; 1.000 ns ; 13.038 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[17] ; MAIN_CLK ; +; -12.022 ns ; 1.000 ns ; 13.022 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[5] ; FB_AD[7] ; MAIN_CLK ; +; -12.008 ns ; 1.000 ns ; 13.008 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QB ; MAIN_CLK ; +; -12.005 ns ; 1.000 ns ; 13.005 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_DOUT[2] ; FB_AD[18] ; MAIN_CLK ; +; -12.004 ns ; 1.000 ns ; 13.004 ns ; interrupt_handler:nobody|WERTE[2][62] ; FB_AD[18] ; MAIN_CLK ; +; -11.984 ns ; 1.000 ns ; 12.984 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[27] ; MAIN_CLK ; +; -11.978 ns ; 1.000 ns ; 12.978 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1] ; YM_QB ; MAIN_CLK ; +; -11.968 ns ; 1.000 ns ; 12.968 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; FB_AD[27] ; MAIN_CLK ; +; -11.957 ns ; 1.000 ns ; 12.957 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[7] ; MAIN_CLK ; +; -11.946 ns ; 1.000 ns ; 12.946 ns ; interrupt_handler:nobody|WERTE[2][42] ; FB_AD[18] ; MAIN_CLK ; +; -11.939 ns ; 1.000 ns ; 12.939 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[17] ; MAIN_CLK ; +; -11.938 ns ; 1.000 ns ; 12.938 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4] ; YM_QB ; MAIN_CLK ; +; -11.937 ns ; 1.000 ns ; 12.937 ns ; interrupt_handler:nobody|WERTE[2][10] ; FB_AD[18] ; MAIN_CLK ; +; -11.935 ns ; 1.000 ns ; 12.935 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; FB_AD[9] ; MAIN_CLK ; +; -11.933 ns ; 1.000 ns ; 12.933 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FB_AD[18] ; MAIN_CLK ; +; -11.924 ns ; 1.000 ns ; 12.924 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; FB_AD[26] ; MAIN_CLK ; +; -11.922 ns ; 1.000 ns ; 12.922 ns ; interrupt_handler:nobody|WERTE[2][58] ; FB_AD[18] ; MAIN_CLK ; +; -11.900 ns ; 1.000 ns ; 12.900 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[17] ; MAIN_CLK ; +; -11.874 ns ; 1.000 ns ; 12.874 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; FB_AD[17] ; MAIN_CLK ; +; -11.871 ns ; 1.000 ns ; 12.871 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[20] ; MAIN_CLK ; +; -11.867 ns ; 1.000 ns ; 12.867 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.859 ns ; 1.000 ns ; 12.859 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[7] ; MAIN_CLK ; +; -11.857 ns ; 1.000 ns ; 12.857 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.845 ns ; 1.000 ns ; 12.845 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[17] ; MAIN_CLK ; +; -11.842 ns ; 1.000 ns ; 12.842 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; FB_AD[20] ; MAIN_CLK ; +; -11.834 ns ; 1.000 ns ; 12.834 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[20] ; MAIN_CLK ; +; -11.831 ns ; 1.000 ns ; 12.831 ns ; interrupt_handler:nobody|WERTE[2][4] ; FB_AD[18] ; MAIN_CLK ; +; -11.813 ns ; 1.000 ns ; 12.813 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; FB_AD[18] ; MAIN_CLK ; +; -11.794 ns ; 1.000 ns ; 12.794 ns ; interrupt_handler:nobody|WERTE[2][43] ; FB_AD[18] ; MAIN_CLK ; +; -11.787 ns ; 1.000 ns ; 12.787 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FB_AD[18] ; MAIN_CLK ; +; -11.775 ns ; 1.000 ns ; 12.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; FB_AD[7] ; MAIN_CLK ; +; -11.774 ns ; 1.000 ns ; 12.774 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FB_AD[27] ; MAIN_CLK ; +; -11.769 ns ; 1.000 ns ; 12.769 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[18] ; MAIN_CLK ; +; -11.762 ns ; 1.000 ns ; 12.762 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.751 ns ; 1.000 ns ; 12.751 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5] ; YM_QC ; MAIN_CLK ; +; -11.747 ns ; 1.000 ns ; 12.747 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.746 ns ; 1.000 ns ; 12.746 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27] ; FB_AD[27] ; MAIN_CLK ; +; -11.736 ns ; 1.000 ns ; 12.736 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[7] ; MAIN_CLK ; +; -11.727 ns ; 1.000 ns ; 12.727 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.725 ns ; 1.000 ns ; 12.725 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.VECTOR_OUT ; FB_AD[7] ; MAIN_CLK ; +; -11.724 ns ; 1.000 ns ; 12.724 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2] ; YM_QC ; MAIN_CLK ; +; -11.721 ns ; 1.000 ns ; 12.721 ns ; interrupt_handler:nobody|WERTE[5][8] ; FB_AD[21] ; MAIN_CLK ; +; -11.717 ns ; 1.000 ns ; 12.717 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[23] ; MAIN_CLK ; +; -11.710 ns ; 1.000 ns ; 12.710 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7] ; FB_AD[9] ; MAIN_CLK ; +; -11.709 ns ; 1.000 ns ; 12.709 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FB_AD[18] ; MAIN_CLK ; +; -11.708 ns ; 1.000 ns ; 12.708 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB[5] ; FB_AD[7] ; MAIN_CLK ; +; -11.700 ns ; 1.000 ns ; 12.700 ns ; interrupt_handler:nobody|WERTE[2][2] ; FB_AD[18] ; MAIN_CLK ; +; -11.694 ns ; 1.000 ns ; 12.694 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; FB_AD[28] ; MAIN_CLK ; +; -11.693 ns ; 1.000 ns ; 12.693 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; FB_AD[9] ; MAIN_CLK ; +; -11.692 ns ; 1.000 ns ; 12.692 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[18] ; MAIN_CLK ; +; -11.680 ns ; 1.000 ns ; 12.680 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1] ; FB_AD[17] ; MAIN_CLK ; +; -11.675 ns ; 1.000 ns ; 12.675 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[23] ; MAIN_CLK ; +; -11.673 ns ; 1.000 ns ; 12.673 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[5] ; FB_AD[7] ; MAIN_CLK ; +; -11.659 ns ; 1.000 ns ; 12.659 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.649 ns ; 1.000 ns ; 12.649 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.648 ns ; 1.000 ns ; 12.648 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[25] ; MAIN_CLK ; +; -11.646 ns ; 1.000 ns ; 12.646 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[20] ; MAIN_CLK ; +; -11.640 ns ; 1.000 ns ; 12.640 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.633 ns ; 1.000 ns ; 12.633 ns ; interrupt_handler:nobody|WERTE[2][38] ; FB_AD[18] ; MAIN_CLK ; +; -11.631 ns ; 1.000 ns ; 12.631 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[19] ; MAIN_CLK ; +; -11.628 ns ; 1.000 ns ; 12.628 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; FB_AD[17] ; MAIN_CLK ; +; -11.628 ns ; 1.000 ns ; 12.628 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FB_AD[27] ; MAIN_CLK ; +; -11.627 ns ; 1.000 ns ; 12.627 ns ; interrupt_handler:nobody|WERTE[2][63] ; FB_AD[18] ; MAIN_CLK ; +; -11.620 ns ; 1.000 ns ; 12.620 ns ; interrupt_handler:nobody|WERTE[2][61] ; FB_AD[18] ; MAIN_CLK ; +; -11.620 ns ; 1.000 ns ; 12.620 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FB_AD[18] ; MAIN_CLK ; +; -11.619 ns ; 1.000 ns ; 12.619 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0] ; YM_QB ; MAIN_CLK ; +; -11.618 ns ; 1.000 ns ; 12.618 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FB_AD[18] ; MAIN_CLK ; +; -11.616 ns ; 1.000 ns ; 12.616 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[20] ; MAIN_CLK ; +; -11.616 ns ; 1.000 ns ; 12.616 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; FB_AD[25] ; MAIN_CLK ; +; -11.608 ns ; 1.000 ns ; 12.608 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[19] ; MAIN_CLK ; +; -11.607 ns ; 1.000 ns ; 12.607 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[21] ; MAIN_CLK ; +; -11.595 ns ; 1.000 ns ; 12.595 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FB_AD[27] ; MAIN_CLK ; +; -11.592 ns ; 1.000 ns ; 12.592 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[20] ; MAIN_CLK ; +; -11.592 ns ; 1.000 ns ; 12.592 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[18] ; MAIN_CLK ; +; -11.589 ns ; 1.000 ns ; 12.589 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3] ; YM_QA ; MAIN_CLK ; +; -11.588 ns ; 1.000 ns ; 12.588 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.588 ns ; 1.000 ns ; 12.588 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FB_AD[18] ; MAIN_CLK ; +; -11.583 ns ; 1.000 ns ; 12.583 ns ; interrupt_handler:nobody|WERTE[2][57] ; FB_AD[18] ; MAIN_CLK ; +; -11.582 ns ; 1.000 ns ; 12.582 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[22] ; MAIN_CLK ; +; -11.579 ns ; 1.000 ns ; 12.579 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QA ; MAIN_CLK ; +; -11.578 ns ; 1.000 ns ; 12.578 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; FB_AD[21] ; MAIN_CLK ; +; -11.576 ns ; 1.000 ns ; 12.576 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7] ; FB_AD[23] ; MAIN_CLK ; +; -11.576 ns ; 1.000 ns ; 12.576 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[22] ; MAIN_CLK ; +; -11.567 ns ; 1.000 ns ; 12.567 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[22] ; MAIN_CLK ; +; -11.559 ns ; 1.000 ns ; 12.559 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; FB_AD[23] ; MAIN_CLK ; +; -11.552 ns ; 1.000 ns ; 12.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QC ; MAIN_CLK ; +; -11.550 ns ; 1.000 ns ; 12.550 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FB_AD[27] ; MAIN_CLK ; +; -11.545 ns ; 1.000 ns ; 12.545 ns ; interrupt_handler:nobody|WERTE[2][31] ; FB_AD[18] ; MAIN_CLK ; +; -11.544 ns ; 1.000 ns ; 12.544 ns ; interrupt_handler:nobody|WERTE[2][6] ; FB_AD[18] ; MAIN_CLK ; +; -11.543 ns ; 1.000 ns ; 12.543 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.542 ns ; 1.000 ns ; 12.542 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2] ; FB_AD[18] ; MAIN_CLK ; +; -11.541 ns ; 1.000 ns ; 12.541 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[23] ; MAIN_CLK ; +; -11.540 ns ; 1.000 ns ; 12.540 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.540 ns ; 1.000 ns ; 12.540 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5] ; FB_AD[21] ; MAIN_CLK ; +; -11.537 ns ; 1.000 ns ; 12.537 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; FB_AD[3] ; MAIN_CLK ; +; -11.531 ns ; 1.000 ns ; 12.531 ns ; interrupt_handler:nobody|WERTE[2][45] ; FB_AD[18] ; MAIN_CLK ; +; -11.527 ns ; 1.000 ns ; 12.527 ns ; interrupt_handler:nobody|WERTE[2][7] ; FB_AD[18] ; MAIN_CLK ; +; -11.527 ns ; 1.000 ns ; 12.527 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; FB_AD[25] ; MAIN_CLK ; +; -11.526 ns ; 1.000 ns ; 12.526 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; FB_AD[20] ; MAIN_CLK ; +; -11.526 ns ; 1.000 ns ; 12.526 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[23] ; MAIN_CLK ; +; -11.526 ns ; 1.000 ns ; 12.526 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[23] ; MAIN_CLK ; +; -11.508 ns ; 1.000 ns ; 12.508 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3] ; FB_AD[27] ; MAIN_CLK ; +; -11.507 ns ; 1.000 ns ; 12.507 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FB_AD[18] ; MAIN_CLK ; +; -11.505 ns ; 1.000 ns ; 12.505 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[23] ; MAIN_CLK ; +; -11.504 ns ; 1.000 ns ; 12.504 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; FB_AD[27] ; MAIN_CLK ; +; -11.502 ns ; 1.000 ns ; 12.502 ns ; interrupt_handler:nobody|WERTE[2][60] ; FB_AD[18] ; MAIN_CLK ; +; -11.502 ns ; 1.000 ns ; 12.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; FB_AD[26] ; MAIN_CLK ; +; -11.495 ns ; 1.000 ns ; 12.495 ns ; interrupt_handler:nobody|WERTE[2][53] ; FB_AD[18] ; MAIN_CLK ; +; -11.492 ns ; 1.000 ns ; 12.492 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FB_AD[18] ; MAIN_CLK ; +; -11.488 ns ; 1.000 ns ; 12.488 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; FB_AD[3] ; MAIN_CLK ; +; -11.487 ns ; 1.000 ns ; 12.487 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[7] ; MAIN_CLK ; +; -11.480 ns ; 1.000 ns ; 12.480 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[23] ; MAIN_CLK ; +; -11.480 ns ; 1.000 ns ; 12.480 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; FB_AD[21] ; MAIN_CLK ; +; -11.479 ns ; 1.000 ns ; 12.479 ns ; interrupt_handler:nobody|WERTE[2][36] ; FB_AD[18] ; MAIN_CLK ; +; -11.478 ns ; 1.000 ns ; 12.478 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[2] ; YM_QB ; MAIN_CLK ; +; -11.470 ns ; 1.000 ns ; 12.470 ns ; interrupt_handler:nobody|WERTE[2][15] ; FB_AD[18] ; MAIN_CLK ; +; -11.461 ns ; 1.000 ns ; 12.461 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FB_AD[27] ; MAIN_CLK ; +; -11.460 ns ; 1.000 ns ; 12.460 ns ; interrupt_handler:nobody|WERTE[2][8] ; FB_AD[18] ; MAIN_CLK ; +; -11.459 ns ; 1.000 ns ; 12.459 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FB_AD[27] ; MAIN_CLK ; +; -11.455 ns ; 1.000 ns ; 12.455 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0] ; YM_QA ; MAIN_CLK ; +; -11.455 ns ; 1.000 ns ; 12.455 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[22] ; MAIN_CLK ; +; -11.451 ns ; 1.000 ns ; 12.451 ns ; interrupt_handler:nobody|WERTE[2][50] ; FB_AD[18] ; MAIN_CLK ; +; -11.447 ns ; 1.000 ns ; 12.447 ns ; interrupt_handler:nobody|WERTE[2][52] ; FB_AD[18] ; MAIN_CLK ; +; -11.444 ns ; 1.000 ns ; 12.444 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; FB_AD[27] ; MAIN_CLK ; +; -11.443 ns ; 1.000 ns ; 12.443 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[20] ; MAIN_CLK ; +; -11.441 ns ; 1.000 ns ; 12.441 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; FB_AD[18] ; MAIN_CLK ; +; -11.435 ns ; 1.000 ns ; 12.435 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[18] ; MAIN_CLK ; +; -11.433 ns ; 1.000 ns ; 12.433 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[4] ; YM_QB ; MAIN_CLK ; +; -11.432 ns ; 1.000 ns ; 12.432 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5] ; FB_AD[7] ; MAIN_CLK ; +; -11.431 ns ; 1.000 ns ; 12.431 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[20] ; MAIN_CLK ; +; -11.429 ns ; 1.000 ns ; 12.429 ns ; interrupt_handler:nobody|WERTE[2][55] ; FB_AD[18] ; MAIN_CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------+ +; tpd ; ++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ +; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; ++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ +; -11.944 ns ; 1.000 ns ; 12.944 ns ; nFB_CS1 ; FB_AD[18] ; +; -11.849 ns ; 1.000 ns ; 12.849 ns ; FB_SIZE0 ; FB_AD[27] ; +; -11.785 ns ; 1.000 ns ; 12.785 ns ; nFB_CS1 ; FB_AD[27] ; +; -11.694 ns ; 1.000 ns ; 12.694 ns ; nFB_CS1 ; FB_AD[7] ; +; -11.672 ns ; 1.000 ns ; 12.672 ns ; FB_SIZE1 ; FB_AD[27] ; +; -11.625 ns ; 1.000 ns ; 12.625 ns ; nFB_WR ; FB_AD[7] ; +; -11.514 ns ; 1.000 ns ; 12.514 ns ; FB_SIZE0 ; FB_AD[18] ; +; -11.464 ns ; 1.000 ns ; 12.464 ns ; IDE_INT ; FB_AD[7] ; +; -11.450 ns ; 1.000 ns ; 12.450 ns ; SRD[11] ; FB_AD[27] ; +; -11.438 ns ; 1.000 ns ; 12.438 ns ; nFB_OE ; FB_AD[27] ; +; -11.420 ns ; 1.000 ns ; 12.420 ns ; nFB_CS2 ; FB_AD[27] ; +; -11.399 ns ; 1.000 ns ; 12.399 ns ; nFB_WR ; FB_AD[27] ; +; -11.376 ns ; 1.000 ns ; 12.376 ns ; nFB_WR ; FB_AD[18] ; +; -11.337 ns ; 1.000 ns ; 12.337 ns ; FB_SIZE1 ; FB_AD[18] ; +; -11.243 ns ; 1.000 ns ; 12.243 ns ; nFB_CS2 ; FB_AD[18] ; +; -10.918 ns ; 1.000 ns ; 11.918 ns ; nFB_CS1 ; FB_AD[20] ; +; -10.824 ns ; 1.000 ns ; 11.824 ns ; nFB_CS2 ; FB_AD[7] ; +; -10.814 ns ; 1.000 ns ; 11.814 ns ; FB_SIZE0 ; FB_AD[7] ; +; -10.798 ns ; 1.000 ns ; 11.798 ns ; nFB_OE ; FB_AD[7] ; +; -10.779 ns ; 1.000 ns ; 11.779 ns ; CTS ; FB_AD[18] ; +; -10.758 ns ; 1.000 ns ; 11.758 ns ; FB_SIZE1 ; FB_AD[7] ; +; -10.658 ns ; 1.000 ns ; 11.658 ns ; MAIN_CLK ; FB_AD[27] ; +; -10.631 ns ; 1.000 ns ; 11.631 ns ; nFB_OE ; FB_AD[18] ; +; -10.578 ns ; 1.000 ns ; 11.578 ns ; MAIN_CLK ; FB_AD[7] ; +; -10.573 ns ; 1.000 ns ; 11.573 ns ; nFB_CS2 ; FB_AD[20] ; +; -10.561 ns ; 1.000 ns ; 11.561 ns ; nFB_CS1 ; FB_AD[6] ; +; -10.549 ns ; 1.000 ns ; 11.549 ns ; FB_SIZE0 ; FB_AD[20] ; +; -10.543 ns ; 1.000 ns ; 11.543 ns ; nFB_CS1 ; FB_AD[9] ; +; -10.529 ns ; 1.000 ns ; 11.529 ns ; FB_SIZE0 ; FB_AD[23] ; +; -10.521 ns ; 1.000 ns ; 11.521 ns ; nFB_CS1 ; FB_AD[23] ; +; -10.471 ns ; 1.000 ns ; 11.471 ns ; FB_SIZE1 ; FB_AD[20] ; +; -10.451 ns ; 1.000 ns ; 11.451 ns ; FB_SIZE1 ; FB_AD[23] ; +; -10.425 ns ; 1.000 ns ; 11.425 ns ; nFB_WR ; FB_AD[9] ; +; -10.420 ns ; 1.000 ns ; 11.420 ns ; nFB_CS1 ; FB_AD[17] ; +; -10.415 ns ; 1.000 ns ; 11.415 ns ; nFB_CS1 ; FB_AD[25] ; +; -10.412 ns ; 1.000 ns ; 11.412 ns ; nFB_CS1 ; FB_AD[21] ; +; -10.370 ns ; 1.000 ns ; 11.370 ns ; nFB_OE ; FB_AD[20] ; +; -10.364 ns ; 1.000 ns ; 11.364 ns ; nFB_WR ; FB_AD[25] ; +; -10.362 ns ; 1.000 ns ; 11.362 ns ; nFB_CS1 ; FB_AD[26] ; +; -10.361 ns ; 1.000 ns ; 11.361 ns ; nFB_WR ; FB_AD[20] ; +; -10.335 ns ; 1.000 ns ; 11.335 ns ; nFB_CS2 ; FB_AD[23] ; +; -10.318 ns ; 1.000 ns ; 11.318 ns ; nFB_CS2 ; FB_AD[21] ; +; -10.317 ns ; 1.000 ns ; 11.317 ns ; nFB_WR ; FB_AD[22] ; +; -10.312 ns ; 1.000 ns ; 11.312 ns ; nFB_CS1 ; FB_AD[22] ; +; -10.311 ns ; 1.000 ns ; 11.311 ns ; nFB_WR ; FB_AD[26] ; +; -10.291 ns ; 1.000 ns ; 11.291 ns ; nFB_WR ; FB_AD[23] ; +; -10.278 ns ; 1.000 ns ; 11.278 ns ; FB_SIZE0 ; FB_AD[17] ; +; -10.277 ns ; 1.000 ns ; 11.277 ns ; MAIN_CLK ; FB_AD[18] ; +; -10.221 ns ; 1.000 ns ; 11.221 ns ; FB_SIZE0 ; FB_AD[29] ; +; -10.220 ns ; 1.000 ns ; 11.220 ns ; nFB_CS2 ; FB_AD[22] ; +; -10.178 ns ; 1.000 ns ; 11.178 ns ; FB_SIZE0 ; FB_AD[19] ; +; -10.146 ns ; 1.000 ns ; 11.146 ns ; FB_SIZE0 ; FB_AD[31] ; +; -10.136 ns ; 1.000 ns ; 11.136 ns ; nFB_CS1 ; FB_AD[24] ; +; -10.123 ns ; 1.000 ns ; 11.123 ns ; nFB_CS1 ; FB_AD[19] ; +; -10.101 ns ; 1.000 ns ; 11.101 ns ; FB_SIZE1 ; FB_AD[17] ; +; -10.085 ns ; 1.000 ns ; 11.085 ns ; nFB_WR ; FB_AD[24] ; +; -10.081 ns ; 1.000 ns ; 11.081 ns ; nFB_CS1 ; FB_AD[16] ; +; -10.077 ns ; 1.000 ns ; 11.077 ns ; nFB_CS2 ; FB_AD[19] ; +; -10.077 ns ; 1.000 ns ; 11.077 ns ; FB_SIZE0 ; FB_AD[21] ; +; -10.076 ns ; 1.000 ns ; 11.076 ns ; FB_SIZE1 ; FB_AD[19] ; +; -10.074 ns ; 1.000 ns ; 11.074 ns ; SRD[9] ; FB_AD[25] ; +; -10.070 ns ; 1.000 ns ; 11.070 ns ; nFB_CS1 ; FB_AD[29] ; +; -10.061 ns ; 1.000 ns ; 11.061 ns ; nFB_OE ; FB_AD[21] ; +; -10.060 ns ; 1.000 ns ; 11.060 ns ; nFB_WR ; FB_AD[21] ; +; -10.051 ns ; 1.000 ns ; 11.051 ns ; nFB_WR ; FB_AD[19] ; +; -10.044 ns ; 1.000 ns ; 11.044 ns ; FB_SIZE1 ; FB_AD[29] ; +; -10.041 ns ; 1.000 ns ; 11.041 ns ; FB_SIZE0 ; FB_AD[30] ; +; -10.021 ns ; 1.000 ns ; 11.021 ns ; FB_SIZE1 ; FB_AD[21] ; +; -10.019 ns ; 1.000 ns ; 11.019 ns ; nFB_WR ; FB_AD[29] ; +; -10.004 ns ; 1.000 ns ; 11.004 ns ; nFB_WR ; FB_AD[6] ; +; -9.969 ns ; 1.000 ns ; 10.969 ns ; FB_SIZE1 ; FB_AD[31] ; +; -9.951 ns ; 1.000 ns ; 10.951 ns ; FB_SIZE0 ; FB_AD[22] ; +; -9.938 ns ; 1.000 ns ; 10.938 ns ; nFB_CS2 ; FB_AD[26] ; +; -9.918 ns ; 1.000 ns ; 10.918 ns ; nFB_CS1 ; FB_AD[31] ; +; -9.914 ns ; 1.000 ns ; 10.914 ns ; nFB_CS2 ; FB_AD[17] ; +; -9.903 ns ; 1.000 ns ; 10.903 ns ; FB_SIZE0 ; FB_AD[25] ; +; -9.899 ns ; 1.000 ns ; 10.899 ns ; IDE_INT ; FB_AD[21] ; +; -9.876 ns ; 1.000 ns ; 10.876 ns ; nFB_CS2 ; FB_AD[31] ; +; -9.864 ns ; 1.000 ns ; 10.864 ns ; FB_SIZE1 ; FB_AD[30] ; +; -9.835 ns ; 1.000 ns ; 10.835 ns ; LP_D[3] ; FB_AD[27] ; +; -9.823 ns ; 1.000 ns ; 10.823 ns ; nFB_WR ; FB_AD[17] ; +; -9.820 ns ; 1.000 ns ; 10.820 ns ; nFB_CS2 ; FB_AD[30] ; +; -9.813 ns ; 1.000 ns ; 10.813 ns ; MAIN_CLK ; FB_AD[20] ; +; -9.802 ns ; 1.000 ns ; 10.802 ns ; nFB_CS2 ; FB_AD[25] ; +; -9.801 ns ; 1.000 ns ; 10.801 ns ; FB_SIZE1 ; FB_AD[25] ; +; -9.792 ns ; 1.000 ns ; 10.792 ns ; nFB_CS2 ; FB_AD[29] ; +; -9.791 ns ; 1.000 ns ; 10.791 ns ; nFB_OE ; FB_AD[25] ; +; -9.778 ns ; 1.000 ns ; 10.778 ns ; FB_SIZE1 ; FB_AD[22] ; +; -9.770 ns ; 1.000 ns ; 10.770 ns ; nFB_OE ; FB_AD[23] ; +; -9.763 ns ; 1.000 ns ; 10.763 ns ; nFB_CS1 ; FB_AD[2] ; +; -9.750 ns ; 1.000 ns ; 10.750 ns ; nFB_WR ; FB_AD[31] ; +; -9.729 ns ; 1.000 ns ; 10.729 ns ; FB_SIZE0 ; FB_AD[9] ; +; -9.729 ns ; 1.000 ns ; 10.729 ns ; nFB_CS1 ; FB_AD[30] ; +; -9.701 ns ; 1.000 ns ; 10.701 ns ; MAIN_CLK ; FB_AD[21] ; +; -9.699 ns ; 1.000 ns ; 10.699 ns ; FB_SIZE0 ; FB_AD[24] ; +; -9.692 ns ; 1.000 ns ; 10.692 ns ; nFB_OE ; FB_AD[22] ; +; -9.685 ns ; 1.000 ns ; 10.685 ns ; nFB_OE ; FB_AD[31] ; +; -9.684 ns ; 1.000 ns ; 10.684 ns ; nFB_OE ; FB_AD[19] ; +; -9.671 ns ; 1.000 ns ; 10.671 ns ; nFB_OE ; FB_AD[17] ; +; -9.634 ns ; 1.000 ns ; 10.634 ns ; nFB_CS2 ; FB_AD[24] ; +; -9.630 ns ; 1.000 ns ; 10.630 ns ; SRD[2] ; FB_AD[18] ; +; -9.629 ns ; 1.000 ns ; 10.629 ns ; nFB_WR ; FB_AD[30] ; +; -9.628 ns ; 1.000 ns ; 10.628 ns ; nFB_CS2 ; FB_AD[9] ; +; -9.627 ns ; 1.000 ns ; 10.627 ns ; FB_SIZE1 ; FB_AD[9] ; +; -9.600 ns ; 1.000 ns ; 10.600 ns ; nFB_CS1 ; FB_AD[28] ; +; -9.597 ns ; 1.000 ns ; 10.597 ns ; FB_SIZE1 ; FB_AD[24] ; +; -9.593 ns ; 1.000 ns ; 10.593 ns ; nFB_WR ; FB_AD[16] ; +; -9.574 ns ; 1.000 ns ; 10.574 ns ; FB_SIZE0 ; FB_AD[28] ; +; -9.572 ns ; 1.000 ns ; 10.572 ns ; DCD ; FB_AD[17] ; +; -9.565 ns ; 1.000 ns ; 10.565 ns ; nFB_OE ; FB_AD[24] ; +; -9.559 ns ; 1.000 ns ; 10.559 ns ; nFB_WR ; FB_AD[8] ; +; -9.554 ns ; 1.000 ns ; 10.554 ns ; nFB_CS1 ; FB_AD[8] ; +; -9.521 ns ; 1.000 ns ; 10.521 ns ; nFB_CS1 ; FB_AD[3] ; +; -9.491 ns ; 1.000 ns ; 10.491 ns ; nFB_WR ; FB_AD[28] ; +; -9.477 ns ; 1.000 ns ; 10.477 ns ; nFB_CS2 ; FB_AD[3] ; +; -9.455 ns ; 1.000 ns ; 10.455 ns ; FB_SIZE0 ; FB_AD[26] ; +; -9.418 ns ; 1.000 ns ; 10.418 ns ; RI ; FB_AD[22] ; +; -9.410 ns ; 1.000 ns ; 10.410 ns ; nFB_CS1 ; FB_AD[5] ; +; -9.398 ns ; 1.000 ns ; 10.398 ns ; MAIN_CLK ; FB_AD[26] ; +; -9.397 ns ; 1.000 ns ; 10.397 ns ; FB_SIZE1 ; FB_AD[28] ; +; -9.394 ns ; 1.000 ns ; 10.394 ns ; SRD[8] ; FB_AD[24] ; +; -9.381 ns ; 1.000 ns ; 10.381 ns ; nFB_OE ; FB_AD[26] ; +; -9.380 ns ; 1.000 ns ; 10.380 ns ; nFB_CS2 ; FB_AD[11] ; +; -9.371 ns ; 1.000 ns ; 10.371 ns ; FB_SIZE0 ; FB_AD[4] ; +; -9.370 ns ; 1.000 ns ; 10.370 ns ; nFB_WR ; FB_AD[5] ; +; -9.355 ns ; 1.000 ns ; 10.355 ns ; nFB_OE ; FB_AD[4] ; +; -9.344 ns ; 1.000 ns ; 10.344 ns ; nFB_CS2 ; FB_AD[5] ; +; -9.333 ns ; 1.000 ns ; 10.333 ns ; FB_SIZE0 ; FB_AD[16] ; +; -9.328 ns ; 1.000 ns ; 10.328 ns ; FB_SIZE0 ; FB_AD[2] ; +; -9.315 ns ; 1.000 ns ; 10.315 ns ; FB_SIZE1 ; FB_AD[4] ; +; -9.312 ns ; 1.000 ns ; 10.312 ns ; FB_SIZE0 ; FB_AD[3] ; +; -9.312 ns ; 1.000 ns ; 10.312 ns ; nFB_OE ; FB_AD[2] ; +; -9.309 ns ; 1.000 ns ; 10.309 ns ; MAIN_CLK ; FB_AD[22] ; +; -9.305 ns ; 1.000 ns ; 10.305 ns ; MAIN_CLK ; FB_AD[25] ; +; -9.296 ns ; 1.000 ns ; 10.296 ns ; nFB_OE ; FB_AD[3] ; +; -9.278 ns ; 1.000 ns ; 10.278 ns ; FB_SIZE1 ; FB_AD[26] ; +; -9.275 ns ; 1.000 ns ; 10.275 ns ; nFB_WR ; FB_AD[2] ; +; -9.273 ns ; 1.000 ns ; 10.273 ns ; nFB_CS1 ; nFB_TA ; +; -9.272 ns ; 1.000 ns ; 10.272 ns ; FB_SIZE1 ; FB_AD[2] ; +; -9.271 ns ; 1.000 ns ; 10.271 ns ; nFB_CS2 ; FB_AD[16] ; +; -9.262 ns ; 1.000 ns ; 10.262 ns ; nFB_OE ; FB_AD[28] ; +; -9.256 ns ; 1.000 ns ; 10.256 ns ; FB_SIZE1 ; FB_AD[3] ; +; -9.245 ns ; 1.000 ns ; 10.245 ns ; nFB_CS2 ; FB_AD[2] ; +; -9.231 ns ; 1.000 ns ; 10.231 ns ; CLK33M ; VB[7] ; +; -9.210 ns ; 1.000 ns ; 10.210 ns ; nFB_CS2 ; FB_AD[4] ; +; -9.203 ns ; 1.000 ns ; 10.203 ns ; nFB_OE ; FB_AD[9] ; +; -9.201 ns ; 1.000 ns ; 10.201 ns ; nFB_CS2 ; FB_AD[8] ; +; -9.199 ns ; 1.000 ns ; 10.199 ns ; MAIN_CLK ; FB_AD[31] ; +; -9.198 ns ; 1.000 ns ; 10.198 ns ; CLK33M ; VSYNC_PAD ; +; -9.193 ns ; 1.000 ns ; 10.193 ns ; CLK33M ; VR[6] ; +; -9.191 ns ; 1.000 ns ; 10.191 ns ; CLK33M ; VG[3] ; +; -9.176 ns ; 1.000 ns ; 10.176 ns ; nFB_CS1 ; FB_AD[4] ; +; -9.168 ns ; 1.000 ns ; 10.168 ns ; LP_D[7] ; FB_AD[31] ; +; -9.156 ns ; 1.000 ns ; 10.156 ns ; FB_SIZE1 ; FB_AD[16] ; +; -9.145 ns ; 1.000 ns ; 10.145 ns ; MAIN_CLK ; FB_AD[23] ; +; -9.145 ns ; 1.000 ns ; 10.145 ns ; nFB_CS2 ; FB_AD[28] ; +; -9.112 ns ; 1.000 ns ; 10.112 ns ; nFB_WR ; FB_AD[3] ; +; -9.099 ns ; 1.000 ns ; 10.099 ns ; MAIN_CLK ; FB_AD[19] ; +; -9.089 ns ; 1.000 ns ; 10.089 ns ; nFB_OE ; FB_AD[5] ; +; -9.088 ns ; 1.000 ns ; 10.088 ns ; SRD[5] ; FB_AD[21] ; +; -9.081 ns ; 1.000 ns ; 10.081 ns ; nFB_OE ; FB_AD[16] ; +; -9.079 ns ; 1.000 ns ; 10.079 ns ; MAIN_CLK ; FB_AD[24] ; +; -9.047 ns ; 1.000 ns ; 10.047 ns ; nFB_CS2 ; FB_AD[10] ; +; -9.019 ns ; 1.000 ns ; 10.019 ns ; nFB_CS2 ; FB_AD[13] ; +; -9.004 ns ; 1.000 ns ; 10.004 ns ; FB_SIZE0 ; FB_AD[8] ; +; -8.984 ns ; 1.000 ns ; 9.984 ns ; LP_D[5] ; FB_AD[29] ; +; -8.935 ns ; 1.000 ns ; 9.935 ns ; SRD[4] ; FB_AD[20] ; +; -8.933 ns ; 1.000 ns ; 9.933 ns ; nFB_OE ; FB_AD[30] ; +; -8.927 ns ; 1.000 ns ; 9.927 ns ; SRD[10] ; FB_AD[26] ; +; -8.926 ns ; 1.000 ns ; 9.926 ns ; nFB_OE ; FB_AD[8] ; +; -8.924 ns ; 1.000 ns ; 9.924 ns ; nFB_CS2 ; FB_AD[6] ; +; -8.921 ns ; 1.000 ns ; 9.921 ns ; nFB_WR ; FB_AD[4] ; +; -8.916 ns ; 1.000 ns ; 9.916 ns ; LP_D[6] ; FB_AD[30] ; +; -8.909 ns ; 1.000 ns ; 9.909 ns ; nFB_CS2 ; FB_AD[15] ; +; -8.902 ns ; 1.000 ns ; 9.902 ns ; FB_SIZE1 ; FB_AD[8] ; +; -8.896 ns ; 1.000 ns ; 9.896 ns ; FB_SIZE0 ; FB_AD[5] ; +; -8.876 ns ; 1.000 ns ; 9.876 ns ; nFB_CS2 ; FB_AD[14] ; +; -8.873 ns ; 1.000 ns ; 9.873 ns ; LP_BUSY ; FB_AD[16] ; +; -8.869 ns ; 1.000 ns ; 9.869 ns ; MAIN_CLK ; FB_AD[4] ; +; -8.864 ns ; 1.000 ns ; 9.864 ns ; nFB_OE ; FB_AD[29] ; +; -8.852 ns ; 1.000 ns ; 9.852 ns ; nFB_CS2 ; FB_AD[12] ; +; -8.840 ns ; 1.000 ns ; 9.840 ns ; FB_SIZE1 ; FB_AD[5] ; +; -8.826 ns ; 1.000 ns ; 9.826 ns ; MAIN_CLK ; FB_AD[2] ; +; -8.819 ns ; 1.000 ns ; 9.819 ns ; DCD ; FB_AD[3] ; +; -8.810 ns ; 1.000 ns ; 9.810 ns ; MAIN_CLK ; FB_AD[3] ; +; -8.804 ns ; 1.000 ns ; 9.804 ns ; nFB_OE ; FB_AD[13] ; +; -8.803 ns ; 1.000 ns ; 9.803 ns ; SRD[7] ; FB_AD[23] ; +; -8.780 ns ; 1.000 ns ; 9.780 ns ; nFB_CS2 ; FB_AD[1] ; +; -8.776 ns ; 1.000 ns ; 9.776 ns ; MAIN_CLK ; FB_AD[28] ; +; -8.715 ns ; 1.000 ns ; 9.715 ns ; FB_SIZE0 ; FB_AD[12] ; +; -8.715 ns ; 1.000 ns ; 9.715 ns ; FB_SIZE0 ; FB_AD[11] ; +; -8.699 ns ; 1.000 ns ; 9.699 ns ; FB_SIZE0 ; BA[0] ; +; -8.699 ns ; 1.000 ns ; 9.699 ns ; nFB_OE ; FB_AD[12] ; +; -8.699 ns ; 1.000 ns ; 9.699 ns ; nFB_OE ; FB_AD[11] ; +; -8.672 ns ; 1.000 ns ; 9.672 ns ; FB_SIZE0 ; FB_AD[6] ; +; -8.660 ns ; 1.000 ns ; 9.660 ns ; RI ; FB_AD[8] ; +; -8.659 ns ; 1.000 ns ; 9.659 ns ; FB_SIZE1 ; FB_AD[12] ; +; -8.659 ns ; 1.000 ns ; 9.659 ns ; FB_SIZE1 ; FB_AD[11] ; +; -8.656 ns ; 1.000 ns ; 9.656 ns ; nFB_OE ; FB_AD[6] ; +; -8.651 ns ; 1.000 ns ; 9.651 ns ; FB_SIZE0 ; FB_AD[0] ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; th ; ++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ +; -0.401 ns ; 1.000 ns ; 1.401 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; MAIN_CLK ; +; -0.386 ns ; 1.000 ns ; 1.386 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9] ; MAIN_CLK ; +; -0.383 ns ; 1.000 ns ; 1.383 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5] ; MAIN_CLK ; +; -0.383 ns ; 1.000 ns ; 1.383 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21] ; MAIN_CLK ; +; -0.370 ns ; 1.000 ns ; 1.370 ns ; CTS ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[2] ; MAIN_CLK ; +; -0.339 ns ; 1.000 ns ; 1.339 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; MAIN_CLK ; +; -0.333 ns ; 1.000 ns ; 1.333 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; MAIN_CLK ; +; -0.328 ns ; 1.000 ns ; 1.328 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9] ; MAIN_CLK ; +; -0.325 ns ; 1.000 ns ; 1.325 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; MAIN_CLK ; +; -0.325 ns ; 1.000 ns ; 1.325 ns ; RI ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[14] ; MAIN_CLK ; +; -0.321 ns ; 1.000 ns ; 1.321 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5] ; MAIN_CLK ; +; -0.320 ns ; 1.000 ns ; 1.320 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25] ; MAIN_CLK ; +; -0.310 ns ; 1.000 ns ; 1.310 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; MAIN_CLK ; +; -0.302 ns ; 1.000 ns ; 1.302 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; MAIN_CLK ; +; -0.302 ns ; 1.000 ns ; 1.302 ns ; CTS ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[2] ; MAIN_CLK ; +; -0.293 ns ; 1.000 ns ; 1.293 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; MAIN_CLK ; +; -0.285 ns ; 1.000 ns ; 1.285 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6] ; MAIN_CLK ; +; -0.283 ns ; 1.000 ns ; 1.283 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9] ; MAIN_CLK ; +; -0.275 ns ; 1.000 ns ; 1.275 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17] ; MAIN_CLK ; +; -0.272 ns ; 1.000 ns ; 1.272 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; MAIN_CLK ; +; -0.269 ns ; 1.000 ns ; 1.269 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4] ; MAIN_CLK ; +; -0.265 ns ; 1.000 ns ; 1.265 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; MAIN_CLK ; +; -0.252 ns ; 1.000 ns ; 1.252 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3] ; MAIN_CLK ; +; -0.247 ns ; 1.000 ns ; 1.247 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8] ; MAIN_CLK ; +; -0.246 ns ; 1.000 ns ; 1.246 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26] ; MAIN_CLK ; +; -0.245 ns ; 1.000 ns ; 1.245 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; MAIN_CLK ; +; -0.238 ns ; 1.000 ns ; 1.238 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16] ; MAIN_CLK ; +; -0.235 ns ; 1.000 ns ; 1.235 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3] ; MAIN_CLK ; +; -0.235 ns ; 1.000 ns ; 1.235 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8] ; MAIN_CLK ; +; -0.227 ns ; 1.000 ns ; 1.227 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; MAIN_CLK ; +; -0.226 ns ; 1.000 ns ; 1.226 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10] ; MAIN_CLK ; +; -0.224 ns ; 1.000 ns ; 1.224 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; MAIN_CLK ; +; -0.223 ns ; 1.000 ns ; 1.223 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; MAIN_CLK ; +; -0.222 ns ; 1.000 ns ; 1.222 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; MAIN_CLK ; +; -0.216 ns ; 1.000 ns ; 1.216 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10] ; MAIN_CLK ; +; -0.208 ns ; 1.000 ns ; 1.208 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8] ; MAIN_CLK ; +; -0.202 ns ; 1.000 ns ; 1.202 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22] ; MAIN_CLK ; +; -0.197 ns ; 1.000 ns ; 1.197 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9] ; MAIN_CLK ; +; -0.194 ns ; 1.000 ns ; 1.194 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; MAIN_CLK ; +; -0.191 ns ; 1.000 ns ; 1.191 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5] ; MAIN_CLK ; +; -0.189 ns ; 1.000 ns ; 1.189 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; MAIN_CLK ; +; -0.187 ns ; 1.000 ns ; 1.187 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; MAIN_CLK ; +; -0.181 ns ; 1.000 ns ; 1.181 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; MAIN_CLK ; +; -0.179 ns ; 1.000 ns ; 1.179 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3] ; MAIN_CLK ; +; -0.173 ns ; 1.000 ns ; 1.173 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; MAIN_CLK ; +; -0.172 ns ; 1.000 ns ; 1.172 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; MAIN_CLK ; +; -0.166 ns ; 1.000 ns ; 1.166 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10] ; MAIN_CLK ; +; -0.165 ns ; 1.000 ns ; 1.165 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10] ; MAIN_CLK ; +; -0.162 ns ; 1.000 ns ; 1.162 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6] ; MAIN_CLK ; +; -0.159 ns ; 1.000 ns ; 1.159 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; MAIN_CLK ; +; -0.159 ns ; 1.000 ns ; 1.159 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; MAIN_CLK ; +; -0.154 ns ; 1.000 ns ; 1.154 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19] ; MAIN_CLK ; +; -0.151 ns ; 1.000 ns ; 1.151 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9] ; MAIN_CLK ; +; -0.149 ns ; 1.000 ns ; 1.149 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; MAIN_CLK ; +; -0.146 ns ; 1.000 ns ; 1.146 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; MAIN_CLK ; +; -0.145 ns ; 1.000 ns ; 1.145 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5] ; MAIN_CLK ; +; -0.142 ns ; 1.000 ns ; 1.142 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9] ; MAIN_CLK ; +; -0.141 ns ; 1.000 ns ; 1.141 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; MAIN_CLK ; +; -0.140 ns ; 1.000 ns ; 1.140 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4] ; MAIN_CLK ; +; -0.137 ns ; 1.000 ns ; 1.137 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; MAIN_CLK ; +; -0.134 ns ; 1.000 ns ; 1.134 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7] ; MAIN_CLK ; +; -0.130 ns ; 1.000 ns ; 1.130 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22] ; MAIN_CLK ; +; -0.130 ns ; 1.000 ns ; 1.130 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; MAIN_CLK ; +; -0.125 ns ; 1.000 ns ; 1.125 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; MAIN_CLK ; +; -0.121 ns ; 1.000 ns ; 1.121 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0] ; MAIN_CLK ; +; -0.121 ns ; 1.000 ns ; 1.121 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; MAIN_CLK ; +; -0.113 ns ; 1.000 ns ; 1.113 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5] ; MAIN_CLK ; +; -0.109 ns ; 1.000 ns ; 1.109 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7] ; MAIN_CLK ; +; -0.108 ns ; 1.000 ns ; 1.108 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; MAIN_CLK ; +; -0.099 ns ; 1.000 ns ; 1.099 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10] ; MAIN_CLK ; +; -0.094 ns ; 1.000 ns ; 1.094 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19] ; MAIN_CLK ; +; -0.092 ns ; 1.000 ns ; 1.092 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9] ; MAIN_CLK ; +; -0.090 ns ; 1.000 ns ; 1.090 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10] ; MAIN_CLK ; +; -0.089 ns ; 1.000 ns ; 1.089 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23] ; MAIN_CLK ; +; -0.087 ns ; 1.000 ns ; 1.087 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3] ; MAIN_CLK ; +; -0.086 ns ; 1.000 ns ; 1.086 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5] ; MAIN_CLK ; +; -0.085 ns ; 1.000 ns ; 1.085 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; MAIN_CLK ; +; -0.081 ns ; 1.000 ns ; 1.081 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; -0.079 ns ; 1.000 ns ; 1.079 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; MAIN_CLK ; +; -0.078 ns ; 1.000 ns ; 1.078 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9] ; MAIN_CLK ; +; -0.077 ns ; 1.000 ns ; 1.077 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; MAIN_CLK ; +; -0.075 ns ; 1.000 ns ; 1.075 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; MAIN_CLK ; +; -0.074 ns ; 1.000 ns ; 1.074 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; MAIN_CLK ; +; -0.070 ns ; 1.000 ns ; 1.070 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1] ; MAIN_CLK ; +; -0.070 ns ; 1.000 ns ; 1.070 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14] ; MAIN_CLK ; +; -0.068 ns ; 1.000 ns ; 1.068 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5] ; MAIN_CLK ; +; -0.068 ns ; 1.000 ns ; 1.068 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; -0.065 ns ; 1.000 ns ; 1.065 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14] ; MAIN_CLK ; +; -0.064 ns ; 1.000 ns ; 1.064 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; MAIN_CLK ; +; -0.064 ns ; 1.000 ns ; 1.064 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10] ; MAIN_CLK ; +; -0.062 ns ; 1.000 ns ; 1.062 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27] ; MAIN_CLK ; +; -0.059 ns ; 1.000 ns ; 1.059 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; MAIN_CLK ; +; -0.057 ns ; 1.000 ns ; 1.057 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4] ; MAIN_CLK ; +; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; MAIN_CLK ; +; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6] ; MAIN_CLK ; +; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25] ; MAIN_CLK ; +; -0.053 ns ; 1.000 ns ; 1.053 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; MAIN_CLK ; +; -0.047 ns ; 1.000 ns ; 1.047 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3] ; MAIN_CLK ; +; -0.047 ns ; 1.000 ns ; 1.047 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9] ; MAIN_CLK ; +; -0.046 ns ; 1.000 ns ; 1.046 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; MAIN_CLK ; +; -0.042 ns ; 1.000 ns ; 1.042 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18] ; MAIN_CLK ; +; -0.042 ns ; 1.000 ns ; 1.042 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8] ; MAIN_CLK ; +; -0.039 ns ; 1.000 ns ; 1.039 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21] ; MAIN_CLK ; +; -0.037 ns ; 1.000 ns ; 1.037 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7] ; MAIN_CLK ; +; -0.037 ns ; 1.000 ns ; 1.037 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4] ; MAIN_CLK ; +; -0.035 ns ; 1.000 ns ; 1.035 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14] ; MAIN_CLK ; +; -0.033 ns ; 1.000 ns ; 1.033 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20] ; MAIN_CLK ; +; -0.028 ns ; 1.000 ns ; 1.028 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4] ; MAIN_CLK ; +; -0.026 ns ; 1.000 ns ; 1.026 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2] ; MAIN_CLK ; +; -0.022 ns ; 1.000 ns ; 1.022 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0] ; MAIN_CLK ; +; -0.018 ns ; 1.000 ns ; 1.018 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; MAIN_CLK ; +; -0.018 ns ; 1.000 ns ; 1.018 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12] ; MAIN_CLK ; +; -0.017 ns ; 1.000 ns ; 1.017 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; MAIN_CLK ; +; -0.017 ns ; 1.000 ns ; 1.017 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; MAIN_CLK ; +; -0.011 ns ; 1.000 ns ; 1.011 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; MAIN_CLK ; +; -0.010 ns ; 1.000 ns ; 1.010 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3] ; MAIN_CLK ; +; -0.004 ns ; 1.000 ns ; 1.004 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3] ; MAIN_CLK ; +; 0.007 ns ; 1.000 ns ; 0.993 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; MAIN_CLK ; +; 0.008 ns ; 1.000 ns ; 0.992 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25] ; MAIN_CLK ; +; 0.009 ns ; 1.000 ns ; 0.991 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10] ; MAIN_CLK ; +; 0.009 ns ; 1.000 ns ; 0.991 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10] ; MAIN_CLK ; +; 0.010 ns ; 1.000 ns ; 0.990 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25] ; MAIN_CLK ; +; 0.015 ns ; 1.000 ns ; 0.985 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; MAIN_CLK ; +; 0.018 ns ; 1.000 ns ; 0.982 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2] ; MAIN_CLK ; +; 0.021 ns ; 1.000 ns ; 0.979 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1] ; MAIN_CLK ; +; 0.022 ns ; 1.000 ns ; 0.978 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2] ; MAIN_CLK ; +; 0.027 ns ; 1.000 ns ; 0.973 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; MAIN_CLK ; +; 0.033 ns ; 1.000 ns ; 0.967 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; MAIN_CLK ; +; 0.036 ns ; 1.000 ns ; 0.964 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6] ; MAIN_CLK ; +; 0.042 ns ; 1.000 ns ; 0.958 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8] ; MAIN_CLK ; +; 0.044 ns ; 1.000 ns ; 0.956 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0] ; MAIN_CLK ; +; 0.045 ns ; 1.000 ns ; 0.955 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22] ; MAIN_CLK ; +; 0.045 ns ; 1.000 ns ; 0.955 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; MAIN_CLK ; +; 0.046 ns ; 1.000 ns ; 0.954 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14] ; MAIN_CLK ; +; 0.047 ns ; 1.000 ns ; 0.953 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; MAIN_CLK ; +; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5] ; MAIN_CLK ; +; 0.050 ns ; 1.000 ns ; 0.950 ns ; VD[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14] ; MAIN_CLK ; +; 0.050 ns ; 1.000 ns ; 0.950 ns ; RI ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[14] ; MAIN_CLK ; +; 0.054 ns ; 1.000 ns ; 0.946 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3] ; MAIN_CLK ; +; 0.054 ns ; 1.000 ns ; 0.946 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2] ; MAIN_CLK ; +; 0.055 ns ; 1.000 ns ; 0.945 ns ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29] ; MAIN_CLK ; +; 0.055 ns ; 1.000 ns ; 0.945 ns ; VD[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4] ; MAIN_CLK ; +; 0.057 ns ; 1.000 ns ; 0.943 ns ; VD[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; MAIN_CLK ; +; 0.064 ns ; 1.000 ns ; 0.936 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20] ; MAIN_CLK ; +; 0.078 ns ; 1.000 ns ; 0.922 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2] ; MAIN_CLK ; +; 0.079 ns ; 1.000 ns ; 0.921 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; MAIN_CLK ; +; 0.079 ns ; 1.000 ns ; 0.921 ns ; VD[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; MAIN_CLK ; +; 0.079 ns ; 1.000 ns ; 0.921 ns ; VD[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8] ; MAIN_CLK ; +; 0.081 ns ; 1.000 ns ; 0.919 ns ; VD[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7] ; MAIN_CLK ; +; 0.082 ns ; 1.000 ns ; 0.918 ns ; VD[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; MAIN_CLK ; +; 0.091 ns ; 1.000 ns ; 0.909 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; MAIN_CLK ; +; 0.098 ns ; 1.000 ns ; 0.902 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3] ; MAIN_CLK ; +; 0.106 ns ; 1.000 ns ; 0.894 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9] ; MAIN_CLK ; +; 0.107 ns ; 1.000 ns ; 0.893 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; MAIN_CLK ; +; 0.109 ns ; 1.000 ns ; 0.891 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0] ; MAIN_CLK ; +; 0.110 ns ; 1.000 ns ; 0.890 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; MAIN_CLK ; +; 0.114 ns ; 1.000 ns ; 0.886 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.119 ns ; 1.000 ns ; 0.881 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21] ; MAIN_CLK ; +; 0.125 ns ; 1.000 ns ; 0.875 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; MAIN_CLK ; +; 0.125 ns ; 1.000 ns ; 0.875 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5] ; MAIN_CLK ; +; 0.128 ns ; 1.000 ns ; 0.872 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2] ; MAIN_CLK ; +; 0.131 ns ; 1.000 ns ; 0.869 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21] ; MAIN_CLK ; +; 0.131 ns ; 1.000 ns ; 0.869 ns ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29] ; MAIN_CLK ; +; 0.132 ns ; 1.000 ns ; 0.868 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.133 ns ; 1.000 ns ; 0.867 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8] ; MAIN_CLK ; +; 0.136 ns ; 1.000 ns ; 0.864 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0] ; MAIN_CLK ; +; 0.148 ns ; 1.000 ns ; 0.852 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9] ; MAIN_CLK ; +; 0.149 ns ; 1.000 ns ; 0.851 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6] ; MAIN_CLK ; +; 0.151 ns ; 1.000 ns ; 0.849 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0] ; MAIN_CLK ; +; 0.151 ns ; 1.000 ns ; 0.849 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; MAIN_CLK ; +; 0.158 ns ; 1.000 ns ; 0.842 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; MAIN_CLK ; +; 0.159 ns ; 1.000 ns ; 0.841 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7] ; MAIN_CLK ; +; 0.159 ns ; 1.000 ns ; 0.841 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22] ; MAIN_CLK ; +; 0.161 ns ; 1.000 ns ; 0.839 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; MAIN_CLK ; +; 0.163 ns ; 1.000 ns ; 0.837 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0] ; MAIN_CLK ; +; 0.168 ns ; 1.000 ns ; 0.832 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; MAIN_CLK ; +; 0.170 ns ; 1.000 ns ; 0.830 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.170 ns ; 1.000 ns ; 0.830 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6] ; MAIN_CLK ; +; 0.172 ns ; 1.000 ns ; 0.828 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; MAIN_CLK ; +; 0.178 ns ; 1.000 ns ; 0.822 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10] ; MAIN_CLK ; +; 0.180 ns ; 1.000 ns ; 0.820 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10] ; MAIN_CLK ; +; 0.181 ns ; 1.000 ns ; 0.819 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1] ; MAIN_CLK ; +; 0.186 ns ; 1.000 ns ; 0.814 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; MAIN_CLK ; +; 0.188 ns ; 1.000 ns ; 0.812 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; MAIN_CLK ; +; 0.191 ns ; 1.000 ns ; 0.809 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26] ; MAIN_CLK ; +; 0.195 ns ; 1.000 ns ; 0.805 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; +; 0.198 ns ; 1.000 ns ; 0.802 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; MAIN_CLK ; +; 0.201 ns ; 1.000 ns ; 0.799 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8] ; MAIN_CLK ; +; 0.202 ns ; 1.000 ns ; 0.798 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; MAIN_CLK ; +; 0.209 ns ; 1.000 ns ; 0.791 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4] ; MAIN_CLK ; +; 0.213 ns ; 1.000 ns ; 0.787 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0] ; MAIN_CLK ; +; 0.216 ns ; 1.000 ns ; 0.784 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; MAIN_CLK ; +; 0.220 ns ; 1.000 ns ; 0.780 ns ; VD[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; MAIN_CLK ; +; 0.221 ns ; 1.000 ns ; 0.779 ns ; VD[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; MAIN_CLK ; +; 0.228 ns ; 1.000 ns ; 0.772 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0] ; MAIN_CLK ; +; 0.228 ns ; 1.000 ns ; 0.772 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; MAIN_CLK ; +; 0.233 ns ; 1.000 ns ; 0.767 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3] ; MAIN_CLK ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Board Trace Model Assignments ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ +; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ +; CLK24M576 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_STR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; CLK25M ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nACSI_ACK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nACSI_RESET ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nACSI_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_A1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_ACK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_ATN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; MIDI_OLR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; MIDI_TLR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; TxD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; RTS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; DTR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; AMKB_TX ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IDE_RES ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_CS0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_CS1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_WR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIDE_RD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nCF_CS0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nCF_CS1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nROM3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nROM4 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nRP_UDS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nRP_LDS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSDSEL ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nWR_GATE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nWR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; YM_QA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; YM_QB ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; YM_QC ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SD_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; DSA_D ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVWE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVCAS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVRAS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nVCS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nPD_VGA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; TIN0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRCS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRBLE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRBHE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSRWE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nDREQ1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LED_FPGA_OK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSROE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VCKE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nFB_TA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nDDR_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; DDR_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VSYNC_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; HSYNC_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nBLANK_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSYNC ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nMOT_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSTEP_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSTEP ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; CLKUSB ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LPDIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; BA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; BA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[4] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[3] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nIRQ[2] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VB[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDM[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VG[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VR[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; FB_AD[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VD[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; VDQS[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; IO[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SRD[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_PAR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_SEL ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; nSCSI_RST ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ACSI_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; LP_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; SCSI_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; +; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; ++---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ + + ++----------------------------------------------------------------------------+ +; Input Transition Times ; ++-------------------------+--------------+-----------------+-----------------+ +; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; ++-------------------------+--------------+-----------------+-----------------+ +; nFB_BURST ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nACSI_DRQ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nACSI_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_DRQ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_MSG ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nDCHG ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_DATA0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_DATA1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_DATA2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_CARD_DEDECT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_WP ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nDACK0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; WP_CF_CARD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_C_D ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_I_O ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_CS3 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; TOUT0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nMASTER ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_AD[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; VD[31] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[30] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[29] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[28] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[27] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[26] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[25] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[24] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[23] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[22] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[21] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[20] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[19] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[18] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[17] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[16] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[15] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[14] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[13] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[12] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[11] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[10] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[9] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[8] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[7] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[6] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[5] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[4] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VD[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[3] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[2] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[1] ; 2.5 V ; 2000 ps ; 2000 ps ; +; VDQS[0] ; 2.5 V ; 2000 ps ; 2000 ps ; +; IO[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IO[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SRD[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_PAR ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_SEL ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nSCSI_RST ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ACSI_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; SCSI_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nRSTO_MCF ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_WR ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_CS1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_SIZE1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_SIZE0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; FB_ALE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_CS2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; MAIN_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nDACK1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nFB_OE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IDE_RDY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CLK33M ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; HD_DD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nINDEX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; RxD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nWP ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; LP_BUSY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DCD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; CTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; TRACK00 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; IDE_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; RI ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTC ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTB ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nPCI_INTA ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; DVI_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; E0_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PIC_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; PIC_AMKB_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; MIDI_IN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; nRD_DATA ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; AMKB_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +; ~ALTERA_DEV_OE~ ; 2.5 V ; 2000 ps ; 2000 ps ; +; ~ALTERA_DEV_CLRn~ ; 2.5 V ; 2000 ps ; 2000 ps ; ++-------------------------+--------------+-----------------+-----------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; CLK24M576 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_STR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; CLK25M ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; +; nACSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nACSI_RESET ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nACSI_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_A1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_ATN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; MIDI_OLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; MIDI_TLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; TxD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; RTS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; DTR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; AMKB_TX ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.36e-006 V ; 3.09 V ; -0.013 V ; 0.103 V ; 0.224 V ; 1.59e-009 s ; 1.71e-009 s ; Yes ; Yes ; 3.08 V ; 3.36e-006 V ; 3.09 V ; -0.013 V ; 0.103 V ; 0.224 V ; 1.59e-009 s ; 1.71e-009 s ; Yes ; Yes ; +; IDE_RES ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; nIDE_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIDE_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIDE_WR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIDE_RD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nCF_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nCF_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nROM3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nROM4 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nRP_UDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nRP_LDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; +; nSDSEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nWR_GATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; nWR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; YM_QA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; YM_QB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; YM_QC ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; DSA_D ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nVWE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nVCAS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nVRAS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nVCS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; nPD_VGA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; TIN0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; nSRCS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSRBLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSRBHE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSRWE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nDREQ1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LED_FPGA_OK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-006 V ; 2.34 V ; -0.00258 V ; 0.168 V ; 0.069 V ; 1.53e-009 s ; 1.92e-009 s ; No ; Yes ; 2.32 V ; 1.97e-006 V ; 2.34 V ; -0.00258 V ; 0.168 V ; 0.069 V ; 1.53e-009 s ; 1.92e-009 s ; No ; Yes ; +; nSROE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; VCKE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; nFB_TA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nDDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; DDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; HSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; nBLANK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; nSYNC ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 6.97e-007 V ; 2.86 V ; -0.0234 V ; 0.145 V ; 0.061 V ; 4.67e-010 s ; 4.98e-010 s ; Yes ; Yes ; 2.8 V ; 6.97e-007 V ; 2.86 V ; -0.0234 V ; 0.145 V ; 0.061 V ; 4.67e-010 s ; 4.98e-010 s ; Yes ; Yes ; +; nMOT_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSTEP_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; nSTEP ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; CLKUSB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; LPDIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; +; nIRQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIRQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nIRQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; nIRQ[4] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; +; nIRQ[3] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; +; nIRQ[2] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; +; VA[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VA[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VA[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VA[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VA[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; VB[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; VB[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VB[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VDM[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; VDM[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VDM[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VDM[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VG[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; VG[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VG[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; +; VR[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; VR[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; +; FB_AD[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; FB_AD[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; FB_AD[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; FB_AD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; FB_AD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; VD[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VD[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; +; VD[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VD[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; +; VD[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; +; VD[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; +; VD[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VD[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VDQS[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VDQS[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; +; VDQS[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; VDQS[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; +; IO[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; IO[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; IO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; IO[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; SRD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SRD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; SCSI_PAR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_SEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; nSCSI_RST ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; ACSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; ACSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ACSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; +; ACSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; LP_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; +; LP_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; LP_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; +; SCSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; SCSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; +; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 1.43e-006 V ; 2.84 V ; -0.0141 V ; 0.183 V ; 0.066 V ; 8.84e-010 s ; 1.02e-009 s ; No ; Yes ; 2.8 V ; 1.43e-006 V ; 2.84 V ; -0.0141 V ; 0.183 V ; 0.066 V ; 8.84e-010 s ; 1.02e-009 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Corner Signal Integrity Metrics ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +; CLK24M576 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_STR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; CLK25M ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; +; nACSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nACSI_RESET ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nACSI_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_A1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_ATN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; MIDI_OLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; MIDI_TLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; TxD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; RTS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; DTR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; AMKB_TX ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 2.1e-007 V ; 3.5 V ; -0.042 V ; 0.297 V ; 0.24 V ; 1.12e-009 s ; 1.29e-009 s ; No ; No ; 3.46 V ; 2.1e-007 V ; 3.5 V ; -0.042 V ; 0.297 V ; 0.24 V ; 1.12e-009 s ; 1.29e-009 s ; No ; No ; +; IDE_RES ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; nIDE_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIDE_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIDE_WR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIDE_RD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nCF_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nCF_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nROM3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nROM4 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nRP_UDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nRP_LDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; +; nSDSEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nWR_GATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; nWR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; YM_QA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; YM_QB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; YM_QC ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; DSA_D ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nVWE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nVCAS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nVRAS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nVCS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; nPD_VGA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; TIN0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; nSRCS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSRBLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSRBHE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSRWE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nDREQ1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LED_FPGA_OK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 7.2e-008 V ; 2.68 V ; -0.0147 V ; 0.295 V ; 0.167 V ; 9.36e-010 s ; 1.3e-009 s ; No ; Yes ; 2.62 V ; 7.2e-008 V ; 2.68 V ; -0.0147 V ; 0.295 V ; 0.167 V ; 9.36e-010 s ; 1.3e-009 s ; No ; Yes ; +; nSROE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; VCKE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; nFB_TA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nDDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; DDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; HSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; nBLANK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; nSYNC ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 3.66e-008 V ; 3.29 V ; -0.0256 V ; 0.236 V ; 0.049 V ; 2.86e-010 s ; 3.59e-010 s ; Yes ; Yes ; 3.15 V ; 3.66e-008 V ; 3.29 V ; -0.0256 V ; 0.236 V ; 0.049 V ; 2.86e-010 s ; 3.59e-010 s ; Yes ; Yes ; +; nMOT_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSTEP_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; nSTEP ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; CLKUSB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; LPDIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; +; nIRQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIRQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nIRQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; nIRQ[4] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; +; nIRQ[3] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; +; nIRQ[2] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; +; VA[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VA[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VA[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VA[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VA[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; VB[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; VB[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VB[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VDM[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; VDM[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VDM[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VDM[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VG[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; VG[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VG[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; +; VR[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; VR[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; +; FB_AD[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; FB_AD[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; FB_AD[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; FB_AD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; FB_AD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; VD[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VD[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; +; VD[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VD[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; +; VD[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; +; VD[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; +; VD[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VD[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VDQS[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VDQS[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; +; VDQS[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; VDQS[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; +; IO[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; IO[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; IO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; IO[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; SRD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SRD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; SCSI_PAR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_SEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_BUSY ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; nSCSI_RST ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SD_CMD_D1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; ACSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; ACSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ACSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; +; ACSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; LP_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; +; LP_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; LP_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; +; SCSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; SCSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; +; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 7.44e-008 V ; 3.24 V ; -0.0384 V ; 0.38 V ; 0.235 V ; 5.22e-010 s ; 7e-010 s ; No ; Yes ; 3.15 V ; 7.44e-008 V ; 3.24 V ; -0.0384 V ; 0.38 V ; 0.235 V ; 5.22e-010 s ; 7e-010 s ; No ; Yes ; ++---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Ignored Timing Assignments ; ++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ +; Option ; Setting ; From ; To ; Entity Name ; Help ; ++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ +; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a ; dcfifo_8fi1 ; Node named delayed_wrptr_g removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK ; ; Node named DDRCLK removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[0] ; ; Node named DDRCLK[0] removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[1] ; ; Node named DDRCLK[1] removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[2] ; ; Node named DDRCLK[2] removed during synthesis ; +; Clock Settings ; fast ; ; DDRCLK[3] ; ; Node named DDRCLK[3] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK ; ; Node named Video:Fredi_Aschwanden|DDRCLK removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[0] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[0] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[1] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[1] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[2] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[2] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[3] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[3] removed during synthesis ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] was found in the netlist ; +; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] was found in the netlist ; +; Maximum Delay ; 5 ns ; VD ; FB_AD ; ; No timing path applicable to specified source and destination ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[16] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[22] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[17] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[18] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[18] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[24] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[15] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[25] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[19] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[23] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[5] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; BA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[3] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[10] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[2] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[14] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[26] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[12] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[21] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[11] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[7] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[9] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; nVRAS ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[20] ; VA[6] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; BA[1] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[4] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[8] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[0] ; ; Assignment is illegal for node and/or path ; +; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[2] ; ; Assignment is illegal for node and/or path ; ++-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Wed Dec 15 02:25:14 2010 +Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only +Warning: Timing Analysis is analyzing one or more combinational loops as latches + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]" is a latch + Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]" is a latch +Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled +Warning: Clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" frequency requirement of 47.96 MHz overrides "Cyclone III" PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 48.0 MHz +Warning: Clock Setting "fast" is unassigned +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" input frequency requirement of 0.5 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" input frequency requirement of 2.46 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" input frequency requirement of 24.57 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" input frequency requirement of 2.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" input frequency requirement of 15.99 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" input frequency requirement of 24.98 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" input frequency requirement of 47.96 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" input frequency requirement of 66.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 95.92 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported +Warning: Found 38 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[3]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[1]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[4]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[2]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[5]" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[3]~23" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[1]~25" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[4]~22" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[2]~24" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[0]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[6]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[9]" as buffer + Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[8]" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[5]~21" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[0]~26" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[6]~20" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[9]~18" as buffer + Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[8]~19" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~31" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~30" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~2" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]" as buffer + Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~29" as buffer + Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1" as buffer +Info: Found timing assignments -- calculating delays +Info: Slack time is 1.997 us for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]" + Info: Fmax is 362.45 MHz (period= 2.759 ns) + Info: + Largest register to register requirement is 1999.813 ns + Info: + Setup relationship between source and destination is 1999.998 ns + Info: + Latch edge is 1990.420 ns + Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is -9.578 ns + Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.001 ns + Info: + Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.532 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.084 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.998 ns ( 84.88 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 2.574 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]' + Info: 2: + IC(0.325 ns) + CELL(0.446 ns) = 0.771 ns; Loc. = LCCOMB_X65_Y16_N14; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita0~COUT' + Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.829 ns; Loc. = LCCOMB_X65_Y16_N16; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita1~COUT' + Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.887 ns; Loc. = LCCOMB_X65_Y16_N18; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita2~COUT' + Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 0.945 ns; Loc. = LCCOMB_X65_Y16_N20; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita3~COUT' + Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 1.003 ns; Loc. = LCCOMB_X65_Y16_N22; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita4~COUT' + Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 1.061 ns; Loc. = LCCOMB_X65_Y16_N24; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita5~COUT' + Info: 8: + IC(0.000 ns) + CELL(0.058 ns) = 1.119 ns; Loc. = LCCOMB_X65_Y16_N26; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita6~COUT' + Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 1.177 ns; Loc. = LCCOMB_X65_Y16_N28; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita7~COUT' + Info: 10: + IC(0.000 ns) + CELL(0.058 ns) = 1.235 ns; Loc. = LCCOMB_X65_Y16_N30; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita8~COUT' + Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 1.293 ns; Loc. = LCCOMB_X65_Y15_N0; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita9~COUT' + Info: 12: + IC(0.000 ns) + CELL(0.058 ns) = 1.351 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10~COUT' + Info: 13: + IC(0.000 ns) + CELL(0.058 ns) = 1.409 ns; Loc. = LCCOMB_X65_Y15_N4; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita11~COUT' + Info: 14: + IC(0.000 ns) + CELL(0.058 ns) = 1.467 ns; Loc. = LCCOMB_X65_Y15_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita12~COUT' + Info: 15: + IC(0.000 ns) + CELL(0.058 ns) = 1.525 ns; Loc. = LCCOMB_X65_Y15_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita13~COUT' + Info: 16: + IC(0.000 ns) + CELL(0.058 ns) = 1.583 ns; Loc. = LCCOMB_X65_Y15_N10; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita14~COUT' + Info: 17: + IC(0.000 ns) + CELL(0.058 ns) = 1.641 ns; Loc. = LCCOMB_X65_Y15_N12; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita15~COUT' + Info: 18: + IC(0.000 ns) + CELL(0.058 ns) = 1.699 ns; Loc. = LCCOMB_X65_Y15_N14; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita16~COUT' + Info: 19: + IC(0.000 ns) + CELL(0.455 ns) = 2.154 ns; Loc. = LCCOMB_X65_Y15_N16; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita17' + Info: 20: + IC(0.199 ns) + CELL(0.130 ns) = 2.483 ns; Loc. = LCCOMB_X65_Y15_N26; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]~feeder' + Info: 21: + IC(0.000 ns) + CELL(0.091 ns) = 2.574 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]' + Info: Total cell delay = 2.050 ns ( 79.64 % ) + Info: Total interconnect delay = 0.524 ns ( 20.36 % ) +Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" +Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" +Info: Slack time is 498.663 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]" + Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits + Info: + Largest register to register requirement is 500.232 ns + Info: + Setup relationship between source and destination is 500.416 ns + Info: + Latch edge is 498.552 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.000 ns + Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 1.569 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: 2: + IC(0.344 ns) + CELL(0.376 ns) = 0.720 ns; Loc. = LCCOMB_X1_Y10_N14; Fanout = 5; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13' + Info: 3: + IC(0.240 ns) + CELL(0.609 ns) = 1.569 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]' + Info: Total cell delay = 0.985 ns ( 62.78 % ) + Info: Total interconnect delay = 0.584 ns ( 37.22 % ) +Info: Slack time is 28.59 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK" + Info: Fmax is 186.15 MHz (period= 5.372 ns) + Info: + Largest register to register requirement is 31.135 ns + Info: + Setup relationship between source and destination is 31.276 ns + Info: + Latch edge is 60.688 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 29.412 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with inverted offset of 29.412 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.020 ns + Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.508 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.065 ns) + CELL(0.534 ns) = 3.508 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK' + Info: Total cell delay = 0.534 ns ( 15.22 % ) + Info: Total interconnect delay = 2.974 ns ( 84.78 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.488 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.131 ns) + CELL(0.448 ns) = 3.488 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In' + Info: Total cell delay = 0.448 ns ( 12.84 % ) + Info: Total interconnect delay = 3.040 ns ( 87.16 % ) + Info: - Micro clock to output delay of source is 0.176 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 2.545 ns + Info: 1: + IC(0.000 ns) + CELL(0.418 ns) = 0.418 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In' + Info: 2: + IC(1.655 ns) + CELL(0.381 ns) = 2.454 ns; Loc. = LCCOMB_X30_Y32_N2; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK~0' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 2.545 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK' + Info: Total cell delay = 0.890 ns ( 34.97 % ) + Info: Total interconnect delay = 1.655 ns ( 65.03 % ) +Info: Slack time is -4.615 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" + Info: + Largest memory to register requirement is -0.928 ns + Info: + Setup relationship between source and destination is 0.145 ns + Info: + Latch edge is 0.221 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.076 ns + Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.862 ns + Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 7.507 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 7.507 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 1.084 ns ( 14.44 % ) + Info: Total interconnect delay = 6.423 ns ( 85.56 % ) + Info: - Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source memory is 8.369 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.112 ns) + CELL(0.816 ns) = 8.369 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: Total cell delay = 1.525 ns ( 18.22 % ) + Info: Total interconnect delay = 6.844 ns ( 81.78 % ) + Info: - Micro clock to output delay of source is 0.226 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest memory to register delay is 3.687 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' + Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' + Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.700 ns ( 73.23 % ) + Info: Total interconnect delay = 0.987 ns ( 26.77 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' along 3741 path(s). See Report window for details. +Info: No valid register-to-register data paths exist for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" +Info: Slack time is -2.673 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC" + Info: + Largest pin to register requirement is 0.814 ns + Info: + Setup relationship between source and destination is 1.262 ns + Info: + Latch edge is 3.955 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 2.693 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 3.537 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.537 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.102 ns) + CELL(0.534 ns) = 3.537 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC' + Info: Total cell delay = 0.534 ns ( 15.10 % ) + Info: Total interconnect delay = 3.003 ns ( 84.90 % ) + Info: - Micro setup delay of destination is -0.015 ns + Info: - Max Input delay of pin is 4.0 ns + Info: - Longest pin to register delay is 3.487 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(1.144 ns) + CELL(0.130 ns) = 2.215 ns; Loc. = LCCOMB_X22_Y6_N18; Fanout = 18; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5' + Info: 4: + IC(0.241 ns) + CELL(0.130 ns) = 2.586 ns; Loc. = LCCOMB_X22_Y6_N24; Fanout = 19; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~0' + Info: 5: + IC(0.680 ns) + CELL(0.130 ns) = 3.396 ns; Loc. = LCCOMB_X25_Y6_N20; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC~1' + Info: 6: + IC(0.000 ns) + CELL(0.091 ns) = 3.487 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC' + Info: Total cell delay = 1.422 ns ( 40.78 % ) + Info: Total interconnect delay = 2.065 ns ( 59.22 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' along 86 path(s). See Report window for details. +Info: Slack time is 2.965 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" + Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits + Info: + Largest register to register requirement is 3.604 ns + Info: + Setup relationship between source and destination is 3.788 ns + Info: + Latch edge is 6.481 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 2.693 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 0.000 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 0.639 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]' + Info: 2: + IC(0.297 ns) + CELL(0.342 ns) = 0.639 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]' + Info: Total cell delay = 0.342 ns ( 53.52 % ) + Info: Total interconnect delay = 0.297 ns ( 46.48 % ) +Info: Slack time is 5.299 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]" + Info: + Largest register to register requirement is 6.118 ns + Info: + Setup relationship between source and destination is 6.313 ns + Info: + Latch edge is 10.268 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 3.955 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.011 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.532 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.097 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.998 ns ( 84.88 % ) + Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]' + Info: Total cell delay = 0.534 ns ( 15.07 % ) + Info: Total interconnect delay = 3.009 ns ( 84.93 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest register to register delay is 0.819 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]' + Info: 2: + IC(0.598 ns) + CELL(0.130 ns) = 0.728 ns; Loc. = LCCOMB_X28_Y12_N28; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.819 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]' + Info: Total cell delay = 0.221 ns ( 26.98 % ) + Info: Total interconnect delay = 0.598 ns ( 73.02 % ) +Info: Slack time is 1.672 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI" + Info: + Largest register to register requirement is 5.308 ns + Info: + Setup relationship between source and destination is 5.999 ns + Info: + Latch edge is 8.690 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 2.691 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.064 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.487 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl' + Info: 3: + IC(1.098 ns) + CELL(0.488 ns) = 3.487 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI' + Info: Total cell delay = 0.488 ns ( 13.99 % ) + Info: Total interconnect delay = 2.999 ns ( 86.01 % ) + Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.551 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.116 ns) + CELL(0.534 ns) = 3.551 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]' + Info: Total cell delay = 0.534 ns ( 15.04 % ) + Info: Total interconnect delay = 3.017 ns ( 84.96 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: - Micro setup delay of destination is 0.428 ns + Info: - Longest register to register delay is 3.636 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]' + Info: 2: + IC(0.330 ns) + CELL(0.367 ns) = 0.697 ns; Loc. = LCCOMB_X22_Y2_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[34]~59' + Info: 3: + IC(2.591 ns) + CELL(0.348 ns) = 3.636 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI' + Info: Total cell delay = 0.715 ns ( 19.66 % ) + Info: Total interconnect delay = 2.921 ns ( 80.34 % ) +Info: Slack time is -1.712 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ" + Info: + Largest pin to register requirement is 1.118 ns + Info: + Setup relationship between source and destination is 1.576 ns + Info: + Latch edge is 2.691 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 1.115 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 3.527 ns + Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.527 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.092 ns) + CELL(0.534 ns) = 3.527 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ' + Info: Total cell delay = 0.534 ns ( 15.14 % ) + Info: Total interconnect delay = 2.993 ns ( 84.86 % ) + Info: - Micro setup delay of destination is -0.015 ns + Info: - Max Input delay of pin is 4.0 ns + Info: - Longest pin to register delay is 2.830 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(1.138 ns) + CELL(0.130 ns) = 2.209 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 7; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL' + Info: 4: + IC(0.400 ns) + CELL(0.130 ns) = 2.739 ns; Loc. = LCCOMB_X21_Y6_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~2' + Info: 5: + IC(0.000 ns) + CELL(0.091 ns) = 2.830 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ' + Info: Total cell delay = 1.292 ns ( 45.65 % ) + Info: Total interconnect delay = 1.538 ns ( 54.35 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' along 29 path(s). See Report window for details. +Info: Slack time is -4.294 ns for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" + Info: + Largest memory to register requirement is -0.607 ns + Info: + Setup relationship between source and destination is 0.272 ns + Info: + Latch edge is 0.493 ns + Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.221 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -0.668 ns + Info: + Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.082 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 8.082 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 1.243 ns ( 15.38 % ) + Info: Total interconnect delay = 6.839 ns ( 84.62 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' + Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: Total cell delay = 1.680 ns ( 19.20 % ) + Info: Total interconnect delay = 7.070 ns ( 80.80 % ) + Info: - Micro clock to output delay of source is 0.226 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest memory to register delay is 3.687 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' + Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' + Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.700 ns ( 73.23 % ) + Info: Total interconnect delay = 0.987 ns ( 26.77 % ) +Warning: Can't achieve timing requirement Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' along 3741 path(s). See Report window for details. +Info: Slack time is -5.966 ns for clock "CLK33M" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" + Info: + Largest memory to register requirement is -2.279 ns + Info: + Setup relationship between source and destination is 0.196 ns + Info: + Latch edge is 0.278 ns + Info: Clock period of Destination clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 0.082 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is -2.264 ns + Info: + Shortest clock path from clock "CLK33M" to destination register is 6.486 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' + Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 6.486 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.006 ns ( 30.93 % ) + Info: Total interconnect delay = 4.480 ns ( 69.07 % ) + Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' + Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: Total cell delay = 1.680 ns ( 19.20 % ) + Info: Total interconnect delay = 7.070 ns ( 80.80 % ) + Info: - Micro clock to output delay of source is 0.226 ns + Info: - Micro setup delay of destination is -0.015 ns + Info: - Longest memory to register delay is 3.687 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' + Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' + Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' + Info: Total cell delay = 2.700 ns ( 73.23 % ) + Info: Total interconnect delay = 0.987 ns ( 26.77 % ) +Warning: Can't achieve timing requirement Clock Setup: 'CLK33M' along 3741 path(s). See Report window for details. +Info: Slack time is -4.261 ns for clock "MAIN_CLK" between source pin "FB_ALE" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7" + Info: + Largest pin to register requirement is 0.057 ns + Info: + Setup relationship between source and destination is 1.094 ns + Info: + Latch edge is 7.575 ns + Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: - Launch edge is 6.481 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: + Largest clock skew is 2.948 ns + Info: + Shortest clock path from clock "MAIN_CLK" to destination register is 2.948 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.433 ns) + CELL(0.534 ns) = 2.948 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7' + Info: Total cell delay = 1.515 ns ( 51.39 % ) + Info: Total interconnect delay = 1.433 ns ( 48.61 % ) + Info: - Micro setup delay of destination is -0.015 ns + Info: - Max Input delay of pin is 4.0 ns + Info: - Longest pin to register delay is 4.318 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(1.524 ns) + CELL(0.130 ns) = 2.595 ns; Loc. = LCCOMB_X23_Y7_N20; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2' + Info: 4: + IC(0.212 ns) + CELL(0.130 ns) = 2.937 ns; Loc. = LCCOMB_X23_Y7_N18; Fanout = 52; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1' + Info: 5: + IC(0.445 ns) + CELL(0.130 ns) = 3.512 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 4; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~2' + Info: 6: + IC(0.235 ns) + CELL(0.130 ns) = 3.877 ns; Loc. = LCCOMB_X22_Y7_N28; Fanout = 3; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~4' + Info: 7: + IC(0.220 ns) + CELL(0.130 ns) = 4.227 ns; Loc. = LCCOMB_X22_Y7_N16; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7~0' + Info: 8: + IC(0.000 ns) + CELL(0.091 ns) = 4.318 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7' + Info: Total cell delay = 1.682 ns ( 38.95 % ) + Info: Total interconnect delay = 2.636 ns ( 61.05 % ) +Warning: Can't achieve timing requirement Clock Setup: 'MAIN_CLK' along 27347 path(s). See Report window for details. +Info: Minimum slack time is 825 ps for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" + Info: + Shortest register to register delay is 0.783 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: 2: + IC(0.323 ns) + CELL(0.369 ns) = 0.692 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.783 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: Total cell delay = 0.460 ns ( 58.75 % ) + Info: Total interconnect delay = 0.323 ns ( 41.25 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -9.578 ns + Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -9.578 ns + Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.531 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' + Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' + Info: Total cell delay = 0.534 ns ( 15.12 % ) + Info: Total interconnect delay = 2.997 ns ( 84.88 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 564 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" + Info: + Shortest register to register delay is 0.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: 2: + IC(0.301 ns) + CELL(0.130 ns) = 0.431 ns; Loc. = LCCOMB_X1_Y10_N10; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.221 ns ( 42.34 % ) + Info: Total interconnect delay = 0.301 ns ( 57.66 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.864 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' + Info: Total cell delay = 0.534 ns ( 15.16 % ) + Info: Total interconnect delay = 2.988 ns ( 84.84 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 502 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y28_N4; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector77~1' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.864 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.526 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: Total cell delay = 0.534 ns ( 15.14 % ) + Info: Total interconnect delay = 2.992 ns ( 84.86 % ) + Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.526 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' + Info: Total cell delay = 0.534 ns ( 15.14 % ) + Info: Total interconnect delay = 2.992 ns ( 84.86 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is -454 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is 0.914 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -1.864 ns + Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -1.864 ns + Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.956 ns + Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 8.469 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' + Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 8.469 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.398 ns ( 16.51 % ) + Info: Total interconnect delay = 7.071 ns ( 83.49 % ) + Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source register is 7.513 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' + Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 7.513 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.084 ns ( 14.43 % ) + Info: Total interconnect delay = 6.429 ns ( 85.57 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Warning: Can't achieve minimum setup and hold requirement altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] along 26 path(s). See Report window for details. +Info: Minimum slack time is 502 ps for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X45_Y15_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]~3' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -3.620 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -3.620 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.559 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: Total cell delay = 0.534 ns ( 15.00 % ) + Info: Total interconnect delay = 3.025 ns ( 85.00 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.559 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' + Info: Total cell delay = 0.534 ns ( 15.00 % ) + Info: Total interconnect delay = 3.025 ns ( 85.00 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 4.336 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" + Info: + Shortest register to register delay is 0.507 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]' + Info: 2: + IC(0.286 ns) + CELL(0.130 ns) = 0.416 ns; Loc. = LCCOMB_X66_Y14_N30; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.507 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]' + Info: Total cell delay = 0.221 ns ( 43.59 % ) + Info: Total interconnect delay = 0.286 ns ( 56.41 % ) + Info: - Smallest register to register requirement is -3.829 ns + Info: + Hold relationship between source and destination is -3.787 ns + Info: + Latch edge is -1.094 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 2.693 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.538 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]' + Info: Total cell delay = 0.534 ns ( 15.09 % ) + Info: Total interconnect delay = 3.004 ns ( 84.91 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.538 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' + Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]' + Info: Total cell delay = 0.534 ns ( 15.09 % ) + Info: Total interconnect delay = 3.004 ns ( 84.91 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 1.825 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]" + Info: + Shortest register to register delay is 0.508 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]' + Info: 2: + IC(0.287 ns) + CELL(0.130 ns) = 0.417 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]~feeder' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.508 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]' + Info: Total cell delay = 0.221 ns ( 43.50 % ) + Info: Total interconnect delay = 0.287 ns ( 56.50 % ) + Info: - Smallest register to register requirement is -1.317 ns + Info: + Hold relationship between source and destination is -1.262 ns + Info: + Latch edge is 2.693 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 3.955 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is -0.013 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.530 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl' + Info: 3: + IC(1.095 ns) + CELL(0.534 ns) = 3.530 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]' + Info: Total cell delay = 0.534 ns ( 15.13 % ) + Info: Total interconnect delay = 2.996 ns ( 84.87 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]' + Info: Total cell delay = 0.534 ns ( 15.07 % ) + Info: Total interconnect delay = 3.009 ns ( 84.93 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is 3.263 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO" + Info: + Shortest register to register delay is 1.570 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y2_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[29]~4' + Info: 3: + IC(0.737 ns) + CELL(0.464 ns) = 1.570 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO' + Info: Total cell delay = 0.833 ns ( 53.06 % ) + Info: Total interconnect delay = 0.737 ns ( 46.94 % ) + Info: - Smallest register to register requirement is -1.693 ns + Info: + Hold relationship between source and destination is -1.576 ns + Info: + Latch edge is 1.115 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 2.691 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is -0.019 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.543 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl' + Info: 3: + IC(1.154 ns) + CELL(0.488 ns) = 3.543 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO' + Info: Total cell delay = 0.488 ns ( 13.77 % ) + Info: Total interconnect delay = 3.055 ns ( 86.23 % ) + Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.562 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.127 ns) + CELL(0.534 ns) = 3.562 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]' + Info: Total cell delay = 0.534 ns ( 14.99 % ) + Info: Total interconnect delay = 3.028 ns ( 85.01 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.101 ns +Info: Minimum slack time is 2.664 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]" + Info: + Shortest pin to register delay is 2.216 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' + Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' + Info: 3: + IC(0.929 ns) + CELL(0.346 ns) = 2.216 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]' + Info: Total cell delay = 1.287 ns ( 58.08 % ) + Info: Total interconnect delay = 0.929 ns ( 41.92 % ) + Info: - Smallest pin to register requirement is -0.448 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -4.884 ns + Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -4.884 ns + Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 3.500 ns + Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.500 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' + Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' + Info: 3: + IC(1.151 ns) + CELL(0.448 ns) = 3.500 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]' + Info: Total cell delay = 0.448 ns ( 12.80 % ) + Info: Total interconnect delay = 3.052 ns ( 87.20 % ) + Info: + Micro hold delay of destination is 0.052 ns + Info: - Min Input delay of pin is 4.0 ns +Info: Minimum slack time is 502 ps for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is -0.042 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is -2.843 ns + Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is -2.843 ns + Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 0.000 ns + Info: + Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.088 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.243 ns ( 15.37 % ) + Info: Total interconnect delay = 6.845 ns ( 84.63 % ) + Info: - Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source register is 8.088 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' + Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' + Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 1.243 ns ( 15.37 % ) + Info: Total interconnect delay = 6.845 ns ( 84.63 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Info: Minimum slack time is -687 ps for clock "CLK33M" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" + Info: + Shortest register to register delay is 0.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 0.460 ns ( 100.00 % ) + Info: - Smallest register to register requirement is 1.147 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 0.000 ns + Info: Clock period of Destination clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 1.189 ns + Info: + Longest clock path from clock "CLK33M" to destination register is 7.681 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' + Info: 3: + IC(1.161 ns) + CELL(0.733 ns) = 2.812 ns; Loc. = FF_X33_Y18_N25; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M' + Info: 4: + IC(0.852 ns) + CELL(0.311 ns) = 3.975 ns; Loc. = LCCOMB_X26_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4' + Info: 5: + IC(0.197 ns) + CELL(0.130 ns) = 4.302 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.034 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 7.681 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 2.626 ns ( 34.19 % ) + Info: Total interconnect delay = 5.055 ns ( 65.81 % ) + Info: - Shortest clock path from clock "CLK33M" to source register is 6.492 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' + Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' + Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 6.492 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' + Info: Total cell delay = 2.006 ns ( 30.90 % ) + Info: Total interconnect delay = 4.486 ns ( 69.10 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Warning: Can't achieve minimum setup and hold requirement CLK33M along 26 path(s). See Report window for details. +Info: Minimum slack time is -3.786 ns for clock "MAIN_CLK" between source register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]" + Info: + Shortest register to register delay is 1.930 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]' + Info: 2: + IC(1.597 ns) + CELL(0.242 ns) = 1.839 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]~1' + Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 1.930 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]' + Info: Total cell delay = 0.333 ns ( 17.25 % ) + Info: Total interconnect delay = 1.597 ns ( 82.75 % ) + Info: - Smallest register to register requirement is 5.716 ns + Info: + Hold relationship between source and destination is 0.000 ns + Info: + Latch edge is 0.000 ns + Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Destination register is 1 + Info: Multicycle Hold factor for Destination register is 1 + Info: - Launch edge is 0.000 ns + Info: Clock period of Source clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 + Info: Multicycle Setup factor for Source register is 1 + Info: Multicycle Hold factor for Source register is 1 + Info: + Smallest clock skew is 5.758 ns + Info: + Longest clock path from clock "MAIN_CLK" to destination register is 8.630 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]' + Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.988 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' + Info: 7: + IC(1.108 ns) + CELL(0.534 ns) = 8.630 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]' + Info: Total cell delay = 2.858 ns ( 33.12 % ) + Info: Total interconnect delay = 5.772 ns ( 66.88 % ) + Info: - Shortest clock path from clock "MAIN_CLK" to source register is 2.872 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.357 ns) + CELL(0.534 ns) = 2.872 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]' + Info: Total cell delay = 1.515 ns ( 52.75 % ) + Info: Total interconnect delay = 1.357 ns ( 47.25 % ) + Info: - Micro clock to output delay of source is 0.199 ns + Info: + Micro hold delay of destination is 0.157 ns +Warning: Can't achieve minimum setup and hold requirement MAIN_CLK along 108 path(s). See Report window for details. +Warning: Can't achieve timing requirement tsu along 6867 path(s). See Report window for details. +Info: Slack time is -4.528 ns for clock "MAIN_CLK" between source clock "MAIN_CLK" and destination register "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state" + Info: + tsu requirement for source pin and destination register is 1.000 ns + Info: - tsu from clock to input pin is 5.528 ns + Info: + Longest clock to register delay is 8.706 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(4.109 ns) + CELL(0.869 ns) = 5.959 ns; Loc. = PLL_2; Fanout = 4; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|scandone' + Info: 4: + IC(1.722 ns) + CELL(0.130 ns) = 7.811 ns; Loc. = LCCOMB_X21_Y26_N18; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~0' + Info: 5: + IC(0.198 ns) + CELL(0.130 ns) = 8.139 ns; Loc. = LCCOMB_X21_Y26_N28; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~1' + Info: 6: + IC(0.346 ns) + CELL(0.130 ns) = 8.615 ns; Loc. = LCCOMB_X22_Y26_N16; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~2' + Info: 7: + IC(0.000 ns) + CELL(0.091 ns) = 8.706 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state' + Info: Total cell delay = 2.331 ns ( 26.77 % ) + Info: Total interconnect delay = 6.375 ns ( 73.23 % ) + Info: + Micro setup delay of destination is -0.015 ns + Info: - Shortest clock path from clock "MAIN_CLK" to destination register is 3.163 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.648 ns) + CELL(0.534 ns) = 3.163 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state' + Info: Total cell delay = 1.515 ns ( 47.90 % ) + Info: Total interconnect delay = 1.648 ns ( 52.10 % ) +Warning: Can't achieve timing requirement tco along 4976 path(s). See Report window for details. +Info: Slack time is -14.84 ns for clock "MAIN_CLK" between source register "interrupt_handler:nobody|INT_LATCH[8]" and destination pin "nIRQ[5]" + Info: + tco requirement for source register and destination pin is 1.000 ns + Info: - tco from clock to output pin is 15.840 ns + Info: + Longest clock path from clock "MAIN_CLK" to source register is 9.460 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]' + Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' + Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' + Info: 6: + IC(1.232 ns) + CELL(0.733 ns) = 7.221 ns; Loc. = FF_X18_Y15_N21; Fanout = 5; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' + Info: 7: + IC(0.716 ns) + CELL(0.308 ns) = 8.245 ns; Loc. = LCCOMB_X15_Y15_N6; Fanout = 1; COMB Node = 'interrupt_handler:nobody|INT_LATCH[8]~19' + Info: 8: + IC(0.681 ns) + CELL(0.534 ns) = 9.460 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]' + Info: Total cell delay = 3.899 ns ( 41.22 % ) + Info: Total interconnect delay = 5.561 ns ( 58.78 % ) + Info: + Micro clock to output delay of source is 0.199 ns + Info: + Longest register to pin delay is 6.181 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]' + Info: 2: + IC(0.325 ns) + CELL(0.241 ns) = 0.566 ns; Loc. = LCCOMB_X16_Y12_N20; Fanout = 1; COMB Node = 'interrupt_handler:nobody|_~17' + Info: 3: + IC(0.198 ns) + CELL(0.130 ns) = 0.894 ns; Loc. = LCCOMB_X16_Y12_N22; Fanout = 1; COMB Node = 'interrupt_handler:nobody|nIRQ[5]' + Info: 4: + IC(1.158 ns) + CELL(4.129 ns) = 6.181 ns; Loc. = IOOBUF_X0_Y12_N16; Fanout = 1; COMB Node = 'nIRQ[5]~output' + Info: 5: + IC(0.000 ns) + CELL(0.000 ns) = 6.181 ns; Loc. = PIN_P5; Fanout = 0; PIN Node = 'nIRQ[5]' + Info: Total cell delay = 4.500 ns ( 72.80 % ) + Info: Total interconnect delay = 1.681 ns ( 27.20 % ) +Info: Slack time is -11.944 ns between source pin "nFB_CS1" and destination pin "FB_AD[18]" + Info: + Longest pin to pin requirement is 1.000 ns + Info: - Longest pin to pin delay is 12.944 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T8; Fanout = 1; PIN Node = 'nFB_CS1' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X14_Y0_N29; Fanout = 59; COMB Node = 'nFB_CS1~input' + Info: 3: + IC(1.591 ns) + CELL(0.241 ns) = 2.750 ns; Loc. = LCCOMB_X27_Y14_N12; Fanout = 68; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1' + Info: 4: + IC(0.915 ns) + CELL(0.130 ns) = 3.795 ns; Loc. = LCCOMB_X29_Y10_N14; Fanout = 12; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB_CS' + Info: 5: + IC(0.302 ns) + CELL(0.342 ns) = 4.439 ns; Loc. = LCCOMB_X29_Y10_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~44' + Info: 6: + IC(0.648 ns) + CELL(0.243 ns) = 5.330 ns; Loc. = LCCOMB_X30_Y13_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~48' + Info: 7: + IC(0.807 ns) + CELL(0.243 ns) = 6.380 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~55' + Info: 8: + IC(0.200 ns) + CELL(0.130 ns) = 6.710 ns; Loc. = LCCOMB_X28_Y12_N30; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5' + Info: 9: + IC(1.088 ns) + CELL(0.242 ns) = 8.040 ns; Loc. = LCCOMB_X21_Y14_N4; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180' + Info: 10: + IC(0.876 ns) + CELL(4.028 ns) = 12.944 ns; Loc. = IOOBUF_X20_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[18]~output' + Info: 11: + IC(0.000 ns) + CELL(0.000 ns) = 12.944 ns; Loc. = PIN_V9; Fanout = 0; PIN Node = 'FB_AD[18]' + Info: Total cell delay = 6.517 ns ( 50.35 % ) + Info: Total interconnect delay = 6.427 ns ( 49.65 % ) +Warning: Can't achieve timing requirement tpd along 514 path(s). See Report window for details. +Warning: Can't achieve timing requirement th along 117 path(s). See Report window for details. +Info: Minimum slack time is -401 ps for clock "MAIN_CLK" between source pin "FB_AD[25]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]" + Info: + th requirement for source pin and destination register is 1.000 ns + Info: - th from clock to input pin is 1.401 ns + Info: + Longest clock path from clock "MAIN_CLK" to destination register is 4.679 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' + Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' + Info: 3: + IC(3.164 ns) + CELL(0.534 ns) = 4.679 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]' + Info: Total cell delay = 1.515 ns ( 32.38 % ) + Info: Total interconnect delay = 3.164 ns ( 67.62 % ) + Info: + Micro hold delay of destination is 0.157 ns + Info: - Shortest pin to register delay is 3.435 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AA9; Fanout = 1; PIN Node = 'FB_AD[25]' + Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X27_Y0_N8; Fanout = 59; COMB Node = 'FB_AD[25]~input' + Info: 3: + IC(2.175 ns) + CELL(0.342 ns) = 3.435 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]' + Info: Total cell delay = 1.260 ns ( 36.68 % ) + Info: Total interconnect delay = 2.175 ns ( 63.32 % ) +Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. +Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 65 warnings + Info: Peak virtual memory: 238 megabytes + Info: Processing ended: Wed Dec 15 02:25:23 2010 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:11 + + diff --git a/FPGA_Quartus_13.1/firebee1.tan.summary b/FPGA_Quartus_13.1/firebee1.tan.summary new file mode 100644 index 0000000..219f117 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.tan.summary @@ -0,0 +1,296 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : -4.528 ns +Required Time : 1.000 ns +Actual Time : 5.528 ns +From : MAIN_CLK +To : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state +From Clock : -- +To Clock : MAIN_CLK +Failed Paths : 6867 + +Type : Worst-case tco +Slack : -14.840 ns +Required Time : 1.000 ns +Actual Time : 15.840 ns +From : interrupt_handler:nobody|INT_LATCH[8] +To : nIRQ[5] +From Clock : MAIN_CLK +To Clock : -- +Failed Paths : 4976 + +Type : Worst-case tpd +Slack : -11.944 ns +Required Time : 1.000 ns +Actual Time : 12.944 ns +From : nFB_CS1 +To : FB_AD[18] +From Clock : -- +To Clock : -- +Failed Paths : 514 + +Type : Worst-case th +Slack : -0.401 ns +Required Time : 1.000 ns +Actual Time : 1.401 ns +From : FB_AD[25] +To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] +From Clock : -- +To Clock : MAIN_CLK +Failed Paths : 117 + +Type : Clock Setup: 'CLK33M' +Slack : -5.966 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 +To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +To Clock : CLK33M +Failed Paths : 3741 + +Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' +Slack : -4.615 ns +Required Time : 24.98 MHz ( period = 40.033 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 +To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] +From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +Failed Paths : 3741 + +Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' +Slack : -4.294 ns +Required Time : 95.92 MHz ( period = 10.425 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 +To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +Failed Paths : 3741 + +Type : Clock Setup: 'MAIN_CLK' +Slack : -4.261 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : FB_ALE +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +To Clock : MAIN_CLK +Failed Paths : 27347 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' +Slack : -2.673 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : FB_ALE +To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +Failed Paths : 86 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' +Slack : -1.712 ns +Required Time : 66.00 MHz ( period = 15.151 ns ) +Actual Time : N/A +From : FB_ALE +To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +Failed Paths : 29 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' +Slack : 1.672 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] +Failed Paths : 0 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' +Slack : 2.965 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) +From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' +Slack : 5.299 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] +To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] +Failed Paths : 0 + +Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' +Slack : 28.590 ns +Required Time : 15.99 MHz ( period = 62.552 ns ) +Actual Time : 186.15 MHz ( period = 5.372 ns ) +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' +Slack : 498.663 ns +Required Time : 2.00 MHz ( period = 500.416 ns ) +Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' +Slack : 1997.239 ns +Required Time : 0.50 MHz ( period = 1999.998 ns ) +Actual Time : 362.45 MHz ( period = 2.759 ns ) +From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] +To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] +From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'MAIN_CLK' +Slack : -3.786 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] +To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] +From Clock : MAIN_CLK +To Clock : MAIN_CLK +Failed Paths : 108 + +Type : Clock Hold: 'CLK33M' +Slack : -0.687 ns +Required Time : 33.00 MHz ( period = 30.303 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +From Clock : CLK33M +To Clock : CLK33M +Failed Paths : 26 + +Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' +Slack : -0.454 ns +Required Time : 24.98 MHz ( period = 40.033 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] +Failed Paths : 26 + +Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' +Slack : 0.502 ns +Required Time : 15.99 MHz ( period = 62.552 ns ) +Actual Time : N/A +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' +Slack : 0.502 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] +To : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' +Slack : 0.502 ns +Required Time : 95.92 MHz ( period = 10.425 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] +From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' +Slack : 0.564 ns +Required Time : 2.00 MHz ( period = 500.416 ns ) +Actual Time : N/A +From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] +To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] +From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' +Slack : 0.825 ns +Required Time : 0.50 MHz ( period = 1999.998 ns ) +Actual Time : N/A +From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] +To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] +From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' +Slack : 1.825 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] +To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' +Slack : 2.664 ns +Required Time : 66.00 MHz ( period = 15.151 ns ) +Actual Time : N/A +From : FB_ALE +To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' +Slack : 3.263 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] +Failed Paths : 0 + +Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' +Slack : 4.336 ns +Required Time : 132.01 MHz ( period = 7.575 ns ) +Actual Time : N/A +From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] +To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] +From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 51319 + +-------------------------------------------------------------------------------------- + diff --git a/FPGA_Quartus_13.1/firebee1_assignment_defaults.qdf b/FPGA_Quartus_13.1/firebee1_assignment_defaults.qdf new file mode 100644 index 0000000..2119467 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1_assignment_defaults.qdf @@ -0,0 +1,687 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 08:49:57 June 14, 2010 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus II software and is used +# to preserve global assignments across Quartus II versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name SMART_RECOMPILE Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name IGNORE_CLOCK_SETTINGS Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off +set_global_assignment -name ENABLE_CLOCK_LATENCY Off +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV E" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II" +set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix +set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10 +set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200 +set_global_assignment -name DO_MIN_ANALYSIS Off +set_global_assignment -name DO_MIN_TIMING Off +set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off +set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix +set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name DISABLE_OCP_HW_EVAL Off +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On +set_global_assignment -name PARALLEL_SYNTHESIS -value ON +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III LS" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy III" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Arria II GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy IV" +set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy Stratix" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV" +set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV" +set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX" +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name DUTY_CYCLE 50 -section_id ? +set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ? +set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ? +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? diff --git a/FPGA_Quartus_13.1/firebeei1.qpf b/FPGA_Quartus_13.1/firebeei1.qpf new file mode 100644 index 0000000..8ab6c97 --- /dev/null +++ b/FPGA_Quartus_13.1/firebeei1.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "8.1" +DATE = "10:07:29 September 03, 2009" + + +# Revisions + +PROJECT_REVISION = "firebee1" diff --git a/FPGA_Quartus_13.1/firebeei1.qws b/FPGA_Quartus_13.1/firebeei1.qws new file mode 100644 index 0000000..89bdcec --- /dev/null +++ b/FPGA_Quartus_13.1/firebeei1.qws @@ -0,0 +1,27 @@ +[ProjectWorkspace] +ptn_Child1=Frames +[ProjectWorkspace.Frames] +ptn_Child1=ChildFrames +[ProjectWorkspace.Frames.ChildFrames] +ptn_Child1=Document-0 +ptn_Child2=Document-1 +ptn_Child3=Document-2 +ptn_Child4=Document-3 +[ProjectWorkspace.Frames.ChildFrames.Document-0] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] +DocPathName=firebee1.bdf +DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-1] +ptn_Child1=ViewFrame-0 +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] +DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} +IsChildFrameDetached=False +IsActiveChildFrame=False +ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/FPGA_Quartus_13.1/lpm_bustri_BYT.bsf b/FPGA_Quartus_13.1/lpm_bustri_BYT.bsf new file mode 100644 index 0000000..dcc4b63 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_BYT.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 96 40) + (text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 96 24) + (bidir) + (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) + (text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 96 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "8" (rect 71 25 76 37)(font "Arial" )) + (text "8" (rect 15 25 20 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 66 28)(pt 74 20)(line_width 1)) + (line (pt 10 28)(pt 18 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/lpm_bustri_BYT.cmp b/FPGA_Quartus_13.1/lpm_bustri_BYT.cmp new file mode 100644 index 0000000..3cf925e --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_BYT.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri_BYT + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/lpm_bustri_BYT.inc b/FPGA_Quartus_13.1/lpm_bustri_BYT.inc new file mode 100644 index 0000000..8cb4941 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_BYT.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri_BYT +( + data[7..0], + enabledt +) + +RETURNS ( + tridata[7..0] +); diff --git a/FPGA_Quartus_13.1/lpm_bustri_BYT.qip b/FPGA_Quartus_13.1/lpm_bustri_BYT.qip new file mode 100644 index 0000000..89e40bd --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_BYT.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_bustri_BYT.vhd b/FPGA_Quartus_13.1/lpm_bustri_BYT.vhd new file mode 100644 index 0000000..d24e3cb --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_BYT.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri_BYT.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri_BYT IS + PORT + ( + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END lpm_bustri_BYT; + + +ARCHITECTURE SYN OF lpm_bustri_byt IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 8 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0] +-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/lpm_bustri_LONG.bsf b/FPGA_Quartus_13.1/lpm_bustri_LONG.bsf new file mode 100644 index 0000000..6535d3e --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_LONG.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 112 40) + (text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 112 24) + (bidir) + (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 112 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "32" (rect 77 25 87 37)(font "Arial" )) + (text "32" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 72 28)(pt 80 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/lpm_bustri_LONG.cmp b/FPGA_Quartus_13.1/lpm_bustri_LONG.cmp new file mode 100644 index 0000000..3a268db --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_LONG.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri_LONG + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/lpm_bustri_LONG.inc b/FPGA_Quartus_13.1/lpm_bustri_LONG.inc new file mode 100644 index 0000000..f180c48 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_LONG.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri_LONG +( + data[31..0], + enabledt +) + +RETURNS ( + tridata[31..0] +); diff --git a/FPGA_Quartus_13.1/lpm_bustri_LONG.qip b/FPGA_Quartus_13.1/lpm_bustri_LONG.qip new file mode 100644 index 0000000..67b7232 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_LONG.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_bustri_LONG.vhd b/FPGA_Quartus_13.1/lpm_bustri_LONG.vhd new file mode 100644 index 0000000..3de83c0 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_LONG.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri_LONG.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri_LONG IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_bustri_LONG; + + +ARCHITECTURE SYN OF lpm_bustri_long IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 32 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0] +-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0 +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.bsf b/FPGA_Quartus_13.1/lpm_bustri_WORD.bsf new file mode 100644 index 0000000..4e882d1 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_WORD.bsf @@ -0,0 +1,56 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 112 40) + (text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 24 25 36)(font "Arial" )) + (port + (pt 40 40) + (input) + (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) + (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) + (line (pt 40 40)(pt 40 28)(line_width 1)) + ) + (port + (pt 0 24) + (input) + (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 0 24)(pt 32 24)(line_width 3)) + ) + (port + (pt 112 24) + (bidir) + (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) + (line (pt 112 24)(pt 48 24)(line_width 3)) + ) + (drawing + (text "16" (rect 77 25 87 37)(font "Arial" )) + (text "16" (rect 13 25 23 37)(font "Arial" )) + (line (pt 32 16)(pt 48 24)(line_width 1)) + (line (pt 48 24)(pt 32 32)(line_width 1)) + (line (pt 32 32)(pt 32 16)(line_width 1)) + (line (pt 72 28)(pt 80 20)(line_width 1)) + (line (pt 8 28)(pt 16 20)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.cmp b/FPGA_Quartus_13.1/lpm_bustri_WORD.cmp new file mode 100644 index 0000000..1f03a0e --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_WORD.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_bustri_WORD + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.inc b/FPGA_Quartus_13.1/lpm_bustri_WORD.inc new file mode 100644 index 0000000..09f6251 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_WORD.inc @@ -0,0 +1,24 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION lpm_bustri_WORD +( + data[15..0], + enabledt +) + +RETURNS ( + tridata[15..0] +); diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.qip b/FPGA_Quartus_13.1/lpm_bustri_WORD.qip new file mode 100644 index 0000000..57bbe2e --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_WORD.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd b/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd new file mode 100644 index 0000000..85cbdd1 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd @@ -0,0 +1,107 @@ +-- megafunction wizard: %LPM_BUSTRI% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_bustri + +-- ============================================================ +-- File Name: lpm_bustri_WORD.vhd +-- Megafunction Name(s): +-- lpm_bustri +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_bustri_WORD IS + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + enabledt : IN STD_LOGIC ; + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END lpm_bustri_WORD; + + +ARCHITECTURE SYN OF lpm_bustri_word IS + + + + + COMPONENT lpm_bustri + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + enabledt : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + + lpm_bustri_component : lpm_bustri + GENERIC MAP ( + lpm_type => "LPM_BUSTRI", + lpm_width => 16 + ) + PORT MAP ( + enabledt => enabledt, + data => data, + tridata => tridata + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: BiDir NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt +-- Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0] +-- Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0 +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/lpm_counter0.bsf b/FPGA_Quartus_13.1/lpm_counter0.bsf new file mode 100644 index 0000000..7fc7aaa --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter0.bsf @@ -0,0 +1,49 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 144 64) + (text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 48 25 60)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) + (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 144 40) + (output) + (text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8))) + (line (pt 144 40)(pt 128 40)(line_width 3)) + ) + (drawing + (text "up counter" (rect 84 17 128 29)(font "Arial" )) + (line (pt 16 16)(pt 128 16)(line_width 1)) + (line (pt 128 16)(pt 128 48)(line_width 1)) + (line (pt 128 48)(pt 16 48)(line_width 1)) + (line (pt 16 48)(pt 16 16)(line_width 1)) + (line (pt 16 26)(pt 22 32)(line_width 1)) + (line (pt 22 32)(pt 16 38)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/lpm_counter0.cmp b/FPGA_Quartus_13.1/lpm_counter0.cmp new file mode 100644 index 0000000..ad18248 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter0.cmp @@ -0,0 +1,22 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_counter0 + PORT + ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/lpm_counter0.qip b/FPGA_Quartus_13.1/lpm_counter0.qip new file mode 100644 index 0000000..a72845b --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_counter0.vhd b/FPGA_Quartus_13.1/lpm_counter0.vhd new file mode 100644 index 0000000..9135dbc --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter0.vhd @@ -0,0 +1,126 @@ +-- megafunction wizard: %LPM_COUNTER% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_counter + +-- ============================================================ +-- File Name: lpm_counter0.vhd +-- Megafunction Name(s): +-- lpm_counter +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_counter0 IS + PORT + ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +END lpm_counter0; + + +ARCHITECTURE SYN OF lpm_counter0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (17 DOWNTO 0); + + + + COMPONENT lpm_counter + GENERIC ( + lpm_direction : STRING; + lpm_port_updown : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + clock : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(17 DOWNTO 0); + + lpm_counter_component : lpm_counter + GENERIC MAP ( + lpm_direction => "UP", + lpm_port_updown => "PORT_UNUSED", + lpm_type => "LPM_COUNTER", + lpm_width => 18 + ) + PORT MAP ( + clock => clock, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACLR NUMERIC "0" +-- Retrieval info: PRIVATE: ALOAD NUMERIC "0" +-- Retrieval info: PRIVATE: ASET NUMERIC "0" +-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" +-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0" +-- Retrieval info: PRIVATE: CarryIn NUMERIC "0" +-- Retrieval info: PRIVATE: CarryOut NUMERIC "0" +-- Retrieval info: PRIVATE: Direction NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0" +-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0" +-- Retrieval info: PRIVATE: SCLR NUMERIC "0" +-- Retrieval info: PRIVATE: SLOAD NUMERIC "0" +-- Retrieval info: PRIVATE: SSET NUMERIC "0" +-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "18" +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP" +-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock +-- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0] +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE 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za-(M2sF^lurj45EfA!!SHPc4Tv{5r{;7l7h69lwv;7l7h(?0;&P+R)1^HW2F~>Nfcl?-dq-`){;>fgbqo$J?1gWQ}nZx zpV)SyXpeo7rhTzl`_6>DW!p|@TOCX|pX0B@+oyEz)|nq~SwB4=ZkB#gQ#QT*yzco1 zT+Lv(S*_cCstuTKzxVMOS6VXHouWNRMbkZP%F* + +Sample Waveforms for lpm_counter0.vhd + + +

Sample behavioral waveforms for design file lpm_counter0.vhd

+

The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter0.vhd. The design lpm_counter0.vhd is a 18 bit up counter.

+
+

Fig. 1 : Wave showing counter operation.

+

+

+ + diff --git a/FPGA_Quartus_13.1/lpm_counter1_waveforms.html b/FPGA_Quartus_13.1/lpm_counter1_waveforms.html new file mode 100644 index 0000000..cea3320 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter1_waveforms.html @@ -0,0 +1,16 @@ + + +Sample Waveforms for lpm_counter1.vhd + + +

Sample behavioral waveforms for design file lpm_counter1.vhd

+

The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter1.vhd. The design lpm_counter1.vhd is a 4 bit up modulus 8 counter.

+
+

Fig. 1 : Wave showing counter operation.

+

+
+

Fig. 2 : Wave showing counter cout and/or modulus operation.

+

The counter counts till the modulus value 7.

+

+ + diff --git a/FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html b/FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html new file mode 100644 index 0000000..12ad5c2 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html @@ -0,0 +1,16 @@ + + +Sample Waveforms for "lpm_fifo_dc0.vhd" + + +

Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd"

+

The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd". The design "lpm_fifo_dc0.vhd" has a write-side depth of 32 words of 8 bits each. a read-side width of 32. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions .

+
+

Fig. 2 : Wave showing FIFO full operation.

+

The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.

+

+ + diff --git a/FPGA_Quartus_13.1/lpm_latch0.bsf b/FPGA_Quartus_13.1/lpm_latch0.bsf new file mode 100644 index 0000000..ddb325c --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_latch0.bsf @@ -0,0 +1,53 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2008 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 80) + (text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10))) + (text "inst" (rect 8 64 25 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) + (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 160 32) + (output) + (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) + (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) + (line (pt 160 32)(pt 144 32)(line_width 3)) + ) + (drawing + (line (pt 16 16)(pt 144 16)(line_width 1)) + (line (pt 144 16)(pt 144 64)(line_width 1)) + (line (pt 144 64)(pt 16 64)(line_width 1)) + (line (pt 16 64)(pt 16 16)(line_width 1)) + ) +) diff --git a/FPGA_Quartus_13.1/lpm_latch0.cmp b/FPGA_Quartus_13.1/lpm_latch0.cmp new file mode 100644 index 0000000..87fbc04 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_latch0.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component lpm_latch0 + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/FPGA_Quartus_13.1/lpm_latch0.qip b/FPGA_Quartus_13.1/lpm_latch0.qip new file mode 100644 index 0000000..1bda27a --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_latch0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_LATCH" +set_global_assignment -name IP_TOOL_VERSION "8.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_latch0.vhd b/FPGA_Quartus_13.1/lpm_latch0.vhd new file mode 100644 index 0000000..1eda161 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_latch0.vhd @@ -0,0 +1,110 @@ +-- megafunction wizard: %LPM_LATCH% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: lpm_latch + +-- ============================================================ +-- File Name: lpm_latch0.vhd +-- Megafunction Name(s): +-- lpm_latch +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 8.1 Build 163 10/28/2008 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2008 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY lpm_latch0 IS + PORT + ( + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END lpm_latch0; + + +ARCHITECTURE SYN OF lpm_latch0 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_latch + GENERIC ( + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + gate : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + lpm_latch_component : lpm_latch + GENERIC MAP ( + lpm_type => "LPM_LATCH", + lpm_width => 32 + ) + PORT MAP ( + data => data, + gate => gate, + q => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: aset NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] +-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0] +-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 +-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0 +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/FPGA_Quartus_13.1/serv_req_info.txt b/FPGA_Quartus_13.1/serv_req_info.txt new file mode 100644 index 0000000..51a4176 --- /dev/null +++ b/FPGA_Quartus_13.1/serv_req_info.txt @@ -0,0 +1,115 @@ + + quartus.exe + VDB + /quartus/db/vdb/vdb_value_bus.cpp + 4101 + + 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) + + loc < m_value->size() + Tue Oct 13 17:01:46 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + loc < m_value->size() +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + VDB + /quartus/db/vdb/vdb_value_bus.cpp + 4101 + + 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) + + loc < m_value->size() + Tue Oct 13 17:11:00 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + loc < m_value->size() +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: GED + Wed Oct 14 23:17:06 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: GED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: SFW, STED + Thu Oct 15 19:23:19 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: SFW, STED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + + 0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6) + + Current editor: RPW, SFW +Current dockable window: PJN + Fri Oct 16 00:14:03 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 0X1002D196 +Current editor: RPW, SFW +Current dockable window: PJN +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: SFW + Sat Oct 17 19:01:54 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: SFW +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + AFC + /quartus/gcl/afc/afc_child_frame.cpp + 1940 + + 0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a) + + (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) + Mon Oct 19 21:58:36 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: RPW, GED + Tue Oct 20 00:53:11 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: RPW, GED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + diff --git a/FPGA_Quartus_13.1/undo_redo.txt b/FPGA_Quartus_13.1/undo_redo.txt new file mode 100644 index 0000000..e69de29 From 95ac8a30046b1f4a4f1e9fdc0cc91c8935492319 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20G=C3=A1lvez?= Date: Mon, 3 Jan 2011 08:10:50 +0000 Subject: [PATCH 002/127] Moved source_fa into trunk From aa1041cb3f90d0121a21bf11bb8f11f657102fd8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 05:45:41 +0000 Subject: [PATCH 003/127] another try to make the old config work From 0a33b29b9592dba554ffcabba311e72047f89892 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 05:48:22 +0000 Subject: [PATCH 004/127] get rid of generated files --- FPGA_Quartus_13.1/altpll0_waveforms.html | 10 - FPGA_Quartus_13.1/altpll1_waveforms.html | 10 - FPGA_Quartus_13.1/altpll2_waveforms.html | 10 - FPGA_Quartus_13.1/altpll3_waveforms.html | 10 - FPGA_Quartus_13.1/firebee1.asm.rpt | 128 - FPGA_Quartus_13.1/firebee1.fit.rpt | 6866 ------------- FPGA_Quartus_13.1/firebee1.flow.rpt | 380 - FPGA_Quartus_13.1/firebee1.map.rpt | 8590 ----------------- FPGA_Quartus_13.1/firebee1.tan.rpt | 6936 ------------- FPGA_Quartus_13.1/lpm_counter0_waveforms.html | 13 - FPGA_Quartus_13.1/lpm_counter1_waveforms.html | 16 - FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html | 16 - 12 files changed, 22985 deletions(-) delete mode 100644 FPGA_Quartus_13.1/altpll0_waveforms.html delete mode 100644 FPGA_Quartus_13.1/altpll1_waveforms.html delete mode 100644 FPGA_Quartus_13.1/altpll2_waveforms.html delete mode 100644 FPGA_Quartus_13.1/altpll3_waveforms.html delete mode 100644 FPGA_Quartus_13.1/firebee1.asm.rpt delete mode 100644 FPGA_Quartus_13.1/firebee1.fit.rpt delete mode 100644 FPGA_Quartus_13.1/firebee1.flow.rpt delete mode 100644 FPGA_Quartus_13.1/firebee1.map.rpt delete mode 100644 FPGA_Quartus_13.1/firebee1.tan.rpt delete mode 100644 FPGA_Quartus_13.1/lpm_counter0_waveforms.html delete mode 100644 FPGA_Quartus_13.1/lpm_counter1_waveforms.html delete mode 100644 FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html diff --git a/FPGA_Quartus_13.1/altpll0_waveforms.html b/FPGA_Quartus_13.1/altpll0_waveforms.html deleted file mode 100644 index 80e236a..0000000 --- a/FPGA_Quartus_13.1/altpll0_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll0.vhd" - - -

Sample behavioral waveforms for design file "altpll0.vhd"

-

-

- - diff --git a/FPGA_Quartus_13.1/altpll1_waveforms.html b/FPGA_Quartus_13.1/altpll1_waveforms.html deleted file mode 100644 index 1382a12..0000000 --- a/FPGA_Quartus_13.1/altpll1_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll1.vhd" - - -

Sample behavioral waveforms for design file "altpll1.vhd"

-

-

- - diff --git a/FPGA_Quartus_13.1/altpll2_waveforms.html b/FPGA_Quartus_13.1/altpll2_waveforms.html deleted file mode 100644 index 1932527..0000000 --- a/FPGA_Quartus_13.1/altpll2_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll2.vhd" - - -

Sample behavioral waveforms for design file "altpll2.vhd"

-

-

- - diff --git a/FPGA_Quartus_13.1/altpll3_waveforms.html b/FPGA_Quartus_13.1/altpll3_waveforms.html deleted file mode 100644 index 3f6367c..0000000 --- a/FPGA_Quartus_13.1/altpll3_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll3.vhd" - - -

Sample behavioral waveforms for design file "altpll3.vhd"

-

-

- - diff --git a/FPGA_Quartus_13.1/firebee1.asm.rpt b/FPGA_Quartus_13.1/firebee1.asm.rpt deleted file mode 100644 index 7ffb13e..0000000 --- a/FPGA_Quartus_13.1/firebee1.asm.rpt +++ /dev/null @@ -1,128 +0,0 @@ -Assembler report for firebee1 -Wed Dec 15 02:25:13 2010 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof - 6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Dec 15 02:25:13 2010 ; -; Revision Name ; firebee1 ; -; Top-level Entity Name ; firebee1 ; -; Family ; Cyclone III ; -; Device ; EP3C40F484C6 ; -+-----------------------+---------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+------------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+------------+---------------+ -; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ; -; Hexadecimal Output File start address ; 0XE0700000 ; 0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; Off ; Off ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Enable OCT_DONE ; Off ; Off ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+------------+---------------+ - - -+------------------------------+ -; Assembler Generated Files ; -+------------------------------+ -; File Name ; -+------------------------------+ -; C:/FireBee/FPGA/firebee1.sof ; -; C:/FireBee/FPGA/firebee1.rbf ; -+------------------------------+ - - -+--------------------------------------------------------+ -; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ; -+----------------+---------------------------------------+ -; Option ; Setting ; -+----------------+---------------------------------------+ -; Device ; EP3C40F484C6 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x0085E8C6 ; -+----------------+---------------------------------------+ - - -+--------------------------------------------------------+ -; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ; -+---------------------+----------------------------------+ -; Option ; Setting ; -+---------------------+----------------------------------+ -; Raw Binary File ; ; -; Compression Ratio ; 2 ; -+---------------------+----------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - Info: Processing started: Wed Dec 15 02:25:08 2010 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 291 megabytes - Info: Processing ended: Wed Dec 15 02:25:13 2010 - Info: Elapsed time: 00:00:05 - Info: Total CPU time (on all processors): 00:00:05 - - diff --git a/FPGA_Quartus_13.1/firebee1.fit.rpt b/FPGA_Quartus_13.1/firebee1.fit.rpt deleted file mode 100644 index e3df129..0000000 --- a/FPGA_Quartus_13.1/firebee1.fit.rpt +++ /dev/null @@ -1,6866 +0,0 @@ -Fitter report for firebee1 -Wed Dec 15 02:25:03 2010 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. I/O Assignment Warnings - 6. Fitter Netlist Optimizations - 7. Ignored Assignments - 8. Incremental Compilation Preservation Summary - 9. Incremental Compilation Partition Settings - 10. Incremental Compilation Placement Preservation - 11. Pin-Out File - 12. Fitter Resource Usage Summary - 13. Input Pins - 14. Output Pins - 15. Bidir Pins - 16. Dual Purpose and Dedicated Pins - 17. I/O Bank Usage - 18. All Package Pins - 19. PLL Summary - 20. PLL Usage - 21. Output Pin Default Load For Reported TCO - 22. Fitter Resource Utilization by Entity - 23. Delay Chain Summary - 24. Pad To Core Delay Chain Fanout - 25. Control Signals - 26. Global & Other Fast Signals - 27. Non-Global High Fan-Out Signals - 28. Fitter RAM Summary - 29. Fitter DSP Block Usage Summary - 30. DSP Block Details - 31. Interconnect Usage Summary - 32. LAB Logic Elements - 33. LAB-wide Signals - 34. LAB Signals Sourced - 35. LAB Signals Sourced Out - 36. LAB Distinct Inputs - 37. I/O Rules Summary - 38. I/O Rules Details - 39. I/O Rules Matrix - 40. Fitter Device Options - 41. Operating Settings and Conditions - 42. Estimated Delay Added for Hold Timing - 43. Fitter Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Fitter Summary ; -+------------------------------------+----------------------------------------------+ -; Fitter Status ; Successful - Wed Dec 15 02:25:02 2010 ; -; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; -; Revision Name ; firebee1 ; -; Top-level Entity Name ; firebee1 ; -; Family ; Cyclone III ; -; Device ; EP3C40F484C6 ; -; Timing Models ; Final ; -; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; -; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ; -; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; -; Total registers ; 4749 ; -; Total pins ; 295 / 332 ( 89 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ; -; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; -; Total PLLs ; 4 / 4 ( 100 % ) ; -+------------------------------------+----------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ -; Device ; EP3C40F484C6 ; ; -; Use TimeQuest Timing Analyzer ; Off ; On ; -; Nominal Core Supply Voltage ; 1.2V ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Device I/O Standard ; 3.3-V LVTTL ; ; -; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ; -; Perform Register Duplication for Performance ; On ; Off ; -; Physical Synthesis Effort Level ; Fast ; Normal ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Optimize Hold Timing ; All Paths ; All Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; SSN Optimization ; Off ; Off ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate full fit report during ECO compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; On ; On ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Packed Registers ; Auto ; Auto ; -; Auto Delay Chains ; On ; On ; -; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ; -; Treat Bidirectional Pin as Output Pin ; Off ; Off ; -; Auto Merge PLLs ; On ; On ; -; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ; -; Stop After Congestion Map Generation ; Off ; Off ; -; Save Intermediate Fitting Results ; Off ; Off ; -; Synchronizer Identification ; Off ; Off ; -; Enable Beneficial Skew Optimization ; On ; On ; -; Optimize Design for Metastability ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -; Use Best Effort Settings for Compilation ; Off ; Off ; -+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+------------------------------------------------------+ -; I/O Assignment Warnings ; -+---------------+--------------------------------------+ -; Pin Name ; Reason ; -+---------------+--------------------------------------+ -; LP_STR ; Missing drive strength ; -; nACSI_ACK ; Missing drive strength ; -; nACSI_RESET ; Missing drive strength ; -; nACSI_CS ; Missing drive strength ; -; ACSI_DIR ; Missing drive strength ; -; ACSI_A1 ; Missing drive strength ; -; nSCSI_ACK ; Missing drive strength ; -; nSCSI_ATN ; Missing drive strength ; -; SCSI_DIR ; Missing drive strength ; -; MIDI_OLR ; Missing drive strength ; -; MIDI_TLR ; Missing drive strength ; -; TxD ; Missing drive strength ; -; RTS ; Missing drive strength ; -; DTR ; Missing drive strength ; -; IDE_RES ; Missing drive strength ; -; nIDE_CS0 ; Missing drive strength ; -; nIDE_CS1 ; Missing drive strength ; -; nIDE_WR ; Missing drive strength ; -; nIDE_RD ; Missing drive strength ; -; nCF_CS0 ; Missing drive strength ; -; nCF_CS1 ; Missing drive strength ; -; nROM3 ; Missing drive strength ; -; nROM4 ; Missing drive strength ; -; nRP_UDS ; Missing drive strength ; -; nRP_LDS ; Missing drive strength ; -; nSDSEL ; Missing drive strength ; -; nWR_GATE ; Missing drive strength ; -; nWR ; Missing drive strength ; -; YM_QA ; Missing drive strength ; -; YM_QB ; Missing drive strength ; -; YM_QC ; Missing drive strength ; -; SD_CLK ; Missing drive strength ; -; DSA_D ; Missing drive strength ; -; nVWE ; Missing slew rate ; -; nVCAS ; Missing slew rate ; -; nVRAS ; Missing slew rate ; -; nVCS ; Missing slew rate ; -; TIN0 ; Missing drive strength ; -; nDREQ1 ; Missing drive strength ; -; LED_FPGA_OK ; Missing slew rate ; -; VCKE ; Missing slew rate ; -; nFB_TA ; Missing drive strength ; -; nDDR_CLK ; Missing slew rate ; -; DDR_CLK ; Missing slew rate ; -; VSYNC_PAD ; Missing slew rate ; -; HSYNC_PAD ; Missing slew rate ; -; nBLANK_PAD ; Missing slew rate ; -; PIXEL_CLK_PAD ; Missing slew rate ; -; nSYNC ; Missing slew rate ; -; nMOT_ON ; Missing drive strength ; -; nSTEP_DIR ; Missing drive strength ; -; nSTEP ; Missing drive strength ; -; LPDIR ; Missing drive strength ; -; BA[1] ; Missing slew rate ; -; BA[0] ; Missing slew rate ; -; nIRQ[7] ; Missing drive strength ; -; nIRQ[6] ; Missing drive strength ; -; nIRQ[5] ; Missing drive strength ; -; nIRQ[4] ; Missing drive strength and slew rate ; -; nIRQ[3] ; Missing drive strength and slew rate ; -; nIRQ[2] ; Missing drive strength and slew rate ; -; VA[12] ; Missing slew rate ; -; VA[11] ; Missing slew rate ; -; VA[10] ; Missing slew rate ; -; VA[9] ; Missing slew rate ; -; VA[8] ; Missing slew rate ; -; VA[7] ; Missing slew rate ; -; VA[6] ; Missing slew rate ; -; VA[5] ; Missing slew rate ; -; VA[4] ; Missing slew rate ; -; VA[3] ; Missing slew rate ; -; VA[2] ; Missing slew rate ; -; VA[1] ; Missing slew rate ; -; VA[0] ; Missing slew rate ; -; VB[7] ; Missing slew rate ; -; VB[6] ; Missing slew rate ; -; VB[5] ; Missing slew rate ; -; VB[4] ; Missing slew rate ; -; VB[3] ; Missing slew rate ; -; VB[2] ; Missing slew rate ; -; VB[1] ; Missing slew rate ; -; VB[0] ; Missing slew rate ; -; VDM[3] ; Missing slew rate ; -; VDM[2] ; Missing slew rate ; -; VDM[1] ; Missing slew rate ; -; VDM[0] ; Missing slew rate ; -; VG[7] ; Missing slew rate ; -; VG[6] ; Missing slew rate ; -; VG[5] ; Missing slew rate ; -; VG[4] ; Missing slew rate ; -; VG[3] ; Missing slew rate ; -; VG[2] ; Missing slew rate ; -; VG[1] ; Missing slew rate ; -; VG[0] ; Missing slew rate ; -; VR[7] ; Missing slew rate ; -; VR[6] ; Missing slew rate ; -; VR[5] ; Missing slew rate ; -; VR[4] ; Missing slew rate ; -; VR[3] ; Missing slew rate ; -; VR[2] ; Missing slew rate ; -; VR[1] ; Missing slew rate ; -; VR[0] ; Missing slew rate ; -; VD[31] ; Missing slew rate ; -; VD[30] ; Missing slew rate ; -; VD[29] ; Missing slew rate ; -; VD[28] ; Missing slew rate ; -; VD[27] ; Missing slew rate ; -; VD[26] ; Missing slew rate ; -; VD[25] ; Missing slew rate ; -; VD[24] ; Missing slew rate ; -; VD[23] ; Missing slew rate ; -; VD[22] ; Missing slew rate ; -; VD[21] ; Missing slew rate ; -; VD[20] ; Missing slew rate ; -; VD[19] ; Missing slew rate ; -; VD[18] ; Missing slew rate ; -; VD[17] ; Missing slew rate ; -; VD[16] ; Missing slew rate ; -; VD[15] ; Missing slew rate ; -; VD[14] ; Missing slew rate ; -; VD[13] ; Missing slew rate ; -; VD[12] ; Missing slew rate ; -; VD[11] ; Missing slew rate ; -; VD[10] ; Missing slew rate ; -; VD[9] ; Missing slew rate ; -; VD[8] ; Missing slew rate ; -; VD[7] ; Missing slew rate ; -; VD[6] ; Missing slew rate ; -; VD[5] ; Missing slew rate ; -; VD[4] ; Missing slew rate ; -; VD[3] ; Missing slew rate ; -; VD[2] ; Missing slew rate ; -; VD[1] ; Missing slew rate ; -; VD[0] ; Missing slew rate ; -; VDQS[3] ; Missing slew rate ; -; VDQS[2] ; Missing slew rate ; -; VDQS[1] ; Missing slew rate ; -; VDQS[0] ; Missing slew rate ; -; SCSI_PAR ; Missing drive strength ; -; nSCSI_SEL ; Missing drive strength ; -; nSCSI_BUSY ; Missing drive strength ; -; nSCSI_RST ; Missing drive strength ; -; SD_CD_DATA3 ; Missing drive strength ; -; SD_CMD_D1 ; Missing drive strength ; -; ACSI_D[7] ; Missing drive strength ; -; ACSI_D[6] ; Missing drive strength ; -; ACSI_D[5] ; Missing drive strength ; -; ACSI_D[4] ; Missing drive strength ; -; ACSI_D[3] ; Missing drive strength ; -; ACSI_D[2] ; Missing drive strength ; -; ACSI_D[1] ; Missing drive strength ; -; ACSI_D[0] ; Missing drive strength ; -; LP_D[7] ; Missing drive strength ; -; LP_D[6] ; Missing drive strength ; -; LP_D[5] ; Missing drive strength ; -; LP_D[4] ; Missing drive strength ; -; LP_D[3] ; Missing drive strength ; -; LP_D[2] ; Missing drive strength ; -; LP_D[1] ; Missing drive strength ; -; LP_D[0] ; Missing drive strength ; -; SCSI_D[7] ; Missing drive strength ; -; SCSI_D[6] ; Missing drive strength ; -; SCSI_D[5] ; Missing drive strength ; -; SCSI_D[4] ; Missing drive strength ; -; SCSI_D[3] ; Missing drive strength ; -; SCSI_D[2] ; Missing drive strength ; -; SCSI_D[1] ; Missing drive strength ; -; SCSI_D[0] ; Missing drive strength ; -+---------------+--------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Netlist Optimizations ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR~_Duplicate_1 ; Q ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSTEP_DIR~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; Q ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nMOT_ON~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSTEP~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|STEP ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; Q ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nWR_GATE~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; Packed Register ; Register Packing ; PLL Source Synchronous assignment ; Q ; ; nRD_DATA~input ; O ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nWR~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSDSEL~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; DSA_D~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; RTS~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; DTR~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_STR~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; Q ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LPDIR~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[0]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[1]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[2]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[3]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[4]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[5]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[6]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; LP_D[7]~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_OUTn ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nSCSI_BUSY~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0_Duplicate_1 ; Q ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; nIDE_RD~output ; I ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0SLOAD_MUX ; Created ; Register Packing ; Timing optimization ; COMBOUT ; ; ; ; ; -; Video:Fredi_Aschwanden|inst90 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Q ; ; -; Video:Fredi_Aschwanden|inst90 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[3]~output ; OE ; ; -; Video:Fredi_Aschwanden|inst90 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Q ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[2]~output ; OE ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Q ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[1]~output ; OE ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Duplicated ; Register Packing ; Timing optimization ; Q ; ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Q ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; VDQS[0]~output ; OE ; ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; Inverted ; Register Packing ; Timing optimization ; Q ; ; ; ; ; -; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[28]~input ; O ; ; -; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[29]~input ; O ; ; -; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[30]~input ; O ; ; -; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[31]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[0]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[1]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[2]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[3]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[4]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[5]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[6]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[7]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[8]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[9]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[10]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[11]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[12]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[13]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[14]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[15]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[16]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[17]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[18]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[19]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[20]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[21]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[22]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[23]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[24]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[25]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[26]~input ; O ; ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; Packed Register ; Register Packing ; Timing optimization ; Q ; ; FB_AD[27]~input ; O ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0_RESYN24_BDD25 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~53 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54_RESYN0_BDD1 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~168 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~177 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~178 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN2_BDD3 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN6_BDD7 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~368 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369_RESYN18_BDD19 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~358 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN10_BDD11 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN12_BDD13 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_RESYN50_BDD51 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN16_BDD17 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20_BDD21 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22_BDD23 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS_RESYN56_BDD57 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Add8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~54 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DELCNT~55 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector96~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~30 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|Add3~31 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|Add1~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_01_STRB~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_10_STRB~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add1~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add3~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add5~12 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~17 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add8~18 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add10~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Add11~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_CLK~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan6~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan7~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LessThan8~14 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux84~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux92~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Mux100~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0]~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_A[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_B[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\MUSICGENERATOR:CNT_CH_C[11]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~16 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|Add2~12 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|Add0~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~162 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[3]~163_RESYN8_BDD9 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add0~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add1~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add2~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add3~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add4~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add5~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add6~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Add7~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux88~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|Mux98~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~2 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE~3 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~3 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~4 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0]~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[3]~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|STRB_LOCK~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:STRB_LOCK~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[6]~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG~13 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|STRB_LOCK~0 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:STRB_LOCK~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0_RESYN30_BDD31 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN26_BDD27 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28_BDD29 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN52_BDD53 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~2_RESYN54_BDD55 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START~5 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_END[10] ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[1]~19 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDIS_START[10]~1 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~28_RESYN32_BDD33 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~29 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_7~32 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_8~17 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~29 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_9~32 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_15~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_17~43 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_26~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_27~22 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_28~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_30~20 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_31~1 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|_~472 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|_~478 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|_~479 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|_~481 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|_~482 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~10 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component|dout[5]~11 ; Deleted ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42_BDD43 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN44_BDD45 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN46_BDD47 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN48_BDD49 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13 ; Modified ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34_BDD35 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN36_BDD37 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN38_BDD39 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -; interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN40_BDD41 ; Created ; Physical Synthesis ; Timing optimization ; ; ; ; ; ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+--------------------+-----------------------------------+-----------+----------------+----------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Ignored Assignments ; -+-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ -; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ; -+-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ -; DDIO_INPUT_REGISTER ; altddio_bidir ; ; input_cell_H ; HIGH ; Compiler or HDL Assignment ; -; DDIO_INPUT_REGISTER ; altddio_bidir ; ; input_cell_L ; LOW ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_0hh1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_0hh1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_0hh1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_0hh1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_0hh1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_0hh1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_3fh1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_3fh1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_3fh1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_3fh1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_3fh1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_3fh1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_8fi1 ; ; rdemp_eq_comp_lsb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_8fi1 ; ; rdemp_eq_comp_msb_aeb ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_8fi1 ; ; rs_dgwp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_8fi1 ; ; wrfull_eq_comp_lsb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_8fi1 ; ; wrfull_eq_comp_msb_mux_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -; Synchronizer Identification ; dcfifo_8fi1 ; ; ws_dgrp_reg ; FORCED_IF_ASYNCHRONOUS ; Compiler or HDL Assignment ; -+-----------------------------+----------------+--------------+----------------------------+------------------------+----------------------------+ - - -+------------------------------------------------+ -; Incremental Compilation Preservation Summary ; -+-------------------------+----------------------+ -; Type ; Value ; -+-------------------------+----------------------+ -; Netlist ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -; ; ; -; Placement ; ; -; -- Requested ; 0 / 13829 ( 0.00 % ) ; -; -- Achieved ; 0 / 13829 ( 0.00 % ) ; -; ; ; -; Routing (by Connection) ; ; -; -- Requested ; 0 / 0 ( 0.00 % ) ; -; -- Achieved ; 0 / 0 ( 0.00 % ) ; -+-------------------------+----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; Incremental Compilation Partition Settings ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ -; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; -+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ - - -+--------------------------------------------------------------------------------------------+ -; Incremental Compilation Placement Preservation ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; -+----------------+---------+-------------------+-------------------------+-------------------+ -; Top ; 13829 ; 0 ; N/A ; Source File ; -+----------------+---------+-------------------+-------------------------+-------------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in C:/FireBee/FPGA/firebee1.pin. - - -+----------------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+------------------------------+ -; Resource ; Usage ; -+---------------------------------------------+------------------------------+ -; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; -; -- Combinational with no register ; 4963 ; -; -- Register only ; 1465 ; -; -- Combinational with a register ; 3098 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 4959 ; -; -- 3 input functions ; 1861 ; -; -- <=2 input functions ; 1241 ; -; -- Register only ; 1465 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 7262 ; -; -- arithmetic mode ; 799 ; -; ; ; -; Total registers* ; 4,749 / 41,185 ( 12 % ) ; -; -- Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; -; -- I/O registers ; 186 / 1,585 ( 12 % ) ; -; ; ; -; Total LABs: partially or completely used ; 756 / 2,475 ( 31 % ) ; -; User inserted logic elements ; 0 ; -; Virtual pins ; 0 ; -; I/O pins ; 295 / 332 ( 89 % ) ; -; -- Clock pins ; 7 / 8 ( 88 % ) ; -; -- Dedicated input pins ; 0 / 9 ( 0 % ) ; -; Global signals ; 20 ; -; M9Ks ; 23 / 126 ( 18 % ) ; -; Total block memory bits ; 109,344 / 1,161,216 ( 9 % ) ; -; Total block memory implementation bits ; 211,968 / 1,161,216 ( 18 % ) ; -; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; -; PLLs ; 4 / 4 ( 100 % ) ; -; Global clocks ; 20 / 20 ( 100 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; CRC blocks ; 0 / 1 ( 0 % ) ; -; ASMI blocks ; 0 / 1 ( 0 % ) ; -; Impedance control blocks ; 0 / 4 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 15% / 14% / 16% ; -; Peak interconnect usage (total/H/V) ; 59% / 54% / 65% ; -; Maximum fan-out node ; MAIN_CLK~input ; -; Maximum fan-out ; 2272 ; -; Highest non-global fan-out signal ; MAIN_CLK~input ; -; Highest non-global fan-out ; 2272 ; -; Total fan-out ; 44654 ; -; Average fan-out ; 3.02 ; -+---------------------------------------------+------------------------------+ -* Register count does not include registers inside RAM blocks or DSP blocks. - - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; -+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ -; AMKB_RX ; Y2 ; 2 ; 0 ; 10 ; 21 ; 10 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; CLK33M ; AB12 ; 4 ; 36 ; 0 ; 0 ; 16 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; CTS ; H14 ; 7 ; 61 ; 43 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; DCD ; A19 ; 7 ; 56 ; 43 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; DVI_INT ; A11 ; 8 ; 34 ; 43 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; E0_INT ; G21 ; 6 ; 67 ; 22 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; FB_ALE ; R7 ; 2 ; 0 ; 2 ; 0 ; 33 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; FB_SIZE0 ; U8 ; 3 ; 3 ; 0 ; 21 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; FB_SIZE1 ; Y4 ; 3 ; 3 ; 0 ; 14 ; 24 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; HD_DD ; F16 ; 7 ; 65 ; 43 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; IDE_INT ; G22 ; 6 ; 67 ; 22 ; 7 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; IDE_RDY ; Y1 ; 2 ; 0 ; 9 ; 0 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; LP_BUSY ; G7 ; 8 ; 3 ; 43 ; 28 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; MAIN_CLK ; G2 ; 1 ; 0 ; 21 ; 0 ; 2272 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; MIDI_IN ; E12 ; 7 ; 36 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; PIC_AMKB_RX ; L7 ; 2 ; 0 ; 18 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; PIC_INT ; AA2 ; 2 ; 0 ; 7 ; 21 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; RI ; B19 ; 7 ; 56 ; 43 ; 14 ; 3 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; RxD ; H15 ; 7 ; 61 ; 43 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SD_CARD_DEDECT ; M20 ; 5 ; 67 ; 19 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SD_DATA0 ; B16 ; 7 ; 50 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SD_DATA1 ; A16 ; 7 ; 50 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SD_DATA2 ; B17 ; 7 ; 50 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; SD_WP ; M19 ; 5 ; 67 ; 19 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; TOUT0 ; T22 ; 5 ; 67 ; 22 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; TRACK00 ; C19 ; 7 ; 61 ; 43 ; 28 ; 11 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; WP_CF_CARD ; T1 ; 2 ; 0 ; 21 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nACSI_DRQ ; K7 ; 1 ; 0 ; 30 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nACSI_INT ; J4 ; 1 ; 0 ; 29 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nDACK0 ; B12 ; 7 ; 34 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nDACK1 ; A12 ; 7 ; 34 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nDCHG ; C17 ; 7 ; 56 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nFB_BURST ; T3 ; 2 ; 0 ; 7 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nFB_CS1 ; T8 ; 3 ; 14 ; 0 ; 28 ; 59 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nFB_CS2 ; T9 ; 3 ; 14 ; 0 ; 21 ; 95 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nFB_CS3 ; V6 ; 3 ; 1 ; 0 ; 28 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nFB_OE ; R6 ; 2 ; 0 ; 3 ; 0 ; 101 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nFB_WR ; T5 ; 2 ; 0 ; 4 ; 0 ; 235 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nINDEX ; E16 ; 7 ; 65 ; 43 ; 28 ; 14 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nMASTER ; T21 ; 5 ; 67 ; 22 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nPCI_INTA ; AA1 ; 2 ; 0 ; 6 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nPCI_INTB ; V4 ; 2 ; 0 ; 5 ; 0 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nPCI_INTC ; V3 ; 2 ; 0 ; 5 ; 7 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nPCI_INTD ; P6 ; 2 ; 0 ; 5 ; 14 ; 2 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nRD_DATA ; A20 ; 7 ; 59 ; 43 ; 7 ; 0 ; 2 ; no ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nRSTO_MCF ; B11 ; 8 ; 34 ; 43 ; 21 ; 27 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nSCSI_C_D ; H1 ; 1 ; 0 ; 28 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nSCSI_DRQ ; U1 ; 2 ; 0 ; 15 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nSCSI_I_O ; J3 ; 1 ; 0 ; 28 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nSCSI_MSG ; H2 ; 1 ; 0 ; 29 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -; nWP ; D19 ; 7 ; 59 ; 43 ; 0 ; 4 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; User ; -+----------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ -; ACSI_A1 ; M6 ; 2 ; 0 ; 20 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; ACSI_DIR ; L6 ; 2 ; 0 ; 20 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; AMKB_TX ; N1 ; 2 ; 0 ; 19 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 2mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; BA[0] ; W19 ; 5 ; 67 ; 5 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; BA[1] ; AA19 ; 4 ; 56 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; CLK24M576 ; AB10 ; 3 ; 34 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; CLK25M ; T4 ; 2 ; 0 ; 4 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; CLKUSB ; J1 ; 1 ; 0 ; 28 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; DDR_CLK ; AB17 ; 4 ; 54 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; DSA_D ; F15 ; 7 ; 63 ; 43 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; DTR ; D15 ; 7 ; 54 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; HSYNC_PAD ; K21 ; 6 ; 67 ; 27 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; IDE_RES ; M5 ; 2 ; 0 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; LED_FPGA_OK ; N19 ; 5 ; 67 ; 15 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 4mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; LPDIR ; E5 ; 8 ; 1 ; 43 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; LP_STR ; E6 ; 8 ; 1 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; MIDI_OLR ; H5 ; 1 ; 0 ; 31 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; MIDI_TLR ; B2 ; 1 ; 0 ; 41 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; PIXEL_CLK_PAD ; F19 ; 6 ; 67 ; 37 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; RTS ; B18 ; 7 ; 54 ; 43 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; SCSI_DIR ; J7 ; 1 ; 0 ; 30 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; SD_CLK ; C15 ; 7 ; 50 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; TIN0 ; R5 ; 2 ; 0 ; 4 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; TxD ; A18 ; 7 ; 54 ; 43 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[0] ; W20 ; 5 ; 67 ; 3 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[10] ; V21 ; 5 ; 67 ; 10 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[11] ; U19 ; 5 ; 67 ; 7 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[12] ; AA18 ; 4 ; 54 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[1] ; W22 ; 5 ; 67 ; 7 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[2] ; W21 ; 5 ; 67 ; 8 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[3] ; Y22 ; 5 ; 67 ; 6 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[4] ; AA22 ; 5 ; 67 ; 2 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[5] ; Y21 ; 5 ; 67 ; 7 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[6] ; AA21 ; 5 ; 67 ; 2 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[7] ; AA20 ; 4 ; 61 ; 0 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[8] ; AB20 ; 4 ; 61 ; 0 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VA[9] ; AB19 ; 4 ; 59 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[0] ; G18 ; 6 ; 67 ; 37 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[1] ; H17 ; 6 ; 67 ; 38 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[2] ; C22 ; 6 ; 67 ; 38 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[3] ; C21 ; 6 ; 67 ; 38 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[4] ; B22 ; 6 ; 67 ; 39 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[5] ; B21 ; 6 ; 67 ; 39 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[6] ; C20 ; 6 ; 67 ; 39 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VB[7] ; D20 ; 6 ; 67 ; 40 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VCKE ; U15 ; 4 ; 50 ; 0 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VDM[0] ; AA16 ; 4 ; 45 ; 0 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VDM[1] ; V16 ; 4 ; 61 ; 0 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VDM[2] ; U20 ; 5 ; 67 ; 7 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VDM[3] ; T17 ; 5 ; 67 ; 3 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[0] ; H19 ; 6 ; 67 ; 34 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[1] ; E22 ; 6 ; 67 ; 34 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[2] ; E21 ; 6 ; 67 ; 34 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[3] ; H18 ; 6 ; 67 ; 35 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[4] ; J17 ; 6 ; 67 ; 36 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[5] ; H16 ; 6 ; 67 ; 36 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[6] ; D22 ; 6 ; 67 ; 36 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VG[7] ; D21 ; 6 ; 67 ; 36 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[0] ; J22 ; 6 ; 67 ; 28 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[1] ; J21 ; 6 ; 67 ; 28 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[2] ; H22 ; 6 ; 67 ; 28 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[3] ; H21 ; 6 ; 67 ; 28 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[4] ; K17 ; 6 ; 67 ; 29 ; 0 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[5] ; K18 ; 6 ; 67 ; 30 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[6] ; J18 ; 6 ; 67 ; 31 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VR[7] ; F22 ; 6 ; 67 ; 31 ; 7 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; VSYNC_PAD ; K19 ; 6 ; 67 ; 26 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; YM_QA ; A17 ; 7 ; 52 ; 43 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; YM_QB ; G13 ; 7 ; 52 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; YM_QC ; E15 ; 7 ; 54 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nACSI_ACK ; M4 ; 2 ; 0 ; 19 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nACSI_CS ; M2 ; 2 ; 0 ; 20 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nACSI_RESET ; M1 ; 2 ; 0 ; 20 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nBLANK_PAD ; G17 ; 6 ; 67 ; 41 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVTTL ; 16mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nCF_CS0 ; W2 ; 2 ; 0 ; 10 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nCF_CS1 ; W1 ; 2 ; 0 ; 10 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nDDR_CLK ; AA17 ; 4 ; 54 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nDREQ1 ; E11 ; 7 ; 36 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nFB_TA ; T7 ; 2 ; 0 ; 2 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIDE_CS0 ; R2 ; 2 ; 0 ; 16 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIDE_CS1 ; R1 ; 2 ; 0 ; 16 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIDE_RD ; P1 ; 2 ; 0 ; 17 ; 21 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIDE_WR ; P2 ; 2 ; 0 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIRQ[2] ; F21 ; 6 ; 67 ; 31 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIRQ[3] ; H20 ; 6 ; 67 ; 34 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIRQ[4] ; F20 ; 6 ; 67 ; 37 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIRQ[5] ; P5 ; 2 ; 0 ; 12 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIRQ[6] ; P7 ; 2 ; 0 ; 7 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nIRQ[7] ; N7 ; 2 ; 0 ; 7 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nMOT_ON ; G16 ; 7 ; 63 ; 43 ; 7 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nPD_VGA ; V1 ; 2 ; 0 ; 13 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nROM3 ; P3 ; 2 ; 0 ; 15 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nROM4 ; U2 ; 2 ; 0 ; 15 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nRP_LDS ; N5 ; 2 ; 0 ; 16 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nRP_UDS ; P4 ; 2 ; 0 ; 16 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSCSI_ACK ; N2 ; 2 ; 0 ; 19 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSCSI_ATN ; M3 ; 2 ; 0 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSDSEL ; B20 ; 7 ; 59 ; 43 ; 14 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSRBHE ; B4 ; 8 ; 7 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSRBLE ; A4 ; 8 ; 9 ; 43 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSRCS ; B8 ; 8 ; 25 ; 43 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSROE ; F11 ; 7 ; 36 ; 43 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSRWE ; F8 ; 8 ; 7 ; 43 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSTEP ; F14 ; 7 ; 63 ; 43 ; 28 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSTEP_DIR ; G15 ; 7 ; 63 ; 43 ; 21 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nSYNC ; F17 ; 6 ; 67 ; 41 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.0-V LVCMOS ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nVCAS ; AB18 ; 4 ; 52 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nVCS ; T18 ; 5 ; 67 ; 3 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nVRAS ; W17 ; 4 ; 59 ; 0 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nVWE ; Y17 ; 4 ; 61 ; 0 ; 28 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nWR ; G14 ; 7 ; 54 ; 43 ; 28 ; yes ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -; nWR_GATE ; D17 ; 7 ; 61 ; 43 ; 14 ; yes ; no ; yes ; 2 ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; User ; 0 pF ; - ; - ; -+---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+------+----------------------+---------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ -; ACSI_D[0] ; B1 ; 1 ; 0 ; 40 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[1] ; G5 ; 1 ; 0 ; 40 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[2] ; E3 ; 1 ; 0 ; 39 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[3] ; C2 ; 1 ; 0 ; 38 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[4] ; C1 ; 1 ; 0 ; 38 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[5] ; D2 ; 1 ; 0 ; 37 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[6] ; H7 ; 1 ; 0 ; 37 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; ACSI_D[7] ; H6 ; 1 ; 0 ; 37 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; FB_AD[0] ; Y3 ; 3 ; 3 ; 0 ; 7 ; 21 ; 25 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[10] ; W7 ; 3 ; 14 ; 0 ; 14 ; 19 ; 27 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[11] ; Y7 ; 3 ; 14 ; 0 ; 7 ; 19 ; 14 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[12] ; U9 ; 3 ; 16 ; 0 ; 21 ; 21 ; 8 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[13] ; V8 ; 3 ; 16 ; 0 ; 14 ; 21 ; 13 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[14] ; W8 ; 3 ; 16 ; 0 ; 7 ; 20 ; 13 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[15] ; AA7 ; 3 ; 16 ; 0 ; 0 ; 19 ; 11 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[16] ; AB7 ; 3 ; 18 ; 0 ; 21 ; 142 ; 10 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted) ; - ; -; FB_AD[17] ; Y8 ; 3 ; 18 ; 0 ; 14 ; 144 ; 9 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 (inverted) ; - ; -; FB_AD[18] ; V9 ; 3 ; 20 ; 0 ; 21 ; 144 ; 9 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; -; FB_AD[19] ; V10 ; 3 ; 20 ; 0 ; 14 ; 142 ; 5 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted) ; - ; -; FB_AD[1] ; Y6 ; 3 ; 5 ; 0 ; 14 ; 20 ; 158 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[20] ; T10 ; 3 ; 18 ; 0 ; 7 ; 143 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; -; FB_AD[21] ; U10 ; 3 ; 22 ; 0 ; 14 ; 142 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; -; FB_AD[22] ; AA8 ; 3 ; 22 ; 0 ; 7 ; 139 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 (inverted) ; - ; -; FB_AD[23] ; AB8 ; 3 ; 22 ; 0 ; 0 ; 136 ; 2 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 (inverted) ; - ; -; FB_AD[24] ; T11 ; 3 ; 18 ; 0 ; 0 ; 62 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted) ; - ; -; FB_AD[25] ; AA9 ; 3 ; 27 ; 0 ; 7 ; 58 ; 3 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 (inverted) ; - ; -; FB_AD[26] ; AB9 ; 3 ; 27 ; 0 ; 0 ; 56 ; 11 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 (inverted) ; - ; -; FB_AD[27] ; U11 ; 3 ; 29 ; 0 ; 28 ; 47 ; 5 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; -; FB_AD[28] ; V11 ; 3 ; 34 ; 0 ; 28 ; 36 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; -; FB_AD[29] ; W10 ; 3 ; 34 ; 0 ; 21 ; 32 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; -; FB_AD[2] ; AA3 ; 3 ; 7 ; 0 ; 28 ; 20 ; 120 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[30] ; Y10 ; 3 ; 34 ; 0 ; 14 ; 36 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; -; FB_AD[31] ; AA10 ; 3 ; 34 ; 0 ; 7 ; 35 ; 1 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 (inverted) ; - ; -; FB_AD[3] ; AB3 ; 3 ; 7 ; 0 ; 21 ; 20 ; 97 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[4] ; W6 ; 3 ; 7 ; 0 ; 14 ; 20 ; 83 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[5] ; V7 ; 3 ; 7 ; 0 ; 7 ; 20 ; 161 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[6] ; AA4 ; 3 ; 9 ; 0 ; 28 ; 19 ; 27 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[7] ; AB4 ; 3 ; 9 ; 0 ; 21 ; 18 ; 26 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[8] ; AA5 ; 3 ; 9 ; 0 ; 14 ; 20 ; 34 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; FB_AD[9] ; AB5 ; 3 ; 9 ; 0 ; 7 ; 20 ; 22 ; no ; yes ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 (inverted) ; - ; -; IO[0] ; A8 ; 8 ; 25 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[10] ; B15 ; 7 ; 45 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[11] ; C13 ; 7 ; 45 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[12] ; D13 ; 7 ; 45 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[13] ; E13 ; 7 ; 41 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[14] ; A14 ; 7 ; 41 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[15] ; B14 ; 7 ; 38 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[16] ; A13 ; 7 ; 38 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[17] ; B13 ; 7 ; 38 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[1] ; A7 ; 8 ; 25 ; 43 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[2] ; B7 ; 8 ; 25 ; 43 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[3] ; A6 ; 8 ; 25 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[4] ; B6 ; 8 ; 22 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[5] ; E9 ; 8 ; 22 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[6] ; C8 ; 8 ; 20 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[7] ; C7 ; 8 ; 20 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[8] ; G10 ; 8 ; 11 ; 43 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; IO[9] ; A15 ; 7 ; 45 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; LP_D[0] ; F7 ; 8 ; 3 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[1] ; C4 ; 8 ; 3 ; 43 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[2] ; C3 ; 8 ; 5 ; 43 ; 28 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[3] ; E7 ; 8 ; 5 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[4] ; D6 ; 8 ; 5 ; 43 ; 14 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[5] ; B3 ; 8 ; 5 ; 43 ; 7 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[6] ; A3 ; 8 ; 5 ; 43 ; 0 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; LP_D[7] ; G8 ; 8 ; 7 ; 43 ; 21 ; 1 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; - ; -; SCSI_D[0] ; J6 ; 1 ; 0 ; 36 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[1] ; E1 ; 1 ; 0 ; 36 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[2] ; F2 ; 1 ; 0 ; 35 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[3] ; F1 ; 1 ; 0 ; 35 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[4] ; G4 ; 1 ; 0 ; 41 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[5] ; G3 ; 1 ; 0 ; 41 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[6] ; L8 ; 1 ; 0 ; 31 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_D[7] ; K8 ; 1 ; 0 ; 30 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SCSI_PAR ; M7 ; 2 ; 0 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SD_CD_DATA3 ; F13 ; 7 ; 45 ; 43 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SD_CMD_D1 ; E14 ; 7 ; 48 ; 43 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; SRD[0] ; B5 ; 8 ; 11 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[10] ; A9 ; 8 ; 32 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[11] ; B10 ; 8 ; 32 ; 43 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[12] ; D10 ; 8 ; 32 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[13] ; F10 ; 8 ; 9 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[14] ; G9 ; 8 ; 1 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[15] ; H10 ; 8 ; 18 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[1] ; A5 ; 8 ; 14 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[2] ; C6 ; 8 ; 9 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[3] ; G11 ; 8 ; 27 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[4] ; C10 ; 8 ; 29 ; 43 ; 21 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[5] ; F9 ; 8 ; 1 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[6] ; E10 ; 8 ; 32 ; 43 ; 7 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[7] ; H11 ; 8 ; 20 ; 43 ; 28 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[8] ; B9 ; 8 ; 29 ; 43 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; SRD[9] ; A10 ; 8 ; 32 ; 43 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; DSP:Mathias_Alles|nSRWE~1 (inverted) ; - ; -; VDQS[0] ; AA15 ; 4 ; 43 ; 0 ; 14 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; - ; -; VDQS[1] ; W15 ; 4 ; 52 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; - ; -; VDQS[2] ; U22 ; 5 ; 67 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; - ; -; VDQS[3] ; T16 ; 4 ; 63 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; yes ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst90 ; - ; -; VD[0] ; M22 ; 5 ; 67 ; 18 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[10] ; P17 ; 5 ; 67 ; 10 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[11] ; R21 ; 5 ; 67 ; 13 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[12] ; N17 ; 5 ; 67 ; 17 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[13] ; P20 ; 5 ; 67 ; 14 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[14] ; R22 ; 5 ; 67 ; 13 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[15] ; N20 ; 5 ; 67 ; 15 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[16] ; T12 ; 4 ; 45 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[17] ; Y13 ; 4 ; 43 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[18] ; AA13 ; 4 ; 38 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[19] ; V14 ; 4 ; 50 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[1] ; M21 ; 5 ; 67 ; 18 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[20] ; U13 ; 4 ; 50 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[21] ; V15 ; 4 ; 50 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[22] ; W14 ; 4 ; 48 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[23] ; AB16 ; 4 ; 45 ; 0 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[24] ; AB15 ; 4 ; 43 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[25] ; AA14 ; 4 ; 38 ; 0 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[26] ; AB14 ; 4 ; 38 ; 0 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[27] ; V13 ; 4 ; 48 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[28] ; W13 ; 4 ; 43 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[29] ; AB13 ; 4 ; 38 ; 0 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[2] ; P22 ; 5 ; 67 ; 14 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[30] ; V12 ; 4 ; 41 ; 0 ; 28 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[31] ; U12 ; 4 ; 43 ; 0 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[3] ; R20 ; 5 ; 67 ; 11 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[4] ; P21 ; 5 ; 67 ; 14 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[5] ; R17 ; 5 ; 67 ; 10 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[6] ; R19 ; 5 ; 67 ; 12 ; 14 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[7] ; U21 ; 5 ; 67 ; 11 ; 0 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[8] ; V22 ; 5 ; 67 ; 10 ; 7 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; VD[9] ; R18 ; 5 ; 67 ; 12 ; 21 ; 3 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 2.5 V ; 12mA ; Off ; -- ; User ; 0 pF ; Video:Fredi_Aschwanden|inst37 (inverted) ; - ; -; nSCSI_BUSY ; N8 ; 2 ; 0 ; 11 ; 14 ; 0 ; 0 ; no ; no ; yes ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; nSCSI_RST ; N6 ; 2 ; 0 ; 12 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -; nSCSI_SEL ; M8 ; 2 ; 0 ; 11 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; User ; 0 pF ; - ; - ; -+-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+---------------------------------------------------------------------------------------------------------------+---------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Dual Purpose and Dedicated Pins ; -+----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ -; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ; -+----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ -; D1 ; DIFFIO_L8n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ; -; E2 ; DIFFIO_L10p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ; -; K6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ; -; K2 ; DCLK ; As input tri-stated ; ~ALTERA_DCLK~ ; Dual Purpose Pin ; -; K1 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ; -; K5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ; -; L3 ; nCE ; - ; - ; Dedicated Programming Pin ; -; N22 ; DIFFIO_R32n, DEV_OE ; Reserved as secondary function ; ~ALTERA_DEV_OE~ ; Dual Purpose Pin ; -; N21 ; DIFFIO_R32p, DEV_CLRn ; Reserved as secondary function ; ~ALTERA_DEV_CLRn~ ; Dual Purpose Pin ; -; M18 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ; -; M17 ; MSEL0 ; - ; - ; Dedicated Programming Pin ; -; L18 ; MSEL1 ; - ; - ; Dedicated Programming Pin ; -; L17 ; MSEL2 ; - ; - ; Dedicated Programming Pin ; -; K20 ; MSEL3 ; - ; - ; Dedicated Programming Pin ; -; K22 ; DIFFIO_R24n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ; -; K21 ; DIFFIO_R24p, CLKUSR ; Use as general purpose IO ; HSYNC_PAD ; Dual Purpose Pin ; -; E22 ; DIFFIO_R12n, nWE ; Use as regular IO ; VG[1] ; Dual Purpose Pin ; -; E21 ; DIFFIO_R12p, nOE ; Use as regular IO ; VG[2] ; Dual Purpose Pin ; -; F20 ; DIFFIO_R8n, nAVD ; Use as regular IO ; nIRQ[4] ; Dual Purpose Pin ; -; F19 ; DIFFIO_R8n, nAVD ; - ; PIXEL_CLK_PAD ; Dual Purpose Pin ; -; G18 ; DIFFIO_R7n, PADD23 ; Use as regular IO ; VB[0] ; Dual Purpose Pin ; -; B22 ; DIFFIO_R5n, PADD22 ; Use as regular IO ; VB[4] ; Dual Purpose Pin ; -; B21 ; DIFFIO_R5p, PADD21 ; Use as regular IO ; VB[5] ; Dual Purpose Pin ; -; C20 ; DIFFIO_R4n, PADD20, DQS2R/CQ3R,CDPCLK5 ; Use as regular IO ; VB[6] ; Dual Purpose Pin ; -; B18 ; DIFFIO_T45p, PADD0 ; Use as regular IO ; RTS ; Dual Purpose Pin ; -; A17 ; DIFFIO_T41n, PADD1 ; Use as regular IO ; YM_QA ; Dual Purpose Pin ; -; B17 ; DIFFIO_T41p, PADD2 ; Use as regular IO ; SD_DATA2 ; Dual Purpose Pin ; -; E14 ; DIFFIO_T38n, PADD3 ; Use as regular IO ; SD_CMD_D1 ; Dual Purpose Pin ; -; F13 ; DIFFIO_T37p, PADD4, DQS2T/CQ3T,DPCLK8 ; Use as regular IO ; SD_CD_DATA3 ; Dual Purpose Pin ; -; A15 ; DIFFIO_T36n, PADD5 ; Use as regular IO ; IO[9] ; Dual Purpose Pin ; -; B15 ; DIFFIO_T36p, PADD6 ; Use as regular IO ; IO[10] ; Dual Purpose Pin ; -; C13 ; DIFFIO_T35n, PADD7 ; Use as regular IO ; IO[11] ; Dual Purpose Pin ; -; D13 ; DIFFIO_T35p, PADD8 ; Use as regular IO ; IO[12] ; Dual Purpose Pin ; -; A14 ; DIFFIO_T31n, PADD9 ; Use as regular IO ; IO[14] ; Dual Purpose Pin ; -; B14 ; DIFFIO_T31p, PADD10 ; Use as regular IO ; IO[15] ; Dual Purpose Pin ; -; A13 ; DIFFIO_T29n, PADD11 ; Use as regular IO ; IO[16] ; Dual Purpose Pin ; -; B13 ; DIFFIO_T29p, PADD12, DQS4T/CQ5T,DPCLK9 ; Use as regular IO ; IO[17] ; Dual Purpose Pin ; -; E11 ; DIFFIO_T27n, PADD13 ; Use as regular IO ; nDREQ1 ; Dual Purpose Pin ; -; F11 ; DIFFIO_T27p, PADD14 ; Use as regular IO ; nSROE ; Dual Purpose Pin ; -; B10 ; DIFFIO_T25p, PADD15 ; Use as regular IO ; SRD[11] ; Dual Purpose Pin ; -; A9 ; DIFFIO_T24n, PADD16 ; Use as regular IO ; SRD[10] ; Dual Purpose Pin ; -; B9 ; DIFFIO_T24p, PADD17, DQS5T/CQ5T#,DPCLK10 ; Use as regular IO ; SRD[8] ; Dual Purpose Pin ; -; A8 ; DIFFIO_T20n, DATA2 ; Use as regular IO ; IO[0] ; Dual Purpose Pin ; -; B8 ; DIFFIO_T20p, DATA3 ; Use as regular IO ; nSRCS ; Dual Purpose Pin ; -; A7 ; DIFFIO_T19n, PADD18 ; Use as regular IO ; IO[1] ; Dual Purpose Pin ; -; B7 ; DIFFIO_T19p, DATA4 ; Use as regular IO ; IO[2] ; Dual Purpose Pin ; -; A6 ; DIFFIO_T18n, PADD19 ; Use as regular IO ; IO[3] ; Dual Purpose Pin ; -; B6 ; DIFFIO_T18p, DATA15 ; Use as regular IO ; IO[4] ; Dual Purpose Pin ; -; C8 ; DIFFIO_T16n, DATA14, DQS3T/CQ3T#,DPCLK11 ; Use as regular IO ; IO[6] ; Dual Purpose Pin ; -; C7 ; DIFFIO_T16p, DATA13 ; Use as regular IO ; IO[7] ; Dual Purpose Pin ; -; A5 ; DIFFIO_T11p, DATA5 ; Use as regular IO ; SRD[1] ; Dual Purpose Pin ; -; F10 ; DIFFIO_T8p, DATA6 ; Use as regular IO ; SRD[13] ; Dual Purpose Pin ; -; C6 ; DIFFIO_T7n, DATA7 ; Use as regular IO ; SRD[2] ; Dual Purpose Pin ; -; B4 ; DIFFIO_T6p, DATA8 ; Use as regular IO ; nSRBHE ; Dual Purpose Pin ; -; F8 ; DIFFIO_T5n, DATA9 ; Use as regular IO ; nSRWE ; Dual Purpose Pin ; -; A3 ; DIFFIO_T4n, DATA10 ; Use as regular IO ; LP_D[6] ; Dual Purpose Pin ; -; B3 ; DIFFIO_T4p, DATA11 ; Use as regular IO ; LP_D[5] ; Dual Purpose Pin ; -; C4 ; DIFFIO_T3p, DATA12, DQS1T/CQ1T#,CDPCLK7 ; Use as regular IO ; LP_D[1] ; Dual Purpose Pin ; -+----------+------------------------------------------+--------------------------------+-------------------------+---------------------------+ - - -+-------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+-------------------+---------------+--------------+ -; 1 ; 30 / 36 ( 83 % ) ; 3.3V ; -- ; -; 2 ; 44 / 46 ( 96 % ) ; 3.3V ; -- ; -; 3 ; 38 / 42 ( 90 % ) ; 3.3V ; -- ; -; 4 ; 33 / 43 ( 77 % ) ; 2.5V ; -- ; -; 5 ; 37 / 42 ( 88 % ) ; 2.5V ; -- ; -; 6 ; 35 / 37 ( 95 % ) ; 3.0V ; -- ; -; 7 ; 43 / 43 ( 100 % ) ; 3.3V ; -- ; -; 8 ; 42 / 43 ( 98 % ) ; 3.3V ; -- ; -+----------+-------------------+---------------+--------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; A3 ; 534 ; 8 ; LP_D[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A4 ; 529 ; 8 ; nSRBLE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A5 ; 518 ; 8 ; SRD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A6 ; 501 ; 8 ; IO[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A7 ; 499 ; 8 ; IO[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A8 ; 497 ; 8 ; IO[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A9 ; 487 ; 8 ; SRD[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A10 ; 485 ; 8 ; SRD[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A11 ; 481 ; 8 ; DVI_INT ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A12 ; 479 ; 7 ; nDACK1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A13 ; 473 ; 7 ; IO[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A14 ; 469 ; 7 ; IO[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A15 ; 458 ; 7 ; IO[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A16 ; 448 ; 7 ; SD_DATA1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A17 ; 446 ; 7 ; YM_QA ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A18 ; 437 ; 7 ; TxD ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A19 ; 435 ; 7 ; DCD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A20 ; 430 ; 7 ; nRD_DATA ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; A21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AA1 ; 125 ; 2 ; nPCI_INTA ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; AA2 ; 124 ; 2 ; PIC_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; AA3 ; 154 ; 3 ; FB_AD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA4 ; 158 ; 3 ; FB_AD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA5 ; 160 ; 3 ; FB_AD[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AA7 ; 173 ; 3 ; FB_AD[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA8 ; 183 ; 3 ; FB_AD[22] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA9 ; 189 ; 3 ; FB_AD[25] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA10 ; 202 ; 3 ; FB_AD[31] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AA11 ; 204 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AA12 ; 206 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AA13 ; 208 ; 4 ; VD[18] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA14 ; 210 ; 4 ; VD[25] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA15 ; 220 ; 4 ; VDQS[0] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA16 ; 224 ; 4 ; VDM[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA17 ; 243 ; 4 ; nDDR_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA18 ; 245 ; 4 ; VA[12] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA19 ; 252 ; 4 ; BA[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA20 ; 259 ; 4 ; VA[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AA21 ; 274 ; 5 ; VA[6] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AA22 ; 273 ; 5 ; VA[4] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AB2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; AB3 ; 155 ; 3 ; FB_AD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB4 ; 159 ; 3 ; FB_AD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB5 ; 161 ; 3 ; FB_AD[9] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; AB7 ; 174 ; 3 ; FB_AD[16] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB8 ; 184 ; 3 ; FB_AD[23] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB9 ; 190 ; 3 ; FB_AD[26] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB10 ; 203 ; 3 ; CLK24M576 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB11 ; 205 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; -; AB12 ; 207 ; 4 ; CLK33M ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; AB13 ; 209 ; 4 ; VD[29] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB14 ; 211 ; 4 ; VD[26] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB15 ; 221 ; 4 ; VD[24] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB16 ; 225 ; 4 ; VD[23] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB17 ; 244 ; 4 ; DDR_CLK ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB18 ; 242 ; 4 ; nVCAS ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB19 ; 253 ; 4 ; VA[9] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB20 ; 260 ; 4 ; VA[8] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; AB21 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; B1 ; 4 ; 1 ; ACSI_D[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; B2 ; 3 ; 1 ; MIDI_TLR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; B3 ; 535 ; 8 ; LP_D[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B4 ; 530 ; 8 ; nSRBHE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B5 ; 523 ; 8 ; SRD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B6 ; 502 ; 8 ; IO[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B7 ; 500 ; 8 ; IO[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B8 ; 498 ; 8 ; nSRCS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B9 ; 488 ; 8 ; SRD[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B10 ; 486 ; 8 ; SRD[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B11 ; 482 ; 8 ; nRSTO_MCF ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B12 ; 480 ; 7 ; nDACK0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B13 ; 474 ; 7 ; IO[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B14 ; 470 ; 7 ; IO[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B15 ; 459 ; 7 ; IO[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B16 ; 449 ; 7 ; SD_DATA0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B17 ; 447 ; 7 ; SD_DATA2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B18 ; 438 ; 7 ; RTS ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B19 ; 434 ; 7 ; RI ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B20 ; 431 ; 7 ; nSDSEL ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; B21 ; 404 ; 6 ; VB[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; B22 ; 403 ; 6 ; VB[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C1 ; 15 ; 1 ; ACSI_D[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C2 ; 14 ; 1 ; ACSI_D[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C3 ; 538 ; 8 ; LP_D[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C4 ; 539 ; 8 ; LP_D[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C6 ; 526 ; 8 ; SRD[2] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C7 ; 508 ; 8 ; IO[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C8 ; 507 ; 8 ; IO[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C10 ; 491 ; 8 ; SRD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C13 ; 460 ; 7 ; IO[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C15 ; 450 ; 7 ; SD_CLK ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C17 ; 433 ; 7 ; nDCHG ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; C19 ; 428 ; 7 ; TRACK00 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; C20 ; 405 ; 6 ; VB[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C21 ; 401 ; 6 ; VB[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; C22 ; 400 ; 6 ; VB[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; D1 ; 17 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; D2 ; 16 ; 1 ; ACSI_D[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D6 ; 536 ; 8 ; LP_D[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; D7 ; 527 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; D8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; D9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D10 ; 483 ; 8 ; SRD[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; D11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D13 ; 461 ; 7 ; IO[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; D14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D15 ; 439 ; 7 ; DTR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; D16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D17 ; 426 ; 7 ; nWR_GATE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; D18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; D19 ; 429 ; 7 ; nWP ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; D20 ; 407 ; 6 ; VB[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; D21 ; 395 ; 6 ; VG[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; D22 ; 394 ; 6 ; VG[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E1 ; 22 ; 1 ; SCSI_D[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E2 ; 21 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; E3 ; 9 ; 1 ; ACSI_D[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E4 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; E5 ; 546 ; 8 ; LPDIR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E6 ; 545 ; 8 ; LP_STR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E7 ; 537 ; 8 ; LP_D[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E8 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; E9 ; 506 ; 8 ; IO[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E10 ; 484 ; 8 ; SRD[6] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E11 ; 477 ; 7 ; nDREQ1 ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E12 ; 476 ; 7 ; MIDI_IN ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E13 ; 468 ; 7 ; IO[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E14 ; 453 ; 7 ; SD_CMD_D1 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E15 ; 440 ; 7 ; YM_QC ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E16 ; 418 ; 7 ; nINDEX ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; E17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; E18 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ; -; E19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; -; E20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; E21 ; 388 ; 6 ; VG[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; E22 ; 387 ; 6 ; VG[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; F1 ; 26 ; 1 ; SCSI_D[3] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; F2 ; 25 ; 1 ; SCSI_D[2] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; F3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; F5 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ; -; F6 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; F7 ; 542 ; 8 ; LP_D[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F8 ; 531 ; 8 ; nSRWE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F9 ; 544 ; 8 ; SRD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F10 ; 525 ; 8 ; SRD[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F11 ; 478 ; 7 ; nSROE ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; F13 ; 457 ; 7 ; SD_CD_DATA3 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F14 ; 423 ; 7 ; nSTEP ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F15 ; 419 ; 7 ; DSA_D ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F16 ; 417 ; 7 ; HD_DD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; F17 ; 410 ; 6 ; nSYNC ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; F18 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; F19 ; 397 ; 6 ; PIXEL_CLK_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; F20 ; 396 ; 6 ; nIRQ[4] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; F21 ; 376 ; 6 ; nIRQ[2] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; F22 ; 375 ; 6 ; VR[7] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G1 ; 67 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; G2 ; 66 ; 1 ; MAIN_CLK ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G3 ; 1 ; 1 ; SCSI_D[5] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G4 ; 0 ; 1 ; SCSI_D[4] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G5 ; 5 ; 1 ; ACSI_D[1] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G6 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; G7 ; 543 ; 8 ; LP_BUSY ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G8 ; 532 ; 8 ; LP_D[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G9 ; 547 ; 8 ; SRD[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G10 ; 524 ; 8 ; IO[8] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G11 ; 492 ; 8 ; SRD[3] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; G13 ; 444 ; 7 ; YM_QB ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G14 ; 441 ; 7 ; nWR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G15 ; 422 ; 7 ; nSTEP_DIR ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G16 ; 420 ; 7 ; nMOT_ON ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; G17 ; 411 ; 6 ; nBLANK_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G18 ; 398 ; 6 ; VB[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; -; G20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; G21 ; 345 ; 6 ; E0_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; G22 ; 344 ; 6 ; IDE_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H1 ; 52 ; 1 ; nSCSI_C_D ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H2 ; 51 ; 1 ; nSCSI_MSG ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; H5 ; 42 ; 1 ; MIDI_OLR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H6 ; 19 ; 1 ; ACSI_D[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H7 ; 18 ; 1 ; ACSI_D[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H8 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; H9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; H10 ; 512 ; 8 ; SRD[15] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; H11 ; 511 ; 8 ; SRD[7] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; H12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; H14 ; 425 ; 7 ; CTS ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; H15 ; 424 ; 7 ; RxD ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; H16 ; 393 ; 6 ; VG[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H17 ; 399 ; 6 ; VB[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H18 ; 391 ; 6 ; VG[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H19 ; 386 ; 6 ; VG[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H20 ; 385 ; 6 ; nIRQ[3] ; output ; 3.0-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; H21 ; 365 ; 6 ; VR[3] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; H22 ; 364 ; 6 ; VR[2] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J1 ; 55 ; 1 ; CLKUSB ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J2 ; 54 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J3 ; 53 ; 1 ; nSCSI_I_O ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J4 ; 50 ; 1 ; nACSI_INT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J5 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J6 ; 20 ; 1 ; SCSI_D[0] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J7 ; 45 ; 1 ; SCSI_DIR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J8 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; J17 ; 392 ; 6 ; VG[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J18 ; 374 ; 6 ; VR[6] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; J20 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; -; J21 ; 363 ; 6 ; VR[1] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; J22 ; 362 ; 6 ; VR[0] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K1 ; 59 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; K2 ; 58 ; 1 ; ~ALTERA_DCLK~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; K5 ; 60 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; -; K6 ; 41 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; -; K7 ; 46 ; 1 ; nACSI_DRQ ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K8 ; 44 ; 1 ; SCSI_D[7] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; K17 ; 369 ; 6 ; VR[4] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K18 ; 370 ; 6 ; VR[5] ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K19 ; 357 ; 6 ; VSYNC_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K20 ; 350 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; -; K21 ; 361 ; 6 ; HSYNC_PAD ; output ; 3.0-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; K22 ; 360 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 3.0-V LVTTL ; ; Row I/O ; N ; no ; Off ; -; L1 ; 63 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; L2 ; 62 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; L3 ; 65 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; -; L4 ; 64 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; L5 ; 61 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; L6 ; 70 ; 2 ; ACSI_DIR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L7 ; 79 ; 2 ; PIC_AMKB_RX ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L8 ; 43 ; 1 ; SCSI_D[6] ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; L17 ; 349 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; -; L18 ; 348 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; -; L19 ; ; 6 ; VCCIO6 ; power ; ; 3.0V ; -- ; ; -- ; -- ; -; L20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; L21 ; 354 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; L22 ; 353 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M1 ; 73 ; 2 ; nACSI_RESET ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M2 ; 72 ; 2 ; nACSI_CS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M3 ; 75 ; 2 ; nSCSI_ATN ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M4 ; 74 ; 2 ; nACSI_ACK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M5 ; 80 ; 2 ; IDE_RES ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M6 ; 71 ; 2 ; ACSI_A1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M7 ; 105 ; 2 ; SCSI_PAR ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M8 ; 106 ; 2 ; nSCSI_SEL ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; M16 ; 337 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; M17 ; 347 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; -; M18 ; 346 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; -; M19 ; 336 ; 5 ; SD_WP ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M20 ; 335 ; 5 ; SD_CARD_DEDECT ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; M21 ; 334 ; 5 ; VD[1] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; M22 ; 333 ; 5 ; VD[0] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; N1 ; 77 ; 2 ; AMKB_TX ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; N2 ; 76 ; 2 ; nSCSI_ACK ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; N5 ; 87 ; 2 ; nRP_LDS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; N6 ; 104 ; 2 ; nSCSI_RST ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; N7 ; 122 ; 2 ; nIRQ[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; N8 ; 107 ; 2 ; nSCSI_BUSY ; bidir ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; N16 ; 314 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N17 ; 329 ; 5 ; VD[12] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; N18 ; 330 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; N19 ; 324 ; 5 ; LED_FPGA_OK ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; N20 ; 323 ; 5 ; VD[15] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; N21 ; 332 ; 5 ; ~ALTERA_DEV_CLRn~ / RESERVED_INPUT ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; N22 ; 331 ; 5 ; ~ALTERA_DEV_OE~ / RESERVED_INPUT ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ; -; P1 ; 84 ; 2 ; nIDE_RD ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P2 ; 83 ; 2 ; nIDE_WR ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P3 ; 89 ; 2 ; nROM3 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P4 ; 88 ; 2 ; nRP_UDS ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P5 ; 103 ; 2 ; nIRQ[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P6 ; 131 ; 2 ; nPCI_INTD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P7 ; 123 ; 2 ; nIRQ[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; P15 ; 298 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P16 ; 299 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; P17 ; 302 ; 5 ; VD[10] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; P18 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; P19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; P20 ; 317 ; 5 ; VD[13] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; P21 ; 320 ; 5 ; VD[4] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; P22 ; 319 ; 5 ; VD[2] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R1 ; 86 ; 2 ; nIDE_CS1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; R2 ; 85 ; 2 ; nIDE_CS0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; R5 ; 135 ; 2 ; TIN0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; R6 ; 136 ; 2 ; nFB_OE ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; R7 ; 137 ; 2 ; FB_ALE ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; R8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; R14 ; 268 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R15 ; 269 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R16 ; 267 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; R17 ; 301 ; 5 ; VD[5] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R18 ; 309 ; 5 ; VD[9] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R19 ; 310 ; 5 ; VD[6] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R20 ; 305 ; 5 ; VD[3] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R21 ; 316 ; 5 ; VD[11] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; R22 ; 315 ; 5 ; VD[14] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; T1 ; 69 ; 2 ; WP_CF_CARD ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T2 ; 68 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; -; T3 ; 121 ; 2 ; nFB_BURST ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T4 ; 134 ; 2 ; CLK25M ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T5 ; 133 ; 2 ; nFB_WR ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T6 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T7 ; 138 ; 2 ; nFB_TA ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T8 ; 166 ; 3 ; nFB_CS1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; T9 ; 167 ; 3 ; nFB_CS2 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; T10 ; 176 ; 3 ; FB_AD[20] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; T11 ; 177 ; 3 ; FB_AD[24] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; T12 ; 226 ; 4 ; VD[16] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; T13 ; 227 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T14 ; 240 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T15 ; 241 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; T16 ; 266 ; 4 ; VDQS[3] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; T17 ; 277 ; 5 ; VDM[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; T18 ; 278 ; 5 ; nVCS ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; T19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; T21 ; 343 ; 5 ; nMASTER ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; T22 ; 342 ; 5 ; TOUT0 ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; U1 ; 92 ; 2 ; nSCSI_DRQ ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; U2 ; 91 ; 2 ; nROM4 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; U4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; U5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ; -; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; U7 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U8 ; 146 ; 3 ; FB_SIZE0 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; U9 ; 170 ; 3 ; FB_AD[12] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; U10 ; 182 ; 3 ; FB_AD[21] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; U11 ; 191 ; 3 ; FB_AD[27] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; U12 ; 222 ; 4 ; VD[31] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; U13 ; 233 ; 4 ; VD[20] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; U14 ; 235 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U15 ; 236 ; 4 ; VCKE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; U16 ; 262 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U17 ; 263 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; U18 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; U19 ; 291 ; 5 ; VA[11] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U20 ; 290 ; 5 ; VDM[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U21 ; 308 ; 5 ; VD[7] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; U22 ; 307 ; 5 ; VDQS[2] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; V1 ; 98 ; 2 ; nPD_VGA ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; V2 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ; -; V3 ; 130 ; 2 ; nPCI_INTC ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; V4 ; 129 ; 2 ; nPCI_INTB ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; V5 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ; -; V6 ; 141 ; 3 ; nFB_CS3 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; V7 ; 157 ; 3 ; FB_AD[5] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; V8 ; 171 ; 3 ; FB_AD[13] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; V9 ; 178 ; 3 ; FB_AD[18] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; V10 ; 179 ; 3 ; FB_AD[19] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; V11 ; 199 ; 3 ; FB_AD[28] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; V12 ; 213 ; 4 ; VD[30] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; V13 ; 228 ; 4 ; VD[27] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; V14 ; 234 ; 4 ; VD[19] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; V15 ; 237 ; 4 ; VD[21] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; V16 ; 261 ; 4 ; VDM[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; V17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; -; V18 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ; -; V19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; V21 ; 304 ; 5 ; VA[10] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; V22 ; 303 ; 5 ; VD[8] ; bidir ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W1 ; 111 ; 2 ; nCF_CS1 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; W2 ; 110 ; 2 ; nCF_CS0 ; output ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; W4 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; W5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; W6 ; 156 ; 3 ; FB_AD[4] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; W7 ; 168 ; 3 ; FB_AD[10] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; W8 ; 172 ; 3 ; FB_AD[14] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; W9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; W10 ; 200 ; 3 ; FB_AD[29] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; W11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; W12 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W13 ; 218 ; 4 ; VD[28] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; W14 ; 229 ; 4 ; VD[22] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; W15 ; 239 ; 4 ; VDQS[1] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; W16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W17 ; 257 ; 4 ; nVRAS ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; W18 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; W19 ; 285 ; 5 ; BA[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W20 ; 280 ; 5 ; VA[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W21 ; 293 ; 5 ; VA[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; W22 ; 292 ; 5 ; VA[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y1 ; 113 ; 2 ; IDE_RDY ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; Y2 ; 112 ; 2 ; AMKB_RX ; input ; 3.3-V LVTTL ; ; Row I/O ; Y ; no ; Off ; -; Y3 ; 148 ; 3 ; FB_AD[0] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y4 ; 147 ; 3 ; FB_SIZE1 ; input ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y6 ; 152 ; 3 ; FB_AD[1] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y7 ; 169 ; 3 ; FB_AD[11] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y8 ; 175 ; 3 ; FB_AD[17] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y10 ; 201 ; 3 ; FB_AD[30] ; bidir ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y13 ; 219 ; 4 ; VD[17] ; bidir ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; Y14 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y17 ; 258 ; 4 ; nVWE ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ; -; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y19 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ; -; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; Y21 ; 289 ; 5 ; VA[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -; Y22 ; 288 ; 5 ; VA[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ; -+----------+------------+----------+--------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PLL Summary ; -+-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ -; Name ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 ; -+-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ -; SDC pin name ; inst|altpll_component|auto_generated|pll1 ; inst13|altpll_component|auto_generated|pll1 ; inst12|altpll_component|auto_generated|pll1 ; inst22|altpll_component|auto_generated|pll1 ; -; PLL mode ; Source Synchronous ; Source Synchronous ; Source Synchronous ; Normal ; -; Compensate clock ; clock0 ; clock1 ; clock0 ; clock0 ; -; Compensated input/output pins ; -- ; nRD_DATA ; MAIN_CLK ; -- ; -; Switchover type ; -- ; -- ; -- ; -- ; -; Input frequency 0 ; 33.0 MHz ; 33.0 MHz ; 33.0 MHz ; 48.0 MHz ; -; Input frequency 1 ; -- ; -- ; -- ; -- ; -; Nominal PFD frequency ; 5.5 MHz ; 11.0 MHz ; 33.0 MHz ; 48.0 MHz ; -; Nominal VCO frequency ; 368.5 MHz ; 1199.0 MHz ; 396.0 MHz ; 576.0 MHz ; -; VCO post scale ; 2 ; -- ; 2 ; 2 ; -; VCO frequency control ; Auto ; Auto ; Auto ; Auto ; -; VCO phase shift step ; 339 ps ; 104 ps ; 315 ps ; 217 ps ; -; VCO multiply ; -- ; -- ; -- ; -- ; -; VCO divide ; -- ; -- ; -- ; -- ; -; Freq min lock ; 32.4 MHz ; 16.8 MHz ; 25.0 MHz ; 25.0 MHz ; -; Freq max lock ; 58.23 MHz ; 35.79 MHz ; 54.18 MHz ; 54.18 MHz ; -; M VCO Tap ; 0 ; 0 ; 0 ; 0 ; -; M Initial ; 1 ; 1 ; 1 ; 1 ; -; M value ; 67 ; 109 ; 12 ; 12 ; -; N value ; 6 ; 3 ; 1 ; 1 ; -; Charge pump current ; setting 1 ; setting 1 ; setting 1 ; setting 1 ; -; Loop filter resistance ; setting 16 ; setting 19 ; setting 27 ; setting 27 ; -; Loop filter capacitance ; setting 0 ; setting 0 ; setting 0 ; setting 0 ; -; Bandwidth ; 340 kHz to 540 kHz ; 450 kHz to 560 kHz ; 680 kHz to 980 kHz ; 680 kHz to 980 kHz ; -; Real time reconfigurable ; Off ; Off ; Off ; On ; -; Scan chain MIF file ; -- ; -- ; -- ; altpll4.mif ; -; Preserve PLL counter order ; Off ; Off ; Off ; Off ; -; PLL location ; PLL_3 ; PLL_4 ; PLL_1 ; PLL_2 ; -; Inclk0 signal ; CLK33M ; CLK33M ; MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; -; Inclk1 signal ; -- ; -- ; -- ; -- ; -; Inclk0 signal type ; Global Clock ; Dedicated Pin ; Dedicated Pin ; Global Clock ; -; Inclk1 signal type ; -- ; -- ; -- ; -- ; -+-------------------------------+----------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; PLL Usage ; -+-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ -; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ; -+-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; clock0 ; 1 ; 66 ; 0.5 MHz ; 0 (0 ps) ; 0.67 (339 ps) ; 50/50 ; C1 ; 67 ; 34/33 Odd ; C0 ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[0] ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; clock1 ; 67 ; 900 ; 2.46 MHz ; 0 (0 ps) ; 0.30 (339 ps) ; 50/50 ; C2 ; 150 ; 75/75 Even ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[1] ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; clock2 ; 67 ; 90 ; 24.57 MHz ; 0 (0 ps) ; 3.00 (339 ps) ; 50/50 ; C3 ; 15 ; 8/7 Odd ; -- ; 1 ; 0 ; inst|altpll_component|auto_generated|pll1|clk[2] ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 11 ; 5/6 Odd ; -- ; 1 ; 0 ; ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; clock0 ; 109 ; 1800 ; 2.0 MHz ; 0 (0 ps) ; 0.15 (104 ps) ; 50/50 ; C1 ; 300 ; 150/150 Even ; C0 ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[0] ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; clock1 ; 109 ; 225 ; 15.99 MHz ; 0 (0 ps) ; 0.60 (104 ps) ; 50/50 ; C2 ; 75 ; 38/37 Odd ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[1] ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; clock2 ; 109 ; 144 ; 24.98 MHz ; 0 (0 ps) ; 0.94 (104 ps) ; 50/50 ; C3 ; 48 ; 24/24 Even ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[2] ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; clock3 ; 109 ; 75 ; 47.96 MHz ; 0 (0 ps) ; 1.80 (104 ps) ; 50/50 ; C4 ; 25 ; 13/12 Odd ; -- ; 1 ; 0 ; inst13|altpll_component|auto_generated|pll1|clk[3] ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~cascade_in ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; C0 ; 2 ; 1/1 Even ; -- ; 1 ; 0 ; ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; clock0 ; 4 ; 1 ; 132.0 MHz ; 240 (5051 ps) ; 15.00 (315 ps) ; 50/50 ; C0 ; 3 ; 2/1 Odd ; -- ; 3 ; 0 ; inst12|altpll_component|auto_generated|pll1|clk[0] ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; clock1 ; 4 ; 1 ; 132.0 MHz ; 0 (0 ps) ; 15.00 (315 ps) ; 50/50 ; C3 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; inst12|altpll_component|auto_generated|pll1|clk[1] ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; clock2 ; 4 ; 1 ; 132.0 MHz ; 180 (3788 ps) ; 15.00 (315 ps) ; 50/50 ; C2 ; 3 ; 2/1 Odd ; -- ; 2 ; 4 ; inst12|altpll_component|auto_generated|pll1|clk[2] ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; clock3 ; 4 ; 1 ; 132.0 MHz ; 105 (2210 ps) ; 15.00 (315 ps) ; 50/50 ; C4 ; 3 ; 2/1 Odd ; -- ; 1 ; 7 ; inst12|altpll_component|auto_generated|pll1|clk[3] ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; clock4 ; 2 ; 1 ; 66.0 MHz ; 270 (11364 ps) ; 7.50 (315 ps) ; 50/50 ; C1 ; 6 ; 3/3 Even ; -- ; 5 ; 4 ; inst12|altpll_component|auto_generated|pll1|clk[4] ; -; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; clock0 ; 2 ; 1 ; 96.0 MHz ; 0 (0 ps) ; 7.50 (217 ps) ; 50/50 ; C0 ; 6 ; 3/3 Even ; -- ; 1 ; 0 ; inst22|altpll_component|auto_generated|pll1|clk[0] ; -+-------------------------------------------------------------------------------------+--------------+------+------+------------------+----------------+------------------+------------+---------+---------------+--------------+---------------+---------+---------+----------------------------------------------------+ - - -+-------------------------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------------+-------+------------------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------------+-------+------------------------------------+ -; 3.0-V LVTTL ; 0 pF ; Not Available ; -; 3.3-V LVTTL ; 0 pF ; Not Available ; -; 3.0-V LVCMOS ; 0 pF ; Not Available ; -; 3.3-V LVCMOS ; 0 pF ; Not Available ; -; 3.0-V PCI ; 10 pF ; Not Available ; -; 3.0-V PCI-X ; 10 pF ; Not Available ; -; 2.5 V ; 0 pF ; Not Available ; -; 1.8 V ; 0 pF ; Not Available ; -; 1.5 V ; 0 pF ; Not Available ; -; 1.2 V ; 0 pF ; Not Available ; -; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; Differential 2.5-V SSTL Class I ; 0 pF ; (See SSTL-2) ; -; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; -; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; -; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; -; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; -; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; -; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; -; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; -; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; -; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; -; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; -; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; -; 1.2-V HSTL Class I ; 0 pF ; Not Available ; -; Differential 1.2-V HSTL Class I ; 0 pF ; Not Available ; -; 1.2-V HSTL Class II ; 0 pF ; Not Available ; -; Differential 1.2-V HSTL Class II ; 0 pF ; Not Available ; -; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; -; LVDS ; 0 pF ; 100 Ohm (Differential) ; -; LVDS_E_3R ; 0 pF ; Not Available ; -; RSDS ; 0 pF ; 100 Ohm (Differential) ; -; RSDS_E_1R ; 0 pF ; Not Available ; -; RSDS_E_3R ; 0 pF ; Not Available ; -; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; -; mini-LVDS_E_3R ; 0 pF ; Not Available ; -; PPDS ; 0 pF ; Not Available ; -; PPDS_E_3R ; 0 pF ; Not Available ; -; Bus LVDS ; 0 pF ; Not Available ; -+----------------------------------+-------+------------------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; -+-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |firebee1 ; 9526 (10) ; 4563 (0) ; 186 (186) ; 109344 ; 23 ; 6 ; 0 ; 3 ; 295 ; 0 ; 4963 (10) ; 1465 (0) ; 3098 (0) ; |firebee1 ; work ; -; |DSP:Mathias_Alles| ; 10 (10) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 0 (0) ; |firebee1|DSP:Mathias_Alles ; ; -; |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden| ; 4093 (640) ; 1616 (114) ; 0 (0) ; 16384 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2414 (465) ; 291 (10) ; 1388 (177) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden ; ; -; |WF1772IP_TOP_SOC:I_FDC| ; 976 (17) ; 403 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 565 (9) ; 33 (0) ; 378 (15) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC ; ; -; |WF1772IP_AM_DETECTOR:I_AM_DETECTOR| ; 40 (40) ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 1 (1) ; 26 (26) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR ; ; -; |WF1772IP_CONTROL:I_CONTROL| ; 545 (545) ; 196 (196) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 344 (344) ; 12 (12) ; 189 (189) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL ; ; -; |WF1772IP_CRC_LOGIC:I_CRC_LOGIC| ; 51 (51) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (35) ; 11 (11) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC ; ; -; |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL| ; 103 (103) ; 37 (37) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 66 (66) ; 0 (0) ; 37 (37) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ; -; |WF1772IP_REGISTERS:I_REGISTERS| ; 105 (105) ; 48 (48) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (57) ; 7 (7) ; 41 (41) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS ; ; -; |WF1772IP_TRANSCEIVER:I_TRANSCEIVER| ; 120 (120) ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 2 (2) ; 77 (77) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER ; ; -; |WF2149IP_TOP_SOC:I_SOUND| ; 490 (36) ; 197 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 293 (20) ; 37 (2) ; 160 (18) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND ; ; -; |WF2149IP_WAVE:I_PSG_WAVE| ; 461 (461) ; 181 (181) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 273 (273) ; 35 (35) ; 153 (153) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE ; ; -; |WF5380_TOP_SOC:I_SCSI| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI ; ; -; |WF5380_CONTROL:I_CONTROL| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL ; ; -; |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD| ; 208 (1) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 106 (1) ; 1 (0) ; 101 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD ; ; -; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 21 (21) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 1 (1) ; 10 (10) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; -; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 101 (101) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 54 (54) ; 0 (0) ; 47 (47) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; -; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 41 (41) ; 0 (0) ; 46 (46) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; -; |WF6850IP_TOP_SOC:I_ACIA_MIDI| ; 218 (2) ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 116 (2) ; 10 (0) ; 92 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI ; ; -; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 27 (27) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 6 (6) ; 9 (9) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; -; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 101 (101) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 53 (53) ; 3 (3) ; 45 (45) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; -; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 88 (88) ; 39 (39) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 49 (49) ; 1 (1) ; 38 (38) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; -; |WF68901IP_TOP_SOC:I_MFP| ; 1261 (110) ; 460 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 797 (107) ; 70 (0) ; 394 (71) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP ; ; -; |WF68901IP_GPIO:I_GPIO| ; 49 (49) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 9 (9) ; 17 (17) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO ; ; -; |WF68901IP_INTERRUPTS:I_INTERRUPTS| ; 290 (290) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 159 (159) ; 5 (5) ; 126 (126) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS ; ; -; |WF68901IP_TIMERS:I_TIMERS| ; 501 (501) ; 166 (166) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 332 (332) ; 44 (44) ; 125 (125) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS ; ; -; |WF68901IP_USART_TOP:I_USART| ; 316 (3) ; 140 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (3) ; 12 (0) ; 128 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART ; ; -; |WF68901IP_USART_CTRL:I_USART_CTRL| ; 77 (77) ; 49 (49) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 9 (9) ; 40 (40) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL ; ; -; |WF68901IP_USART_RX:I_USART_RECEIVE| ; 160 (160) ; 56 (56) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 2 (2) ; 58 (58) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE ; ; -; |WF68901IP_USART_TX:I_USART_TRANSMIT| ; 87 (87) ; 35 (35) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 45 (45) ; 1 (1) ; 41 (41) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT ; ; -; |dcfifo0:RDF| ; 156 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 60 (0) ; 66 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF ; ; -; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 156 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (0) ; 60 (0) ; 66 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; -; |dcfifo_0hh1:auto_generated| ; 156 (55) ; 124 (42) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 30 (4) ; 60 (27) ; 66 (13) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ; -; |a_gray2bin_lfb:wrptr_g_gray2bin| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin ; ; -; |a_gray2bin_lfb:ws_dgrp_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin ; ; -; |a_graycounter_fic:wrptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 1 (1) ; 13 (13) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ; -; |a_graycounter_k47:rdptr_g1p| ; 18 (18) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ; -; |alt_synch_pipe_ikd:rs_dgwp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (0) ; 4 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ; -; |dffpipe_hd9:dffpipe12| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 14 (14) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ; -; |alt_synch_pipe_jkd:ws_dgrp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (0) ; 1 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ; -; |dffpipe_id9:dffpipe17| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (17) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ; -; |altsyncram_bi31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ; -; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; -; |cmpr_156:wrfull_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb ; ; -; |cntr_t2e:cntr_b| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b ; ; -; |dffpipe_gd9:ws_brp| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ; -; |dffpipe_pe9:ws_bwp| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (10) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ; -; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; -; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; -; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; -; |mux_a18:wrfull_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; -; |dcfifo1:WRF| ; 166 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 70 (0) ; 54 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF ; ; -; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 166 (0) ; 124 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (0) ; 70 (0) ; 54 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; -; |dcfifo_3fh1:auto_generated| ; 166 (58) ; 124 (42) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 42 (6) ; 70 (34) ; 54 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ; -; |a_gray2bin_lfb:rdptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin ; ; -; |a_gray2bin_lfb:rs_dgwp_gray2bin| ; 8 (8) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin ; ; -; |a_graycounter_gic:wrptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ; -; |a_graycounter_j47:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 12 (12) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ; -; |alt_synch_pipe_kkd:rs_dgwp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (0) ; 3 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ; -; |dffpipe_jd9:dffpipe12| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 15 (15) ; 3 (3) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ; -; |alt_synch_pipe_lkd:ws_dgrp| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (0) ; 2 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ; -; |dffpipe_kd9:dffpipe15| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ; -; |altsyncram_ci31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 8192 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ; -; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; -; |cntr_t2e:cntr_b| ; 4 (4) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b ; ; -; |dffpipe_gd9:rs_bwp| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 6 (6) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ; -; |dffpipe_pe9:rs_brp| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 9 (9) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ; -; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 1 (1) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; -; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 3 (3) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; -; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 2 (2) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; -; |mux_a18:wrfull_eq_comp_msb_mux| ; 6 (6) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; -; |Video:Fredi_Aschwanden| ; 4088 (14) ; 2168 (4) ; 0 (0) ; 92816 ; 20 ; 6 ; 0 ; 3 ; 0 ; 0 ; 1920 (10) ; 916 (4) ; 1252 (0) ; |firebee1|Video:Fredi_Aschwanden ; ; -; |DDR_CTR:DDR_CTR| ; 374 (342) ; 158 (158) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (180) ; 20 (20) ; 143 (140) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR ; ; -; |lpm_bustri_BYT:$00002| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002 ; ; -; |lpm_bustri:lpm_bustri_component| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00004| ; 31 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (0) ; 0 (0) ; 3 (0) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004 ; ; -; |lpm_bustri:lpm_bustri_component| ; 31 (31) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 (28) ; 0 (0) ; 3 (3) ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; -; |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR| ; 1420 (1292) ; 529 (529) ; 0 (0) ; 0 ; 0 ; 6 ; 0 ; 3 ; 0 ; 0 ; 891 (763) ; 158 (158) ; 371 (252) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR ; ; -; |lpm_bustri_WORD:$00000| ; 187 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (0) ; 0 (0) ; 75 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000 ; ; -; |lpm_bustri:lpm_bustri_component| ; 187 (187) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 112 (112) ; 0 (0) ; 75 (75) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_WORD:$00002| ; 60 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 44 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002 ; ; -; |lpm_bustri:lpm_bustri_component| ; 60 (60) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 44 (44) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ; -; |lpm_mult:op_12| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ; -; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated ; ; -; |lpm_mult:op_14| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ; -; |mult_cat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated ; ; -; |lpm_mult:op_6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ; -; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated ; ; -; |altddio_bidir0:inst1| ; 96 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1 ; ; -; |altddio_bidir:altddio_bidir_component| ; 96 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ; -; |ddio_bidir_3jl:auto_generated| ; 96 (96) ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 96 (96) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ; -; |altddio_out0:inst2| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ; -; |ddio_out_are:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ; -; |altddio_out2:inst5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ; -; |ddio_out_o2f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ; -; |altdpram0:ST_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ; -; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; -; |altdpram0:ST_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ; -; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; -; |altdpram0:ST_CLUT_RED| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ; -; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 48 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; -; |altdpram1:FALCON_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ; -; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; -; |altdpram1:FALCON_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ; -; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; -; |altdpram1:FALCON_CLUT_RED| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ; -; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 1536 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; -; |altdpram2:ACP_CLUT_RAM54| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54 ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ; -; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; -; |altdpram2:ACP_CLUT_RAM55| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55 ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ; -; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; -; |altdpram2:ACP_CLUT_RAM| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ; -; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; -; |lpm_bustri_LONG:inst119| ; 5 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119 ; ; -; |lpm_bustri:lpm_bustri_component| ; 5 (5) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ; -; |lpm_ff0:inst13| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 23 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 23 (23) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst14| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 31 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 31 (31) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst15| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 25 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 25 (25) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst16| ; 28 (0) ; 28 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (0) ; 2 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16 ; ; -; |lpm_ff:lpm_ff_component| ; 28 (28) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 2 (2) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst17| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 31 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 31 (31) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst18| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 30 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 30 (30) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst19| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst12| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (0) ; 2 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (30) ; 2 (2) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst20| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 28 (0) ; 4 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 28 (28) ; 4 (4) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst3| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 32 (32) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst4| ; 32 (0) ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (0) ; 6 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4 ; ; -; |lpm_ff:lpm_ff_component| ; 32 (32) ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 26 (26) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst9| ; 24 (0) ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (0) ; 12 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9 ; ; -; |lpm_ff:lpm_ff_component| ; 24 (24) ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 12 (12) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst46| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46 ; ; -; |lpm_ff:lpm_ff_component| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst47| ; 18 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47 ; ; -; |lpm_ff:lpm_ff_component| ; 18 (18) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 18 (18) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst49| ; 9 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49 ; ; -; |lpm_ff:lpm_ff_component| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst52| ; 9 (0) ; 9 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52 ; ; -; |lpm_ff:lpm_ff_component| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 9 (9) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ; -; |lpm_ff4:inst10| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (0) ; 4 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10 ; ; -; |lpm_ff:lpm_ff_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 12 (12) ; 4 (4) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ; -; |lpm_ff5:inst11| ; 8 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11 ; ; -; |lpm_ff:lpm_ff_component| ; 8 (8) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ; -; |lpm_ff5:inst97| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97 ; ; -; |lpm_ff:lpm_ff_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ; -; |lpm_ff6:inst71| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 87 (0) ; 41 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71 ; ; -; |lpm_ff:lpm_ff_component| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 87 (87) ; 41 (41) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ; -; |lpm_ff6:inst94| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 85 (0) ; 43 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94 ; ; -; |lpm_ff:lpm_ff_component| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 85 (85) ; 43 (43) ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ; -; |lpm_fifoDZ:inst63| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63 ; ; -; |scfifo:scfifo_component| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ; -; |scfifo_lk21:auto_generated| ; 22 (0) ; 21 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 21 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated ; ; -; |a_dpfifo_oq21:dpfifo| ; 22 (9) ; 21 (8) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 21 (8) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo ; ; -; |altsyncram_gj81:FIFOram| ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ; -; |cntr_omb:rd_ptr_msb| ; 6 (6) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb ; ; -; |cntr_pmb:wr_ptr| ; 7 (7) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr ; ; -; |lpm_fifo_dc0:inst| ; 118 (0) ; 98 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 51 (0) ; 47 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst ; ; -; |dcfifo:dcfifo_component| ; 118 (0) ; 98 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (0) ; 51 (0) ; 47 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ; -; |dcfifo_8fi1:auto_generated| ; 118 (31) ; 98 (20) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 20 (2) ; 51 (16) ; 47 (10) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ; -; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 3 (3) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; ; -; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; ; -; |a_graycounter_njc:wrptr_gp| ; 18 (18) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 1 (1) ; 13 (13) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ; -; |a_graycounter_s57:rdptr_g1p| ; 20 (20) ; 14 (14) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 1 (1) ; 14 (14) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ; -; |alt_synch_pipe_sld:ws_dgrp| ; 30 (0) ; 30 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ; -; |dffpipe_re9:dffpipe22| ; 30 (30) ; 30 (30) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 30 (30) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ; -; |altsyncram_tl31:fifo_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 65536 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ; -; |dffpipe_9d9:wraclr| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ; -; |dffpipe_oe9:ws_brp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 9 (9) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ; -; |dffpipe_oe9:ws_bwp| ; 9 (9) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ; -; |lpm_latch0:inst27| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27 ; ; -; |lpm_latch:lpm_latch_component| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 31 (31) ; 0 (0) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ; -; |lpm_mux0:inst21| ; 120 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 71 (0) ; 27 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21 ; ; -; |lpm_mux:lpm_mux_component| ; 120 (0) ; 96 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (0) ; 71 (0) ; 27 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component ; ; -; |mux_gpe:auto_generated| ; 120 (120) ; 96 (96) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 71 (71) ; 27 (27) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated ; ; -; |lpm_mux1:inst24| ; 113 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 33 (0) ; 48 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24 ; ; -; |lpm_mux:lpm_mux_component| ; 113 (0) ; 81 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 33 (0) ; 48 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component ; ; -; |mux_npe:auto_generated| ; 113 (113) ; 81 (81) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 33 (33) ; 48 (48) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated ; ; -; |lpm_mux2:inst25| ; 81 (0) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (0) ; 1 (0) ; 40 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25 ; ; -; |lpm_mux:lpm_mux_component| ; 81 (0) ; 41 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (0) ; 1 (0) ; 40 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component ; ; -; |mux_mpe:auto_generated| ; 81 (81) ; 41 (41) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 1 (1) ; 40 (40) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated ; ; -; |lpm_mux3:inst102| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102 ; ; -; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component ; ; -; |mux_96e:auto_generated| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated ; ; -; |lpm_mux4:inst81| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81 ; ; -; |lpm_mux:lpm_mux_component| ; 7 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component ; ; -; |mux_f6e:auto_generated| ; 7 (7) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated ; ; -; |lpm_mux5:inst22| ; 64 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 60 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22 ; ; -; |lpm_mux:lpm_mux_component| ; 64 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (0) ; 0 (0) ; 60 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component ; ; -; |mux_58e:auto_generated| ; 64 (64) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 60 (60) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated ; ; -; |lpm_mux6:inst7| ; 91 (0) ; 67 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 1 (0) ; 82 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7 ; ; -; |lpm_mux:lpm_mux_component| ; 91 (0) ; 67 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (0) ; 1 (0) ; 82 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component ; ; -; |mux_kpe:auto_generated| ; 91 (91) ; 67 (67) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 1 (1) ; 82 (82) ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated ; ; -; |lpm_muxDZ:inst62| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62 ; ; -; |lpm_mux:lpm_mux_component| ; 128 (0) ; 128 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component ; ; -; |mux_dcf:auto_generated| ; 128 (128) ; 128 (128) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 128 (128) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated ; ; -; |lpm_muxVDM:inst100| ; 736 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (0) ; 0 (0) ; 96 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100 ; ; -; |lpm_mux:lpm_mux_component| ; 736 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (0) ; 0 (0) ; 96 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component ; ; -; |mux_bbe:auto_generated| ; 736 (736) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 640 (640) ; 0 (0) ; 96 (96) ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated ; ; -; |lpm_shiftreg0:sr0| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr1| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr2| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr3| ; 17 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 17 (17) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (2) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr4| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr5| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 15 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 15 (15) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr6| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr7| ; 16 (0) ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 16 (16) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg4:inst26| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg6:inst92| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (0) ; 1 (0) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 1 (1) ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ; -; |mux41:inst40| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40 ; ; -; |mux41:inst41| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41 ; ; -; |mux41:inst42| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42 ; ; -; |mux41:inst43| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43 ; ; -; |mux41:inst44| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44 ; ; -; |mux41:inst45| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45 ; ; -; |altddio_out3:inst5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component ; ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; -; |altddio_out3:inst6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component ; ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; -; |altddio_out3:inst8| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component ; ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; -; |altddio_out3:inst9| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9 ; work ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component ; work ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; work ; -; |altpll1:inst| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst ; ; -; |altpll:altpll_component| ; 1 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst|altpll:altpll_component ; ; -; |altpll_pul2:auto_generated| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated ; ; -; |altpll2:inst12| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12 ; ; -; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12|altpll:altpll_component ; ; -; |altpll_isv2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated ; ; -; |altpll3:inst13| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13 ; ; -; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13|altpll:altpll_component ; ; -; |altpll_41p2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated ; ; -; |altpll4:inst22| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22 ; ; -; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22|altpll:altpll_component ; ; -; |altpll_c6j2:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ; -; |altpll_reconfig1:inst7| ; 334 (0) ; 128 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 206 (0) ; 22 (0) ; 106 (0) ; |firebee1|altpll_reconfig1:inst7 ; ; -; |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 334 (237) ; 128 (80) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 206 (157) ; 22 (22) ; 106 (57) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ; -; |altsyncram:altsyncram4| ; 0 (0) ; 0 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ; -; |altsyncram_46r:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 144 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ; -; |lpm_compare:cmpr7| ; 3 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 1 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ; -; |cmpr_tnd:auto_generated| ; 3 (3) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated ; ; -; |lpm_counter:cntr12| ; 10 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ; -; |cntr_30l:auto_generated| ; 10 (10) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated ; ; -; |lpm_counter:cntr13| ; 7 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 6 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ; -; |cntr_qij:auto_generated| ; 7 (7) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 6 (6) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated ; ; -; |lpm_counter:cntr14| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ; -; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated ; ; -; |lpm_counter:cntr15| ; 18 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ; -; |cntr_30l:auto_generated| ; 18 (18) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated ; ; -; |lpm_counter:cntr1| ; 41 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ; -; |cntr_30l:auto_generated| ; 41 (41) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated ; ; -; |lpm_counter:cntr2| ; 9 (0) ; 8 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 8 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ; -; |cntr_9cj:auto_generated| ; 9 (9) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 8 (8) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated ; ; -; |lpm_counter:cntr3| ; 5 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ; -; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated ; ; -; |interrupt_handler:nobody| ; 1037 (999) ; 633 (633) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 401 (363) ; 235 (235) ; 401 (355) ; |firebee1|interrupt_handler:nobody ; ; -; |lpm_bustri_BYT:$00000| ; 14 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (0) ; 0 (0) ; 9 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000 ; ; -; |lpm_bustri:lpm_bustri_component| ; 14 (14) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 9 (9) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00002| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 0 (0) ; 8 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002 ; ; -; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 8 (8) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00004| ; 24 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (0) ; 0 (0) ; 14 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004 ; ; -; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 14 (14) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00006| ; 22 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (0) ; 0 (0) ; 15 (0) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006 ; ; -; |lpm_bustri:lpm_bustri_component| ; 22 (22) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 15 (15) ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ; -; |lpm_counter0:inst18| ; 19 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 17 (0) ; |firebee1|lpm_counter0:inst18 ; ; -; |lpm_counter:lpm_counter_component| ; 19 (0) ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 1 (0) ; 17 (0) ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ; -; |cntr_mph:auto_generated| ; 19 (19) ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 17 (17) ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated ; ; -; |lpm_ff0:inst1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|lpm_ff0:inst1 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ; -+-----------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+---------------------------------------------------------------------------------------------------------+ -; Delay Chain Summary ; -+----------------+----------+---------------+---------------+-----------------------+----------+----------+ -; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; -+----------------+----------+---------------+---------------+-----------------------+----------+----------+ -; CLK24M576 ; Output ; -- ; -- ; -- ; -- ; -- ; -; LP_STR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nFB_BURST ; Input ; -- ; -- ; -- ; -- ; -- ; -; nACSI_DRQ ; Input ; -- ; -- ; -- ; -- ; -- ; -; nACSI_INT ; Input ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_DRQ ; Input ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_MSG ; Input ; -- ; -- ; -- ; -- ; -- ; -; nDCHG ; Input ; -- ; -- ; -- ; -- ; -- ; -; SD_DATA0 ; Input ; -- ; -- ; -- ; -- ; -- ; -; SD_DATA1 ; Input ; -- ; -- ; -- ; -- ; -- ; -; SD_DATA2 ; Input ; -- ; -- ; -- ; -- ; -- ; -; SD_CARD_DEDECT ; Input ; -- ; -- ; -- ; -- ; -- ; -; SD_WP ; Input ; -- ; -- ; -- ; -- ; -- ; -; nDACK0 ; Input ; -- ; -- ; -- ; -- ; -- ; -; WP_CF_CARD ; Input ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_C_D ; Input ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_I_O ; Input ; -- ; -- ; -- ; -- ; -- ; -; nFB_CS3 ; Input ; -- ; -- ; -- ; -- ; -- ; -; CLK25M ; Output ; -- ; -- ; -- ; -- ; -- ; -; nACSI_ACK ; Output ; -- ; -- ; -- ; -- ; -- ; -; nACSI_RESET ; Output ; -- ; -- ; -- ; -- ; -- ; -; nACSI_CS ; Output ; -- ; -- ; -- ; -- ; -- ; -; ACSI_DIR ; Output ; -- ; -- ; -- ; -- ; -- ; -; ACSI_A1 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_ACK ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_ATN ; Output ; -- ; -- ; -- ; -- ; -- ; -; SCSI_DIR ; Output ; -- ; -- ; -- ; -- ; -- ; -; MIDI_OLR ; Output ; -- ; -- ; -- ; -- ; -- ; -; MIDI_TLR ; Output ; -- ; -- ; -- ; -- ; -- ; -; TxD ; Output ; -- ; -- ; -- ; -- ; -- ; -; RTS ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; DTR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; AMKB_TX ; Output ; -- ; -- ; -- ; -- ; -- ; -; IDE_RES ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIDE_CS0 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIDE_CS1 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIDE_WR ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIDE_RD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nCF_CS0 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nCF_CS1 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nROM3 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nROM4 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nRP_UDS ; Output ; -- ; -- ; -- ; -- ; -- ; -; nRP_LDS ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSDSEL ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nWR_GATE ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nWR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; YM_QA ; Output ; -- ; -- ; -- ; -- ; -- ; -; YM_QB ; Output ; -- ; -- ; -- ; -- ; -- ; -; YM_QC ; Output ; -- ; -- ; -- ; -- ; -- ; -; SD_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; -; DSA_D ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nVWE ; Output ; -- ; -- ; -- ; -- ; -- ; -; nVCAS ; Output ; -- ; -- ; -- ; -- ; -- ; -; nVRAS ; Output ; -- ; -- ; -- ; -- ; -- ; -; nVCS ; Output ; -- ; -- ; -- ; -- ; -- ; -; nPD_VGA ; Output ; -- ; -- ; -- ; -- ; -- ; -; TIN0 ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSRCS ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSRBLE ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSRBHE ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSRWE ; Output ; -- ; -- ; -- ; -- ; -- ; -; nDREQ1 ; Output ; -- ; -- ; -- ; -- ; -- ; -; LED_FPGA_OK ; Output ; -- ; -- ; -- ; -- ; -- ; -; nSROE ; Output ; -- ; -- ; -- ; -- ; -- ; -; VCKE ; Output ; -- ; -- ; -- ; -- ; -- ; -; nFB_TA ; Output ; -- ; -- ; -- ; -- ; -- ; -; nDDR_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; -; DDR_CLK ; Output ; -- ; -- ; -- ; -- ; -- ; -; VSYNC_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; HSYNC_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nBLANK_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; PIXEL_CLK_PAD ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nSYNC ; Output ; -- ; -- ; -- ; -- ; -- ; -; nMOT_ON ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nSTEP_DIR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nSTEP ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; CLKUSB ; Output ; -- ; -- ; -- ; -- ; -- ; -; LPDIR ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; BA[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; BA[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIRQ[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIRQ[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIRQ[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIRQ[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIRQ[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; nIRQ[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[12] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[11] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[10] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[9] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[8] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[7] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[6] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[5] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[4] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[3] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[2] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[1] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VA[0] ; Output ; -- ; -- ; -- ; -- ; -- ; -; VB[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VB[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VDM[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VDM[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VDM[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VDM[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VG[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[7] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[6] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[5] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[4] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[3] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[2] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[1] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; VR[0] ; Output ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; TOUT0 ; Input ; -- ; -- ; -- ; -- ; -- ; -; nMASTER ; Input ; -- ; -- ; -- ; -- ; -- ; -; FB_AD[31] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[30] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[29] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[28] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[27] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[26] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[25] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[24] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[23] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[22] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[21] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[20] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[19] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[18] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[17] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[16] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[15] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[14] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[13] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[12] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[11] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[10] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[9] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[8] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[7] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[6] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[5] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[4] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[3] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[2] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[1] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; FB_AD[0] ; Bidir ; -- ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -; VD[31] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[30] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[29] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[28] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[27] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[26] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[25] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[24] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[23] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[22] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[21] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[20] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[19] ; Bidir ; (1) 634 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[18] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[17] ; Bidir ; (0) 0 ps ; (1) 634 ps ; -- ; (0) 0 ps ; -- ; -; VD[16] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[15] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[14] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[13] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[12] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[11] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; -; VD[10] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[9] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[8] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[7] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[6] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[5] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[4] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; VD[3] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; -; VD[2] ; Bidir ; (0) 0 ps ; (2) 952 ps ; -- ; (0) 0 ps ; -- ; -; VD[1] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VD[0] ; Bidir ; (2) 952 ps ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; VDQS[3] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; -; VDQS[2] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; -; VDQS[1] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; -; VDQS[0] ; Bidir ; -- ; -- ; -- ; -- ; (0) 0 ps ; -; IO[17] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[16] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[15] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[14] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[13] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[12] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[11] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[10] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[9] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[8] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; IO[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SRD[15] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[14] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[13] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SRD[12] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SRD[11] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SRD[10] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[9] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[8] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[7] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SRD[6] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[5] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SRD[4] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[3] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[2] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SRD[1] ; Bidir ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; SRD[0] ; Bidir ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; SCSI_PAR ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_SEL ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; nSCSI_BUSY ; Bidir ; -- ; -- ; -- ; (0) 0 ps ; -- ; -; nSCSI_RST ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SD_CD_DATA3 ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SD_CMD_D1 ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; ACSI_D[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; LP_D[7] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; LP_D[6] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; LP_D[5] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; LP_D[4] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; LP_D[3] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; LP_D[2] ; Bidir ; -- ; (0) 0 ps ; -- ; (0) 0 ps ; -- ; -; LP_D[1] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; LP_D[0] ; Bidir ; (0) 0 ps ; -- ; -- ; (0) 0 ps ; -- ; -; SCSI_D[7] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[6] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[5] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[4] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[3] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[2] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[1] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; SCSI_D[0] ; Bidir ; -- ; -- ; -- ; -- ; -- ; -; nRSTO_MCF ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; nFB_WR ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; nFB_CS1 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; FB_SIZE1 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; FB_SIZE0 ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; FB_ALE ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; nFB_CS2 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; MAIN_CLK ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; nDACK1 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; nFB_OE ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; IDE_RDY ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; CLK33M ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; HD_DD ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -; nINDEX ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; RxD ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; nWP ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; LP_BUSY ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; DCD ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; CTS ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; TRACK00 ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; IDE_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; RI ; Input ; -- ; (0) 0 ps ; -- ; -- ; -- ; -; nPCI_INTD ; Input ; (6) 2223 ps ; (0) 0 ps ; -- ; -- ; -- ; -; nPCI_INTC ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; -; nPCI_INTB ; Input ; (6) 2223 ps ; (0) 0 ps ; -- ; -- ; -- ; -; nPCI_INTA ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; -; DVI_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; E0_INT ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ; -; PIC_INT ; Input ; (0) 0 ps ; (6) 2223 ps ; -- ; -- ; -- ; -; PIC_AMKB_RX ; Input ; (1) 663 ps ; -- ; -- ; -- ; -- ; -; MIDI_IN ; Input ; -- ; (1) 634 ps ; -- ; -- ; -- ; -; nRD_DATA ; Input ; -- ; -- ; (0) 0 ps ; -- ; -- ; -; AMKB_RX ; Input ; (0) 0 ps ; (0) 0 ps ; -- ; -- ; -- ; -+----------------+----------+---------------+---------------+-----------------------+----------+----------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Pad To Core Delay Chain Fanout ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -; Source Pin / Fanout ; Pad To Core Index ; Setting ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ -; nFB_BURST ; ; ; -; nACSI_DRQ ; ; ; -; nACSI_INT ; ; ; -; nSCSI_DRQ ; ; ; -; nSCSI_MSG ; ; ; -; nDCHG ; ; ; -; SD_DATA0 ; ; ; -; SD_DATA1 ; ; ; -; SD_DATA2 ; ; ; -; SD_CARD_DEDECT ; ; ; -; SD_WP ; ; ; -; nDACK0 ; ; ; -; WP_CF_CARD ; ; ; -; nSCSI_C_D ; ; ; -; nSCSI_I_O ; ; ; -; nFB_CS3 ; ; ; -; TOUT0 ; ; ; -; nMASTER ; ; ; -; FB_AD[31] ; ; ; -; - SRD[15]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[7] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[31] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~32 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[15] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[31] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[15] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[31]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[30] ; ; ; -; - SRD[14]~output ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[30] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[30] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[30]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[14] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[30] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[30] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[30] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[30] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5_RESYN28 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[14]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[30]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[6]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[29] ; ; ; -; - SRD[13]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[29] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[29] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[29]~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[13] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[29] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[29] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[29]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[13]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[29]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[28] ; ; ; -; - SRD[12]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[28] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[28]~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[12] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[12] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[28] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[28] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[28] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[28] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[12] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~6 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[28]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[4]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[12]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[28]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[28]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[27] ; ; ; -; - SRD[11]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[27]~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[27] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[27] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~9 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN20 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[11]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[3]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[27]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[11]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[26] ; ; ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - SRD[10]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[12]~53 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[10] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[10] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[26]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[2] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[26] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[26] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[10]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[10]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[25] ; ; ; -; - SRD[9]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[11]~55 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[9] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[9] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[25]~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[1] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[25] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[25] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[25] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[9]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[25]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[24] ; ; ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7]~22 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - SRD[8]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[10]~58 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[8] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[24]~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[0] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[24] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[24] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[24] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9]~29 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[8]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[8]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[24]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[24]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[8]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[8]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[24]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[24]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24]~feeder ; 1 ; 0 ; -; FB_AD[23] ; ; ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6]~20 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[7]~0 ; 1 ; 0 ; -; - SRD[7]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[9]~60 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~10 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[23]~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[23] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[23] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][5] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][9] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][10] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][14] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][20] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][21] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][23] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][26] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][30] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][32] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][34] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][35] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][37] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][39] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][42] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][46] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][45] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][50] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][52] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][54] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][56] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][58] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][57] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][59] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][61] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][63] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[7] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][0]~73 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][2]~74 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][4]~75 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~10 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[7] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~24 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~24 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][60]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][43]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][53]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][62]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][38]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][11]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][22]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][41]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][27]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][33]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][40]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][17]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][7]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][55]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][51]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][19]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][12]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][47]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][15]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[23]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][49]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][8]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[22] ; ; ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5]~18 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[6]~0 ; 1 ; 0 ; -; - SRD[6]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[8]~62 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22]~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[22] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[6] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[22] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[22] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][5] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][7] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][9] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][11] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][13] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][17] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][21] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][23] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][25] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][33] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][38] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][39] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][41] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][46] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][47] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][50] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][52] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][53] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][55] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][58] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][57] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][59] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][61] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][62] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[6] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][0]~78 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][2]~79 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][4]~80 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[6]~12 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[6] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11]~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~30 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~30 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[6]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][51]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][14]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][43]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][60]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][63]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][42]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][40]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][8]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][32]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][35]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][30]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][15]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][27]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][26]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][37]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][34]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][49]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][45]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][20]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][54]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][56]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][12]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][22]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[6][18]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[6]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[6]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[6]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[22]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[6]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[5]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[21] ; ; ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4]~16 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[5]~1 ; 1 ; 0 ; -; - SRD[5]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[7]~64 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~14 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21]~10 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17 ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[21] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[21] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[21] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[21] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][30] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][17] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][39] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][40] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][43] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][32] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][35] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][47] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][13] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][14] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][12] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][7] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][15] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][58] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][56] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][59] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][52] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][55] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][51] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][60] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][63] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[5] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][2]~82 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][4]~83 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][0]~85 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[5]~15 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[5] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12]~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~36 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~36 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][41]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][8]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][9]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][20]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][42]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][45]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[5]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][57]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][62]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][37]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][46]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][53]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][38]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][33]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][34]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][49]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][10]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][50]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][27]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][54]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][11]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][26]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][21]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][22]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][23]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[5][61]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[20] ; ; ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3]~14 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4]~2 ; 1 ; 0 ; -; - SRD[4]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[6]~66 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20]~11 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18 ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[20] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[20] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[20] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[20] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][39] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][40] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][43] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][32] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][35] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][47] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][30] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][17] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][9] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][13] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][14] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][12] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][7] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][15] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][56] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][59] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][52] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][55] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][51] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][60] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][63] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[4] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][2]~86 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][4]~87 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][0]~89 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[4]~18 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~42 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~42 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13]~27 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[4] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][62]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][58]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[4]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][11]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][20]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][41]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][22]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[4]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][50]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[20]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[20]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][27]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][61]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][38]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][42]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][54]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][57]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][34]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][49]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][53]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][45]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][46]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][10]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][23]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][37]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][33]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][26]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[4]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][8]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[4][21]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[19] ; ; ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2]~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[3]~3 ; 1 ; 0 ; -; - SRD[3]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[5]~68 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~10 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~16 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19]~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19 ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[19] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[19] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][30] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][17] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][39] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][40] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][43] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][32] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][35] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][47] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][13] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][10] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][14] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][8] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][12] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][7] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][15] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][56] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][59] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][52] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][55] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][51] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][60] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][63] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[3] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[3]~21 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][2]~90 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][4]~91 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][0]~93 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~47 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~47 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14]~24 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[19]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[19]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[3]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][38]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][45]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][61]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][53]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][62]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][58]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][27]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][54]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][42]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][57]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][34]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][49]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][26]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][21]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][37]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][33]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][46]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][23]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][11]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][22]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][41]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][20]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][5]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][9]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[3][50]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[3]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[3]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[3]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[18] ; ; ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1]~10 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[2]~4 ; 1 ; 0 ; -; - SRD[2]~output ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[4]~70 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[18] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18]~13 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20 ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[18] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[18] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][5] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][9] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][12] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][13] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][21] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][24] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][26] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][27] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][32] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][33] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][35] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][37] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][39] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][41] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][46] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][50] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][49] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][51] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][54] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][56] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][57] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][59] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][61] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][63] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~6 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0]~1 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][0]~69 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][2]~70 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][4]~71 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[2]~9 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~18 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~18 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15]~21 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[2]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][60]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][45]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][47]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][17]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][30]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][62]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][15]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][40]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][43]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[2]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][53]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][55]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][58]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][38]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][10]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][14]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][34]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][6]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][7]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][23]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][8]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][36]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][42]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][52]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][20]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[2][22]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[2]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[17] ; ; ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[1]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[1] ; 1 ; 0 ; -; - SRD[1]~output ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VCAS~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[3]~72 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~14 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17]~14 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21 ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[17] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[17] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[1] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[17] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[17] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[17] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][5] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][9] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][12] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][13] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][15] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][19] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][21] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][23] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][26] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][27] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][29] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][31] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][34] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][37] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][40] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][42] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][43] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][46] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][47] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][49] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][51] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][53] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][55] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][58] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][60] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][61] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][62] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~7 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~3 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][0]~65 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][2]~66 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][4]~67 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[1]~6 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~12 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16]~18 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[1]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[1]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][59]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][50]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][48]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][8]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][30]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[1]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][20]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][22]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[1]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[1]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[1]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[1]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][56]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][45]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][63]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][44]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][54]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][7]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][17]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][52]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][38]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][10]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][14]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][41]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][57]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][32]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][35]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][24]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][39]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[1][33]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[17]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[1]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[17]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1]~feeder ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[16] ; ; ; -; - Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0]~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[0]~6 ; 1 ; 0 ; -; - SRD[0]~output ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VWE ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[16] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[2]~74 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~16 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16]~15 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[16] ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[0] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][1] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][3] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][5] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][6] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][9] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][10] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][14] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][16] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][18] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][20] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][22] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][24] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][26] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][27] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][28] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][30] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][32] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][34] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][36] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][38] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][40] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][42] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][44] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][46] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][48] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][50] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][52] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][54] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][56] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][58] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][60] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][61] ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][63] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_HIGH[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0]~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][0]~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][2]~3 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][4]~6 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][13]~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A~6 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~15 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8] ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated|aneb_result_wire[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][59]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][12]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][51]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][17]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][7]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][37]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][25]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][29]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][41]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][35]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][15]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[16]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][31]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][57]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][43]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][47]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][23]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][39]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][49]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][33]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][45]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][62]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][53]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][55]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[16]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[0]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][21]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][8]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][19]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[0]~feeder ; 1 ; 0 ; -; FB_AD[15] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[1]~76 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15]~16 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[15] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[15] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[7]~6 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[15]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[14] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA[0]~78 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[14]~17 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[14] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[14] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[6]~7 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[14]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[13] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[1]~9 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[13]~18 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[13] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[13] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[13] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[13] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[5]~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[13]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[12] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~4 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA[0]~11 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[12]~19 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[12] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[12] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[12] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[12] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[12] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[12] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[4]~4 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[12]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[11] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11]~2 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[11]~20 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[11] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[11] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[11] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[11] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[3]~8 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[11]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[10] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10]~21 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[10] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[10] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[2]~5 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[9] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9]~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9]~22 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[9]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[9] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[9] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1]~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[9]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; FB_AD[8] ; ; ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8]~13 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8]~23 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[8]~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[8] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[8] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[8]~feeder ; 1 ; 0 ; -; FB_AD[7] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~16 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7]~24 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[7] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[7] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[7]~4 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[6] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6]~23 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[6]~25 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[6]~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[6] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[6] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[6]~5 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[6]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[5] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5]~26 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[5]~26 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[5] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[5]~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[5] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[5] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~6 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5]~6 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[4] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4]~29 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[4]~27 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[4]~4 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[4] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[4] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[4]~7 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[3] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3]~32 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[3]~28 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[3]~5 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[3] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[3] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~8 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[3]~8 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[3]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[2] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2]~35 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[2]~29 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[2] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[2]~6 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[2] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[2] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2]~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[1] ; ; ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1]~41 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1]~30 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[1] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[1]~7 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[1] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[1] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1]~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1]~feeder ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; FB_AD[0] ; ; ; -; - Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0]~43 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[0]~31 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[0]~8 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[0] ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~5 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[0]~feeder ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0]~feeder ; 1 ; 0 ; -; VD[31] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]~feeder ; 0 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]~feeder ; 0 ; 1 ; -; VD[30] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]~feeder ; 1 ; 1 ; -; VD[29] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]~feeder ; 1 ; 1 ; -; VD[28] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]~feeder ; 1 ; 1 ; -; VD[27] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]~feeder ; 1 ; 1 ; -; VD[26] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]~feeder ; 1 ; 0 ; -; VD[25] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]~feeder ; 0 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]~feeder ; 0 ; 1 ; -; VD[24] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]~feeder ; 1 ; 1 ; -; VD[23] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]~feeder ; 0 ; 0 ; -; VD[22] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]~feeder ; 1 ; 1 ; -; VD[21] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]~feeder ; 1 ; 1 ; -; VD[20] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]~feeder ; 1 ; 1 ; -; VD[19] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]~feeder ; 0 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]~feeder ; 0 ; 1 ; -; VD[18] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]~feeder ; 0 ; 0 ; -; VD[17] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]~feeder ; 1 ; 1 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]~feeder ; 1 ; 1 ; -; VD[16] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]~feeder ; 0 ; 0 ; -; VD[15] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]~feeder ; 0 ; 2 ; -; VD[14] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]~feeder ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]~feeder ; 1 ; 0 ; -; VD[13] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]~feeder ; 0 ; 2 ; -; VD[12] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]~feeder ; 0 ; 2 ; -; VD[11] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]~feeder ; 1 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]~feeder ; 1 ; 2 ; -; VD[10] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]~feeder ; 0 ; 2 ; -; VD[9] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]~feeder ; 0 ; 2 ; -; VD[8] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]~feeder ; 0 ; 0 ; -; VD[7] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]~feeder ; 0 ; 0 ; -; VD[6] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]~feeder ; 0 ; 2 ; -; VD[5] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]~feeder ; 0 ; 0 ; -; VD[4] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]~feeder ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]~feeder ; 0 ; 0 ; -; VD[3] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]~feeder ; 1 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]~feeder ; 1 ; 2 ; -; VD[2] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]~feeder ; 1 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]~feeder ; 1 ; 2 ; -; VD[1] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]~feeder ; 0 ; 2 ; -; VD[0] ; ; ; -; - Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]~feeder ; 0 ; 2 ; -; - Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]~feeder ; 0 ; 2 ; -; VDQS[3] ; ; ; -; VDQS[2] ; ; ; -; VDQS[1] ; ; ; -; VDQS[0] ; ; ; -; IO[17] ; ; ; -; IO[16] ; ; ; -; IO[15] ; ; ; -; IO[14] ; ; ; -; IO[13] ; ; ; -; IO[12] ; ; ; -; IO[11] ; ; ; -; IO[10] ; ; ; -; IO[9] ; ; ; -; IO[8] ; ; ; -; IO[7] ; ; ; -; IO[6] ; ; ; -; IO[5] ; ; ; -; IO[4] ; ; ; -; IO[3] ; ; ; -; IO[2] ; ; ; -; IO[1] ; ; ; -; IO[0] ; ; ; -; SRD[15] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~156 ; 1 ; 0 ; -; SRD[14] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~131 ; 1 ; 0 ; -; SRD[13] ; ; ; -; - DSP:Mathias_Alles|FB_AD[29]~3 ; 0 ; 0 ; -; SRD[12] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~369 ; 0 ; 0 ; -; SRD[11] ; ; ; -; - DSP:Mathias_Alles|FB_AD[27]~4 ; 0 ; 0 ; -; SRD[10] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~197 ; 1 ; 0 ; -; SRD[9] ; ; ; -; - DSP:Mathias_Alles|FB_AD[25]~0 ; 1 ; 0 ; -; SRD[8] ; ; ; -; - DSP:Mathias_Alles|FB_AD[24]~1 ; 1 ; 0 ; -; SRD[7] ; ; ; -; - DSP:Mathias_Alles|FB_AD[23]~2 ; 0 ; 0 ; -; SRD[6] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~269 ; 1 ; 0 ; -; SRD[5] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~285 ; 0 ; 0 ; -; SRD[4] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~301 ; 1 ; 0 ; -; SRD[3] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~319 ; 1 ; 0 ; -; SRD[2] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~172 ; 0 ; 0 ; -; SRD[1] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~86 ; 1 ; 0 ; -; SRD[0] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~54 ; 0 ; 0 ; -; SCSI_PAR ; ; ; -; nSCSI_SEL ; ; ; -; nSCSI_BUSY ; ; ; -; nSCSI_RST ; ; ; -; SD_CD_DATA3 ; ; ; -; SD_CMD_D1 ; ; ; -; ACSI_D[7] ; ; ; -; ACSI_D[6] ; ; ; -; ACSI_D[5] ; ; ; -; ACSI_D[4] ; ; ; -; ACSI_D[3] ; ; ; -; ACSI_D[2] ; ; ; -; ACSI_D[1] ; ; ; -; ACSI_D[0] ; ; ; -; LP_D[7] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~142 ; 1 ; 0 ; -; LP_D[6] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~112 ; 0 ; 0 ; -; LP_D[5] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~339 ; 0 ; 0 ; -; LP_D[4] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~378 ; 0 ; 0 ; -; LP_D[3] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~383 ; 1 ; 0 ; -; LP_D[2] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~186 ; 1 ; 0 ; -; LP_D[1] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~206 ; 0 ; 0 ; -; LP_D[0] ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~227 ; 0 ; 0 ; -; SCSI_D[7] ; ; ; -; SCSI_D[6] ; ; ; -; SCSI_D[5] ; ; ; -; SCSI_D[4] ; ; ; -; SCSI_D[3] ; ; ; -; SCSI_D[2] ; ; ; -; SCSI_D[1] ; ; ; -; SCSI_D[0] ; ; ; -; nRSTO_MCF ; ; ; -; nFB_WR ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SUB_BUS~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 1 ; 0 ; -; - interrupt_handler:nobody|TIN0~0 ; 1 ; 0 ; -; - DSP:Mathias_Alles|nSRWE~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPIO_REGISTERS~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[31]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector0~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~11 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0]~1 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[31]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|Selector1~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRA~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[7]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7]~19 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CONTROL~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATAREG~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~11 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~15 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT_EN~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR_READ~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR_READ~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR_READ~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_EN~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|Mux1~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~2 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DATA_EN~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_EN~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRA~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|ISRB~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[9]~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[8]~1 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[6]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[5]~3 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[4]~4 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[3]~5 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[2]~6 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[1]~7 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR[0]~8 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~4 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~6 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT~5 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~10 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~14 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~15 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|DATA_OUT~17 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~218 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~42 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~238 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|DATA_OUT~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~35 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~37 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|DATA_OUT~40 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~350 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[3]~1 ; 0 ; 0 ; -; - DSP:Mathias_Alles|nSRWE~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[2]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nFDC_WR~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[23]~1 ; 1 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[23]~1 ; 1 ; 0 ; -; - interrupt_handler:nobody|RTC_ADR[5]~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[23]~1 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~491 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[0][0]~1 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][1]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~492 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][3]~5 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~496 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][5]~9 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~503 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~504 ; 1 ; 0 ; -; - interrupt_handler:nobody|_~505 ; 1 ; 0 ; -; - interrupt_handler:nobody|_~506 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][10]~10 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][12]~11 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][13]~13 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][14]~15 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][15]~16 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][16]~17 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][17]~18 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][18]~19 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][19]~20 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][20]~21 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][21]~22 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][22]~23 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][23]~24 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][24]~25 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][25]~26 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][26]~27 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][27]~28 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][28]~29 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][29]~30 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][30]~31 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][31]~32 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][32]~33 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][33]~34 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][34]~35 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][35]~36 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][36]~37 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][37]~38 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][38]~39 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][39]~40 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][40]~41 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][41]~42 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][42]~43 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][43]~44 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][44]~45 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][45]~46 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][46]~47 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][47]~48 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][48]~49 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][49]~50 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][50]~51 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][51]~52 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][52]~53 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][53]~54 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][54]~55 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][55]~56 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][56]~57 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][57]~58 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][58]~59 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][59]~60 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][60]~61 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][61]~62 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][62]~63 ; 0 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][63]~64 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[15]~2 ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[15]~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[31]~3 ; 0 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~4 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[7]~3 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_WR~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_RECONFIG~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|WERTE[7][11]~77 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3 ; 1 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[7]~4 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_2~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4 ; 0 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state~2 ; 1 ; 0 ; -; - altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state~0 ; 1 ; 0 ; -; nFB_CS1 ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|ROM_CS ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_CS ; 0 ; 0 ; -; - interrupt_handler:nobody|TIN0~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE_CS ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT_CS~2 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF_CS ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW_CS~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|UHR_DS~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|MFP_CS~1 ; 1 ; 0 ; -; - interrupt_handler:nobody|_~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|NEXT_CMD_STATE.T1~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector2~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~28 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~32 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~7 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_M ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_H ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~6 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~8 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~36 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~37 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~38 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~39 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~27 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~40 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~41 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[9]~81 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~43 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~38 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~44 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~45 ; 1 ; 0 ; -; - interrupt_handler:nobody|TIN0~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_CNT_L ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~46 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~47 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~48 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~49 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~50 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~51 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~52 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~53 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~54 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~55 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]~7 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~34 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~35 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[2]~36 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_DATEN_CS~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SNDCS ; 1 ; 0 ; -; FB_SIZE1 ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|FB_B[0]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|_~22 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|UHR_AS~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|UHR_DS~6 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~194 ; 1 ; 0 ; -; - interrupt_handler:nobody|FB_B[2]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; 1 ; 0 ; -; FB_SIZE0 ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_UDS~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nRP_LDS~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VRAS~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_B1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_CS~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|FB_B[0]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[1]~0 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[3]~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~22 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~20 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|UHR_AS~0 ; 1 ; 0 ; -; - interrupt_handler:nobody|UHR_DS~6 ; 1 ; 0 ; -; - interrupt_handler:nobody|_~194 ; 1 ; 0 ; -; - interrupt_handler:nobody|FB_B[2]~1 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FB_B[2] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_B[0] ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~491 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2_RESYN22 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~0 ; 0 ; 0 ; -; FB_ALE ; ; ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5 ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; 1 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; 0 ; 0 ; -; - lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~5 ; 1 ; 0 ; -; nFB_CS2 ; ; ; -; - DSP:Mathias_Alles|nSRCS~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_MOD_TA~4 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_RECONFIG_CS~0 ; 0 ; 0 ; -; - inst2~3 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[31]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VIDEO_PLL_CONFIG_CS~0 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_ENA_CS ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CTR_CS ; 0 ; 0 ; -; - interrupt_handler:nobody|_~23 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF_CS ; 0 ; 0 ; -; - interrupt_handler:nobody|_~25 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH_CS ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH_CS ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL_CS ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL_CS ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~3 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR_CS ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~13 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~14 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~147 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~148 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR_CS ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CLEAR_CS ; 0 ; 0 ; -; - interrupt_handler:nobody|_~195 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~196 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~198 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~199 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~200 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~201 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~24 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~25 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~246 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~247 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~35 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~41 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~42 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~248 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~46 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~47 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~295 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~53 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~54 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~338 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~339 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~60 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~61 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~382 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~383 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~67 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~68 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~426 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~427 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~470 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~471 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~473 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~474 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~71 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~475 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~476 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~73 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~74 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~477 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~75 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~76 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~480 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~77 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~78 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~79 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~80 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~483 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~484 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~485 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~486 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~487 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~488 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~489 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~490 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[23]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_CTR[15]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|INT_ENA[15]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[15]~3 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2 ; 0 ; 0 ; -; - interrupt_handler:nobody|ACP_CONF[7]~4 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~508 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[1]~13_RESYN34 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component|dout[0]~15_RESYN42 ; 0 ; 0 ; -; MAIN_CLK ; ; ; -; nDACK1 ; ; ; -; nFB_OE ; ; ; -; - DSP:Mathias_Alles|nSROE~0 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~31 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~39 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~40 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~43 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[0]~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~45 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~47 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~48 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_RD ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_RD ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~51 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[3]~2 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[0]~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~55 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~56 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[1]~4 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_VDOE[2]~5 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~59 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~60 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~61 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~65 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~10 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~67 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~70 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~72 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~77 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[3]~28 ; 1 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[1]~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~85 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[17]~89 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~94 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~19 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~20 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~111 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~124 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD~127 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[30]~129 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDH ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[14]~34 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[15]~40 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~154 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~160 ; 1 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[2]~6 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_RDL~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~170 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~175 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~176 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~179 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~181 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~182 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~193 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~195 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~211 ; 0 ; 0 ; -; - DSP:Mathias_Alles|FB_AD[25]~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~215 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[25]~220 ; 0 ; 0 ; -; - DSP:Mathias_Alles|FB_AD[24]~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~235 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[24]~240 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[7]~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~250 ; 0 ; 0 ; -; - DSP:Mathias_Alles|FB_AD[23]~2 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[23]~255 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[6]~12 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~267 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[22]~272 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[5]~15 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~283 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21]~288 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[4]~18 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~299 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[20]~304 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~308 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~312 ; 0 ; 0 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component|dout[3]~21 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[19]~317 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[15]~327 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~352 ; 0 ; 0 ; -; - DSP:Mathias_Alles|FB_AD[29]~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~356 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[13]~173 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~366 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[28]~375 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~388 ; 1 ; 0 ; -; - DSP:Mathias_Alles|FB_AD[27]~4 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[27]~392 ; 1 ; 0 ; -; - Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[11]~186 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~411 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[9]~415 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~420 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[8]~424 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[7]~432 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[6]~437 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[5]~445 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[4]~453 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[3]~461 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[2]~469 ; 0 ; 0 ; -; - interrupt_handler:nobody|_~508 ; 0 ; 0 ; -; - Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~59 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~490 ; 1 ; 0 ; -; IDE_RDY ; ; ; -; - inst2~1 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector1~0 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IDE_CF_TA~0 ; 1 ; 0 ; -; CLK33M ; ; ; -; HD_DD ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|HD_DD_OUT~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~62 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PHASE_DECODER~0 ; 1 ; 0 ; -; nINDEX ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MOTORSWITCH~2 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~78 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOCK~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~113 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~173 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_COUNTER~2 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ~4 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~205 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DRQ_IPn~0 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_INDEX_MARK:LOCK~0 ; 0 ; 0 ; -; - nINDEX~_wirecell ; 0 ; 0 ; -; RxD ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|SDATA_IN_I~1 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SDATA_IN_I~2 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_SAMPLE~6 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|P_START_BIT~0 ; 0 ; 0 ; -; nWP ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~85 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~168 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~176 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR~0 ; 1 ; 0 ; -; LP_BUSY ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[0]~20 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~15 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~15 ; 0 ; 0 ; -; DCD ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[1]~43 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~10 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~10 ; 0 ; 0 ; -; CTS ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT[2]~63 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~9 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~9 ; 1 ; 0 ; -; TRACK00 ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TR_CLR ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~18 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~20 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~22 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~24 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~26 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~28 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE~103 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~2 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|LOST_DATA_TR00~3 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Add1~30 ; 0 ; 0 ; -; IDE_INT ; ; ; -; RI ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|EDGE_ENA~11 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DATA_OUT~104 ; 1 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|LOCK~11 ; 1 ; 0 ; -; nPCI_INTD ; ; ; -; - interrupt_handler:nobody|INT_LATCH[6]~11 ; 0 ; 6 ; -; - interrupt_handler:nobody|_~484 ; 1 ; 0 ; -; nPCI_INTC ; ; ; -; - interrupt_handler:nobody|INT_LATCH[5]~12 ; 1 ; 6 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[5]~5 ; 0 ; 0 ; -; nPCI_INTB ; ; ; -; - interrupt_handler:nobody|INT_LATCH[4]~13 ; 0 ; 6 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[4]~8 ; 1 ; 0 ; -; nPCI_INTA ; ; ; -; - interrupt_handler:nobody|INT_LATCH[3]~14 ; 1 ; 6 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[3]~11 ; 0 ; 0 ; -; DVI_INT ; ; ; -; E0_INT ; ; ; -; PIC_INT ; ; ; -; - interrupt_handler:nobody|INT_LATCH[0]~17 ; 1 ; 6 ; -; - interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component|dout[0]~20 ; 0 ; 0 ; -; - interrupt_handler:nobody|PIC_INT_SYNC[0] ; 0 ; 0 ; -; PIC_AMKB_RX ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|KEYB_RxD ; 0 ; 1 ; -; MIDI_IN ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RXDATA_I~feeder ; 1 ; 1 ; -; nRD_DATA ; ; ; -; AMKB_RX ; ; ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~11 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2]~9 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1]~7 ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; 0 ; 0 ; -; - FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13 ; 1 ; 0 ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ -; CLK33M ; PIN_AB12 ; 12 ; Clock ; yes ; Global Clock ; GCLK15 ; -- ; -; CLK33M ; PIN_AB12 ; 5 ; Clock ; no ; -- ; -- ; -- ; -; DSP:Mathias_Alles|nSRWE~1 ; LCCOMB_X23_Y8_N20 ; 16 ; Output enable ; no ; -- ; -- ; -- ; -; FB_ALE ; PIN_R7 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13 ; LCCOMB_X1_Y10_N14 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO ; LCCOMB_X26_Y22_N16 ; 250 ; Async. clear ; yes ; Global Clock ; GCLK7 ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[31]~1 ; LCCOMB_X18_Y17_N18 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[0]~1 ; LCCOMB_X22_Y14_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[0]~1 ; LCCOMB_X22_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[1]~0 ; LCCOMB_X16_Y14_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[8]~1 ; LCCOMB_X16_Y14_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[13]~104 ; LCCOMB_X21_Y12_N8 ; 16 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[16]~78 ; LCCOMB_X22_Y13_N12 ; 2 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~183 ; LCCOMB_X22_Y13_N30 ; 4 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~259 ; LCCOMB_X22_Y13_N4 ; 2 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~203 ; LCCOMB_X22_Y13_N16 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[26]~224 ; LCCOMB_X22_Y13_N10 ; 2 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[31]~141 ; LCCOMB_X33_Y1_N4 ; 5 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|Selector4~1 ; LCCOMB_X23_Y18_N0 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WDC_BSL[0]~1 ; LCCOMB_X22_Y13_N2 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|Equal0~4 ; LCCOMB_X22_Y28_N30 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4]~1 ; LCCOMB_X21_Y28_N6 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4]~3 ; LCCOMB_X21_Y28_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SHFT ; FF_X34_Y29_N7 ; 26 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SHFT_LOAD_ND~0 ; LCCOMB_X28_Y27_N8 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47 ; LCCOMB_X35_Y25_N2 ; 88 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector78~0 ; LCCOMB_X32_Y25_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor2~5 ; LCCOMB_X36_Y28_N0 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WideNor8 ; LCCOMB_X28_Y27_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2]~1 ; LCCOMB_X32_Y27_N4 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5]~37 ; LCCOMB_X27_Y26_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT~27 ; LCCOMB_X30_Y30_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE ; FF_X30_Y32_N13 ; 18 ; Clock enable, Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1]~1 ; LCCOMB_X27_Y32_N24 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7] ; FF_X32_Y25_N31 ; 20 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7]~1 ; LCCOMB_X32_Y25_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|Equal3~2 ; LCCOMB_X27_Y25_N14 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTORREG~1 ; LCCOMB_X29_Y25_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6]~9 ; LCCOMB_X28_Y27_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG~8 ; LCCOMB_X30_Y28_N22 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACKREG~1 ; LCCOMB_X30_Y26_N20 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6]~3 ; LCCOMB_X30_Y26_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT~1 ; LCCOMB_X28_Y30_N28 ; 31 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT~12 ; LCCOMB_X36_Y29_N10 ; 4 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK~0 ; LCCOMB_X25_Y29_N26 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0]~0 ; LCCOMB_X25_Y27_N6 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADDRESSLATCH~1 ; LCCOMB_X18_Y19_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DIG_PORTS~0 ; LCCOMB_X15_Y14_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_A[6]~_Duplicate_1 ; FF_X4_Y41_N5 ; 8 ; Output enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|PORT_B[7]~0 ; LCCOMB_X7_Y39_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|P_CTRL_REG~0 ; LCCOMB_X19_Y23_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WAV_STRB ; FF_X9_Y21_N23 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_FREQ[7]~0 ; LCCOMB_X17_Y22_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET ; FF_X18_Y22_N21 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_RESET~0 ; LCCOMB_X18_Y22_N20 ; 9 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_SHAPE[2]~0 ; LCCOMB_X18_Y24_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|ENV_STRB~1 ; LCCOMB_X18_Y23_N8 ; 19 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal14~3 ; LCCOMB_X20_Y21_N28 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal16~3 ; LCCOMB_X19_Y24_N20 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|Equal18~3 ; LCCOMB_X18_Y20_N28 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[11]~0 ; LCCOMB_X15_Y14_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_A[7]~1 ; LCCOMB_X20_Y23_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[11]~0 ; LCCOMB_X19_Y24_N30 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[7]~1 ; LCCOMB_X20_Y20_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[11]~0 ; LCCOMB_X18_Y20_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_C[7]~1 ; LCCOMB_X17_Y18_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_A[4]~0 ; LCCOMB_X17_Y25_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_B[4]~0 ; LCCOMB_X20_Y22_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[4]~0 ; LCCOMB_X21_Y27_N0 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_FREQ[4]~0 ; LCCOMB_X17_Y19_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|OSC_A_OUT~1 ; LCCOMB_X17_Y25_N24 ; 39 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3]~12 ; LCCOMB_X18_Y25_N10 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0]~0 ; LCCOMB_X16_Y24_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0]~0 ; LCCOMB_X16_Y24_N6 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16]~2 ; LCCOMB_X16_Y24_N24 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7]~0 ; LCCOMB_X6_Y18_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1 ; LCCOMB_X4_Y19_N12 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0]~1 ; LCCOMB_X5_Y18_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0 ; LCCOMB_X2_Y21_N28 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4]~1 ; LCCOMB_X5_Y17_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5]~1 ; LCCOMB_X1_Y18_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1 ; LCCOMB_X1_Y19_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2]~1 ; LCCOMB_X3_Y19_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6]~1 ; LCCOMB_X2_Y19_N2 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE ; FF_X1_Y20_N15 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4]~3 ; LCCOMB_X1_Y20_N26 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2]~1 ; LCCOMB_X7_Y18_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT~1 ; LCCOMB_X4_Y19_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2]~1 ; LCCOMB_X5_Y16_N14 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE~0 ; LCCOMB_X3_Y17_N26 ; 6 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0]~1 ; LCCOMB_X4_Y17_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4]~1 ; LCCOMB_X3_Y17_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT~1 ; LCCOMB_X5_Y20_N0 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0]~1 ; LCCOMB_X4_Y21_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4]~1 ; LCCOMB_X5_Y21_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.IDLE ; FF_X6_Y19_N27 ; 12 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2]~1 ; LCCOMB_X6_Y19_N28 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|AER[0]~0 ; LCCOMB_X14_Y18_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|DDR[0]~0 ; LCCOMB_X14_Y14_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO|GPDR[0]~0 ; LCCOMB_X14_Y15_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERA[0]~0 ; LCCOMB_X14_Y16_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IERB[0]~0 ; LCCOMB_X14_Y16_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRA[0]~0 ; LCCOMB_X16_Y19_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[0]~0 ; LCCOMB_X16_Y19_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[9]~5 ; LCCOMB_X17_Y21_N4 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.REQUEST ; FF_X16_Y17_N3 ; 23 ; Sync. clear ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[0]~7 ; LCCOMB_X17_Y17_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VR[7]~0 ; LCCOMB_X16_Y16_N4 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_A~0 ; LCCOMB_X6_Y20_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_B~0 ; LCCOMB_X6_Y20_N8 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_C~0 ; LCCOMB_X3_Y20_N0 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|PRESCALE_D~0 ; LCCOMB_X9_Y17_N6 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[0]~0 ; LCCOMB_X12_Y16_N22 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TADR[0]~0 ; LCCOMB_X8_Y20_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[0]~0 ; LCCOMB_X10_Y18_N30 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBDR[0]~0 ; LCCOMB_X7_Y17_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[0]~0 ; LCCOMB_X12_Y18_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDR[0]~0 ; LCCOMB_X10_Y15_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TDDR[3]~0 ; LCCOMB_X4_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERC~1 ; LCCOMB_X10_Y15_N2 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMERD~1 ; LCCOMB_X3_Y15_N4 ; 9 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[0]~0 ; LCCOMB_X10_Y18_N16 ; 10 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[0]~3 ; LCCOMB_X12_Y17_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[0]~1 ; LCCOMB_X11_Y18_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[0]~1 ; LCCOMB_X11_Y18_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|XTAL_STRB ; FF_X3_Y20_N7 ; 44 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|RSR[1]~0 ; LCCOMB_X14_Y19_N26 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|SCR[0]~0 ; LCCOMB_X14_Y22_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|TSR[0]~1 ; LCCOMB_X14_Y19_N24 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3]~0 ; LCCOMB_X12_Y16_N8 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[7] ; FF_X14_Y20_N1 ; 19 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[7]~3 ; LCCOMB_X11_Y19_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0]~2 ; LCCOMB_X10_Y24_N14 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6]~1 ; LCCOMB_X10_Y22_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[0]~0 ; LCCOMB_X3_Y27_N20 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT~1 ; LCCOMB_X14_Y23_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|CLK_STRB ; FF_X2_Y27_N7 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFTREG~0 ; LCCOMB_X12_Y21_N12 ; 7 ; Sync. load ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1]~8 ; LCCOMB_X12_Y23_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TX_END ; FF_X12_Y23_N17 ; 17 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|_~0 ; LCCOMB_X21_Y9_N28 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1 ; LCCOMB_X23_Y7_N18 ; 20 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_wrreq~1 ; LCCOMB_X18_Y18_N20 ; 18 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|_~0 ; LCCOMB_X22_Y22_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_rdreq~1 ; LCCOMB_X22_Y22_N4 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|valid_wrreq~0 ; LCCOMB_X26_Y24_N4 ; 22 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_10~0 ; LCCOMB_X20_Y16_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_11~0 ; LCCOMB_X20_Y16_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 ; LCCOMB_X26_Y22_N14 ; 32 ; Async. clear ; yes ; Global Clock ; GCLK5 ; -- ; -; MAIN_CLK ; PIN_G2 ; 2272 ; Clock ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT ; FF_X23_Y12_N17 ; 26 ; Sync. load ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3]~1 ; LCCOMB_X27_Y6_N0 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[0]~4 ; LCCOMB_X22_Y2_N22 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[1]~2 ; LCCOMB_X34_Y2_N8 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[2]~3 ; LCCOMB_X21_Y4_N10 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_LE[3] ; LCCOMB_X34_Y2_N24 ; 32 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22]~40 ; LCCOMB_X26_Y8_N24 ; 23 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_H_D[7]~0 ; LCCOMB_X26_Y11_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[7]~0 ; LCCOMB_X26_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7]~0 ; LCCOMB_X25_Y11_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2]~0 ; LCCOMB_X23_Y11_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[1] ; LCCOMB_X25_Y16_N22 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[2] ; LCCOMB_X25_Y14_N26 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_CLUT_WR[3] ; LCCOMB_X25_Y16_N0 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15]~3 ; LCCOMB_X22_Y19_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[23]~0 ; LCCOMB_X23_Y12_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[31]~2 ; LCCOMB_X27_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5]~1 ; LCCOMB_X23_Y18_N22 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]~6 ; LCCOMB_X28_Y18_N22 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[15]~1 ; LCCOMB_X21_Y19_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[23]~0 ; LCCOMB_X29_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[31]~2 ; LCCOMB_X23_Y14_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7]~3 ; LCCOMB_X23_Y14_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15]~1 ; LCCOMB_X23_Y19_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23]~0 ; LCCOMB_X28_Y15_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[31]~2 ; LCCOMB_X25_Y17_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7]~3 ; LCCOMB_X22_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[15]~1 ; LCCOMB_X21_Y19_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[23]~0 ; LCCOMB_X28_Y15_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31]~2 ; LCCOMB_X28_Y17_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7]~3 ; LCCOMB_X28_Y17_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[15]~1 ; LCCOMB_X23_Y19_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[23]~0 ; LCCOMB_X29_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[31]~2 ; LCCOMB_X25_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7]~3 ; LCCOMB_X25_Y17_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15]~1 ; LCCOMB_X22_Y18_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23]~0 ; LCCOMB_X29_Y18_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7]~2 ; LCCOMB_X23_Y18_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; FF_X33_Y18_N13 ; 54 ; Sync. load ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; FF_X33_Y18_N15 ; 54 ; Sync. clear ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; FF_X29_Y21_N3 ; 34 ; Async. clear ; yes ; Global Clock ; GCLK11 ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_FIFO_CLR ; FF_X36_Y17_N25 ; 21 ; Async. clear ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[0] ; LCCOMB_X23_Y16_N24 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[1] ; LCCOMB_X23_Y16_N8 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_CLUT_WR[3] ; LCCOMB_X23_Y16_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[10]~3 ; LCCOMB_X28_Y16_N22 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7]~1 ; LCCOMB_X28_Y16_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; FF_X37_Y20_N27 ; 141 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; FF_X33_Y12_N25 ; 30 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 3 ; Clock ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 850 ; Clock ; yes ; Global Clock ; GCLK6 ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[0] ; LCCOMB_X26_Y13_N18 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_CLUT_WR[1] ; LCCOMB_X21_Y13_N14 ; 1 ; Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[1]~0 ; LCCOMB_X29_Y17_N18 ; 2 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[6]~7 ; LCCOMB_X35_Y17_N16 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX ; FF_X34_Y14_N13 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYS_CTR[6]~0 ; LCCOMB_X26_Y16_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11]~1 ; LCCOMB_X30_Y13_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7]~0 ; LCCOMB_X30_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11]~1 ; LCCOMB_X30_Y10_N2 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7]~0 ; LCCOMB_X29_Y10_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11]~1 ; LCCOMB_X30_Y10_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7]~0 ; LCCOMB_X29_Y10_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11]~1 ; LCCOMB_X33_Y13_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7]~0 ; LCCOMB_X33_Y13_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11]~1 ; LCCOMB_X30_Y12_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7]~0 ; LCCOMB_X30_Y12_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11]~1 ; LCCOMB_X29_Y14_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7]~0 ; LCCOMB_X26_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[15]~1 ; LCCOMB_X26_Y17_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LOF[7]~0 ; LCCOMB_X27_Y15_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[15]~3 ; LCCOMB_X26_Y17_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_LWD[7]~2 ; LCCOMB_X26_Y15_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[10]~1 ; LCCOMB_X30_Y15_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[7]~0 ; LCCOMB_X29_Y15_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10]~1 ; LCCOMB_X25_Y13_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[7]~0 ; LCCOMB_X30_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[7]~0 ; LCCOMB_X26_Y18_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[8]~1 ; LCCOMB_X26_Y13_N20 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10]~1 ; LCCOMB_X29_Y14_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7]~0 ; LCCOMB_X29_Y13_N4 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10]~1 ; LCCOMB_X30_Y15_N30 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[7]~0 ; LCCOMB_X29_Y16_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10]~1 ; LCCOMB_X26_Y14_N6 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7]~0 ; LCCOMB_X27_Y16_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[3]~0 ; LCCOMB_X25_Y18_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10]~1 ; LCCOMB_X27_Y18_N20 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7]~0 ; LCCOMB_X26_Y16_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7]~3 ; LCCOMB_X27_Y18_N6 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~92 ; LCCOMB_X28_Y20_N4 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst37 ; LCCOMB_X66_Y4_N2 ; 32 ; Output enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst65~0 ; LCCOMB_X37_Y20_N28 ; 34 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst67 ; LCCOMB_X37_Y17_N12 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst90 ; DDIOOECELL_X63_Y0_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; DDIOOECELL_X67_Y11_N12 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; DDIOOECELL_X52_Y0_N26 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; DDIOOECELL_X43_Y0_N19 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|inst95 ; FF_X39_Y18_N21 ; 128 ; Sync. load ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|_~0 ; LCCOMB_X36_Y20_N2 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21 ; 72 ; Async. clear ; yes ; Global Clock ; GCLK9 ; -- ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0 ; LCCOMB_X57_Y17_N14 ; 14 ; Clock enable, Write enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; FF_X45_Y15_N1 ; 258 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; FF_X18_Y13_N29 ; 64 ; Clock enable ; no ; -- ; -- ; -- ; -; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; FF_X18_Y13_N3 ; 33 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; PLL_3 ; 52 ; Clock ; yes ; Global Clock ; GCLK14 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; PLL_1 ; 691 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; PLL_1 ; 96 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; PLL_1 ; 5 ; Clock ; yes ; Global Clock ; GCLK0 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; PLL_1 ; 41 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; PLL_1 ; 189 ; Clock, Latch enable ; yes ; Global Clock ; GCLK4 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; PLL_4 ; 7 ; Clock ; yes ; Global Clock ; GCLK16 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; PLL_4 ; 585 ; Clock ; yes ; Global Clock ; GCLK17 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; PLL_4 ; 4 ; Clock ; yes ; Global Clock ; GCLK18 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; PLL_4 ; 2 ; Clock ; yes ; Global Clock ; GCLK19 ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|_~1 ; LCCOMB_X23_Y26_N8 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|busy ; LCCOMB_X22_Y25_N2 ; 15 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|input_latch_enable~0 ; LCCOMB_X22_Y26_N10 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X14_Y25_N0 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|_~0 ; LCCOMB_X19_Y28_N4 ; 14 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X21_Y29_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|_~9 ; LCCOMB_X21_Y27_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7]~0 ; LCCOMB_X18_Y29_N18 ; 8 ; Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|_~0 ; LCCOMB_X21_Y26_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~4 ; LCCOMB_X21_Y26_N10 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|power_up~5 ; LCCOMB_X21_Y27_N12 ; 5 ; Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~0 ; LCCOMB_X21_Y29_N6 ; 16 ; Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state~1 ; LCCOMB_X18_Y29_N24 ; 13 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state ; FF_X22_Y29_N31 ; 13 ; Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|scan_cache_write_enable~0 ; LCCOMB_X20_Y26_N4 ; 3 ; Write enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17]~3 ; LCCOMB_X22_Y23_N2 ; 18 ; Clock enable ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg_clear~0 ; LCCOMB_X22_Y27_N28 ; 35 ; Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state ; FF_X21_Y25_N29 ; 10 ; Sync. load ; no ; -- ; -- ; -- ; -; inst25 ; LCCOMB_X15_Y23_N20 ; 1027 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK10 ; -- ; -; inst25 ; LCCOMB_X15_Y23_N20 ; 119 ; Clock enable, Sync. clear, Sync. load ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|ACHTELSEKUNDEN[2]~0 ; LCCOMB_X1_Y13_N6 ; 4 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|ACP_CONF[15]~3 ; LCCOMB_X16_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|ACP_CONF[23]~1 ; LCCOMB_X11_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|ACP_CONF[31]~0 ; LCCOMB_X16_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|ACP_CONF[7]~4 ; LCCOMB_X15_Y11_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[0] ; FF_X17_Y10_N9 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[1] ; FF_X17_Y10_N31 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[2] ; FF_X17_Y10_N1 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[3] ; FF_X17_Y10_N23 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[4] ; FF_X17_Y10_N21 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[5] ; FF_X17_Y10_N11 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[6] ; FF_X17_Y10_N25 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[8] ; FF_X17_Y10_N15 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CLEAR[9] ; FF_X17_Y10_N29 ; 1 ; Async. clear ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CTR[15]~2 ; LCCOMB_X15_Y15_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CTR[23]~1 ; LCCOMB_X12_Y11_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CTR[31]~3 ; LCCOMB_X18_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_CTR[7]~0 ; LCCOMB_X15_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_ENA[15]~2 ; LCCOMB_X15_Y15_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_ENA[23]~1 ; LCCOMB_X12_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_ENA[31]~0 ; LCCOMB_X16_Y13_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_ENA[7]~3 ; LCCOMB_X15_Y13_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[0]~26 ; LCCOMB_X14_Y13_N30 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[1]~25 ; LCCOMB_X15_Y11_N22 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[2]~24 ; LCCOMB_X15_Y11_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[3]~23 ; LCCOMB_X15_Y10_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[4]~22 ; LCCOMB_X14_Y13_N20 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[5]~21 ; LCCOMB_X15_Y11_N0 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[6]~20 ; LCCOMB_X15_Y12_N26 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[8]~19 ; LCCOMB_X15_Y15_N6 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|INT_LATCH[9]~18 ; LCCOMB_X15_Y15_N16 ; 1 ; Clock ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|RTC_ADR[5]~0 ; LCCOMB_X8_Y12_N24 ; 6 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[0][0]~1 ; LCCOMB_X6_Y15_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[0][13]~14 ; LCCOMB_X4_Y14_N22 ; 1 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[0][2]~4 ; LCCOMB_X7_Y15_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][10]~10 ; LCCOMB_X7_Y14_N4 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][11]~77 ; LCCOMB_X1_Y13_N26 ; 5 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][12]~11 ; LCCOMB_X8_Y13_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][13]~13 ; LCCOMB_X6_Y14_N18 ; 7 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][14]~15 ; LCCOMB_X7_Y14_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][15]~16 ; LCCOMB_X11_Y13_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][16]~17 ; LCCOMB_X4_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][17]~18 ; LCCOMB_X3_Y11_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][18]~19 ; LCCOMB_X2_Y14_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][19]~20 ; LCCOMB_X2_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][1]~2 ; LCCOMB_X7_Y13_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][20]~21 ; LCCOMB_X2_Y13_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][21]~22 ; LCCOMB_X3_Y14_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][22]~23 ; LCCOMB_X2_Y14_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][23]~24 ; LCCOMB_X3_Y10_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][24]~25 ; LCCOMB_X3_Y10_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][25]~26 ; LCCOMB_X2_Y12_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][26]~27 ; LCCOMB_X2_Y12_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][27]~28 ; LCCOMB_X4_Y9_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][28]~29 ; LCCOMB_X4_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][29]~30 ; LCCOMB_X3_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][30]~31 ; LCCOMB_X3_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][31]~32 ; LCCOMB_X5_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][32]~33 ; LCCOMB_X4_Y10_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][33]~34 ; LCCOMB_X8_Y10_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][34]~35 ; LCCOMB_X8_Y10_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][35]~36 ; LCCOMB_X4_Y10_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][36]~37 ; LCCOMB_X2_Y10_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][37]~38 ; LCCOMB_X2_Y10_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][38]~39 ; LCCOMB_X7_Y10_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][39]~40 ; LCCOMB_X4_Y10_N2 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][3]~5 ; LCCOMB_X6_Y13_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][40]~41 ; LCCOMB_X6_Y9_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][41]~42 ; LCCOMB_X5_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][42]~43 ; LCCOMB_X6_Y9_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][43]~44 ; LCCOMB_X9_Y11_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][44]~45 ; LCCOMB_X10_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][45]~46 ; LCCOMB_X10_Y10_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][46]~47 ; LCCOMB_X10_Y10_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][47]~48 ; LCCOMB_X9_Y13_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][48]~49 ; LCCOMB_X9_Y13_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][49]~50 ; LCCOMB_X9_Y10_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][50]~51 ; LCCOMB_X9_Y10_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][51]~52 ; LCCOMB_X8_Y9_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][52]~53 ; LCCOMB_X7_Y9_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][53]~54 ; LCCOMB_X11_Y9_N14 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][54]~55 ; LCCOMB_X10_Y9_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][55]~56 ; LCCOMB_X10_Y11_N20 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][56]~57 ; LCCOMB_X10_Y9_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][57]~58 ; LCCOMB_X8_Y12_N8 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][58]~59 ; LCCOMB_X8_Y12_N10 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][59]~60 ; LCCOMB_X9_Y12_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][5]~9 ; LCCOMB_X6_Y14_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][60]~61 ; LCCOMB_X5_Y12_N26 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][61]~62 ; LCCOMB_X5_Y12_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][62]~63 ; LCCOMB_X12_Y12_N16 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|WERTE[7][63]~64 ; LCCOMB_X11_Y12_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|_~503 ; LCCOMB_X6_Y11_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|_~504 ; LCCOMB_X5_Y11_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|_~505 ; LCCOMB_X4_Y14_N28 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -; interrupt_handler:nobody|_~506 ; LCCOMB_X7_Y13_N22 ; 8 ; Clock enable ; no ; -- ; -- ; -- ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------+---------+---------------------------------------+--------+----------------------+------------------+---------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; -+---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ -; CLK33M ; PIN_AB12 ; 12 ; 0 ; Global Clock ; GCLK15 ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO ; LCCOMB_X26_Y22_N16 ; 250 ; 0 ; Global Clock ; GCLK7 ; -- ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 ; LCCOMB_X26_Y22_N14 ; 32 ; 0 ; Global Clock ; GCLK5 ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; FF_X29_Y21_N3 ; 34 ; 0 ; Global Clock ; GCLK11 ; -- ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK ; LCCOMB_X26_Y18_N4 ; 850 ; 0 ; Global Clock ; GCLK6 ; -- ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; FF_X57_Y17_N21 ; 72 ; 0 ; Global Clock ; GCLK9 ; -- ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; PLL_3 ; 52 ; 0 ; Global Clock ; GCLK14 ; -- ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; PLL_3 ; 1 ; 0 ; Global Clock ; GCLK12 ; -- ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; PLL_3 ; 1 ; 0 ; Global Clock ; GCLK13 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; PLL_1 ; 691 ; 0 ; Global Clock ; GCLK3 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; PLL_1 ; 96 ; 0 ; Global Clock ; GCLK1 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; PLL_1 ; 5 ; 0 ; Global Clock ; GCLK0 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; PLL_1 ; 41 ; 0 ; Global Clock ; GCLK2 ; -- ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; PLL_1 ; 189 ; 0 ; Global Clock ; GCLK4 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; PLL_4 ; 7 ; 0 ; Global Clock ; GCLK16 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; PLL_4 ; 585 ; 0 ; Global Clock ; GCLK17 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; PLL_4 ; 4 ; 0 ; Global Clock ; GCLK18 ; -- ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; PLL_4 ; 2 ; 0 ; Global Clock ; GCLK19 ; -- ; -; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; PLL_2 ; 1 ; 0 ; Global Clock ; GCLK8 ; -- ; -; inst25 ; LCCOMB_X15_Y23_N20 ; 1027 ; 0 ; Global Clock ; GCLK10 ; -- ; -+---------------------------------------------------------------------------------------------------------------------------+--------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Non-Global High Fan-Out Signals ; -+-----------------------------------------------------------------------------------------------------------------------------------+---------+ -; Name ; Fan-Out ; -+-----------------------------------------------------------------------------------------------------------------------------------+---------+ -; MAIN_CLK~input ; 2272 ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; 385 ; -; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; 258 ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; 257 ; -; nFB_WR~input ; 235 ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; 225 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; 208 ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; 161 ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; 158 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; 156 ; -; FB_AD[17]~input ; 145 ; -; FB_AD[18]~input ; 145 ; -; FB_AD[20]~input ; 144 ; -; FB_AD[16]~input ; 143 ; -; FB_AD[19]~input ; 143 ; -; FB_AD[21]~input ; 143 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; 141 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; 141 ; -; FB_AD[22]~input ; 140 ; -; FB_AD[23]~input ; 137 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; 132 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; 132 ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; 129 ; -; Video:Fredi_Aschwanden|inst95 ; 128 ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; 120 ; -; inst25 ; 118 ; -; nFB_OE~input ; 101 ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; 97 ; -; nFB_CS2~input ; 95 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector68~47 ; 88 ; -; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; 83 ; -; interrupt_handler:nobody|RTC_ADR[4] ; 80 ; -; interrupt_handler:nobody|RTC_ADR[5] ; 79 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ROLL_OVER ; 78 ; -; interrupt_handler:nobody|UHR_DS~5 ; 71 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1 ; 68 ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; 66 ; -; interrupt_handler:nobody|UHR_DS~6 ; 66 ; -; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; 65 ; -; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; 64 ; -; FB_AD[24]~input ; 63 ; -; interrupt_handler:nobody|RTC_ADR[3] ; 62 ; -; interrupt_handler:nobody|RTC_ADR[2] ; 62 ; -; interrupt_handler:nobody|RTC_ADR[1] ; 62 ; -; interrupt_handler:nobody|RTC_ADR[0] ; 62 ; -; ~GND ; 61 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; 60 ; -; nFB_CS1~input ; 59 ; -; FB_AD[25]~input ; 59 ; -; FB_AD[26]~input ; 57 ; -+-----------------------------------------------------------------------------------------------------------------------------------+---------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter RAM Summary ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ -; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 1024 ; 8 ; 256 ; 32 ; yes ; no ; yes ; yes ; 8192 ; 1024 ; 8 ; 256 ; 32 ; 8192 ; 1 ; None ; M9K_X24_Y11_N0 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 256 ; 32 ; 1024 ; 8 ; yes ; no ; yes ; yes ; 8192 ; 256 ; 32 ; 1024 ; 8 ; 8192 ; 1 ; None ; M9K_X24_Y21_N0 ; -; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y15_N0 ; -; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y15_N0 ; -; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 16 ; 3 ; 16 ; 3 ; yes ; yes ; yes ; yes ; 48 ; 16 ; 3 ; 16 ; 3 ; 48 ; 1 ; None ; M9K_X24_Y13_N0 ; -; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y20_N0 ; -; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y19_N0 ; -; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 6 ; 256 ; 6 ; yes ; yes ; yes ; yes ; 1536 ; 256 ; 6 ; 256 ; 6 ; 1536 ; 1 ; None ; M9K_X24_Y17_N0 ; -; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y14_N0 ; -; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y16_N0 ; -; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; Dual Clocks ; 256 ; 8 ; 256 ; 8 ; yes ; yes ; yes ; yes ; 2048 ; 256 ; 8 ; 256 ; 8 ; 2048 ; 1 ; None ; M9K_X24_Y18_N0 ; -; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 128 ; 128 ; 128 ; 128 ; yes ; no ; yes ; no ; 16384 ; 128 ; 128 ; 128 ; 128 ; 16384 ; 4 ; None ; M9K_X40_Y19_N0, M9K_X40_Y20_N0, M9K_X40_Y21_N0, M9K_X40_Y22_N0 ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 512 ; 128 ; 512 ; 128 ; yes ; no ; yes ; yes ; 65536 ; 512 ; 128 ; 512 ; 128 ; 65536 ; 8 ; None ; M9K_X40_Y16_N0, M9K_X40_Y15_N0, M9K_X58_Y16_N0, M9K_X58_Y17_N0, M9K_X40_Y17_N0, M9K_X40_Y14_N0, M9K_X40_Y13_N0, M9K_X40_Y18_N0 ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; Single Clock ; 144 ; 1 ; -- ; -- ; yes ; no ; -- ; -- ; 144 ; 144 ; 1 ; -- ; -- ; 144 ; 1 ; None ; M9K_X24_Y25_N0 ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------+ -Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. - - -+-----------------------------------------------------------------------------------------------+ -; Fitter DSP Block Usage Summary ; -+---------------------------------------+-------------+---------------------+-------------------+ -; Statistic ; Number Used ; Available per Block ; Maximum Available ; -+---------------------------------------+-------------+---------------------+-------------------+ -; Simple Multipliers (9-bit) ; 0 ; 2 ; 252 ; -; Simple Multipliers (18-bit) ; 3 ; 1 ; 126 ; -; Embedded Multiplier Blocks ; 3 ; -- ; 126 ; -; Embedded Multiplier 9-bit elements ; 6 ; 2 ; 252 ; -; Signed Embedded Multipliers ; 0 ; -- ; -- ; -; Unsigned Embedded Multipliers ; 3 ; -- ; -- ; -; Mixed Sign Embedded Multipliers ; 0 ; -- ; -- ; -; Variable Sign Embedded Multipliers ; 0 ; -- ; -- ; -; Dedicated Input Shift Register Chains ; 0 ; -- ; -- ; -+---------------------------------------+-------------+---------------------+-------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; DSP Block Details ; -+------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ -; Name ; Mode ; Location ; Sign Representation ; Has Input Shift Register Chain ; Data A Input Register ; Data B Input Register ; Pipeline Register ; Output Register ; -+------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y14_N2 ; ; No ; ; ; ; no ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y14_N0 ; Unsigned ; ; no ; no ; no ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y10_N2 ; ; No ; ; ; ; no ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y10_N0 ; Unsigned ; ; no ; no ; no ; ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_out2 ; Simple Multiplier (18-bit) ; DSPOUT_X31_Y12_N2 ; ; No ; ; ; ; no ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated|mac_mult1 ; ; DSPMULT_X31_Y12_N0 ; Unsigned ; ; no ; no ; no ; ; -+------------------------------------------------------------------------------------------------------------------------+----------------------------+--------------------+---------------------+--------------------------------+-----------------------+-----------------------+-------------------+-----------------+ - - -+--------------------------------------------------------+ -; Interconnect Usage Summary ; -+----------------------------+---------------------------+ -; Interconnect Resource Type ; Usage ; -+----------------------------+---------------------------+ -; Block interconnects ; 16,358 / 116,715 ( 14 % ) ; -; C16 interconnects ; 749 / 3,886 ( 19 % ) ; -; C4 interconnects ; 10,626 / 73,752 ( 14 % ) ; -; Direct links ; 2,046 / 116,715 ( 2 % ) ; -; Global clocks ; 20 / 20 ( 100 % ) ; -; Local interconnects ; 4,734 / 39,600 ( 12 % ) ; -; R24 interconnects ; 882 / 3,777 ( 23 % ) ; -; R4 interconnects ; 11,442 / 99,858 ( 11 % ) ; -+----------------------------+---------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Logic Elements ; -+---------------------------------------------+-------------------------------+ -; Number of Logic Elements (Average = 12.60) ; Number of LABs (Total = 756) ; -+---------------------------------------------+-------------------------------+ -; 1 ; 41 ; -; 2 ; 20 ; -; 3 ; 22 ; -; 4 ; 11 ; -; 5 ; 13 ; -; 6 ; 12 ; -; 7 ; 15 ; -; 8 ; 13 ; -; 9 ; 13 ; -; 10 ; 30 ; -; 11 ; 23 ; -; 12 ; 32 ; -; 13 ; 29 ; -; 14 ; 47 ; -; 15 ; 59 ; -; 16 ; 376 ; -+---------------------------------------------+-------------------------------+ - - -+--------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+-------------------------------+ -; LAB-wide Signals (Average = 1.78) ; Number of LABs (Total = 756) ; -+------------------------------------+-------------------------------+ -; 1 Async. clear ; 239 ; -; 1 Clock ; 631 ; -; 1 Clock enable ; 289 ; -; 1 Sync. clear ; 20 ; -; 1 Sync. load ; 26 ; -; 2 Async. clears ; 12 ; -; 2 Clock enables ; 84 ; -; 2 Clocks ; 41 ; -+------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+-------------------------------+ -; Number of Signals Sourced (Average = 18.19) ; Number of LABs (Total = 756) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 19 ; -; 2 ; 26 ; -; 3 ; 12 ; -; 4 ; 16 ; -; 5 ; 8 ; -; 6 ; 14 ; -; 7 ; 5 ; -; 8 ; 11 ; -; 9 ; 8 ; -; 10 ; 14 ; -; 11 ; 9 ; -; 12 ; 20 ; -; 13 ; 17 ; -; 14 ; 15 ; -; 15 ; 30 ; -; 16 ; 49 ; -; 17 ; 41 ; -; 18 ; 43 ; -; 19 ; 30 ; -; 20 ; 42 ; -; 21 ; 35 ; -; 22 ; 49 ; -; 23 ; 45 ; -; 24 ; 31 ; -; 25 ; 31 ; -; 26 ; 27 ; -; 27 ; 28 ; -; 28 ; 20 ; -; 29 ; 17 ; -; 30 ; 18 ; -; 31 ; 10 ; -; 32 ; 16 ; -+----------------------------------------------+-------------------------------+ - - -+---------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+-------------------------------+ -; Number of Signals Sourced Out (Average = 8.27) ; Number of LABs (Total = 756) ; -+-------------------------------------------------+-------------------------------+ -; 0 ; 1 ; -; 1 ; 61 ; -; 2 ; 48 ; -; 3 ; 47 ; -; 4 ; 43 ; -; 5 ; 40 ; -; 6 ; 51 ; -; 7 ; 50 ; -; 8 ; 53 ; -; 9 ; 71 ; -; 10 ; 46 ; -; 11 ; 45 ; -; 12 ; 51 ; -; 13 ; 46 ; -; 14 ; 26 ; -; 15 ; 25 ; -; 16 ; 19 ; -; 17 ; 5 ; -; 18 ; 9 ; -; 19 ; 6 ; -; 20 ; 4 ; -; 21 ; 1 ; -; 22 ; 2 ; -; 23 ; 0 ; -; 24 ; 3 ; -; 25 ; 2 ; -; 26 ; 0 ; -; 27 ; 1 ; -+-------------------------------------------------+-------------------------------+ - - -+------------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+-------------------------------+ -; Number of Distinct Inputs (Average = 18.51) ; Number of LABs (Total = 756) ; -+----------------------------------------------+-------------------------------+ -; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 22 ; -; 3 ; 24 ; -; 4 ; 30 ; -; 5 ; 15 ; -; 6 ; 15 ; -; 7 ; 23 ; -; 8 ; 16 ; -; 9 ; 20 ; -; 10 ; 17 ; -; 11 ; 19 ; -; 12 ; 16 ; -; 13 ; 20 ; -; 14 ; 18 ; -; 15 ; 17 ; -; 16 ; 19 ; -; 17 ; 34 ; -; 18 ; 26 ; -; 19 ; 19 ; -; 20 ; 27 ; -; 21 ; 33 ; -; 22 ; 35 ; -; 23 ; 33 ; -; 24 ; 33 ; -; 25 ; 30 ; -; 26 ; 30 ; -; 27 ; 21 ; -; 28 ; 15 ; -; 29 ; 16 ; -; 30 ; 26 ; -; 31 ; 28 ; -; 32 ; 29 ; -; 33 ; 25 ; -; 34 ; 4 ; -+----------------------------------------------+-------------------------------+ - - -+------------------------------------------+ -; I/O Rules Summary ; -+----------------------------------+-------+ -; I/O Rules Statistic ; Total ; -+----------------------------------+-------+ -; Total I/O Rules ; 30 ; -; Number of I/O Rules Passed ; 17 ; -; Number of I/O Rules Failed ; 0 ; -; Number of I/O Rules Unchecked ; 0 ; -; Number of I/O Rules Inapplicable ; 13 ; -+----------------------------------+-------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Details ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ -; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; -; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; -; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; -; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; -; Pass ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ; -; Pass ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; -; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ; -; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; -; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; -; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; -; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ; -+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; I/O Rules Matrix ; -+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ; -+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ -; Total Pass ; 295 ; 121 ; 295 ; 0 ; 0 ; 295 ; 295 ; 0 ; 295 ; 295 ; 168 ; 3 ; 0 ; 0 ; 183 ; 168 ; 3 ; 183 ; 0 ; 0 ; 11 ; 3 ; 171 ; 0 ; 0 ; 0 ; 0 ; 295 ; 0 ; 0 ; -; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; Total Inapplicable ; 0 ; 174 ; 0 ; 295 ; 295 ; 0 ; 0 ; 295 ; 0 ; 0 ; 127 ; 292 ; 295 ; 295 ; 112 ; 127 ; 292 ; 112 ; 295 ; 295 ; 284 ; 292 ; 124 ; 295 ; 295 ; 295 ; 295 ; 0 ; 295 ; 295 ; -; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; CLK24M576 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_STR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_BURST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nACSI_DRQ ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nACSI_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_DRQ ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_MSG ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nDCHG ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_DATA0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_DATA1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_DATA2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_CARD_DEDECT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_WP ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nDACK0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; WP_CF_CARD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_C_D ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_I_O ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_CS3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLK25M ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nACSI_ACK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nACSI_RESET ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nACSI_CS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_DIR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_A1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_ACK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_ATN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_DIR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; MIDI_OLR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; MIDI_TLR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; TxD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; RTS ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; DTR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; AMKB_TX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IDE_RES ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIDE_CS0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIDE_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIDE_WR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIDE_RD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nCF_CS0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nCF_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nROM3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nROM4 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nRP_UDS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nRP_LDS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSDSEL ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nWR_GATE ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nWR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; YM_QA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; YM_QB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; YM_QC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; DSA_D ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nVWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nVCAS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nVRAS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nVCS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nPD_VGA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; TIN0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSRCS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSRBLE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSRBHE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSRWE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nDREQ1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LED_FPGA_OK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSROE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VCKE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_TA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nDDR_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; DDR_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VSYNC_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HSYNC_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nBLANK_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; PIXEL_CLK_PAD ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSYNC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nMOT_ON ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSTEP_DIR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSTEP ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLKUSB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LPDIR ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; BA[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; BA[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIRQ[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIRQ[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIRQ[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIRQ[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIRQ[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nIRQ[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VA[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VB[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDM[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDM[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDM[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDM[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VG[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VR[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; TOUT0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nMASTER ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[31] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[30] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[29] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[28] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[27] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[26] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[25] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[24] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[23] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[22] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[21] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[20] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[19] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[18] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[17] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[16] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_AD[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[31] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[30] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[29] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[28] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[27] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[26] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[25] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[24] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[23] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[22] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[21] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[20] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[19] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[18] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[17] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[16] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[15] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[14] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[13] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[12] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[11] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[10] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[9] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[8] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VD[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDQS[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDQS[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDQS[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; VDQS[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[17] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[16] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IO[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[15] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[14] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[13] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[12] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[11] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[10] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[9] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[8] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SRD[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_PAR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_SEL ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_BUSY ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nSCSI_RST ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_CD_DATA3 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SD_CMD_D1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; ACSI_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[7] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[6] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[5] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[4] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[3] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[2] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[1] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_D[0] ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; SCSI_D[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nRSTO_MCF ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_WR ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_CS1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_SIZE1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_SIZE0 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; FB_ALE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_CS2 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; MAIN_CLK ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nDACK1 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nFB_OE ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IDE_RDY ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CLK33M ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; HD_DD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nINDEX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; RxD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nWP ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; LP_BUSY ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; DCD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; CTS ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; TRACK00 ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; IDE_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; RI ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nPCI_INTD ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nPCI_INTC ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nPCI_INTB ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nPCI_INTA ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; DVI_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; E0_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; PIC_INT ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; PIC_AMKB_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; MIDI_IN ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; nRD_DATA ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -; AMKB_RX ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; -+--------------------+-----------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; On ; -; Enable device-wide output enable (DEV_OE) ; On ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Passive Serial ; -; Error detection CRC ; Off ; -; Enable Open Drain on CRC Error pin ; Off ; -; Configuration Voltage Level ; Auto ; -; Force Configuration Voltage Level ; On ; -; nCEO ; As output driving ground ; -; Data[0] ; As input tri-stated ; -; Data[1]/ASDO ; As input tri-stated ; -; Data[7..2] ; Unreserved ; -; FLASH_nCE/nCSO ; As input tri-stated ; -; Other Active Parallel pins ; Unreserved ; -; DCLK ; As input tri-stated ; -; Base pin-out file on sameframe device ; Off ; -+----------------------------------------------+--------------------------+ - - -+------------------------------------+ -; Operating Settings and Conditions ; -+---------------------------+--------+ -; Setting ; Value ; -+---------------------------+--------+ -; Nominal Core Voltage ; 1.20 V ; -; Low Junction Temperature ; 0 °C ; -; High Junction Temperature ; 85 °C ; -+---------------------------+--------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Estimated Delay Added for Hold Timing ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -; I/O ; MAIN_CLK ; 245.886 ; -; MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 444.109 ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2],altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0],CLK33M,MAIN_CLK ; 1092.93 ; -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------+ -Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off. -This will disable optimization of problematic paths and expose them for further analysis using either the TimeQuest Timing Analyzer or the Classic Timing Analyzer. - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info: ******************************************************************* -Info: Running Quartus II Fitter - Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - Info: Processing started: Wed Dec 15 02:21:57 2010 -Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 -Info: Selected device EP3C40F484C6 for design "firebee1" -Info: Core supply voltage is 1.2V -Info: Low junction temperature is 0 degrees C -Info: High junction temperature is 85 degrees C -Info: Implemented PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" as Cyclone III PLL type - Info: Implementing clock multiplication of 1, clock division of 66, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] port - Info: Implementing clock multiplication of 67, clock division of 900, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] port - Info: Implementing clock multiplication of 67, clock division of 90, and phase shift of 0 degrees (0 ps) for altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] port -Info: None of the inputs fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input - Info: Input "nRD_DATA" that is fed by the compensated output clock of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input -Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings - Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109 - Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75 - Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port - Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port - Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port - Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port -Info: None of the inputs fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode are set as the compensated input - Info: Input "MAIN_CLK" that is fed by the compensated output clock of PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode has been set as a compensated input -Info: Implemented PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" as Cyclone III PLL type - Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 240 degrees (5051 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] port - Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] port - Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 180 degrees (3788 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] port - Info: Implementing clock multiplication of 4, clock division of 1, and phase shift of 105 degrees (2210 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] port - Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 270 degrees (11364 ps) for altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] port -Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type - Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port -Critical Warning: The input clock frequency specification of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is different from the output clock frequency specification of the source PLLs that are driving it - Critical Warning: Input port inclk[0] of PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" and its source clk[3] (the output port of PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1") have different specified frequencies, 48.0 MHz and 48.0 MHz respectively -Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature. -Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info: Device EP3C16F484C6 is compatible - Info: Device EP3C55F484C6 is compatible - Info: Device EP3C80F484C6 is compatible -Info: Fitter converted 7 user pins into dedicated programming pins - Info: Pin ~ALTERA_ASDO_DATA1~ is reserved at location D1 - Info: Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2 - Info: Pin ~ALTERA_DCLK~ is reserved at location K2 - Info: Pin ~ALTERA_DATA0~ is reserved at location K1 - Info: Pin ~ALTERA_DEV_OE~ is reserved at location N22 - Info: Pin ~ALTERA_DEV_CLRn~ is reserved at location N21 - Info: Pin ~ALTERA_nCEO~ is reserved at location K22 -Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details -Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. -Warning: The parameters of the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 and the PLL altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 do not have the same values - hence these PLLs cannot be merged - Info: The values of the parameter "M" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "M" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 67 - Info: The value of the parameter "M" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 109 - Info: The values of the parameter "N" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "N" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 6 - Info: The value of the parameter "N" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 3 - Info: The values of the parameter "LOOP FILTER R" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 12000 - Info: The value of the parameter "LOOP FILTER R" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 10000 - Info: The values of the parameter "VCO POST SCALE" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 2 - Info: The value of the parameter "VCO POST SCALE" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1 - Info: The values of the parameter "Min VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "Min VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538 - Info: The value of the parameter "Min VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769 - Info: The values of the parameter "Max VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "Max VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 3333 - Info: The value of the parameter "Max VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 1666 - Info: The values of the parameter "Center VCO Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "Center VCO Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 1538 - Info: The value of the parameter "Center VCO Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 769 - Info: The values of the parameter "Min Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "Min Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 17174 - Info: The value of the parameter "Min Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 27940 - Info: The values of the parameter "Max Lock Period" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "Max Lock Period" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is 30864 - Info: The value of the parameter "Max Lock Period" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is 59523 - Info: The values of the parameter "Compensate Clock" do not match for the PLL atoms altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 and PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 - Info: The value of the parameter "Compensate Clock" for the PLL atom altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1 is clock0 - Info: The value of the parameter "Compensate Clock" for the PLL atom altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 is clock1 -Warning: The input ports of the PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 and the PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 are mismatched, preventing the PLLs to be merged - Warning: Input clock frequency of PLL altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1 differs from input clock frequency of PLL altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1 -Warning: Implemented PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" as Cyclone III PLL type, but with warnings - Warning: Can't achieve requested value multiplication of 16 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter multiplication factor -- achieved value of multiplication of 109 - Warning: Can't achieve requested value division of 11 for clock output altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] of parameter division factor -- achieved value of division of 75 - Info: Implementing clock multiplication of 109, clock division of 1800, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] port - Info: Implementing clock multiplication of 109, clock division of 225, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] port - Info: Implementing clock multiplication of 109, clock division of 144, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] port - Info: Implementing clock multiplication of 109, clock division of 75, and phase shift of 0 degrees (0 ps) for altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] port -Info: Implemented PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" as Cyclone III PLL type - Info: Implementing clock multiplication of 2, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] port -Critical Warning: Input pin "CLK33M" feeds inclk port of PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" by global clock - I/O timing will be affected -Info: Timing-driven compilation is using the Classic Timing Analyzer -Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements -Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] (placed in counter C1 of PLL_3) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G14 -Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] (placed in counter C2 of PLL_3) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G12 -Info: Automatically promoted node altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] (placed in counter C3 of PLL_3) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G13 -Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] (placed in counter C0 of PLL_1) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 -Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] (placed in counter C3 of PLL_1) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 -Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] (placed in counter C2 of PLL_1) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G0 -Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] (placed in counter C4 of PLL_1) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2 -Info: Automatically promoted node altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] (placed in counter C1 of PLL_1) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4 -Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] (placed in counter C1 of PLL_4) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G16 -Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] (placed in counter C2 of PLL_4) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G17 -Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] (placed in counter C3 of PLL_4) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G18 -Info: Automatically promoted node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] (placed in counter C4 of PLL_4) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G19 -Info: Automatically promoted node altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] (placed in counter C0 of PLL_2) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G8 -Info: Automatically promoted node CLK33M~input (placed in PIN AB12 (CLK12, DIFFCLK_7n)) - Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G15 - Info: Following destination nodes may be non-global or may not use global or regional clocks - Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0 - Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3 - Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M -Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK - Info: Automatically promoted destinations to use location or clock signal Global Clock - Info: Following destination nodes may be non-global or may not use global or regional clocks - Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC - Info: Destination node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC -Info: Automatically promoted node inst25 - Info: Automatically promoted destinations to use location or clock signal Global Clock - Info: Following destination nodes may be non-global or may not use global or regional clocks - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_WR~reg0 - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_In - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|DTACK_OUTn - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TDRE - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[10] - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[14] - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[15] - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[12] - Info: Destination node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_PASS[13] - Info: Non-global destination nodes limited to 10 nodes -Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CLR_FIFO - Info: Automatically promoted destinations to use location or clock signal Global Clock -Info: Automatically promoted node Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO - Info: Automatically promoted destinations to use location or clock signal Global Clock - Info: Following destination nodes may be non-global or may not use global or regional clocks - Info: Destination node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC -Info: Automatically promoted node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] - Info: Automatically promoted destinations to use location or clock signal Global Clock - Info: Following destination nodes may be non-global or may not use global or regional clocks - Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|_~0 - Info: Destination node Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|valid_wrreq~0 -Info: Automatically promoted node FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|process_8~2 - Info: Automatically promoted destinations to use location or clock signal Global Clock -Info: Following DDIO Input nodes are constrained by the Fitter to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "VD[31]~input" is constrained to location IOIBUF_X43_Y0_N1 to improve DDIO timing - Info: Node "VD[31]" is constrained to location PIN U12 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30]" is constrained to location LAB_X41_Y1_N0 to improve DDIO timing - Info: Node "VD[30]~input" is constrained to location IOIBUF_X41_Y0_N29 to improve DDIO timing - Info: Node "VD[30]" is constrained to location PIN V12 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "VD[29]~input" is constrained to location IOIBUF_X38_Y0_N22 to improve DDIO timing - Info: Node "VD[29]" is constrained to location PIN AB13 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "VD[28]~input" is constrained to location IOIBUF_X43_Y0_N29 to improve DDIO timing - Info: Node "VD[28]" is constrained to location PIN W13 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing - Info: Node "VD[27]~input" is constrained to location IOIBUF_X48_Y0_N29 to improve DDIO timing - Info: Node "VD[27]" is constrained to location PIN V13 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "VD[26]~input" is constrained to location IOIBUF_X38_Y0_N8 to improve DDIO timing - Info: Node "VD[26]" is constrained to location PIN AB14 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "VD[25]~input" is constrained to location IOIBUF_X38_Y0_N15 to improve DDIO timing - Info: Node "VD[25]" is constrained to location PIN AA14 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "VD[24]~input" is constrained to location IOIBUF_X43_Y0_N8 to improve DDIO timing - Info: Node "VD[24]" is constrained to location PIN AB15 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing - Info: Node "VD[23]~input" is constrained to location IOIBUF_X45_Y0_N15 to improve DDIO timing - Info: Node "VD[23]" is constrained to location PIN AB16 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22]" is constrained to location LAB_X48_Y1_N0 to improve DDIO timing - Info: Node "VD[22]~input" is constrained to location IOIBUF_X48_Y0_N22 to improve DDIO timing - Info: Node "VD[22]" is constrained to location PIN W14 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "VD[21]~input" is constrained to location IOIBUF_X50_Y0_N1 to improve DDIO timing - Info: Node "VD[21]" is constrained to location PIN V15 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "VD[20]~input" is constrained to location IOIBUF_X50_Y0_N29 to improve DDIO timing - Info: Node "VD[20]" is constrained to location PIN U13 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19]" is constrained to location LAB_X50_Y1_N0 to improve DDIO timing - Info: Node "VD[19]~input" is constrained to location IOIBUF_X50_Y0_N22 to improve DDIO timing - Info: Node "VD[19]" is constrained to location PIN V14 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18]" is constrained to location LAB_X38_Y1_N0 to improve DDIO timing - Info: Node "VD[18]~input" is constrained to location IOIBUF_X38_Y0_N29 to improve DDIO timing - Info: Node "VD[18]" is constrained to location PIN AA13 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17]" is constrained to location LAB_X43_Y1_N0 to improve DDIO timing - Info: Node "VD[17]~input" is constrained to location IOIBUF_X43_Y0_N22 to improve DDIO timing - Info: Node "VD[17]" is constrained to location PIN Y13 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16]" is constrained to location LAB_X45_Y1_N0 to improve DDIO timing - Info: Node "VD[16]~input" is constrained to location IOIBUF_X45_Y0_N8 to improve DDIO timing - Info: Node "VD[16]" is constrained to location PIN T12 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15]" is constrained to location LAB_X66_Y15_N0 to improve DDIO timing - Info: Node "VD[15]~input" is constrained to location IOIBUF_X67_Y15_N8 to improve DDIO timing - Info: Node "VD[15]" is constrained to location PIN N20 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing - Info: Node "VD[14]~input" is constrained to location IOIBUF_X67_Y13_N8 to improve DDIO timing - Info: Node "VD[14]" is constrained to location PIN R22 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "VD[13]~input" is constrained to location IOIBUF_X67_Y14_N22 to improve DDIO timing - Info: Node "VD[13]" is constrained to location PIN P20 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12]" is constrained to location LAB_X66_Y17_N0 to improve DDIO timing - Info: Node "VD[12]~input" is constrained to location IOIBUF_X67_Y17_N22 to improve DDIO timing - Info: Node "VD[12]" is constrained to location PIN N17 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11]" is constrained to location LAB_X66_Y13_N0 to improve DDIO timing - Info: Node "VD[11]~input" is constrained to location IOIBUF_X67_Y13_N1 to improve DDIO timing - Info: Node "VD[11]" is constrained to location PIN R21 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "VD[10]~input" is constrained to location IOIBUF_X67_Y10_N15 to improve DDIO timing - Info: Node "VD[10]" is constrained to location PIN P17 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing - Info: Node "VD[9]~input" is constrained to location IOIBUF_X67_Y12_N22 to improve DDIO timing - Info: Node "VD[9]" is constrained to location PIN R18 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "VD[8]~input" is constrained to location IOIBUF_X67_Y10_N8 to improve DDIO timing - Info: Node "VD[8]" is constrained to location PIN V22 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing - Info: Node "VD[7]~input" is constrained to location IOIBUF_X67_Y11_N1 to improve DDIO timing - Info: Node "VD[7]" is constrained to location PIN U21 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" is constrained to location LAB_X66_Y12_N0 to improve DDIO timing - Info: Node "VD[6]~input" is constrained to location IOIBUF_X67_Y12_N15 to improve DDIO timing - Info: Node "VD[6]" is constrained to location PIN R19 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5]" is constrained to location LAB_X66_Y10_N0 to improve DDIO timing - Info: Node "VD[5]~input" is constrained to location IOIBUF_X67_Y10_N22 to improve DDIO timing - Info: Node "VD[5]" is constrained to location PIN R17 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "VD[4]~input" is constrained to location IOIBUF_X67_Y14_N1 to improve DDIO timing - Info: Node "VD[4]" is constrained to location PIN P21 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3]" is constrained to location LAB_X66_Y11_N0 to improve DDIO timing - Info: Node "VD[3]~input" is constrained to location IOIBUF_X67_Y11_N22 to improve DDIO timing - Info: Node "VD[3]" is constrained to location PIN R20 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" is constrained to location LAB_X66_Y14_N0 to improve DDIO timing - Info: Node "VD[2]~input" is constrained to location IOIBUF_X67_Y14_N8 to improve DDIO timing - Info: Node "VD[2]" is constrained to location PIN P22 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing - Info: Node "VD[1]~input" is constrained to location IOIBUF_X67_Y18_N1 to improve DDIO timing - Info: Node "VD[1]" is constrained to location PIN M21 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing - Info: Node "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0]" is constrained to location LAB_X66_Y18_N0 to improve DDIO timing - Info: Node "VD[0]~input" is constrained to location IOIBUF_X67_Y18_N8 to improve DDIO timing - Info: Node "VD[0]" is constrained to location PIN M22 to improve DDIO timing -Info: Starting register packing -Extra Info: Performing register packing on registers with non-logic cell location assignments -Extra Info: Completed register packing on registers with non-logic cell location assignments -Extra Info: Started Fast Input/Output/OE register processing -Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] to I/O pin - Warning: Can't pack node Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[0] and I/O node MAIN_CLK -- I/O node is a dedicated I/O pin -Extra Info: Finished Fast Input/Output/OE register processing -Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density -Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks -Info: Finished register packing - Extra Info: Packed 33 registers into blocks of type I/O Input Buffer - Extra Info: Packed 25 registers into blocks of type I/O Output Buffer - Extra Info: Created 9 register duplicates -Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register -Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input - Info: Input port INCLK[0] of node "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" is driven by CLK33M~inputclkctrl which is OUTCLK output port of Clock control block type node CLK33M~inputclkctrl -Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|pll1" output port clk[2] feeds output pin "CLK24M576~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[2] feeds output pin "CLK25M~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|pll1" output port clk[3] feeds output pin "CLKUSB~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[3]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[2]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[1]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "VDQS[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "nDDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" output port clk[0] feeds output pin "DDR_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance -Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input - Info: Input port INCLK[0] of node "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|pll1" is driven by altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl which is OUTCLK output port of Clock control block type node altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]~clkctrl -Info: Starting physical synthesis optimizations for speed -Info: Starting physical synthesis algorithm combinational resynthesis using boolean division -Info: Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 2208 ps -Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:23 -Info: Fitter preparation operations ending: elapsed time is 00:00:47 -Info: Fitter placement preparation operations beginning -Info: Fitter placement preparation operations ending: elapsed time is 00:00:18 -Info: Fitter placement operations beginning -Info: Fitter placement was successful -Info: Fitter placement operations ending: elapsed time is 00:01:10 -Info: Starting physical synthesis optimizations for speed -Info: Physical synthesis optimizations for speed complete: elapsed CPU time is 00:00:05 -Info: Estimated most critical path is register to pin delay of 5.130 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y12_N0; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[9]' - Info: 2: + IC(0.161 ns) + CELL(0.369 ns) = 0.530 ns; Loc. = LAB_X16_Y12_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359_RESYN14_BDD15' - Info: 3: + IC(0.528 ns) + CELL(0.243 ns) = 1.301 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~359' - Info: 4: + IC(0.172 ns) + CELL(0.130 ns) = 1.603 ns; Loc. = LAB_X17_Y13_N0; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[29]~360' - Info: 5: + IC(1.521 ns) + CELL(2.006 ns) = 5.130 ns; Loc. = IOOBUF_X34_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[29]~output' - Info: 6: + IC(0.000 ns) + CELL(0.000 ns) = 5.130 ns; Loc. = PIN_W10; Fanout = 0; PIN Node = 'FB_AD[29]' - Info: Total cell delay = 2.748 ns ( 53.57 % ) - Info: Total interconnect delay = 2.382 ns ( 46.43 % ) -Info: Fitter routing operations beginning -Info: 2 (of 32134) connections in the design require a large routing delay to satisfy hold requirements. Refer to the Fitter report for a summary of the relevant clock transfers. Also, check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks. -Info: Average interconnect usage is 13% of the available device resources - Info: Peak interconnect usage is 51% of the available device resources in the region that extends from location X22_Y11 to location X33_Y21 -Info: Fitter routing operations ending: elapsed time is 00:01:18 -Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. - Info: Optimizations that may affect the design's routability were skipped -Info: Started post-fitting delay annotation -Info: Delay annotation completed successfully -Info: Auto delay chain can't change the delay chain setting on I/O pin nRD_DATA since it's a PLL compensated pin -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|pll1" in Source Synchronous mode with compensated output clock set to clk[0] is not fully compensated because it does not feed an I/O input register -Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. -Warning: Total number of single-ended output or bi-directional pins in bank 4 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition. - Info: There are 32 output pin(s) with I/O standard 2.5 V and current strength 12mA - Info: Location AA13 (pad PAD_208): Pin VD[18] of type bi-directional uses 2.5 V I/O standard - Info: Location AB13 (pad PAD_209): Pin VD[29] of type bi-directional uses 2.5 V I/O standard - Info: Location AA14 (pad PAD_210): Pin VD[25] of type bi-directional uses 2.5 V I/O standard - Info: Location AB14 (pad PAD_211): Pin VD[26] of type bi-directional uses 2.5 V I/O standard - Info: Location V12 (pad PAD_213): Pin VD[30] of type bi-directional uses 2.5 V I/O standard - Info: Location W13 (pad PAD_218): Pin VD[28] of type bi-directional uses 2.5 V I/O standard - Info: Location Y13 (pad PAD_219): Pin VD[17] of type bi-directional uses 2.5 V I/O standard - Info: Location AA15 (pad PAD_220): Pin VDQS[0] of type bi-directional uses 2.5 V I/O standard - Info: Location AB15 (pad PAD_221): Pin VD[24] of type bi-directional uses 2.5 V I/O standard - Info: Location U12 (pad PAD_222): Pin VD[31] of type bi-directional uses 2.5 V I/O standard - Info: Location AA16 (pad PAD_224): Pin VDM[0] of type output uses 2.5 V I/O standard - Info: Location AB16 (pad PAD_225): Pin VD[23] of type bi-directional uses 2.5 V I/O standard - Info: Location T12 (pad PAD_226): Pin VD[16] of type bi-directional uses 2.5 V I/O standard - Info: Location V13 (pad PAD_228): Pin VD[27] of type bi-directional uses 2.5 V I/O standard - Info: Location W14 (pad PAD_229): Pin VD[22] of type bi-directional uses 2.5 V I/O standard - Info: Location U13 (pad PAD_233): Pin VD[20] of type bi-directional uses 2.5 V I/O standard - Info: Location V14 (pad PAD_234): Pin VD[19] of type bi-directional uses 2.5 V I/O standard - Info: Location U15 (pad PAD_236): Pin VCKE of type output uses 2.5 V I/O standard - Info: Location V15 (pad PAD_237): Pin VD[21] of type bi-directional uses 2.5 V I/O standard - Info: Location W15 (pad PAD_239): Pin VDQS[1] of type bi-directional uses 2.5 V I/O standard - Info: Location AB18 (pad PAD_242): Pin nVCAS of type output uses 2.5 V I/O standard - Info: Location AA17 (pad PAD_243): Pin nDDR_CLK of type output uses 2.5 V I/O standard - Info: Location AB17 (pad PAD_244): Pin DDR_CLK of type output uses 2.5 V I/O standard - Info: Location AA18 (pad PAD_245): Pin VA[12] of type output uses 2.5 V I/O standard - Info: Location AA19 (pad PAD_252): Pin BA[1] of type output uses 2.5 V I/O standard - Info: Location AB19 (pad PAD_253): Pin VA[9] of type output uses 2.5 V I/O standard - Info: Location W17 (pad PAD_257): Pin nVRAS of type output uses 2.5 V I/O standard - Info: Location Y17 (pad PAD_258): Pin nVWE of type output uses 2.5 V I/O standard - Info: Location AA20 (pad PAD_259): Pin VA[7] of type output uses 2.5 V I/O standard - Info: Location AB20 (pad PAD_260): Pin VA[8] of type output uses 2.5 V I/O standard - Info: Location V16 (pad PAD_261): Pin VDM[1] of type output uses 2.5 V I/O standard - Info: Location T16 (pad PAD_266): Pin VDQS[3] of type bi-directional uses 2.5 V I/O standard -Warning: Total number of single-ended output or bi-directional pins in bank 5 have exceeded the recommended amount in a bank where dedicated LVDS, RSDS, or mini-LVDS outputs exists. Refer to the pad placement and DC guidelines section in the Cyclone III Device I/O Features chapter of the Cyclone III Device Handbook for details on this condition. - Info: There are 30 output pin(s) with I/O standard 2.5 V and current strength 12mA - Info: Location AA22 (pad PAD_273): Pin VA[4] of type output uses 2.5 V I/O standard - Info: Location AA21 (pad PAD_274): Pin VA[6] of type output uses 2.5 V I/O standard - Info: Location T17 (pad PAD_277): Pin VDM[3] of type output uses 2.5 V I/O standard - Info: Location T18 (pad PAD_278): Pin nVCS of type output uses 2.5 V I/O standard - Info: Location W20 (pad PAD_280): Pin VA[0] of type output uses 2.5 V I/O standard - Info: Location W19 (pad PAD_285): Pin BA[0] of type output uses 2.5 V I/O standard - Info: Location Y22 (pad PAD_288): Pin VA[3] of type output uses 2.5 V I/O standard - Info: Location Y21 (pad PAD_289): Pin VA[5] of type output uses 2.5 V I/O standard - Info: Location U20 (pad PAD_290): Pin VDM[2] of type output uses 2.5 V I/O standard - Info: Location U19 (pad PAD_291): Pin VA[11] of type output uses 2.5 V I/O standard - Info: Location W22 (pad PAD_292): Pin VA[1] of type output uses 2.5 V I/O standard - Info: Location W21 (pad PAD_293): Pin VA[2] of type output uses 2.5 V I/O standard - Info: Location R17 (pad PAD_301): Pin VD[5] of type bi-directional uses 2.5 V I/O standard - Info: Location P17 (pad PAD_302): Pin VD[10] of type bi-directional uses 2.5 V I/O standard - Info: Location V22 (pad PAD_303): Pin VD[8] of type bi-directional uses 2.5 V I/O standard - Info: Location V21 (pad PAD_304): Pin VA[10] of type output uses 2.5 V I/O standard - Info: Location R20 (pad PAD_305): Pin VD[3] of type bi-directional uses 2.5 V I/O standard - Info: Location U22 (pad PAD_307): Pin VDQS[2] of type bi-directional uses 2.5 V I/O standard - Info: Location U21 (pad PAD_308): Pin VD[7] of type bi-directional uses 2.5 V I/O standard - Info: Location R18 (pad PAD_309): Pin VD[9] of type bi-directional uses 2.5 V I/O standard - Info: Location R19 (pad PAD_310): Pin VD[6] of type bi-directional uses 2.5 V I/O standard - Info: Location R22 (pad PAD_315): Pin VD[14] of type bi-directional uses 2.5 V I/O standard - Info: Location R21 (pad PAD_316): Pin VD[11] of type bi-directional uses 2.5 V I/O standard - Info: Location P20 (pad PAD_317): Pin VD[13] of type bi-directional uses 2.5 V I/O standard - Info: Location P22 (pad PAD_319): Pin VD[2] of type bi-directional uses 2.5 V I/O standard - Info: Location P21 (pad PAD_320): Pin VD[4] of type bi-directional uses 2.5 V I/O standard - Info: Location N20 (pad PAD_323): Pin VD[15] of type bi-directional uses 2.5 V I/O standard - Info: Location N17 (pad PAD_329): Pin VD[12] of type bi-directional uses 2.5 V I/O standard - Info: Location M22 (pad PAD_333): Pin VD[0] of type bi-directional uses 2.5 V I/O standard - Info: Location M21 (pad PAD_334): Pin VD[1] of type bi-directional uses 2.5 V I/O standard -Warning: 145 pins must meet Altera requirements for 3.3, 3.0, and 2.5-V interfaces. Refer to the device Application Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems). - Info: Pin nFB_BURST uses I/O standard 3.3-V LVTTL at T3 - Info: Pin nACSI_DRQ uses I/O standard 3.3-V LVTTL at K7 - Info: Pin nACSI_INT uses I/O standard 3.3-V LVTTL at J4 - Info: Pin nSCSI_DRQ uses I/O standard 3.3-V LVTTL at U1 - Info: Pin nSCSI_MSG uses I/O standard 3.3-V LVTTL at H2 - Info: Pin nDCHG uses I/O standard 3.3-V LVTTL at C17 - Info: Pin SD_DATA0 uses I/O standard 3.3-V LVTTL at B16 - Info: Pin SD_DATA1 uses I/O standard 3.3-V LVTTL at A16 - Info: Pin SD_DATA2 uses I/O standard 3.3-V LVTTL at B17 - Info: Pin SD_CARD_DEDECT uses I/O standard 3.3-V LVTTL at M20 - Info: Pin SD_WP uses I/O standard 3.3-V LVTTL at M19 - Info: Pin nDACK0 uses I/O standard 3.3-V LVTTL at B12 - Info: Pin WP_CF_CARD uses I/O standard 3.3-V LVTTL at T1 - Info: Pin nSCSI_C_D uses I/O standard 3.3-V LVTTL at H1 - Info: Pin nSCSI_I_O uses I/O standard 3.3-V LVTTL at J3 - Info: Pin nFB_CS3 uses I/O standard 3.3-V LVTTL at V6 - Info: Pin TOUT0 uses I/O standard 3.3-V LVTTL at T22 - Info: Pin nMASTER uses I/O standard 3.3-V LVTTL at T21 - Info: Pin FB_AD[31] uses I/O standard 3.3-V LVTTL at AA10 - Info: Pin FB_AD[30] uses I/O standard 3.3-V LVTTL at Y10 - Info: Pin FB_AD[29] uses I/O standard 3.3-V LVTTL at W10 - Info: Pin FB_AD[28] uses I/O standard 3.3-V LVTTL at V11 - Info: Pin FB_AD[27] uses I/O standard 3.3-V LVTTL at U11 - Info: Pin FB_AD[26] uses I/O standard 3.3-V LVTTL at AB9 - Info: Pin FB_AD[25] uses I/O standard 3.3-V LVTTL at AA9 - Info: Pin FB_AD[24] uses I/O standard 3.3-V LVTTL at T11 - Info: Pin FB_AD[23] uses I/O standard 3.3-V LVTTL at AB8 - Info: Pin FB_AD[22] uses I/O standard 3.3-V LVTTL at AA8 - Info: Pin FB_AD[21] uses I/O standard 3.3-V LVTTL at U10 - Info: Pin FB_AD[20] uses I/O standard 3.3-V LVTTL at T10 - Info: Pin FB_AD[19] uses I/O standard 3.3-V LVTTL at V10 - Info: Pin FB_AD[18] uses I/O standard 3.3-V LVTTL at V9 - Info: Pin FB_AD[17] uses I/O standard 3.3-V LVTTL at Y8 - Info: Pin FB_AD[16] uses I/O standard 3.3-V LVTTL at AB7 - Info: Pin FB_AD[15] uses I/O standard 3.3-V LVTTL at AA7 - Info: Pin FB_AD[14] uses I/O standard 3.3-V LVTTL at W8 - Info: Pin FB_AD[13] uses I/O standard 3.3-V LVTTL at V8 - Info: Pin FB_AD[12] uses I/O standard 3.3-V LVTTL at U9 - Info: Pin FB_AD[11] uses I/O standard 3.3-V LVTTL at Y7 - Info: Pin FB_AD[10] uses I/O standard 3.3-V LVTTL at W7 - Info: Pin FB_AD[9] uses I/O standard 3.3-V LVTTL at AB5 - Info: Pin FB_AD[8] uses I/O standard 3.3-V LVTTL at AA5 - Info: Pin FB_AD[7] uses I/O standard 3.3-V LVTTL at AB4 - Info: Pin FB_AD[6] uses I/O standard 3.3-V LVTTL at AA4 - Info: Pin FB_AD[5] uses I/O standard 3.3-V LVTTL at V7 - Info: Pin FB_AD[4] uses I/O standard 3.3-V LVTTL at W6 - Info: Pin FB_AD[3] uses I/O standard 3.3-V LVTTL at AB3 - Info: Pin FB_AD[2] uses I/O standard 3.3-V LVTTL at AA3 - Info: Pin FB_AD[1] uses I/O standard 3.3-V LVTTL at Y6 - Info: Pin FB_AD[0] uses I/O standard 3.3-V LVTTL at Y3 - Info: Pin IO[17] uses I/O standard 3.3-V LVTTL at B13 - Info: Pin IO[16] uses I/O standard 3.3-V LVTTL at A13 - Info: Pin IO[15] uses I/O standard 3.3-V LVTTL at B14 - Info: Pin IO[14] uses I/O standard 3.3-V LVTTL at A14 - Info: Pin IO[13] uses I/O standard 3.3-V LVTTL at E13 - Info: Pin IO[12] uses I/O standard 3.3-V LVTTL at D13 - Info: Pin IO[11] uses I/O standard 3.3-V LVTTL at C13 - Info: Pin IO[10] uses I/O standard 3.3-V LVTTL at B15 - Info: Pin IO[9] uses I/O standard 3.3-V LVTTL at A15 - Info: Pin IO[8] uses I/O standard 3.3-V LVTTL at G10 - Info: Pin IO[7] uses I/O standard 3.3-V LVTTL at C7 - Info: Pin IO[6] uses I/O standard 3.3-V LVTTL at C8 - Info: Pin IO[5] uses I/O standard 3.3-V LVTTL at E9 - Info: Pin IO[4] uses I/O standard 3.3-V LVTTL at B6 - Info: Pin IO[3] uses I/O standard 3.3-V LVTTL at A6 - Info: Pin IO[2] uses I/O standard 3.3-V LVTTL at B7 - Info: Pin IO[1] uses I/O standard 3.3-V LVTTL at A7 - Info: Pin IO[0] uses I/O standard 3.3-V LVTTL at A8 - Info: Pin SRD[15] uses I/O standard 3.3-V LVTTL at H10 - Info: Pin SRD[14] uses I/O standard 3.3-V LVTTL at G9 - Info: Pin SRD[13] uses I/O standard 3.3-V LVTTL at F10 - Info: Pin SRD[12] uses I/O standard 3.3-V LVTTL at D10 - Info: Pin SRD[11] uses I/O standard 3.3-V LVTTL at B10 - Info: Pin SRD[10] uses I/O standard 3.3-V LVTTL at A9 - Info: Pin SRD[9] uses I/O standard 3.3-V LVTTL at A10 - Info: Pin SRD[8] uses I/O standard 3.3-V LVTTL at B9 - Info: Pin SRD[7] uses I/O standard 3.3-V LVTTL at H11 - Info: Pin SRD[6] uses I/O standard 3.3-V LVTTL at E10 - Info: Pin SRD[5] uses I/O standard 3.3-V LVTTL at F9 - Info: Pin SRD[4] uses I/O standard 3.3-V LVTTL at C10 - Info: Pin SRD[3] uses I/O standard 3.3-V LVTTL at G11 - Info: Pin SRD[2] uses I/O standard 3.3-V LVTTL at C6 - Info: Pin SRD[1] uses I/O standard 3.3-V LVTTL at A5 - Info: Pin SRD[0] uses I/O standard 3.3-V LVTTL at B5 - Info: Pin SCSI_PAR uses I/O standard 3.3-V LVTTL at M7 - Info: Pin nSCSI_SEL uses I/O standard 3.3-V LVTTL at M8 - Info: Pin nSCSI_BUSY uses I/O standard 3.3-V LVTTL at N8 - Info: Pin nSCSI_RST uses I/O standard 3.3-V LVTTL at N6 - Info: Pin SD_CD_DATA3 uses I/O standard 3.3-V LVTTL at F13 - Info: Pin SD_CMD_D1 uses I/O standard 3.3-V LVTTL at E14 - Info: Pin ACSI_D[7] uses I/O standard 3.3-V LVTTL at H6 - Info: Pin ACSI_D[6] uses I/O standard 3.3-V LVTTL at H7 - Info: Pin ACSI_D[5] uses I/O standard 3.3-V LVTTL at D2 - Info: Pin ACSI_D[4] uses I/O standard 3.3-V LVTTL at C1 - Info: Pin ACSI_D[3] uses I/O standard 3.3-V LVTTL at C2 - Info: Pin ACSI_D[2] uses I/O standard 3.3-V LVTTL at E3 - Info: Pin ACSI_D[1] uses I/O standard 3.3-V LVTTL at G5 - Info: Pin ACSI_D[0] uses I/O standard 3.3-V LVTTL at B1 - Info: Pin LP_D[7] uses I/O standard 3.3-V LVTTL at G8 - Info: Pin LP_D[6] uses I/O standard 3.3-V LVTTL at A3 - Info: Pin LP_D[5] uses I/O standard 3.3-V LVTTL at B3 - Info: Pin LP_D[4] uses I/O standard 3.3-V LVTTL at D6 - Info: Pin LP_D[3] uses I/O standard 3.3-V LVTTL at E7 - Info: Pin LP_D[2] uses I/O standard 3.3-V LVTTL at C3 - Info: Pin LP_D[1] uses I/O standard 3.3-V LVTTL at C4 - Info: Pin LP_D[0] uses I/O standard 3.3-V LVTTL at F7 - Info: Pin SCSI_D[7] uses I/O standard 3.3-V LVTTL at K8 - Info: Pin SCSI_D[6] uses I/O standard 3.3-V LVTTL at L8 - Info: Pin SCSI_D[5] uses I/O standard 3.3-V LVTTL at G3 - Info: Pin SCSI_D[4] uses I/O standard 3.3-V LVTTL at G4 - Info: Pin SCSI_D[3] uses I/O standard 3.3-V LVTTL at F1 - Info: Pin SCSI_D[2] uses I/O standard 3.3-V LVTTL at F2 - Info: Pin SCSI_D[1] uses I/O standard 3.3-V LVTTL at E1 - Info: Pin SCSI_D[0] uses I/O standard 3.3-V LVTTL at J6 - Info: Pin nRSTO_MCF uses I/O standard 3.3-V LVTTL at B11 - Info: Pin nFB_WR uses I/O standard 3.3-V LVTTL at T5 - Info: Pin nFB_CS1 uses I/O standard 3.3-V LVTTL at T8 - Info: Pin FB_SIZE1 uses I/O standard 3.3-V LVTTL at Y4 - Info: Pin FB_SIZE0 uses I/O standard 3.3-V LVTTL at U8 - Info: Pin FB_ALE uses I/O standard 3.3-V LVTTL at R7 - Info: Pin nFB_CS2 uses I/O standard 3.3-V LVTTL at T9 - Info: Pin MAIN_CLK uses I/O standard 3.3-V LVTTL at G2 - Info: Pin nDACK1 uses I/O standard 3.3-V LVTTL at A12 - Info: Pin nFB_OE uses I/O standard 3.3-V LVTTL at R6 - Info: Pin IDE_RDY uses I/O standard 3.3-V LVTTL at Y1 - Info: Pin CLK33M uses I/O standard 3.3-V LVTTL at AB12 - Info: Pin HD_DD uses I/O standard 3.3-V LVTTL at F16 - Info: Pin nINDEX uses I/O standard 3.3-V LVTTL at E16 - Info: Pin RxD uses I/O standard 3.3-V LVTTL at H15 - Info: Pin nWP uses I/O standard 3.3-V LVTTL at D19 - Info: Pin LP_BUSY uses I/O standard 3.3-V LVTTL at G7 - Info: Pin DCD uses I/O standard 3.3-V LVTTL at A19 - Info: Pin CTS uses I/O standard 3.3-V LVTTL at H14 - Info: Pin TRACK00 uses I/O standard 3.3-V LVTTL at C19 - Info: Pin RI uses I/O standard 3.3-V LVTTL at B19 - Info: Pin nPCI_INTD uses I/O standard 3.3-V LVTTL at P6 - Info: Pin nPCI_INTC uses I/O standard 3.3-V LVTTL at V3 - Info: Pin nPCI_INTB uses I/O standard 3.3-V LVTTL at V4 - Info: Pin nPCI_INTA uses I/O standard 3.3-V LVTTL at AA1 - Info: Pin DVI_INT uses I/O standard 3.3-V LVTTL at A11 - Info: Pin PIC_INT uses I/O standard 3.3-V LVTTL at AA2 - Info: Pin PIC_AMKB_RX uses I/O standard 3.3-V LVTTL at L7 - Info: Pin MIDI_IN uses I/O standard 3.3-V LVTTL at E12 - Info: Pin nRD_DATA uses I/O standard 3.3-V LVTTL at A20 - Info: Pin AMKB_RX uses I/O standard 3.3-V LVTTL at Y2 -Warning: Following 40 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results - Info: Pin IO[17] has a permanently enabled output enable - Info: Pin IO[16] has a permanently enabled output enable - Info: Pin IO[15] has a permanently enabled output enable - Info: Pin IO[14] has a permanently enabled output enable - Info: Pin IO[13] has a permanently enabled output enable - Info: Pin IO[12] has a permanently enabled output enable - Info: Pin IO[11] has a permanently enabled output enable - Info: Pin IO[10] has a permanently enabled output enable - Info: Pin IO[9] has a permanently enabled output enable - Info: Pin IO[8] has a permanently enabled output enable - Info: Pin IO[7] has a permanently enabled output enable - Info: Pin IO[6] has a permanently enabled output enable - Info: Pin IO[5] has a permanently enabled output enable - Info: Pin IO[4] has a permanently enabled output enable - Info: Pin IO[3] has a permanently enabled output enable - Info: Pin IO[2] has a permanently enabled output enable - Info: Pin IO[1] has a permanently enabled output enable - Info: Pin IO[0] has a permanently enabled output enable - Info: Pin SCSI_PAR has a permanently disabled output enable - Info: Pin nSCSI_SEL has a permanently enabled output enable - Info: Pin nSCSI_BUSY has a permanently enabled output enable - Info: Pin nSCSI_RST has a permanently disabled output enable - Info: Pin SD_CD_DATA3 has a permanently disabled output enable - Info: Pin SD_CMD_D1 has a permanently disabled output enable - Info: Pin ACSI_D[7] has a permanently disabled output enable - Info: Pin ACSI_D[6] has a permanently disabled output enable - Info: Pin ACSI_D[5] has a permanently disabled output enable - Info: Pin ACSI_D[4] has a permanently disabled output enable - Info: Pin ACSI_D[3] has a permanently disabled output enable - Info: Pin ACSI_D[2] has a permanently disabled output enable - Info: Pin ACSI_D[1] has a permanently disabled output enable - Info: Pin ACSI_D[0] has a permanently disabled output enable - Info: Pin SCSI_D[7] has a permanently disabled output enable - Info: Pin SCSI_D[6] has a permanently disabled output enable - Info: Pin SCSI_D[5] has a permanently disabled output enable - Info: Pin SCSI_D[4] has a permanently disabled output enable - Info: Pin SCSI_D[3] has a permanently disabled output enable - Info: Pin SCSI_D[2] has a permanently disabled output enable - Info: Pin SCSI_D[1] has a permanently disabled output enable - Info: Pin SCSI_D[0] has a permanently disabled output enable -Info: Quartus II Fitter was successful. 0 errors, 34 warnings - Info: Peak virtual memory: 334 megabytes - Info: Processing ended: Wed Dec 15 02:25:07 2010 - Info: Elapsed time: 00:03:10 - Info: Total CPU time (on all processors): 00:03:11 - - diff --git a/FPGA_Quartus_13.1/firebee1.flow.rpt b/FPGA_Quartus_13.1/firebee1.flow.rpt deleted file mode 100644 index 297d7a0..0000000 --- a/FPGA_Quartus_13.1/firebee1.flow.rpt +++ /dev/null @@ -1,380 +0,0 @@ -Flow report for firebee1 -Wed Dec 15 02:25:22 2010 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Wed Dec 15 02:25:21 2010 ; -; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; -; Revision Name ; firebee1 ; -; Top-level Entity Name ; firebee1 ; -; Family ; Cyclone III ; -; Device ; EP3C40F484C6 ; -; Timing Models ; Final ; -; Met timing requirements ; No ; -; Total logic elements ; 9,526 / 39,600 ( 24 % ) ; -; Total combinational functions ; 8,061 / 39,600 ( 20 % ) ; -; Dedicated logic registers ; 4,563 / 39,600 ( 12 % ) ; -; Total registers ; 4749 ; -; Total pins ; 295 / 332 ( 89 % ) ; -; Total virtual pins ; 0 ; -; Total memory bits ; 109,344 / 1,161,216 ( 9 % ) ; -; Embedded Multiplier 9-bit elements ; 6 / 252 ( 2 % ) ; -; Total PLLs ; 4 / 4 ( 100 % ) ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 12/15/2010 02:20:37 ; -; Main task ; Compilation ; -; Revision Name ; firebee1 ; -+-------------------+---------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-----------------------------------------+------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-----------------------------------------+------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 150661768621.129237603704664 ; -- ; -- ; -- ; -; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ; -; FMAX_REQUIREMENT ; 30 ns ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_LATCH ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_COMPARE ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_BIDIR ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL_RECONFIG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; C:/firebee/FPGA/firebee1.dpf ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.ppf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux2.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram2.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_latch1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_latch1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant4.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_compare1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_compare1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_compare1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_LONG.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_LONG.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_LONG.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_BYT.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_BYT.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_BYT.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_WORD.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_WORD.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_WORD.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff4.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff5.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff5.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff5.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff6.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg3.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux5.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux5.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux5.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg5.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg5.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg5.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg6.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg4.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.inc ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux6.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxDZ.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxDZ.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxVDM.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxVDM.cmp ; -- ; -- ; -- ; -; MISC_FILE ; C:/FireBee/FPGA/firebee1.dpf ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.tdf ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.tdf ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.ppf ; -- ; -- ; -- ; -; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ; -; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ; -; PHYSICAL_SYNTHESIS_EFFORT ; Fast ; Normal ; -- ; -- ; -; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ; -; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ; -; TCO_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; TH_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; TPD_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; TSU_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -; USE_TIMEQUEST_TIMING_ANALYZER ; Off ; On ; -- ; -- ; -+-----------------------------------------+------------------------------------+---------------+-------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:01:16 ; 1.0 ; 347 MB ; 00:01:17 ; -; Fitter ; 00:03:05 ; 1.0 ; 334 MB ; 00:03:07 ; -; Assembler ; 00:00:05 ; 1.0 ; 291 MB ; 00:00:04 ; -; Classic Timing Analyzer ; 00:00:07 ; 1.0 ; 227 MB ; 00:00:09 ; -; Total ; 00:04:33 ; -- ; -- ; 00:04:37 ; -+-------------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+-------------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+-------------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; -; Fitter ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; -; Assembler ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; -; Classic Timing Analyzer ; envy15 ; Windows Vista ; 6.1 ; x86_64 ; -+-------------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 -quartus_fit --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 -quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 -quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only - - - diff --git a/FPGA_Quartus_13.1/firebee1.map.rpt b/FPGA_Quartus_13.1/firebee1.map.rpt deleted file mode 100644 index 11a1ac1..0000000 --- a/FPGA_Quartus_13.1/firebee1.map.rpt +++ /dev/null @@ -1,8590 +0,0 @@ -Analysis & Synthesis report for firebee1 -Wed Dec 15 02:21:56 2010 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis RAM Summary - 9. Analysis & Synthesis DSP Block Usage Summary - 10. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR - 11. State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM - 12. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE - 13. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE - 14. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE - 15. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE - 16. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE - 17. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE - 18. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE - 19. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE - 20. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE - 21. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE - 22. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE - 23. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP - 24. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE - 25. State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE - 26. Registers Protected by Synthesis - 27. User-Specified and Inferred Latches - 28. Registers Removed During Synthesis - 29. Removed Registers Triggering Further Register Optimizations - 30. General Register Statistics - 31. Inverted Register Statistics - 32. Multiplexer Restructuring Statistics (Restructuring Performed) - 33. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated - 34. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p - 35. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p - 36. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram - 37. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp - 38. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 - 39. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp - 40. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp - 41. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp - 42. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 - 43. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated - 44. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p - 45. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p - 46. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram - 47. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp - 48. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp - 49. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp - 50. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 - 51. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp - 52. Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 - 53. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component - 54. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated - 55. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p - 56. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p - 57. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp - 58. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram - 59. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp - 60. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 - 61. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr - 62. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp - 63. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp - 64. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp - 65. Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 - 66. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component - 67. Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated - 68. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated - 69. Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram - 70. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated - 71. Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated - 72. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated - 73. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated - 74. Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated - 75. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated - 76. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated - 77. Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated - 78. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component - 79. Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated - 80. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component - 81. Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated - 82. Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated - 83. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component - 84. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated - 85. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 - 86. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 - 87. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 - 88. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 - 89. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 - 90. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 - 91. Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 - 92. Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component - 93. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component - 94. Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated - 95. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component - 96. Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated - 97. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component - 98. Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated - 99. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component -100. Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated -101. Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component -102. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component -103. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component -104. Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL -105. Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component -106. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component -107. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component -108. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component -109. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component -110. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component -111. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component -112. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component -113. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component -114. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component -115. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component -116. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component -117. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component -118. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component -119. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component -120. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component -121. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component -122. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component -123. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component -124. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component -125. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component -126. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component -127. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component -128. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component -129. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component -130. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component -131. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component -132. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component -133. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component -134. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component -135. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component -136. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component -137. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component -138. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component -139. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component -140. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component -141. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component -142. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component -143. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component -144. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component -145. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component -146. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component -147. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component -148. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component -149. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component -150. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component -151. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component -152. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component -153. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component -154. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component -155. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component -156. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component -157. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component -158. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component -159. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component -160. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component -161. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component -162. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component -163. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component -164. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component -165. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component -166. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component -167. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component -168. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component -169. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component -170. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component -171. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component -172. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component -173. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component -174. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component -175. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component -176. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component -177. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component -178. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component -179. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component -180. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component -181. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component -182. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component -183. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component -184. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component -185. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component -186. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component -187. Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component -188. Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component -189. Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component -190. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component -191. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 -192. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 -193. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 -194. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 -195. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 -196. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 -197. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 -198. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 -199. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 -200. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 -201. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 -202. Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 -203. Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component -204. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component -205. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component -206. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component -207. Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component -208. Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component -209. Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component -210. Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component -211. Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component -212. Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component -213. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 -214. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 -215. Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 -216. altpll Parameter Settings by Entity Instance -217. lpm_shiftreg Parameter Settings by Entity Instance -218. dcfifo Parameter Settings by Entity Instance -219. scfifo Parameter Settings by Entity Instance -220. altsyncram Parameter Settings by Entity Instance -221. lpm_mult Parameter Settings by Entity Instance -222. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" -223. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" -224. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" -225. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" -226. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" -227. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" -228. Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" -229. Analysis & Synthesis Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+------------------------------------+----------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Dec 15 02:21:55 2010 ; -; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; -; Revision Name ; firebee1 ; -; Top-level Entity Name ; firebee1 ; -; Family ; Cyclone III ; -; Total logic elements ; 10,706 ; -; Total combinational functions ; 8,060 ; -; Dedicated logic registers ; 4,612 ; -; Total registers ; 4740 ; -; Total pins ; 295 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 109,344 ; -; Embedded Multiplier 9-bit elements ; 6 ; -; Total PLLs ; 4 ; -+------------------------------------+----------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+----------------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EP3C40F484C6 ; ; -; Top-level entity name ; firebee1 ; firebee1 ; -; Family name ; Cyclone III ; Stratix II ; -; State Machine Processing ; One-Hot ; Auto ; -; Optimization Technique ; Speed ; Balanced ; -; Use Generated Physical Constraints File ; Off ; ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Disable OpenCore Plus hardware evaluation ; Off ; Off ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Parallel Synthesis ; On ; On ; -; DSP Block Balancing ; Auto ; Auto ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto ROM Replacement ; On ; On ; -; Auto RAM Replacement ; On ; On ; -; Auto DSP Block Replacement ; On ; On ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Strict RAM Replacement ; Off ; Off ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto RAM Block Balancing ; On ; On ; -; Auto RAM to Logic Cell Conversion ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Allow Any RAM Size For Recognition ; Off ; Off ; -; Allow Any ROM Size For Recognition ; Off ; Off ; -; Allow Any Shift Register Size For Recognition ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Timing-Driven Synthesis ; On ; On ; -; Show Parameter Settings Tables in Synthesis Report ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Auto Gated Clock Conversion ; Off ; Off ; -; Block Design Naming ; Auto ; Auto ; -; SDC constraint protection ; Off ; Off ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -; Resource Aware Inference For Block RAM ; On ; On ; -+----------------------------------------------------------------------------+--------------------+--------------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; -+----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ -; FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd ; -; FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd ; -; FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd ; -; FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd ; -; FalconIO_SDCard_IDE_CF/dcfifo0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo0.vhd ; -; Video/DDR_CTR.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Video/DDR_CTR.tdf ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd ; -; FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd ; -; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd ; -; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd ; -; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd ; -; FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd ; -; FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd ; -; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd ; -; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd ; -; FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd ; -; lpm_latch0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_latch0.vhd ; -; altpll1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll1.vhd ; -; Video/lpm_fifoDZ.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_fifoDZ.vhd ; -; altpll2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll2.vhd ; -; altpll3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altpll3.vhd ; -; Video/altdpram0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram0.vhd ; -; Video/lpm_muxDZ.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_muxDZ.vhd ; -; Video/lpm_bustri3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_bustri3.vhd ; -; Video/lpm_ff0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff0.vhd ; -; Video/lpm_ff1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff1.vhd ; -; Video/lpm_ff3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff3.vhd ; -; Video/VIDEO_MOD_MUX_CLUTCTR.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Video/VIDEO_MOD_MUX_CLUTCTR.tdf ; -; Video/lpm_fifo_dc0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_fifo_dc0.vhd ; -; Video/Video.bdf ; yes ; User Block Diagram/Schematic File ; C:/FireBee/FPGA/Video/Video.bdf ; -; firebee1.bdf ; yes ; User Block Diagram/Schematic File ; C:/FireBee/FPGA/firebee1.bdf ; -; lpm_counter0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_counter0.vhd ; -; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd ; -; DSP/DSP.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/DSP/DSP.vhd ; -; Video/lpm_shiftreg0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg0.vhd ; -; Video/lpm_bustri1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_bustri1.vhd ; -; Video/altdpram1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram1.vhd ; -; Video/lpm_constant0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant0.vhd ; -; Video/lpm_constant1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant1.vhd ; -; Video/lpm_mux0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux0.vhd ; -; Video/lpm_mux1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux1.vhd ; -; Video/lpm_mux2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux2.vhd ; -; Video/lpm_constant2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant2.vhd ; -; Video/altdpram2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altdpram2.vhd ; -; Video/lpm_mux3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux3.vhd ; -; Video/lpm_mux4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux4.vhd ; -; Video/lpm_constant3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_constant3.vhd ; -; Interrupt_Handler/interrupt_handler.tdf ; yes ; User AHDL File ; C:/FireBee/FPGA/Interrupt_Handler/interrupt_handler.tdf ; -; lpm_bustri_LONG.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_LONG.vhd ; -; lpm_bustri_BYT.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_BYT.vhd ; -; lpm_bustri_WORD.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/lpm_bustri_WORD.vhd ; -; Video/lpm_ff4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff4.vhd ; -; Video/lpm_ff5.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff5.vhd ; -; Video/lpm_ff6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_ff6.vhd ; -; Video/altddio_bidir0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_bidir0.vhd ; -; Video/altddio_out0.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_out0.vhd ; -; Video/lpm_mux5.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux5.vhd ; -; Video/BLITTER/BLITTER.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/Video/BLITTER/BLITTER.vhd ; -; Video/lpm_shiftreg6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg6.vhd ; -; Video/lpm_shiftreg4.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_shiftreg4.vhd ; -; Video/altddio_out2.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/altddio_out2.vhd ; -; altddio_out3.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/altddio_out3.vhd ; -; Video/lpm_mux6.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_mux6.vhd ; -; FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd ; yes ; User VHDL File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd ; -; FalconIO_SDCard_IDE_CF/dcfifo1.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/FalconIO_SDCard_IDE_CF/dcfifo1.vhd ; -; Video/lpm_muxVDM.vhd ; yes ; User Wizard-Generated File ; C:/FireBee/FPGA/Video/lpm_muxVDM.vhd ; -; lpm_bustri_byt.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_byt.inc ; -; lpm_bustri_word.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_word.inc ; -; lpm_bustri_long.inc ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/lpm_bustri_long.inc ; -; altpll.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.tdf ; -; db/altpll_pul2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_pul2.tdf ; -; dcfifo_mixed_widths.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo_mixed_widths.tdf ; -; db/dcfifo_0hh1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_0hh1.tdf ; -; db/a_gray2bin_lfb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_gray2bin_lfb.tdf ; -; db/a_graycounter_k47.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_k47.tdf ; -; db/a_graycounter_fic.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_fic.tdf ; -; db/altsyncram_bi31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_bi31.tdf ; -; db/alt_synch_pipe_ikd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_ikd.tdf ; -; db/dffpipe_hd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_hd9.tdf ; -; db/dffpipe_gd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_gd9.tdf ; -; db/dffpipe_pe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_pe9.tdf ; -; db/alt_synch_pipe_jkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_jkd.tdf ; -; db/dffpipe_id9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_id9.tdf ; -; db/cmpr_256.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_256.tdf ; -; db/cmpr_156.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_156.tdf ; -; db/cntr_t2e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_t2e.tdf ; -; db/mux_a18.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_a18.tdf ; -; db/dcfifo_3fh1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_3fh1.tdf ; -; db/a_graycounter_j47.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_j47.tdf ; -; db/a_graycounter_gic.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_gic.tdf ; -; db/altsyncram_ci31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_ci31.tdf ; -; db/alt_synch_pipe_kkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_kkd.tdf ; -; db/dffpipe_jd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_jd9.tdf ; -; db/alt_synch_pipe_lkd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_lkd.tdf ; -; db/dffpipe_kd9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_kd9.tdf ; -; db/altpll_41p2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_41p2.tdf ; -; lpm_bustri.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_bustri.tdf ; -; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; -; dcfifo.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/dcfifo.tdf ; -; db/dcfifo_8fi1.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dcfifo_8fi1.tdf ; -; db/a_gray2bin_tgb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_gray2bin_tgb.tdf ; -; db/a_graycounter_s57.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_s57.tdf ; -; db/a_graycounter_ojc.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_ojc.tdf ; -; db/a_graycounter_njc.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_graycounter_njc.tdf ; -; db/altsyncram_tl31.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_tl31.tdf ; -; db/alt_synch_pipe_rld.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_rld.tdf ; -; db/dffpipe_qe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_qe9.tdf ; -; db/dffpipe_9d9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_9d9.tdf ; -; db/dffpipe_oe9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_oe9.tdf ; -; db/alt_synch_pipe_sld.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/alt_synch_pipe_sld.tdf ; -; db/dffpipe_re9.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/dffpipe_re9.tdf ; -; lpm_mux.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mux.tdf ; -; db/mux_bbe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_bbe.tdf ; -; lpm_ff.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_ff.tdf ; -; altddio_bidir.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_bidir.tdf ; -; db/ddio_bidir_3jl.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_bidir_3jl.tdf ; -; db/mux_58e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_58e.tdf ; -; lpm_latch.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_latch.tdf ; -; altsyncram.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.tdf ; -; db/altsyncram_lf92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_lf92.tdf ; -; mux41.bdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/others/maxplus2/mux41.bdf ; -; db/mux_dcf.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_dcf.tdf ; -; scfifo.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/scfifo.tdf ; -; db/scfifo_lk21.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/scfifo_lk21.tdf ; -; db/a_dpfifo_oq21.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/a_dpfifo_oq21.tdf ; -; db/altsyncram_gj81.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_gj81.tdf ; -; db/cmpr_br8.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_br8.tdf ; -; db/cntr_omb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_omb.tdf ; -; db/cntr_5n7.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_5n7.tdf ; -; db/cntr_pmb.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_pmb.tdf ; -; db/altsyncram_rb92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_rb92.tdf ; -; db/altsyncram_pf92.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_pf92.tdf ; -; db/mux_96e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_96e.tdf ; -; db/mux_mpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_mpe.tdf ; -; db/mux_f6e.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_f6e.tdf ; -; lpm_constant.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_constant.tdf ; -; altddio_out.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/altddio_out.tdf ; -; db/ddio_out_o2f.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_o2f.tdf ; -; db/mux_kpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_kpe.tdf ; -; db/mux_npe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_npe.tdf ; -; db/mux_gpe.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mux_gpe.tdf ; -; db/ddio_out_are.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_are.tdf ; -; db/altpll_isv2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_isv2.tdf ; -; altpll4.tdf ; yes ; Auto-Found Wizard-Generated File ; C:/FireBee/FPGA/altpll4.tdf ; -; altpll.inc ; yes ; Auto-Found AHDL File ; c:/altera/91sp2/quartus/libraries/megafunctions/altpll.inc ; -; db/altpll_c6j2.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altpll_c6j2.tdf ; -; altpll_reconfig1.tdf ; yes ; Auto-Found Wizard-Generated File ; C:/FireBee/FPGA/altpll_reconfig1.tdf ; -; altpll_reconfig1_pllrcfg_t4q.tdf ; yes ; Auto-Found AHDL File ; C:/FireBee/FPGA/altpll_reconfig1_pllrcfg_t4q.tdf ; -; altsyncram.inc ; yes ; Auto-Found AHDL File ; c:/altera/91sp2/quartus/libraries/megafunctions/altsyncram.inc ; -; db/altsyncram_46r.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/altsyncram_46r.tdf ; -; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_add_sub.tdf ; -; db/add_sub_hpa.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/add_sub_hpa.tdf ; -; db/add_sub_k8a.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/add_sub_k8a.tdf ; -; lpm_compare.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_compare.tdf ; -; db/cmpr_tnd.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cmpr_tnd.tdf ; -; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_counter.tdf ; -; db/cntr_30l.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_30l.tdf ; -; db/cntr_qij.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_qij.tdf ; -; db/cntr_pij.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_pij.tdf ; -; db/cntr_9cj.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_9cj.tdf ; -; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_decode.tdf ; -; db/decode_2af.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/decode_2af.tdf ; -; db/cntr_mph.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/cntr_mph.tdf ; -; db/ddio_out_31f.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/ddio_out_31f.tdf ; -; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/91sp2/quartus/libraries/megafunctions/lpm_mult.tdf ; -; db/mult_cat.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mult_cat.tdf ; -; db/mult_aat.tdf ; yes ; Auto-Generated Megafunction ; C:/FireBee/FPGA/db/mult_aat.tdf ; -+----------------------------------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+----------------+ -; Resource ; Usage ; -+---------------------------------------------+----------------+ -; Estimated Total logic elements ; 10,706 ; -; ; ; -; Total combinational functions ; 8060 ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 4947 ; -; -- 3 input functions ; 1867 ; -; -- <=2 input functions ; 1246 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 7261 ; -; -- arithmetic mode ; 799 ; -; ; ; -; Total registers ; 4740 ; -; -- Dedicated logic registers ; 4612 ; -; -- I/O registers ; 256 ; -; ; ; -; I/O pins ; 295 ; -; Total memory bits ; 109344 ; -; Embedded Multiplier 9-bit elements ; 6 ; -; Total PLLs ; 4 ; -; Maximum fan-out node ; MAIN_CLK~input ; -; Maximum fan-out ; 2327 ; -; Total fan-out ; 49317 ; -; Average fan-out ; 3.57 ; -+---------------------------------------------+----------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; -+-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -; |firebee1 ; 8060 (10) ; 4612 (0) ; 109344 ; 6 ; 0 ; 3 ; 295 ; 0 ; |firebee1 ; work ; -; |DSP:Mathias_Alles| ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|DSP:Mathias_Alles ; ; -; |FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden| ; 3814 (634) ; 1633 (114) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden ; ; -; |WF1772IP_TOP_SOC:I_FDC| ; 944 (24) ; 406 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC ; ; -; |WF1772IP_AM_DETECTOR:I_AM_DETECTOR| ; 39 (39) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR ; ; -; |WF1772IP_CONTROL:I_CONTROL| ; 533 (533) ; 197 (197) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL ; ; -; |WF1772IP_CRC_LOGIC:I_CRC_LOGIC| ; 40 (40) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC ; ; -; |WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL| ; 104 (104) ; 38 (38) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; ; -; |WF1772IP_REGISTERS:I_REGISTERS| ; 86 (86) ; 48 (48) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS ; ; -; |WF1772IP_TRANSCEIVER:I_TRANSCEIVER| ; 118 (118) ; 80 (80) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER ; ; -; |WF2149IP_TOP_SOC:I_SOUND| ; 445 (32) ; 210 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND ; ; -; |WF2149IP_WAVE:I_PSG_WAVE| ; 413 (413) ; 181 (181) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE ; ; -; |WF5380_TOP_SOC:I_SCSI| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI ; ; -; |WF5380_CONTROL:I_CONTROL| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL ; ; -; |WF6850IP_TOP_SOC:I_ACIA_KEYBOARD| ; 199 (2) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD ; ; -; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 16 (16) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; -; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 94 (94) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; -; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; -; |WF6850IP_TOP_SOC:I_ACIA_MIDI| ; 203 (2) ; 97 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI ; ; -; |WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS| ; 20 (20) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS ; ; -; |WF6850IP_RECEIVE:I_UART_RECEIVE| ; 94 (94) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE ; ; -; |WF6850IP_TRANSMIT:I_UART_TRANSMIT| ; 87 (87) ; 39 (39) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT ; ; -; |WF68901IP_TOP_SOC:I_MFP| ; 1199 (178) ; 460 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP ; ; -; |WF68901IP_GPIO:I_GPIO| ; 25 (25) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO ; ; -; |WF68901IP_INTERRUPTS:I_INTERRUPTS| ; 273 (273) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS ; ; -; |WF68901IP_TIMERS:I_TIMERS| ; 434 (434) ; 166 (166) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS ; ; -; |WF68901IP_USART_TOP:I_USART| ; 289 (4) ; 140 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART ; ; -; |WF68901IP_USART_CTRL:I_USART_CTRL| ; 38 (38) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL ; ; -; |WF68901IP_USART_RX:I_USART_RECEIVE| ; 159 (159) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE ; ; -; |WF68901IP_USART_TX:I_USART_TRANSMIT| ; 88 (88) ; 35 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT ; ; -; |dcfifo0:RDF| ; 94 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF ; ; -; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 94 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; -; |dcfifo_0hh1:auto_generated| ; 94 (17) ; 124 (42) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; ; -; |a_gray2bin_lfb:wrptr_g_gray2bin| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin ; ; -; |a_gray2bin_lfb:ws_dgrp_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:ws_dgrp_gray2bin ; ; -; |a_graycounter_fic:wrptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; ; -; |a_graycounter_k47:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; ; -; |alt_synch_pipe_ikd:rs_dgwp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; ; -; |dffpipe_hd9:dffpipe12| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; ; -; |alt_synch_pipe_jkd:ws_dgrp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; ; -; |dffpipe_id9:dffpipe17| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; ; -; |altsyncram_bi31:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; ; -; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; -; |cmpr_156:wrfull_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:wrfull_eq_comp1_msb ; ; -; |cntr_t2e:cntr_b| ; 3 (3) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b ; ; -; |dffpipe_gd9:ws_brp| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; ; -; |dffpipe_pe9:ws_bwp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; ; -; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; -; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; -; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; -; |mux_a18:wrfull_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; -; |dcfifo1:WRF| ; 96 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF ; ; -; |dcfifo_mixed_widths:dcfifo_mixed_widths_component| ; 96 (0) ; 124 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; ; -; |dcfifo_3fh1:auto_generated| ; 96 (18) ; 124 (42) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; ; -; |a_gray2bin_lfb:rdptr_g_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rdptr_g_gray2bin ; ; -; |a_gray2bin_lfb:rs_dgwp_gray2bin| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_gray2bin_lfb:rs_dgwp_gray2bin ; ; -; |a_graycounter_gic:wrptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; ; -; |a_graycounter_j47:rdptr_g1p| ; 16 (16) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; ; -; |alt_synch_pipe_kkd:rs_dgwp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; ; -; |dffpipe_jd9:dffpipe12| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; ; -; |alt_synch_pipe_lkd:ws_dgrp| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; ; -; |dffpipe_kd9:dffpipe15| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; ; -; |altsyncram_ci31:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; ; -; |cmpr_156:rdempty_eq_comp1_msb| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb ; ; -; |cntr_t2e:cntr_b| ; 4 (4) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b ; ; -; |dffpipe_gd9:rs_bwp| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; ; -; |dffpipe_pe9:rs_brp| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; ; -; |mux_a18:rdemp_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux ; ; -; |mux_a18:rdemp_eq_comp_msb_mux| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:rdemp_eq_comp_msb_mux ; ; -; |mux_a18:wrfull_eq_comp_lsb_mux| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_lsb_mux ; ; -; |mux_a18:wrfull_eq_comp_msb_mux| ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|mux_a18:wrfull_eq_comp_msb_mux ; ; -; |Video:Fredi_Aschwanden| ; 3109 (10) ; 2172 (4) ; 92816 ; 6 ; 0 ; 3 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden ; ; -; |DDR_CTR:DDR_CTR| ; 348 (314) ; 158 (158) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR ; ; -; |lpm_bustri_BYT:$00002| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002 ; ; -; |lpm_bustri:lpm_bustri_component| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00004| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004 ; ; -; |lpm_bustri:lpm_bustri_component| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; -; |VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR| ; 1260 (1013) ; 529 (529) ; 0 ; 6 ; 0 ; 3 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR ; ; -; |lpm_bustri_WORD:$00000| ; 187 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000 ; ; -; |lpm_bustri:lpm_bustri_component| ; 187 (187) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_WORD:$00002| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002 ; ; -; |lpm_bustri:lpm_bustri_component| ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; ; -; |lpm_mult:op_12| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; ; -; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12|mult_aat:auto_generated ; ; -; |lpm_mult:op_14| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; ; -; |mult_cat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14|mult_cat:auto_generated ; ; -; |lpm_mult:op_6| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; ; -; |mult_aat:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 2 ; 0 ; 1 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6|mult_aat:auto_generated ; ; -; |altddio_bidir0:inst1| ; 0 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1 ; ; -; |altddio_bidir:altddio_bidir_component| ; 0 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; ; -; |ddio_bidir_3jl:auto_generated| ; 0 (0) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; ; -; |altddio_out0:inst2| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; ; -; |ddio_out_are:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; ; -; |altddio_out2:inst5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; ; -; |ddio_out_o2f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; ; -; |altdpram0:ST_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; ; -; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; -; |altdpram0:ST_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; ; -; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; -; |altdpram0:ST_CLUT_RED| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; ; -; |altsyncram_rb92:auto_generated| ; 0 (0) ; 0 (0) ; 48 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; ; -; |altdpram1:FALCON_CLUT_BLUE| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; ; -; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; -; |altdpram1:FALCON_CLUT_GREEN| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; ; -; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; -; |altdpram1:FALCON_CLUT_RED| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; ; -; |altsyncram_lf92:auto_generated| ; 0 (0) ; 0 (0) ; 1536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; ; -; |altdpram2:ACP_CLUT_RAM54| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54 ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; ; -; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; -; |altdpram2:ACP_CLUT_RAM55| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55 ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; ; -; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; -; |altdpram2:ACP_CLUT_RAM| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM ; ; -; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; ; -; |altsyncram_pf92:auto_generated| ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; ; -; |lpm_bustri_LONG:inst119| ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119 ; ; -; |lpm_bustri:lpm_bustri_component| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; ; -; |lpm_ff0:inst13| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst14| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst15| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst16| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst17| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst18| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; ; -; |lpm_ff0:inst19| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst12| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst20| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst3| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst4| ; 0 (0) ; 32 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; ; -; |lpm_ff1:inst9| ; 0 (0) ; 24 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst46| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst47| ; 0 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst49| ; 0 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; ; -; |lpm_ff3:inst52| ; 0 (0) ; 9 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; ; -; |lpm_ff4:inst10| ; 0 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; ; -; |lpm_ff5:inst11| ; 0 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; ; -; |lpm_ff5:inst97| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; ; -; |lpm_ff6:inst71| ; 0 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; ; -; |lpm_ff6:inst94| ; 0 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; ; -; |lpm_fifoDZ:inst63| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63 ; ; -; |scfifo:scfifo_component| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; ; -; |scfifo_lk21:auto_generated| ; 22 (0) ; 21 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated ; ; -; |a_dpfifo_oq21:dpfifo| ; 22 (9) ; 21 (8) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo ; ; -; |altsyncram_gj81:FIFOram| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; ; -; |cntr_omb:rd_ptr_msb| ; 6 (6) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb ; ; -; |cntr_pmb:wr_ptr| ; 7 (7) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr ; ; -; |lpm_fifo_dc0:inst| ; 66 (0) ; 98 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst ; ; -; |dcfifo:dcfifo_component| ; 66 (0) ; 98 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; ; -; |dcfifo_8fi1:auto_generated| ; 66 (12) ; 98 (20) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; ; -; |a_gray2bin_tgb:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin ; ; -; |a_gray2bin_tgb:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:ws_dgrp_gray2bin ; ; -; |a_graycounter_njc:wrptr_gp| ; 17 (17) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; ; -; |a_graycounter_s57:rdptr_g1p| ; 19 (19) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; ; -; |alt_synch_pipe_sld:ws_dgrp| ; 0 (0) ; 30 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; ; -; |dffpipe_re9:dffpipe22| ; 0 (0) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; ; -; |altsyncram_tl31:fifo_ram| ; 0 (0) ; 0 (0) ; 65536 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; ; -; |dffpipe_9d9:wraclr| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; ; -; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; ; -; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; ; -; |lpm_latch0:inst27| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27 ; ; -; |lpm_latch:lpm_latch_component| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; ; -; |lpm_mux0:inst21| ; 48 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21 ; ; -; |lpm_mux:lpm_mux_component| ; 48 (0) ; 96 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component ; ; -; |mux_gpe:auto_generated| ; 48 (48) ; 96 (96) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated ; ; -; |lpm_mux1:inst24| ; 80 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24 ; ; -; |lpm_mux:lpm_mux_component| ; 80 (0) ; 81 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component ; ; -; |mux_npe:auto_generated| ; 80 (80) ; 81 (81) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated ; ; -; |lpm_mux2:inst25| ; 80 (0) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25 ; ; -; |lpm_mux:lpm_mux_component| ; 80 (0) ; 41 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component ; ; -; |mux_mpe:auto_generated| ; 80 (80) ; 41 (41) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated ; ; -; |lpm_mux3:inst102| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102 ; ; -; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component ; ; -; |mux_96e:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux3:inst102|lpm_mux:lpm_mux_component|mux_96e:auto_generated ; ; -; |lpm_mux4:inst81| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81 ; ; -; |lpm_mux:lpm_mux_component| ; 7 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component ; ; -; |mux_f6e:auto_generated| ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux4:inst81|lpm_mux:lpm_mux_component|mux_f6e:auto_generated ; ; -; |lpm_mux5:inst22| ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22 ; ; -; |lpm_mux:lpm_mux_component| ; 64 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component ; ; -; |mux_58e:auto_generated| ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated ; ; -; |lpm_mux6:inst7| ; 90 (0) ; 67 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7 ; ; -; |lpm_mux:lpm_mux_component| ; 90 (0) ; 67 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component ; ; -; |mux_kpe:auto_generated| ; 90 (90) ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated ; ; -; |lpm_muxDZ:inst62| ; 128 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62 ; ; -; |lpm_mux:lpm_mux_component| ; 128 (0) ; 128 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component ; ; -; |mux_dcf:auto_generated| ; 128 (128) ; 128 (128) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated ; ; -; |lpm_muxVDM:inst100| ; 736 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100 ; ; -; |lpm_mux:lpm_mux_component| ; 736 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component ; ; -; |mux_bbe:auto_generated| ; 736 (736) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_muxVDM:inst100|lpm_mux:lpm_mux_component|mux_bbe:auto_generated ; ; -; |lpm_shiftreg0:sr0| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr1| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr2| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr3| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr4| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr5| ; 15 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 15 (15) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr6| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg0:sr7| ; 16 (0) ; 16 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 16 (16) ; 16 (16) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg4:inst26| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; ; -; |lpm_shiftreg6:inst92| ; 0 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92 ; ; -; |lpm_shiftreg:lpm_shiftreg_component| ; 0 (0) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; ; -; |mux41:inst40| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst40 ; ; -; |mux41:inst41| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst41 ; ; -; |mux41:inst42| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst42 ; ; -; |mux41:inst43| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst43 ; ; -; |mux41:inst44| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst44 ; ; -; |mux41:inst45| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|Video:Fredi_Aschwanden|mux41:inst45 ; ; -; |altddio_out3:inst5| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component ; ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; -; |altddio_out3:inst6| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component ; ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; -; |altddio_out3:inst8| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8 ; ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component ; ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; ; -; |altddio_out3:inst9| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9 ; work ; -; |altddio_out:altddio_out_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component ; work ; -; |ddio_out_31f:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; work ; -; |altpll1:inst| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst ; ; -; |altpll:altpll_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst|altpll:altpll_component ; ; -; |altpll_pul2:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated ; ; -; |altpll2:inst12| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12 ; ; -; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12|altpll:altpll_component ; ; -; |altpll_isv2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated ; ; -; |altpll3:inst13| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13 ; ; -; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13|altpll:altpll_component ; ; -; |altpll_41p2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated ; ; -; |altpll4:inst22| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22 ; ; -; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22|altpll:altpll_component ; ; -; |altpll_c6j2:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; ; -; |altpll_reconfig1:inst7| ; 309 (0) ; 128 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7 ; ; -; |altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component| ; 309 (211) ; 128 (80) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; ; -; |altsyncram:altsyncram4| ; 0 (0) ; 0 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; ; -; |altsyncram_46r:auto_generated| ; 0 (0) ; 0 (0) ; 144 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; ; -; |lpm_compare:cmpr7| ; 3 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; ; -; |cmpr_tnd:auto_generated| ; 3 (3) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated ; ; -; |lpm_counter:cntr12| ; 10 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; ; -; |cntr_30l:auto_generated| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated ; ; -; |lpm_counter:cntr13| ; 7 (0) ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; ; -; |cntr_qij:auto_generated| ; 7 (7) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated ; ; -; |lpm_counter:cntr14| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; ; -; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated ; ; -; |lpm_counter:cntr15| ; 18 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; ; -; |cntr_30l:auto_generated| ; 18 (18) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated ; ; -; |lpm_counter:cntr1| ; 41 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; ; -; |cntr_30l:auto_generated| ; 41 (41) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated ; ; -; |lpm_counter:cntr2| ; 9 (0) ; 8 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; ; -; |cntr_9cj:auto_generated| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated ; ; -; |lpm_counter:cntr3| ; 5 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; ; -; |cntr_pij:auto_generated| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated ; ; -; |interrupt_handler:nobody| ; 789 (711) ; 633 (633) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody ; ; -; |lpm_bustri_BYT:$00000| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000 ; ; -; |lpm_bustri:lpm_bustri_component| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00002| ; 24 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002 ; ; -; |lpm_bustri:lpm_bustri_component| ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00004| ; 16 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004 ; ; -; |lpm_bustri:lpm_bustri_component| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; ; -; |lpm_bustri_BYT:$00006| ; 22 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006 ; ; -; |lpm_bustri:lpm_bustri_component| ; 22 (22) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; ; -; |lpm_counter0:inst18| ; 18 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18 ; ; -; |lpm_counter:lpm_counter_component| ; 18 (0) ; 18 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component ; ; -; |cntr_mph:auto_generated| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated ; ; -; |lpm_ff0:inst1| ; 0 (0) ; 28 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_ff0:inst1 ; ; -; |lpm_ff:lpm_ff_component| ; 0 (0) ; 28 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |firebee1|lpm_ff0:inst1|lpm_ff:lpm_ff_component ; ; -+-----------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis RAM Summary ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ -; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 1024 ; 8 ; 256 ; 32 ; 8192 ; None ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 256 ; 32 ; 1024 ; 8 ; 8192 ; None ; -; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; -; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; -; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 16 ; 3 ; 16 ; 3 ; 48 ; None ; -; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; -; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; -; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 6 ; 256 ; 6 ; 1536 ; None ; -; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; -; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; -; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 8 ; 256 ; 8 ; 2048 ; None ; -; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 128 ; 128 ; 128 ; 128 ; 16384 ; None ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 512 ; 128 ; 512 ; 128 ; 65536 ; None ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 144 ; 1 ; -- ; -- ; 144 ; None ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis DSP Block Usage Summary ; -+---------------------------------------+-------------+ -; Statistic ; Number Used ; -+---------------------------------------+-------------+ -; Simple Multipliers (9-bit) ; 0 ; -; Simple Multipliers (18-bit) ; 3 ; -; Embedded Multiplier Blocks ; -- ; -; Embedded Multiplier 9-bit elements ; 6 ; -; Signed Embedded Multipliers ; 0 ; -; Unsigned Embedded Multipliers ; 3 ; -; Mixed Sign Embedded Multipliers ; 0 ; -; Variable Sign Embedded Multipliers ; 0 ; -; Dedicated Input Shift Register Chains ; 0 ; -+---------------------------------------+-------------+ -Note: number of Embedded Multiplier Blocks used is only available after a successful fit. - - -Encoding Type: One-Hot -+----------------------------------------------------------------------------+ -; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FB_REGDDR ; -+---------+-------+-------+-------+-------+----------------------------------+ -; Name ; FR_S3 ; FR_S2 ; FR_S1 ; FR_S0 ; FR_WAIT ; -+---------+-------+-------+-------+-------+----------------------------------+ -; FR_WAIT ; 0 ; 0 ; 0 ; 0 ; 0 ; -; FR_S0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; FR_S1 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; FR_S2 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; FR_S3 ; 1 ; 0 ; 0 ; 0 ; 1 ; -+---------+-------+-------+-------+-------+----------------------------------+ - - -Encoding Type: One-Hot -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SM ; -+---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ -; Name ; DS_R6 ; DS_R5 ; DS_R4 ; DS_R3 ; DS_R2 ; DS_CB8 ; DS_CB6 ; DS_T10F ; DS_T9F ; DS_T8F ; DS_T7F ; DS_T6F ; DS_T5F ; DS_T4F ; DS_T9W ; DS_T8W ; DS_T7W ; DS_T6W ; DS_T5W ; DS_T4W ; DS_T5R ; DS_T4R ; DS_C7 ; DS_C6 ; DS_C5 ; DS_C4 ; DS_C3 ; DS_C2 ; DS_N8 ; DS_N7 ; DS_N6 ; DS_N5 ; DS_T3 ; DS_T2B ; DS_T2A ; DS_T1 ; -+---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ -; DS_T1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DS_T2A ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; DS_T2B ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; DS_T3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; DS_N5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; DS_N6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_N7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_N8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_C2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_C3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_C4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_C5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_C6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_C7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T4R ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T5R ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T4W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T5W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T6W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T7W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T8W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T9W ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T4F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T5F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T6F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T7F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T8F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T9F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_T10F ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_CB6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_CB8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_R2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_R3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_R4 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_R5 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; DS_R6 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+---------+-------+-------+-------+-------+-------+--------+--------+---------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+-------+--------+--------+-------+ - - -Encoding Type: One-Hot -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE ; -+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ -; Name ; FCF_STATE.FCF_T7 ; FCF_STATE.FCF_T6 ; FCF_STATE.FCF_T3 ; FCF_STATE.FCF_T2 ; FCF_STATE.FCF_T1 ; FCF_STATE.FCF_T0 ; FCF_STATE.FCF_IDLE ; -+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ -; FCF_STATE.FCF_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; FCF_STATE.FCF_T0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; FCF_STATE.FCF_T1 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; FCF_STATE.FCF_T2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; FCF_STATE.FCF_T3 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; FCF_STATE.FCF_T6 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; FCF_STATE.FCF_T7 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+--------------------+------------------+------------------+------------------+------------------+------------------+------------------+--------------------+ - - -Encoding Type: One-Hot -+---------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE ; -+----------------+--------------+--------------+--------------+-------------------------------------+ -; Name ; CMD_STATE.T7 ; CMD_STATE.T6 ; CMD_STATE.T1 ; CMD_STATE.IDLE ; -+----------------+--------------+--------------+--------------+-------------------------------------+ -; CMD_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; -; CMD_STATE.T1 ; 0 ; 0 ; 1 ; 1 ; -; CMD_STATE.T6 ; 0 ; 1 ; 0 ; 1 ; -; CMD_STATE.T7 ; 1 ; 0 ; 0 ; 1 ; -+----------------+--------------+--------------+--------------+-------------------------------------+ - - -Encoding Type: One-Hot -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE ; -+----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ -; Name ; INT_STATE.VECTOR_OUT ; INT_STATE.REQUEST ; INT_STATE.SCAN ; -+----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ -; INT_STATE.SCAN ; 0 ; 0 ; 0 ; -; INT_STATE.REQUEST ; 0 ; 1 ; 1 ; -; INT_STATE.VECTOR_OUT ; 1 ; 0 ; 1 ; -+----------------------+----------------------+-------------------+-------------------------------------------------------------------------------------------+ - - -Encoding Type: One-Hot -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|TR_STATE ; -+----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ -; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.CHECK_BREAK ; TR_STATE.IDLE ; -+----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ -; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TR_STATE.CHECK_BREAK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+----------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------+------------------------------+ - - -Encoding Type: One-Hot -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_STATE ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ -; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ -; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-------------------------------------------------+ - - -Encoding Type: One-Hot -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ; -+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ -; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE ; -+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ -; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+------------------------------+ - - -Encoding Type: One-Hot -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ -; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ -; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+-----------------------+ - - -Encoding Type: One-Hot -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE ; -+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ -; Name ; TR_STATE.STOP2 ; TR_STATE.STOP1 ; TR_STATE.PARITY ; TR_STATE.SHIFTOUT ; TR_STATE.START ; TR_STATE.LOAD_SHFT ; TR_STATE.IDLE ; -+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ -; TR_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; TR_STATE.LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; TR_STATE.START ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; TR_STATE.SHIFTOUT ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; TR_STATE.PARITY ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.STOP1 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; TR_STATE.STOP2 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+--------------------+----------------+----------------+-----------------+-------------------+----------------+--------------------+----------------------------------+ - - -Encoding Type: One-Hot -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_STATE ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ -; Name ; RCV_STATE.SYNC ; RCV_STATE.STOP2 ; RCV_STATE.STOP1 ; RCV_STATE.PARITY ; RCV_STATE.SAMPLE ; RCV_STATE.WAIT_START ; RCV_STATE.IDLE ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ -; RCV_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; RCV_STATE.WAIT_START ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; RCV_STATE.SAMPLE ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; RCV_STATE.PARITY ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; RCV_STATE.STOP1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; RCV_STATE.STOP2 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; RCV_STATE.SYNC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+----------------------+----------------+-----------------+-----------------+------------------+------------------+----------------------+---------------------------+ - - -Encoding Type: One-Hot -+--------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE ; -+----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ -; Name ; DMA_STATE.DMA_STEP_4 ; DMA_STATE.DMA_STEP_3 ; DMA_STATE.DMA_STEP_2 ; DMA_STATE.DMA_STEP_1 ; DMA_STATE.IDLE ; -+----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ -; DMA_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; -; DMA_STATE.DMA_STEP_1 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; DMA_STATE.DMA_STEP_2 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; DMA_STATE.DMA_STEP_3 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; DMA_STATE.DMA_STEP_4 ; 1 ; 0 ; 0 ; 0 ; 1 ; -+----------------------+----------------------+----------------------+----------------------+----------------------+-------------------------------+ - - -Encoding Type: One-Hot -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE ; -+-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ -; Name ; CTRL_STATE.DMA_INIT_RCV ; CTRL_STATE.DMA_TARG_RCV ; CTRL_STATE.DMA_SEND ; CTRL_STATE.WAIT_2200ns ; CTRL_STATE.WAIT_800ns ; CTRL_STATE.IDLE ; -+-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ -; CTRL_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; CTRL_STATE.WAIT_800ns ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; CTRL_STATE.WAIT_2200ns ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; CTRL_STATE.DMA_SEND ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; CTRL_STATE.DMA_TARG_RCV ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; CTRL_STATE.DMA_INIT_RCV ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+-------------------------+-------------------------+-------------------------+---------------------+------------------------+-----------------------+-----------------+ - - -Encoding Type: One-Hot -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|PRECOMP ; -+-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ -; Name ; PRECOMP.LATE ; PRECOMP.EARLY ; PRECOMP.NOMINAL ; -+-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ -; PRECOMP.NOMINAL ; 0 ; 0 ; 0 ; -; PRECOMP.EARLY ; 0 ; 1 ; 1 ; -; PRECOMP.LATE ; 1 ; 0 ; 1 ; -+-----------------+--------------+---------------+----------------------------------------------------------------------------------------------------------+ - - -Encoding Type: One-Hot -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE ; -+----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ -; Name ; MFM_STATE.C_10 ; MFM_STATE.B_01 ; MFM_STATE.A_00 ; -+----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ -; MFM_STATE.A_00 ; 0 ; 0 ; 0 ; -; MFM_STATE.B_01 ; 0 ; 1 ; 1 ; -; MFM_STATE.C_10 ; 1 ; 0 ; 1 ; -+----------------+----------------+----------------+----------------------------------------------------------------------------------------------------------+ - - -Encoding Type: One-Hot -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; State Machine - |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; -+----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ -; Name ; CMD_STATE.T3_VERIFY_CRC ; CMD_STATE.T3_LOAD_SR ; CMD_STATE.T3_CHECK_RD ; CMD_STATE.T3_SET_DRQ_2 ; CMD_STATE.T3_LOAD_DATA_2 ; CMD_STATE.T3_SHIFT_ADR ; CMD_STATE.T3_VERIFY_AM ; CMD_STATE.T3_RD_ADR ; CMD_STATE.T3_SET_DRQ_1 ; CMD_STATE.T3_LOAD_DATA_1 ; CMD_STATE.T3_CHECK_DR ; CMD_STATE.T3_CHECK_BYTE ; CMD_STATE.T3_DETECT_AM ; CMD_STATE.T3_CHECK_INDEX_3 ; CMD_STATE.T3_SHIFT ; CMD_STATE.T3_RD_TRACK ; CMD_STATE.T3_DATALOST ; CMD_STATE.T3_CHECK_INDEX_2 ; CMD_STATE.T3_WR_DATA ; CMD_STATE.T3_LOAD_SHFT ; CMD_STATE.T3_CHECK_INDEX_1 ; CMD_STATE.T3_VERIFY_DRQ ; CMD_STATE.T3_DELAY_B3 ; CMD_STATE.T3_WR ; CMD_STATE.T2_WR_FF ; CMD_STATE.T2_WR_CRC ; CMD_STATE.T2_WRSTAT ; CMD_STATE.T2_DATALOST ; CMD_STATE.T2_VERIFY_DRQ_3 ; CMD_STATE.T2_WR_BYTE ; CMD_STATE.T2_LOAD_SHFT ; CMD_STATE.T2_WR_AM ; CMD_STATE.T2_WR_LEADIN ; CMD_STATE.T2_DELAY_B11 ; CMD_STATE.T2_CHECK_MODE ; CMD_STATE.T2_DELAY_B1 ; CMD_STATE.T2_VERIFY_DRQ_2 ; CMD_STATE.T2_DELAY_B8 ; CMD_STATE.T2_SET_DRQ ; CMD_STATE.T2_DELAY_B2 ; CMD_STATE.T2_MULTISECT ; CMD_STATE.T2_VERIFY_CRC_2 ; CMD_STATE.T2_RDSTAT ; CMD_STATE.T2_VERIFY_DRQ_1 ; CMD_STATE.T2_NEXTBYTE ; CMD_STATE.T2_LOAD_DATA ; CMD_STATE.T2_FIRSTBYTE ; CMD_STATE.T2_VERIFY_AM ; CMD_STATE.T2_VERIFY_CRC_1 ; CMD_STATE.T2_SCAN_LEN ; CMD_STATE.T2_SCAN_SECT ; CMD_STATE.T2_SCAN_TRACK ; CMD_STATE.T2_INIT ; CMD_STATE.T2_RD_WR_SECT ; CMD_STATE.T1_VERIFY_CRC ; CMD_STATE.T1_VERIFY_DELAY ; CMD_STATE.T1_SCAN_CRC ; CMD_STATE.T1_SCAN_TRACK ; CMD_STATE.T1_SPINDOWN ; CMD_STATE.T1_STEP_DELAY ; CMD_STATE.T1_TRAP ; CMD_STATE.T1_STEP ; CMD_STATE.T1_HEAD_CTRL ; CMD_STATE.T1_CHECK_DIR ; CMD_STATE.T1_COMP_TR_DSR ; CMD_STATE.T1_LOAD_SHFT ; CMD_STATE.T1_STEPPING ; CMD_STATE.T1_SEEK_RESTORE ; CMD_STATE.DECODE ; CMD_STATE.DELAY_15MS ; CMD_STATE.SPINUP ; CMD_STATE.INIT ; CMD_STATE.IDLE ; -+----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ -; CMD_STATE.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; -; CMD_STATE.INIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ; -; CMD_STATE.SPINUP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ; -; CMD_STATE.DELAY_15MS ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; -; CMD_STATE.DECODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_SEEK_RESTORE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_STEPPING ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_COMP_TR_DSR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_CHECK_DIR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_HEAD_CTRL ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_STEP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_TRAP ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_STEP_DELAY ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_SPINDOWN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_SCAN_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_SCAN_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_VERIFY_DELAY ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T1_VERIFY_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_RD_WR_SECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_INIT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_SCAN_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_SCAN_SECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_SCAN_LEN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_VERIFY_CRC_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_VERIFY_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_FIRSTBYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_LOAD_DATA ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_NEXTBYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_VERIFY_DRQ_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_RDSTAT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_VERIFY_CRC_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_MULTISECT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_DELAY_B2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_SET_DRQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_DELAY_B8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_VERIFY_DRQ_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_DELAY_B1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_CHECK_MODE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_DELAY_B11 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_WR_LEADIN ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_WR_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_WR_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_VERIFY_DRQ_3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_DATALOST ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_WRSTAT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_WR_CRC ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T2_WR_FF ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_WR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_DELAY_B3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_VERIFY_DRQ ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_CHECK_INDEX_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_LOAD_SHFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_WR_DATA ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_CHECK_INDEX_2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_DATALOST ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_RD_TRACK ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_SHIFT ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_CHECK_INDEX_3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_DETECT_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_CHECK_BYTE ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_CHECK_DR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_LOAD_DATA_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_SET_DRQ_1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_RD_ADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_VERIFY_AM ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_SHIFT_ADR ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_LOAD_DATA_2 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_SET_DRQ_2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_CHECK_RD ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_LOAD_SR ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -; CMD_STATE.T3_VERIFY_CRC ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; -+----------------------------+-------------------------+----------------------+-----------------------+------------------------+--------------------------+------------------------+------------------------+---------------------+------------------------+--------------------------+-----------------------+-------------------------+------------------------+----------------------------+--------------------+-----------------------+-----------------------+----------------------------+----------------------+------------------------+----------------------------+-------------------------+-----------------------+-----------------+--------------------+---------------------+---------------------+-----------------------+---------------------------+----------------------+------------------------+--------------------+------------------------+------------------------+-------------------------+-----------------------+---------------------------+-----------------------+----------------------+-----------------------+------------------------+---------------------------+---------------------+---------------------------+-----------------------+------------------------+------------------------+------------------------+---------------------------+-----------------------+------------------------+-------------------------+-------------------+-------------------------+-------------------------+---------------------------+-----------------------+-------------------------+-----------------------+-------------------------+-------------------+-------------------+------------------------+------------------------+--------------------------+------------------------+-----------------------+---------------------------+------------------+----------------------+------------------+----------------+----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Protected by Synthesis ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ -; Register Name ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[10] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_nominal_data_out_state ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[31] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1 ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3|cntr_pij:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_nominal_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_nominal_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_last_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[30] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[13] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[12] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[11] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[18] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[12] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate3_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate_state ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[25] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[8] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[7] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[16] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[6] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[13] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[22] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[20] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[19] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[15] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[29] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[27] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[11] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[10] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[9] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[6] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[3] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[2] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[0] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[16] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_data_nominal_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_nominal_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_init_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[7] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[9] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[17] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_param_latch_reg[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_nominal_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|write_init_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|counter_type_latch_reg[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|read_first_nominal_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_counter_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_init_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_seq_ena_state ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[15] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[6] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[14] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C0_ena_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C1_ena_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C2_ena_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C3_ena_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|C4_ena_state ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[4] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[5] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[6] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[6] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated|counter_reg_bit[7] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12|cntr_30l:auto_generated|counter_reg_bit[7] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|configupdate2_state ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[9] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[10] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[1] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[11] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[2] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[12] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[3] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[13] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[4] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; no ; yes ; -; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|nominal_data[8] ; no ; yes ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|tmp_seq_ena_state ; no ; yes ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; User-Specified and Inferred Latches ; -+------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ -; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ; -+------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; yes ; -; Number of user-specified and inferred latches = 32 ; ; ; -+------------------------------------------------------------------------------------+--------------------------------------------------------------------------+------------------------+ -Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations. - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Registers Removed During Synthesis ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; interrupt_handler:nobody|INT_LATCH[31] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[31] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[30] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[30] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[29] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[29] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[28] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[28] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[27] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[27] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[26] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[26] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[25] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[25] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[24] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[24] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[23] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[23] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[22] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[22] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[21] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[21] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[20] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[20] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[19] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[19] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[18] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[18] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[17] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[17] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[16] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[16] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[15] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[15] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[14] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[14] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[13] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[13] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[12] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[12] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[11] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[11] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[10] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[10] ; Lost fanout ; -; interrupt_handler:nobody|INT_LATCH[7] ; Stuck at GND due to stuck port clock ; -; interrupt_handler:nobody|INT_CLEAR[7] ; Lost fanout ; -; interrupt_handler:nobody|WERTE[7][13] ; Stuck at VCC due to stuck port data_in ; -; interrupt_handler:nobody|WERTE[6][10] ; Stuck at GND due to stuck port clear ; -; interrupt_handler:nobody|WERTE[2][11] ; Stuck at VCC due to stuck port data_in ; -; interrupt_handler:nobody|WERTE[1][11] ; Stuck at VCC due to stuck port data_in ; -; interrupt_handler:nobody|WERTE[0][11] ; Stuck at VCC due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17] ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0..1,8..9,16..17] ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20] ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0..4,8..12,16..20] ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_REQ ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In ; Lost fanout ; -; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0..6] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0..5] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0..7] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[6] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0,2..5,7] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[0..2] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[0..7] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SPER ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0..2] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6..7] ; Lost fanout ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9] ; Lost fanout ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10] ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8] ; Lost fanout ; -; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[2] ; Merged with Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|NOISE_OUT ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|OE ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\OVERRUN:FIRST_READ ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|OVR ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\OVERRUN:FIRST_READ ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[6] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[7] ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[0..3] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_DRQ:LOCK ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_ACTIVE_I ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4,7] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[1] ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe18 ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe2 ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe20 ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe34 ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe36 ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe4 ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|INT ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DRQ ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[0..7] ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDRWR_D_SEL ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[0..2] ; Merged with Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; -; Video:Fredi_Aschwanden|inst88 ; Merged with Video:Fredi_Aschwanden|inst90 ; -; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[0..2] ; Merged with Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; -; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BLITTER_AC ; Stuck at GND due to stuck port data_in ; -; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[2] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1 ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2 ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3 ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4 ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00 ; Lost fanout ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DELAY_800ns ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[0..3] ; Stuck at GND due to stuck port data_in ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[0] ; Merged with FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12] ; Lost fanout ; -; Total Number of Removed Registers = 223 ; ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Removed Registers Triggering Further Register Optimizations ; -+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Register name ; Reason for Removal ; Registers Removed due to This Register ; -+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_800ns ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DATA_EN, ; -; ; due to stuck port data_in ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\DELAY_800:TMP[2] ; -; interrupt_handler:nobody|INT_LATCH[30] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[30] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[29] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[29] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[28] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[28] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[27] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[27] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[26] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[26] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[25] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[25] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[24] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[24] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[23] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[23] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[22] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[22] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[21] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[21] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[20] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[20] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[19] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[19] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[18] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[18] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[17] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[17] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[16] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[16] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[15] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[15] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[14] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[14] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[13] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[13] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[12] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[12] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[11] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[11] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[10] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[10] ; -; ; due to stuck port clock ; ; -; interrupt_handler:nobody|INT_LATCH[7] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[7] ; -; ; due to stuck port clock ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[17] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[17] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[16] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[16] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[9] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[9] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[8] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[8] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[1] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[1] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[0] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[0] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[20] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[20] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[19] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[19] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[18] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[18] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[17] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[17] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[16] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[16] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[12] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[12] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[11] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[11] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[10] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[10] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[9] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[9] ; -; ; due to stuck port data_in ; ; -; interrupt_handler:nobody|INT_LATCH[31] ; Stuck at GND ; interrupt_handler:nobody|INT_CLEAR[31] ; -; ; due to stuck port clock ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[4] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[4] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[3] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[3] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[2] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[2] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[1] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[1] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[0] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[0] ; -; ; due to stuck port data_in ; ; -; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[8] ; Stuck at GND ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[8] ; -; ; due to stuck port data_in ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTS_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3] ; -; ; due to stuck port data_in ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; -; ; due to stuck port data_in ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[2] ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ICR[4] ; -; ; due to stuck port data_in ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|MR2[0] ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE ; -; ; due to stuck port data_in ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_FLAGn ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|ODR[2] ; -; ; due to stuck port data_in ; ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|DCD_In ; Stuck at GND ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS ; -; ; due to stuck port data_in ; ; -+-----------------------------------------------------------------------------------------------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 4612 ; -; Number of registers using Synchronous Clear ; 156 ; -; Number of registers using Synchronous Load ; 204 ; -; Number of registers using Asynchronous Clear ; 1431 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 2735 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Inverted Register Statistics ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; Inverted Register ; Fan out ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; 4 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[2] ; 5 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[1] ; 5 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0] ; 4 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PER_CNT[7] ; 7 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE ; 7 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TDRE ; 7 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|IRQ_ACIAn ; 2 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb ; 1 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb ; 1 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0 ; 8 ; -; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reset_state ; 2 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_lsb_aeb ; 1 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdemp_eq_comp_msb_aeb ; 1 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6 ; 4 ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; 1 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|counter8a0 ; 8 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p|parity9 ; 4 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; 1 ; -; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; 1 ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; 7 ; -; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; 3 ; -; Total number of inverted registers = 22 ; ; -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[7] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CLK_DIV[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:HI_FLT[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|SHIFT_REG[6] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[2] ; -; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|CTRL_REG[7] ; -; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\P_SAMPLE:FLT_TMP[0] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|SHIFT_REG[4] ; -; 3:1 ; 8 bits ; 16 LEs ; 0 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[7] ; -; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4] ; -; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[4] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[4] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[7] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[6] ; -; 3:1 ; 2 bits ; 4 LEs ; 0 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UCR[3] ; -; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[2] ; -; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; -; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[6] ; -; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[4] ; -; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[2] ; -; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|BITCNT[0] ; -; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|SHIFT_REG[6] ; -; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|BITCNT[0] ; -; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|\CLKDIV:CLK_DIVCNT[0] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_START_BIT:TMP[0] ; -; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:LOW_FLT[0] ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\CLKDIV:CLK_DIVCNT[3] ; -; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[0] ; -; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|BITCNT[1] ; -; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[0] ; -; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|DATA_REG[2] ; -; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[0] ; -; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|DATA_REG[2] ; -; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|BITCNT[0] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[7] ; -; 5:1 ; 21 bits ; 63 LEs ; 42 LEs ; 21 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; -; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[19] ; -; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|SHIFT_REG[1] ; -; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:CNT_NOISE[0] ; -; 4:1 ; 31 bits ; 62 LEs ; 62 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; -; 5:1 ; 3 bits ; 9 LEs ; 6 LEs ; 3 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|\P_SAMPLE:TIMER[1] ; -; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|DATA_REG[4] ; -; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_A:PRESCALE[5] ; -; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_D:PRESCALE[2] ; -; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_B:PRESCALE[1] ; -; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|\PRESCALE_C:PRESCALE[5] ; -; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_D[3] ; -; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_C[0] ; -; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[2] ; -; 7:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[4] ; -; 7:1 ; 7 bits ; 28 LEs ; 14 LEs ; 14 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|\CLKDIV:CLK_DIVCNT[4] ; -; 7:1 ; 7 bits ; 28 LEs ; 21 LEs ; 7 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|\CLKDIV:CLK_DIVCNT[5] ; -; 6:1 ; 8 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[6] ; -; 7:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nIDE_RD~reg0 ; -; 7:1 ; 13 bits ; 52 LEs ; 52 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[10] ; -; 6:1 ; 20 bits ; 80 LEs ; 20 LEs ; 60 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; -; 11:1 ; 2 bits ; 14 LEs ; 10 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[1] ; -; 8:1 ; 5 bits ; 25 LEs ; 20 LEs ; 5 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL|UDR[0] ; -; 9:1 ; 2 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[5] ; -; 14:1 ; 5 bits ; 45 LEs ; 10 LEs ; 35 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[3] ; -; 11:1 ; 8 bits ; 56 LEs ; 16 LEs ; 40 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_B[1] ; -; 11:1 ; 8 bits ; 56 LEs ; 16 LEs ; 40 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_A[1] ; -; 17:1 ; 4 bits ; 44 LEs ; 40 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[2] ; -; 17:1 ; 4 bits ; 44 LEs ; 0 LEs ; 44 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MID[1] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[5] ; -; 3:1 ; 24 bits ; 48 LEs ; 48 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[1] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; -; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[0] ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE|RCV_NEXT_STATE ; -; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE ; -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEXCNT ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[21] ; -; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|DATA_OUT[4] ; -; 3:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|DATA_OUT[1] ; -; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CNT ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE ; -; 3:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE|RCV_NEXT_STATE ; -; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|NEXT_CMD_STATE ; -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_A[1] ; -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_B[2] ; -; 3:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|AMPLITUDE_C[1] ; -; 16:1 ; 8 bits ; 80 LEs ; 24 LEs ; 56 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|DATA_OUT[2] ; -; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|ADDER_IN[1] ; -; 64:1 ; 3 bits ; 126 LEs ; 126 LEs ; 0 LEs ; No ; |firebee1|interrupt_handler:nobody|_ ; -; 17:1 ; 3 bits ; 33 LEs ; 18 LEs ; 15 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[7] ; -; 18:1 ; 4 bits ; 48 LEs ; 44 LEs ; 4 LEs ; No ; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|DA_OUT[2] ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3 ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; -; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; -; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; -; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; wrptr_g ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; -; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe17|dffe18a ; -; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_id9:dffpipe17|dffe18a* ; - ; - ; -; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; -; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a* ; - ; - ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p ; -+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; -; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; -+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; -; POWER_UP_LEVEL ; HIGH ; - ; sub_parity9a0 ; -; POWER_UP_LEVEL ; LOW ; - ; parity8 ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12 ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17 ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 3 ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; -; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; -; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; -; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; wrptr_g ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; -; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe15|dffe16a ; -; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a* ; - ; - ; -; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; -; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a* ; - ; - ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+-------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p ; -+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; POWER_UP_LEVEL ; HIGH ; - ; sub_parity6a0 ; -; POWER_UP_LEVEL ; LOW ; - ; parity5 ; -+----------------+-------+------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; -; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; -; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12 ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ -; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; -+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15 ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; -+---------------------------------+-------+------+----------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+----------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+----------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -; REMOVE_DUPLICATE_REGISTERS ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -; SYNCHRONIZATION_REGISTER_CHAIN_LENGTH ; 4 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; d101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; d102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; R105 ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_lsb_aeb ; -; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_lsb_aeb ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rdemp_eq_comp_msb_aeb ; -; POWER_UP_LEVEL ; HIGH ; - ; rdemp_eq_comp_msb_aeb ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; rs_dgwp_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_lsb_mux_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; wrfull_eq_comp_msb_mux_reg ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; ws_dgrp_reg ; -; CUT ; ON ; rdptr_g ; ws_dgrp|dffpipe22|dffe23a ; -; SDC_STATEMENT ; set_false_path -from *rdptr_g* -to *ws_dgrp|dffpipe_re9:dffpipe22|dffe23a* ; - ; - ; -; CUT ; ON ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a ; -; SDC_STATEMENT ; set_false_path -from *delayed_wrptr_g* -to *rs_dgwp|dffpipe_qe9:dffpipe15|dffe16a* ; - ; - ; -+---------------------------------------+-------------------------------------------------------------------------------------+-----------------+----------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p ; -+----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ -; POWER_UP_LEVEL ; HIGH ; - ; counter5a0 ; -; POWER_UP_LEVEL ; HIGH ; - ; parity6 ; -+----------------+-------+------+----------------------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p ; -+---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; -; POWER_UP_LEVEL ; HIGH ; - ; counter8a0 ; -; POWER_UP_LEVEL ; HIGH ; - ; parity9 ; -+---------------------------+-------+------+-----------------------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; S102 ; - ; - ; -; POWER_UP_LEVEL ; HIGH ; - ; sub_parity12a0 ; -; POWER_UP_LEVEL ; LOW ; - ; parity11 ; -+---------------------------+-------+------+----------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ -; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15 ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ -; X_ON_VIOLATION_OPTION ; OFF ; - ; - ; -; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; - ; - ; -+-----------------------------+------------------------+------+---------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22 ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ -; AUTO_SHIFT_REGISTER_RECOGNITION ; OFF ; - ; - ; -+---------------------------------+-------+------+--------------------------------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; -+---------------------------+-------------+------+---------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+---------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; DDIO_INPUT_REGISTER ; LOW ; - ; input_cell_L ; -; DDIO_INPUT_REGISTER ; HIGH ; - ; input_cell_H ; -; SUPPRESS_DA_RULE_INTERNAL ; D101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; D103 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; D102 ; - ; - ; -+---------------------------+-------------+------+---------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated ; -+-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -; DDIO_INPUT_REGISTER ; HIGH ; - ; input_cell_h ; -; DDIO_INPUT_REGISTER ; LOW ; - ; input_cell_l ; -; MEGAFUNCTION_GENERATED_TRI ; ON ; - ; tri_buf1a ; -+-----------------------------+-------+------+-------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; -+---------------------------------+--------------------+------+--------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+--------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+--------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+---------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated ; -+---------------------------------+--------------------+------+-----------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-----------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-----------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated ; -+---------------------------------+--------------------+------+-----------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+-----------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+-----------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; -+---------------------------+-------------+------+---------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+---------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -+---------------------------+-------------+------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated ; -+-----------------------------+-------+------+-----------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+-----------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -+-----------------------------+-------+------+-----------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; -+---------------------------+-------------+------+---------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+---------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -+---------------------------+-------------+------+---------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated ; -+-----------------------------+-------+------+-----------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+-----------------------------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -+-----------------------------+-------+------+-----------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------+ -; Source assignments for altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated ; -+---------------------------+-------+------+-----------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-----------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -+---------------------------+-------+------+-----------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; -+---------------------------------------+-------------+------+------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------------+-------------+------+------------------------------------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 2 ; - ; le_comb10 ; -; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 0 ; - ; le_comb8 ; -; PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL ; 1 ; - ; le_comb9 ; -; POWER_UP_LEVEL ; LOW ; - ; idle_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_data_nominal_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_data_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_first_nominal_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_first_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_init_nominal_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_init_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_last_nominal_state ; -; POWER_UP_LEVEL ; LOW ; - ; read_last_state ; -; POWER_UP_LEVEL ; LOW ; - ; reconfig_counter_state ; -; POWER_UP_LEVEL ; LOW ; - ; reconfig_init_state ; -; POWER_UP_LEVEL ; LOW ; - ; reconfig_post_state ; -; POWER_UP_LEVEL ; LOW ; - ; reconfig_seq_data_state ; -; POWER_UP_LEVEL ; LOW ; - ; reconfig_seq_ena_state ; -; POWER_UP_LEVEL ; LOW ; - ; reconfig_wait_state ; -; POWER_UP_LEVEL ; HIGH ; - ; reset_state ; -; POWER_UP_LEVEL ; LOW ; - ; write_data_state ; -; POWER_UP_LEVEL ; LOW ; - ; write_init_nominal_state ; -; POWER_UP_LEVEL ; LOW ; - ; write_init_state ; -; POWER_UP_LEVEL ; LOW ; - ; write_nominal_state ; -+---------------------------------------+-------------+------+------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ -; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; -+---------------------------------+--------------------+------+----------------------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+-------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Source assignments for altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+------------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------+ -; Source assignments for lpm_counter0:inst18|lpm_counter:lpm_counter_component ; -+---------------------------+-------+------+-----------------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------+------+-----------------------------------+ -; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ; -+---------------------------+-------+------+-----------------------------------+ - - -+-----------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component ; -+---------------------------+-------------+------+----------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+----------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -+---------------------------+-------------+------+----------------------------+ - - -+---------------------------------------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -+-----------------------------+-------+------+------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component ; -+---------------------------+-------------+------+----------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+----------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -+---------------------------+-------------+------+----------------------------+ - - -+---------------------------------------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -+-----------------------------+-------+------+------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component ; -+---------------------------+-------------+------+----------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+----------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -+---------------------------+-------------+------+----------------------------+ - - -+---------------------------------------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst8|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -+-----------------------------+-------+------+------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component ; -+---------------------------+-------------+------+----------------------------+ -; Assignment ; Value ; From ; To ; -+---------------------------+-------------+------+----------------------------+ -; ADV_NETLIST_OPT_ALLOWED ; NEVER_ALLOW ; - ; - ; -; PRESERVE_REGISTER ; ON ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; LOW ; - ; output_cell_L ; -; DDIO_OUTPUT_REGISTER ; HIGH ; - ; mux ; -; SUPPRESS_DA_RULE_INTERNAL ; C104 ; - ; - ; -; SUPPRESS_DA_RULE_INTERNAL ; C106 ; - ; - ; -+---------------------------+-------------+------+----------------------------+ - - -+---------------------------------------------------------------------------------------------------------+ -; Source assignments for altddio_out3:inst9|altddio_out:altddio_out_component|ddio_out_31f:auto_generated ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; Assignment ; Value ; From ; To ; -+-----------------------------+-------+------+------------------------------------------------------------+ -; SYNCHRONIZER_IDENTIFICATION ; OFF ; - ; - ; -+-----------------------------+-------+------+------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll1:inst|altpll:altpll_component ; -+-------------------------------+--------------------+------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+--------------------+------------------------------+ -; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; -; PLL_TYPE ; AUTO ; Untyped ; -; QUALIFY_CONF_DONE ; OFF ; Untyped ; -; COMPENSATE_CLOCK ; CLK0 ; Untyped ; -; SCAN_CHAIN ; LONG ; Untyped ; -; PRIMARY_CLOCK ; INCLK0 ; Untyped ; -; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; -; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; -; GATE_LOCK_SIGNAL ; NO ; Untyped ; -; GATE_LOCK_COUNTER ; 0 ; Untyped ; -; LOCK_HIGH ; 1 ; Untyped ; -; LOCK_LOW ; 1 ; Untyped ; -; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; -; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; -; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; -; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; -; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; -; SKIP_VCO ; OFF ; Untyped ; -; SWITCH_OVER_COUNTER ; 0 ; Untyped ; -; SWITCH_OVER_TYPE ; AUTO ; Untyped ; -; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; -; BANDWIDTH ; 0 ; Untyped ; -; BANDWIDTH_TYPE ; AUTO ; Untyped ; -; SPREAD_FREQUENCY ; 0 ; Untyped ; -; DOWN_SPREAD ; 0 ; Untyped ; -; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; -; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; -; CLK9_MULTIPLY_BY ; 0 ; Untyped ; -; CLK8_MULTIPLY_BY ; 0 ; Untyped ; -; CLK7_MULTIPLY_BY ; 0 ; Untyped ; -; CLK6_MULTIPLY_BY ; 0 ; Untyped ; -; CLK5_MULTIPLY_BY ; 1 ; Untyped ; -; CLK4_MULTIPLY_BY ; 1 ; Untyped ; -; CLK3_MULTIPLY_BY ; 1 ; Untyped ; -; CLK2_MULTIPLY_BY ; 67 ; Signed Integer ; -; CLK1_MULTIPLY_BY ; 67 ; Signed Integer ; -; CLK0_MULTIPLY_BY ; 1 ; Signed Integer ; -; CLK9_DIVIDE_BY ; 0 ; Untyped ; -; CLK8_DIVIDE_BY ; 0 ; Untyped ; -; CLK7_DIVIDE_BY ; 0 ; Untyped ; -; CLK6_DIVIDE_BY ; 0 ; Untyped ; -; CLK5_DIVIDE_BY ; 1 ; Untyped ; -; CLK4_DIVIDE_BY ; 1 ; Untyped ; -; CLK3_DIVIDE_BY ; 1 ; Untyped ; -; CLK2_DIVIDE_BY ; 90 ; Signed Integer ; -; CLK1_DIVIDE_BY ; 900 ; Signed Integer ; -; CLK0_DIVIDE_BY ; 66 ; Signed Integer ; -; CLK9_PHASE_SHIFT ; 0 ; Untyped ; -; CLK8_PHASE_SHIFT ; 0 ; Untyped ; -; CLK7_PHASE_SHIFT ; 0 ; Untyped ; -; CLK6_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_PHASE_SHIFT ; 0 ; Untyped ; -; CLK4_PHASE_SHIFT ; 0 ; Untyped ; -; CLK3_PHASE_SHIFT ; 0 ; Untyped ; -; CLK2_PHASE_SHIFT ; 0 ; Untyped ; -; CLK1_PHASE_SHIFT ; 0 ; Untyped ; -; CLK0_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_TIME_DELAY ; 0 ; Untyped ; -; CLK4_TIME_DELAY ; 0 ; Untyped ; -; CLK3_TIME_DELAY ; 0 ; Untyped ; -; CLK2_TIME_DELAY ; 0 ; Untyped ; -; CLK1_TIME_DELAY ; 0 ; Untyped ; -; CLK0_TIME_DELAY ; 0 ; Untyped ; -; CLK9_DUTY_CYCLE ; 50 ; Untyped ; -; CLK8_DUTY_CYCLE ; 50 ; Untyped ; -; CLK7_DUTY_CYCLE ; 50 ; Untyped ; -; CLK6_DUTY_CYCLE ; 50 ; Untyped ; -; CLK5_DUTY_CYCLE ; 50 ; Untyped ; -; CLK4_DUTY_CYCLE ; 50 ; Untyped ; -; CLK3_DUTY_CYCLE ; 50 ; Untyped ; -; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; LOCK_WINDOW_UI ; 0.05 ; Untyped ; -; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; -; DPA_MULTIPLY_BY ; 0 ; Untyped ; -; DPA_DIVIDE_BY ; 1 ; Untyped ; -; DPA_DIVIDER ; 0 ; Untyped ; -; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; -; VCO_MULTIPLY_BY ; 0 ; Untyped ; -; VCO_DIVIDE_BY ; 0 ; Untyped ; -; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; -; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; -; VCO_MIN ; 0 ; Untyped ; -; VCO_MAX ; 0 ; Untyped ; -; VCO_CENTER ; 0 ; Untyped ; -; PFD_MIN ; 0 ; Untyped ; -; PFD_MAX ; 0 ; Untyped ; -; M_INITIAL ; 0 ; Untyped ; -; M ; 0 ; Untyped ; -; N ; 1 ; Untyped ; -; M2 ; 1 ; Untyped ; -; N2 ; 1 ; Untyped ; -; SS ; 1 ; Untyped ; -; C0_HIGH ; 0 ; Untyped ; -; C1_HIGH ; 0 ; Untyped ; -; C2_HIGH ; 0 ; Untyped ; -; C3_HIGH ; 0 ; Untyped ; -; C4_HIGH ; 0 ; Untyped ; -; C5_HIGH ; 0 ; Untyped ; -; C6_HIGH ; 0 ; Untyped ; -; C7_HIGH ; 0 ; Untyped ; -; C8_HIGH ; 0 ; Untyped ; -; C9_HIGH ; 0 ; Untyped ; -; C0_LOW ; 0 ; Untyped ; -; C1_LOW ; 0 ; Untyped ; -; C2_LOW ; 0 ; Untyped ; -; C3_LOW ; 0 ; Untyped ; -; C4_LOW ; 0 ; Untyped ; -; C5_LOW ; 0 ; Untyped ; -; C6_LOW ; 0 ; Untyped ; -; C7_LOW ; 0 ; Untyped ; -; C8_LOW ; 0 ; Untyped ; -; C9_LOW ; 0 ; Untyped ; -; C0_INITIAL ; 0 ; Untyped ; -; C1_INITIAL ; 0 ; Untyped ; -; C2_INITIAL ; 0 ; Untyped ; -; C3_INITIAL ; 0 ; Untyped ; -; C4_INITIAL ; 0 ; Untyped ; -; C5_INITIAL ; 0 ; Untyped ; -; C6_INITIAL ; 0 ; Untyped ; -; C7_INITIAL ; 0 ; Untyped ; -; C8_INITIAL ; 0 ; Untyped ; -; C9_INITIAL ; 0 ; Untyped ; -; C0_MODE ; BYPASS ; Untyped ; -; C1_MODE ; BYPASS ; Untyped ; -; C2_MODE ; BYPASS ; Untyped ; -; C3_MODE ; BYPASS ; Untyped ; -; C4_MODE ; BYPASS ; Untyped ; -; C5_MODE ; BYPASS ; Untyped ; -; C6_MODE ; BYPASS ; Untyped ; -; C7_MODE ; BYPASS ; Untyped ; -; C8_MODE ; BYPASS ; Untyped ; -; C9_MODE ; BYPASS ; Untyped ; -; C0_PH ; 0 ; Untyped ; -; C1_PH ; 0 ; Untyped ; -; C2_PH ; 0 ; Untyped ; -; C3_PH ; 0 ; Untyped ; -; C4_PH ; 0 ; Untyped ; -; C5_PH ; 0 ; Untyped ; -; C6_PH ; 0 ; Untyped ; -; C7_PH ; 0 ; Untyped ; -; C8_PH ; 0 ; Untyped ; -; C9_PH ; 0 ; Untyped ; -; L0_HIGH ; 1 ; Untyped ; -; L1_HIGH ; 1 ; Untyped ; -; G0_HIGH ; 1 ; Untyped ; -; G1_HIGH ; 1 ; Untyped ; -; G2_HIGH ; 1 ; Untyped ; -; G3_HIGH ; 1 ; Untyped ; -; E0_HIGH ; 1 ; Untyped ; -; E1_HIGH ; 1 ; Untyped ; -; E2_HIGH ; 1 ; Untyped ; -; E3_HIGH ; 1 ; Untyped ; -; L0_LOW ; 1 ; Untyped ; -; L1_LOW ; 1 ; Untyped ; -; G0_LOW ; 1 ; Untyped ; -; G1_LOW ; 1 ; Untyped ; -; G2_LOW ; 1 ; Untyped ; -; G3_LOW ; 1 ; Untyped ; -; E0_LOW ; 1 ; Untyped ; -; E1_LOW ; 1 ; Untyped ; -; E2_LOW ; 1 ; Untyped ; -; E3_LOW ; 1 ; Untyped ; -; L0_INITIAL ; 1 ; Untyped ; -; L1_INITIAL ; 1 ; Untyped ; -; G0_INITIAL ; 1 ; Untyped ; -; G1_INITIAL ; 1 ; Untyped ; -; G2_INITIAL ; 1 ; Untyped ; -; G3_INITIAL ; 1 ; Untyped ; -; E0_INITIAL ; 1 ; Untyped ; -; E1_INITIAL ; 1 ; Untyped ; -; E2_INITIAL ; 1 ; Untyped ; -; E3_INITIAL ; 1 ; Untyped ; -; L0_MODE ; BYPASS ; Untyped ; -; L1_MODE ; BYPASS ; Untyped ; -; G0_MODE ; BYPASS ; Untyped ; -; G1_MODE ; BYPASS ; Untyped ; -; G2_MODE ; BYPASS ; Untyped ; -; G3_MODE ; BYPASS ; Untyped ; -; E0_MODE ; BYPASS ; Untyped ; -; E1_MODE ; BYPASS ; Untyped ; -; E2_MODE ; BYPASS ; Untyped ; -; E3_MODE ; BYPASS ; Untyped ; -; L0_PH ; 0 ; Untyped ; -; L1_PH ; 0 ; Untyped ; -; G0_PH ; 0 ; Untyped ; -; G1_PH ; 0 ; Untyped ; -; G2_PH ; 0 ; Untyped ; -; G3_PH ; 0 ; Untyped ; -; E0_PH ; 0 ; Untyped ; -; E1_PH ; 0 ; Untyped ; -; E2_PH ; 0 ; Untyped ; -; E3_PH ; 0 ; Untyped ; -; M_PH ; 0 ; Untyped ; -; C1_USE_CASC_IN ; OFF ; Untyped ; -; C2_USE_CASC_IN ; OFF ; Untyped ; -; C3_USE_CASC_IN ; OFF ; Untyped ; -; C4_USE_CASC_IN ; OFF ; Untyped ; -; C5_USE_CASC_IN ; OFF ; Untyped ; -; C6_USE_CASC_IN ; OFF ; Untyped ; -; C7_USE_CASC_IN ; OFF ; Untyped ; -; C8_USE_CASC_IN ; OFF ; Untyped ; -; C9_USE_CASC_IN ; OFF ; Untyped ; -; CLK0_COUNTER ; G0 ; Untyped ; -; CLK1_COUNTER ; G0 ; Untyped ; -; CLK2_COUNTER ; G0 ; Untyped ; -; CLK3_COUNTER ; G0 ; Untyped ; -; CLK4_COUNTER ; G0 ; Untyped ; -; CLK5_COUNTER ; G0 ; Untyped ; -; CLK6_COUNTER ; E0 ; Untyped ; -; CLK7_COUNTER ; E1 ; Untyped ; -; CLK8_COUNTER ; E2 ; Untyped ; -; CLK9_COUNTER ; E3 ; Untyped ; -; L0_TIME_DELAY ; 0 ; Untyped ; -; L1_TIME_DELAY ; 0 ; Untyped ; -; G0_TIME_DELAY ; 0 ; Untyped ; -; G1_TIME_DELAY ; 0 ; Untyped ; -; G2_TIME_DELAY ; 0 ; Untyped ; -; G3_TIME_DELAY ; 0 ; Untyped ; -; E0_TIME_DELAY ; 0 ; Untyped ; -; E1_TIME_DELAY ; 0 ; Untyped ; -; E2_TIME_DELAY ; 0 ; Untyped ; -; E3_TIME_DELAY ; 0 ; Untyped ; -; M_TIME_DELAY ; 0 ; Untyped ; -; N_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_COUNTER ; E3 ; Untyped ; -; EXTCLK2_COUNTER ; E2 ; Untyped ; -; EXTCLK1_COUNTER ; E1 ; Untyped ; -; EXTCLK0_COUNTER ; E0 ; Untyped ; -; ENABLE0_COUNTER ; L0 ; Untyped ; -; ENABLE1_COUNTER ; L0 ; Untyped ; -; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; -; LOOP_FILTER_R ; 1.000000 ; Untyped ; -; LOOP_FILTER_C ; 5 ; Untyped ; -; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; -; VCO_POST_SCALE ; 0 ; Untyped ; -; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; -; PORT_CLK0 ; PORT_USED ; Untyped ; -; PORT_CLK1 ; PORT_USED ; Untyped ; -; PORT_CLK2 ; PORT_USED ; Untyped ; -; PORT_CLK3 ; PORT_UNUSED ; Untyped ; -; PORT_CLK4 ; PORT_UNUSED ; Untyped ; -; PORT_CLK5 ; PORT_UNUSED ; Untyped ; -; PORT_CLK6 ; PORT_UNUSED ; Untyped ; -; PORT_CLK7 ; PORT_UNUSED ; Untyped ; -; PORT_CLK8 ; PORT_UNUSED ; Untyped ; -; PORT_CLK9 ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; -; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; -; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; -; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; -; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_INCLK0 ; PORT_USED ; Untyped ; -; PORT_FBIN ; PORT_UNUSED ; Untyped ; -; PORT_PLLENA ; PORT_UNUSED ; Untyped ; -; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; -; PORT_ARESET ; PORT_UNUSED ; Untyped ; -; PORT_PFDENA ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; -; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; -; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; -; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; -; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_LOCKED ; PORT_USED ; Untyped ; -; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; -; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; -; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; -; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; -; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; -; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; -; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; M_TEST_SOURCE ; 5 ; Untyped ; -; C0_TEST_SOURCE ; 5 ; Untyped ; -; C1_TEST_SOURCE ; 5 ; Untyped ; -; C2_TEST_SOURCE ; 5 ; Untyped ; -; C3_TEST_SOURCE ; 5 ; Untyped ; -; C4_TEST_SOURCE ; 5 ; Untyped ; -; C5_TEST_SOURCE ; 5 ; Untyped ; -; C6_TEST_SOURCE ; 5 ; Untyped ; -; C7_TEST_SOURCE ; 5 ; Untyped ; -; C8_TEST_SOURCE ; 5 ; Untyped ; -; C9_TEST_SOURCE ; 5 ; Untyped ; -; CBXI_PARAMETER ; altpll_pul2 ; Untyped ; -; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; -; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; -; WIDTH_CLOCK ; 5 ; Signed Integer ; -; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; -; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; -; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+-------------------------------+--------------------+------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; -+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ -; ACF_DISABLE_MLAB_RAM_USE ; FALSE ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; -; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; -; DELAY_RDUSEDW ; 1 ; Untyped ; -; DELAY_WRUSEDW ; 1 ; Untyped ; -; LPM_NUMWORDS ; 1024 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; LPM_WIDTH ; 8 ; Signed Integer ; -; LPM_WIDTH_R ; 32 ; Signed Integer ; -; LPM_WIDTHU ; 10 ; Signed Integer ; -; LPM_WIDTHU_R ; 8 ; Signed Integer ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; OVERFLOW_CHECKING ; ON ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; RDSYNC_DELAYPIPE ; 5 ; Signed Integer ; -; UNDERFLOW_CHECKING ; ON ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; WRITE_ACLR_SYNCH ; OFF ; Untyped ; -; WRSYNC_DELAYPIPE ; 5 ; Signed Integer ; -; CBXI_PARAMETER ; dcfifo_0hh1 ; Untyped ; -+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component ; -+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ -; ACF_DISABLE_MLAB_RAM_USE ; FALSE ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; -; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; -; DELAY_RDUSEDW ; 1 ; Untyped ; -; DELAY_WRUSEDW ; 1 ; Untyped ; -; LPM_NUMWORDS ; 256 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_WIDTH_R ; 8 ; Signed Integer ; -; LPM_WIDTHU ; 8 ; Signed Integer ; -; LPM_WIDTHU_R ; 10 ; Signed Integer ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; OVERFLOW_CHECKING ; ON ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; RDSYNC_DELAYPIPE ; 5 ; Signed Integer ; -; UNDERFLOW_CHECKING ; ON ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; WRITE_ACLR_SYNCH ; OFF ; Untyped ; -; WRSYNC_DELAYPIPE ; 5 ; Signed Integer ; -; CBXI_PARAMETER ; dcfifo_3fh1 ; Untyped ; -+--------------------------+-------------+---------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -; TOP ; 152 ; Signed Integer ; -; BOTTOM ; 104 ; Signed Integer ; -; PHASE_CORR ; 75 ; Signed Integer ; -+----------------+-------+---------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll3:inst13|altpll:altpll_component ; -+-------------------------------+--------------------+--------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+--------------------+--------------------------------+ -; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; -; PLL_TYPE ; AUTO ; Untyped ; -; QUALIFY_CONF_DONE ; OFF ; Untyped ; -; COMPENSATE_CLOCK ; CLK1 ; Untyped ; -; SCAN_CHAIN ; LONG ; Untyped ; -; PRIMARY_CLOCK ; INCLK0 ; Untyped ; -; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; -; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; -; GATE_LOCK_SIGNAL ; NO ; Untyped ; -; GATE_LOCK_COUNTER ; 0 ; Untyped ; -; LOCK_HIGH ; 1 ; Untyped ; -; LOCK_LOW ; 1 ; Untyped ; -; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; -; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; -; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; -; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; -; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; -; SKIP_VCO ; OFF ; Untyped ; -; SWITCH_OVER_COUNTER ; 0 ; Untyped ; -; SWITCH_OVER_TYPE ; AUTO ; Untyped ; -; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; -; BANDWIDTH ; 0 ; Untyped ; -; BANDWIDTH_TYPE ; AUTO ; Untyped ; -; SPREAD_FREQUENCY ; 0 ; Untyped ; -; DOWN_SPREAD ; 0 ; Untyped ; -; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; -; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; -; CLK9_MULTIPLY_BY ; 0 ; Untyped ; -; CLK8_MULTIPLY_BY ; 0 ; Untyped ; -; CLK7_MULTIPLY_BY ; 0 ; Untyped ; -; CLK6_MULTIPLY_BY ; 0 ; Untyped ; -; CLK5_MULTIPLY_BY ; 1 ; Untyped ; -; CLK4_MULTIPLY_BY ; 1 ; Untyped ; -; CLK3_MULTIPLY_BY ; 16 ; Signed Integer ; -; CLK2_MULTIPLY_BY ; 25 ; Signed Integer ; -; CLK1_MULTIPLY_BY ; 16 ; Signed Integer ; -; CLK0_MULTIPLY_BY ; 2 ; Signed Integer ; -; CLK9_DIVIDE_BY ; 0 ; Untyped ; -; CLK8_DIVIDE_BY ; 0 ; Untyped ; -; CLK7_DIVIDE_BY ; 0 ; Untyped ; -; CLK6_DIVIDE_BY ; 0 ; Untyped ; -; CLK5_DIVIDE_BY ; 1 ; Untyped ; -; CLK4_DIVIDE_BY ; 1 ; Untyped ; -; CLK3_DIVIDE_BY ; 11 ; Signed Integer ; -; CLK2_DIVIDE_BY ; 33 ; Signed Integer ; -; CLK1_DIVIDE_BY ; 33 ; Signed Integer ; -; CLK0_DIVIDE_BY ; 33 ; Signed Integer ; -; CLK9_PHASE_SHIFT ; 0 ; Untyped ; -; CLK8_PHASE_SHIFT ; 0 ; Untyped ; -; CLK7_PHASE_SHIFT ; 0 ; Untyped ; -; CLK6_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_PHASE_SHIFT ; 0 ; Untyped ; -; CLK4_PHASE_SHIFT ; 0 ; Untyped ; -; CLK3_PHASE_SHIFT ; 0 ; Untyped ; -; CLK2_PHASE_SHIFT ; 0 ; Untyped ; -; CLK1_PHASE_SHIFT ; 0 ; Untyped ; -; CLK0_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_TIME_DELAY ; 0 ; Untyped ; -; CLK4_TIME_DELAY ; 0 ; Untyped ; -; CLK3_TIME_DELAY ; 0 ; Untyped ; -; CLK2_TIME_DELAY ; 0 ; Untyped ; -; CLK1_TIME_DELAY ; 0 ; Untyped ; -; CLK0_TIME_DELAY ; 0 ; Untyped ; -; CLK9_DUTY_CYCLE ; 50 ; Untyped ; -; CLK8_DUTY_CYCLE ; 50 ; Untyped ; -; CLK7_DUTY_CYCLE ; 50 ; Untyped ; -; CLK6_DUTY_CYCLE ; 50 ; Untyped ; -; CLK5_DUTY_CYCLE ; 50 ; Untyped ; -; CLK4_DUTY_CYCLE ; 50 ; Untyped ; -; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; LOCK_WINDOW_UI ; 0.05 ; Untyped ; -; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; -; DPA_MULTIPLY_BY ; 0 ; Untyped ; -; DPA_DIVIDE_BY ; 1 ; Untyped ; -; DPA_DIVIDER ; 0 ; Untyped ; -; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; -; VCO_MULTIPLY_BY ; 0 ; Untyped ; -; VCO_DIVIDE_BY ; 0 ; Untyped ; -; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; -; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; -; VCO_MIN ; 0 ; Untyped ; -; VCO_MAX ; 0 ; Untyped ; -; VCO_CENTER ; 0 ; Untyped ; -; PFD_MIN ; 0 ; Untyped ; -; PFD_MAX ; 0 ; Untyped ; -; M_INITIAL ; 0 ; Untyped ; -; M ; 0 ; Untyped ; -; N ; 1 ; Untyped ; -; M2 ; 1 ; Untyped ; -; N2 ; 1 ; Untyped ; -; SS ; 1 ; Untyped ; -; C0_HIGH ; 0 ; Untyped ; -; C1_HIGH ; 0 ; Untyped ; -; C2_HIGH ; 0 ; Untyped ; -; C3_HIGH ; 0 ; Untyped ; -; C4_HIGH ; 0 ; Untyped ; -; C5_HIGH ; 0 ; Untyped ; -; C6_HIGH ; 0 ; Untyped ; -; C7_HIGH ; 0 ; Untyped ; -; C8_HIGH ; 0 ; Untyped ; -; C9_HIGH ; 0 ; Untyped ; -; C0_LOW ; 0 ; Untyped ; -; C1_LOW ; 0 ; Untyped ; -; C2_LOW ; 0 ; Untyped ; -; C3_LOW ; 0 ; Untyped ; -; C4_LOW ; 0 ; Untyped ; -; C5_LOW ; 0 ; Untyped ; -; C6_LOW ; 0 ; Untyped ; -; C7_LOW ; 0 ; Untyped ; -; C8_LOW ; 0 ; Untyped ; -; C9_LOW ; 0 ; Untyped ; -; C0_INITIAL ; 0 ; Untyped ; -; C1_INITIAL ; 0 ; Untyped ; -; C2_INITIAL ; 0 ; Untyped ; -; C3_INITIAL ; 0 ; Untyped ; -; C4_INITIAL ; 0 ; Untyped ; -; C5_INITIAL ; 0 ; Untyped ; -; C6_INITIAL ; 0 ; Untyped ; -; C7_INITIAL ; 0 ; Untyped ; -; C8_INITIAL ; 0 ; Untyped ; -; C9_INITIAL ; 0 ; Untyped ; -; C0_MODE ; BYPASS ; Untyped ; -; C1_MODE ; BYPASS ; Untyped ; -; C2_MODE ; BYPASS ; Untyped ; -; C3_MODE ; BYPASS ; Untyped ; -; C4_MODE ; BYPASS ; Untyped ; -; C5_MODE ; BYPASS ; Untyped ; -; C6_MODE ; BYPASS ; Untyped ; -; C7_MODE ; BYPASS ; Untyped ; -; C8_MODE ; BYPASS ; Untyped ; -; C9_MODE ; BYPASS ; Untyped ; -; C0_PH ; 0 ; Untyped ; -; C1_PH ; 0 ; Untyped ; -; C2_PH ; 0 ; Untyped ; -; C3_PH ; 0 ; Untyped ; -; C4_PH ; 0 ; Untyped ; -; C5_PH ; 0 ; Untyped ; -; C6_PH ; 0 ; Untyped ; -; C7_PH ; 0 ; Untyped ; -; C8_PH ; 0 ; Untyped ; -; C9_PH ; 0 ; Untyped ; -; L0_HIGH ; 1 ; Untyped ; -; L1_HIGH ; 1 ; Untyped ; -; G0_HIGH ; 1 ; Untyped ; -; G1_HIGH ; 1 ; Untyped ; -; G2_HIGH ; 1 ; Untyped ; -; G3_HIGH ; 1 ; Untyped ; -; E0_HIGH ; 1 ; Untyped ; -; E1_HIGH ; 1 ; Untyped ; -; E2_HIGH ; 1 ; Untyped ; -; E3_HIGH ; 1 ; Untyped ; -; L0_LOW ; 1 ; Untyped ; -; L1_LOW ; 1 ; Untyped ; -; G0_LOW ; 1 ; Untyped ; -; G1_LOW ; 1 ; Untyped ; -; G2_LOW ; 1 ; Untyped ; -; G3_LOW ; 1 ; Untyped ; -; E0_LOW ; 1 ; Untyped ; -; E1_LOW ; 1 ; Untyped ; -; E2_LOW ; 1 ; Untyped ; -; E3_LOW ; 1 ; Untyped ; -; L0_INITIAL ; 1 ; Untyped ; -; L1_INITIAL ; 1 ; Untyped ; -; G0_INITIAL ; 1 ; Untyped ; -; G1_INITIAL ; 1 ; Untyped ; -; G2_INITIAL ; 1 ; Untyped ; -; G3_INITIAL ; 1 ; Untyped ; -; E0_INITIAL ; 1 ; Untyped ; -; E1_INITIAL ; 1 ; Untyped ; -; E2_INITIAL ; 1 ; Untyped ; -; E3_INITIAL ; 1 ; Untyped ; -; L0_MODE ; BYPASS ; Untyped ; -; L1_MODE ; BYPASS ; Untyped ; -; G0_MODE ; BYPASS ; Untyped ; -; G1_MODE ; BYPASS ; Untyped ; -; G2_MODE ; BYPASS ; Untyped ; -; G3_MODE ; BYPASS ; Untyped ; -; E0_MODE ; BYPASS ; Untyped ; -; E1_MODE ; BYPASS ; Untyped ; -; E2_MODE ; BYPASS ; Untyped ; -; E3_MODE ; BYPASS ; Untyped ; -; L0_PH ; 0 ; Untyped ; -; L1_PH ; 0 ; Untyped ; -; G0_PH ; 0 ; Untyped ; -; G1_PH ; 0 ; Untyped ; -; G2_PH ; 0 ; Untyped ; -; G3_PH ; 0 ; Untyped ; -; E0_PH ; 0 ; Untyped ; -; E1_PH ; 0 ; Untyped ; -; E2_PH ; 0 ; Untyped ; -; E3_PH ; 0 ; Untyped ; -; M_PH ; 0 ; Untyped ; -; C1_USE_CASC_IN ; OFF ; Untyped ; -; C2_USE_CASC_IN ; OFF ; Untyped ; -; C3_USE_CASC_IN ; OFF ; Untyped ; -; C4_USE_CASC_IN ; OFF ; Untyped ; -; C5_USE_CASC_IN ; OFF ; Untyped ; -; C6_USE_CASC_IN ; OFF ; Untyped ; -; C7_USE_CASC_IN ; OFF ; Untyped ; -; C8_USE_CASC_IN ; OFF ; Untyped ; -; C9_USE_CASC_IN ; OFF ; Untyped ; -; CLK0_COUNTER ; G0 ; Untyped ; -; CLK1_COUNTER ; G0 ; Untyped ; -; CLK2_COUNTER ; G0 ; Untyped ; -; CLK3_COUNTER ; G0 ; Untyped ; -; CLK4_COUNTER ; G0 ; Untyped ; -; CLK5_COUNTER ; G0 ; Untyped ; -; CLK6_COUNTER ; E0 ; Untyped ; -; CLK7_COUNTER ; E1 ; Untyped ; -; CLK8_COUNTER ; E2 ; Untyped ; -; CLK9_COUNTER ; E3 ; Untyped ; -; L0_TIME_DELAY ; 0 ; Untyped ; -; L1_TIME_DELAY ; 0 ; Untyped ; -; G0_TIME_DELAY ; 0 ; Untyped ; -; G1_TIME_DELAY ; 0 ; Untyped ; -; G2_TIME_DELAY ; 0 ; Untyped ; -; G3_TIME_DELAY ; 0 ; Untyped ; -; E0_TIME_DELAY ; 0 ; Untyped ; -; E1_TIME_DELAY ; 0 ; Untyped ; -; E2_TIME_DELAY ; 0 ; Untyped ; -; E3_TIME_DELAY ; 0 ; Untyped ; -; M_TIME_DELAY ; 0 ; Untyped ; -; N_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_COUNTER ; E3 ; Untyped ; -; EXTCLK2_COUNTER ; E2 ; Untyped ; -; EXTCLK1_COUNTER ; E1 ; Untyped ; -; EXTCLK0_COUNTER ; E0 ; Untyped ; -; ENABLE0_COUNTER ; L0 ; Untyped ; -; ENABLE1_COUNTER ; L0 ; Untyped ; -; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; -; LOOP_FILTER_R ; 1.000000 ; Untyped ; -; LOOP_FILTER_C ; 5 ; Untyped ; -; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; -; VCO_POST_SCALE ; 0 ; Untyped ; -; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; -; PORT_CLK0 ; PORT_USED ; Untyped ; -; PORT_CLK1 ; PORT_USED ; Untyped ; -; PORT_CLK2 ; PORT_USED ; Untyped ; -; PORT_CLK3 ; PORT_USED ; Untyped ; -; PORT_CLK4 ; PORT_UNUSED ; Untyped ; -; PORT_CLK5 ; PORT_UNUSED ; Untyped ; -; PORT_CLK6 ; PORT_UNUSED ; Untyped ; -; PORT_CLK7 ; PORT_UNUSED ; Untyped ; -; PORT_CLK8 ; PORT_UNUSED ; Untyped ; -; PORT_CLK9 ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; -; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; -; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; -; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; -; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_INCLK0 ; PORT_USED ; Untyped ; -; PORT_FBIN ; PORT_UNUSED ; Untyped ; -; PORT_PLLENA ; PORT_UNUSED ; Untyped ; -; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; -; PORT_ARESET ; PORT_UNUSED ; Untyped ; -; PORT_PFDENA ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; -; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; -; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; -; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; -; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_LOCKED ; PORT_UNUSED ; Untyped ; -; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; -; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; -; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; -; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; -; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; -; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; -; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; M_TEST_SOURCE ; 5 ; Untyped ; -; C0_TEST_SOURCE ; 5 ; Untyped ; -; C1_TEST_SOURCE ; 5 ; Untyped ; -; C2_TEST_SOURCE ; 5 ; Untyped ; -; C3_TEST_SOURCE ; 5 ; Untyped ; -; C4_TEST_SOURCE ; 5 ; Untyped ; -; C5_TEST_SOURCE ; 5 ; Untyped ; -; C6_TEST_SOURCE ; 5 ; Untyped ; -; C7_TEST_SOURCE ; 5 ; Untyped ; -; C8_TEST_SOURCE ; 5 ; Untyped ; -; C9_TEST_SOURCE ; 5 ; Untyped ; -; CBXI_PARAMETER ; altpll_41p2 ; Untyped ; -; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; -; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; -; WIDTH_CLOCK ; 5 ; Signed Integer ; -; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; -; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; -; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+-------------------------------+--------------------+--------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00002|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 5 ; Signed Integer ; -; LPM_DIRECTION ; RIGHT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; -+-------------------------+-------------+-----------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+-------------+-----------------------------------------------------------------------+ -; WIDTH_BYTEENA ; 1 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 128 ; Signed Integer ; -; LPM_NUMWORDS ; 512 ; Signed Integer ; -; LPM_WIDTHU ; 9 ; Signed Integer ; -; LPM_SHOWAHEAD ; OFF ; Untyped ; -; UNDERFLOW_CHECKING ; OFF ; Untyped ; -; OVERFLOW_CHECKING ; OFF ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; DELAY_RDUSEDW ; 1 ; Untyped ; -; DELAY_WRUSEDW ; 1 ; Untyped ; -; RDSYNC_DELAYPIPE ; 6 ; Signed Integer ; -; WRSYNC_DELAYPIPE ; 6 ; Signed Integer ; -; CLOCKS_ARE_SYNCHRONIZED ; FALSE ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; ADD_USEDW_MSB_BIT ; OFF ; Untyped ; -; WRITE_ACLR_SYNCH ; ON ; Untyped ; -; CBXI_PARAMETER ; dcfifo_8fi1 ; Untyped ; -+-------------------------+-------------+-----------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 5 ; Signed Integer ; -; LPM_DIRECTION ; RIGHT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+---------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 128 ; Signed Integer ; -; LPM_SIZE ; 16 ; Signed Integer ; -; LPM_WIDTHS ; 4 ; Signed Integer ; -; LPM_PIPELINE ; 0 ; Signed Integer ; -; CBXI_PARAMETER ; mux_bbe ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+---------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 128 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 128 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component ; -+------------------------+-------------+--------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+--------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component ; -+------------------------+-------------+--------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+--------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component ; -+--------------------------+----------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------------+----------------+------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 32 ; Signed Integer ; -; POWER_UP_HIGH ; OFF ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; IMPLEMENT_INPUT_IN_LCELL ; ON ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_bidir_3jl ; Untyped ; -+--------------------------+----------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 64 ; Signed Integer ; -; LPM_SIZE ; 4 ; Signed Integer ; -; LPM_WIDTHS ; 2 ; Signed Integer ; -; LPM_PIPELINE ; 0 ; Signed Integer ; -; CBXI_PARAMETER ; mux_58e ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff6:inst36|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 128 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component ; -+----------------+--------+-------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+--------+-------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -+----------------+--------+-------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst119|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 5 ; Signed Integer ; -; LPM_DIRECTION ; RIGHT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst110|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_LONG:inst109|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 6 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 6 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 6 ; Signed Integer ; -; WIDTHAD_B ; 8 ; Signed Integer ; -; NUMWORDS_B ; 256 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; -+------------------------------------+-----------------+------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+-------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+-------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 128 ; Signed Integer ; -; LPM_SIZE ; 2 ; Signed Integer ; -; LPM_WIDTHS ; 1 ; Signed Integer ; -; LPM_PIPELINE ; 1 ; Signed Integer ; -; CBXI_PARAMETER ; mux_dcf ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+-------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; -+-------------------------+-------------+-----------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------+-------------+-----------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; lpm_width ; 128 ; Signed Integer ; -; LPM_NUMWORDS ; 128 ; Signed Integer ; -; LPM_WIDTHU ; 7 ; Signed Integer ; -; LPM_SHOWAHEAD ; ON ; Untyped ; -; UNDERFLOW_CHECKING ; OFF ; Untyped ; -; OVERFLOW_CHECKING ; OFF ; Untyped ; -; ALLOW_RWCYCLE_WHEN_FULL ; OFF ; Untyped ; -; ADD_RAM_OUTPUT_REGISTER ; OFF ; Untyped ; -; ALMOST_FULL_VALUE ; 0 ; Untyped ; -; ALMOST_EMPTY_VALUE ; 0 ; Untyped ; -; USE_EAB ; ON ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; -; CBXI_PARAMETER ; scfifo_lk21 ; Untyped ; -+-------------------------+-------------+-----------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_DIRECTION ; LEFT ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst70|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 6 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+--------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+--------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 6 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 6 ; Signed Integer ; -; WIDTHAD_B ; 8 ; Signed Integer ; -; NUMWORDS_B ; 256 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; -+------------------------------------+-----------------+--------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri3:inst74|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 6 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+-------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+-------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 6 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 6 ; Signed Integer ; -; WIDTHAD_B ; 8 ; Signed Integer ; -; NUMWORDS_B ; 256 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_lf92 ; Untyped ; -+------------------------------------+-----------------+-------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 3 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+--------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+--------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 3 ; Signed Integer ; -; WIDTHAD_A ; 4 ; Signed Integer ; -; NUMWORDS_A ; 16 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 3 ; Signed Integer ; -; WIDTHAD_B ; 4 ; Signed Integer ; -; NUMWORDS_B ; 16 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; -+------------------------------------+-----------------+--------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst56|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 3 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+----------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+----------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 3 ; Signed Integer ; -; WIDTHAD_A ; 4 ; Signed Integer ; -; NUMWORDS_A ; 16 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 3 ; Signed Integer ; -; WIDTHAD_B ; 4 ; Signed Integer ; -; NUMWORDS_B ; 16 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; -+------------------------------------+-----------------+----------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri1:inst61|lpm_bustri:lpm_bustri_component ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 3 ; Signed Integer ; -+----------------+-------+-----------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+---------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 3 ; Signed Integer ; -; WIDTHAD_A ; 4 ; Signed Integer ; -; NUMWORDS_A ; 16 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 3 ; Signed Integer ; -; WIDTHAD_B ; 4 ; Signed Integer ; -; NUMWORDS_B ; 16 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_rb92 ; Untyped ; -+------------------------------------+-----------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst58|lpm_bustri:lpm_bustri_component ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+-----------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+-----------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 8 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 8 ; Signed Integer ; -; WIDTHAD_B ; 8 ; Signed Integer ; -; NUMWORDS_B ; 256 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; -+------------------------------------+-----------------+-----------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+-------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+-------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 1 ; Signed Integer ; -; LPM_SIZE ; 2 ; Signed Integer ; -; LPM_WIDTHS ; 1 ; Signed Integer ; -; LPM_PIPELINE ; 0 ; Signed Integer ; -; CBXI_PARAMETER ; mux_96e ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+-------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 8 ; Signed Integer ; -; LPM_SIZE ; 16 ; Signed Integer ; -; LPM_WIDTHS ; 4 ; Signed Integer ; -; LPM_PIPELINE ; 2 ; Signed Integer ; -; CBXI_PARAMETER ; mux_mpe ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 7 ; Signed Integer ; -; LPM_SIZE ; 2 ; Signed Integer ; -; LPM_WIDTHS ; 1 ; Signed Integer ; -; LPM_PIPELINE ; 0 ; Signed Integer ; -; CBXI_PARAMETER ; mux_f6e ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 7 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_pf6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst57|lpm_bustri:lpm_bustri_component ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+-----------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+-----------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 8 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 8 ; Signed Integer ; -; WIDTHAD_B ; 8 ; Signed Integer ; -; NUMWORDS_B ; 256 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; -+------------------------------------+-----------------+-----------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_bustri_BYT:inst53|lpm_bustri:lpm_bustri_component ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+--------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; -+------------------------------------+-----------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+-----------------+---------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ; -; WIDTH_A ; 8 ; Signed Integer ; -; WIDTHAD_A ; 8 ; Signed Integer ; -; NUMWORDS_A ; 256 ; Signed Integer ; -; OUTDATA_REG_A ; CLOCK0 ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 8 ; Signed Integer ; -; WIDTHAD_B ; 8 ; Signed Integer ; -; NUMWORDS_B ; 256 ; Signed Integer ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; CLOCK1 ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Signed Integer ; -; WIDTH_BYTEENA_B ; 1 ; Signed Integer ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; OLD_DATA ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; OLD_DATA ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; BYPASS ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_pf92 ; Untyped ; -+------------------------------------+-----------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component ; -+------------------------+--------------+----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------+----------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 24 ; Signed Integer ; -; POWER_UP_HIGH ; OFF ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_out_o2f ; Untyped ; -+------------------------+--------------+----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+-----------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+-----------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 24 ; Signed Integer ; -; LPM_SIZE ; 8 ; Signed Integer ; -; LPM_WIDTHS ; 3 ; Signed Integer ; -; LPM_PIPELINE ; 2 ; Signed Integer ; -; CBXI_PARAMETER ; mux_kpe ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+-----------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 24 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 24 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 5 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst54|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 5 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant0:inst64|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 5 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_nf6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 24 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 24 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 2 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst80|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 2 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant1:inst83|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 2 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_4e6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 16 ; Signed Integer ; -; LPM_SIZE ; 8 ; Signed Integer ; -; LPM_WIDTHS ; 3 ; Signed Integer ; -; LPM_PIPELINE ; 4 ; Signed Integer ; -; CBXI_PARAMETER ; mux_npe ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -; LPM_CVALUE ; 0 ; Signed Integer ; -; ENABLE_RUNTIME_MOD ; NO ; Untyped ; -; CBXI_PARAMETER ; lpm_constant_qf6 ; Untyped ; -+--------------------+------------------+--------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component ; -+------------------------+-------------+--------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+--------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component ; -+------------------------+-------------+------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_SIZE ; 4 ; Signed Integer ; -; LPM_WIDTHS ; 2 ; Signed Integer ; -; LPM_PIPELINE ; 4 ; Signed Integer ; -; CBXI_PARAMETER ; mux_gpe ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -+------------------------+-------------+------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component ; -+------------------------+--------------+----------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------+----------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 4 ; Signed Integer ; -; POWER_UP_HIGH ; ON ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_out_are ; Untyped ; -+------------------------+--------------+----------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll2:inst12|altpll:altpll_component ; -+-------------------------------+--------------------+--------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+--------------------+--------------------------------+ -; OPERATION_MODE ; SOURCE_SYNCHRONOUS ; Untyped ; -; PLL_TYPE ; AUTO ; Untyped ; -; QUALIFY_CONF_DONE ; OFF ; Untyped ; -; COMPENSATE_CLOCK ; CLK0 ; Untyped ; -; SCAN_CHAIN ; LONG ; Untyped ; -; PRIMARY_CLOCK ; INCLK0 ; Untyped ; -; INCLK0_INPUT_FREQUENCY ; 30303 ; Signed Integer ; -; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; -; GATE_LOCK_SIGNAL ; NO ; Untyped ; -; GATE_LOCK_COUNTER ; 0 ; Untyped ; -; LOCK_HIGH ; 1 ; Untyped ; -; LOCK_LOW ; 1 ; Untyped ; -; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; -; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; -; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; -; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; -; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; -; SKIP_VCO ; OFF ; Untyped ; -; SWITCH_OVER_COUNTER ; 0 ; Untyped ; -; SWITCH_OVER_TYPE ; AUTO ; Untyped ; -; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; -; BANDWIDTH ; 0 ; Untyped ; -; BANDWIDTH_TYPE ; AUTO ; Untyped ; -; SPREAD_FREQUENCY ; 0 ; Untyped ; -; DOWN_SPREAD ; 0 ; Untyped ; -; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; -; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; -; CLK9_MULTIPLY_BY ; 0 ; Untyped ; -; CLK8_MULTIPLY_BY ; 0 ; Untyped ; -; CLK7_MULTIPLY_BY ; 0 ; Untyped ; -; CLK6_MULTIPLY_BY ; 0 ; Untyped ; -; CLK5_MULTIPLY_BY ; 1 ; Untyped ; -; CLK4_MULTIPLY_BY ; 2 ; Signed Integer ; -; CLK3_MULTIPLY_BY ; 4 ; Signed Integer ; -; CLK2_MULTIPLY_BY ; 4 ; Signed Integer ; -; CLK1_MULTIPLY_BY ; 4 ; Signed Integer ; -; CLK0_MULTIPLY_BY ; 4 ; Signed Integer ; -; CLK9_DIVIDE_BY ; 0 ; Untyped ; -; CLK8_DIVIDE_BY ; 0 ; Untyped ; -; CLK7_DIVIDE_BY ; 0 ; Untyped ; -; CLK6_DIVIDE_BY ; 0 ; Untyped ; -; CLK5_DIVIDE_BY ; 1 ; Untyped ; -; CLK4_DIVIDE_BY ; 1 ; Signed Integer ; -; CLK3_DIVIDE_BY ; 1 ; Signed Integer ; -; CLK2_DIVIDE_BY ; 1 ; Signed Integer ; -; CLK1_DIVIDE_BY ; 1 ; Signed Integer ; -; CLK0_DIVIDE_BY ; 1 ; Signed Integer ; -; CLK9_PHASE_SHIFT ; 0 ; Untyped ; -; CLK8_PHASE_SHIFT ; 0 ; Untyped ; -; CLK7_PHASE_SHIFT ; 0 ; Untyped ; -; CLK6_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_PHASE_SHIFT ; 0 ; Untyped ; -; CLK4_PHASE_SHIFT ; 11364 ; Untyped ; -; CLK3_PHASE_SHIFT ; 2210 ; Untyped ; -; CLK2_PHASE_SHIFT ; 3788 ; Untyped ; -; CLK1_PHASE_SHIFT ; 0 ; Untyped ; -; CLK0_PHASE_SHIFT ; 5051 ; Untyped ; -; CLK5_TIME_DELAY ; 0 ; Untyped ; -; CLK4_TIME_DELAY ; 0 ; Untyped ; -; CLK3_TIME_DELAY ; 0 ; Untyped ; -; CLK2_TIME_DELAY ; 0 ; Untyped ; -; CLK1_TIME_DELAY ; 0 ; Untyped ; -; CLK0_TIME_DELAY ; 0 ; Untyped ; -; CLK9_DUTY_CYCLE ; 50 ; Untyped ; -; CLK8_DUTY_CYCLE ; 50 ; Untyped ; -; CLK7_DUTY_CYCLE ; 50 ; Untyped ; -; CLK6_DUTY_CYCLE ; 50 ; Untyped ; -; CLK5_DUTY_CYCLE ; 50 ; Untyped ; -; CLK4_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; -; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; LOCK_WINDOW_UI ; 0.05 ; Untyped ; -; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; -; DPA_MULTIPLY_BY ; 0 ; Untyped ; -; DPA_DIVIDE_BY ; 1 ; Untyped ; -; DPA_DIVIDER ; 0 ; Untyped ; -; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; -; VCO_MULTIPLY_BY ; 0 ; Untyped ; -; VCO_DIVIDE_BY ; 0 ; Untyped ; -; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; -; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; -; VCO_MIN ; 0 ; Untyped ; -; VCO_MAX ; 0 ; Untyped ; -; VCO_CENTER ; 0 ; Untyped ; -; PFD_MIN ; 0 ; Untyped ; -; PFD_MAX ; 0 ; Untyped ; -; M_INITIAL ; 0 ; Untyped ; -; M ; 0 ; Untyped ; -; N ; 1 ; Untyped ; -; M2 ; 1 ; Untyped ; -; N2 ; 1 ; Untyped ; -; SS ; 1 ; Untyped ; -; C0_HIGH ; 0 ; Untyped ; -; C1_HIGH ; 0 ; Untyped ; -; C2_HIGH ; 0 ; Untyped ; -; C3_HIGH ; 0 ; Untyped ; -; C4_HIGH ; 0 ; Untyped ; -; C5_HIGH ; 0 ; Untyped ; -; C6_HIGH ; 0 ; Untyped ; -; C7_HIGH ; 0 ; Untyped ; -; C8_HIGH ; 0 ; Untyped ; -; C9_HIGH ; 0 ; Untyped ; -; C0_LOW ; 0 ; Untyped ; -; C1_LOW ; 0 ; Untyped ; -; C2_LOW ; 0 ; Untyped ; -; C3_LOW ; 0 ; Untyped ; -; C4_LOW ; 0 ; Untyped ; -; C5_LOW ; 0 ; Untyped ; -; C6_LOW ; 0 ; Untyped ; -; C7_LOW ; 0 ; Untyped ; -; C8_LOW ; 0 ; Untyped ; -; C9_LOW ; 0 ; Untyped ; -; C0_INITIAL ; 0 ; Untyped ; -; C1_INITIAL ; 0 ; Untyped ; -; C2_INITIAL ; 0 ; Untyped ; -; C3_INITIAL ; 0 ; Untyped ; -; C4_INITIAL ; 0 ; Untyped ; -; C5_INITIAL ; 0 ; Untyped ; -; C6_INITIAL ; 0 ; Untyped ; -; C7_INITIAL ; 0 ; Untyped ; -; C8_INITIAL ; 0 ; Untyped ; -; C9_INITIAL ; 0 ; Untyped ; -; C0_MODE ; BYPASS ; Untyped ; -; C1_MODE ; BYPASS ; Untyped ; -; C2_MODE ; BYPASS ; Untyped ; -; C3_MODE ; BYPASS ; Untyped ; -; C4_MODE ; BYPASS ; Untyped ; -; C5_MODE ; BYPASS ; Untyped ; -; C6_MODE ; BYPASS ; Untyped ; -; C7_MODE ; BYPASS ; Untyped ; -; C8_MODE ; BYPASS ; Untyped ; -; C9_MODE ; BYPASS ; Untyped ; -; C0_PH ; 0 ; Untyped ; -; C1_PH ; 0 ; Untyped ; -; C2_PH ; 0 ; Untyped ; -; C3_PH ; 0 ; Untyped ; -; C4_PH ; 0 ; Untyped ; -; C5_PH ; 0 ; Untyped ; -; C6_PH ; 0 ; Untyped ; -; C7_PH ; 0 ; Untyped ; -; C8_PH ; 0 ; Untyped ; -; C9_PH ; 0 ; Untyped ; -; L0_HIGH ; 1 ; Untyped ; -; L1_HIGH ; 1 ; Untyped ; -; G0_HIGH ; 1 ; Untyped ; -; G1_HIGH ; 1 ; Untyped ; -; G2_HIGH ; 1 ; Untyped ; -; G3_HIGH ; 1 ; Untyped ; -; E0_HIGH ; 1 ; Untyped ; -; E1_HIGH ; 1 ; Untyped ; -; E2_HIGH ; 1 ; Untyped ; -; E3_HIGH ; 1 ; Untyped ; -; L0_LOW ; 1 ; Untyped ; -; L1_LOW ; 1 ; Untyped ; -; G0_LOW ; 1 ; Untyped ; -; G1_LOW ; 1 ; Untyped ; -; G2_LOW ; 1 ; Untyped ; -; G3_LOW ; 1 ; Untyped ; -; E0_LOW ; 1 ; Untyped ; -; E1_LOW ; 1 ; Untyped ; -; E2_LOW ; 1 ; Untyped ; -; E3_LOW ; 1 ; Untyped ; -; L0_INITIAL ; 1 ; Untyped ; -; L1_INITIAL ; 1 ; Untyped ; -; G0_INITIAL ; 1 ; Untyped ; -; G1_INITIAL ; 1 ; Untyped ; -; G2_INITIAL ; 1 ; Untyped ; -; G3_INITIAL ; 1 ; Untyped ; -; E0_INITIAL ; 1 ; Untyped ; -; E1_INITIAL ; 1 ; Untyped ; -; E2_INITIAL ; 1 ; Untyped ; -; E3_INITIAL ; 1 ; Untyped ; -; L0_MODE ; BYPASS ; Untyped ; -; L1_MODE ; BYPASS ; Untyped ; -; G0_MODE ; BYPASS ; Untyped ; -; G1_MODE ; BYPASS ; Untyped ; -; G2_MODE ; BYPASS ; Untyped ; -; G3_MODE ; BYPASS ; Untyped ; -; E0_MODE ; BYPASS ; Untyped ; -; E1_MODE ; BYPASS ; Untyped ; -; E2_MODE ; BYPASS ; Untyped ; -; E3_MODE ; BYPASS ; Untyped ; -; L0_PH ; 0 ; Untyped ; -; L1_PH ; 0 ; Untyped ; -; G0_PH ; 0 ; Untyped ; -; G1_PH ; 0 ; Untyped ; -; G2_PH ; 0 ; Untyped ; -; G3_PH ; 0 ; Untyped ; -; E0_PH ; 0 ; Untyped ; -; E1_PH ; 0 ; Untyped ; -; E2_PH ; 0 ; Untyped ; -; E3_PH ; 0 ; Untyped ; -; M_PH ; 0 ; Untyped ; -; C1_USE_CASC_IN ; OFF ; Untyped ; -; C2_USE_CASC_IN ; OFF ; Untyped ; -; C3_USE_CASC_IN ; OFF ; Untyped ; -; C4_USE_CASC_IN ; OFF ; Untyped ; -; C5_USE_CASC_IN ; OFF ; Untyped ; -; C6_USE_CASC_IN ; OFF ; Untyped ; -; C7_USE_CASC_IN ; OFF ; Untyped ; -; C8_USE_CASC_IN ; OFF ; Untyped ; -; C9_USE_CASC_IN ; OFF ; Untyped ; -; CLK0_COUNTER ; G0 ; Untyped ; -; CLK1_COUNTER ; G0 ; Untyped ; -; CLK2_COUNTER ; G0 ; Untyped ; -; CLK3_COUNTER ; G0 ; Untyped ; -; CLK4_COUNTER ; G0 ; Untyped ; -; CLK5_COUNTER ; G0 ; Untyped ; -; CLK6_COUNTER ; E0 ; Untyped ; -; CLK7_COUNTER ; E1 ; Untyped ; -; CLK8_COUNTER ; E2 ; Untyped ; -; CLK9_COUNTER ; E3 ; Untyped ; -; L0_TIME_DELAY ; 0 ; Untyped ; -; L1_TIME_DELAY ; 0 ; Untyped ; -; G0_TIME_DELAY ; 0 ; Untyped ; -; G1_TIME_DELAY ; 0 ; Untyped ; -; G2_TIME_DELAY ; 0 ; Untyped ; -; G3_TIME_DELAY ; 0 ; Untyped ; -; E0_TIME_DELAY ; 0 ; Untyped ; -; E1_TIME_DELAY ; 0 ; Untyped ; -; E2_TIME_DELAY ; 0 ; Untyped ; -; E3_TIME_DELAY ; 0 ; Untyped ; -; M_TIME_DELAY ; 0 ; Untyped ; -; N_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_COUNTER ; E3 ; Untyped ; -; EXTCLK2_COUNTER ; E2 ; Untyped ; -; EXTCLK1_COUNTER ; E1 ; Untyped ; -; EXTCLK0_COUNTER ; E0 ; Untyped ; -; ENABLE0_COUNTER ; L0 ; Untyped ; -; ENABLE1_COUNTER ; L0 ; Untyped ; -; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; -; LOOP_FILTER_R ; 1.000000 ; Untyped ; -; LOOP_FILTER_C ; 5 ; Untyped ; -; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; -; VCO_POST_SCALE ; 0 ; Untyped ; -; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; -; PORT_CLK0 ; PORT_USED ; Untyped ; -; PORT_CLK1 ; PORT_USED ; Untyped ; -; PORT_CLK2 ; PORT_USED ; Untyped ; -; PORT_CLK3 ; PORT_USED ; Untyped ; -; PORT_CLK4 ; PORT_USED ; Untyped ; -; PORT_CLK5 ; PORT_UNUSED ; Untyped ; -; PORT_CLK6 ; PORT_UNUSED ; Untyped ; -; PORT_CLK7 ; PORT_UNUSED ; Untyped ; -; PORT_CLK8 ; PORT_UNUSED ; Untyped ; -; PORT_CLK9 ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; -; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; -; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; -; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; -; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_INCLK0 ; PORT_USED ; Untyped ; -; PORT_FBIN ; PORT_UNUSED ; Untyped ; -; PORT_PLLENA ; PORT_UNUSED ; Untyped ; -; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; -; PORT_ARESET ; PORT_UNUSED ; Untyped ; -; PORT_PFDENA ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; -; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; -; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; -; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; -; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_LOCKED ; PORT_UNUSED ; Untyped ; -; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; -; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; -; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; -; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; -; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; -; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; -; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; M_TEST_SOURCE ; 5 ; Untyped ; -; C0_TEST_SOURCE ; 5 ; Untyped ; -; C1_TEST_SOURCE ; 5 ; Untyped ; -; C2_TEST_SOURCE ; 5 ; Untyped ; -; C3_TEST_SOURCE ; 5 ; Untyped ; -; C4_TEST_SOURCE ; 5 ; Untyped ; -; C5_TEST_SOURCE ; 5 ; Untyped ; -; C6_TEST_SOURCE ; 5 ; Untyped ; -; C7_TEST_SOURCE ; 5 ; Untyped ; -; C8_TEST_SOURCE ; 5 ; Untyped ; -; C9_TEST_SOURCE ; 5 ; Untyped ; -; CBXI_PARAMETER ; altpll_isv2 ; Untyped ; -; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; -; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; -; WIDTH_CLOCK ; 5 ; Signed Integer ; -; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; -; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; -; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+-------------------------------+--------------------+--------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll4:inst22|altpll:altpll_component ; -+-------------------------------+-------------------+---------------------------------+ -; Parameter Name ; Value ; Type ; -+-------------------------------+-------------------+---------------------------------+ -; OPERATION_MODE ; NORMAL ; Untyped ; -; PLL_TYPE ; AUTO ; Untyped ; -; QUALIFY_CONF_DONE ; OFF ; Untyped ; -; COMPENSATE_CLOCK ; CLK0 ; Untyped ; -; SCAN_CHAIN ; LONG ; Untyped ; -; PRIMARY_CLOCK ; INCLK0 ; Untyped ; -; INCLK0_INPUT_FREQUENCY ; 20833 ; Untyped ; -; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; -; GATE_LOCK_SIGNAL ; NO ; Untyped ; -; GATE_LOCK_COUNTER ; 0 ; Untyped ; -; LOCK_HIGH ; 1 ; Untyped ; -; LOCK_LOW ; 1 ; Untyped ; -; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; -; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; -; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; -; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; -; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; -; SKIP_VCO ; OFF ; Untyped ; -; SWITCH_OVER_COUNTER ; 0 ; Untyped ; -; SWITCH_OVER_TYPE ; AUTO ; Untyped ; -; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; -; BANDWIDTH ; 0 ; Untyped ; -; BANDWIDTH_TYPE ; AUTO ; Untyped ; -; SPREAD_FREQUENCY ; 0 ; Untyped ; -; DOWN_SPREAD ; 0 ; Untyped ; -; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; -; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; -; CLK9_MULTIPLY_BY ; 0 ; Untyped ; -; CLK8_MULTIPLY_BY ; 0 ; Untyped ; -; CLK7_MULTIPLY_BY ; 0 ; Untyped ; -; CLK6_MULTIPLY_BY ; 0 ; Untyped ; -; CLK5_MULTIPLY_BY ; 1 ; Untyped ; -; CLK4_MULTIPLY_BY ; 1 ; Untyped ; -; CLK3_MULTIPLY_BY ; 1 ; Untyped ; -; CLK2_MULTIPLY_BY ; 1 ; Untyped ; -; CLK1_MULTIPLY_BY ; 1 ; Untyped ; -; CLK0_MULTIPLY_BY ; 2 ; Untyped ; -; CLK9_DIVIDE_BY ; 0 ; Untyped ; -; CLK8_DIVIDE_BY ; 0 ; Untyped ; -; CLK7_DIVIDE_BY ; 0 ; Untyped ; -; CLK6_DIVIDE_BY ; 0 ; Untyped ; -; CLK5_DIVIDE_BY ; 1 ; Untyped ; -; CLK4_DIVIDE_BY ; 1 ; Untyped ; -; CLK3_DIVIDE_BY ; 1 ; Untyped ; -; CLK2_DIVIDE_BY ; 1 ; Untyped ; -; CLK1_DIVIDE_BY ; 1 ; Untyped ; -; CLK0_DIVIDE_BY ; 1 ; Untyped ; -; CLK9_PHASE_SHIFT ; 0 ; Untyped ; -; CLK8_PHASE_SHIFT ; 0 ; Untyped ; -; CLK7_PHASE_SHIFT ; 0 ; Untyped ; -; CLK6_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_PHASE_SHIFT ; 0 ; Untyped ; -; CLK4_PHASE_SHIFT ; 0 ; Untyped ; -; CLK3_PHASE_SHIFT ; 0 ; Untyped ; -; CLK2_PHASE_SHIFT ; 0 ; Untyped ; -; CLK1_PHASE_SHIFT ; 0 ; Untyped ; -; CLK0_PHASE_SHIFT ; 0 ; Untyped ; -; CLK5_TIME_DELAY ; 0 ; Untyped ; -; CLK4_TIME_DELAY ; 0 ; Untyped ; -; CLK3_TIME_DELAY ; 0 ; Untyped ; -; CLK2_TIME_DELAY ; 0 ; Untyped ; -; CLK1_TIME_DELAY ; 0 ; Untyped ; -; CLK0_TIME_DELAY ; 0 ; Untyped ; -; CLK9_DUTY_CYCLE ; 50 ; Untyped ; -; CLK8_DUTY_CYCLE ; 50 ; Untyped ; -; CLK7_DUTY_CYCLE ; 50 ; Untyped ; -; CLK6_DUTY_CYCLE ; 50 ; Untyped ; -; CLK5_DUTY_CYCLE ; 50 ; Untyped ; -; CLK4_DUTY_CYCLE ; 50 ; Untyped ; -; CLK3_DUTY_CYCLE ; 50 ; Untyped ; -; CLK2_DUTY_CYCLE ; 50 ; Untyped ; -; CLK1_DUTY_CYCLE ; 50 ; Untyped ; -; CLK0_DUTY_CYCLE ; 50 ; Untyped ; -; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; -; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; -; LOCK_WINDOW_UI ; 0.05 ; Untyped ; -; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; -; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; -; DPA_MULTIPLY_BY ; 0 ; Untyped ; -; DPA_DIVIDE_BY ; 1 ; Untyped ; -; DPA_DIVIDER ; 0 ; Untyped ; -; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; -; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; -; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; -; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; -; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; -; VCO_MULTIPLY_BY ; 0 ; Untyped ; -; VCO_DIVIDE_BY ; 0 ; Untyped ; -; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; -; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; -; VCO_MIN ; 0 ; Untyped ; -; VCO_MAX ; 0 ; Untyped ; -; VCO_CENTER ; 0 ; Untyped ; -; PFD_MIN ; 0 ; Untyped ; -; PFD_MAX ; 0 ; Untyped ; -; M_INITIAL ; 0 ; Untyped ; -; M ; 0 ; Untyped ; -; N ; 1 ; Untyped ; -; M2 ; 1 ; Untyped ; -; N2 ; 1 ; Untyped ; -; SS ; 1 ; Untyped ; -; C0_HIGH ; 0 ; Untyped ; -; C1_HIGH ; 0 ; Untyped ; -; C2_HIGH ; 0 ; Untyped ; -; C3_HIGH ; 0 ; Untyped ; -; C4_HIGH ; 0 ; Untyped ; -; C5_HIGH ; 0 ; Untyped ; -; C6_HIGH ; 0 ; Untyped ; -; C7_HIGH ; 0 ; Untyped ; -; C8_HIGH ; 0 ; Untyped ; -; C9_HIGH ; 0 ; Untyped ; -; C0_LOW ; 0 ; Untyped ; -; C1_LOW ; 0 ; Untyped ; -; C2_LOW ; 0 ; Untyped ; -; C3_LOW ; 0 ; Untyped ; -; C4_LOW ; 0 ; Untyped ; -; C5_LOW ; 0 ; Untyped ; -; C6_LOW ; 0 ; Untyped ; -; C7_LOW ; 0 ; Untyped ; -; C8_LOW ; 0 ; Untyped ; -; C9_LOW ; 0 ; Untyped ; -; C0_INITIAL ; 0 ; Untyped ; -; C1_INITIAL ; 0 ; Untyped ; -; C2_INITIAL ; 0 ; Untyped ; -; C3_INITIAL ; 0 ; Untyped ; -; C4_INITIAL ; 0 ; Untyped ; -; C5_INITIAL ; 0 ; Untyped ; -; C6_INITIAL ; 0 ; Untyped ; -; C7_INITIAL ; 0 ; Untyped ; -; C8_INITIAL ; 0 ; Untyped ; -; C9_INITIAL ; 0 ; Untyped ; -; C0_MODE ; BYPASS ; Untyped ; -; C1_MODE ; BYPASS ; Untyped ; -; C2_MODE ; BYPASS ; Untyped ; -; C3_MODE ; BYPASS ; Untyped ; -; C4_MODE ; BYPASS ; Untyped ; -; C5_MODE ; BYPASS ; Untyped ; -; C6_MODE ; BYPASS ; Untyped ; -; C7_MODE ; BYPASS ; Untyped ; -; C8_MODE ; BYPASS ; Untyped ; -; C9_MODE ; BYPASS ; Untyped ; -; C0_PH ; 0 ; Untyped ; -; C1_PH ; 0 ; Untyped ; -; C2_PH ; 0 ; Untyped ; -; C3_PH ; 0 ; Untyped ; -; C4_PH ; 0 ; Untyped ; -; C5_PH ; 0 ; Untyped ; -; C6_PH ; 0 ; Untyped ; -; C7_PH ; 0 ; Untyped ; -; C8_PH ; 0 ; Untyped ; -; C9_PH ; 0 ; Untyped ; -; L0_HIGH ; 1 ; Untyped ; -; L1_HIGH ; 1 ; Untyped ; -; G0_HIGH ; 1 ; Untyped ; -; G1_HIGH ; 1 ; Untyped ; -; G2_HIGH ; 1 ; Untyped ; -; G3_HIGH ; 1 ; Untyped ; -; E0_HIGH ; 1 ; Untyped ; -; E1_HIGH ; 1 ; Untyped ; -; E2_HIGH ; 1 ; Untyped ; -; E3_HIGH ; 1 ; Untyped ; -; L0_LOW ; 1 ; Untyped ; -; L1_LOW ; 1 ; Untyped ; -; G0_LOW ; 1 ; Untyped ; -; G1_LOW ; 1 ; Untyped ; -; G2_LOW ; 1 ; Untyped ; -; G3_LOW ; 1 ; Untyped ; -; E0_LOW ; 1 ; Untyped ; -; E1_LOW ; 1 ; Untyped ; -; E2_LOW ; 1 ; Untyped ; -; E3_LOW ; 1 ; Untyped ; -; L0_INITIAL ; 1 ; Untyped ; -; L1_INITIAL ; 1 ; Untyped ; -; G0_INITIAL ; 1 ; Untyped ; -; G1_INITIAL ; 1 ; Untyped ; -; G2_INITIAL ; 1 ; Untyped ; -; G3_INITIAL ; 1 ; Untyped ; -; E0_INITIAL ; 1 ; Untyped ; -; E1_INITIAL ; 1 ; Untyped ; -; E2_INITIAL ; 1 ; Untyped ; -; E3_INITIAL ; 1 ; Untyped ; -; L0_MODE ; BYPASS ; Untyped ; -; L1_MODE ; BYPASS ; Untyped ; -; G0_MODE ; BYPASS ; Untyped ; -; G1_MODE ; BYPASS ; Untyped ; -; G2_MODE ; BYPASS ; Untyped ; -; G3_MODE ; BYPASS ; Untyped ; -; E0_MODE ; BYPASS ; Untyped ; -; E1_MODE ; BYPASS ; Untyped ; -; E2_MODE ; BYPASS ; Untyped ; -; E3_MODE ; BYPASS ; Untyped ; -; L0_PH ; 0 ; Untyped ; -; L1_PH ; 0 ; Untyped ; -; G0_PH ; 0 ; Untyped ; -; G1_PH ; 0 ; Untyped ; -; G2_PH ; 0 ; Untyped ; -; G3_PH ; 0 ; Untyped ; -; E0_PH ; 0 ; Untyped ; -; E1_PH ; 0 ; Untyped ; -; E2_PH ; 0 ; Untyped ; -; E3_PH ; 0 ; Untyped ; -; M_PH ; 0 ; Untyped ; -; C1_USE_CASC_IN ; OFF ; Untyped ; -; C2_USE_CASC_IN ; OFF ; Untyped ; -; C3_USE_CASC_IN ; OFF ; Untyped ; -; C4_USE_CASC_IN ; OFF ; Untyped ; -; C5_USE_CASC_IN ; OFF ; Untyped ; -; C6_USE_CASC_IN ; OFF ; Untyped ; -; C7_USE_CASC_IN ; OFF ; Untyped ; -; C8_USE_CASC_IN ; OFF ; Untyped ; -; C9_USE_CASC_IN ; OFF ; Untyped ; -; CLK0_COUNTER ; G0 ; Untyped ; -; CLK1_COUNTER ; G0 ; Untyped ; -; CLK2_COUNTER ; G0 ; Untyped ; -; CLK3_COUNTER ; G0 ; Untyped ; -; CLK4_COUNTER ; G0 ; Untyped ; -; CLK5_COUNTER ; G0 ; Untyped ; -; CLK6_COUNTER ; E0 ; Untyped ; -; CLK7_COUNTER ; E1 ; Untyped ; -; CLK8_COUNTER ; E2 ; Untyped ; -; CLK9_COUNTER ; E3 ; Untyped ; -; L0_TIME_DELAY ; 0 ; Untyped ; -; L1_TIME_DELAY ; 0 ; Untyped ; -; G0_TIME_DELAY ; 0 ; Untyped ; -; G1_TIME_DELAY ; 0 ; Untyped ; -; G2_TIME_DELAY ; 0 ; Untyped ; -; G3_TIME_DELAY ; 0 ; Untyped ; -; E0_TIME_DELAY ; 0 ; Untyped ; -; E1_TIME_DELAY ; 0 ; Untyped ; -; E2_TIME_DELAY ; 0 ; Untyped ; -; E3_TIME_DELAY ; 0 ; Untyped ; -; M_TIME_DELAY ; 0 ; Untyped ; -; N_TIME_DELAY ; 0 ; Untyped ; -; EXTCLK3_COUNTER ; E3 ; Untyped ; -; EXTCLK2_COUNTER ; E2 ; Untyped ; -; EXTCLK1_COUNTER ; E1 ; Untyped ; -; EXTCLK0_COUNTER ; E0 ; Untyped ; -; ENABLE0_COUNTER ; L0 ; Untyped ; -; ENABLE1_COUNTER ; L0 ; Untyped ; -; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; -; LOOP_FILTER_R ; 1.000000 ; Untyped ; -; LOOP_FILTER_C ; 5 ; Untyped ; -; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; -; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; -; VCO_POST_SCALE ; 0 ; Untyped ; -; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; -; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; -; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; -; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; -; PORT_CLK0 ; PORT_USED ; Untyped ; -; PORT_CLK1 ; PORT_UNUSED ; Untyped ; -; PORT_CLK2 ; PORT_UNUSED ; Untyped ; -; PORT_CLK3 ; PORT_UNUSED ; Untyped ; -; PORT_CLK4 ; PORT_UNUSED ; Untyped ; -; PORT_CLK5 ; PORT_UNUSED ; Untyped ; -; PORT_CLK6 ; PORT_UNUSED ; Untyped ; -; PORT_CLK7 ; PORT_UNUSED ; Untyped ; -; PORT_CLK8 ; PORT_UNUSED ; Untyped ; -; PORT_CLK9 ; PORT_UNUSED ; Untyped ; -; PORT_SCANDATA ; PORT_USED ; Untyped ; -; PORT_SCANDATAOUT ; PORT_USED ; Untyped ; -; PORT_SCANDONE ; PORT_USED ; Untyped ; -; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; -; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; -; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; -; PORT_INCLK0 ; PORT_USED ; Untyped ; -; PORT_FBIN ; PORT_UNUSED ; Untyped ; -; PORT_PLLENA ; PORT_UNUSED ; Untyped ; -; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; -; PORT_ARESET ; PORT_USED ; Untyped ; -; PORT_PFDENA ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLK ; PORT_USED ; Untyped ; -; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; -; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; -; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; -; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; -; PORT_LOCKED ; PORT_USED ; Untyped ; -; PORT_CONFIGUPDATE ; PORT_USED ; Untyped ; -; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; -; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; -; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; -; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; -; PORT_SCANCLKENA ; PORT_USED ; Untyped ; -; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; -; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; -; M_TEST_SOURCE ; 5 ; Untyped ; -; C0_TEST_SOURCE ; 5 ; Untyped ; -; C1_TEST_SOURCE ; 5 ; Untyped ; -; C2_TEST_SOURCE ; 5 ; Untyped ; -; C3_TEST_SOURCE ; 5 ; Untyped ; -; C4_TEST_SOURCE ; 5 ; Untyped ; -; C5_TEST_SOURCE ; 5 ; Untyped ; -; C6_TEST_SOURCE ; 5 ; Untyped ; -; C7_TEST_SOURCE ; 5 ; Untyped ; -; C8_TEST_SOURCE ; 5 ; Untyped ; -; C9_TEST_SOURCE ; 5 ; Untyped ; -; CBXI_PARAMETER ; altpll_c6j2 ; Untyped ; -; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; -; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; -; WIDTH_CLOCK ; 5 ; Untyped ; -; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; -; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; SCAN_CHAIN_MIF_FILE ; altpll4.mif ; Untyped ; -; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+-------------------------------+-------------------+---------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------+ -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -+-----------------+-------+---------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; -+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ -; BYTE_SIZE_BLOCK ; 8 ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH_BYTEENA ; 1 ; Untyped ; -; OPERATION_MODE ; SINGLE_PORT ; Untyped ; -; WIDTH_A ; 1 ; Untyped ; -; WIDTHAD_A ; 8 ; Untyped ; -; NUMWORDS_A ; 144 ; Untyped ; -; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; -; ADDRESS_ACLR_A ; NONE ; Untyped ; -; OUTDATA_ACLR_A ; NONE ; Untyped ; -; WRCONTROL_ACLR_A ; NONE ; Untyped ; -; INDATA_ACLR_A ; NONE ; Untyped ; -; BYTEENA_ACLR_A ; NONE ; Untyped ; -; WIDTH_B ; 1 ; Untyped ; -; WIDTHAD_B ; 1 ; Untyped ; -; NUMWORDS_B ; 1 ; Untyped ; -; INDATA_REG_B ; CLOCK1 ; Untyped ; -; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; -; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; -; ADDRESS_REG_B ; CLOCK1 ; Untyped ; -; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; -; BYTEENA_REG_B ; CLOCK1 ; Untyped ; -; INDATA_ACLR_B ; NONE ; Untyped ; -; WRCONTROL_ACLR_B ; NONE ; Untyped ; -; ADDRESS_ACLR_B ; NONE ; Untyped ; -; OUTDATA_ACLR_B ; NONE ; Untyped ; -; RDCONTROL_ACLR_B ; NONE ; Untyped ; -; BYTEENA_ACLR_B ; NONE ; Untyped ; -; WIDTH_BYTEENA_A ; 1 ; Untyped ; -; WIDTH_BYTEENA_B ; 1 ; Untyped ; -; RAM_BLOCK_TYPE ; AUTO ; Untyped ; -; BYTE_SIZE ; 8 ; Untyped ; -; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; -; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; -; INIT_FILE ; UNUSED ; Untyped ; -; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; -; MAXIMUM_DEPTH ; 0 ; Untyped ; -; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; -; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; -; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; -; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; -; ENABLE_ECC ; FALSE ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; altsyncram_46r ; Untyped ; -+------------------------------------+----------------------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5 ; -+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 9 ; Untyped ; -; LPM_REPRESENTATION ; SIGNED ; Untyped ; -; LPM_DIRECTION ; DEFAULT ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; REGISTERED_AT_END ; 0 ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; -; USE_CS_BUFFERS ; 1 ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; USE_WYS ; OFF ; Untyped ; -; STYLE ; FAST ; Untyped ; -; CBXI_PARAMETER ; add_sub_hpa ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6 ; -+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_REPRESENTATION ; SIGNED ; Untyped ; -; LPM_DIRECTION ; DEFAULT ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; REGISTERED_AT_END ; 0 ; Untyped ; -; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ; -; USE_CS_BUFFERS ; 1 ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; USE_WYS ; OFF ; Untyped ; -; STYLE ; FAST ; Untyped ; -; CBXI_PARAMETER ; add_sub_k8a ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7 ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; lpm_width ; 8 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; CHAIN_SIZE ; 8 ; Untyped ; -; ONE_INPUT_IS_CONSTANT ; NO ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CASCADE_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; CASCADE_CHAIN_LENGTH ; 2 ; CASCADE_CHAIN_LENGTH ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; cmpr_tnd ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1 ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_DIRECTION ; DOWN ; Untyped ; -; LPM_MODULUS ; 144 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_30l ; Untyped ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr12 ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_DIRECTION ; DOWN ; Untyped ; -; LPM_MODULUS ; 144 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_30l ; Untyped ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13 ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 6 ; Untyped ; -; LPM_DIRECTION ; DOWN ; Untyped ; -; LPM_MODULUS ; 0 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_qij ; Untyped ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14 ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 5 ; Untyped ; -; LPM_DIRECTION ; DOWN ; Untyped ; -; LPM_MODULUS ; 0 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_pij ; Untyped ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr15 ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_DIRECTION ; DOWN ; Untyped ; -; LPM_MODULUS ; 144 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_30l ; Untyped ; -+------------------------+-------------+---------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2 ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 8 ; Untyped ; -; LPM_DIRECTION ; UP ; Untyped ; -; LPM_MODULUS ; 0 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_9cj ; Untyped ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr3 ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 5 ; Untyped ; -; LPM_DIRECTION ; DOWN ; Untyped ; -; LPM_MODULUS ; 0 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_pij ; Untyped ; -+------------------------+-------------+--------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11 ; -+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 3 ; Untyped ; -; LPM_DECODES ; 5 ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; CASCADE_CHAIN ; MANUAL ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; decode_2af ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+----------------------------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: lpm_ff0:inst1|lpm_ff:lpm_ff_component ; -+------------------------+-------------+---------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+---------------------------------------------+ -; LPM_WIDTH ; 32 ; Signed Integer ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_FFTYPE ; DFF ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; NOTHING ; Untyped ; -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -+------------------------+-------------+---------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00000|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00004|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: interrupt_handler:nobody|lpm_bustri_BYT:$00006|lpm_bustri:lpm_bustri_component ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -; LPM_WIDTH ; 8 ; Signed Integer ; -+----------------+-------+----------------------------------------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+----------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: lpm_counter0:inst18|lpm_counter:lpm_counter_component ; -+------------------------+-------------+-------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+-------------+-------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTH ; 18 ; Signed Integer ; -; LPM_DIRECTION ; UP ; Untyped ; -; LPM_MODULUS ; 0 ; Untyped ; -; LPM_AVALUE ; UNUSED ; Untyped ; -; LPM_SVALUE ; UNUSED ; Untyped ; -; LPM_PORT_UPDOWN ; PORT_UNUSED ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ; -; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ; -; CARRY_CNT_EN ; SMART ; Untyped ; -; LABWIDE_SCLR ; ON ; Untyped ; -; USE_NEW_VERSION ; TRUE ; Untyped ; -; CBXI_PARAMETER ; cntr_mph ; Untyped ; -+------------------------+-------------+-------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altddio_out3:inst5|altddio_out:altddio_out_component ; -+------------------------+--------------+-----------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------+-----------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 1 ; Signed Integer ; -; POWER_UP_HIGH ; OFF ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; -+------------------------+--------------+-----------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altddio_out3:inst6|altddio_out:altddio_out_component ; -+------------------------+--------------+-----------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------+-----------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 1 ; Signed Integer ; -; POWER_UP_HIGH ; OFF ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; -+------------------------+--------------+-----------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altddio_out3:inst8|altddio_out:altddio_out_component ; -+------------------------+--------------+-----------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------+-----------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 1 ; Signed Integer ; -; POWER_UP_HIGH ; OFF ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; -+------------------------+--------------+-----------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+---------------------------------------------------------------------------------------------------+ -; Parameter Settings for User Entity Instance: altddio_out3:inst9|altddio_out:altddio_out_component ; -+------------------------+--------------+-----------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------+--------------+-----------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; WIDTH ; 1 ; Signed Integer ; -; POWER_UP_HIGH ; OFF ; Untyped ; -; OE_REG ; UNUSED ; Untyped ; -; extend_oe_disable ; UNUSED ; Untyped ; -; INTENDED_DEVICE_FAMILY ; Cyclone III ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CBXI_PARAMETER ; ddio_out_31f ; Untyped ; -+------------------------+--------------+-----------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; -+------------------------------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------------------+-------------+---------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTHA ; 12 ; Untyped ; -; LPM_WIDTHB ; 6 ; Untyped ; -; LPM_WIDTHP ; 18 ; Untyped ; -; LPM_WIDTHR ; 18 ; Untyped ; -; LPM_WIDTHS ; 1 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; LATENCY ; 0 ; Untyped ; -; INPUT_A_IS_CONSTANT ; NO ; Untyped ; -; INPUT_B_IS_CONSTANT ; NO ; Untyped ; -; USE_EAB ; OFF ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; -; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; -; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; -; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; -; CBXI_PARAMETER ; mult_cat ; Untyped ; -; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; -; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; -; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; -+------------------------------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; -+------------------------------------------------+-------------+--------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------------------+-------------+--------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTHA ; 12 ; Untyped ; -; LPM_WIDTHB ; 5 ; Untyped ; -; LPM_WIDTHP ; 17 ; Untyped ; -; LPM_WIDTHR ; 17 ; Untyped ; -; LPM_WIDTHS ; 1 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; LATENCY ; 0 ; Untyped ; -; INPUT_A_IS_CONSTANT ; NO ; Untyped ; -; INPUT_B_IS_CONSTANT ; NO ; Untyped ; -; USE_EAB ; OFF ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; -; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; -; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; -; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; -; CBXI_PARAMETER ; mult_aat ; Untyped ; -; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; -; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; -; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; -+------------------------------------------------+-------------+--------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; Parameter Settings for Inferred Entity Instance: Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; -+------------------------------------------------+-------------+---------------------------------------------------------------------+ -; Parameter Name ; Value ; Type ; -+------------------------------------------------+-------------+---------------------------------------------------------------------+ -; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; -; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; -; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; -; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; -; LPM_WIDTHA ; 12 ; Untyped ; -; LPM_WIDTHB ; 5 ; Untyped ; -; LPM_WIDTHP ; 17 ; Untyped ; -; LPM_WIDTHR ; 17 ; Untyped ; -; LPM_WIDTHS ; 1 ; Untyped ; -; LPM_REPRESENTATION ; UNSIGNED ; Untyped ; -; LPM_PIPELINE ; 0 ; Untyped ; -; LATENCY ; 0 ; Untyped ; -; INPUT_A_IS_CONSTANT ; NO ; Untyped ; -; INPUT_B_IS_CONSTANT ; NO ; Untyped ; -; USE_EAB ; OFF ; Untyped ; -; MAXIMIZE_SPEED ; 5 ; Untyped ; -; DEVICE_FAMILY ; Cyclone III ; Untyped ; -; CARRY_CHAIN ; MANUAL ; Untyped ; -; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ; -; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ; -; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; -; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ; -; CBXI_PARAMETER ; mult_aat ; Untyped ; -; INPUT_A_FIXED_VALUE ; Bx ; Untyped ; -; INPUT_B_FIXED_VALUE ; Bx ; Untyped ; -; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ; -+------------------------------------------------+-------------+---------------------------------------------------------------------+ -Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". - - -+------------------------------------------------------------------------+ -; altpll Parameter Settings by Entity Instance ; -+-------------------------------+----------------------------------------+ -; Name ; Value ; -+-------------------------------+----------------------------------------+ -; Number of entity instances ; 4 ; -; Entity Instance ; altpll1:inst|altpll:altpll_component ; -; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; -; -- PLL_TYPE ; AUTO ; -; -- PRIMARY_CLOCK ; INCLK0 ; -; -- INCLK0_INPUT_FREQUENCY ; 30303 ; -; -- INCLK1_INPUT_FREQUENCY ; 0 ; -; -- VCO_MULTIPLY_BY ; 0 ; -; -- VCO_DIVIDE_BY ; 0 ; -; Entity Instance ; altpll3:inst13|altpll:altpll_component ; -; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; -; -- PLL_TYPE ; AUTO ; -; -- PRIMARY_CLOCK ; INCLK0 ; -; -- INCLK0_INPUT_FREQUENCY ; 30303 ; -; -- INCLK1_INPUT_FREQUENCY ; 0 ; -; -- VCO_MULTIPLY_BY ; 0 ; -; -- VCO_DIVIDE_BY ; 0 ; -; Entity Instance ; altpll2:inst12|altpll:altpll_component ; -; -- OPERATION_MODE ; SOURCE_SYNCHRONOUS ; -; -- PLL_TYPE ; AUTO ; -; -- PRIMARY_CLOCK ; INCLK0 ; -; -- INCLK0_INPUT_FREQUENCY ; 30303 ; -; -- INCLK1_INPUT_FREQUENCY ; 0 ; -; -- VCO_MULTIPLY_BY ; 0 ; -; -- VCO_DIVIDE_BY ; 0 ; -; Entity Instance ; altpll4:inst22|altpll:altpll_component ; -; -- OPERATION_MODE ; NORMAL ; -; -- PLL_TYPE ; AUTO ; -; -- PRIMARY_CLOCK ; INCLK0 ; -; -- INCLK0_INPUT_FREQUENCY ; 20833 ; -; -- INCLK1_INPUT_FREQUENCY ; 0 ; -; -- VCO_MULTIPLY_BY ; 0 ; -; -- VCO_DIVIDE_BY ; 0 ; -+-------------------------------+----------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------+ -; lpm_shiftreg Parameter Settings by Entity Instance ; -+----------------------------+---------------------------------------------------------------------------------+ -; Name ; Value ; -+----------------------------+---------------------------------------------------------------------------------+ -; Number of entity instances ; 11 ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 5 ; -; -- LPM_DIRECTION ; RIGHT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 5 ; -; -- LPM_DIRECTION ; RIGHT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 5 ; -; -- LPM_DIRECTION ; RIGHT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component ; -; -- LPM_WIDTH ; 16 ; -; -- LPM_DIRECTION ; LEFT ; -+----------------------------+---------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------+ -; dcfifo Parameter Settings by Entity Instance ; -+----------------------------+------------------------------------------------------------------+ -; Name ; Value ; -+----------------------------+------------------------------------------------------------------+ -; Number of entity instances ; 1 ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component ; -; -- FIFO Type ; Dual Clock ; -; -- LPM_WIDTH ; 128 ; -; -- LPM_NUMWORDS ; 512 ; -; -- LPM_SHOWAHEAD ; OFF ; -; -- USE_EAB ; ON ; -+----------------------------+------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------+ -; scfifo Parameter Settings by Entity Instance ; -+----------------------------+------------------------------------------------------------------+ -; Name ; Value ; -+----------------------------+------------------------------------------------------------------+ -; Number of entity instances ; 1 ; -; Entity Instance ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component ; -; -- FIFO Type ; Single Clock ; -; -- lpm_width ; 128 ; -; -- LPM_NUMWORDS ; 128 ; -; -- LPM_SHOWAHEAD ; ON ; -; -- USE_EAB ; ON ; -+----------------------------+------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; altsyncram Parameter Settings by Entity Instance ; -+-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ -; Name ; Value ; -+-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ -; Number of entity instances ; 10 ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 6 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 6 ; -; -- NUMWORDS_B ; 256 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 6 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 6 ; -; -- NUMWORDS_B ; 256 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 6 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 6 ; -; -- NUMWORDS_B ; 256 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 3 ; -; -- NUMWORDS_A ; 16 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 3 ; -; -- NUMWORDS_B ; 16 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 3 ; -; -- NUMWORDS_A ; 16 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 3 ; -; -- NUMWORDS_B ; 16 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 3 ; -; -- NUMWORDS_A ; 16 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 3 ; -; -- NUMWORDS_B ; 16 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 8 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 8 ; -; -- NUMWORDS_B ; 256 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 8 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 8 ; -; -- NUMWORDS_B ; 256 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component ; -; -- OPERATION_MODE ; BIDIR_DUAL_PORT ; -; -- WIDTH_A ; 8 ; -; -- NUMWORDS_A ; 256 ; -; -- OUTDATA_REG_A ; CLOCK0 ; -; -- WIDTH_B ; 8 ; -; -- NUMWORDS_B ; 256 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; CLOCK1 ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -; Entity Instance ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4 ; -; -- OPERATION_MODE ; SINGLE_PORT ; -; -- WIDTH_A ; 1 ; -; -- NUMWORDS_A ; 144 ; -; -- OUTDATA_REG_A ; UNREGISTERED ; -; -- WIDTH_B ; 1 ; -; -- NUMWORDS_B ; 1 ; -; -- ADDRESS_REG_B ; CLOCK1 ; -; -- OUTDATA_REG_B ; UNREGISTERED ; -; -- RAM_BLOCK_TYPE ; AUTO ; -; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; -+-------------------------------------------+-------------------------------------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; lpm_mult Parameter Settings by Entity Instance ; -+---------------------------------------+-----------------------------------------------------------------------------------+ -; Name ; Value ; -+---------------------------------------+-----------------------------------------------------------------------------------+ -; Number of entity instances ; 3 ; -; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14 ; -; -- LPM_WIDTHA ; 12 ; -; -- LPM_WIDTHB ; 6 ; -; -- LPM_WIDTHP ; 18 ; -; -- LPM_REPRESENTATION ; UNSIGNED ; -; -- INPUT_A_IS_CONSTANT ; NO ; -; -- INPUT_B_IS_CONSTANT ; NO ; -; -- USE_EAB ; OFF ; -; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; -; -- INPUT_A_FIXED_VALUE ; Bx ; -; -- INPUT_B_FIXED_VALUE ; Bx ; -; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6 ; -; -- LPM_WIDTHA ; 12 ; -; -- LPM_WIDTHB ; 5 ; -; -- LPM_WIDTHP ; 17 ; -; -- LPM_REPRESENTATION ; UNSIGNED ; -; -- INPUT_A_IS_CONSTANT ; NO ; -; -- INPUT_B_IS_CONSTANT ; NO ; -; -- USE_EAB ; OFF ; -; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; -; -- INPUT_A_FIXED_VALUE ; Bx ; -; -- INPUT_B_FIXED_VALUE ; Bx ; -; Entity Instance ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_12 ; -; -- LPM_WIDTHA ; 12 ; -; -- LPM_WIDTHB ; 5 ; -; -- LPM_WIDTHP ; 17 ; -; -- LPM_REPRESENTATION ; UNSIGNED ; -; -- INPUT_A_IS_CONSTANT ; NO ; -; -- INPUT_B_IS_CONSTANT ; NO ; -; -- USE_EAB ; OFF ; -; -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; -; -- INPUT_A_FIXED_VALUE ; Bx ; -; -- INPUT_B_FIXED_VALUE ; Bx ; -+---------------------------------------+-----------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" ; -+-------------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+-------------+--------+----------+-------------------------------------------------------------------------------------+ -; seln ; Input ; Info ; Stuck at VCC ; -; bc2 ; Input ; Info ; Stuck at VCC ; -; a9n ; Input ; Info ; Stuck at GND ; -; a8 ; Input ; Info ; Stuck at VCC ; -; da_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; io_a_in ; Input ; Info ; Stuck at GND ; -; io_a_out[2] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; io_a_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; io_b_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+-------------+--------+----------+-------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" ; -+----------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+-------------------------------------------------------------------------------------+ -; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; gpip_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; gpip_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; iein ; Input ; Info ; Stuck at GND ; -; ieon ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; tai ; Input ; Info ; Stuck at GND ; -; tao ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; tbo ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; tco ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; so_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; rrn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; trn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+----------+--------+----------+-------------------------------------------------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI" ; -+---------+--------+----------+------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+------------------------------------------------------------------------------------------+ -; cs2n ; Input ; Info ; Stuck at GND ; -; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; ctsn ; Input ; Info ; Stuck at GND ; -; dcdn ; Input ; Info ; Stuck at GND ; -; rtsn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" ; -+---------+--------+----------+----------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+----------------------------------------------------------------------------------------------+ -; cs1 ; Input ; Info ; Stuck at VCC ; -; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; ctsn ; Input ; Info ; Stuck at GND ; -; dcdn ; Input ; Info ; Stuck at GND ; -; rtsn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+---------+--------+----------+----------------------------------------------------------------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" ; -+------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ -; icr_out[7] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; icr_out[5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+------------+--------+----------+-------------------------------------------------------------------------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" ; -+----------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+----------+--------+----------+-------------------------------------------------------------------------------------+ -; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; csn ; Input ; Info ; Stuck at VCC ; -; eopn ; Input ; Info ; Stuck at VCC ; -; ready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; ack_inn ; Input ; Info ; Stuck at VCC ; -; ack_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; atn_inn ; Input ; Info ; Stuck at VCC ; -; atn_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; req_outn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; req_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; ion_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; io_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; cdn_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; cd_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; msg_outn ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; msg_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+----------+--------+----------+-------------------------------------------------------------------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ -; data_en ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -; dden ; Input ; Info ; Stuck at GND ; -+---------+--------+----------+-------------------------------------------------------------------------------------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Analysis & Synthesis - Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - Info: Processing started: Wed Dec 15 02:20:37 2010 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_control.vhd - Info: Found design unit 1: WF5380_CONTROL-BEHAVIOUR - Info: Found entity 1: WF5380_CONTROL -Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_pkg.vhd - Info: Found design unit 1: WF5380_PKG -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_registers.vhd - Info: Found design unit 1: WF5380_REGISTERS-BEHAVIOUR - Info: Found entity 1: WF5380_REGISTERS -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_soc_top.vhd - Info: Found design unit 1: WF5380_TOP_SOC-STRUCTURE - Info: Found entity 1: WF5380_TOP_SOC -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf5380/wf5380_top.vhd - Info: Found design unit 1: WF5380_TOP-STRUCTURE - Info: Found entity 1: WF5380_TOP -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_am_detector.vhd - Info: Found design unit 1: WF1772IP_AM_DETECTOR-BEHAVIOR - Info: Found entity 1: WF1772IP_AM_DETECTOR -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo0.vhd - Info: Found design unit 1: dcfifo0-SYN - Info: Found entity 1: dcfifo0 -Info: Found 1 design units, including 1 entities, in source file video/ddr_ctr.tdf - Info: Found entity 1: DDR_CTR -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri0.vhd - Info: Found design unit 1: lpm_bustri0-SYN - Info: Found entity 1: lpm_bustri0 -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_control.vhd - Info: Found design unit 1: WF1772IP_CONTROL-BEHAVIOR - Info: Found entity 1: WF1772IP_CONTROL -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_crc_logic.vhd - Info: Found design unit 1: WF1772IP_CRC_LOGIC-BEHAVIOR - Info: Found entity 1: WF1772IP_CRC_LOGIC -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_digital_pll.vhd - Info: Found design unit 1: WF1772IP_DIGITAL_PLL-BEHAVIOR - Info: Found entity 1: WF1772IP_DIGITAL_PLL -Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_pkg.vhd - Info: Found design unit 1: WF1772IP_PKG -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_registers.vhd - Info: Found design unit 1: WF1772IP_REGISTERS-BEHAVIOR - Info: Found entity 1: WF1772IP_REGISTERS -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top.vhd - Info: Found design unit 1: WF1772IP_TOP-STRUCTURE - Info: Found entity 1: WF1772IP_TOP -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_top_soc.vhd - Info: Found design unit 1: WF1772IP_TOP_SOC-STRUCTURE - Info: Found entity 1: WF1772IP_TOP_SOC -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_fdc1772_ip/wf1772ip_transceiver.vhd - Info: Found design unit 1: WF1772IP_TRANSCEIVER-BEHAVIOR - Info: Found entity 1: WF1772IP_TRANSCEIVER -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri5.vhd - Info: Found design unit 1: lpm_bustri5-SYN - Info: Found entity 1: lpm_bustri5 -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_ctrl_status.vhd - Info: Found design unit 1: WF6850IP_CTRL_STATUS-BEHAVIOR - Info: Found entity 1: WF6850IP_CTRL_STATUS -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri7.vhd - Info: Found design unit 1: lpm_bustri7-SYN - Info: Found entity 1: lpm_bustri7 -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_receive.vhd - Info: Found design unit 1: WF6850IP_RECEIVE-BEHAVIOR - Info: Found entity 1: WF6850IP_RECEIVE -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top.vhd - Info: Found design unit 1: WF6850IP_TOP-STRUCTURE - Info: Found entity 1: WF6850IP_TOP -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_top_soc.vhd - Info: Found design unit 1: WF6850IP_TOP_SOC-STRUCTURE - Info: Found entity 1: WF6850IP_TOP_SOC -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_uart6850_ip/wf6850ip_transmit.vhd - Info: Found design unit 1: WF6850IP_TRANSMIT-BEHAVIOR - Info: Found entity 1: WF6850IP_TRANSMIT -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_gpio.vhd - Info: Found design unit 1: WF68901IP_GPIO-BEHAVIOR - Info: Found entity 1: WF68901IP_GPIO -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_interrupts.vhd - Info: Found design unit 1: WF68901IP_INTERRUPTS-BEHAVIOR - Info: Found entity 1: WF68901IP_INTERRUPTS -Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_pkg.vhd - Info: Found design unit 1: WF68901IP_PKG -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_timers.vhd - Info: Found design unit 1: WF68901IP_TIMERS-BEHAVIOR - Info: Found entity 1: WF68901IP_TIMERS -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top.vhd - Info: Found design unit 1: WF68901IP_TOP-STRUCTURE - Info: Found entity 1: WF68901IP_TOP -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_top_soc.vhd - Info: Found design unit 1: WF68901IP_TOP_SOC-STRUCTURE - Info: Found entity 1: WF68901IP_TOP_SOC -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_ctrl.vhd - Info: Found design unit 1: WF68901IP_USART_CTRL-BEHAVIOR - Info: Found entity 1: WF68901IP_USART_CTRL -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_rx.vhd - Info: Found design unit 1: WF68901IP_USART_RX-BEHAVIOR - Info: Found entity 1: WF68901IP_USART_RX -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_top.vhd - Info: Found design unit 1: WF68901IP_USART_TOP-STRUCTURE - Info: Found entity 1: WF68901IP_USART_TOP -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_mfp68901_ip/wf68901ip_usart_tx.vhd - Info: Found design unit 1: WF68901IP_USART_TX-BEHAVIOR - Info: Found entity 1: WF68901IP_USART_TX -Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_pkg.vhd - Info: Found design unit 1: WF2149IP_PKG -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top.vhd - Info: Found design unit 1: WF2149IP_TOP-STRUCTURE - Info: Found entity 1: WF2149IP_TOP -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_top_soc.vhd - Info: Found design unit 1: WF2149IP_TOP_SOC-STRUCTURE - Info: Found entity 1: WF2149IP_TOP_SOC -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/wf_snd2149_ip/wf2149ip_wave.vhd - Info: Found design unit 1: WF2149IP_WAVE-BEHAVIOR - Info: Found entity 1: WF2149IP_WAVE -Info: Found 2 design units, including 1 entities, in source file lpm_latch0.vhd - Info: Found design unit 1: lpm_latch0-SYN - Info: Found entity 1: lpm_latch0 -Info: Found 2 design units, including 1 entities, in source file altpll1.vhd - Info: Found design unit 1: altpll1-SYN - Info: Found entity 1: altpll1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_fifodz.vhd - Info: Found design unit 1: lpm_fifodz-SYN - Info: Found entity 1: lpm_fifoDZ -Info: Found 2 design units, including 1 entities, in source file altpll2.vhd - Info: Found design unit 1: altpll2-SYN - Info: Found entity 1: altpll2 -Info: Found 2 design units, including 1 entities, in source file altpll3.vhd - Info: Found design unit 1: altpll3-SYN - Info: Found entity 1: altpll3 -Info: Found 2 design units, including 1 entities, in source file video/altdpram0.vhd - Info: Found design unit 1: altdpram0-SYN - Info: Found entity 1: altdpram0 -Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz2.vhd - Info: Found design unit 1: lpm_muxdz2-SYN - Info: Found entity 1: lpm_muxDZ2 -Info: Found 2 design units, including 1 entities, in source file video/lpm_muxdz.vhd - Info: Found design unit 1: lpm_muxdz-SYN - Info: Found entity 1: lpm_muxDZ -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri3.vhd - Info: Found design unit 1: lpm_bustri3-SYN - Info: Found entity 1: lpm_bustri3 -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff0.vhd - Info: Found design unit 1: lpm_ff0-SYN - Info: Found entity 1: lpm_ff0 -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff1.vhd - Info: Found design unit 1: lpm_ff1-SYN - Info: Found entity 1: lpm_ff1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff3.vhd - Info: Found design unit 1: lpm_ff3-SYN - Info: Found entity 1: lpm_ff3 -Info: Found 1 design units, including 1 entities, in source file video/video_mod_mux_clutctr.tdf - Info: Found entity 1: VIDEO_MOD_MUX_CLUTCTR -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff2.vhd - Info: Found design unit 1: lpm_ff2-SYN - Info: Found entity 1: lpm_ff2 -Info: Found 2 design units, including 1 entities, in source file video/lpm_fifo_dc0.vhd - Info: Found design unit 1: lpm_fifo_dc0-SYN - Info: Found entity 1: lpm_fifo_dc0 -Info: Found 1 design units, including 1 entities, in source file video/video.bdf - Info: Found entity 1: Video -Info: Found 1 design units, including 1 entities, in source file firebee1.bdf - Info: Found entity 1: firebee1 -Info: Found 2 design units, including 1 entities, in source file altpll0.vhd - Info: Found design unit 1: altpll0-SYN - Info: Found entity 1: altpll0 -Info: Found 2 design units, including 1 entities, in source file lpm_counter0.vhd - Info: Found design unit 1: lpm_counter0-SYN - Info: Found entity 1: lpm_counter0 -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf.vhd - Info: Found design unit 1: FalconIO_SDCard_IDE_CF-FalconIO_SDCard_IDE_CF_architecture - Info: Found entity 1: FalconIO_SDCard_IDE_CF -Info: Found 2 design units, including 1 entities, in source file dsp/dsp.vhd - Info: Found design unit 1: DSP-DSP_architecture - Info: Found entity 1: DSP -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg0.vhd - Info: Found design unit 1: lpm_shiftreg0-SYN - Info: Found entity 1: lpm_shiftreg0 -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri1.vhd - Info: Found design unit 1: lpm_bustri1-SYN - Info: Found entity 1: lpm_bustri1 -Info: Found 2 design units, including 1 entities, in source file video/altdpram1.vhd - Info: Found design unit 1: altdpram1-SYN - Info: Found entity 1: altdpram1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri2.vhd - Info: Found design unit 1: lpm_bustri2-SYN - Info: Found entity 1: lpm_bustri2 -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri4.vhd - Info: Found design unit 1: lpm_bustri4-SYN - Info: Found entity 1: lpm_bustri4 -Info: Found 2 design units, including 1 entities, in source file video/lpm_constant0.vhd - Info: Found design unit 1: lpm_constant0-SYN - Info: Found entity 1: lpm_constant0 -Info: Found 2 design units, including 1 entities, in source file video/lpm_constant1.vhd - Info: Found design unit 1: lpm_constant1-SYN - Info: Found entity 1: lpm_constant1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux0.vhd - Info: Found design unit 1: lpm_mux0-SYN - Info: Found entity 1: lpm_mux0 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux1.vhd - Info: Found design unit 1: lpm_mux1-SYN - Info: Found entity 1: lpm_mux1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux2.vhd - Info: Found design unit 1: lpm_mux2-SYN - Info: Found entity 1: lpm_mux2 -Info: Found 2 design units, including 1 entities, in source file video/lpm_constant2.vhd - Info: Found design unit 1: lpm_constant2-SYN - Info: Found entity 1: lpm_constant2 -Info: Found 2 design units, including 1 entities, in source file video/altdpram2.vhd - Info: Found design unit 1: altdpram2-SYN - Info: Found entity 1: altdpram2 -Info: Found 2 design units, including 1 entities, in source file video/lpm_bustri6.vhd - Info: Found design unit 1: lpm_bustri6-SYN - Info: Found entity 1: lpm_bustri6 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux3.vhd - Info: Found design unit 1: lpm_mux3-SYN - Info: Found entity 1: lpm_mux3 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux4.vhd - Info: Found design unit 1: lpm_mux4-SYN - Info: Found entity 1: lpm_mux4 -Info: Found 2 design units, including 1 entities, in source file video/lpm_constant3.vhd - Info: Found design unit 1: lpm_constant3-SYN - Info: Found entity 1: lpm_constant3 -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg1.vhd - Info: Found design unit 1: lpm_shiftreg1-SYN - Info: Found entity 1: lpm_shiftreg1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_latch1.vhd - Info: Found design unit 1: lpm_latch1-SYN - Info: Found entity 1: lpm_latch1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_constant4.vhd - Info: Found design unit 1: lpm_constant4-SYN - Info: Found entity 1: lpm_constant4 -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg2.vhd - Info: Found design unit 1: lpm_shiftreg2-SYN - Info: Found entity 1: lpm_shiftreg2 -Info: Found 2 design units, including 1 entities, in source file video/lpm_compare1.vhd - Info: Found design unit 1: lpm_compare1-SYN - Info: Found entity 1: lpm_compare1 -Info: Found 1 design units, including 1 entities, in source file interrupt_handler/interrupt_handler.tdf - Info: Found entity 1: interrupt_handler -Info: Found 2 design units, including 1 entities, in source file lpm_bustri_long.vhd - Info: Found design unit 1: lpm_bustri_long-SYN - Info: Found entity 1: lpm_bustri_LONG -Info: Found 2 design units, including 1 entities, in source file lpm_bustri_byt.vhd - Info: Found design unit 1: lpm_bustri_byt-SYN - Info: Found entity 1: lpm_bustri_BYT -Info: Found 2 design units, including 1 entities, in source file lpm_bustri_word.vhd - Info: Found design unit 1: lpm_bustri_word-SYN - Info: Found entity 1: lpm_bustri_WORD -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff4.vhd - Info: Found design unit 1: lpm_ff4-SYN - Info: Found entity 1: lpm_ff4 -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff5.vhd - Info: Found design unit 1: lpm_ff5-SYN - Info: Found entity 1: lpm_ff5 -Info: Found 2 design units, including 1 entities, in source file video/lpm_ff6.vhd - Info: Found design unit 1: lpm_ff6-SYN - Info: Found entity 1: lpm_ff6 -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg3.vhd - Info: Found design unit 1: lpm_shiftreg3-SYN - Info: Found entity 1: lpm_shiftreg3 -Info: Found 2 design units, including 1 entities, in source file video/altddio_bidir0.vhd - Info: Found design unit 1: altddio_bidir0-SYN - Info: Found entity 1: altddio_bidir0 -Info: Found 2 design units, including 1 entities, in source file video/altddio_out0.vhd - Info: Found design unit 1: altddio_out0-SYN - Info: Found entity 1: altddio_out0 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux5.vhd - Info: Found design unit 1: lpm_mux5-SYN - Info: Found entity 1: lpm_mux5 -Info: Found 2 design units, including 1 entities, in source file video/blitter/blitter.vhd - Info: Found design unit 1: BLITTER-BLITTER_architecture - Info: Found entity 1: BLITTER -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg5.vhd - Info: Found design unit 1: lpm_shiftreg5-SYN - Info: Found entity 1: lpm_shiftreg5 -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg6.vhd - Info: Found design unit 1: lpm_shiftreg6-SYN - Info: Found entity 1: lpm_shiftreg6 -Info: Found 2 design units, including 1 entities, in source file video/lpm_shiftreg4.vhd - Info: Found design unit 1: lpm_shiftreg4-SYN - Info: Found entity 1: lpm_shiftreg4 -Info: Found 2 design units, including 1 entities, in source file video/altddio_out1.vhd - Info: Found design unit 1: altddio_out1-SYN - Info: Found entity 1: altddio_out1 -Info: Found 2 design units, including 1 entities, in source file video/altddio_out2.vhd - Info: Found design unit 1: altddio_out2-SYN - Info: Found entity 1: altddio_out2 -Info: Found 2 design units, including 1 entities, in source file altddio_out3.vhd - Info: Found design unit 1: altddio_out3-SYN - Info: Found entity 1: altddio_out3 -Info: Found 2 design units, including 1 entities, in source file video/lpm_mux6.vhd - Info: Found design unit 1: lpm_mux6-SYN - Info: Found entity 1: lpm_mux6 -Info: Found 1 design units, including 0 entities, in source file falconio_sdcard_ide_cf/falconio_sdcard_ide_cf_pgk.vhd - Info: Found design unit 1: FalconIO_SDCard_IDE_CF_PKG -Info: Found 2 design units, including 1 entities, in source file falconio_sdcard_ide_cf/dcfifo1.vhd - Info: Found design unit 1: dcfifo1-SYN - Info: Found entity 1: dcfifo1 -Info: Found 2 design units, including 1 entities, in source file video/lpm_muxvdm.vhd - Info: Found design unit 1: lpm_muxvdm-SYN - Info: Found entity 1: lpm_muxVDM -Info: Elaborating entity "firebee1" for the top level hierarchy -Warning: Pin "TOUT0" not connected -Warning: Pin "nMASTER" not connected -Info: Elaborating entity "altpll1" for hierarchy "altpll1:inst" -Info: Elaborating entity "altpll" for hierarchy "altpll1:inst|altpll:altpll_component" -Info: Elaborated megafunction instantiation "altpll1:inst|altpll:altpll_component" -Info: Instantiated megafunction "altpll1:inst|altpll:altpll_component" with the following parameter: - Info: Parameter "bandwidth_type" = "AUTO" - Info: Parameter "clk0_divide_by" = "66" - Info: Parameter "clk0_duty_cycle" = "50" - Info: Parameter "clk0_multiply_by" = "1" - Info: Parameter "clk0_phase_shift" = "0" - Info: Parameter "clk1_divide_by" = "900" - Info: Parameter "clk1_duty_cycle" = "50" - Info: Parameter "clk1_multiply_by" = "67" - Info: Parameter "clk1_phase_shift" = "0" - Info: Parameter "clk2_divide_by" = "90" - Info: Parameter "clk2_duty_cycle" = "50" - Info: Parameter "clk2_multiply_by" = "67" - Info: Parameter "clk2_phase_shift" = "0" - Info: Parameter "compensate_clock" = "CLK0" - Info: Parameter "inclk0_input_frequency" = "30303" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altpll" - Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" - Info: Parameter "pll_type" = "AUTO" - Info: Parameter "port_activeclock" = "PORT_UNUSED" - Info: Parameter "port_areset" = "PORT_UNUSED" - Info: Parameter "port_clkbad0" = "PORT_UNUSED" - Info: Parameter "port_clkbad1" = "PORT_UNUSED" - Info: Parameter "port_clkloss" = "PORT_UNUSED" - Info: Parameter "port_clkswitch" = "PORT_UNUSED" - Info: Parameter "port_configupdate" = "PORT_UNUSED" - Info: Parameter "port_fbin" = "PORT_UNUSED" - Info: Parameter "port_inclk0" = "PORT_USED" - Info: Parameter "port_inclk1" = "PORT_UNUSED" - Info: Parameter "port_locked" = "PORT_USED" - Info: Parameter "port_pfdena" = "PORT_UNUSED" - Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" - Info: Parameter "port_phasedone" = "PORT_UNUSED" - Info: Parameter "port_phasestep" = "PORT_UNUSED" - Info: Parameter "port_phaseupdown" = "PORT_UNUSED" - Info: Parameter "port_pllena" = "PORT_UNUSED" - Info: Parameter "port_scanaclr" = "PORT_UNUSED" - Info: Parameter "port_scanclk" = "PORT_UNUSED" - Info: Parameter "port_scanclkena" = "PORT_UNUSED" - Info: Parameter "port_scandata" = "PORT_UNUSED" - Info: Parameter "port_scandataout" = "PORT_UNUSED" - Info: Parameter "port_scandone" = "PORT_UNUSED" - Info: Parameter "port_scanread" = "PORT_UNUSED" - Info: Parameter "port_scanwrite" = "PORT_UNUSED" - Info: Parameter "port_clk0" = "PORT_USED" - Info: Parameter "port_clk1" = "PORT_USED" - Info: Parameter "port_clk2" = "PORT_USED" - Info: Parameter "port_clk3" = "PORT_UNUSED" - Info: Parameter "port_clk4" = "PORT_UNUSED" - Info: Parameter "port_clk5" = "PORT_UNUSED" - Info: Parameter "port_clkena0" = "PORT_UNUSED" - Info: Parameter "port_clkena1" = "PORT_UNUSED" - Info: Parameter "port_clkena2" = "PORT_UNUSED" - Info: Parameter "port_clkena3" = "PORT_UNUSED" - Info: Parameter "port_clkena4" = "PORT_UNUSED" - Info: Parameter "port_clkena5" = "PORT_UNUSED" - Info: Parameter "port_extclk0" = "PORT_UNUSED" - Info: Parameter "port_extclk1" = "PORT_UNUSED" - Info: Parameter "port_extclk2" = "PORT_UNUSED" - Info: Parameter "port_extclk3" = "PORT_UNUSED" - Info: Parameter "self_reset_on_loss_lock" = "OFF" - Info: Parameter "width_clock" = "5" -Info: Found 1 design units, including 1 entities, in source file db/altpll_pul2.tdf - Info: Found entity 1: altpll_pul2 -Info: Elaborating entity "altpll_pul2" for hierarchy "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated" -Info: Elaborating entity "FalconIO_SDCard_IDE_CF" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden" -Warning (10036): Verilog HDL or VHDL warning at FalconIO_SDCard_IDE_CF.vhd(244): object "SCSI_CSn" assigned a value but never read -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(303): signal "nIDE_RD" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(304): signal "nIDE_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(313): signal "IDE_CF_CS" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(314): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(315): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(324): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(325): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(335): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Warning (10492): VHDL Process Statement warning at FalconIO_SDCard_IDE_CF.vhd(336): signal "nFB_WR" is read inside the Process Statement but isn't in the Process Statement's sensitivity list -Critical Warning (10920): VHDL Incomplete Partial Association warning at FalconIO_SDCard_IDE_CF.vhd(928): port or argument "IO_A_OUT" has 1/8 unassociated elements -Info: Elaborating entity "dcfifo0" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF" -Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" -Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" -Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_numwords" = "1024" - Info: Parameter "lpm_showahead" = "OFF" - Info: Parameter "lpm_type" = "dcfifo" - Info: Parameter "lpm_width" = "8" - Info: Parameter "lpm_widthu" = "10" - Info: Parameter "lpm_widthu_r" = "8" - Info: Parameter "lpm_width_r" = "32" - Info: Parameter "overflow_checking" = "ON" - Info: Parameter "rdsync_delaypipe" = "5" - Info: Parameter "underflow_checking" = "ON" - Info: Parameter "use_eab" = "ON" - Info: Parameter "write_aclr_synch" = "OFF" - Info: Parameter "wrsync_delaypipe" = "5" -Info: Found 1 design units, including 1 entities, in source file db/dcfifo_0hh1.tdf - Info: Found entity 1: dcfifo_0hh1 -Info: Elaborating entity "dcfifo_0hh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated" -Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_lfb.tdf - Info: Found entity 1: a_gray2bin_lfb -Info: Elaborating entity "a_gray2bin_lfb" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_gray2bin_lfb:wrptr_g_gray2bin" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_k47.tdf - Info: Found entity 1: a_graycounter_k47 -Info: Elaborating entity "a_graycounter_k47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_fic.tdf - Info: Found entity 1: a_graycounter_fic -Info: Elaborating entity "a_graycounter_fic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_bi31.tdf - Info: Found entity 1: altsyncram_bi31 -Info: Elaborating entity "altsyncram_bi31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram" -Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_ikd.tdf - Info: Found entity 1: alt_synch_pipe_ikd -Info: Elaborating entity "alt_synch_pipe_ikd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_hd9.tdf - Info: Found entity 1: dffpipe_hd9 -Info: Elaborating entity "dffpipe_hd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_ikd:rs_dgwp|dffpipe_hd9:dffpipe12" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_gd9.tdf - Info: Found entity 1: dffpipe_gd9 -Info: Elaborating entity "dffpipe_gd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_pe9.tdf - Info: Found entity 1: dffpipe_pe9 -Info: Elaborating entity "dffpipe_pe9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp" -Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_jkd.tdf - Info: Found entity 1: alt_synch_pipe_jkd -Info: Elaborating entity "alt_synch_pipe_jkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_id9.tdf - Info: Found entity 1: dffpipe_id9 -Info: Elaborating entity "dffpipe_id9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17" -Info: Found 1 design units, including 1 entities, in source file db/cmpr_256.tdf - Info: Found entity 1: cmpr_256 -Info: Elaborating entity "cmpr_256" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_256:rdempty_eq_comp1_lsb" -Info: Found 1 design units, including 1 entities, in source file db/cmpr_156.tdf - Info: Found entity 1: cmpr_156 -Info: Elaborating entity "cmpr_156" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cmpr_156:rdempty_eq_comp1_msb" -Info: Found 1 design units, including 1 entities, in source file db/cntr_t2e.tdf - Info: Found entity 1: cntr_t2e -Info: Elaborating entity "cntr_t2e" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b" -Info: Found 1 design units, including 1 entities, in source file db/mux_a18.tdf - Info: Found entity 1: mux_a18 -Info: Elaborating entity "mux_a18" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|mux_a18:rdemp_eq_comp_lsb_mux" -Info: Elaborating entity "dcfifo1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF" -Info: Elaborating entity "dcfifo_mixed_widths" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" -Info: Elaborated megafunction instantiation "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" -Info: Instantiated megafunction "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component" with the following parameter: - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_numwords" = "256" - Info: Parameter "lpm_showahead" = "OFF" - Info: Parameter "lpm_type" = "dcfifo" - Info: Parameter "lpm_width" = "32" - Info: Parameter "lpm_widthu" = "8" - Info: Parameter "lpm_widthu_r" = "10" - Info: Parameter "lpm_width_r" = "8" - Info: Parameter "overflow_checking" = "ON" - Info: Parameter "rdsync_delaypipe" = "5" - Info: Parameter "underflow_checking" = "ON" - Info: Parameter "use_eab" = "ON" - Info: Parameter "write_aclr_synch" = "OFF" - Info: Parameter "wrsync_delaypipe" = "5" -Info: Found 1 design units, including 1 entities, in source file db/dcfifo_3fh1.tdf - Info: Found entity 1: dcfifo_3fh1 -Info: Elaborating entity "dcfifo_3fh1" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_j47.tdf - Info: Found entity 1: a_graycounter_j47 -Info: Elaborating entity "a_graycounter_j47" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_gic.tdf - Info: Found entity 1: a_graycounter_gic -Info: Elaborating entity "a_graycounter_gic" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_gic:wrptr_g1p" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ci31.tdf - Info: Found entity 1: altsyncram_ci31 -Info: Elaborating entity "altsyncram_ci31" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram" -Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_kkd.tdf - Info: Found entity 1: alt_synch_pipe_kkd -Info: Elaborating entity "alt_synch_pipe_kkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_jd9.tdf - Info: Found entity 1: dffpipe_jd9 -Info: Elaborating entity "dffpipe_jd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12" -Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_lkd.tdf - Info: Found entity 1: alt_synch_pipe_lkd -Info: Elaborating entity "alt_synch_pipe_lkd" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_kd9.tdf - Info: Found entity 1: dffpipe_kd9 -Info: Elaborating entity "dffpipe_kd9" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_lkd:ws_dgrp|dffpipe_kd9:dffpipe15" -Info: Elaborating entity "WF1772IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC" -Info: Elaborating entity "WF1772IP_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL" -Info: Elaborating entity "WF1772IP_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS" -Info: Elaborating entity "WF1772IP_DIGITAL_PLL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL" -Info: Elaborating entity "WF1772IP_AM_DETECTOR" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR" -Info: Elaborating entity "WF1772IP_CRC_LOGIC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC" -Info: Elaborating entity "WF1772IP_TRANSCEIVER" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER" -Info: Elaborating entity "WF5380_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI" -Info: Elaborating entity "WF5380_REGISTERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS" -Info: Elaborating entity "WF5380_CONTROL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL" -Info: Elaborating entity "WF6850IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD" -Info: Elaborating entity "WF6850IP_CTRL_STATUS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS" -Info: Elaborating entity "WF6850IP_RECEIVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_RECEIVE:I_UART_RECEIVE" -Info: Elaborating entity "WF6850IP_TRANSMIT" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT" -Info: Elaborating entity "WF68901IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP" -Info: Elaborating entity "WF68901IP_USART_TOP" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART" -Info: Elaborating entity "WF68901IP_USART_CTRL" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_CTRL:I_USART_CTRL" -Info: Elaborating entity "WF68901IP_USART_RX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_RX:I_USART_RECEIVE" -Info: Elaborating entity "WF68901IP_USART_TX" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT" -Info: Elaborating entity "WF68901IP_INTERRUPTS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS" -Info: Elaborating entity "WF68901IP_GPIO" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_GPIO:I_GPIO" -Info: Elaborating entity "WF68901IP_TIMERS" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS" -Info: Elaborating entity "WF2149IP_TOP_SOC" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND" -Info: Elaborating entity "WF2149IP_WAVE" for hierarchy "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE" -Info: Elaborating entity "altpll3" for hierarchy "altpll3:inst13" -Info: Elaborating entity "altpll" for hierarchy "altpll3:inst13|altpll:altpll_component" -Info: Elaborated megafunction instantiation "altpll3:inst13|altpll:altpll_component" -Info: Instantiated megafunction "altpll3:inst13|altpll:altpll_component" with the following parameter: - Info: Parameter "bandwidth_type" = "AUTO" - Info: Parameter "clk0_divide_by" = "33" - Info: Parameter "clk0_duty_cycle" = "50" - Info: Parameter "clk0_multiply_by" = "2" - Info: Parameter "clk0_phase_shift" = "0" - Info: Parameter "clk1_divide_by" = "33" - Info: Parameter "clk1_duty_cycle" = "50" - Info: Parameter "clk1_multiply_by" = "16" - Info: Parameter "clk1_phase_shift" = "0" - Info: Parameter "clk2_divide_by" = "33" - Info: Parameter "clk2_duty_cycle" = "50" - Info: Parameter "clk2_multiply_by" = "25" - Info: Parameter "clk2_phase_shift" = "0" - Info: Parameter "clk3_divide_by" = "11" - Info: Parameter "clk3_duty_cycle" = "50" - Info: Parameter "clk3_multiply_by" = "16" - Info: Parameter "clk3_phase_shift" = "0" - Info: Parameter "compensate_clock" = "CLK1" - Info: Parameter "inclk0_input_frequency" = "30303" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altpll" - Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" - Info: Parameter "pll_type" = "AUTO" - Info: Parameter "port_activeclock" = "PORT_UNUSED" - Info: Parameter "port_areset" = "PORT_UNUSED" - Info: Parameter "port_clkbad0" = "PORT_UNUSED" - Info: Parameter "port_clkbad1" = "PORT_UNUSED" - Info: Parameter "port_clkloss" = "PORT_UNUSED" - Info: Parameter "port_clkswitch" = "PORT_UNUSED" - Info: Parameter "port_configupdate" = "PORT_UNUSED" - Info: Parameter "port_fbin" = "PORT_UNUSED" - Info: Parameter "port_inclk0" = "PORT_USED" - Info: Parameter "port_inclk1" = "PORT_UNUSED" - Info: Parameter "port_locked" = "PORT_UNUSED" - Info: Parameter "port_pfdena" = "PORT_UNUSED" - Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" - Info: Parameter "port_phasedone" = "PORT_UNUSED" - Info: Parameter "port_phasestep" = "PORT_UNUSED" - Info: Parameter "port_phaseupdown" = "PORT_UNUSED" - Info: Parameter "port_pllena" = "PORT_UNUSED" - Info: Parameter "port_scanaclr" = "PORT_UNUSED" - Info: Parameter "port_scanclk" = "PORT_UNUSED" - Info: Parameter "port_scanclkena" = "PORT_UNUSED" - Info: Parameter "port_scandata" = "PORT_UNUSED" - Info: Parameter "port_scandataout" = "PORT_UNUSED" - Info: Parameter "port_scandone" = "PORT_UNUSED" - Info: Parameter "port_scanread" = "PORT_UNUSED" - Info: Parameter "port_scanwrite" = "PORT_UNUSED" - Info: Parameter "port_clk0" = "PORT_USED" - Info: Parameter "port_clk1" = "PORT_USED" - Info: Parameter "port_clk2" = "PORT_USED" - Info: Parameter "port_clk3" = "PORT_USED" - Info: Parameter "port_clk4" = "PORT_UNUSED" - Info: Parameter "port_clk5" = "PORT_UNUSED" - Info: Parameter "port_clkena0" = "PORT_UNUSED" - Info: Parameter "port_clkena1" = "PORT_UNUSED" - Info: Parameter "port_clkena2" = "PORT_UNUSED" - Info: Parameter "port_clkena3" = "PORT_UNUSED" - Info: Parameter "port_clkena4" = "PORT_UNUSED" - Info: Parameter "port_clkena5" = "PORT_UNUSED" - Info: Parameter "port_extclk0" = "PORT_UNUSED" - Info: Parameter "port_extclk1" = "PORT_UNUSED" - Info: Parameter "port_extclk2" = "PORT_UNUSED" - Info: Parameter "port_extclk3" = "PORT_UNUSED" - Info: Parameter "width_clock" = "5" -Info: Found 1 design units, including 1 entities, in source file db/altpll_41p2.tdf - Info: Found entity 1: altpll_41p2 -Info: Elaborating entity "altpll_41p2" for hierarchy "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated" -Info: Elaborating entity "Video" for hierarchy "Video:Fredi_Aschwanden" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ADR[31..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "MAIN_CLK" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS1" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS2" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_CS3" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_WR" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE0" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_SIZE1" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nRSTO" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nFB_OE" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_ALE" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDRCLK[3..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "DDR_SYNC_66M" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK33M" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK25M" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLK_VIDEO" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_D[8..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_BUSY" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VG[7..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VB[7..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR[7..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nBLANK" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VA[12..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVWE" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCAS" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVRAS" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nVCS" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDM[3..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nPD_VGA" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VCKE" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VSYNC" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "HSYNC" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "nSYNC" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_TA" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "PIXEL_CLK" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "BA[1..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VIDEO_RECONFIG" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_WR" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VR_RD" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VDQS[3..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "FB_AD[31..0]" -Warning: INPUTC, OUTPUTC and BIDIRC pins not supported for pin "VD[31..0]" -Info: Elaborating entity "VIDEO_MOD_MUX_CLUTCTR" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR" -Warning: Variable or input pin "nRSTO" is defined but never used -Warning: Variable or input pin "nFB_CS3" is defined but never used -Warning: Variable or input pin "nFB_BURST" is defined but never used -Info: Elaborating entity "lpm_bustri_WORD" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000" -Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component" with the following parameter: - Info: Parameter "lpm_type" = "LPM_BUSTRI" - Info: Parameter "lpm_width" = "16" -Info: Elaborating entity "BLITTER" for hierarchy "Video:Fredi_Aschwanden|BLITTER:BLITTER" -Info: Elaborating entity "lpm_shiftreg6" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89" -Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg6:inst89|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: - Info: Parameter "lpm_direction" = "RIGHT" - Info: Parameter "lpm_type" = "LPM_SHIFTREG" - Info: Parameter "lpm_width" = "5" -Info: Elaborating entity "DDR_CTR" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR" -Warning: Variable or input pin "nFB_CS2" is defined but never used -Warning: Variable or input pin "nFB_CS3" is defined but never used -Warning: Variable or input pin "nRSTO" is defined but never used -Info: Elaborating entity "lpm_bustri_BYT" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002" -Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|lpm_bustri_BYT:$00002|lpm_bustri:lpm_bustri_component" with the following parameter: - Info: Parameter "lpm_type" = "LPM_BUSTRI" - Info: Parameter "lpm_width" = "8" -Info: Elaborating entity "lpm_fifo_dc0" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst" -Info: Elaborating entity "dcfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component" with the following parameter: - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_numwords" = "512" - Info: Parameter "lpm_showahead" = "OFF" - Info: Parameter "lpm_type" = "dcfifo" - Info: Parameter "lpm_width" = "128" - Info: Parameter "lpm_widthu" = "9" - Info: Parameter "overflow_checking" = "OFF" - Info: Parameter "rdsync_delaypipe" = "6" - Info: Parameter "underflow_checking" = "OFF" - Info: Parameter "use_eab" = "ON" - Info: Parameter "write_aclr_synch" = "ON" - Info: Parameter "wrsync_delaypipe" = "6" -Info: Found 1 design units, including 1 entities, in source file db/dcfifo_8fi1.tdf - Info: Found entity 1: dcfifo_8fi1 -Info: Elaborating entity "dcfifo_8fi1" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated" -Info: Found 1 design units, including 1 entities, in source file db/a_gray2bin_tgb.tdf - Info: Found entity 1: a_gray2bin_tgb -Info: Elaborating entity "a_gray2bin_tgb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_gray2bin_tgb:wrptr_g_gray2bin" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_s57.tdf - Info: Found entity 1: a_graycounter_s57 -Info: Elaborating entity "a_graycounter_s57" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_ojc.tdf - Info: Found entity 1: a_graycounter_ojc -Info: Elaborating entity "a_graycounter_ojc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_ojc:wrptr_g1p" -Info: Found 1 design units, including 1 entities, in source file db/a_graycounter_njc.tdf - Info: Found entity 1: a_graycounter_njc -Info: Elaborating entity "a_graycounter_njc" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tl31.tdf - Info: Found entity 1: altsyncram_tl31 -Info: Elaborating entity "altsyncram_tl31" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram" -Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_rld.tdf - Info: Found entity 1: alt_synch_pipe_rld -Info: Elaborating entity "alt_synch_pipe_rld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_qe9.tdf - Info: Found entity 1: dffpipe_qe9 -Info: Elaborating entity "dffpipe_qe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_rld:rs_dgwp|dffpipe_qe9:dffpipe15" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_9d9.tdf - Info: Found entity 1: dffpipe_9d9 -Info: Elaborating entity "dffpipe_9d9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_oe9.tdf - Info: Found entity 1: dffpipe_oe9 -Info: Elaborating entity "dffpipe_oe9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp" -Info: Found 1 design units, including 1 entities, in source file db/alt_synch_pipe_sld.tdf - Info: Found entity 1: alt_synch_pipe_sld -Info: Elaborating entity "alt_synch_pipe_sld" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp" -Info: Found 1 design units, including 1 entities, in source file db/dffpipe_re9.tdf - Info: Found entity 1: dffpipe_re9 -Info: Elaborating entity "dffpipe_re9" for hierarchy "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22" -Info: Elaborating entity "lpm_shiftreg4" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26" -Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: - Info: Parameter "lpm_direction" = "RIGHT" - Info: Parameter "lpm_type" = "LPM_SHIFTREG" - Info: Parameter "lpm_width" = "5" -Info: Elaborating entity "lpm_muxVDM" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "128" - Info: Parameter "LPM_SIZE" = "16" - Info: Parameter "LPM_WIDTHS" = "4" - Info: Parameter "LPM_PIPELINE" = "0" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_bbe.tdf - Info: Found entity 1: mux_bbe -Info: Elaborating entity "mux_bbe" for hierarchy "Video:Fredi_Aschwanden|lpm_muxVDM:inst100|LPM_MUX:lpm_mux_component|mux_bbe:auto_generated" -Info: Elaborating entity "lpm_ff6" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94" -Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component" with the following parameter: - Info: Parameter "lpm_fftype" = "DFF" - Info: Parameter "lpm_type" = "LPM_FF" - Info: Parameter "lpm_width" = "128" -Info: Elaborating entity "lpm_ff1" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4" -Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component" with the following parameter: - Info: Parameter "lpm_fftype" = "DFF" - Info: Parameter "lpm_type" = "LPM_FF" - Info: Parameter "lpm_width" = "32" -Info: Elaborating entity "altddio_bidir0" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1" -Info: Elaborating entity "altddio_bidir" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component" with the following parameter: - Info: Parameter "extend_oe_disable" = "UNUSED" - Info: Parameter "implement_input_in_lcell" = "ON" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "invert_output" = "OFF" - Info: Parameter "lpm_type" = "altddio_bidir" - Info: Parameter "oe_reg" = "UNUSED" - Info: Parameter "power_up_high" = "OFF" - Info: Parameter "width" = "32" -Info: Found 1 design units, including 1 entities, in source file db/ddio_bidir_3jl.tdf - Info: Found entity 1: ddio_bidir_3jl -Info: Elaborating entity "ddio_bidir_3jl" for hierarchy "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated" -Info: Elaborating entity "lpm_mux5" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "64" - Info: Parameter "LPM_SIZE" = "4" - Info: Parameter "LPM_WIDTHS" = "2" - Info: Parameter "LPM_PIPELINE" = "0" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_58e.tdf - Info: Found entity 1: mux_58e -Info: Elaborating entity "mux_58e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux5:inst22|LPM_MUX:lpm_mux_component|mux_58e:auto_generated" -Info: Elaborating entity "lpm_ff0" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14" -Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component" with the following parameter: - Info: Parameter "lpm_fftype" = "DFF" - Info: Parameter "lpm_type" = "LPM_FF" - Info: Parameter "lpm_width" = "32" -Info: Elaborating entity "lpm_bustri_LONG" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108" -Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri_LONG:inst108|lpm_bustri:lpm_bustri_component" with the following parameter: - Info: Parameter "lpm_type" = "LPM_BUSTRI" - Info: Parameter "lpm_width" = "32" -Info: Elaborating entity "lpm_latch0" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27" -Info: Elaborating entity "lpm_latch" for hierarchy "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component" with the following parameter: - Info: Parameter "lpm_type" = "LPM_LATCH" - Info: Parameter "lpm_width" = "32" -Info: Elaborating entity "lpm_bustri3" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66" -Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri3:inst66|lpm_bustri:lpm_bustri_component" with the following parameter: - Info: Parameter "lpm_type" = "LPM_BUSTRI" - Info: Parameter "lpm_width" = "6" -Info: Elaborating entity "altdpram1" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED" -Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component" with the following parameter: - Info: Parameter "address_reg_b" = "CLOCK1" - Info: Parameter "clock_enable_input_a" = "BYPASS" - Info: Parameter "clock_enable_input_b" = "BYPASS" - Info: Parameter "clock_enable_output_a" = "BYPASS" - Info: Parameter "clock_enable_output_b" = "BYPASS" - Info: Parameter "indata_reg_b" = "CLOCK1" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altsyncram" - Info: Parameter "numwords_a" = "256" - Info: Parameter "numwords_b" = "256" - Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" - Info: Parameter "outdata_aclr_a" = "NONE" - Info: Parameter "outdata_aclr_b" = "NONE" - Info: Parameter "outdata_reg_a" = "CLOCK0" - Info: Parameter "outdata_reg_b" = "CLOCK1" - Info: Parameter "power_up_uninitialized" = "FALSE" - Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" - Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" - Info: Parameter "widthad_a" = "8" - Info: Parameter "widthad_b" = "8" - Info: Parameter "width_a" = "6" - Info: Parameter "width_b" = "6" - Info: Parameter "width_byteena_a" = "1" - Info: Parameter "width_byteena_b" = "1" - Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_lf92.tdf - Info: Found entity 1: altsyncram_lf92 -Info: Elaborating entity "altsyncram_lf92" for hierarchy "Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated" -Info: Elaborating entity "lpm_shiftreg0" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0" -Info: Elaborating entity "lpm_shiftreg" for hierarchy "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component" with the following parameter: - Info: Parameter "lpm_direction" = "LEFT" - Info: Parameter "lpm_type" = "LPM_SHIFTREG" - Info: Parameter "lpm_width" = "16" -Info: Elaborating entity "MUX41" for hierarchy "Video:Fredi_Aschwanden|MUX41:inst45" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|MUX41:inst45" -Info: Elaborating entity "lpm_muxDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "128" - Info: Parameter "LPM_SIZE" = "2" - Info: Parameter "LPM_WIDTHS" = "1" - Info: Parameter "LPM_PIPELINE" = "1" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_dcf.tdf - Info: Found entity 1: mux_dcf -Info: Elaborating entity "mux_dcf" for hierarchy "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|LPM_MUX:lpm_mux_component|mux_dcf:auto_generated" -Info: Elaborating entity "lpm_fifoDZ" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63" -Info: Elaborating entity "scfifo" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component" with the following parameter: - Info: Parameter "add_ram_output_register" = "OFF" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_numwords" = "128" - Info: Parameter "lpm_showahead" = "ON" - Info: Parameter "lpm_type" = "scfifo" - Info: Parameter "lpm_width" = "128" - Info: Parameter "lpm_widthu" = "7" - Info: Parameter "overflow_checking" = "OFF" - Info: Parameter "underflow_checking" = "OFF" - Info: Parameter "use_eab" = "ON" -Info: Found 1 design units, including 1 entities, in source file db/scfifo_lk21.tdf - Info: Found entity 1: scfifo_lk21 -Info: Elaborating entity "scfifo_lk21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated" -Info: Found 1 design units, including 1 entities, in source file db/a_dpfifo_oq21.tdf - Info: Found entity 1: a_dpfifo_oq21 -Info: Elaborating entity "a_dpfifo_oq21" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gj81.tdf - Info: Found entity 1: altsyncram_gj81 -Info: Elaborating entity "altsyncram_gj81" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram" -Info: Found 1 design units, including 1 entities, in source file db/cmpr_br8.tdf - Info: Found entity 1: cmpr_br8 -Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:almost_full_comparer" -Info: Elaborating entity "cmpr_br8" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cmpr_br8:three_comparison" -Info: Found 1 design units, including 1 entities, in source file db/cntr_omb.tdf - Info: Found entity 1: cntr_omb -Info: Elaborating entity "cntr_omb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb" -Info: Found 1 design units, including 1 entities, in source file db/cntr_5n7.tdf - Info: Found entity 1: cntr_5n7 -Info: Elaborating entity "cntr_5n7" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter" -Info: Found 1 design units, including 1 entities, in source file db/cntr_pmb.tdf - Info: Found entity 1: cntr_pmb -Info: Elaborating entity "cntr_pmb" for hierarchy "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr" -Info: Elaborating entity "lpm_bustri1" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51" -Info: Elaborating entity "lpm_bustri" for hierarchy "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_bustri1:inst51|lpm_bustri:lpm_bustri_component" with the following parameter: - Info: Parameter "lpm_type" = "LPM_BUSTRI" - Info: Parameter "lpm_width" = "3" -Info: Elaborating entity "altdpram0" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED" -Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component" with the following parameter: - Info: Parameter "address_reg_b" = "CLOCK1" - Info: Parameter "clock_enable_input_a" = "BYPASS" - Info: Parameter "clock_enable_input_b" = "BYPASS" - Info: Parameter "clock_enable_output_a" = "BYPASS" - Info: Parameter "clock_enable_output_b" = "BYPASS" - Info: Parameter "indata_reg_b" = "CLOCK1" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altsyncram" - Info: Parameter "numwords_a" = "16" - Info: Parameter "numwords_b" = "16" - Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" - Info: Parameter "outdata_aclr_a" = "NONE" - Info: Parameter "outdata_aclr_b" = "NONE" - Info: Parameter "outdata_reg_a" = "CLOCK0" - Info: Parameter "outdata_reg_b" = "CLOCK1" - Info: Parameter "power_up_uninitialized" = "FALSE" - Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" - Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" - Info: Parameter "widthad_a" = "4" - Info: Parameter "widthad_b" = "4" - Info: Parameter "width_a" = "3" - Info: Parameter "width_b" = "3" - Info: Parameter "width_byteena_a" = "1" - Info: Parameter "width_byteena_b" = "1" - Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rb92.tdf - Info: Found entity 1: altsyncram_rb92 -Info: Elaborating entity "altsyncram_rb92" for hierarchy "Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated" -Info: Elaborating entity "altdpram2" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55" -Info: Elaborating entity "altsyncram" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component" with the following parameter: - Info: Parameter "address_reg_b" = "CLOCK1" - Info: Parameter "clock_enable_input_a" = "BYPASS" - Info: Parameter "clock_enable_input_b" = "BYPASS" - Info: Parameter "clock_enable_output_a" = "BYPASS" - Info: Parameter "clock_enable_output_b" = "BYPASS" - Info: Parameter "indata_reg_b" = "CLOCK1" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altsyncram" - Info: Parameter "numwords_a" = "256" - Info: Parameter "numwords_b" = "256" - Info: Parameter "operation_mode" = "BIDIR_DUAL_PORT" - Info: Parameter "outdata_aclr_a" = "NONE" - Info: Parameter "outdata_aclr_b" = "NONE" - Info: Parameter "outdata_reg_a" = "CLOCK0" - Info: Parameter "outdata_reg_b" = "CLOCK1" - Info: Parameter "power_up_uninitialized" = "FALSE" - Info: Parameter "read_during_write_mode_port_a" = "OLD_DATA" - Info: Parameter "read_during_write_mode_port_b" = "OLD_DATA" - Info: Parameter "widthad_a" = "8" - Info: Parameter "widthad_b" = "8" - Info: Parameter "width_a" = "8" - Info: Parameter "width_b" = "8" - Info: Parameter "width_byteena_a" = "1" - Info: Parameter "width_byteena_b" = "1" - Info: Parameter "wrcontrol_wraddress_reg_b" = "CLOCK1" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_pf92.tdf - Info: Found entity 1: altsyncram_pf92 -Info: Elaborating entity "altsyncram_pf92" for hierarchy "Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated" -Info: Elaborating entity "lpm_mux3" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "1" - Info: Parameter "LPM_SIZE" = "2" - Info: Parameter "LPM_WIDTHS" = "1" - Info: Parameter "LPM_PIPELINE" = "0" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_96e.tdf - Info: Found entity 1: mux_96e -Info: Elaborating entity "mux_96e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux3:inst102|LPM_MUX:lpm_mux_component|mux_96e:auto_generated" -Info: Elaborating entity "lpm_ff5" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11" -Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff5:inst11|lpm_ff:lpm_ff_component" with the following parameter: - Info: Parameter "lpm_fftype" = "DFF" - Info: Parameter "lpm_type" = "LPM_FF" - Info: Parameter "lpm_width" = "8" -Info: Elaborating entity "lpm_mux2" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "8" - Info: Parameter "LPM_SIZE" = "16" - Info: Parameter "LPM_WIDTHS" = "4" - Info: Parameter "LPM_PIPELINE" = "2" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_mpe.tdf - Info: Found entity 1: mux_mpe -Info: Elaborating entity "mux_mpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux2:inst25|LPM_MUX:lpm_mux_component|mux_mpe:auto_generated" -Info: Elaborating entity "lpm_mux4" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "7" - Info: Parameter "LPM_SIZE" = "2" - Info: Parameter "LPM_WIDTHS" = "1" - Info: Parameter "LPM_PIPELINE" = "0" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_f6e.tdf - Info: Found entity 1: mux_f6e -Info: Elaborating entity "mux_f6e" for hierarchy "Video:Fredi_Aschwanden|lpm_mux4:inst81|LPM_MUX:lpm_mux_component|mux_f6e:auto_generated" -Info: Elaborating entity "lpm_constant3" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82" -Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant3:inst82|lpm_constant:lpm_constant_component" with the following parameter: - Info: Parameter "lpm_cvalue" = "0" - Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" - Info: Parameter "lpm_type" = "LPM_CONSTANT" - Info: Parameter "lpm_width" = "7" -Info: Elaborating entity "altddio_out2" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5" -Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component" with the following parameter: - Info: Parameter "extend_oe_disable" = "UNUSED" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "invert_output" = "OFF" - Info: Parameter "lpm_type" = "altddio_out" - Info: Parameter "oe_reg" = "UNUSED" - Info: Parameter "power_up_high" = "OFF" - Info: Parameter "width" = "24" -Info: Found 1 design units, including 1 entities, in source file db/ddio_out_o2f.tdf - Info: Found entity 1: ddio_out_o2f -Info: Elaborating entity "ddio_out_o2f" for hierarchy "Video:Fredi_Aschwanden|altddio_out2:inst5|altddio_out:altddio_out_component|ddio_out_o2f:auto_generated" -Info: Elaborating entity "lpm_mux6" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "24" - Info: Parameter "LPM_SIZE" = "8" - Info: Parameter "LPM_WIDTHS" = "3" - Info: Parameter "LPM_PIPELINE" = "2" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_kpe.tdf - Info: Found entity 1: mux_kpe -Info: Elaborating entity "mux_kpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux6:inst7|LPM_MUX:lpm_mux_component|mux_kpe:auto_generated" -Info: Elaborating entity "lpm_ff3" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49" -Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component" with the following parameter: - Info: Parameter "lpm_fftype" = "DFF" - Info: Parameter "lpm_type" = "LPM_FF" - Info: Parameter "lpm_width" = "24" -Info: Elaborating entity "lpm_constant0" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59" -Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant0:inst59|lpm_constant:lpm_constant_component" with the following parameter: - Info: Parameter "lpm_cvalue" = "0" - Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" - Info: Parameter "lpm_type" = "LPM_CONSTANT" - Info: Parameter "lpm_width" = "5" -Info: Elaborating entity "lpm_constant1" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77" -Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant1:inst77|lpm_constant:lpm_constant_component" with the following parameter: - Info: Parameter "lpm_cvalue" = "0" - Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" - Info: Parameter "lpm_type" = "LPM_CONSTANT" - Info: Parameter "lpm_width" = "2" -Info: Elaborating entity "lpm_ff4" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10" -Info: Elaborating entity "lpm_ff" for hierarchy "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component" with the following parameter: - Info: Parameter "lpm_fftype" = "DFF" - Info: Parameter "lpm_type" = "LPM_FF" - Info: Parameter "lpm_width" = "16" -Info: Elaborating entity "lpm_mux1" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" -Info: Assertion information: Value of LPM_PIPELINE parameter (4) should be lower -- use 1 for best performance/utilization -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "16" - Info: Parameter "LPM_SIZE" = "8" - Info: Parameter "LPM_WIDTHS" = "3" - Info: Parameter "LPM_PIPELINE" = "4" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Assertion information: Value of LPM_PIPELINE parameter 4 should be lower -- use 1 for best performance/utilization -Info: Found 1 design units, including 1 entities, in source file db/mux_npe.tdf - Info: Found entity 1: mux_npe -Info: Elaborating entity "mux_npe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux1:inst24|LPM_MUX:lpm_mux_component|mux_npe:auto_generated" -Info: Elaborating entity "lpm_constant2" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23" -Info: Elaborating entity "lpm_constant" for hierarchy "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_constant2:inst23|lpm_constant:lpm_constant_component" with the following parameter: - Info: Parameter "lpm_cvalue" = "0" - Info: Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO" - Info: Parameter "lpm_type" = "LPM_CONSTANT" - Info: Parameter "lpm_width" = "8" -Info: Elaborating entity "lpm_mux0" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21" -Info: Elaborating entity "LPM_MUX" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component" with the following parameter: - Info: Parameter "LPM_WIDTH" = "32" - Info: Parameter "LPM_SIZE" = "4" - Info: Parameter "LPM_WIDTHS" = "2" - Info: Parameter "LPM_PIPELINE" = "4" - Info: Parameter "LPM_TYPE" = "LPM_MUX" - Info: Parameter "LPM_HINT" = "UNUSED" -Info: Found 1 design units, including 1 entities, in source file db/mux_gpe.tdf - Info: Found entity 1: mux_gpe -Info: Elaborating entity "mux_gpe" for hierarchy "Video:Fredi_Aschwanden|lpm_mux0:inst21|LPM_MUX:lpm_mux_component|mux_gpe:auto_generated" -Info: Elaborating entity "altddio_out0" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2" -Info: Elaborating entity "altddio_out" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component" with the following parameter: - Info: Parameter "extend_oe_disable" = "UNUSED" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "invert_output" = "ON" - Info: Parameter "lpm_type" = "altddio_out" - Info: Parameter "oe_reg" = "UNUSED" - Info: Parameter "power_up_high" = "ON" - Info: Parameter "width" = "4" -Info: Found 1 design units, including 1 entities, in source file db/ddio_out_are.tdf - Info: Found entity 1: ddio_out_are -Info: Elaborating entity "ddio_out_are" for hierarchy "Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated" -Info: Elaborating entity "altpll2" for hierarchy "altpll2:inst12" -Info: Elaborating entity "altpll" for hierarchy "altpll2:inst12|altpll:altpll_component" -Info: Elaborated megafunction instantiation "altpll2:inst12|altpll:altpll_component" -Info: Instantiated megafunction "altpll2:inst12|altpll:altpll_component" with the following parameter: - Info: Parameter "bandwidth_type" = "AUTO" - Info: Parameter "clk0_divide_by" = "1" - Info: Parameter "clk0_duty_cycle" = "50" - Info: Parameter "clk0_multiply_by" = "4" - Info: Parameter "clk0_phase_shift" = "5051" - Info: Parameter "clk1_divide_by" = "1" - Info: Parameter "clk1_duty_cycle" = "50" - Info: Parameter "clk1_multiply_by" = "4" - Info: Parameter "clk1_phase_shift" = "0" - Info: Parameter "clk2_divide_by" = "1" - Info: Parameter "clk2_duty_cycle" = "50" - Info: Parameter "clk2_multiply_by" = "4" - Info: Parameter "clk2_phase_shift" = "3788" - Info: Parameter "clk3_divide_by" = "1" - Info: Parameter "clk3_duty_cycle" = "50" - Info: Parameter "clk3_multiply_by" = "4" - Info: Parameter "clk3_phase_shift" = "2210" - Info: Parameter "clk4_divide_by" = "1" - Info: Parameter "clk4_duty_cycle" = "50" - Info: Parameter "clk4_multiply_by" = "2" - Info: Parameter "clk4_phase_shift" = "11364" - Info: Parameter "compensate_clock" = "CLK0" - Info: Parameter "inclk0_input_frequency" = "30303" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altpll" - Info: Parameter "operation_mode" = "SOURCE_SYNCHRONOUS" - Info: Parameter "pll_type" = "AUTO" - Info: Parameter "port_activeclock" = "PORT_UNUSED" - Info: Parameter "port_areset" = "PORT_UNUSED" - Info: Parameter "port_clkbad0" = "PORT_UNUSED" - Info: Parameter "port_clkbad1" = "PORT_UNUSED" - Info: Parameter "port_clkloss" = "PORT_UNUSED" - Info: Parameter "port_clkswitch" = "PORT_UNUSED" - Info: Parameter "port_configupdate" = "PORT_UNUSED" - Info: Parameter "port_fbin" = "PORT_UNUSED" - Info: Parameter "port_inclk0" = "PORT_USED" - Info: Parameter "port_inclk1" = "PORT_UNUSED" - Info: Parameter "port_locked" = "PORT_UNUSED" - Info: Parameter "port_pfdena" = "PORT_UNUSED" - Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" - Info: Parameter "port_phasedone" = "PORT_UNUSED" - Info: Parameter "port_phasestep" = "PORT_UNUSED" - Info: Parameter "port_phaseupdown" = "PORT_UNUSED" - Info: Parameter "port_pllena" = "PORT_UNUSED" - Info: Parameter "port_scanaclr" = "PORT_UNUSED" - Info: Parameter "port_scanclk" = "PORT_UNUSED" - Info: Parameter "port_scanclkena" = "PORT_UNUSED" - Info: Parameter "port_scandata" = "PORT_UNUSED" - Info: Parameter "port_scandataout" = "PORT_UNUSED" - Info: Parameter "port_scandone" = "PORT_UNUSED" - Info: Parameter "port_scanread" = "PORT_UNUSED" - Info: Parameter "port_scanwrite" = "PORT_UNUSED" - Info: Parameter "port_clk0" = "PORT_USED" - Info: Parameter "port_clk1" = "PORT_USED" - Info: Parameter "port_clk2" = "PORT_USED" - Info: Parameter "port_clk3" = "PORT_USED" - Info: Parameter "port_clk4" = "PORT_USED" - Info: Parameter "port_clk5" = "PORT_UNUSED" - Info: Parameter "port_clkena0" = "PORT_UNUSED" - Info: Parameter "port_clkena1" = "PORT_UNUSED" - Info: Parameter "port_clkena2" = "PORT_UNUSED" - Info: Parameter "port_clkena3" = "PORT_UNUSED" - Info: Parameter "port_clkena4" = "PORT_UNUSED" - Info: Parameter "port_clkena5" = "PORT_UNUSED" - Info: Parameter "port_extclk0" = "PORT_UNUSED" - Info: Parameter "port_extclk1" = "PORT_UNUSED" - Info: Parameter "port_extclk2" = "PORT_UNUSED" - Info: Parameter "port_extclk3" = "PORT_UNUSED" - Info: Parameter "width_clock" = "5" -Info: Found 1 design units, including 1 entities, in source file db/altpll_isv2.tdf - Info: Found entity 1: altpll_isv2 -Info: Elaborating entity "altpll_isv2" for hierarchy "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated" -Warning: Using design file altpll4.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info: Found entity 1: altpll4 -Info: Elaborating entity "altpll4" for hierarchy "altpll4:inst22" -Info: Elaborating entity "altpll" for hierarchy "altpll4:inst22|altpll:altpll_component" -Info: Elaborated megafunction instantiation "altpll4:inst22|altpll:altpll_component" -Info: Instantiated megafunction "altpll4:inst22|altpll:altpll_component" with the following parameter: - Info: Parameter "bandwidth_type" = "AUTO" - Info: Parameter "clk0_divide_by" = "1" - Info: Parameter "clk0_duty_cycle" = "50" - Info: Parameter "clk0_multiply_by" = "2" - Info: Parameter "clk0_phase_shift" = "0" - Info: Parameter "compensate_clock" = "CLK0" - Info: Parameter "inclk0_input_frequency" = "20833" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "lpm_type" = "altpll" - Info: Parameter "operation_mode" = "NORMAL" - Info: Parameter "pll_type" = "AUTO" - Info: Parameter "port_activeclock" = "PORT_UNUSED" - Info: Parameter "port_areset" = "PORT_USED" - Info: Parameter "port_clk0" = "PORT_USED" - Info: Parameter "port_clk1" = "PORT_UNUSED" - Info: Parameter "port_clk2" = "PORT_UNUSED" - Info: Parameter "port_clk3" = "PORT_UNUSED" - Info: Parameter "port_clk4" = "PORT_UNUSED" - Info: Parameter "port_clk5" = "PORT_UNUSED" - Info: Parameter "port_clkbad0" = "PORT_UNUSED" - Info: Parameter "port_clkbad1" = "PORT_UNUSED" - Info: Parameter "port_clkena0" = "PORT_UNUSED" - Info: Parameter "port_clkena1" = "PORT_UNUSED" - Info: Parameter "port_clkena2" = "PORT_UNUSED" - Info: Parameter "port_clkena3" = "PORT_UNUSED" - Info: Parameter "port_clkena4" = "PORT_UNUSED" - Info: Parameter "port_clkena5" = "PORT_UNUSED" - Info: Parameter "port_clkloss" = "PORT_UNUSED" - Info: Parameter "port_clkswitch" = "PORT_UNUSED" - Info: Parameter "port_configupdate" = "PORT_USED" - Info: Parameter "port_extclk0" = "PORT_UNUSED" - Info: Parameter "port_extclk1" = "PORT_UNUSED" - Info: Parameter "port_extclk2" = "PORT_UNUSED" - Info: Parameter "port_extclk3" = "PORT_UNUSED" - Info: Parameter "port_fbin" = "PORT_UNUSED" - Info: Parameter "port_inclk0" = "PORT_USED" - Info: Parameter "port_inclk1" = "PORT_UNUSED" - Info: Parameter "port_locked" = "PORT_USED" - Info: Parameter "port_pfdena" = "PORT_UNUSED" - Info: Parameter "port_phasecounterselect" = "PORT_UNUSED" - Info: Parameter "port_phasedone" = "PORT_UNUSED" - Info: Parameter "port_phasestep" = "PORT_UNUSED" - Info: Parameter "port_phaseupdown" = "PORT_UNUSED" - Info: Parameter "port_pllena" = "PORT_UNUSED" - Info: Parameter "port_scanaclr" = "PORT_UNUSED" - Info: Parameter "port_scanclk" = "PORT_USED" - Info: Parameter "port_scanclkena" = "PORT_USED" - Info: Parameter "port_scandata" = "PORT_USED" - Info: Parameter "port_scandataout" = "PORT_USED" - Info: Parameter "port_scandone" = "PORT_USED" - Info: Parameter "port_scanread" = "PORT_UNUSED" - Info: Parameter "port_scanwrite" = "PORT_UNUSED" - Info: Parameter "scan_chain_mif_file" = "altpll4.mif" - Info: Parameter "self_reset_on_loss_lock" = "OFF" - Info: Parameter "width_clock" = "5" - Info: Parameter "width_phasecounterselect" = "4" -Info: Found 1 design units, including 1 entities, in source file db/altpll_c6j2.tdf - Info: Found entity 1: altpll_c6j2 -Info: Elaborating entity "altpll_c6j2" for hierarchy "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated" -Warning: Using design file altpll_reconfig1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info: Found entity 1: altpll_reconfig1 -Info: Elaborating entity "altpll_reconfig1" for hierarchy "altpll_reconfig1:inst7" -Warning: Using design file altpll_reconfig1_pllrcfg_t4q.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project - Info: Found entity 1: altpll_reconfig1_pllrcfg_t4q -Info: Elaborating entity "altpll_reconfig1_pllrcfg_t4q" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component" -Info: Elaborating entity "altsyncram" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4" with the following parameter: - Info: Parameter "OPERATION_MODE" = "SINGLE_PORT" - Info: Parameter "WIDTH_A" = "1" - Info: Parameter "WIDTHAD_A" = "8" - Info: Parameter "NUMWORDS_A" = "144" - Info: Parameter "WIDTH_BYTEENA_A" = "1" -Info: Found 1 design units, including 1 entities, in source file db/altsyncram_46r.tdf - Info: Found entity 1: altsyncram_46r -Info: Elaborating entity "altsyncram_46r" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated" -Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5" with the following parameter: - Info: Parameter "LPM_WIDTH" = "9" -Info: Found 1 design units, including 1 entities, in source file db/add_sub_hpa.tdf - Info: Found entity 1: add_sub_hpa -Info: Elaborating entity "add_sub_hpa" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub5|add_sub_hpa:auto_generated" -Info: Elaborating entity "lpm_add_sub" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6" with the following parameter: - Info: Parameter "LPM_WIDTH" = "8" -Info: Found 1 design units, including 1 entities, in source file db/add_sub_k8a.tdf - Info: Found entity 1: add_sub_k8a -Info: Elaborating entity "add_sub_k8a" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_add_sub:add_sub6|add_sub_k8a:auto_generated" -Info: Elaborating entity "lpm_compare" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7" with the following parameter: - Info: Parameter "LPM_WIDTH" = "8" -Info: Found 1 design units, including 1 entities, in source file db/cmpr_tnd.tdf - Info: Found entity 1: cmpr_tnd -Info: Elaborating entity "cmpr_tnd" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_compare:cmpr7|cmpr_tnd:auto_generated" -Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1" with the following parameter: - Info: Parameter "LPM_DIRECTION" = "DOWN" - Info: Parameter "lpm_modulus" = "144" - Info: Parameter "lpm_port_updown" = "PORT_UNUSED" - Info: Parameter "LPM_WIDTH" = "8" -Info: Found 1 design units, including 1 entities, in source file db/cntr_30l.tdf - Info: Found entity 1: cntr_30l -Info: Elaborating entity "cntr_30l" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr1|cntr_30l:auto_generated" -Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13" with the following parameter: - Info: Parameter "LPM_DIRECTION" = "DOWN" - Info: Parameter "lpm_port_updown" = "PORT_UNUSED" - Info: Parameter "LPM_WIDTH" = "6" -Info: Found 1 design units, including 1 entities, in source file db/cntr_qij.tdf - Info: Found entity 1: cntr_qij -Info: Elaborating entity "cntr_qij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr13|cntr_qij:auto_generated" -Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14" with the following parameter: - Info: Parameter "LPM_DIRECTION" = "DOWN" - Info: Parameter "lpm_port_updown" = "PORT_UNUSED" - Info: Parameter "LPM_WIDTH" = "5" -Info: Found 1 design units, including 1 entities, in source file db/cntr_pij.tdf - Info: Found entity 1: cntr_pij -Info: Elaborating entity "cntr_pij" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr14|cntr_pij:auto_generated" -Info: Elaborating entity "lpm_counter" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2" with the following parameter: - Info: Parameter "LPM_DIRECTION" = "UP" - Info: Parameter "lpm_port_updown" = "PORT_UNUSED" - Info: Parameter "LPM_WIDTH" = "8" -Info: Found 1 design units, including 1 entities, in source file db/cntr_9cj.tdf - Info: Found entity 1: cntr_9cj -Info: Elaborating entity "cntr_9cj" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_counter:cntr2|cntr_9cj:auto_generated" -Info: Elaborating entity "lpm_decode" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" -Info: Elaborated megafunction instantiation "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" -Info: Instantiated megafunction "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11" with the following parameter: - Info: Parameter "LPM_DECODES" = "5" - Info: Parameter "LPM_WIDTH" = "3" -Info: Found 1 design units, including 1 entities, in source file db/decode_2af.tdf - Info: Found entity 1: decode_2af -Info: Elaborating entity "decode_2af" for hierarchy "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|lpm_decode:decode11|decode_2af:auto_generated" -Info: Elaborating entity "DSP" for hierarchy "DSP:Mathias_Alles" -Info: Elaborating entity "interrupt_handler" for hierarchy "interrupt_handler:nobody" -Info: Elaborating entity "lpm_counter0" for hierarchy "lpm_counter0:inst18" -Info: Elaborating entity "lpm_counter" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component" -Info: Elaborated megafunction instantiation "lpm_counter0:inst18|lpm_counter:lpm_counter_component" -Info: Instantiated megafunction "lpm_counter0:inst18|lpm_counter:lpm_counter_component" with the following parameter: - Info: Parameter "lpm_direction" = "UP" - Info: Parameter "lpm_port_updown" = "PORT_UNUSED" - Info: Parameter "lpm_type" = "LPM_COUNTER" - Info: Parameter "lpm_width" = "18" -Info: Found 1 design units, including 1 entities, in source file db/cntr_mph.tdf - Info: Found entity 1: cntr_mph -Info: Elaborating entity "cntr_mph" for hierarchy "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated" -Info: Elaborating entity "altddio_out3" for hierarchy "altddio_out3:inst5" -Info: Elaborating entity "altddio_out" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component" -Info: Elaborated megafunction instantiation "altddio_out3:inst5|altddio_out:altddio_out_component" -Info: Instantiated megafunction "altddio_out3:inst5|altddio_out:altddio_out_component" with the following parameter: - Info: Parameter "extend_oe_disable" = "UNUSED" - Info: Parameter "intended_device_family" = "Cyclone III" - Info: Parameter "invert_output" = "OFF" - Info: Parameter "lpm_type" = "altddio_out" - Info: Parameter "oe_reg" = "UNUSED" - Info: Parameter "power_up_high" = "OFF" - Info: Parameter "width" = "1" -Info: Found 1 design units, including 1 entities, in source file db/ddio_out_31f.tdf - Info: Found entity 1: ddio_out_31f -Info: Elaborating entity "ddio_out_31f" for hierarchy "altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated" -Warning: Timing-Driven Synthesis is skipped because the Classic Timing Analyzer is turned on -Info: Inferred 3 megafunctions from design logic - Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_14" - Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_6" - Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|op_12" -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_14" with the following parameter: - Info: Parameter "LPM_WIDTHA" = "12" - Info: Parameter "LPM_WIDTHB" = "6" - Info: Parameter "LPM_WIDTHP" = "18" - Info: Parameter "LPM_WIDTHR" = "18" - Info: Parameter "LPM_WIDTHS" = "1" - Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" - Info: Parameter "INPUT_A_IS_CONSTANT" = "NO" - Info: Parameter "INPUT_B_IS_CONSTANT" = "NO" - Info: Parameter "MAXIMIZE_SPEED" = "5" -Info: Found 1 design units, including 1 entities, in source file db/mult_cat.tdf - Info: Found entity 1: mult_cat -Info: Elaborated megafunction instantiation "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" -Info: Instantiated megafunction "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_mult:op_6" with the following parameter: - Info: Parameter "LPM_WIDTHA" = "12" - Info: Parameter "LPM_WIDTHB" = "5" - Info: Parameter "LPM_WIDTHP" = "17" - Info: Parameter "LPM_WIDTHR" = "17" - Info: Parameter "LPM_WIDTHS" = "1" - Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED" - Info: Parameter "INPUT_A_IS_CONSTANT" = "NO" - Info: Parameter "INPUT_B_IS_CONSTANT" = "NO" - Info: Parameter "MAXIMIZE_SPEED" = "5" -Info: Found 1 design units, including 1 entities, in source file db/mult_aat.tdf - Info: Found entity 1: mult_aat -Warning: The following nodes have both tri-state and non-tri-state drivers - Warning: Inserted always-enabled tri-state buffer between "IO[17]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[16]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[15]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[14]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[13]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[12]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[11]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[10]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[9]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[8]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[7]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[6]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[5]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[4]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[3]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[2]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[1]" and its non-tri-state driver. - Warning: Inserted always-enabled tri-state buffer between "IO[0]" and its non-tri-state driver. -Info: Registers with preset signals will power-up high -Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back -Warning: TRI or OPNDRN buffers permanently disabled - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_PAR~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_RST~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[7]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[6]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[5]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[4]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[3]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[2]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[1]~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|SCSI_D[0]~synth" -Warning: TRI or OPNDRN buffers permanently enabled - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "IO~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_SEL~synth" - Warning: Node "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|nSCSI_BUSY~synth" -Warning: Output pins are stuck at VCC or GND - Warning (13410): Pin "nACSI_ACK" is stuck at VCC - Warning (13410): Pin "nACSI_CS" is stuck at VCC - Warning (13410): Pin "ACSI_DIR" is stuck at GND - Warning (13410): Pin "nSCSI_ACK" is stuck at VCC - Warning (13410): Pin "nSCSI_ATN" is stuck at VCC - Warning (13410): Pin "SCSI_DIR" is stuck at VCC - Warning (13410): Pin "nSYNC" is stuck at GND -Info: 78 registers lost all their fanouts during netlist optimizations. The first 78 are displayed below. - Info: Register "interrupt_handler:nobody|INT_CLEAR[31]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[30]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[29]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[28]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[27]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[26]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[25]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[24]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[23]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[22]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[21]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[20]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[19]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[18]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[17]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[16]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[15]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[14]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[13]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[12]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[11]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[10]" lost all its fanouts during netlist optimizations. - Info: Register "interrupt_handler:nobody|INT_CLEAR[7]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|FM_In" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[6]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[5]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[4]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[3]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[2]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[1]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_5n7:usedw_counter|counter_reg_bit[0]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|\P_WAVSTRB:TMP" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_MIDI|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|\P_IRQ:DCD_TRANS" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|AIP" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|LA" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BSY_ERR" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|TCR[3]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[5]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[4]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[3]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[2]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[1]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[0]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\PARITY:LOCK" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[7]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[6]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[5]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[4]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[3]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[2]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[1]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\FM_ENCODER:CNT[0]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|BUS_FREE" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|\REGISTERS:BSY_LOCK" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[2]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[1]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|\P_BUSFREE:TMP[0]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[7]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|IDR[6]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[9]" lost all its fanouts during netlist optimizations. - Info: Register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[9]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[8]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_pe9:rs_brp|dffe16a[10]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_pe9:ws_bwp|dffe16a[10]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|dffpipe_gd9:ws_brp|dffe15a[8]" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.IDLE" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_1" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_2" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_3" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|DMA_STATE.DMA_STEP_4" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.IDLE" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_SEND" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_TARG_RCV" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.DMA_INIT_RCV" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_CONTROL:I_CONTROL|CTRL_STATE.WAIT_2200ns" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" lost all its fanouts during netlist optimizations. - Info: Register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[12]" lost all its fanouts during netlist optimizations. -Info: Found the following redundant logic cells in design - Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[0]" - Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[1]" - Info (17048): Logic cell "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|cuda_combout_wire[2]" -Warning: Design contains 18 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "nFB_BURST" - Warning (15610): No output dependent on input pin "nACSI_DRQ" - Warning (15610): No output dependent on input pin "nACSI_INT" - Warning (15610): No output dependent on input pin "nSCSI_DRQ" - Warning (15610): No output dependent on input pin "nSCSI_MSG" - Warning (15610): No output dependent on input pin "nDCHG" - Warning (15610): No output dependent on input pin "SD_DATA0" - Warning (15610): No output dependent on input pin "SD_DATA1" - Warning (15610): No output dependent on input pin "SD_DATA2" - Warning (15610): No output dependent on input pin "SD_CARD_DEDECT" - Warning (15610): No output dependent on input pin "SD_WP" - Warning (15610): No output dependent on input pin "nDACK0" - Warning (15610): No output dependent on input pin "WP_CF_CARD" - Warning (15610): No output dependent on input pin "nSCSI_C_D" - Warning (15610): No output dependent on input pin "nSCSI_I_O" - Warning (15610): No output dependent on input pin "nFB_CS3" - Warning (15610): No output dependent on input pin "TOUT0" - Warning (15610): No output dependent on input pin "nMASTER" -Info: Implemented 11489 device resources after synthesis - the final resource count might be different - Info: Implemented 51 input pins - Info: Implemented 112 output pins - Info: Implemented 132 bidirectional pins - Info: Implemented 10796 logic cells - Info: Implemented 324 RAM segments - Info: Implemented 4 PLLs - Info: Implemented 6 DSP elements -Info: Quartus II Analysis & Synthesis was successful. 0 errors, 143 warnings - Info: Peak virtual memory: 347 megabytes - Info: Processing ended: Wed Dec 15 02:21:56 2010 - Info: Elapsed time: 00:01:19 - Info: Total CPU time (on all processors): 00:01:20 - - diff --git a/FPGA_Quartus_13.1/firebee1.tan.rpt b/FPGA_Quartus_13.1/firebee1.tan.rpt deleted file mode 100644 index b84e104..0000000 --- a/FPGA_Quartus_13.1/firebee1.tan.rpt +++ /dev/null @@ -1,6936 +0,0 @@ -Classic Timing Analyzer report for firebee1 -Wed Dec 15 02:25:22 2010 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Timing Analyzer Settings - 4. Clock Settings Summary - 5. Parallel Compilation - 6. Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' - 7. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' - 8. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' - 9. Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - 10. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - 11. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' - 12. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' - 13. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' - 14. Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' - 15. Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' - 16. Clock Setup: 'CLK33M' - 17. Clock Setup: 'MAIN_CLK' - 18. Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' - 19. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' - 20. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' - 21. Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - 22. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - 23. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' - 24. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' - 25. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' - 26. Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' - 27. Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' - 28. Clock Hold: 'CLK33M' - 29. Clock Hold: 'MAIN_CLK' - 30. tsu - 31. tco - 32. tpd - 33. th - 34. Board Trace Model Assignments - 35. Input Transition Times - 36. Slow Corner Signal Integrity Metrics - 37. Fast Corner Signal Integrity Metrics - 38. Ignored Timing Assignments - 39. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ -; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; -+-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ -; Worst-case tsu ; -4.528 ns ; 1.000 ns ; 5.528 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; -- ; MAIN_CLK ; 6867 ; -; Worst-case tco ; -14.840 ns ; 1.000 ns ; 15.840 ns ; interrupt_handler:nobody|INT_LATCH[8] ; nIRQ[5] ; MAIN_CLK ; -- ; 4976 ; -; Worst-case tpd ; -11.944 ns ; 1.000 ns ; 12.944 ns ; nFB_CS1 ; FB_AD[18] ; -- ; -- ; 514 ; -; Worst-case th ; -0.401 ns ; 1.000 ns ; 1.401 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; -- ; MAIN_CLK ; 117 ; -; Clock Setup: 'CLK33M' ; -5.966 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 3741 ; -; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -4.615 ns ; 24.98 MHz ( period = 40.033 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 3741 ; -; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -4.294 ns ; 95.92 MHz ( period = 10.425 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 3741 ; -; Clock Setup: 'MAIN_CLK' ; -4.261 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 27347 ; -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -2.673 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 86 ; -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -1.712 ns ; 66.00 MHz ( period = 15.151 ns ) ; N/A ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 29 ; -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 1.672 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0 ; -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 2.965 ns ; 132.01 MHz ( period = 7.575 ns ) ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0 ; -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 5.299 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0 ; -; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 28.590 ns ; 15.99 MHz ( period = 62.552 ns ) ; 186.15 MHz ( period = 5.372 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0 ; -; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 498.663 ns ; 2.00 MHz ( period = 500.416 ns ) ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0 ; -; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; 1997.239 ns ; 0.50 MHz ( period = 1999.998 ns ) ; 362.45 MHz ( period = 2.759 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0 ; -; Clock Hold: 'MAIN_CLK' ; -3.786 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 108 ; -; Clock Hold: 'CLK33M' ; -0.687 ns ; 33.00 MHz ( period = 30.303 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; CLK33M ; CLK33M ; 26 ; -; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -0.454 ns ; 24.98 MHz ( period = 40.033 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 26 ; -; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; 0.502 ns ; 15.99 MHz ( period = 62.552 ns ) ; N/A ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0 ; -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; 0.502 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0 ; -; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; 0.502 ns ; 95.92 MHz ( period = 10.425 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0 ; -; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; 0.564 ns ; 2.00 MHz ( period = 500.416 ns ) ; N/A ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0 ; -; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; 0.825 ns ; 0.50 MHz ( period = 1999.998 ns ) ; N/A ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0 ; -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; 1.825 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 0 ; -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; 2.664 ns ; 66.00 MHz ( period = 15.151 ns ) ; N/A ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0 ; -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; 3.263 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0 ; -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; 4.336 ns ; 132.01 MHz ( period = 7.575 ns ) ; N/A ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 0 ; -; Total number of failed paths ; ; ; ; ; ; ; ; 51319 ; -+-----------------------------------------------------------------------------------------+-------------+-----------------------------------+------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Timing Analyzer Settings ; -+------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ -; Option ; Setting ; From ; To ; Entity Name ; -+------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ -; Device Name ; EP3C40F484C6 ; ; ; ; -; Timing Models ; Final ; ; ; ; -; Default hold multicycle ; Same as Multicycle ; ; ; ; -; Cut paths between unrelated clock domains ; On ; ; ; ; -; Cut off read during write signal paths ; On ; ; ; ; -; Cut off feedback from I/O pins ; On ; ; ; ; -; Report Combined Fast/Slow Timing ; Off ; ; ; ; -; tpd Requirement ; 1 ns ; ; ; ; -; th Requirement ; 1 ns ; ; ; ; -; tsu Requirement ; 1 ns ; ; ; ; -; tco Requirement ; 1 ns ; ; ; ; -; fmax Requirement ; 30 ns ; ; ; ; -; Ignore Clock Settings ; Off ; ; ; ; -; Analyze latches as synchronous elements ; On ; ; ; ; -; Enable Recovery/Removal analysis ; Off ; ; ; ; -; Enable Clock Latency ; Off ; ; ; ; -; Use TimeQuest Timing Analyzer ; Off ; ; ; ; -; Nominal Core Supply Voltage ; 1.2V ; ; ; ; -; Minimum Core Junction Temperature ; 0 ; ; ; ; -; Maximum Core Junction Temperature ; 85 ; ; ; ; -; Number of source nodes to report per destination node ; 10 ; ; ; ; -; Number of destination nodes to report ; 10 ; ; ; ; -; Number of paths to report ; 200 ; ; ; ; -; Report Minimum Timing Checks ; Off ; ; ; ; -; Use Fast Timing Models ; Off ; ; ; ; -; Report IO Paths Separately ; Off ; ; ; ; -; Perform Multicorner Analysis ; On ; ; ; ; -; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; -; Reports worst-case timing paths for each clock domain and analysis ; On ; ; ; ; -; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; -; Removes common clock path pessimism (CCPP) during slack computation ; On ; ; ; ; -; Output I/O Timing Endpoint ; Near End ; ; ; ; -; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_0hh1 ; -; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe17|dffe18a ; dcfifo_0hh1 ; -; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe12|dffe13a ; dcfifo_3fh1 ; -; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe15|dffe16a ; dcfifo_3fh1 ; -; Cut Timing Path ; On ; rdptr_g ; ws_dgrp|dffpipe22|dffe23a ; dcfifo_8fi1 ; -; Input Maximum Delay ; 4 ns ; * ; FB_ALE ; ; -; Maximum Delay ; 5 ns ; FB_AD ; BA ; ; -; Maximum Delay ; 5 ns ; FB_AD ; VA ; ; -; Maximum Delay ; 5 ns ; FB_AD ; nVRAS ; ; -+------------------------------------------------------------------------------------------------------+--------------------+-----------------+---------------------------+-------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Settings Summary ; -+--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ -; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; -+--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; ; PLL output ; 0.5 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 1 ; 66 ; -9.578 ns ; ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1] ; ; PLL output ; 2.46 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 67 ; 900 ; -9.578 ns ; ; -; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2] ; ; PLL output ; 24.57 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 67 ; 90 ; -9.578 ns ; ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; ; PLL output ; 2.0 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 1800 ; -1.864 ns ; ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; ; PLL output ; 15.99 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 225 ; -1.864 ns ; ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; ; PLL output ; 24.98 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 144 ; -1.864 ns ; ; -; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3] ; ; PLL output ; 47.96 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 109 ; 75 ; -1.864 ns ; ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; -3.620 ns ; ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; -1.094 ns ; ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; 2.693 ns ; ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; ; PLL output ; 132.01 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 4 ; 1 ; 1.115 ns ; ; -; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; ; PLL output ; 66.0 MHz ; 0.000 ns ; 0.000 ns ; MAIN_CLK ; 2 ; 1 ; -4.884 ns ; ; -; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; ; PLL output ; 95.92 MHz ; 0.000 ns ; 0.000 ns ; CLK33M ; 218 ; 75 ; -2.843 ns ; ; -; CLK33M ; ; User Pin ; 33.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; -; MAIN_CLK ; ; User Pin ; 33.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; -+--------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+ - - -Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. -+-------------------------------------+ -; Parallel Compilation ; -+----------------------------+--------+ -; Processors ; Number ; -+----------------------------+--------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 1 ; -+----------------------------+--------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; -+-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; 1997.239 ns ; 362.45 MHz ( period = 2.759 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.574 ns ; -; 1997.297 ns ; 370.23 MHz ( period = 2.701 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.516 ns ; -; 1997.355 ns ; 378.36 MHz ( period = 2.643 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.458 ns ; -; 1997.413 ns ; 386.85 MHz ( period = 2.585 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.400 ns ; -; 1997.476 ns ; 396.51 MHz ( period = 2.522 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.337 ns ; -; 1997.531 ns ; 405.35 MHz ( period = 2.467 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.282 ns ; -; 1997.593 ns ; 415.80 MHz ( period = 2.405 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.220 ns ; -; 1997.626 ns ; 421.59 MHz ( period = 2.372 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.187 ns ; -; 1997.647 ns ; 425.35 MHz ( period = 2.351 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.166 ns ; -; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.129 ns ; -; 1997.684 ns ; 432.15 MHz ( period = 2.314 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.129 ns ; -; 1997.709 ns ; 436.87 MHz ( period = 2.289 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.104 ns ; -; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; -; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; -; 1997.742 ns ; 443.26 MHz ( period = 2.256 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.071 ns ; -; 1997.765 ns ; 447.83 MHz ( period = 2.233 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 2.049 ns ; -; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; -; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; -; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; -; 1997.800 ns ; 454.96 MHz ( period = 2.198 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 2.013 ns ; -; 1997.822 ns ; 459.56 MHz ( period = 2.176 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.992 ns ; -; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; -; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; -; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; -; 1997.858 ns ; 467.29 MHz ( period = 2.140 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.955 ns ; -; 1997.863 ns ; 468.38 MHz ( period = 2.135 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.950 ns ; -; 1997.880 ns ; 472.14 MHz ( period = 2.118 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.934 ns ; -; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; -; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; -; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; -; 1997.916 ns ; 480.31 MHz ( period = 2.082 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.897 ns ; -; 1997.918 ns ; 480.77 MHz ( period = 2.080 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.895 ns ; -; 1997.921 ns ; 481.46 MHz ( period = 2.077 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.892 ns ; -; 1997.941 ns ; 486.14 MHz ( period = 2.057 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.873 ns ; -; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; -; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; -; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; -; 1997.974 ns ; 494.07 MHz ( period = 2.024 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.839 ns ; -; 1997.976 ns ; 494.56 MHz ( period = 2.022 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.837 ns ; -; 1997.979 ns ; 495.29 MHz ( period = 2.019 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.834 ns ; -; 1997.980 ns ; 495.54 MHz ( period = 2.018 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.833 ns ; -; 1997.995 ns ; 499.25 MHz ( period = 2.003 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.819 ns ; -; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; -; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; -; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; -; 1998.032 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.781 ns ; -; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.779 ns ; -; 1998.034 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.779 ns ; -; 1998.037 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.776 ns ; -; 1998.038 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.775 ns ; -; 1998.055 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.759 ns ; -; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; -; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; -; 1998.090 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.723 ns ; -; 1998.091 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.723 ns ; -; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.721 ns ; -; 1998.092 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.721 ns ; -; 1998.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.718 ns ; -; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.717 ns ; -; 1998.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.717 ns ; -; 1998.113 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.701 ns ; -; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.665 ns ; -; 1998.148 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.665 ns ; -; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.665 ns ; -; 1998.149 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.665 ns ; -; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.663 ns ; -; 1998.150 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.663 ns ; -; 1998.152 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.662 ns ; -; 1998.153 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.660 ns ; -; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.659 ns ; -; 1998.154 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.659 ns ; -; 1998.167 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.647 ns ; -; 1998.206 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.607 ns ; -; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; -; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; -; 1998.207 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.607 ns ; -; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.605 ns ; -; 1998.208 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.605 ns ; -; 1998.209 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.605 ns ; -; 1998.210 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.604 ns ; -; 1998.211 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.602 ns ; -; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.601 ns ; -; 1998.212 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.601 ns ; -; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; -; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; -; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; -; 1998.265 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.549 ns ; -; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.547 ns ; -; 1998.266 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.547 ns ; -; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.547 ns ; -; 1998.267 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.547 ns ; -; 1998.268 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.546 ns ; -; 1998.269 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.544 ns ; -; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.543 ns ; -; 1998.270 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.543 ns ; -; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; -; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; -; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; -; 1998.323 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.491 ns ; -; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.489 ns ; -; 1998.324 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.489 ns ; -; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.489 ns ; -; 1998.325 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.489 ns ; -; 1998.326 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.488 ns ; -; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.486 ns ; -; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.485 ns ; -; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.485 ns ; -; 1998.328 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.486 ns ; -; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; -; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; -; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; -; 1998.381 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.433 ns ; -; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.432 ns ; -; 1998.382 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.431 ns ; -; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; -; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; -; 1998.383 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.431 ns ; -; 1998.384 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.430 ns ; -; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.428 ns ; -; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.427 ns ; -; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.427 ns ; -; 1998.386 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.428 ns ; -; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; -; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; -; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; -; 1998.439 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.375 ns ; -; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.374 ns ; -; 1998.440 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.373 ns ; -; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; -; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; -; 1998.441 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.373 ns ; -; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.372 ns ; -; 1998.442 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.372 ns ; -; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.370 ns ; -; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.369 ns ; -; 1998.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.370 ns ; -; 1998.445 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.369 ns ; -; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; -; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; -; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; -; 1998.497 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.317 ns ; -; 1998.498 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.316 ns ; -; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; -; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; -; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; -; 1998.499 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.315 ns ; -; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; -; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; -; 1998.500 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.314 ns ; -; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.312 ns ; -; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.813 ns ; 1.311 ns ; -; 1998.502 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.312 ns ; -; 1998.503 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.311 ns ; -; 1998.671 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 1.143 ns ; -; 1999.023 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.791 ns ; -; 1999.024 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.790 ns ; -; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.789 ns ; -; 1999.025 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.789 ns ; -; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; -; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; -; 1999.026 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.788 ns ; -; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; -; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; -; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; -; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; -; 1999.027 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.787 ns ; -; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.786 ns ; -; 1999.028 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.786 ns ; -; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.785 ns ; -; 1999.029 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.785 ns ; -; 1999.031 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 1999.998 ns ; 1999.814 ns ; 0.783 ns ; -+-------------+---------------------------------------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; -+------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; -; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; -; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; -; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; -; 498.663 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.569 ns ; -; 498.729 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.503 ns ; -; 498.743 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.489 ns ; -; 498.787 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.445 ns ; -; 498.800 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.432 ns ; -; 498.801 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.431 ns ; -; 498.858 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.374 ns ; -; 498.859 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.373 ns ; -; 498.894 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.338 ns ; -; 498.916 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.316 ns ; -; 498.917 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 1.315 ns ; -; 499.319 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.913 ns ; -; 499.422 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.810 ns ; -; 499.444 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.788 ns ; -; 499.449 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 500.416 ns ; 500.232 ns ; 0.783 ns ; -+------------+---------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; -+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; 28.590 ns ; 186.15 MHz ( period = 5.372 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns ; 31.135 ns ; 2.545 ns ; -; 28.759 ns ; 198.65 MHz ( period = 5.034 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_PULSE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 31.276 ns ; 31.135 ns ; 2.376 ns ; -; 54.429 ns ; 123.11 MHz ( period = 8.123 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.941 ns ; -; 54.452 ns ; 123.46 MHz ( period = 8.100 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.920 ns ; -; 54.563 ns ; 125.17 MHz ( period = 7.989 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.803 ns ; -; 54.586 ns ; 125.53 MHz ( period = 7.966 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.782 ns ; -; 54.600 ns ; 125.75 MHz ( period = 7.952 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.766 ns ; -; 54.623 ns ; 126.12 MHz ( period = 7.929 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.745 ns ; -; 54.812 ns ; 129.20 MHz ( period = 7.740 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.551 ns ; -; 54.822 ns ; 129.37 MHz ( period = 7.730 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.550 ns ; -; 54.835 ns ; 129.58 MHz ( period = 7.717 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.530 ns ; -; 54.845 ns ; 129.75 MHz ( period = 7.707 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.374 ns ; 7.529 ns ; -; 54.868 ns ; 130.14 MHz ( period = 7.684 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.491 ns ; -; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.474 ns ; -; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; -; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; -; 54.889 ns ; 130.50 MHz ( period = 7.663 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.481 ns ; -; 54.910 ns ; 130.86 MHz ( period = 7.642 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.456 ns ; -; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.453 ns ; -; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; -; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; -; 54.912 ns ; 130.89 MHz ( period = 7.640 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.460 ns ; -; 54.933 ns ; 131.25 MHz ( period = 7.619 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.435 ns ; -; 54.944 ns ; 131.44 MHz ( period = 7.608 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.417 ns ; -; 54.947 ns ; 131.49 MHz ( period = 7.605 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.414 ns ; -; 54.948 ns ; 131.51 MHz ( period = 7.604 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.413 ns ; -; 54.948 ns ; 131.51 MHz ( period = 7.604 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.413 ns ; -; 54.967 ns ; 131.84 MHz ( period = 7.585 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.396 ns ; -; 54.970 ns ; 131.89 MHz ( period = 7.582 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.393 ns ; -; 54.971 ns ; 131.91 MHz ( period = 7.581 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.392 ns ; -; 54.971 ns ; 131.91 MHz ( period = 7.581 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.392 ns ; -; 54.979 ns ; 132.05 MHz ( period = 7.573 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.382 ns ; -; 54.981 ns ; 132.08 MHz ( period = 7.571 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.387 ns ; -; 54.996 ns ; 132.35 MHz ( period = 7.556 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.374 ns ; -; 55.002 ns ; 132.45 MHz ( period = 7.550 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.361 ns ; -; 55.002 ns ; 132.45 MHz ( period = 7.550 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.353 ns ; -; 55.010 ns ; 132.59 MHz ( period = 7.542 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.362 ns ; -; 55.035 ns ; 133.03 MHz ( period = 7.517 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.326 ns ; -; 55.039 ns ; 133.10 MHz ( period = 7.513 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.316 ns ; -; 55.047 ns ; 133.24 MHz ( period = 7.505 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.312 ns ; -; 55.078 ns ; 133.80 MHz ( period = 7.474 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.291 ns ; -; 55.090 ns ; 134.01 MHz ( period = 7.462 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.270 ns ; -; 55.094 ns ; 134.08 MHz ( period = 7.458 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.266 ns ; -; 55.101 ns ; 134.21 MHz ( period = 7.451 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.INIT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.371 ns ; 7.270 ns ; -; 55.102 ns ; 134.23 MHz ( period = 7.450 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.259 ns ; -; 55.104 ns ; 134.26 MHz ( period = 7.448 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.257 ns ; -; 55.113 ns ; 134.43 MHz ( period = 7.439 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.249 ns ; -; 55.113 ns ; 134.43 MHz ( period = 7.439 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.248 ns ; -; 55.115 ns ; 134.46 MHz ( period = 7.437 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.249 ns ; -; 55.117 ns ; 134.50 MHz ( period = 7.435 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.245 ns ; -; 55.125 ns ; 134.64 MHz ( period = 7.427 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.238 ns ; -; 55.127 ns ; 134.68 MHz ( period = 7.425 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WRSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.236 ns ; -; 55.127 ns ; 134.68 MHz ( period = 7.425 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.243 ns ; -; 55.130 ns ; 134.73 MHz ( period = 7.422 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.236 ns ; -; 55.136 ns ; 134.84 MHz ( period = 7.416 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.227 ns ; -; 55.140 ns ; 134.92 MHz ( period = 7.412 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.232 ns ; -; 55.144 ns ; 134.99 MHz ( period = 7.408 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.224 ns ; -; 55.152 ns ; 135.14 MHz ( period = 7.400 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.212 ns ; -; 55.152 ns ; 135.14 MHz ( period = 7.400 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.218 ns ; -; 55.161 ns ; 135.30 MHz ( period = 7.391 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.208 ns ; -; 55.167 ns ; 135.41 MHz ( period = 7.385 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.199 ns ; -; 55.169 ns ; 135.45 MHz ( period = 7.383 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.357 ns ; 7.188 ns ; -; 55.181 ns ; 135.67 MHz ( period = 7.371 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.174 ns ; -; 55.181 ns ; 135.67 MHz ( period = 7.371 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.187 ns ; -; 55.190 ns ; 135.83 MHz ( period = 7.362 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.169 ns ; -; 55.204 ns ; 136.09 MHz ( period = 7.348 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.166 ns ; -; 55.206 ns ; 136.13 MHz ( period = 7.346 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.357 ns ; 7.151 ns ; -; 55.218 ns ; 136.35 MHz ( period = 7.334 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.137 ns ; -; 55.227 ns ; 136.52 MHz ( period = 7.325 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_HEAD_CTRL ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.145 ns ; -; 55.251 ns ; 136.97 MHz ( period = 7.301 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 7.101 ns ; -; 55.261 ns ; 137.16 MHz ( period = 7.291 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.105 ns ; -; 55.261 ns ; 137.16 MHz ( period = 7.291 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.100 ns ; -; 55.272 ns ; 137.36 MHz ( period = 7.280 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.369 ns ; 7.097 ns ; -; 55.274 ns ; 137.40 MHz ( period = 7.278 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.094 ns ; -; 55.278 ns ; 137.48 MHz ( period = 7.274 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|TRACK_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.274 ns ; 6.996 ns ; -; 55.286 ns ; 137.63 MHz ( period = 7.266 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.080 ns ; -; 55.288 ns ; 137.67 MHz ( period = 7.264 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 7.084 ns ; -; 55.294 ns ; 137.78 MHz ( period = 7.258 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.076 ns ; -; 55.295 ns ; 137.80 MHz ( period = 7.257 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.070 ns ; -; 55.298 ns ; 137.85 MHz ( period = 7.254 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.068 ns ; -; 55.299 ns ; 137.87 MHz ( period = 7.253 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.065 ns ; -; 55.300 ns ; 137.89 MHz ( period = 7.252 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.068 ns ; -; 55.303 ns ; 137.95 MHz ( period = 7.249 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 7.061 ns ; -; 55.311 ns ; 138.10 MHz ( period = 7.241 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.057 ns ; -; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.045 ns ; -; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.045 ns ; -; 55.316 ns ; 138.20 MHz ( period = 7.236 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.052 ns ; -; 55.317 ns ; 138.22 MHz ( period = 7.235 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.044 ns ; -; 55.319 ns ; 138.26 MHz ( period = 7.233 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 7.042 ns ; -; 55.322 ns ; 138.31 MHz ( period = 7.230 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_WR_DATA ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.044 ns ; -; 55.323 ns ; 138.33 MHz ( period = 7.229 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.043 ns ; -; 55.323 ns ; 138.33 MHz ( period = 7.229 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.047 ns ; -; 55.324 ns ; 138.35 MHz ( period = 7.228 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.031 ns ; -; 55.326 ns ; 138.39 MHz ( period = 7.226 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.040 ns ; -; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 7.024 ns ; -; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; -; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; -; 55.328 ns ; 138.43 MHz ( period = 7.224 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 7.031 ns ; -; 55.331 ns ; 138.48 MHz ( period = 7.221 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.032 ns ; -; 55.331 ns ; 138.48 MHz ( period = 7.221 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.029 ns ; -; 55.332 ns ; 138.50 MHz ( period = 7.220 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.028 ns ; -; 55.332 ns ; 138.50 MHz ( period = 7.220 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.033 ns ; -; 55.333 ns ; 138.52 MHz ( period = 7.219 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.027 ns ; -; 55.333 ns ; 138.52 MHz ( period = 7.219 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.027 ns ; -; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.024 ns ; -; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.024 ns ; -; 55.339 ns ; 138.64 MHz ( period = 7.213 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 7.031 ns ; -; 55.340 ns ; 138.66 MHz ( period = 7.212 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.023 ns ; -; 55.341 ns ; 138.68 MHz ( period = 7.211 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.019 ns ; -; 55.342 ns ; 138.70 MHz ( period = 7.210 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 7.021 ns ; -; 55.344 ns ; 138.73 MHz ( period = 7.208 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.360 ns ; 7.016 ns ; -; 55.344 ns ; 138.73 MHz ( period = 7.208 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 7.022 ns ; -; 55.349 ns ; 138.83 MHz ( period = 7.203 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 7.006 ns ; -; 55.354 ns ; 138.93 MHz ( period = 7.198 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 7.011 ns ; -; 55.354 ns ; 138.93 MHz ( period = 7.198 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_LOAD_SHFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.008 ns ; -; 55.355 ns ; 138.95 MHz ( period = 7.197 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_MULTISECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.007 ns ; -; 55.356 ns ; 138.97 MHz ( period = 7.196 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.006 ns ; -; 55.356 ns ; 138.97 MHz ( period = 7.196 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_FIRSTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 7.006 ns ; -; 55.361 ns ; 139.06 MHz ( period = 7.191 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.355 ns ; 6.994 ns ; -; 55.364 ns ; 139.12 MHz ( period = 7.188 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.997 ns ; -; 55.364 ns ; 139.12 MHz ( period = 7.188 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_RDSTAT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 6.998 ns ; -; 55.367 ns ; 139.18 MHz ( period = 7.185 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.362 ns ; 6.995 ns ; -; 55.367 ns ; 139.18 MHz ( period = 7.185 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 7.001 ns ; -; 55.374 ns ; 139.31 MHz ( period = 7.178 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.996 ns ; -; 55.376 ns ; 139.35 MHz ( period = 7.176 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.987 ns ; -; 55.379 ns ; 139.41 MHz ( period = 7.173 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.984 ns ; -; 55.383 ns ; 139.49 MHz ( period = 7.169 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.980 ns ; -; 55.383 ns ; 139.49 MHz ( period = 7.169 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.967 ns ; -; 55.384 ns ; 139.51 MHz ( period = 7.168 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.986 ns ; -; 55.386 ns ; 139.55 MHz ( period = 7.166 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.964 ns ; -; 55.386 ns ; 139.55 MHz ( period = 7.166 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.982 ns ; -; 55.387 ns ; 139.57 MHz ( period = 7.165 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.963 ns ; -; 55.387 ns ; 139.57 MHz ( period = 7.165 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.963 ns ; -; 55.389 ns ; 139.61 MHz ( period = 7.163 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.983 ns ; -; 55.393 ns ; 139.68 MHz ( period = 7.159 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.972 ns ; -; 55.399 ns ; 139.80 MHz ( period = 7.153 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.966 ns ; -; 55.403 ns ; 139.88 MHz ( period = 7.149 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.374 ns ; 6.971 ns ; -; 55.406 ns ; 139.94 MHz ( period = 7.146 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.959 ns ; -; 55.406 ns ; 139.94 MHz ( period = 7.146 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_NEXTBYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.959 ns ; -; 55.408 ns ; 139.98 MHz ( period = 7.144 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.739 ns ; 7.331 ns ; -; 55.409 ns ; 140.00 MHz ( period = 7.143 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.961 ns ; -; 55.415 ns ; 140.11 MHz ( period = 7.137 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.944 ns ; -; 55.418 ns ; 140.17 MHz ( period = 7.134 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.354 ns ; 6.936 ns ; -; 55.418 ns ; 140.17 MHz ( period = 7.134 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_DR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.350 ns ; 6.932 ns ; -; 55.422 ns ; 140.25 MHz ( period = 7.130 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.946 ns ; -; 55.428 ns ; 140.37 MHz ( period = 7.124 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SET_DRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.938 ns ; -; 55.428 ns ; 140.37 MHz ( period = 7.124 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.935 ns ; -; 55.430 ns ; 140.41 MHz ( period = 7.122 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 6.922 ns ; -; 55.440 ns ; 140.61 MHz ( period = 7.112 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.DELAY_15MS ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.921 ns ; -; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.920 ns ; -; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; -; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; -; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.927 ns ; -; 55.441 ns ; 140.63 MHz ( period = 7.111 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.918 ns ; -; 55.443 ns ; 140.67 MHz ( period = 7.109 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|COMMAND_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.922 ns ; -; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.907 ns ; -; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; -; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; -; 55.456 ns ; 140.92 MHz ( period = 7.096 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.914 ns ; -; 55.459 ns ; 140.98 MHz ( period = 7.093 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.909 ns ; -; 55.462 ns ; 141.04 MHz ( period = 7.090 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.902 ns ; -; 55.463 ns ; 141.06 MHz ( period = 7.089 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.901 ns ; -; 55.465 ns ; 141.10 MHz ( period = 7.087 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_DELAY_B3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.901 ns ; -; 55.467 ns ; 141.14 MHz ( period = 7.085 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.897 ns ; -; 55.469 ns ; 141.18 MHz ( period = 7.083 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.895 ns ; -; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.365 ns ; 6.895 ns ; -; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; -; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; -; 55.470 ns ; 141.20 MHz ( period = 7.082 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.372 ns ; 6.902 ns ; -; 55.471 ns ; 141.22 MHz ( period = 7.081 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.364 ns ; 6.893 ns ; -; 55.477 ns ; 141.34 MHz ( period = 7.075 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.889 ns ; -; 55.478 ns ; 141.36 MHz ( period = 7.074 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.890 ns ; -; 55.480 ns ; 141.40 MHz ( period = 7.072 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.888 ns ; -; 55.483 ns ; 141.46 MHz ( period = 7.069 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.885 ns ; -; 55.486 ns ; 141.52 MHz ( period = 7.066 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_STEP_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.880 ns ; -; 55.487 ns ; 141.54 MHz ( period = 7.065 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.883 ns ; -; 55.490 ns ; 141.60 MHz ( period = 7.062 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.278 ns ; 6.788 ns ; -; 55.490 ns ; 141.60 MHz ( period = 7.062 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.876 ns ; -; 55.491 ns ; 141.62 MHz ( period = 7.061 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_DELAY_B2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.368 ns ; 6.877 ns ; -; 55.492 ns ; 141.64 MHz ( period = 7.060 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_TRAP ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.874 ns ; -; 55.494 ns ; 141.68 MHz ( period = 7.058 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_BYTE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.366 ns ; 6.872 ns ; -; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.354 ns ; 6.859 ns ; -; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; -; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; -; 55.495 ns ; 141.70 MHz ( period = 7.057 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.866 ns ; -; 55.496 ns ; 141.72 MHz ( period = 7.056 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.863 ns ; -; 55.497 ns ; 141.74 MHz ( period = 7.055 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.866 ns ; -; 55.499 ns ; 141.78 MHz ( period = 7.053 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_INDEX_3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.860 ns ; -; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.859 ns ; -; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_DELAY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.361 ns ; 6.861 ns ; -; 55.500 ns ; 141.80 MHz ( period = 7.052 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.859 ns ; -; 55.501 ns ; 141.82 MHz ( period = 7.051 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.869 ns ; -; 55.503 ns ; 141.86 MHz ( period = 7.049 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.867 ns ; -; 55.506 ns ; 141.92 MHz ( period = 7.046 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.370 ns ; 6.864 ns ; -; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_ERRFLAG ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.352 ns ; 6.845 ns ; -; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_SECT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; -; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_LEN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; -; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.856 ns ; -; 55.507 ns ; 141.94 MHz ( period = 7.045 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_SCAN_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.359 ns ; 6.852 ns ; -; 55.508 ns ; 141.96 MHz ( period = 7.044 ns ) ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\P_DELAY:DELCNT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_SCAN_TRACK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 62.552 ns ; 62.363 ns ; 6.855 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; -4.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.928 ns ; 3.687 ns ; -; -4.573 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.921 ns ; 3.652 ns ; -; -4.568 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.642 ns ; -; -4.562 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.915 ns ; 3.647 ns ; -; -4.553 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.635 ns ; -; -4.549 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.631 ns ; -; -4.541 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.928 ns ; 3.613 ns ; -; -4.533 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.610 ns ; -; -4.526 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.918 ns ; 3.608 ns ; -; -4.479 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.898 ns ; -; -4.440 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.141 ns ; -; -4.440 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.517 ns ; -; -4.413 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.114 ns ; -; -4.409 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.486 ns ; -; -4.407 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.916 ns ; 3.491 ns ; -; -4.406 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.914 ns ; 3.492 ns ; -; -4.394 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.468 ns ; -; -4.391 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.465 ns ; -; -4.391 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.466 ns ; -; -4.386 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.461 ns ; -; -4.381 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.458 ns ; -; -4.378 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.455 ns ; -; -4.372 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.447 ns ; -; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.447 ns ; -; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.447 ns ; -; -4.370 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.445 ns ; -; -4.369 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 4.068 ns ; -; -4.367 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.444 ns ; -; -4.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.441 ns ; -; -4.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.441 ns ; -; -4.364 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.441 ns ; -; -4.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 4.063 ns ; -; -4.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.440 ns ; -; -4.361 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.436 ns ; -; -4.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.434 ns ; -; -4.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.435 ns ; -; -4.357 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.431 ns ; -; -4.356 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.433 ns ; -; -4.353 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.428 ns ; -; -4.353 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.428 ns ; -; -4.351 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.931 ns ; 3.420 ns ; -; -4.348 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.426 ns ; -; -4.318 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.916 ns ; 3.402 ns ; -; -4.316 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.919 ns ; 3.397 ns ; -; -4.308 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 4.008 ns ; -; -4.306 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.725 ns ; -; -4.305 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.379 ns ; -; -4.301 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 4.002 ns ; -; -4.299 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.376 ns ; -; -4.298 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.924 ns ; 3.374 ns ; -; -4.297 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.374 ns ; -; -4.294 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.372 ns ; -; -4.293 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.370 ns ; -; -4.293 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.922 ns ; 3.371 ns ; -; -4.290 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.365 ns ; -; -4.289 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.366 ns ; -; -4.289 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.364 ns ; -; -4.288 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.363 ns ; -; -4.279 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.356 ns ; -; -4.278 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.355 ns ; -; -4.277 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.354 ns ; -; -4.273 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.347 ns ; -; -4.271 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.972 ns ; -; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.970 ns ; -; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.343 ns ; -; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.346 ns ; -; -4.269 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.346 ns ; -; -4.268 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.345 ns ; -; -4.268 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.345 ns ; -; -4.267 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.344 ns ; -; -4.266 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.343 ns ; -; -4.264 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.341 ns ; -; -4.264 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.341 ns ; -; -4.262 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.339 ns ; -; -4.262 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.339 ns ; -; -4.259 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.960 ns ; -; -4.259 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.334 ns ; -; -4.258 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.332 ns ; -; -4.256 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.333 ns ; -; -4.256 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.333 ns ; -; -4.255 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.329 ns ; -; -4.255 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.330 ns ; -; -4.253 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.330 ns ; -; -4.253 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.327 ns ; -; -4.251 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.328 ns ; -; -4.248 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.325 ns ; -; -4.247 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.324 ns ; -; -4.246 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.323 ns ; -; -4.245 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.319 ns ; -; -4.243 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.944 ns ; -; -4.241 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.316 ns ; -; -4.236 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.310 ns ; -; -4.230 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.929 ns ; -; -4.229 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.928 ns ; -; -4.219 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.919 ns ; -; -4.217 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.292 ns ; -; -4.215 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.916 ns ; -; -4.203 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.904 ns ; -; -4.199 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.899 ns ; -; -4.195 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.614 ns ; -; -4.194 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.269 ns ; -; -4.190 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.257 ns ; -; -4.188 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.887 ns ; -; -4.188 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.624 ns ; 3.564 ns ; -; -4.179 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.931 ns ; 3.248 ns ; -; -4.175 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.876 ns ; -; -4.172 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.591 ns ; -; -4.156 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.855 ns ; -; -4.154 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.551 ns ; -; -4.149 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.850 ns ; -; -4.148 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.847 ns ; -; -4.143 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.540 ns ; -; -4.142 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.612 ns ; 3.530 ns ; -; -4.140 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.624 ns ; 3.516 ns ; -; -4.139 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.216 ns ; -; -4.138 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.838 ns ; -; -4.137 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.211 ns ; -; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; -; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; -; -4.135 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.212 ns ; -; -4.134 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.211 ns ; -; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.210 ns ; -; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.208 ns ; -; -4.133 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.208 ns ; -; -4.130 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.204 ns ; -; -4.130 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.205 ns ; -; -4.128 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.205 ns ; -; -4.127 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.202 ns ; -; -4.125 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.199 ns ; -; -4.124 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.191 ns ; -; -4.113 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.190 ns ; -; -4.113 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.190 ns ; -; -4.113 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.616 ns ; 3.497 ns ; -; -4.109 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.186 ns ; -; -4.108 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.505 ns ; -; -4.104 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.171 ns ; -; -4.102 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.176 ns ; -; -4.101 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.802 ns ; -; -4.100 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.519 ns ; -; -4.098 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.936 ns ; 3.162 ns ; -; -4.098 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.495 ns ; -; -4.097 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.796 ns ; -; -4.092 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.793 ns ; -; -4.088 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.507 ns ; -; -4.083 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.480 ns ; -; -4.078 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.779 ns ; -; -4.069 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.306 ns ; 3.763 ns ; -; -4.068 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.612 ns ; 3.456 ns ; -; -4.068 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.306 ns ; 3.762 ns ; -; -4.064 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.307 ns ; 3.757 ns ; -; -4.049 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.613 ns ; 3.436 ns ; -; -4.045 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.442 ns ; -; -4.045 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.442 ns ; -; -4.041 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.308 ns ; 3.733 ns ; -; -4.038 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.615 ns ; 3.423 ns ; -; -4.034 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.938 ns ; 3.096 ns ; -; -4.034 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.943 ns ; 3.091 ns ; -; -4.034 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.734 ns ; -; -4.024 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.613 ns ; 3.411 ns ; -; -4.019 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.438 ns ; -; -4.016 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.093 ns ; -; -4.015 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.092 ns ; -; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.091 ns ; -; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.091 ns ; -; -4.014 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.089 ns ; -; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; -; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; -; -4.012 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.089 ns ; -; -4.011 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.088 ns ; -; -4.011 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.085 ns ; -; -4.009 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.084 ns ; -; -4.006 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.080 ns ; -; -4.006 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.403 ns ; -; -4.005 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.080 ns ; -; -4.004 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.301 ns ; 3.703 ns ; -; -4.000 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.581 ns ; 3.419 ns ; -; -3.998 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.075 ns ; -; -3.998 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.299 ns ; 3.699 ns ; -; -3.996 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.073 ns ; -; -3.995 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.392 ns ; -; -3.993 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.070 ns ; -; -3.991 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.068 ns ; -; -3.989 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.938 ns ; 3.051 ns ; -; -3.989 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.610 ns ; 3.379 ns ; -; -3.988 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.923 ns ; 3.065 ns ; -; -3.986 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.061 ns ; -; -3.986 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.061 ns ; -; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.060 ns ; -; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.059 ns ; -; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.059 ns ; -; -3.985 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.060 ns ; -; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.058 ns ; -; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.925 ns ; 3.059 ns ; -; -3.983 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.057 ns ; -; -3.982 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.056 ns ; -; -3.981 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.926 ns ; 3.055 ns ; -; -3.972 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.603 ns ; 3.369 ns ; -; -3.970 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.933 ns ; 3.037 ns ; -; -3.966 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.300 ns ; 3.666 ns ; -; -3.954 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.145 ns ; -0.935 ns ; 3.019 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; -2.673 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.814 ns ; 3.487 ns ; -; -2.447 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 3.530 ns ; -; -2.348 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_BANK_OK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.155 ns ; -; -2.346 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.153 ns ; -; -2.275 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.082 ns ; -; -2.254 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 3.061 ns ; -; -2.243 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.138 ns ; 3.381 ns ; -; -2.194 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.100 ns ; 3.294 ns ; -; -2.187 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 3.262 ns ; -; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.239 ns ; -; -2.024 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.169 ns ; -; -2.006 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 3.151 ns ; -; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.132 ns ; 3.125 ns ; -; -1.990 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_FIFO_WRE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.797 ns ; -; -1.911 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.140 ns ; 3.051 ns ; -; -1.896 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 2.986 ns ; -; -1.895 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 2.985 ns ; -; -1.873 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7F ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.680 ns ; -; -1.871 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.262 ns ; 0.807 ns ; 2.678 ns ; -; -1.838 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLR_FIFO ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLR_FIFO_SYNC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; -1.306 ns ; 0.532 ns ; -; -1.834 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.131 ns ; 2.965 ns ; -; -1.828 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.907 ns ; -; -1.827 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.906 ns ; -; -1.824 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.903 ns ; -; -1.800 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.131 ns ; 2.931 ns ; -; -1.800 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.879 ns ; -; -1.765 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.910 ns ; -; -1.763 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.132 ns ; 2.895 ns ; -; -1.755 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.136 ns ; 2.891 ns ; -; -1.647 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.133 ns ; 2.780 ns ; -; -1.646 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.133 ns ; 2.779 ns ; -; -1.641 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.770 ns ; -; -1.610 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.739 ns ; -; -1.593 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.152 ns ; 2.745 ns ; -; -1.556 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.134 ns ; 2.690 ns ; -; -1.553 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.682 ns ; -; -1.470 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.612 ns ; -; -1.465 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.129 ns ; 2.594 ns ; -; -1.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.127 ns ; 2.590 ns ; -; -1.451 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.596 ns ; -; -1.441 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.586 ns ; -; -1.436 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.136 ns ; 2.572 ns ; -; -1.413 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.555 ns ; -; -1.361 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.506 ns ; -; -1.341 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.145 ns ; 2.486 ns ; -; -1.329 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.404 ns ; -; -1.327 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.410 ns ; -; -1.326 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.410 ns ; -; -1.302 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.385 ns ; -; -1.298 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.126 ns ; 2.424 ns ; -; -1.271 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 2.348 ns ; -; -1.252 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.335 ns ; -; -1.216 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.142 ns ; 2.358 ns ; -; -1.202 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.277 ns ; -; -1.202 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.075 ns ; 2.277 ns ; -; -1.181 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.083 ns ; 2.264 ns ; -; -1.167 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_CB8 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.246 ns ; -; -1.162 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8F ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.079 ns ; 2.241 ns ; -; -1.139 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.130 ns ; 2.269 ns ; -; -1.102 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.186 ns ; -; -1.077 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.140 ns ; 2.217 ns ; -; -1.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.151 ns ; 2.199 ns ; -; -1.047 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.084 ns ; 2.131 ns ; -; -0.910 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.123 ns ; 2.033 ns ; -; -0.901 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.992 ns ; -; -0.827 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.917 ns ; -; -0.750 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.841 ns ; -; -0.750 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.841 ns ; -; -0.741 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.832 ns ; -; -0.642 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.730 ns ; -; -0.623 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.711 ns ; -; -0.616 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.704 ns ; -; -0.600 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.088 ns ; 1.688 ns ; -; -0.596 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.087 ns ; 1.683 ns ; -; -0.413 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 1.490 ns ; -; -0.410 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.077 ns ; 1.487 ns ; -; -0.199 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.289 ns ; -; -0.193 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2B ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.090 ns ; 1.283 ns ; -; -0.191 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.282 ns ; -; -0.186 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.175 ns ; 4.361 ns ; -; -0.183 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.274 ns ; -; -0.102 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 3.040 ns ; 3.142 ns ; -; -0.068 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.171 ns ; 4.239 ns ; -; -0.062 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.175 ns ; 4.237 ns ; -; -0.041 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.162 ns ; 4.203 ns ; -; -0.024 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.181 ns ; 4.205 ns ; -; 0.003 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.168 ns ; 4.165 ns ; -; 0.039 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.173 ns ; 4.134 ns ; -; 0.059 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 1.264 ns ; 1.091 ns ; 1.032 ns ; -; 0.073 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.171 ns ; 4.098 ns ; -; 0.080 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.167 ns ; 4.087 ns ; -; 0.108 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.181 ns ; 4.073 ns ; -; 0.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.168 ns ; 4.045 ns ; -; 0.165 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.182 ns ; 4.017 ns ; -; 0.166 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.173 ns ; 4.007 ns ; -; 0.194 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.167 ns ; 3.973 ns ; -; 0.201 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.162 ns ; 3.961 ns ; -; 0.250 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.464 ns ; 4.214 ns ; -; 0.301 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.522 ns ; 4.221 ns ; -; 0.306 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.483 ns ; 4.177 ns ; -; 0.375 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.514 ns ; 4.139 ns ; -; 0.401 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.475 ns ; 4.074 ns ; -; 0.451 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.182 ns ; 3.731 ns ; -; 0.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.477 ns ; 4.023 ns ; -; 0.467 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.473 ns ; 4.006 ns ; -; 0.509 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a1~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.503 ns ; 3.994 ns ; -; 0.514 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.469 ns ; 3.955 ns ; -; 0.539 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.484 ns ; 3.945 ns ; -; 0.568 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.823 ns ; -; 0.576 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.470 ns ; 3.894 ns ; -; 0.579 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.804 ns ; -; 0.580 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.408 ns ; 3.828 ns ; -; 0.619 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.768 ns ; -; 0.677 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.516 ns ; 3.839 ns ; -; 0.695 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a2~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.508 ns ; 3.813 ns ; -; 0.773 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a4~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.512 ns ; 3.739 ns ; -; 0.800 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.587 ns ; -; 0.805 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.582 ns ; -; 0.810 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.509 ns ; 3.699 ns ; -; 0.818 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_L_D[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_datain_reg0 ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.523 ns ; 3.705 ns ; -; 0.834 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.212 ns ; 3.378 ns ; -; 0.838 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.545 ns ; -; 0.840 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.551 ns ; -; 0.841 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.551 ns ; -; 0.933 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.387 ns ; 3.454 ns ; -; 0.965 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.418 ns ; -; 0.965 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.383 ns ; 3.418 ns ; -; 1.026 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.365 ns ; -; 1.038 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 3.347 ns ; -; 1.057 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.334 ns ; -; 1.110 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.057 ns ; 2.947 ns ; -; 1.120 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.272 ns ; -; 1.147 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.391 ns ; 3.244 ns ; -; 1.153 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 3.245 ns ; -; 1.207 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.392 ns ; 3.185 ns ; -; 1.266 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 3.133 ns ; -; 1.344 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.057 ns ; 2.713 ns ; -; 1.374 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_S[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 3.024 ns ; -; 1.417 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.982 ns ; -; 1.417 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T2A ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.982 ns ; -; 1.426 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.973 ns ; -; 1.426 ns ; 162.63 MHz ( period = 6.149 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.936 ns ; -; 1.427 ns ; 162.65 MHz ( period = 6.148 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.935 ns ; -; 1.481 ns ; 164.10 MHz ( period = 6.094 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.881 ns ; -; 1.482 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 2.916 ns ; -; 1.484 ns ; 164.18 MHz ( period = 6.091 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.878 ns ; -; 1.526 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CLEAR_FIFO_CNT ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 3.055 ns ; 1.529 ns ; -; 1.527 ns ; 165.34 MHz ( period = 6.048 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.835 ns ; -; 1.540 ns ; 165.70 MHz ( period = 6.035 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.822 ns ; -; 1.543 ns ; 165.78 MHz ( period = 6.032 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.819 ns ; -; 1.582 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.858 ns ; 3.276 ns ; -; 1.589 ns ; 167.06 MHz ( period = 5.986 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.773 ns ; -; 1.598 ns ; 167.31 MHz ( period = 5.977 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.764 ns ; -; 1.601 ns ; 167.39 MHz ( period = 5.974 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.761 ns ; -; 1.656 ns ; 168.95 MHz ( period = 5.919 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.706 ns ; -; 1.676 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.850 ns ; 3.174 ns ; -; 1.677 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.147 ns ; -; 1.679 ns ; 169.61 MHz ( period = 5.896 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.700 ns ; -; 1.680 ns ; 169.64 MHz ( period = 5.895 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.699 ns ; -; 1.686 ns ; 169.81 MHz ( period = 5.889 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.668 ns ; -; 1.687 ns ; 169.84 MHz ( period = 5.888 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.667 ns ; -; 1.714 ns ; 170.62 MHz ( period = 5.861 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.648 ns ; -; 1.734 ns ; 171.20 MHz ( period = 5.841 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.645 ns ; -; 1.737 ns ; 171.29 MHz ( period = 5.838 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.642 ns ; -; 1.738 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.841 ns ; 3.103 ns ; -; 1.741 ns ; 171.41 MHz ( period = 5.834 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.613 ns ; -; 1.744 ns ; 171.50 MHz ( period = 5.831 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.610 ns ; -; 1.746 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[21] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.841 ns ; 3.095 ns ; -; 1.747 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.865 ns ; 3.118 ns ; -; 1.750 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.866 ns ; 3.116 ns ; -; 1.756 ns ; 171.85 MHz ( period = 5.819 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[6] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.362 ns ; 5.606 ns ; -; 1.760 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.865 ns ; 3.105 ns ; -; 1.779 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.045 ns ; -; 1.780 ns ; 172.56 MHz ( period = 5.795 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.599 ns ; -; 1.787 ns ; 172.77 MHz ( period = 5.788 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[4] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.567 ns ; -; 1.792 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[24] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 3.032 ns ; -; 1.793 ns ; 172.95 MHz ( period = 5.782 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.586 ns ; -; 1.796 ns ; 173.04 MHz ( period = 5.779 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.583 ns ; -; 1.800 ns ; 173.16 MHz ( period = 5.775 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.554 ns ; -; 1.803 ns ; 173.25 MHz ( period = 5.772 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.551 ns ; -; 1.805 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 2.580 ns ; -; 1.808 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.385 ns ; 2.577 ns ; -; 1.812 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.831 ns ; 3.019 ns ; -; 1.829 ns ; 174.03 MHz ( period = 5.746 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.525 ns ; -; 1.830 ns ; 174.06 MHz ( period = 5.745 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.524 ns ; -; 1.840 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.559 ns ; -; 1.842 ns ; 174.43 MHz ( period = 5.733 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.537 ns ; -; 1.842 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BA_P[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.399 ns ; 2.557 ns ; -; 1.842 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[28] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.824 ns ; 2.982 ns ; -; 1.845 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; Video:Fredi_Aschwanden|lpm_ff0:inst18|lpm_ff:lpm_ff_component|dffs[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.847 ns ; 3.002 ns ; -; 1.847 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[23] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.847 ns ; 3.000 ns ; -; 1.849 ns ; 174.64 MHz ( period = 5.726 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.505 ns ; -; 1.851 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 3.955 ns ; 4.398 ns ; 2.547 ns ; -; 1.851 ns ; 174.70 MHz ( period = 5.724 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.528 ns ; -; 1.854 ns ; 174.79 MHz ( period = 5.721 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.379 ns ; 5.525 ns ; -; 1.858 ns ; 174.92 MHz ( period = 5.717 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_bwp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.496 ns ; -; 1.861 ns ; 175.01 MHz ( period = 5.714 ns ) ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_oe9:ws_brp|dffe21a[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 7.575 ns ; 7.354 ns ; 5.493 ns ; -; 1.865 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.826 ns ; 2.961 ns ; -; 1.873 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst19|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.829 ns ; 2.956 ns ; -; 1.881 ns ; None ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst17|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 5.049 ns ; 4.829 ns ; 2.948 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; -+----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; 2.965 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.639 ns ; -; 2.966 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.638 ns ; -; 2.967 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.637 ns ; -; 2.968 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.636 ns ; -; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; -; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; -; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; -; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; -; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; -; 3.093 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.511 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.094 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.510 ns ; -; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; -; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; -; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; -; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; -; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; -; 3.095 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.509 ns ; -; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; -; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; -; 3.096 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.508 ns ; -; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; -; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; -; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; -; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; -; 3.097 ns ; Restricted to 500.0 MHz ( period = 2.0 ns ) ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; 3.788 ns ; 3.604 ns ; 0.507 ns ; -+----------+---------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; -+----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; 5.299 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.118 ns ; 0.819 ns ; -; 5.479 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.637 ns ; -; 5.480 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.636 ns ; -; 5.606 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.510 ns ; -; 5.608 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; 6.313 ns ; 6.116 ns ; 0.508 ns ; -+----------+----------------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; 1.672 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 3.636 ns ; -; 1.683 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.304 ns ; 3.621 ns ; -; 1.703 ns ; 170.30 MHz ( period = 5.872 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 5.190 ns ; -; 1.806 ns ; 173.34 MHz ( period = 5.769 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.887 ns ; 5.081 ns ; -; 1.842 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.327 ns ; 3.485 ns ; -; 1.881 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.428 ns ; -; 1.904 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.325 ns ; 3.421 ns ; -; 1.914 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.395 ns ; -; 1.923 ns ; 176.93 MHz ( period = 5.652 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 4.970 ns ; -; 2.000 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 3.308 ns ; -; 2.018 ns ; 179.95 MHz ( period = 5.557 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.883 ns ; 4.865 ns ; -; 2.034 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.321 ns ; 3.287 ns ; -; 2.040 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 3.253 ns ; -; 2.068 ns ; 181.59 MHz ( period = 5.507 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.887 ns ; 4.819 ns ; -; 2.105 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.302 ns ; 3.197 ns ; -; 2.112 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.488 ns ; 2.376 ns ; -; 2.131 ns ; 183.69 MHz ( period = 5.444 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.896 ns ; 4.765 ns ; -; 2.141 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 3.175 ns ; -; 2.151 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.307 ns ; 3.156 ns ; -; 2.155 ns ; 184.50 MHz ( period = 5.420 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.900 ns ; 4.745 ns ; -; 2.159 ns ; 184.64 MHz ( period = 5.416 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.891 ns ; 4.732 ns ; -; 2.166 ns ; 184.88 MHz ( period = 5.409 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.712 ns ; -; 2.178 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.309 ns ; 3.131 ns ; -; 2.202 ns ; 186.12 MHz ( period = 5.373 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.893 ns ; 4.691 ns ; -; 2.203 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 3.109 ns ; -; 2.207 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.335 ns ; 3.128 ns ; -; 2.238 ns ; 187.37 MHz ( period = 5.337 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.640 ns ; -; 2.242 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.317 ns ; 3.075 ns ; -; 2.260 ns ; 188.15 MHz ( period = 5.315 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.891 ns ; 4.631 ns ; -; 2.265 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.428 ns ; 2.163 ns ; -; 2.273 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.492 ns ; 2.219 ns ; -; 2.298 ns ; 189.50 MHz ( period = 5.277 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.901 ns ; 4.603 ns ; -; 2.325 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.991 ns ; -; 2.338 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.383 ns ; 3.045 ns ; -; 2.357 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.321 ns ; 2.964 ns ; -; 2.370 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.302 ns ; 2.932 ns ; -; 2.376 ns ; 192.34 MHz ( period = 5.199 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.883 ns ; 4.507 ns ; -; 2.385 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 3.250 ns ; -; 2.410 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.906 ns ; -; 2.417 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.307 ns ; 2.890 ns ; -; 2.434 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.373 ns ; 2.939 ns ; -; 2.445 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.495 ns ; 2.050 ns ; -; 2.447 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 2.865 ns ; -; 2.470 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.175 ns ; -; 2.502 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.652 ns ; 3.150 ns ; -; 2.509 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 3.134 ns ; -; 2.516 ns ; 197.67 MHz ( period = 5.059 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.725 ns ; -; 2.517 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.308 ns ; 2.791 ns ; -; 2.520 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 2.773 ns ; -; 2.523 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.122 ns ; -; 2.531 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 3.108 ns ; -; 2.548 ns ; 198.93 MHz ( period = 5.027 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.248 ns ; 4.700 ns ; -; 2.549 ns ; 198.97 MHz ( period = 5.026 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.878 ns ; 4.329 ns ; -; 2.550 ns ; 199.00 MHz ( period = 5.025 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.901 ns ; 4.351 ns ; -; 2.550 ns ; 199.00 MHz ( period = 5.025 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.239 ns ; 4.689 ns ; -; 2.561 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 2.814 ns ; -; 2.567 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.290 ns ; 2.723 ns ; -; 2.569 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.317 ns ; 2.748 ns ; -; 2.569 ns ; 199.76 MHz ( period = 5.006 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.231 ns ; 4.662 ns ; -; 2.570 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 2.805 ns ; -; 2.571 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 3.072 ns ; -; 2.572 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.306 ns ; 2.734 ns ; -; 2.597 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.719 ns ; -; 2.603 ns ; 201.13 MHz ( period = 4.972 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.638 ns ; -; 2.614 ns ; 201.57 MHz ( period = 4.961 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.239 ns ; 4.625 ns ; -; 2.616 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.377 ns ; 2.761 ns ; -; 2.622 ns ; 201.90 MHz ( period = 4.953 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 4.325 ns ; -; 2.641 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 3.004 ns ; -; 2.685 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.330 ns ; 2.645 ns ; -; 2.690 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.949 ns ; -; 2.695 ns ; 204.92 MHz ( period = 4.880 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.254 ns ; -; 2.697 ns ; 205.00 MHz ( period = 4.878 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.529 ns ; -; 2.708 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.648 ns ; 2.940 ns ; -; 2.716 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.312 ns ; 2.596 ns ; -; 2.717 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.913 ns ; -; 2.718 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.912 ns ; -; 2.724 ns ; 206.14 MHz ( period = 4.851 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.241 ns ; 4.517 ns ; -; 2.733 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.356 ns ; 2.623 ns ; -; 2.734 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.911 ns ; -; 2.734 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.381 ns ; 2.647 ns ; -; 2.734 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 4.735 ns ; 4.559 ns ; 1.825 ns ; -; 2.751 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.377 ns ; 2.626 ns ; -; 2.758 ns ; 207.60 MHz ( period = 4.817 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.244 ns ; 4.486 ns ; -; 2.761 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.874 ns ; -; 2.761 ns ; 207.73 MHz ( period = 4.814 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.188 ns ; -; 2.764 ns ; 207.86 MHz ( period = 4.811 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 4.185 ns ; -; 2.768 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.652 ns ; 2.884 ns ; -; 2.771 ns ; 208.16 MHz ( period = 4.804 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.235 ns ; 4.464 ns ; -; 2.776 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 2.867 ns ; -; 2.778 ns ; 208.46 MHz ( period = 4.797 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.948 ns ; 4.170 ns ; -; 2.780 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.855 ns ; -; 2.793 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.852 ns ; -; 2.793 ns ; 209.12 MHz ( period = 4.782 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.433 ns ; -; 2.797 ns ; 209.29 MHz ( period = 4.778 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.226 ns ; 4.429 ns ; -; 2.798 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.378 ns ; 2.580 ns ; -; 2.807 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.779 ns ; 2.972 ns ; -; 2.808 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.374 ns ; 2.566 ns ; -; 2.815 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.373 ns ; 2.558 ns ; -; 2.821 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.818 ns ; -; 2.838 ns ; 211.10 MHz ( period = 4.737 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.231 ns ; 4.393 ns ; -; 2.839 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.643 ns ; 2.804 ns ; -; 2.846 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.293 ns ; 2.447 ns ; -; 2.851 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.334 ns ; 2.483 ns ; -; 2.862 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.316 ns ; 2.454 ns ; -; 2.909 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.645 ns ; 2.736 ns ; -; 2.935 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.423 ns ; -; 2.937 ns ; 215.61 MHz ( period = 4.638 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 4.006 ns ; -; 2.951 ns ; 216.26 MHz ( period = 4.624 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.949 ns ; 3.998 ns ; -; 2.954 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.639 ns ; 2.685 ns ; -; 2.960 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.655 ns ; 2.695 ns ; -; 2.963 ns ; 216.83 MHz ( period = 4.612 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 3.980 ns ; -; 2.969 ns ; 217.11 MHz ( period = 4.606 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.978 ns ; -; 2.977 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.648 ns ; 2.671 ns ; -; 2.983 ns ; 217.77 MHz ( period = 4.592 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.235 ns ; 4.252 ns ; -; 2.984 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.646 ns ; -; 2.985 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.645 ns ; -; 2.988 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.779 ns ; 2.791 ns ; -; 3.004 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 2.358 ns ; -; 3.005 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.364 ns ; 2.359 ns ; -; 3.010 ns ; 219.06 MHz ( period = 4.565 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.292 ns ; 4.282 ns ; -; 3.018 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.653 ns ; 2.635 ns ; -; 3.027 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.635 ns ; 2.608 ns ; -; 3.042 ns ; 220.60 MHz ( period = 4.533 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.294 ns ; 4.252 ns ; -; 3.047 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.729 ns ; 2.682 ns ; -; 3.051 ns ; 221.04 MHz ( period = 4.524 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.249 ns ; 4.198 ns ; -; 3.058 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.354 ns ; 2.296 ns ; -; 3.061 ns ; 221.53 MHz ( period = 4.514 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.249 ns ; 4.188 ns ; -; 3.074 ns ; 222.17 MHz ( period = 4.501 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.946 ns ; 3.872 ns ; -; 3.096 ns ; 223.26 MHz ( period = 4.479 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.851 ns ; -; 3.115 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.246 ns ; -; 3.127 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.234 ns ; -; 3.131 ns ; 225.02 MHz ( period = 4.444 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.943 ns ; 3.812 ns ; -; 3.141 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.325 ns ; 2.184 ns ; -; 3.143 ns ; 225.63 MHz ( period = 4.432 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 4.152 ns ; -; 3.151 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.479 ns ; -; 3.158 ns ; 226.40 MHz ( period = 4.417 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.292 ns ; 4.134 ns ; -; 3.159 ns ; 226.45 MHz ( period = 4.416 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.132 ns ; -; 3.162 ns ; 226.60 MHz ( period = 4.413 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 4.133 ns ; -; 3.163 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.780 ns ; 2.617 ns ; -; 3.173 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.680 ns ; 2.507 ns ; -; 3.181 ns ; 227.58 MHz ( period = 4.394 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.944 ns ; 3.763 ns ; -; 3.192 ns ; 228.15 MHz ( period = 4.383 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.947 ns ; 3.755 ns ; -; 3.199 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.630 ns ; 2.431 ns ; -; 3.207 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.671 ns ; 2.464 ns ; -; 3.208 ns ; 228.99 MHz ( period = 4.367 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.946 ns ; 3.738 ns ; -; 3.209 ns ; 229.04 MHz ( period = 4.366 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 6.944 ns ; 3.735 ns ; -; 3.225 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.470 ns ; -; 3.226 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.655 ns ; 2.429 ns ; -; 3.233 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 2.126 ns ; -; 3.236 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 2.125 ns ; -; 3.251 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.107 ns ; -; 3.253 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.355 ns ; 2.102 ns ; -; 3.261 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 2.097 ns ; -; 3.262 ns ; 231.86 MHz ( period = 4.313 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 4.035 ns ; -; 3.263 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.363 ns ; 2.100 ns ; -; 3.266 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.363 ns ; 2.097 ns ; -; 3.271 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 2.091 ns ; -; 3.277 ns ; 232.67 MHz ( period = 4.298 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.014 ns ; -; 3.279 ns ; 232.77 MHz ( period = 4.296 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.291 ns ; 4.012 ns ; -; 3.282 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.653 ns ; 2.371 ns ; -; 3.307 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.383 ns ; 2.076 ns ; -; 3.346 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.352 ns ; -; 3.351 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.344 ns ; -; 3.365 ns ; 237.53 MHz ( period = 4.210 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.296 ns ; 3.931 ns ; -; 3.387 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 1.974 ns ; -; 3.390 ns ; 238.95 MHz ( period = 4.185 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.294 ns ; 3.904 ns ; -; 3.410 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.362 ns ; 1.952 ns ; -; 3.415 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.283 ns ; -; 3.429 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.358 ns ; 1.929 ns ; -; 3.438 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.375 ns ; 1.937 ns ; -; 3.450 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.700 ns ; 2.250 ns ; -; 3.458 ns ; 242.90 MHz ( period = 4.117 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 3.837 ns ; -; 3.459 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.239 ns ; -; 3.461 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.781 ns ; 2.320 ns ; -; 3.474 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.380 ns ; 1.906 ns ; -; 3.477 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 1.882 ns ; -; 3.492 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.695 ns ; 2.203 ns ; -; 3.495 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.700 ns ; 2.205 ns ; -; 3.499 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.359 ns ; 1.860 ns ; -; 3.504 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.361 ns ; 1.857 ns ; -; 3.558 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.141 ns ; -; 3.575 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 2.122 ns ; -; 3.602 ns ; 251.70 MHz ( period = 3.973 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.295 ns ; 3.693 ns ; -; 3.610 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.089 ns ; -; 3.614 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.698 ns ; 2.084 ns ; -; 3.616 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.701 ns ; 2.085 ns ; -; 3.617 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.696 ns ; 2.079 ns ; -; 3.620 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 2.077 ns ; -; 3.625 ns ; 253.16 MHz ( period = 3.950 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 3.672 ns ; -; 3.640 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.059 ns ; -; 3.649 ns ; None ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.997 ns ; 5.726 ns ; 2.077 ns ; -; 3.657 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.042 ns ; -; 3.663 ns ; 255.62 MHz ( period = 3.912 ns ) ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 7.575 ns ; 7.297 ns ; 3.634 ns ; -; 3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.696 ns ; 2.032 ns ; -; 3.673 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.703 ns ; 2.030 ns ; -; 3.675 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 2.024 ns ; -; 3.708 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.702 ns ; 1.994 ns ; -; 3.720 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.703 ns ; 1.983 ns ; -; 3.738 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.697 ns ; 1.959 ns ; -; 3.825 ns ; None ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 5.999 ns ; 5.699 ns ; 1.874 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; -1.712 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 1.118 ns ; 2.830 ns ; -; -1.664 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.656 ns ; -; -1.597 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.589 ns ; -; -1.597 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.992 ns ; 2.589 ns ; -; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; -; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; -; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; -; -1.358 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.985 ns ; 2.343 ns ; -; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; -; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; -; -1.354 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.987 ns ; 2.341 ns ; -; -1.333 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.319 ns ; -; -1.333 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.319 ns ; -; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; -; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; -; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; -; -1.280 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.266 ns ; -; -1.278 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.264 ns ; -; -1.278 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.986 ns ; 2.264 ns ; -; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; -; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; -; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; -; -1.250 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.238 ns ; -; -1.248 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.989 ns ; 2.237 ns ; -; -1.243 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.989 ns ; 2.232 ns ; -; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; -; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; -; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; -; -1.228 ns ; None ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 1.576 ns ; 0.988 ns ; 2.216 ns ; -; 4.485 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 6.311 ns ; 6.117 ns ; 1.632 ns ; -; 6.612 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.393 ns ; 3.781 ns ; -; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; -; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; -; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; -; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; -; 6.644 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.392 ns ; 3.748 ns ; -; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; -; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; -; 6.665 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.873 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.672 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.527 ns ; 3.855 ns ; -; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; -; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; -; 6.685 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.852 ns ; -; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; -; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; -; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; -; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; -; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; -; 6.727 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.811 ns ; -; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; -; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; -; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; -; 6.788 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.234 ns ; 3.446 ns ; -; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; -; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; -; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; -; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; -; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; -; 6.826 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.568 ns ; -; 6.843 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.545 ns ; 3.702 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.845 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.549 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.849 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.394 ns ; 3.545 ns ; -; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; -; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; -; 6.955 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.564 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 6.969 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.519 ns ; 3.550 ns ; -; 7.011 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.390 ns ; 3.379 ns ; -; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; -; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; -; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; -; 7.016 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.546 ns ; 3.530 ns ; -; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; -; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; -; 7.074 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.537 ns ; 3.463 ns ; -; 7.111 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.514 ns ; 3.403 ns ; -; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; -; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; -; 7.123 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.364 ns ; 3.241 ns ; -; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; -; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; -; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; -; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; -; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; -; 7.147 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.656 ns ; 3.509 ns ; -; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; -; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; -; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; -; 7.184 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.391 ns ; 3.207 ns ; -; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; -; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; -; 7.242 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.382 ns ; 3.140 ns ; -; 7.264 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.548 ns ; 3.284 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.286 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.252 ns ; -; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; -; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; -; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; -; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; -; 7.296 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.251 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.297 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.361 ns ; -; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; -; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; -; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; -; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; -; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; -; 7.298 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.547 ns ; 3.249 ns ; -; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; -; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; -; 7.323 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.539 ns ; 3.216 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.334 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.324 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.380 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.658 ns ; 3.278 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.411 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.538 ns ; 3.127 ns ; -; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; -; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; -; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; -; 7.440 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.389 ns ; 2.949 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.448 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.549 ns ; 3.101 ns ; -; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; -; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; -; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; -; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; -; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; -; 7.454 ns ; None ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 10.267 ns ; 10.383 ns ; 2.929 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ -; -4.294 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.607 ns ; 3.687 ns ; -; -4.252 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.600 ns ; 3.652 ns ; -; -4.247 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.642 ns ; -; -4.241 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.594 ns ; 3.647 ns ; -; -4.232 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.635 ns ; -; -4.228 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.631 ns ; -; -4.220 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.607 ns ; 3.613 ns ; -; -4.212 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.610 ns ; -; -4.205 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.597 ns ; 3.608 ns ; -; -4.158 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.898 ns ; -; -4.119 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.141 ns ; -; -4.119 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.517 ns ; -; -4.092 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.114 ns ; -; -4.088 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.486 ns ; -; -4.086 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.595 ns ; 3.491 ns ; -; -4.085 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.593 ns ; 3.492 ns ; -; -4.073 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.468 ns ; -; -4.070 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.465 ns ; -; -4.070 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.466 ns ; -; -4.065 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.461 ns ; -; -4.060 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.458 ns ; -; -4.057 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.455 ns ; -; -4.051 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.447 ns ; -; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.447 ns ; -; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.447 ns ; -; -4.049 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.445 ns ; -; -4.048 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 4.068 ns ; -; -4.046 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.444 ns ; -; -4.045 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.441 ns ; -; -4.045 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.441 ns ; -; -4.043 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.441 ns ; -; -4.042 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 4.063 ns ; -; -4.042 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.440 ns ; -; -4.040 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.436 ns ; -; -4.039 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.434 ns ; -; -4.039 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.435 ns ; -; -4.036 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.431 ns ; -; -4.035 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.433 ns ; -; -4.032 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.428 ns ; -; -4.032 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.428 ns ; -; -4.030 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.610 ns ; 3.420 ns ; -; -4.027 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.426 ns ; -; -3.997 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.595 ns ; 3.402 ns ; -; -3.995 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.598 ns ; 3.397 ns ; -; -3.987 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 4.008 ns ; -; -3.985 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.725 ns ; -; -3.984 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.379 ns ; -; -3.980 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 4.002 ns ; -; -3.978 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.376 ns ; -; -3.977 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.603 ns ; 3.374 ns ; -; -3.976 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.374 ns ; -; -3.973 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.372 ns ; -; -3.972 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.370 ns ; -; -3.972 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.601 ns ; 3.371 ns ; -; -3.969 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.365 ns ; -; -3.968 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.366 ns ; -; -3.968 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.364 ns ; -; -3.967 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.363 ns ; -; -3.958 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.356 ns ; -; -3.957 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.355 ns ; -; -3.956 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.354 ns ; -; -3.952 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.347 ns ; -; -3.950 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.972 ns ; -; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.970 ns ; -; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.343 ns ; -; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.346 ns ; -; -3.948 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.346 ns ; -; -3.947 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.345 ns ; -; -3.947 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.345 ns ; -; -3.946 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.344 ns ; -; -3.945 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.343 ns ; -; -3.943 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.341 ns ; -; -3.943 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.341 ns ; -; -3.941 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.339 ns ; -; -3.941 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.339 ns ; -; -3.938 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.960 ns ; -; -3.938 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.334 ns ; -; -3.937 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.332 ns ; -; -3.935 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.333 ns ; -; -3.935 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.333 ns ; -; -3.934 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.329 ns ; -; -3.934 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.330 ns ; -; -3.932 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.330 ns ; -; -3.932 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.327 ns ; -; -3.930 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.328 ns ; -; -3.927 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.325 ns ; -; -3.926 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.324 ns ; -; -3.925 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.323 ns ; -; -3.924 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.319 ns ; -; -3.922 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.944 ns ; -; -3.920 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.316 ns ; -; -3.915 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.310 ns ; -; -3.909 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.929 ns ; -; -3.908 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.928 ns ; -; -3.898 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.919 ns ; -; -3.896 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.292 ns ; -; -3.894 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.916 ns ; -; -3.882 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.904 ns ; -; -3.878 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.899 ns ; -; -3.874 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.614 ns ; -; -3.873 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.269 ns ; -; -3.869 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.257 ns ; -; -3.867 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.887 ns ; -; -3.867 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.303 ns ; 3.564 ns ; -; -3.858 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.610 ns ; 3.248 ns ; -; -3.854 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.876 ns ; -; -3.851 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.591 ns ; -; -3.835 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.855 ns ; -; -3.833 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.551 ns ; -; -3.828 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.850 ns ; -; -3.827 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.847 ns ; -; -3.822 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.540 ns ; -; -3.821 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.291 ns ; 3.530 ns ; -; -3.819 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.303 ns ; 3.516 ns ; -; -3.818 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.216 ns ; -; -3.817 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.838 ns ; -; -3.816 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.211 ns ; -; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; -; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; -; -3.814 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.212 ns ; -; -3.813 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.211 ns ; -; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.210 ns ; -; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.208 ns ; -; -3.812 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.208 ns ; -; -3.809 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.204 ns ; -; -3.809 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.205 ns ; -; -3.807 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.205 ns ; -; -3.806 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.202 ns ; -; -3.804 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.199 ns ; -; -3.803 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.191 ns ; -; -3.792 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.190 ns ; -; -3.792 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.190 ns ; -; -3.792 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.295 ns ; 3.497 ns ; -; -3.788 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.186 ns ; -; -3.787 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.505 ns ; -; -3.783 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.171 ns ; -; -3.781 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.176 ns ; -; -3.780 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.802 ns ; -; -3.779 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.519 ns ; -; -3.777 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.615 ns ; 3.162 ns ; -; -3.777 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.495 ns ; -; -3.776 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.796 ns ; -; -3.771 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.793 ns ; -; -3.767 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.507 ns ; -; -3.762 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.480 ns ; -; -3.757 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.779 ns ; -; -3.748 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.015 ns ; 3.763 ns ; -; -3.747 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.291 ns ; 3.456 ns ; -; -3.747 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.015 ns ; 3.762 ns ; -; -3.743 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.014 ns ; 3.757 ns ; -; -3.728 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.292 ns ; 3.436 ns ; -; -3.724 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.442 ns ; -; -3.724 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.442 ns ; -; -3.720 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.013 ns ; 3.733 ns ; -; -3.717 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.294 ns ; 3.423 ns ; -; -3.713 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.617 ns ; 3.096 ns ; -; -3.713 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.622 ns ; 3.091 ns ; -; -3.713 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.734 ns ; -; -3.703 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.292 ns ; 3.411 ns ; -; -3.698 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.438 ns ; -; -3.695 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.093 ns ; -; -3.694 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.092 ns ; -; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.091 ns ; -; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.091 ns ; -; -3.693 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.089 ns ; -; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; -; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; -; -3.691 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.089 ns ; -; -3.690 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.088 ns ; -; -3.690 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.085 ns ; -; -3.688 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.084 ns ; -; -3.685 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.080 ns ; -; -3.685 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.403 ns ; -; -3.684 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.080 ns ; -; -3.683 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.020 ns ; 3.703 ns ; -; -3.679 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.260 ns ; 3.419 ns ; -; -3.677 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.075 ns ; -; -3.677 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.022 ns ; 3.699 ns ; -; -3.675 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.073 ns ; -; -3.674 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.392 ns ; -; -3.672 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.070 ns ; -; -3.670 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.068 ns ; -; -3.668 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.617 ns ; 3.051 ns ; -; -3.668 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.289 ns ; 3.379 ns ; -; -3.667 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.602 ns ; 3.065 ns ; -; -3.665 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.061 ns ; -; -3.665 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.061 ns ; -; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.060 ns ; -; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.059 ns ; -; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.059 ns ; -; -3.664 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.060 ns ; -; -3.663 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.058 ns ; -; -3.663 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.604 ns ; 3.059 ns ; -; -3.662 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.057 ns ; -; -3.661 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.056 ns ; -; -3.660 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.605 ns ; 3.055 ns ; -; -3.651 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.282 ns ; 3.369 ns ; -; -3.649 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.612 ns ; 3.037 ns ; -; -3.645 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; 0.021 ns ; 3.666 ns ; -; -3.633 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.272 ns ; -0.614 ns ; 3.019 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------------------+---------------------------+-------------------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'CLK33M' ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ -; -5.966 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.279 ns ; 3.687 ns ; -; -5.924 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[95] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.272 ns ; 3.652 ns ; -; -5.919 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.642 ns ; -; -5.913 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[90] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.266 ns ; 3.647 ns ; -; -5.904 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.635 ns ; -; -5.900 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.631 ns ; -; -5.892 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[34] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.279 ns ; 3.613 ns ; -; -5.884 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.610 ns ; -; -5.877 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[57] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.269 ns ; 3.608 ns ; -; -5.830 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.898 ns ; -; -5.791 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.141 ns ; -; -5.791 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.517 ns ; -; -5.764 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.114 ns ; -; -5.760 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[111] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.486 ns ; -; -5.758 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[84] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.267 ns ; 3.491 ns ; -; -5.757 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.265 ns ; 3.492 ns ; -; -5.745 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[85] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.468 ns ; -; -5.742 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[60] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.465 ns ; -; -5.742 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[48] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.466 ns ; -; -5.737 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.461 ns ; -; -5.732 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[97] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.458 ns ; -; -5.729 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.455 ns ; -; -5.723 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[83] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.447 ns ; -; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.447 ns ; -; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.447 ns ; -; -5.721 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[41] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.445 ns ; -; -5.720 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 4.068 ns ; -; -5.718 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[108] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.444 ns ; -; -5.717 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[78] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.441 ns ; -; -5.717 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[59] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.441 ns ; -; -5.715 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.441 ns ; -; -5.714 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 4.063 ns ; -; -5.714 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.440 ns ; -; -5.712 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[72] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.436 ns ; -; -5.711 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[70] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.434 ns ; -; -5.711 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.435 ns ; -; -5.708 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[38] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.431 ns ; -; -5.707 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[112] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.433 ns ; -; -5.704 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[75] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.428 ns ; -; -5.704 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.428 ns ; -; -5.702 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.282 ns ; 3.420 ns ; -; -5.699 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[46] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.426 ns ; -; -5.669 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[92] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.267 ns ; 3.402 ns ; -; -5.667 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.270 ns ; 3.397 ns ; -; -5.659 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 4.008 ns ; -; -5.657 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.725 ns ; -; -5.656 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.379 ns ; -; -5.652 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 4.002 ns ; -; -5.650 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[80] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.376 ns ; -; -5.649 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.275 ns ; 3.374 ns ; -; -5.648 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[124] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.374 ns ; -; -5.645 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[104] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.372 ns ; -; -5.644 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[91] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.370 ns ; -; -5.644 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.273 ns ; 3.371 ns ; -; -5.641 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[58] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.365 ns ; -; -5.640 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.366 ns ; -; -5.640 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.364 ns ; -; -5.639 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[47] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.363 ns ; -; -5.630 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.356 ns ; -; -5.629 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.355 ns ; -; -5.628 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.354 ns ; -; -5.624 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[69] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.347 ns ; -; -5.622 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.972 ns ; -; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.970 ns ; -; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[54] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.343 ns ; -; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[68] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.346 ns ; -; -5.620 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[113] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.346 ns ; -; -5.619 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.345 ns ; -; -5.619 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[106] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.345 ns ; -; -5.618 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.344 ns ; -; -5.617 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.343 ns ; -; -5.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[116] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.341 ns ; -; -5.615 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[127] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.341 ns ; -; -5.613 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[125] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.339 ns ; -; -5.613 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.339 ns ; -; -5.610 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.960 ns ; -; -5.610 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[51] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.334 ns ; -; -5.609 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[61] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.332 ns ; -; -5.607 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[122] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.333 ns ; -; -5.607 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[98] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.333 ns ; -; -5.606 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.329 ns ; -; -5.606 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.330 ns ; -; -5.604 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[109] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.330 ns ; -; -5.604 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[118] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.327 ns ; -; -5.602 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.328 ns ; -; -5.599 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.325 ns ; -; -5.598 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[105] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.324 ns ; -; -5.597 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.323 ns ; -; -5.596 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[53] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.319 ns ; -; -5.594 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.944 ns ; -; -5.592 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.316 ns ; -; -5.587 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[55] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.310 ns ; -; -5.581 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.929 ns ; -; -5.580 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.928 ns ; -; -5.570 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.919 ns ; -; -5.568 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.292 ns ; -; -5.566 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.916 ns ; -; -5.554 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.904 ns ; -; -5.550 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.899 ns ; -; -5.546 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.614 ns ; -; -5.545 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.269 ns ; -; -5.541 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.257 ns ; -; -5.539 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.887 ns ; -; -5.539 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.975 ns ; 3.564 ns ; -; -5.530 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.282 ns ; 3.248 ns ; -; -5.526 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.876 ns ; -; -5.523 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.591 ns ; -; -5.507 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.855 ns ; -; -5.505 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.551 ns ; -; -5.500 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.850 ns ; -; -5.499 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.847 ns ; -; -5.494 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.540 ns ; -; -5.493 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.963 ns ; 3.530 ns ; -; -5.491 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.975 ns ; 3.516 ns ; -; -5.490 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[89] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.216 ns ; -; -5.489 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.838 ns ; -; -5.488 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.211 ns ; -; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; -; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[100] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; -; -5.486 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[71] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.212 ns ; -; -5.485 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[39] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.211 ns ; -; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[121] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.210 ns ; -; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.208 ns ; -; -5.484 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.208 ns ; -; -5.481 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[123] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.204 ns ; -; -5.481 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[120] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.205 ns ; -; -5.479 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[126] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.205 ns ; -; -5.478 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.202 ns ; -; -5.476 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[117] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.199 ns ; -; -5.475 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.191 ns ; -; -5.464 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[74] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.190 ns ; -; -5.464 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[44] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.190 ns ; -; -5.464 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.967 ns ; 3.497 ns ; -; -5.460 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[64] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.186 ns ; -; -5.459 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.505 ns ; -; -5.455 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.171 ns ; -; -5.453 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.176 ns ; -; -5.452 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.802 ns ; -; -5.451 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.519 ns ; -; -5.449 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.287 ns ; 3.162 ns ; -; -5.449 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.495 ns ; -; -5.448 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.796 ns ; -; -5.443 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.793 ns ; -; -5.439 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.507 ns ; -; -5.434 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.480 ns ; -; -5.429 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.779 ns ; -; -5.420 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.657 ns ; 3.763 ns ; -; -5.419 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.963 ns ; 3.456 ns ; -; -5.419 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.657 ns ; 3.762 ns ; -; -5.415 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.658 ns ; 3.757 ns ; -; -5.400 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.964 ns ; 3.436 ns ; -; -5.396 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.442 ns ; -; -5.396 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.442 ns ; -; -5.392 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.659 ns ; 3.733 ns ; -; -5.389 ns ; None ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[110] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.966 ns ; 3.423 ns ; -; -5.385 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.289 ns ; 3.096 ns ; -; -5.385 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.294 ns ; 3.091 ns ; -; -5.385 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.734 ns ; -; -5.375 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.964 ns ; 3.411 ns ; -; -5.370 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.438 ns ; -; -5.367 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[79] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.093 ns ; -; -5.366 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[32] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.092 ns ; -; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[73] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.091 ns ; -; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[119] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.091 ns ; -; -5.365 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.089 ns ; -; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; -; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[63] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; -; -5.363 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.089 ns ; -; -5.362 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[93] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.088 ns ; -; -5.362 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[115] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.085 ns ; -; -5.360 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[56] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.084 ns ; -; -5.357 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[102] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.080 ns ; -; -5.357 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.403 ns ; -; -5.356 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.080 ns ; -; -5.355 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.652 ns ; 3.703 ns ; -; -5.351 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.932 ns ; 3.419 ns ; -; -5.349 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[76] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.075 ns ; -; -5.349 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.650 ns ; 3.699 ns ; -; -5.347 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[62] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.073 ns ; -; -5.346 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.392 ns ; -; -5.344 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[52] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.070 ns ; -; -5.342 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[66] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.068 ns ; -; -5.340 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.289 ns ; 3.051 ns ; -; -5.340 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.961 ns ; 3.379 ns ; -; -5.339 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.274 ns ; 3.065 ns ; -; -5.337 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.061 ns ; -; -5.337 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.061 ns ; -; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[94] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.060 ns ; -; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.059 ns ; -; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.059 ns ; -; -5.336 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.060 ns ; -; -5.335 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.058 ns ; -; -5.335 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.276 ns ; 3.059 ns ; -; -5.334 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.057 ns ; -; -5.333 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.056 ns ; -; -5.332 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~portb_address_reg0 ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[101] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.277 ns ; 3.055 ns ; -; -5.323 ns ; None ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.954 ns ; 3.369 ns ; -; -5.321 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.284 ns ; 3.037 ns ; -; -5.317 ns ; None ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_omb:rd_ptr_msb|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -1.651 ns ; 3.666 ns ; -; -5.305 ns ; None ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; CLK33M ; 0.196 ns ; -2.286 ns ; 3.019 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Setup: 'MAIN_CLK' ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ -; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ -; -4.261 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.318 ns ; -; -4.260 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a8 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.317 ns ; -; -4.258 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.315 ns ; -; -4.239 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 4.296 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.204 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|q_b[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.122 ns ; 4.326 ns ; -; -4.071 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~portb_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.225 ns ; 4.296 ns ; -; -4.023 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.012 ns ; 4.035 ns ; -; -4.023 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.012 ns ; 4.035 ns ; -; -3.979 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.272 ns ; 4.251 ns ; -; -3.910 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.967 ns ; -; -3.907 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.964 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|sub_parity7a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|parity6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.784 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdptr_g[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.055 ns ; 3.839 ns ; -; -3.546 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.603 ns ; -; -3.544 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_lsb_aeb ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.057 ns ; 3.601 ns ; -; -3.541 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.096 ns ; 3.637 ns ; -; -3.426 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|rdemp_eq_comp_msb_aeb ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; -0.013 ns ; 3.413 ns ; -; -3.055 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.360 ns ; 3.415 ns ; -; -3.039 ns ; None ; FB_ALE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WRF_WRE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; -0.013 ns ; 3.026 ns ; -; -2.598 ns ; None ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; MAIN_CLK ; 1.094 ns ; 0.205 ns ; 2.803 ns ; -; -2.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.530 ns ; -; -2.463 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.530 ns ; -; -2.375 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 7.143 ns ; -; -2.355 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.341 ns ; -; -2.320 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.304 ns ; -; -2.317 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.384 ns ; -; -2.317 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.384 ns ; -; -2.290 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 7.056 ns ; -; -2.250 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.317 ns ; -; -2.250 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.067 ns ; 6.317 ns ; -; -2.246 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 6.245 ns ; -; -2.239 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.307 ns ; -; -2.239 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.307 ns ; -; -2.229 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.997 ns ; -; -2.209 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.195 ns ; -; -2.199 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.317 ns ; -; -2.199 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.317 ns ; -; -2.183 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.129 ns ; 6.312 ns ; -; -2.177 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.390 ns ; -; -2.177 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.390 ns ; -; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.769 ns ; 6.920 ns ; -; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.270 ns ; -; -2.151 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.270 ns ; -; -2.147 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.265 ns ; -; -2.147 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.265 ns ; -; -2.146 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.120 ns ; 6.266 ns ; -; -2.146 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.120 ns ; 6.266 ns ; -; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.260 ns ; -; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.261 ns ; -; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.118 ns ; 6.260 ns ; -; -2.142 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.261 ns ; -; -2.139 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 6.905 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.135 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.957 ns ; -; -2.133 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.986 ns ; 6.119 ns ; -; -2.132 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.116 ns ; -; -2.131 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.987 ns ; 6.118 ns ; -; -2.129 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.248 ns ; -; -2.129 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.248 ns ; -; -2.122 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.187 ns ; -; -2.122 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.187 ns ; -; -2.118 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.186 ns ; -; -2.118 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.068 ns ; 6.186 ns ; -; -2.100 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 6.099 ns ; -; -2.098 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.215 ns ; -; -2.098 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.215 ns ; -; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.159 ns ; -; -2.094 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.065 ns ; 6.159 ns ; -; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; -; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; -; -2.084 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|shift_reg[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.238 ns ; 6.322 ns ; -; -2.083 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.620 ns ; -; -2.062 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.830 ns ; -; -2.060 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.768 ns ; 6.828 ns ; -; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; -; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; -; -2.048 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_X_D[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.176 ns ; 6.224 ns ; -; -2.045 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.766 ns ; 6.811 ns ; -; -2.045 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_USART_TOP:I_USART|WF68901IP_USART_TX:I_USART_TRANSMIT|UE ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.701 ns ; 5.746 ns ; -; -2.037 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_BASE_M_D[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.129 ns ; 6.166 ns ; -; -2.035 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.573 ns ; -; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[3][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; -; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[4][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; -; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; interrupt_handler:nobody|WERTE[5][19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.251 ns ; 6.284 ns ; -; -2.033 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 6.017 ns ; -; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.568 ns ; -; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.244 ns ; -; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_TOP[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.213 ns ; 6.244 ns ; -; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.144 ns ; -; -2.031 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.144 ns ; -; -2.030 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_TA ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.769 ns ; 6.799 ns ; -; -2.030 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.539 ns ; 6.569 ns ; -; -2.026 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.537 ns ; 6.563 ns ; -; -2.026 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.564 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.000 ns ; 6.022 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.022 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.841 ns ; -; -2.013 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.538 ns ; 6.551 ns ; -; -2.010 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.987 ns ; 5.997 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.005 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.819 ns ; 5.824 ns ; -; -2.002 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.986 ns ; -; -2.001 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.985 ns ; -; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; -; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; -; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; -; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|VECT_NUMBER[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.013 ns ; 6.011 ns ; -; -1.998 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|FREQUENCY_B[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.999 ns ; 5.997 ns ; -; -1.997 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_CTRL_STATUS:I_UART_CTRL_STATUS|IRQn ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.984 ns ; 5.981 ns ; -; -1.996 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.064 ns ; 6.060 ns ; -; -1.996 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_LOW[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.064 ns ; 6.060 ns ; -; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.106 ns ; -; -1.993 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.113 ns ; 6.106 ns ; -; -1.991 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.050 ns ; 6.041 ns ; -; -1.991 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.050 ns ; 6.041 ns ; -; -1.990 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.109 ns ; -; -1.990 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.119 ns ; 6.109 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.106 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 4.117 ns ; 6.106 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; -1.989 ns ; None ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_BYT_CNT[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; MAIN_CLK ; 4.884 ns ; 3.822 ns ; 5.811 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+----------+-----------------------------+---------------------------+-------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' ; -+---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 0.825 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.783 ns ; -; 0.827 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.785 ns ; -; 0.827 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.785 ns ; -; 0.828 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.786 ns ; -; 0.828 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.786 ns ; -; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; -; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; -; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; -; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; -; 0.829 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.787 ns ; -; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; -; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; -; 0.830 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; -; 0.831 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.789 ns ; -; 0.831 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.789 ns ; -; 0.832 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.790 ns ; -; 0.833 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.791 ns ; -; 1.185 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.143 ns ; -; 1.353 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.311 ns ; -; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.312 ns ; -; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.311 ns ; -; 1.354 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.312 ns ; -; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; -; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; -; 1.356 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.314 ns ; -; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; -; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; -; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; -; 1.357 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; -; 1.358 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.316 ns ; -; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; -; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; -; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; -; 1.359 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.317 ns ; -; 1.411 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.369 ns ; -; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.370 ns ; -; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.369 ns ; -; 1.412 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.370 ns ; -; 1.414 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.372 ns ; -; 1.414 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.372 ns ; -; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; -; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; -; 1.415 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; -; 1.416 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.374 ns ; -; 1.416 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.373 ns ; -; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; -; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; -; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; -; 1.417 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.375 ns ; -; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.428 ns ; -; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.427 ns ; -; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.427 ns ; -; 1.470 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.428 ns ; -; 1.472 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.430 ns ; -; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; -; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; -; 1.473 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; -; 1.474 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.432 ns ; -; 1.474 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.431 ns ; -; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; -; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; -; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; -; 1.475 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.433 ns ; -; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.486 ns ; -; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.485 ns ; -; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.485 ns ; -; 1.528 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.486 ns ; -; 1.530 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.488 ns ; -; 1.531 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; -; 1.531 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; -; 1.532 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.489 ns ; -; 1.532 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.489 ns ; -; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; -; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; -; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; -; 1.533 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.491 ns ; -; 1.586 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.543 ns ; -; 1.586 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.543 ns ; -; 1.587 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.544 ns ; -; 1.588 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.546 ns ; -; 1.589 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.547 ns ; -; 1.589 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.547 ns ; -; 1.590 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.547 ns ; -; 1.590 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.547 ns ; -; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; -; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; -; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; -; 1.591 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.549 ns ; -; 1.644 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.601 ns ; -; 1.644 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.601 ns ; -; 1.645 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.602 ns ; -; 1.646 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.604 ns ; -; 1.647 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.605 ns ; -; 1.648 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.605 ns ; -; 1.648 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.605 ns ; -; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; -; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; -; 1.649 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.607 ns ; -; 1.650 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.607 ns ; -; 1.689 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.647 ns ; -; 1.702 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.659 ns ; -; 1.702 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.659 ns ; -; 1.703 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.660 ns ; -; 1.704 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.662 ns ; -; 1.706 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.663 ns ; -; 1.706 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.663 ns ; -; 1.707 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.665 ns ; -; 1.707 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.665 ns ; -; 1.708 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.665 ns ; -; 1.708 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.665 ns ; -; 1.743 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.701 ns ; -; 1.760 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.717 ns ; -; 1.760 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.717 ns ; -; 1.761 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.718 ns ; -; 1.764 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.721 ns ; -; 1.764 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.721 ns ; -; 1.765 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.723 ns ; -; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; -; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; -; 1.766 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.723 ns ; -; 1.801 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.759 ns ; -; 1.818 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.775 ns ; -; 1.819 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.776 ns ; -; 1.822 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.779 ns ; -; 1.822 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.779 ns ; -; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; -; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; -; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; -; 1.824 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.781 ns ; -; 1.861 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.819 ns ; -; 1.876 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.833 ns ; -; 1.877 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.834 ns ; -; 1.880 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.837 ns ; -; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; -; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; -; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; -; 1.882 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.839 ns ; -; 1.915 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.873 ns ; -; 1.935 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.892 ns ; -; 1.938 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.895 ns ; -; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; -; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; -; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; -; 1.940 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.897 ns ; -; 1.976 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[11] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.934 ns ; -; 1.993 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.950 ns ; -; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; -; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; -; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; -; 1.998 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[12] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.955 ns ; -; 2.034 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.992 ns ; -; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; -; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; -; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; -; 2.056 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[13] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.013 ns ; -; 2.091 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[9] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 2.049 ns ; -; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; -; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; -; 2.114 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[14] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.071 ns ; -; 2.147 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[8] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.104 ns ; -; 2.172 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.129 ns ; -; 2.172 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[15] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.129 ns ; -; 2.209 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[7] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.166 ns ; -; 2.230 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[16] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.187 ns ; -; 2.263 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[6] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.220 ns ; -; 2.325 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[5] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.282 ns ; -; 2.380 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[4] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.337 ns ; -; 2.443 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[3] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.400 ns ; -; 2.501 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[2] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.458 ns ; -; 2.559 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[1] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.516 ns ; -; 2.617 ns ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] ; lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 2.574 ns ; -+---------------+---------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' ; -+---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 0.564 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.522 ns ; -; 0.825 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.783 ns ; -; 0.830 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.788 ns ; -; 0.852 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.810 ns ; -; 0.955 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.913 ns ; -; 1.357 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.315 ns ; -; 1.358 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.316 ns ; -; 1.380 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.338 ns ; -; 1.415 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.373 ns ; -; 1.416 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.374 ns ; -; 1.473 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.431 ns ; -; 1.474 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.432 ns ; -; 1.487 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.445 ns ; -; 1.531 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.489 ns ; -; 1.545 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.503 ns ; -; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; -; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; -; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; -; 1.611 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.569 ns ; -+---------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' ; -+-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WR_PR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\MOTORSWITCH:INDEXCNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\INDEX_COUNTER:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\BYTEASMBLY:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO~_Duplicate_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\PHASE_DECODER:PHASE_AMOUNT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|SECT_LEN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_VERIFY_CRC ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_VERIFY_CRC_1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INDEX_MARK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|PLL_D ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T1_CHECK_DIR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T7 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_ACTIV ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_LEADIN ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|BUSY ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:LOCK ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_FF ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T2_WR_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_STROBES:CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_WR_TIMING:CLKMASK_MFM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|DEC_STATE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.B_01 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.C_10 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.547 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.505 ns ; -; 0.549 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[19] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\MFM_PRECOMPENSATION:WRITEPATTERN[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[20] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\ADRMARK_STROBES:DDATA_AM_LOCK ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|DDATA_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[31] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.559 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\RESTORE_TRAP:STEP_CNT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; -; 0.562 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; -; 0.563 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; -; 0.569 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|\MFM_SYNCLOCK:TMP[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; -; 0.569 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\ADDER:ADDER_DATA[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; -; 0.571 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; -; 0.572 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_RD_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_VERIFY_AM ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; -; 0.572 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SHIFT_REG[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; -; 0.573 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.577 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.535 ns ; -; 0.580 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.538 ns ; -; 0.582 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.540 ns ; -; 0.584 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.542 ns ; -; 0.591 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|WR_CNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.549 ns ; -; 0.592 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.550 ns ; -; 0.593 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.551 ns ; -; 0.608 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.566 ns ; -; 0.609 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.567 ns ; -; 0.610 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.568 ns ; -; 0.610 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.568 ns ; -; 0.614 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.572 ns ; -; 0.614 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.572 ns ; -; 0.616 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.574 ns ; -; 0.616 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_CHECK_RD ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.574 ns ; -; 0.625 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.583 ns ; -; 0.626 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.584 ns ; -; 0.627 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.585 ns ; -; 0.667 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[23] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.625 ns ; -; 0.668 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.626 ns ; -; 0.669 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.627 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[12] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[26] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[27] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[28] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[21] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.670 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[22] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.628 ns ; -; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|parity8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[16] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.671 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|parity5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; -; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[13] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|\CLK_MASK:MASK_SHFT[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; -; 0.672 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[24] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[25] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.630 ns ; -; 0.673 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[29] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[30] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.631 ns ; -; 0.675 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.633 ns ; -; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; -; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; -; 0.677 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; -; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T1 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.678 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.679 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; -; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.639 ns ; -; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[6] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; -; 0.680 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T3 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_STATE.FCF_T6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; -; 0.681 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|AM_SHFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.639 ns ; -; 0.683 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[14] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.641 ns ; -; 0.683 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.641 ns ; -; 0.689 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.689 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|\CNT_T3BYTES:CNT[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_SR ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.649 ns ; -; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2 ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SET_DRQ_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_SHIFT_ADR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.T3_LOAD_DATA_2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.691 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; -; 0.693 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rs_dgwp_reg[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|dffpipe_gd9:rs_bwp|dffe15a[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.652 ns ; -; 0.698 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; 0.330 ns ; 1.028 ns ; -; 0.699 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; -; 0.700 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|TRACKMEM[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_REGISTERS:I_REGISTERS|SECTOR_REG[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; -; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.701 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.704 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.662 ns ; -; 0.704 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a[4] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|alt_synch_pipe_kkd:rs_dgwp|dffpipe_jd9:dffpipe12|dffe14a[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.662 ns ; -; 0.706 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|HISTORY_REG[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.664 ns ; -; 0.708 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_AM_DETECTOR:I_AM_DETECTOR|SHIFT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.666 ns ; -; 0.711 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|cntr_t2e:cntr_b|counter_reg_bit[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_b[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.669 ns ; -; 0.712 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe18a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.043 ns ; 0.669 ns ; -; 0.712 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[0] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|sub_parity6a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.670 ns ; -; 0.714 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.673 ns ; -; 0.715 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[3] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.673 ns ; -; 0.715 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|alt_synch_pipe_jkd:ws_dgrp|dffpipe_id9:dffpipe17|dffe19a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|ws_dgrp_reg[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.673 ns ; -; 0.720 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CRC_PRES ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CRC_LOGIC:I_CRC_LOGIC|CRC_SHIFT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.678 ns ; -; 0.724 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[1] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|sub_parity9a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.682 ns ; -; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[7] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; 0.330 ns ; 1.056 ns ; -; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[10] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|delayed_wrptr_g[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.041 ns ; 0.685 ns ; -; 0.726 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|a_graycounter_j47:rdptr_g1p|counter7a[8] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|rdptr_g[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.684 ns ; -; 0.728 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_fic:wrptr_g1p|counter10a[2] ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] ; 0.000 ns ; -0.042 ns ; 0.686 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; -0.454 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.531 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.443 ns ; -; 0.536 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.403 ns ; 2.939 ns ; -; 0.538 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.450 ns ; -; 0.538 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.450 ns ; -; 0.541 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.453 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.908 ns ; 1.459 ns ; -; 0.556 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.503 ns ; -; 0.557 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.960 ns ; 1.517 ns ; -; 0.559 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.471 ns ; -; 0.559 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.935 ns ; 1.494 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.583 ns ; 1.143 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.476 ns ; -; 0.561 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.478 ns ; -; 0.564 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.570 ns ; 1.134 ns ; -; 0.567 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.514 ns ; -; 0.570 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.486 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.905 ns ; 1.478 ns ; -; 0.576 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.929 ns ; 1.505 ns ; -; 0.578 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.490 ns ; -; 0.579 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.493 ns ; -; 0.580 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.864 ns ; -; 0.583 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.919 ns ; 1.502 ns ; -; 0.583 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.584 ns ; 1.167 ns ; -; 0.583 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.494 ns ; -; 0.584 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.551 ns ; -; 0.585 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.496 ns ; -; 0.586 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.500 ns ; -; 0.588 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.504 ns ; -; 0.589 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.495 ns ; -; 0.589 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.909 ns ; 1.498 ns ; -; 0.590 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.504 ns ; -; 0.591 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.875 ns ; -; 0.592 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.507 ns ; -; 0.592 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.929 ns ; 1.521 ns ; -; 0.597 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.511 ns ; -; 0.600 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.517 ns ; -; 0.600 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.524 ns ; -; 0.600 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.521 ns ; -; 0.600 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.282 ns ; 1.882 ns ; -; 0.601 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.513 ns ; -; 0.601 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.926 ns ; 1.527 ns ; -; 0.604 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.551 ns ; -; 0.608 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.524 ns ; -; 0.608 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.522 ns ; -; 0.609 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.401 ns ; 3.010 ns ; -; 0.610 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.894 ns ; -; 0.611 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.528 ns ; -; 0.613 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.527 ns ; -; 0.613 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.530 ns ; -; 0.613 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.580 ns ; -; 0.614 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.526 ns ; -; 0.614 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.526 ns ; -; 0.614 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.531 ns ; -; 0.614 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.561 ns ; -; 0.614 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.531 ns ; -; 0.617 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.534 ns ; -; 0.618 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.962 ns ; 1.580 ns ; -; 0.619 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.540 ns ; -; 0.620 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.541 ns ; -; 0.620 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.534 ns ; -; 0.620 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.541 ns ; -; 0.622 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.542 ns ; -; 0.622 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.539 ns ; -; 0.622 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.546 ns ; -; 0.622 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.597 ns ; 1.219 ns ; -; 0.622 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.528 ns ; -; 0.623 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.537 ns ; -; 0.623 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.544 ns ; -; 0.623 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.283 ns ; 1.906 ns ; -; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.547 ns ; -; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.550 ns ; -; 0.626 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.550 ns ; -; 0.627 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.548 ns ; -; 0.627 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.551 ns ; -; 0.627 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.544 ns ; -; 0.628 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.543 ns ; -; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.543 ns ; -; 0.628 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.912 ns ; -; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.545 ns ; -; 0.628 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.541 ns ; -; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.550 ns ; -; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.921 ns ; 1.550 ns ; -; 0.629 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.553 ns ; -; 0.630 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.544 ns ; -; 0.630 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.554 ns ; -; 0.631 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.545 ns ; -; 0.632 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.588 ns ; 1.220 ns ; -; 0.633 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.546 ns ; -; 0.633 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.549 ns ; -; 0.636 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.909 ns ; 1.545 ns ; -; 0.637 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.551 ns ; -; 0.637 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.551 ns ; -; 0.638 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.555 ns ; -; 0.638 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.549 ns ; -; 0.638 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.552 ns ; -; 0.639 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.556 ns ; -; 0.639 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.555 ns ; -; 0.641 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.558 ns ; -; 0.641 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.555 ns ; -; 0.642 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.558 ns ; -; 0.643 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.557 ns ; -; 0.644 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.558 ns ; -; 0.644 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.611 ns ; -; 0.645 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.557 ns ; -; 0.646 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.560 ns ; -; 0.646 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.586 ns ; 1.232 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.561 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.910 ns ; 1.557 ns ; -; 0.648 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.907 ns ; 1.555 ns ; -; 0.648 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.577 ns ; 1.225 ns ; -; 0.648 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.560 ns ; -; 0.648 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.907 ns ; 1.555 ns ; -; 0.648 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.562 ns ; -; 0.649 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.566 ns ; -; 0.649 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.567 ns ; -; 0.649 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.563 ns ; -; 0.650 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.568 ns ; -; 0.650 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.570 ns ; 1.220 ns ; -; 0.651 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.577 ns ; 1.228 ns ; -; 0.651 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 2.404 ns ; 3.055 ns ; -; 0.652 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.576 ns ; -; 0.653 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.567 ns ; -; 0.653 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.567 ns ; -; 0.655 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.602 ns ; -; 0.656 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.585 ns ; 1.241 ns ; -; 0.656 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.282 ns ; 1.938 ns ; -; 0.657 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.924 ns ; 1.581 ns ; -; 0.657 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.571 ns ; -; 0.658 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.905 ns ; 1.563 ns ; -; 0.658 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.572 ns ; -; 0.659 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.565 ns ; -; 0.660 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.627 ns ; -; 0.661 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.608 ns ; -; 0.661 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.575 ns ; -; 0.662 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.577 ns ; -; 0.662 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.912 ns ; 1.574 ns ; -; 0.662 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.576 ns ; -; 0.662 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.918 ns ; 1.580 ns ; -; 0.663 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.916 ns ; 1.579 ns ; -; 0.663 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.947 ns ; 1.610 ns ; -; 0.664 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.911 ns ; 1.575 ns ; -; 0.664 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.930 ns ; 1.594 ns ; -; 0.664 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.906 ns ; 1.570 ns ; -; 0.664 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.584 ns ; -; 0.665 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.582 ns ; -; 0.665 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.579 ns ; -; 0.665 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.578 ns ; -; 0.666 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.580 ns ; -; 0.666 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.580 ns ; -; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.581 ns ; -; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.581 ns ; -; 0.667 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.920 ns ; 1.587 ns ; -; 0.667 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.580 ns ; -; 0.667 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.634 ns ; -; 0.669 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.585 ns ; 1.254 ns ; -; 0.669 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.913 ns ; 1.582 ns ; -; 0.669 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 1.284 ns ; 1.953 ns ; -; 0.669 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.967 ns ; 1.636 ns ; -; 0.669 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.583 ns ; -; 0.670 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.914 ns ; 1.584 ns ; -; 0.670 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.917 ns ; 1.587 ns ; -; 0.671 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.915 ns ; 1.586 ns ; -; 0.671 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] ; 0.000 ns ; 0.908 ns ; 1.579 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' ; -+-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_AC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FIFO_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[75] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[99] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[65] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[81] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.549 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.507 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[87] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[105] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[110] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[94] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.550 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.508 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[124] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[123] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[66] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[126] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[8] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[9] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.551 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe19a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|dffpipe_9d9:wraclr|dffe20a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.509 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[102] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[86] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[118] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[67] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[83] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C6 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.552 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.510 ns ; -; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[125] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[92] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[73] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[121] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[0] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.553 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|MCS[1] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_DDR_SYNC ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.511 ns ; -; 0.554 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[120] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.512 ns ; -; 0.554 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.512 ns ; -; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; -; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; -; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; -; 0.558 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.516 ns ; -; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; -; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[42] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; -; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; -; 0.559 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[56] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.517 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[32] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; -; 0.560 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.518 ns ; -; 0.561 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[39] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.519 ns ; -; 0.561 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.519 ns ; -; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; -; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; -; 0.562 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.520 ns ; -; 0.563 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[52] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; -; 0.563 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[57] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.521 ns ; -; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; -; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; -; 0.569 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.527 ns ; -; 0.570 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.528 ns ; -; 0.570 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.528 ns ; -; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; -; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; -; 0.571 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.529 ns ; -; 0.572 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VIDEO_ADR_CNT[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.530 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[84] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[84] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[95] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[95] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[46] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.573 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|parity11 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.531 ns ; -; 0.574 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.532 ns ; -; 0.582 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[70] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[70] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.540 ns ; -; 0.583 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_REFRESH_SIG[3] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.541 ns ; -; 0.592 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.550 ns ; -; 0.593 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[4] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.551 ns ; -; 0.595 ns ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_shiftreg6:inst92|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.553 ns ; -; 0.601 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.559 ns ; -; 0.604 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.562 ns ; -; 0.605 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.563 ns ; -; 0.605 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.563 ns ; -; 0.643 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a3~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.340 ns ; 0.983 ns ; -; 0.647 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[7] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.332 ns ; 0.979 ns ; -; 0.654 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 0.988 ns ; -; 0.670 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a0~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.332 ns ; 1.002 ns ; -; 0.671 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.629 ns ; -; 0.673 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 1.007 ns ; -; 0.675 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[90] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.633 ns ; -; 0.676 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C2 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.634 ns ; -; 0.677 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; -; 0.677 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[88] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.635 ns ; -; 0.678 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[97] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.678 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[2] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.678 ns ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_shiftreg4:inst26|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.636 ns ; -; 0.679 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[85] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; -; 0.679 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[100] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; -; 0.679 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe23a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; -; 0.679 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe24a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.637 ns ; -; 0.680 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[93] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; -; 0.680 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[114] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; -; 0.680 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|alt_synch_pipe_sld:ws_dgrp|dffpipe_re9:dffpipe22|dffe25a[3] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|ws_dgrp_reg[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.638 ns ; -; 0.681 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[98] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.639 ns ; -; 0.687 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.645 ns ; -; 0.687 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.645 ns ; -; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; -; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; -; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; -; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; -; 0.688 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.646 ns ; -; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[41] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.689 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[49] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.647 ns ; -; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[44] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[33] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[61] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.690 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.648 ns ; -; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; -; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; -; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[43] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; -; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; -; 0.691 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.649 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[54] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[91] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.649 ns ; -; 0.692 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R6 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_N5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.650 ns ; -; 0.693 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.651 ns ; -; 0.694 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a14~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.334 ns ; 1.028 ns ; -; 0.695 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[106] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[45] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[77] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[77] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[109] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.655 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.656 ns ; -; 0.698 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C5 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 0.657 ns ; -; 0.699 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[46] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; -; 0.699 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[78] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[78] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.657 ns ; -; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst12|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; -; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; -; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[53] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; -; 0.700 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst20|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[82] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; -; 0.700 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T7W ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T8W ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.658 ns ; -; 0.701 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.701 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_C4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_R2 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.701 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T4W ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DS_T5W ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.659 ns ; -; 0.703 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff1:inst4|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.661 ns ; -; 0.703 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|sub_parity12a0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.661 ns ; -; 0.704 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.031 ns ; -; 0.705 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[5] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a7~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.341 ns ; 1.046 ns ; -; 0.706 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ram_block14a5~porta_address_reg0 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.033 ns ; -; 0.707 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst3|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[51] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.665 ns ; -; 0.710 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 0.669 ns ; -; 0.712 ns ; Video:Fredi_Aschwanden|lpm_ff6:inst71|lpm_ff:lpm_ff_component|dffs[40] ; Video:Fredi_Aschwanden|lpm_ff6:inst94|lpm_ff:lpm_ff_component|dffs[40] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 0.669 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' ; -+---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; -; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; -; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; -; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; -; 4.336 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.507 ns ; -; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; -; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; -; 4.337 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.508 ns ; -; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; -; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; -; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; -; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; -; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; -; 4.338 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.509 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.339 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[31] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.510 ns ; -; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; -; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; -; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; -; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; -; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; -; 4.340 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[30] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.511 ns ; -; 4.465 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[28] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.636 ns ; -; 4.466 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[29] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.637 ns ; -; 4.467 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.638 ns ; -; 4.468 ns ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] ; -3.787 ns ; -3.829 ns ; 0.639 ns ; -+---------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' ; -+---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 1.825 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.508 ns ; -; 1.827 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[7] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.510 ns ; -; 1.953 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.636 ns ; -; 1.954 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[5] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.317 ns ; 0.637 ns ; -; 2.134 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; -1.262 ns ; -1.315 ns ; 0.819 ns ; -+---------------+---------------------------------------------------+-----------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' ; -+-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 3.263 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.570 ns ; -; 3.273 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.580 ns ; -; 3.460 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.363 ns ; -; 3.511 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 1.818 ns ; -; 3.539 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 1.845 ns ; -; 3.543 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 1.857 ns ; -; 3.548 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 1.860 ns ; -; 3.569 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 1.874 ns ; -; 3.570 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 1.882 ns ; -; 3.573 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.667 ns ; 1.906 ns ; -; 3.609 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 1.937 ns ; -; 3.618 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 1.929 ns ; -; 3.637 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 1.952 ns ; -; 3.656 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 1.959 ns ; -; 3.660 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 1.974 ns ; -; 3.674 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 1.983 ns ; -; 3.686 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.692 ns ; 1.994 ns ; -; 3.719 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.024 ns ; -; 3.721 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 2.030 ns ; -; 3.730 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.698 ns ; 2.032 ns ; -; 3.731 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.634 ns ; -; 3.737 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.042 ns ; -; 3.740 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.664 ns ; 2.076 ns ; -; 3.745 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.668 ns ; 2.077 ns ; -; 3.754 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.059 ns ; -; 3.769 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 3.672 ns ; -; 3.774 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 2.077 ns ; -; 3.776 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 2.091 ns ; -; 3.777 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.698 ns ; 2.079 ns ; -; 3.778 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 2.085 ns ; -; 3.780 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.084 ns ; -; 3.781 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.684 ns ; 2.097 ns ; -; 3.784 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.089 ns ; -; 3.784 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.684 ns ; 2.100 ns ; -; 3.786 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.097 ns ; -; 3.792 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 3.693 ns ; -; 3.794 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.692 ns ; 2.102 ns ; -; 3.796 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.107 ns ; -; 3.811 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.125 ns ; -; 3.814 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.688 ns ; 2.126 ns ; -; 3.819 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.697 ns ; 2.122 ns ; -; 3.836 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.695 ns ; 2.141 ns ; -; 3.838 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 3.735 ns ; -; 3.839 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.101 ns ; 3.738 ns ; -; 3.855 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.755 ns ; -; 3.866 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 3.763 ns ; -; 3.899 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 2.205 ns ; -; 3.902 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.203 ns ; -; 3.906 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.722 ns ; 2.184 ns ; -; 3.916 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 3.812 ns ; -; 3.920 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.234 ns ; -; 3.932 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.686 ns ; 2.246 ns ; -; 3.933 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.613 ns ; 2.320 ns ; -; 3.935 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.239 ns ; -; 3.936 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 3.837 ns ; -; 3.944 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.694 ns ; 2.250 ns ; -; 3.951 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.851 ns ; -; 3.973 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.101 ns ; 3.872 ns ; -; 3.979 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.283 ns ; -; 3.989 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.693 ns ; 2.296 ns ; -; 4.004 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.904 ns ; -; 4.029 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 3.931 ns ; -; 4.042 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.683 ns ; 2.359 ns ; -; 4.043 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.685 ns ; 2.358 ns ; -; 4.043 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.344 ns ; -; 4.048 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[16]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.696 ns ; 2.352 ns ; -; 4.078 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[17]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 3.978 ns ; -; 4.084 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 3.980 ns ; -; 4.096 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 3.998 ns ; -; 4.110 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.104 ns ; 4.006 ns ; -; 4.112 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.371 ns ; -; 4.112 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.689 ns ; 2.423 ns ; -; 4.115 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.012 ns ; -; 4.117 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.014 ns ; -; 4.132 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.097 ns ; 4.035 ns ; -; 4.168 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.429 ns ; -; 4.169 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.699 ns ; 2.470 ns ; -; 4.185 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.454 ns ; -; 4.187 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.723 ns ; 2.464 ns ; -; 4.195 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.431 ns ; -; 4.196 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.713 ns ; 2.483 ns ; -; 4.201 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 2.447 ns ; -; 4.221 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.714 ns ; 2.507 ns ; -; 4.231 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.614 ns ; 2.617 ns ; -; 4.232 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.133 ns ; -; 4.232 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.674 ns ; 2.558 ns ; -; 4.235 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.103 ns ; 4.132 ns ; -; 4.236 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[27]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.102 ns ; 4.134 ns ; -; 4.239 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.673 ns ; 2.566 ns ; -; 4.243 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.479 ns ; -; 4.249 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.669 ns ; 2.580 ns ; -; 4.251 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.152 ns ; -; 4.269 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[30]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.099 ns ; 4.170 ns ; -; 4.283 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.185 ns ; -; 4.286 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.188 ns ; -; 4.296 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[20]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.670 ns ; 2.626 ns ; -; 4.313 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[24]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.666 ns ; 2.647 ns ; -; 4.314 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.691 ns ; 2.623 ns ; -; 4.331 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 2.596 ns ; -; 4.333 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.145 ns ; 4.188 ns ; -; 4.343 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.145 ns ; 4.198 ns ; -; 4.347 ns ; Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_out0:inst2|altddio_out:altddio_out_component|ddio_out_are:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.578 ns ; -1.665 ns ; 2.682 ns ; -; 4.352 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.098 ns ; 4.254 ns ; -; 4.352 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[23]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 4.252 ns ; -; 4.362 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.717 ns ; 2.645 ns ; -; 4.367 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.608 ns ; -; 4.376 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.635 ns ; -; 4.384 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[22]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.102 ns ; 4.282 ns ; -; 4.406 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.615 ns ; 2.791 ns ; -; 4.409 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.645 ns ; -; 4.410 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.646 ns ; -; 4.411 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.159 ns ; 4.252 ns ; -; 4.417 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.746 ns ; 2.671 ns ; -; 4.425 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.100 ns ; 4.325 ns ; -; 4.431 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[19]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.670 ns ; 2.761 ns ; -; 4.434 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.695 ns ; -; 4.440 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.685 ns ; -; 4.450 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.719 ns ; -; 4.475 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.741 ns ; 2.734 ns ; -; 4.477 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[26]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 2.805 ns ; -; 4.478 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.730 ns ; 2.748 ns ; -; 4.480 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.757 ns ; 2.723 ns ; -; 4.485 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.736 ns ; -; 4.486 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[25]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.672 ns ; 2.814 ns ; -; 4.497 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.351 ns ; -; 4.498 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.329 ns ; -; 4.527 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 2.773 ns ; -; 4.530 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 2.791 ns ; -; 4.555 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 2.804 ns ; -; 4.556 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.163 ns ; 4.393 ns ; -; 4.573 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.818 ns ; -; 4.587 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.615 ns ; 2.972 ns ; -; 4.597 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.429 ns ; -; 4.600 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 2.865 ns ; -; 4.601 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.852 ns ; -; 4.601 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.433 ns ; -; 4.613 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[28]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.674 ns ; 2.939 ns ; -; 4.614 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.855 ns ; -; 4.618 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 2.867 ns ; -; 4.623 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.159 ns ; 4.464 ns ; -; 4.626 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.742 ns ; 2.884 ns ; -; 4.630 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.740 ns ; 2.890 ns ; -; 4.633 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 2.874 ns ; -; 4.636 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.150 ns ; 4.486 ns ; -; 4.637 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.906 ns ; -; 4.660 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 2.911 ns ; -; 4.670 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.517 ns ; -; 4.671 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.164 ns ; 4.507 ns ; -; 4.676 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.912 ns ; -; 4.677 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.745 ns ; 2.932 ns ; -; 4.677 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[8]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.764 ns ; 2.913 ns ; -; 4.686 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.746 ns ; 2.940 ns ; -; 4.690 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.726 ns ; 2.964 ns ; -; 4.697 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.168 ns ; 4.529 ns ; -; 4.699 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.874 ns ; 1.825 ns ; -; 4.704 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 2.949 ns ; -; 4.709 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[18]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.664 ns ; 3.045 ns ; -; 4.722 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 2.991 ns ; -; 4.749 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[0]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.603 ns ; -; 4.753 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.004 ns ; -; 4.780 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.155 ns ; 4.625 ns ; -; 4.787 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.156 ns ; 4.631 ns ; -; 4.791 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.638 ns ; -; 4.805 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.730 ns ; 3.075 ns ; -; 4.809 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.640 ns ; -; 4.823 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 3.072 ns ; -; 4.825 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.163 ns ; 4.662 ns ; -; 4.840 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[1]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.712 ns ; 3.128 ns ; -; 4.844 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.735 ns ; 3.109 ns ; -; 4.844 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.155 ns ; 4.689 ns ; -; 4.845 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.154 ns ; 4.691 ns ; -; 4.846 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.146 ns ; 4.700 ns ; -; 4.863 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.755 ns ; 3.108 ns ; -; 4.869 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.131 ns ; -; 4.871 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.122 ns ; -; 4.878 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.153 ns ; 4.725 ns ; -; 4.881 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[10]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.169 ns ; 4.712 ns ; -; 4.885 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.751 ns ; 3.134 ns ; -; 4.888 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.156 ns ; 4.732 ns ; -; 4.892 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.147 ns ; 4.745 ns ; -; 4.892 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.742 ns ; 3.150 ns ; -; 4.896 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[14]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.740 ns ; 3.156 ns ; -; 4.906 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[12]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.731 ns ; 3.175 ns ; -; 4.916 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.866 ns ; 2.050 ns ; -; 4.916 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[15]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.151 ns ; 4.765 ns ; -; 4.924 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.749 ns ; 3.175 ns ; -; 4.942 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.745 ns ; 3.197 ns ; -; 4.979 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[6]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.160 ns ; 4.819 ns ; -; 5.007 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[5]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.754 ns ; 3.253 ns ; -; 5.009 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFLO ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.759 ns ; 3.250 ns ; -; 5.013 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[9]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.726 ns ; 3.287 ns ; -; 5.029 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[3]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.164 ns ; 4.865 ns ; -; 5.047 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.739 ns ; 3.308 ns ; -; 5.088 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_3 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.869 ns ; 2.219 ns ; -; 5.096 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_DDR_WR ; Video:Fredi_Aschwanden|inst90~_Duplicate_1 ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -2.840 ns ; -2.933 ns ; 2.163 ns ; -; 5.124 ns ; Video:Fredi_Aschwanden|inst90~_Duplicate_4 ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; 0.000 ns ; -0.154 ns ; 4.970 ns ; -; 5.133 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[13]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.395 ns ; -; 5.143 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[11]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.722 ns ; 3.421 ns ; -; 5.166 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[7]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.738 ns ; 3.428 ns ; -; 5.205 ns ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[4]~DFFHI ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] ; -1.576 ns ; -1.720 ns ; 3.485 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' ; -+-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; -; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; -; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[3] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; -; 2.664 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.216 ns ; -; 2.679 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.447 ns ; 2.232 ns ; -; 2.684 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[1] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.447 ns ; 2.237 ns ; -; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; -; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[6] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; -; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; -; 2.686 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[9] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.448 ns ; 2.238 ns ; -; 2.714 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.264 ns ; -; 2.714 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[10] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.264 ns ; -; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; -; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[15] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; -; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; -; 2.716 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.266 ns ; -; 2.769 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.319 ns ; -; 2.769 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.450 ns ; 2.319 ns ; -; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[21] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; -; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[22] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; -; 2.790 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[23] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.449 ns ; 2.341 ns ; -; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[20] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; -; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[24] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; -; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; -; 2.794 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.451 ns ; 2.343 ns ; -; 2.948 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -1.264 ns ; -1.316 ns ; 1.632 ns ; -; 3.033 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[26] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.589 ns ; -; 3.033 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[25] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.589 ns ; -; 3.088 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.042 ns ; 3.046 ns ; -; 3.100 ns ; FB_ALE ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[27] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.444 ns ; 2.656 ns ; -; 3.146 ns ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; 0.000 ns ; -0.316 ns ; 2.830 ns ; -; 6.237 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.309 ns ; 1.928 ns ; -; 6.282 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.386 ns ; 1.896 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.650 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.288 ns ; -; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; -; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; -; 6.738 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.361 ns ; 2.377 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.739 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.358 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.413 ns ; -; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; -; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; -; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; -; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; -; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; -; 6.981 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.619 ns ; -; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; -; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; -; 6.987 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.624 ns ; -; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; -; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; -; 7.023 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.363 ns ; 2.660 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.036 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.373 ns ; 2.663 ns ; -; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; -; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; -; 7.043 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.362 ns ; 2.681 ns ; -; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; -; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; -; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; -; 7.045 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.354 ns ; 2.691 ns ; -; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; -; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; -; 7.106 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.381 ns ; 2.725 ns ; -; 7.218 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_WAIT ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.355 ns ; 2.863 ns ; -; 7.413 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.650 ns ; 2.763 ns ; -; 7.427 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.650 ns ; 2.777 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.430 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.804 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.478 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.018 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.508 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.048 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.512 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.052 ns ; -; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; -; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; -; 7.518 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.625 ns ; 2.893 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.524 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.064 ns ; -; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; -; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; -; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; -; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; -; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; -; 7.531 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.071 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.555 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.626 ns ; 2.929 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.561 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.460 ns ; 3.101 ns ; -; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; -; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; -; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; -; 7.571 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.622 ns ; 2.949 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.598 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.471 ns ; 3.127 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.629 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.278 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.675 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.351 ns ; 3.324 ns ; -; 7.686 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] ; -4.884 ns ; -4.470 ns ; 3.216 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+---------------------------------------------------------------------------------+------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 0.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 0.460 ns ; -; 1.487 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.443 ns ; -; 1.492 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.447 ns ; 2.939 ns ; -; 1.494 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.450 ns ; -; 1.494 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.450 ns ; -; 1.497 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.453 ns ; -; 1.507 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.048 ns ; 1.459 ns ; -; 1.512 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.503 ns ; -; 1.513 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.004 ns ; 1.517 ns ; -; 1.515 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.471 ns ; -; 1.515 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.021 ns ; 1.494 ns ; -; 1.516 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.373 ns ; 1.143 ns ; -; 1.516 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.476 ns ; -; 1.517 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.478 ns ; -; 1.520 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.386 ns ; 1.134 ns ; -; 1.523 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.514 ns ; -; 1.526 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.486 ns ; -; 1.529 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.051 ns ; 1.478 ns ; -; 1.532 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.027 ns ; 1.505 ns ; -; 1.534 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.490 ns ; -; 1.535 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.493 ns ; -; 1.536 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.864 ns ; -; 1.539 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.037 ns ; 1.502 ns ; -; 1.539 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.372 ns ; 1.167 ns ; -; 1.539 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.494 ns ; -; 1.540 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.551 ns ; -; 1.541 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.496 ns ; -; 1.542 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.500 ns ; -; 1.544 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.504 ns ; -; 1.545 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.495 ns ; -; 1.545 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.047 ns ; 1.498 ns ; -; 1.546 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.504 ns ; -; 1.547 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.875 ns ; -; 1.548 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.507 ns ; -; 1.548 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.027 ns ; 1.521 ns ; -; 1.553 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.511 ns ; -; 1.556 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.517 ns ; -; 1.556 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.524 ns ; -; 1.556 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.521 ns ; -; 1.556 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.326 ns ; 1.882 ns ; -; 1.557 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.513 ns ; -; 1.557 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.030 ns ; 1.527 ns ; -; 1.560 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.551 ns ; -; 1.564 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.524 ns ; -; 1.564 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.522 ns ; -; 1.565 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.445 ns ; 3.010 ns ; -; 1.566 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.894 ns ; -; 1.567 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.528 ns ; -; 1.569 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.527 ns ; -; 1.569 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.530 ns ; -; 1.569 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.580 ns ; -; 1.570 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.526 ns ; -; 1.570 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.526 ns ; -; 1.570 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.531 ns ; -; 1.570 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.561 ns ; -; 1.570 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.531 ns ; -; 1.573 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.534 ns ; -; 1.574 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.006 ns ; 1.580 ns ; -; 1.575 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.540 ns ; -; 1.576 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.541 ns ; -; 1.576 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.534 ns ; -; 1.576 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.541 ns ; -; 1.578 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.542 ns ; -; 1.578 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.539 ns ; -; 1.578 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.546 ns ; -; 1.578 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.359 ns ; 1.219 ns ; -; 1.578 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.528 ns ; -; 1.579 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.537 ns ; -; 1.579 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.544 ns ; -; 1.579 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.327 ns ; 1.906 ns ; -; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.547 ns ; -; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.550 ns ; -; 1.582 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.550 ns ; -; 1.583 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.548 ns ; -; 1.583 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.551 ns ; -; 1.583 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.544 ns ; -; 1.584 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.543 ns ; -; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.543 ns ; -; 1.584 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.912 ns ; -; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.545 ns ; -; 1.584 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.541 ns ; -; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.550 ns ; -; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.035 ns ; 1.550 ns ; -; 1.585 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.553 ns ; -; 1.586 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.544 ns ; -; 1.586 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.554 ns ; -; 1.587 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.545 ns ; -; 1.588 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.368 ns ; 1.220 ns ; -; 1.589 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.546 ns ; -; 1.589 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.549 ns ; -; 1.592 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.047 ns ; 1.545 ns ; -; 1.593 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.551 ns ; -; 1.593 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.551 ns ; -; 1.594 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.555 ns ; -; 1.594 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.549 ns ; -; 1.594 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.552 ns ; -; 1.595 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.556 ns ; -; 1.595 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.555 ns ; -; 1.597 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.558 ns ; -; 1.597 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.555 ns ; -; 1.598 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.558 ns ; -; 1.599 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.557 ns ; -; 1.600 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.558 ns ; -; 1.600 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.611 ns ; -; 1.601 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.557 ns ; -; 1.602 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.560 ns ; -; 1.602 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.370 ns ; 1.232 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.561 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.603 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.046 ns ; 1.557 ns ; -; 1.604 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.049 ns ; 1.555 ns ; -; 1.604 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.379 ns ; 1.225 ns ; -; 1.604 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.560 ns ; -; 1.604 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.049 ns ; 1.555 ns ; -; 1.604 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.562 ns ; -; 1.605 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.566 ns ; -; 1.605 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.567 ns ; -; 1.605 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.563 ns ; -; 1.606 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.568 ns ; -; 1.606 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.386 ns ; 1.220 ns ; -; 1.607 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.379 ns ; 1.228 ns ; -; 1.607 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 1.448 ns ; 3.055 ns ; -; 1.608 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.576 ns ; -; 1.609 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.567 ns ; -; 1.609 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.567 ns ; -; 1.611 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.602 ns ; -; 1.612 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.371 ns ; 1.241 ns ; -; 1.612 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.326 ns ; 1.938 ns ; -; 1.613 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.032 ns ; 1.581 ns ; -; 1.613 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.571 ns ; -; 1.614 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.051 ns ; 1.563 ns ; -; 1.614 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.572 ns ; -; 1.615 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.565 ns ; -; 1.616 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.627 ns ; -; 1.617 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.608 ns ; -; 1.617 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.575 ns ; -; 1.618 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.577 ns ; -; 1.618 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.044 ns ; 1.574 ns ; -; 1.618 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.576 ns ; -; 1.618 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.038 ns ; 1.580 ns ; -; 1.619 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.040 ns ; 1.579 ns ; -; 1.619 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.009 ns ; 1.610 ns ; -; 1.620 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.045 ns ; 1.575 ns ; -; 1.620 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.026 ns ; 1.594 ns ; -; 1.620 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.050 ns ; 1.570 ns ; -; 1.620 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.584 ns ; -; 1.621 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.582 ns ; -; 1.621 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.579 ns ; -; 1.621 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.578 ns ; -; 1.622 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.580 ns ; -; 1.622 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.580 ns ; -; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.581 ns ; -; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.581 ns ; -; 1.623 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.036 ns ; 1.587 ns ; -; 1.623 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.580 ns ; -; 1.623 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.634 ns ; -; 1.625 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.371 ns ; 1.254 ns ; -; 1.625 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.043 ns ; 1.582 ns ; -; 1.625 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.328 ns ; 1.953 ns ; -; 1.625 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; 0.011 ns ; 1.636 ns ; -; 1.625 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.583 ns ; -; 1.626 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.584 ns ; -; 1.626 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.039 ns ; 1.587 ns ; -; 1.627 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.041 ns ; 1.586 ns ; -; 1.627 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.048 ns ; 1.579 ns ; -; 1.627 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] ; 0.000 ns ; -0.042 ns ; 1.585 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+--------------------------------------------------------------------------+----------------------------+----------------------------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'CLK33M' ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; -0.687 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 0.460 ns ; -; 0.298 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.443 ns ; -; 0.303 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; CLK33M ; CLK33M ; 0.000 ns ; 2.636 ns ; 2.939 ns ; -; 0.305 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.450 ns ; -; 0.305 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.450 ns ; -; 0.308 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.453 ns ; -; 0.318 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; CLK33M ; CLK33M ; 0.000 ns ; 1.141 ns ; 1.459 ns ; -; 0.323 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.503 ns ; -; 0.324 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.193 ns ; 1.517 ns ; -; 0.326 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.471 ns ; -; 0.326 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; CLK33M ; CLK33M ; 0.000 ns ; 1.168 ns ; 1.494 ns ; -; 0.327 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; CLK33M ; CLK33M ; 0.000 ns ; 0.816 ns ; 1.143 ns ; -; 0.327 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.476 ns ; -; 0.328 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.478 ns ; -; 0.331 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 0.803 ns ; 1.134 ns ; -; 0.334 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.514 ns ; -; 0.337 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.486 ns ; -; 0.340 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.138 ns ; 1.478 ns ; -; 0.343 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.162 ns ; 1.505 ns ; -; 0.345 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.490 ns ; -; 0.346 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.493 ns ; -; 0.347 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.864 ns ; -; 0.350 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.152 ns ; 1.502 ns ; -; 0.350 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 0.817 ns ; 1.167 ns ; -; 0.350 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.494 ns ; -; 0.351 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.551 ns ; -; 0.352 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.496 ns ; -; 0.353 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.500 ns ; -; 0.355 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.504 ns ; -; 0.356 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.495 ns ; -; 0.356 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; CLK33M ; CLK33M ; 0.000 ns ; 1.142 ns ; 1.498 ns ; -; 0.357 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.504 ns ; -; 0.358 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.875 ns ; -; 0.359 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.507 ns ; -; 0.359 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; CLK33M ; CLK33M ; 0.000 ns ; 1.162 ns ; 1.521 ns ; -; 0.364 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.511 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.517 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[82] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe6 ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.524 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.521 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.515 ns ; 1.882 ns ; -; 0.368 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[55] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[87] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.513 ns ; -; 0.368 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.159 ns ; 1.527 ns ; -; 0.371 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[48] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.551 ns ; -; 0.375 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe22 ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.524 ns ; -; 0.375 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.522 ns ; -; 0.376 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; altddio_out3:inst6|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; CLK33M ; CLK33M ; 0.000 ns ; 2.634 ns ; 3.010 ns ; -; 0.377 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.894 ns ; -; 0.378 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.528 ns ; -; 0.380 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.527 ns ; -; 0.380 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.530 ns ; -; 0.380 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[125] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.580 ns ; -; 0.381 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.526 ns ; -; 0.381 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.526 ns ; -; 0.381 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.531 ns ; -; 0.381 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[36] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.561 ns ; -; 0.381 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.531 ns ; -; 0.384 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe13 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.534 ns ; -; 0.385 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[16] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.195 ns ; 1.580 ns ; -; 0.386 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.540 ns ; -; 0.387 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.541 ns ; -; 0.387 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.534 ns ; -; 0.387 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.541 ns ; -; 0.389 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[26] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[42] ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.542 ns ; -; 0.389 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.539 ns ; -; 0.389 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.546 ns ; -; 0.389 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[88] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[88] ; CLK33M ; CLK33M ; 0.000 ns ; 0.830 ns ; 1.219 ns ; -; 0.389 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_AV[1][0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[0] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.528 ns ; -; 0.390 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[38] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.537 ns ; -; 0.390 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.544 ns ; -; 0.390 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.516 ns ; 1.906 ns ; -; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.547 ns ; -; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[8] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.550 ns ; -; 0.393 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.550 ns ; -; 0.394 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.548 ns ; -; 0.394 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.551 ns ; -; 0.394 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[3] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe1a[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.544 ns ; -; 0.395 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.543 ns ; -; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.543 ns ; -; 0.395 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.912 ns ; -; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe12 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.545 ns ; -; 0.395 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[20] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[36] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.541 ns ; -; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.550 ns ; -; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.154 ns ; 1.550 ns ; -; 0.396 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.553 ns ; -; 0.397 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.544 ns ; -; 0.397 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr2|lpm_shiftreg:lpm_shiftreg_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.554 ns ; -; 0.398 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe38 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.545 ns ; -; 0.399 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[96] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[96] ; CLK33M ; CLK33M ; 0.000 ns ; 0.821 ns ; 1.220 ns ; -; 0.400 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[54] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[86] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.546 ns ; -; 0.400 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.549 ns ; -; 0.403 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[43] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe25 ; CLK33M ; CLK33M ; 0.000 ns ; 1.142 ns ; 1.545 ns ; -; 0.404 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[117] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.551 ns ; -; 0.404 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe33 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.551 ns ; -; 0.405 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[37] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.555 ns ; -; 0.405 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[25] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.549 ns ; -; 0.405 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[71] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.552 ns ; -; 0.406 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[18] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.556 ns ; -; 0.406 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.555 ns ; -; 0.408 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[16] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[16] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.558 ns ; -; 0.408 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[101] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.555 ns ; -; 0.409 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.558 ns ; -; 0.410 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[111] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[15] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.557 ns ; -; 0.411 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe30 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.558 ns ; -; 0.411 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[124] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.611 ns ; -; 0.412 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.557 ns ; -; 0.413 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[75] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[107] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.560 ns ; -; 0.413 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[8] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[8] ; CLK33M ; CLK33M ; 0.000 ns ; 0.819 ns ; 1.232 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe20 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.561 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[5] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[9] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[8] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[3] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.414 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.143 ns ; 1.557 ns ; -; 0.415 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.140 ns ; 1.555 ns ; -; 0.415 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 0.810 ns ; 1.225 ns ; -; 0.415 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[114] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[2] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.560 ns ; -; 0.415 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr3|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.140 ns ; 1.555 ns ; -; 0.415 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[103] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[7] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.562 ns ; -; 0.416 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[81] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.566 ns ; -; 0.416 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe42 ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.567 ns ; -; 0.416 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[119] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[23] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.563 ns ; -; 0.417 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe26 ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.568 ns ; -; 0.417 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[107] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[107] ; CLK33M ; CLK33M ; 0.000 ns ; 0.803 ns ; 1.220 ns ; -; 0.418 ns ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|q_b[0] ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[5] ; CLK33M ; CLK33M ; 0.000 ns ; 0.810 ns ; 1.228 ns ; -; 0.418 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFLO ; CLK33M ; CLK33M ; 0.000 ns ; 2.637 ns ; 3.055 ns ; -; 0.419 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe40 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.576 ns ; -; 0.420 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[77] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe28 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.567 ns ; -; 0.420 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[5] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr7|lpm_shiftreg:lpm_shiftreg_component|dffs[6] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.567 ns ; -; 0.422 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[19] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.602 ns ; -; 0.423 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[1] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[19] ; CLK33M ; CLK33M ; 0.000 ns ; 0.818 ns ; 1.241 ns ; -; 0.423 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.515 ns ; 1.938 ns ; -; 0.424 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[19] ; CLK33M ; CLK33M ; 0.000 ns ; 1.157 ns ; 1.581 ns ; -; 0.424 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.571 ns ; -; 0.425 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[46] ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.138 ns ; 1.563 ns ; -; 0.425 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.572 ns ; -; 0.426 ns ; Video:Fredi_Aschwanden|lpm_ff4:inst10|lpm_ff:lpm_ff_component|dffs[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.565 ns ; -; 0.427 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[28] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.627 ns ; -; 0.428 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[30] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.608 ns ; -; 0.428 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[14] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.575 ns ; -; 0.429 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe22 ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.577 ns ; -; 0.429 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[100] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.145 ns ; 1.574 ns ; -; 0.429 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.576 ns ; -; 0.429 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[0][4] ; CLK33M ; CLK33M ; 0.000 ns ; 1.151 ns ; 1.580 ns ; -; 0.430 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_ff3:inst46|lpm_ff:lpm_ff_component|dffs[12] ; CLK33M ; CLK33M ; 0.000 ns ; 1.149 ns ; 1.579 ns ; -; 0.430 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[44] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.180 ns ; 1.610 ns ; -; 0.431 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; CLK33M ; CLK33M ; 0.000 ns ; 1.144 ns ; 1.575 ns ; -; 0.431 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst52|lpm_ff:lpm_ff_component|dffs[21] ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 1.163 ns ; 1.594 ns ; -; 0.431 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[13] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[45] ; CLK33M ; CLK33M ; 0.000 ns ; 1.139 ns ; 1.570 ns ; -; 0.431 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe9 ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.584 ns ; -; 0.432 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[17] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.582 ns ; -; 0.432 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLUT_MUX_ADR[1] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe33 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.579 ns ; -; 0.432 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[8] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[40] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.578 ns ; -; 0.433 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe4 ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.580 ns ; -; 0.433 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[0] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.580 ns ; -; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe24 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[11] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.581 ns ; -; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[109] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.581 ns ; -; 0.434 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; CLK33M ; CLK33M ; 0.000 ns ; 1.153 ns ; 1.587 ns ; -; 0.434 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[0] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[16] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.580 ns ; -; 0.434 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[12] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.634 ns ; -; 0.436 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[21] ; CLK33M ; CLK33M ; 0.000 ns ; 0.818 ns ; 1.254 ns ; -; 0.436 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[106] ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; CLK33M ; CLK33M ; 0.000 ns ; 1.146 ns ; 1.582 ns ; -; 0.436 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.517 ns ; 1.953 ns ; -; 0.436 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[117] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; CLK33M ; CLK33M ; 0.000 ns ; 1.200 ns ; 1.636 ns ; -; 0.436 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[5] ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe25 ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.583 ns ; -; 0.437 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[65] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.584 ns ; -; 0.437 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[35] ; CLK33M ; CLK33M ; 0.000 ns ; 1.150 ns ; 1.587 ns ; -; 0.438 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[17] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[49] ; CLK33M ; CLK33M ; 0.000 ns ; 1.148 ns ; 1.586 ns ; -; 0.438 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[99] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; CLK33M ; CLK33M ; 0.000 ns ; 1.141 ns ; 1.579 ns ; -; 0.438 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr4|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; CLK33M ; CLK33M ; 0.000 ns ; 1.147 ns ; 1.585 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clock Hold: 'MAIN_CLK' ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ -; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ -; -3.786 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.716 ns ; 1.930 ns ; -; -3.611 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.756 ns ; 2.145 ns ; -; -3.448 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.709 ns ; 2.261 ns ; -; -3.293 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|RAND[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.327 ns ; 1.034 ns ; -; -3.012 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 2.694 ns ; -; -2.912 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 2.794 ns ; -; -2.048 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.740 ns ; 1.692 ns ; -; -1.996 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe41 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.143 ns ; 1.147 ns ; -; -1.985 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.371 ns ; -; -1.961 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[2][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.104 ns ; 1.143 ns ; -; -1.958 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.142 ns ; 1.184 ns ; -; -1.934 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.422 ns ; -; -1.923 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.433 ns ; -; -1.867 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe45 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.143 ns ; 1.276 ns ; -; -1.842 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.356 ns ; 1.514 ns ; -; -1.835 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[11] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe25 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.390 ns ; 1.555 ns ; -; -1.795 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[13] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe29 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.392 ns ; 1.597 ns ; -; -1.749 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.390 ns ; 1.641 ns ; -; -1.745 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[12] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe27 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.392 ns ; 1.647 ns ; -; -1.641 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.348 ns ; 1.707 ns ; -; -1.595 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.204 ns ; 1.609 ns ; -; -1.569 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe47 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.142 ns ; 1.573 ns ; -; -1.508 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.111 ns ; 1.603 ns ; -; -1.350 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[14] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe31 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.398 ns ; 2.048 ns ; -; -1.326 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.623 ns ; 2.297 ns ; -; -1.242 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe43 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.145 ns ; 1.903 ns ; -; -1.234 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.973 ns ; 0.739 ns ; -; -1.159 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe13 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 1.922 ns ; -; -1.152 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe35 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 1.989 ns ; -; -1.113 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.740 ns ; 2.627 ns ; -; -1.095 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe37 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 2.046 ns ; -; -1.072 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe19 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.362 ns ; 2.290 ns ; -; -1.055 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe39 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.141 ns ; 2.086 ns ; -; -1.001 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.966 ns ; 0.965 ns ; -; -0.993 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 1.310 ns ; -; -0.961 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe15 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 2.120 ns ; -; -0.918 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe33 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.364 ns ; 2.446 ns ; -; -0.893 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.350 ns ; 1.457 ns ; -; -0.849 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.714 ns ; -; -0.825 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe17 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.091 ns ; 2.266 ns ; -; -0.819 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe5 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.080 ns ; 2.261 ns ; -; -0.770 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe3 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.080 ns ; 2.310 ns ; -; -0.743 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.179 ns ; 1.436 ns ; -; -0.742 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.179 ns ; 1.437 ns ; -; -0.692 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe9 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.089 ns ; 2.397 ns ; -; -0.675 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.521 ns ; 2.846 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|rd_ptr_lsb ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DISP_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_I[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SUB_PIXEL_CNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a7 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a1 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a4 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a5 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a8 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a2 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a6 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a9 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|counter5a3 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VHCNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.672 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VVCNT[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 0.460 ns ; -; -0.668 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 2.975 ns ; -; -0.658 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.905 ns ; -; -0.655 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 1.908 ns ; -; -0.591 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe11 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.081 ns ; 2.490 ns ; -; -0.569 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.731 ns ; -; -0.553 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.296 ns ; 1.743 ns ; -; -0.530 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 2.033 ns ; -; -0.447 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.350 ns ; 1.903 ns ; -; -0.441 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.090 ns ; 1.649 ns ; -; -0.422 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.878 ns ; -; -0.420 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.880 ns ; -; -0.407 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe7 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.091 ns ; 2.684 ns ; -; -0.353 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.563 ns ; 2.210 ns ; -; -0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.980 ns ; -; -0.319 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.300 ns ; 1.981 ns ; -; -0.198 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.328 ns ; -; -0.184 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.709 ns ; 5.525 ns ; -; -0.155 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.216 ns ; 3.061 ns ; -; -0.143 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 3.990 ns ; -; -0.133 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.718 ns ; 5.585 ns ; -; -0.126 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.007 ns ; -; -0.126 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.685 ns ; 5.559 ns ; -; -0.125 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.004 ns ; -; -0.116 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.017 ns ; -; -0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 5.593 ns ; -; -0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.314 ns ; -; -0.092 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.037 ns ; -; -0.070 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.885 ns ; 3.815 ns ; -; -0.067 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.214 ns ; 3.147 ns ; -; -0.065 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 3.784 ns ; -; -0.060 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.917 ns ; 3.857 ns ; -; -0.059 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe21 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.363 ns ; 3.304 ns ; -; -0.046 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.311 ns ; 4.265 ns ; -; -0.025 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 5.665 ns ; -; -0.022 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.389 ns ; -; -0.006 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.036 ns ; 2.030 ns ; -; 0.007 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DOP_ZEI ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.760 ns ; 3.767 ns ; -; 0.026 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.689 ns ; 5.715 ns ; -; 0.067 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.593 ns ; -; 0.072 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.526 ns ; 3.598 ns ; -; 0.091 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.637 ns ; 3.728 ns ; -; 0.093 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.885 ns ; 3.978 ns ; -; 0.093 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.961 ns ; 1.054 ns ; -; 0.097 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.036 ns ; 2.133 ns ; -; 0.104 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.718 ns ; 5.822 ns ; -; 0.118 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 3.761 ns ; -; 0.119 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.422 ns ; -; 0.119 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.422 ns ; -; 0.121 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.598 ns ; 4.719 ns ; -; 0.123 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 3.972 ns ; -; 0.132 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.083 ns ; 2.215 ns ; -; 0.150 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.815 ns ; 3.965 ns ; -; 0.151 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.129 ns ; 4.280 ns ; -; 0.158 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[0] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.228 ns ; 1.386 ns ; -; 0.167 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.470 ns ; -; 0.168 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.817 ns ; 3.985 ns ; -; 0.177 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.357 ns ; 2.534 ns ; -; 0.181 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.689 ns ; 5.870 ns ; -; 0.184 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.017 ns ; 6.201 ns ; -; 0.186 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.615 ns ; 3.801 ns ; -; 0.188 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.849 ns ; 4.037 ns ; -; 0.191 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.323 ns ; -; 0.192 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.324 ns ; -; 0.195 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.693 ns ; -; 0.216 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.685 ns ; 3.901 ns ; -; 0.226 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.598 ns ; 4.824 ns ; -; 0.231 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[2] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.707 ns ; 5.938 ns ; -; 0.235 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.013 ns ; 6.248 ns ; -; 0.243 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.459 ns ; 3.702 ns ; -; 0.261 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[7] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.916 ns ; 2.177 ns ; -; 0.262 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.916 ns ; 2.178 ns ; -; 0.265 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.132 ns ; 4.397 ns ; -; 0.266 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_ZL ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.707 ns ; 5.973 ns ; -; 0.291 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.917 ns ; 4.208 ns ; -; 0.311 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.722 ns ; -; 0.313 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[45] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe29 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.443 ns ; -; 0.314 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[1] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.133 ns ; 4.447 ns ; -; 0.315 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.813 ns ; -; 0.315 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[1] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.033 ns ; 2.348 ns ; -; 0.318 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; altddio_out3:inst5|altddio_out:altddio_out_component|ddio_out_31f:auto_generated|ddio_outa[0]~DFFHI ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.621 ns ; 2.939 ns ; -; 0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.450 ns ; -; 0.320 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe28 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.450 ns ; -; 0.323 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCSEL[0] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe30 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.453 ns ; -; 0.324 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.768 ns ; 6.092 ns ; -; 0.333 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[1] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[33] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.126 ns ; 1.459 ns ; -; 0.338 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[62] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.165 ns ; 1.503 ns ; -; 0.339 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[35] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.178 ns ; 1.517 ns ; -; 0.341 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[35] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.471 ns ; -; 0.341 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|SYNC_PIX2 ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FIFO_RDE ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.153 ns ; 1.494 ns ; -; 0.342 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[5] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.801 ns ; 1.143 ns ; -; 0.342 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.476 ns ; -; 0.343 ns ; Video:Fredi_Aschwanden|inst95 ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr1|lpm_shiftreg:lpm_shiftreg_component|dffs[9] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.135 ns ; 1.478 ns ; -; 0.344 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.637 ns ; 3.981 ns ; -; 0.346 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[11] ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.788 ns ; 1.134 ns ; -; 0.347 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.643 ns ; 3.990 ns ; -; 0.349 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[79] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.165 ns ; 1.514 ns ; -; 0.350 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 2.303 ns ; 2.653 ns ; -; 0.352 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[12] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr0|lpm_shiftreg:lpm_shiftreg_component|dffs[13] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.486 ns ; -; 0.354 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7] ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ram_block1a0~portb_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 6.067 ns ; 6.421 ns ; -; 0.355 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe16 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.123 ns ; 1.478 ns ; -; 0.355 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.498 ns ; 3.853 ns ; -; 0.358 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|sub_parity7a[1] ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_s57:rdptr_g1p|parity6 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.147 ns ; 1.505 ns ; -; 0.360 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[19] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[19] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.130 ns ; 1.490 ns ; -; 0.360 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.411 ns ; 3.771 ns ; -; 0.361 ns ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|dffe29 ; Video:Fredi_Aschwanden|lpm_mux2:inst25|lpm_mux:lpm_mux_component|mux_mpe:auto_generated|external_latency_ffsa[6] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.493 ns ; -; 0.362 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[4] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.502 ns ; 1.864 ns ; -; 0.365 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe48 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.137 ns ; 1.502 ns ; -; 0.365 ns ; Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|q_b[3] ; Video:Fredi_Aschwanden|lpm_ff3:inst47|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.802 ns ; 1.167 ns ; -; 0.365 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe8 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.129 ns ; 1.494 ns ; -; 0.366 ns ; Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|q_b[93] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a3~porta_datain_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.185 ns ; 1.551 ns ; -; 0.366 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.747 ns ; 6.113 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[67] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[3] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.129 ns ; 1.496 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[5] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 0.868 ns ; 1.235 ns ; -; 0.367 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|LAST ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.746 ns ; 6.113 ns ; -; 0.368 ns ; Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[27] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr6|lpm_shiftreg:lpm_shiftreg_component|dffs[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.500 ns ; -; 0.368 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 4.264 ns ; 4.632 ns ; -; 0.370 ns ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe49 ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|external_latency_ffsa[23] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.134 ns ; 1.504 ns ; -; 0.371 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[11] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.124 ns ; 1.495 ns ; -; 0.371 ns ; Video:Fredi_Aschwanden|lpm_ff1:inst9|lpm_ff:lpm_ff_component|dffs[10] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe23 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.127 ns ; 1.498 ns ; -; 0.372 ns ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[3] ; Video:Fredi_Aschwanden|lpm_shiftreg0:sr5|lpm_shiftreg:lpm_shiftreg_component|dffs[4] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.504 ns ; -; 0.373 ns ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|cntr_pmb:wr_ptr|counter_reg_bit[1] ; Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a5~porta_address_reg0 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.502 ns ; 1.875 ns ; -; 0.374 ns ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|dffe1a[2] ; Video:Fredi_Aschwanden|lpm_mux1:inst24|lpm_mux:lpm_mux_component|mux_npe:auto_generated|external_latency_ffsa[15] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.133 ns ; 1.507 ns ; -; 0.374 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC_START ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.706 ns ; 6.080 ns ; -; 0.374 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDTRON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.147 ns ; 1.521 ns ; -; 0.376 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|DPO_OFF ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 5.690 ns ; 6.066 ns ; -; 0.379 ns ; Video:Fredi_Aschwanden|lpm_ff3:inst49|lpm_ff:lpm_ff_component|dffs[15] ; Video:Fredi_Aschwanden|lpm_mux6:inst7|lpm_mux:lpm_mux_component|mux_kpe:auto_generated|dffe32 ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.132 ns ; 1.511 ns ; -; 0.381 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDO_ON ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 3.460 ns ; 3.841 ns ; -; 0.382 ns ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[18] ; Video:Fredi_Aschwanden|lpm_mux0:inst21|lpm_mux:lpm_mux_component|mux_gpe:auto_generated|external_latency_ffsa[50] ; MAIN_CLK ; MAIN_CLK ; 0.000 ns ; 1.135 ns ; 1.517 ns ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; tsu ; -+-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ -; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; -+-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ -; -4.528 ns ; 1.000 ns ; 5.528 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state ; MAIN_CLK ; -; -4.169 ns ; 1.000 ns ; 5.169 ns ; VD[19] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19] ; MAIN_CLK ; -; -4.134 ns ; 1.000 ns ; 5.134 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; -; -4.083 ns ; 1.000 ns ; 5.083 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; -; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; -; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; -; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; -; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; -; -4.051 ns ; 1.000 ns ; 5.051 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; -; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; -; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; -; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; -; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; -; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; -; -4.047 ns ; 1.000 ns ; 5.047 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; -; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; -; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; -; -4.022 ns ; 1.000 ns ; 5.022 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; -; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; -; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; -; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; -; -3.961 ns ; 1.000 ns ; 4.961 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; -; -3.956 ns ; 1.000 ns ; 4.956 ns ; VD[27] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27] ; MAIN_CLK ; -; -3.930 ns ; 1.000 ns ; 4.930 ns ; nINDEX ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; CLK33M ; -; -3.930 ns ; 1.000 ns ; 4.930 ns ; VD[31] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31] ; MAIN_CLK ; -; -3.927 ns ; 1.000 ns ; 4.927 ns ; VD[1] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1] ; MAIN_CLK ; -; -3.927 ns ; 1.000 ns ; 4.927 ns ; VD[9] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9] ; MAIN_CLK ; -; -3.913 ns ; 1.000 ns ; 4.913 ns ; VD[2] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2] ; MAIN_CLK ; -; -3.912 ns ; 1.000 ns ; 4.912 ns ; VD[12] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12] ; MAIN_CLK ; -; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; -; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; -; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; -; -3.907 ns ; 1.000 ns ; 4.907 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; -; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; -; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; -; -3.903 ns ; 1.000 ns ; 4.903 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; -; -3.897 ns ; 1.000 ns ; 4.897 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; -; -3.885 ns ; 1.000 ns ; 4.885 ns ; VD[20] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20] ; MAIN_CLK ; -; -3.883 ns ; 1.000 ns ; 4.883 ns ; VD[25] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25] ; MAIN_CLK ; -; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; -; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; -; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; -; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; -; -3.869 ns ; 1.000 ns ; 4.869 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; -; -3.860 ns ; 1.000 ns ; 4.860 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; -; -3.859 ns ; 1.000 ns ; 4.859 ns ; VD[28] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28] ; MAIN_CLK ; -; -3.855 ns ; 1.000 ns ; 4.855 ns ; VD[22] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22] ; MAIN_CLK ; -; -3.851 ns ; 1.000 ns ; 4.851 ns ; VD[17] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; -; -3.850 ns ; 1.000 ns ; 4.850 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; -; -3.846 ns ; 1.000 ns ; 4.846 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; -; -3.827 ns ; 1.000 ns ; 4.827 ns ; VD[11] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; -; -3.814 ns ; 1.000 ns ; 4.814 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; -; -3.804 ns ; 1.000 ns ; 4.804 ns ; VD[0] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0] ; MAIN_CLK ; -; -3.801 ns ; 1.000 ns ; 4.801 ns ; VD[10] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10] ; MAIN_CLK ; -; -3.796 ns ; 1.000 ns ; 4.796 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_post_state ; MAIN_CLK ; -; -3.794 ns ; 1.000 ns ; 4.794 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|areset_init_state_1 ; MAIN_CLK ; -; -3.794 ns ; 1.000 ns ; 4.794 ns ; MAIN_CLK ; altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|reconfig_wait_state ; MAIN_CLK ; -; -3.783 ns ; 1.000 ns ; 4.783 ns ; VD[14] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14] ; MAIN_CLK ; -; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; -; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; -; -3.768 ns ; 1.000 ns ; 4.768 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; -; -3.765 ns ; 1.000 ns ; 4.765 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|MO ; CLK33M ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[29] ; MAIN_CLK ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[30] ; MAIN_CLK ; -; -3.761 ns ; 1.000 ns ; 4.761 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[31] ; MAIN_CLK ; -; -3.752 ns ; 1.000 ns ; 4.752 ns ; VD[6] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6] ; MAIN_CLK ; -; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; -; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[13] ; MAIN_CLK ; -; -3.748 ns ; 1.000 ns ; 4.748 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[14] ; MAIN_CLK ; -; -3.744 ns ; 1.000 ns ; 4.744 ns ; VD[21] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21] ; MAIN_CLK ; -; -3.742 ns ; 1.000 ns ; 4.742 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; -; -3.740 ns ; 1.000 ns ; 4.740 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; -; -3.740 ns ; 1.000 ns ; 4.740 ns ; VD[16] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16] ; MAIN_CLK ; -; -3.739 ns ; 1.000 ns ; 4.739 ns ; VD[29] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29] ; MAIN_CLK ; -; -3.735 ns ; 1.000 ns ; 4.735 ns ; VD[15] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15] ; MAIN_CLK ; -; -3.708 ns ; 1.000 ns ; 4.708 ns ; VD[26] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26] ; MAIN_CLK ; -; -3.707 ns ; 1.000 ns ; 4.707 ns ; VD[13] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13] ; MAIN_CLK ; -; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; -; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; -; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; -; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; -; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; -; -3.706 ns ; 1.000 ns ; 4.706 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; -; -3.703 ns ; 1.000 ns ; 4.703 ns ; VD[3] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3] ; MAIN_CLK ; -; -3.699 ns ; 1.000 ns ; 4.699 ns ; VD[30] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30] ; MAIN_CLK ; -; -3.694 ns ; 1.000 ns ; 4.694 ns ; VD[24] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; -; -3.691 ns ; 1.000 ns ; 4.691 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; -; -3.684 ns ; 1.000 ns ; 4.684 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; -; -3.684 ns ; 1.000 ns ; 4.684 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; -; -3.680 ns ; 1.000 ns ; 4.680 ns ; FB_AD[30] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; -; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[25] ; MAIN_CLK ; -; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[26] ; MAIN_CLK ; -; -3.654 ns ; 1.000 ns ; 4.654 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[28] ; MAIN_CLK ; -; -3.634 ns ; 1.000 ns ; 4.634 ns ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[0] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[8] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[21] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[23] ; MAIN_CLK ; -; -3.566 ns ; 1.000 ns ; 4.566 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[27] ; MAIN_CLK ; -; -3.471 ns ; 1.000 ns ; 4.471 ns ; VD[4] ; Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[9] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[11] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[18] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[19] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[20] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[22] ; MAIN_CLK ; -; -3.464 ns ; 1.000 ns ; 4.464 ns ; nFB_WR ; Video:Fredi_Aschwanden|lpm_ff0:inst15|lpm_ff:lpm_ff_component|dffs[24] ; MAIN_CLK ; -; -3.386 ns ; 1.000 ns ; 4.386 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[5] ; MAIN_CLK ; -; -3.339 ns ; 1.000 ns ; 4.339 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; -; -3.334 ns ; 1.000 ns ; 4.334 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|CMD_STATE.IDLE ; CLK33M ; -; -3.324 ns ; 1.000 ns ; 4.324 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; -; -3.290 ns ; 1.000 ns ; 4.290 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; -; -3.272 ns ; 1.000 ns ; 4.272 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC ; MAIN_CLK ; -; -3.248 ns ; 1.000 ns ; 4.248 ns ; nFB_WR ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; CLK33M ; -; -3.245 ns ; 1.000 ns ; 4.245 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; -; -3.236 ns ; 1.000 ns ; 4.236 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; -; -3.226 ns ; 1.000 ns ; 4.226 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; -; -3.226 ns ; 1.000 ns ; 4.226 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[17] ; MAIN_CLK ; -; -3.218 ns ; 1.000 ns ; 4.218 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[16] ; MAIN_CLK ; -; -3.214 ns ; 1.000 ns ; 4.214 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.214 ns ; 1.000 ns ; 4.214 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[7] ; MAIN_CLK ; -; -3.211 ns ; 1.000 ns ; 4.211 ns ; FB_SIZE0 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_AC ; MAIN_CLK ; -; -3.208 ns ; 1.000 ns ; 4.208 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; -; -3.206 ns ; 1.000 ns ; 4.206 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; -; -3.203 ns ; 1.000 ns ; 4.203 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.199 ns ; 1.000 ns ; 4.199 ns ; FB_AD[31] ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; -; -3.197 ns ; 1.000 ns ; 4.197 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[3] ; MAIN_CLK ; -; -3.194 ns ; 1.000 ns ; 4.194 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[4] ; MAIN_CLK ; -; -3.193 ns ; 1.000 ns ; 4.193 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; -; -3.190 ns ; 1.000 ns ; 4.190 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[10] ; MAIN_CLK ; -; -3.187 ns ; 1.000 ns ; 4.187 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[15] ; MAIN_CLK ; -; -3.182 ns ; 1.000 ns ; 4.182 ns ; HD_DD ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\FREQUENCY_DECODER:FREQ_AMOUNT[1] ; CLK33M ; -; -3.181 ns ; 1.000 ns ; 4.181 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; -; -3.174 ns ; 1.000 ns ; 4.174 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[12] ; MAIN_CLK ; -; -3.173 ns ; 1.000 ns ; 4.173 ns ; FB_SIZE1 ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10] ; MAIN_CLK ; -; -3.172 ns ; 1.000 ns ; 4.172 ns ; FB_ALE ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ ; MAIN_CLK ; -; -3.171 ns ; 1.000 ns ; 4.171 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|lpm_ff0:inst16|lpm_ff:lpm_ff_component|dffs[5] ; MAIN_CLK ; -; -3.167 ns ; 1.000 ns ; 4.167 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[6] ; MAIN_CLK ; -; -3.162 ns ; 1.000 ns ; 4.162 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[1] ; MAIN_CLK ; -; -3.160 ns ; 1.000 ns ; 4.160 ns ; nFB_WR ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[9] ; MAIN_CLK ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+------------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+----------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; tco ; -+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ -; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; -+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ -; -14.840 ns ; 1.000 ns ; 15.840 ns ; interrupt_handler:nobody|INT_LATCH[8] ; nIRQ[5] ; MAIN_CLK ; -; -14.829 ns ; 1.000 ns ; 15.829 ns ; interrupt_handler:nobody|INT_LATCH[9] ; nIRQ[5] ; MAIN_CLK ; -; -13.764 ns ; 1.000 ns ; 14.764 ns ; interrupt_handler:nobody|INT_LATCH[8] ; FB_AD[8] ; MAIN_CLK ; -; -13.654 ns ; 1.000 ns ; 14.654 ns ; interrupt_handler:nobody|INT_LATCH[9] ; FB_AD[9] ; MAIN_CLK ; -; -13.587 ns ; 1.000 ns ; 14.587 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.587 ns ; 1.000 ns ; 14.587 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.587 ns ; 1.000 ns ; 14.587 ns ; interrupt_handler:nobody|INT_LATCH[8] ; FB_AD[29] ; MAIN_CLK ; -; -13.575 ns ; 1.000 ns ; 14.575 ns ; interrupt_handler:nobody|INT_LATCH[9] ; FB_AD[29] ; MAIN_CLK ; -; -13.493 ns ; 1.000 ns ; 14.493 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[18] ; MAIN_CLK ; -; -13.477 ns ; 1.000 ns ; 14.477 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[18] ; MAIN_CLK ; -; -13.457 ns ; 1.000 ns ; 14.457 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; FB_AD[18] ; MAIN_CLK ; -; -13.418 ns ; 1.000 ns ; 14.418 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.386 ns ; 1.000 ns ; 14.386 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; FB_AD[7] ; MAIN_CLK ; -; -13.358 ns ; 1.000 ns ; 14.358 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[18] ; MAIN_CLK ; -; -13.358 ns ; 1.000 ns ; 14.358 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[18] ; MAIN_CLK ; -; -13.309 ns ; 1.000 ns ; 14.309 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[27] ; MAIN_CLK ; -; -13.294 ns ; 1.000 ns ; 14.294 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[11] ; FB_AD[27] ; MAIN_CLK ; -; -13.259 ns ; 1.000 ns ; 14.259 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.250 ns ; 1.000 ns ; 14.250 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.227 ns ; 1.000 ns ; 14.227 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.207 ns ; 1.000 ns ; 14.207 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[18] ; MAIN_CLK ; -; -13.171 ns ; 1.000 ns ; 14.171 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.170 ns ; 1.000 ns ; 14.170 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[11] ; FB_AD[27] ; MAIN_CLK ; -; -13.157 ns ; 1.000 ns ; 14.157 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[2] ; FB_AD[18] ; MAIN_CLK ; -; -13.028 ns ; 1.000 ns ; 14.028 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[27] ; MAIN_CLK ; -; -13.015 ns ; 1.000 ns ; 14.015 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[2] ; FB_AD[27] ; MAIN_CLK ; -; -12.999 ns ; 1.000 ns ; 13.999 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.921 ns ; 1.000 ns ; 13.921 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.886 ns ; 1.000 ns ; 13.886 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[11] ; FB_AD[27] ; MAIN_CLK ; -; -12.876 ns ; 1.000 ns ; 13.876 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[11] ; FB_AD[27] ; MAIN_CLK ; -; -12.861 ns ; 1.000 ns ; 13.861 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] ; FB_AD[27] ; MAIN_CLK ; -; -12.846 ns ; 1.000 ns ; 13.846 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; FB_AD[27] ; MAIN_CLK ; -; -12.836 ns ; 1.000 ns ; 13.836 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18] ; FB_AD[18] ; MAIN_CLK ; -; -12.823 ns ; 1.000 ns ; 13.823 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.817 ns ; 1.000 ns ; 13.817 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[0] ; FB_AD[27] ; MAIN_CLK ; -; -12.784 ns ; 1.000 ns ; 13.784 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[27] ; MAIN_CLK ; -; -12.732 ns ; 1.000 ns ; 13.732 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[5] ; FB_AD[7] ; MAIN_CLK ; -; -12.620 ns ; 1.000 ns ; 13.620 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; FB_AD[27] ; MAIN_CLK ; -; -12.567 ns ; 1.000 ns ; 13.567 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[3] ; FB_AD[27] ; MAIN_CLK ; -; -12.434 ns ; 1.000 ns ; 13.434 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; FB_AD[7] ; MAIN_CLK ; -; -12.425 ns ; 1.000 ns ; 13.425 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[7] ; MAIN_CLK ; -; -12.404 ns ; 1.000 ns ; 13.404 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; FB_AD[8] ; MAIN_CLK ; -; -12.403 ns ; 1.000 ns ; 13.403 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; FB_AD[7] ; MAIN_CLK ; -; -12.361 ns ; 1.000 ns ; 13.361 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; FB_AD[23] ; MAIN_CLK ; -; -12.361 ns ; 1.000 ns ; 13.361 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; FB_AD[27] ; MAIN_CLK ; -; -12.302 ns ; 1.000 ns ; 13.302 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[4] ; FB_AD[7] ; MAIN_CLK ; -; -12.301 ns ; 1.000 ns ; 13.301 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[27] ; FB_AD[27] ; MAIN_CLK ; -; -12.300 ns ; 1.000 ns ; 13.300 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.286 ns ; 1.000 ns ; 13.286 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; FB_AD[18] ; MAIN_CLK ; -; -12.285 ns ; 1.000 ns ; 13.285 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TCDCR[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.283 ns ; 1.000 ns ; 13.283 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|INTRQ ; FB_AD[7] ; CLK33M ; -; -12.260 ns ; 1.000 ns ; 13.260 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; FB_AD[7] ; MAIN_CLK ; -; -12.241 ns ; 1.000 ns ; 13.241 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_A[5] ; FB_AD[7] ; MAIN_CLK ; -; -12.219 ns ; 1.000 ns ; 13.219 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TACR[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.211 ns ; 1.000 ns ; 13.211 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.205 ns ; 1.000 ns ; 13.205 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[27] ; MAIN_CLK ; -; -12.200 ns ; 1.000 ns ; 13.200 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; FB_AD[7] ; MAIN_CLK ; -; -12.186 ns ; 1.000 ns ; 13.186 ns ; interrupt_handler:nobody|WERTE[2][0] ; FB_AD[18] ; MAIN_CLK ; -; -12.182 ns ; 1.000 ns ; 13.182 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; FB_AD[22] ; MAIN_CLK ; -; -12.177 ns ; 1.000 ns ; 13.177 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[18] ; MAIN_CLK ; -; -12.175 ns ; 1.000 ns ; 13.175 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.173 ns ; 1.000 ns ; 13.173 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[17] ; MAIN_CLK ; -; -12.166 ns ; 1.000 ns ; 13.166 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; FB_AD[18] ; MAIN_CLK ; -; -12.158 ns ; 1.000 ns ; 13.158 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.157 ns ; 1.000 ns ; 13.157 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[17] ; MAIN_CLK ; -; -12.082 ns ; 1.000 ns ; 13.082 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TBCR[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.055 ns ; 1.000 ns ; 13.055 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; FB_AD[21] ; MAIN_CLK ; -; -12.052 ns ; 1.000 ns ; 13.052 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; FB_AD[17] ; MAIN_CLK ; -; -12.039 ns ; 1.000 ns ; 13.039 ns ; interrupt_handler:nobody|ACP_CONF[28] ; FB_AD[7] ; MAIN_CLK ; -; -12.038 ns ; 1.000 ns ; 13.038 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[17] ; MAIN_CLK ; -; -12.022 ns ; 1.000 ns ; 13.022 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_C[5] ; FB_AD[7] ; MAIN_CLK ; -; -12.008 ns ; 1.000 ns ; 13.008 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QB ; MAIN_CLK ; -; -12.005 ns ; 1.000 ns ; 13.005 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_DOUT[2] ; FB_AD[18] ; MAIN_CLK ; -; -12.004 ns ; 1.000 ns ; 13.004 ns ; interrupt_handler:nobody|WERTE[2][62] ; FB_AD[18] ; MAIN_CLK ; -; -11.984 ns ; 1.000 ns ; 12.984 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[27] ; MAIN_CLK ; -; -11.978 ns ; 1.000 ns ; 12.978 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[1] ; YM_QB ; MAIN_CLK ; -; -11.968 ns ; 1.000 ns ; 12.968 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; FB_AD[27] ; MAIN_CLK ; -; -11.957 ns ; 1.000 ns ; 12.957 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[7] ; MAIN_CLK ; -; -11.946 ns ; 1.000 ns ; 12.946 ns ; interrupt_handler:nobody|WERTE[2][42] ; FB_AD[18] ; MAIN_CLK ; -; -11.939 ns ; 1.000 ns ; 12.939 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[17] ; MAIN_CLK ; -; -11.938 ns ; 1.000 ns ; 12.938 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[4] ; YM_QB ; MAIN_CLK ; -; -11.937 ns ; 1.000 ns ; 12.937 ns ; interrupt_handler:nobody|WERTE[2][10] ; FB_AD[18] ; MAIN_CLK ; -; -11.935 ns ; 1.000 ns ; 12.935 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; FB_AD[9] ; MAIN_CLK ; -; -11.933 ns ; 1.000 ns ; 12.933 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FB_AD[18] ; MAIN_CLK ; -; -11.924 ns ; 1.000 ns ; 12.924 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC ; FB_AD[26] ; MAIN_CLK ; -; -11.922 ns ; 1.000 ns ; 12.922 ns ; interrupt_handler:nobody|WERTE[2][58] ; FB_AD[18] ; MAIN_CLK ; -; -11.900 ns ; 1.000 ns ; 12.900 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[17] ; MAIN_CLK ; -; -11.874 ns ; 1.000 ns ; 12.874 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; FB_AD[17] ; MAIN_CLK ; -; -11.871 ns ; 1.000 ns ; 12.871 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[20] ; MAIN_CLK ; -; -11.867 ns ; 1.000 ns ; 12.867 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; FB_AD[18] ; MAIN_CLK ; -; -11.859 ns ; 1.000 ns ; 12.859 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[7] ; MAIN_CLK ; -; -11.857 ns ; 1.000 ns ; 12.857 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; FB_AD[20] ; MAIN_CLK ; -; -11.845 ns ; 1.000 ns ; 12.845 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[17] ; MAIN_CLK ; -; -11.842 ns ; 1.000 ns ; 12.842 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; FB_AD[20] ; MAIN_CLK ; -; -11.834 ns ; 1.000 ns ; 12.834 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[20] ; MAIN_CLK ; -; -11.831 ns ; 1.000 ns ; 12.831 ns ; interrupt_handler:nobody|WERTE[2][4] ; FB_AD[18] ; MAIN_CLK ; -; -11.813 ns ; 1.000 ns ; 12.813 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; FB_AD[18] ; MAIN_CLK ; -; -11.794 ns ; 1.000 ns ; 12.794 ns ; interrupt_handler:nobody|WERTE[2][43] ; FB_AD[18] ; MAIN_CLK ; -; -11.787 ns ; 1.000 ns ; 12.787 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FB_AD[18] ; MAIN_CLK ; -; -11.775 ns ; 1.000 ns ; 12.775 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S2 ; FB_AD[7] ; MAIN_CLK ; -; -11.774 ns ; 1.000 ns ; 12.774 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[18] ; FB_AD[27] ; MAIN_CLK ; -; -11.769 ns ; 1.000 ns ; 12.769 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[18] ; MAIN_CLK ; -; -11.762 ns ; 1.000 ns ; 12.762 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[4] ; FB_AD[20] ; MAIN_CLK ; -; -11.751 ns ; 1.000 ns ; 12.751 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[5] ; YM_QC ; MAIN_CLK ; -; -11.747 ns ; 1.000 ns ; 12.747 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[7] ; FB_AD[23] ; MAIN_CLK ; -; -11.746 ns ; 1.000 ns ; 12.746 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[27] ; FB_AD[27] ; MAIN_CLK ; -; -11.736 ns ; 1.000 ns ; 12.736 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[7] ; MAIN_CLK ; -; -11.727 ns ; 1.000 ns ; 12.727 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[7] ; FB_AD[23] ; MAIN_CLK ; -; -11.725 ns ; 1.000 ns ; 12.725 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_STATE.VECTOR_OUT ; FB_AD[7] ; MAIN_CLK ; -; -11.724 ns ; 1.000 ns ; 12.724 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[2] ; YM_QC ; MAIN_CLK ; -; -11.721 ns ; 1.000 ns ; 12.721 ns ; interrupt_handler:nobody|WERTE[5][8] ; FB_AD[21] ; MAIN_CLK ; -; -11.717 ns ; 1.000 ns ; 12.717 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[23] ; MAIN_CLK ; -; -11.710 ns ; 1.000 ns ; 12.710 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7] ; FB_AD[9] ; MAIN_CLK ; -; -11.709 ns ; 1.000 ns ; 12.709 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FB_AD[18] ; MAIN_CLK ; -; -11.708 ns ; 1.000 ns ; 12.708 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IPRB[5] ; FB_AD[7] ; MAIN_CLK ; -; -11.700 ns ; 1.000 ns ; 12.700 ns ; interrupt_handler:nobody|WERTE[2][2] ; FB_AD[18] ; MAIN_CLK ; -; -11.694 ns ; 1.000 ns ; 12.694 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC ; FB_AD[28] ; MAIN_CLK ; -; -11.693 ns ; 1.000 ns ; 12.693 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; FB_AD[9] ; MAIN_CLK ; -; -11.692 ns ; 1.000 ns ; 12.692 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S0 ; FB_AD[18] ; MAIN_CLK ; -; -11.680 ns ; 1.000 ns ; 12.680 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[1] ; FB_AD[17] ; MAIN_CLK ; -; -11.675 ns ; 1.000 ns ; 12.675 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[23] ; MAIN_CLK ; -; -11.673 ns ; 1.000 ns ; 12.673 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_B[5] ; FB_AD[7] ; MAIN_CLK ; -; -11.659 ns ; 1.000 ns ; 12.659 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[7] ; FB_AD[23] ; MAIN_CLK ; -; -11.649 ns ; 1.000 ns ; 12.649 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; FB_AD[23] ; MAIN_CLK ; -; -11.648 ns ; 1.000 ns ; 12.648 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[25] ; MAIN_CLK ; -; -11.646 ns ; 1.000 ns ; 12.646 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[20] ; MAIN_CLK ; -; -11.640 ns ; 1.000 ns ; 12.640 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[7] ; FB_AD[23] ; MAIN_CLK ; -; -11.633 ns ; 1.000 ns ; 12.633 ns ; interrupt_handler:nobody|WERTE[2][38] ; FB_AD[18] ; MAIN_CLK ; -; -11.631 ns ; 1.000 ns ; 12.631 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[19] ; MAIN_CLK ; -; -11.628 ns ; 1.000 ns ; 12.628 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; FB_AD[17] ; MAIN_CLK ; -; -11.628 ns ; 1.000 ns ; 12.628 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[19] ; FB_AD[27] ; MAIN_CLK ; -; -11.627 ns ; 1.000 ns ; 12.627 ns ; interrupt_handler:nobody|WERTE[2][63] ; FB_AD[18] ; MAIN_CLK ; -; -11.620 ns ; 1.000 ns ; 12.620 ns ; interrupt_handler:nobody|WERTE[2][61] ; FB_AD[18] ; MAIN_CLK ; -; -11.620 ns ; 1.000 ns ; 12.620 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FB_AD[18] ; MAIN_CLK ; -; -11.619 ns ; 1.000 ns ; 12.619 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[0] ; YM_QB ; MAIN_CLK ; -; -11.618 ns ; 1.000 ns ; 12.618 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FB_AD[18] ; MAIN_CLK ; -; -11.616 ns ; 1.000 ns ; 12.616 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[20] ; MAIN_CLK ; -; -11.616 ns ; 1.000 ns ; 12.616 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; FB_AD[25] ; MAIN_CLK ; -; -11.608 ns ; 1.000 ns ; 12.608 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[19] ; MAIN_CLK ; -; -11.607 ns ; 1.000 ns ; 12.607 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[21] ; MAIN_CLK ; -; -11.595 ns ; 1.000 ns ; 12.595 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FB_AD[27] ; MAIN_CLK ; -; -11.592 ns ; 1.000 ns ; 12.592 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[19] ; FB_AD[20] ; MAIN_CLK ; -; -11.592 ns ; 1.000 ns ; 12.592 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[18] ; MAIN_CLK ; -; -11.589 ns ; 1.000 ns ; 12.589 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[3] ; YM_QA ; MAIN_CLK ; -; -11.588 ns ; 1.000 ns ; 12.588 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2] ; FB_AD[18] ; MAIN_CLK ; -; -11.588 ns ; 1.000 ns ; 12.588 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] ; FB_AD[18] ; MAIN_CLK ; -; -11.583 ns ; 1.000 ns ; 12.583 ns ; interrupt_handler:nobody|WERTE[2][57] ; FB_AD[18] ; MAIN_CLK ; -; -11.582 ns ; 1.000 ns ; 12.582 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[22] ; MAIN_CLK ; -; -11.579 ns ; 1.000 ns ; 12.579 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QA ; MAIN_CLK ; -; -11.578 ns ; 1.000 ns ; 12.578 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; FB_AD[21] ; MAIN_CLK ; -; -11.576 ns ; 1.000 ns ; 12.576 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[7] ; FB_AD[23] ; MAIN_CLK ; -; -11.576 ns ; 1.000 ns ; 12.576 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[22] ; MAIN_CLK ; -; -11.567 ns ; 1.000 ns ; 12.567 ns ; interrupt_handler:nobody|RTC_ADR[1] ; FB_AD[22] ; MAIN_CLK ; -; -11.559 ns ; 1.000 ns ; 12.559 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|DMA_MODUS[6] ; FB_AD[23] ; MAIN_CLK ; -; -11.552 ns ; 1.000 ns ; 12.552 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|\NOISEGENERATOR:N_SHFT[16] ; YM_QC ; MAIN_CLK ; -; -11.550 ns ; 1.000 ns ; 12.550 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[17] ; FB_AD[27] ; MAIN_CLK ; -; -11.545 ns ; 1.000 ns ; 12.545 ns ; interrupt_handler:nobody|WERTE[2][31] ; FB_AD[18] ; MAIN_CLK ; -; -11.544 ns ; 1.000 ns ; 12.544 ns ; interrupt_handler:nobody|WERTE[2][6] ; FB_AD[18] ; MAIN_CLK ; -; -11.543 ns ; 1.000 ns ; 12.543 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2] ; FB_AD[18] ; MAIN_CLK ; -; -11.542 ns ; 1.000 ns ; 12.542 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[2] ; FB_AD[18] ; MAIN_CLK ; -; -11.541 ns ; 1.000 ns ; 12.541 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_CS ; FB_AD[23] ; MAIN_CLK ; -; -11.540 ns ; 1.000 ns ; 12.540 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_TIMERS:I_TIMERS|TIMER_R_D[4] ; FB_AD[20] ; MAIN_CLK ; -; -11.540 ns ; 1.000 ns ; 12.540 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5] ; FB_AD[21] ; MAIN_CLK ; -; -11.537 ns ; 1.000 ns ; 12.537 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; FB_AD[3] ; MAIN_CLK ; -; -11.531 ns ; 1.000 ns ; 12.531 ns ; interrupt_handler:nobody|WERTE[2][45] ; FB_AD[18] ; MAIN_CLK ; -; -11.527 ns ; 1.000 ns ; 12.527 ns ; interrupt_handler:nobody|WERTE[2][7] ; FB_AD[18] ; MAIN_CLK ; -; -11.527 ns ; 1.000 ns ; 12.527 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; FB_AD[25] ; MAIN_CLK ; -; -11.526 ns ; 1.000 ns ; 12.526 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; FB_AD[20] ; MAIN_CLK ; -; -11.526 ns ; 1.000 ns ; 12.526 ns ; interrupt_handler:nobody|RTC_ADR[3] ; FB_AD[23] ; MAIN_CLK ; -; -11.526 ns ; 1.000 ns ; 12.526 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[23] ; MAIN_CLK ; -; -11.508 ns ; 1.000 ns ; 12.508 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|LEVEL_C[3] ; FB_AD[27] ; MAIN_CLK ; -; -11.507 ns ; 1.000 ns ; 12.507 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[7] ; FB_AD[18] ; MAIN_CLK ; -; -11.505 ns ; 1.000 ns ; 12.505 ns ; interrupt_handler:nobody|RTC_ADR[2] ; FB_AD[23] ; MAIN_CLK ; -; -11.504 ns ; 1.000 ns ; 12.504 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; FB_AD[27] ; MAIN_CLK ; -; -11.502 ns ; 1.000 ns ; 12.502 ns ; interrupt_handler:nobody|WERTE[2][60] ; FB_AD[18] ; MAIN_CLK ; -; -11.502 ns ; 1.000 ns ; 12.502 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; FB_AD[26] ; MAIN_CLK ; -; -11.495 ns ; 1.000 ns ; 12.495 ns ; interrupt_handler:nobody|WERTE[2][53] ; FB_AD[18] ; MAIN_CLK ; -; -11.492 ns ; 1.000 ns ; 12.492 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[8] ; FB_AD[18] ; MAIN_CLK ; -; -11.488 ns ; 1.000 ns ; 12.488 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; FB_AD[3] ; MAIN_CLK ; -; -11.487 ns ; 1.000 ns ; 12.487 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[7] ; MAIN_CLK ; -; -11.480 ns ; 1.000 ns ; 12.480 ns ; interrupt_handler:nobody|RTC_ADR[5] ; FB_AD[23] ; MAIN_CLK ; -; -11.480 ns ; 1.000 ns ; 12.480 ns ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; FB_AD[21] ; MAIN_CLK ; -; -11.479 ns ; 1.000 ns ; 12.479 ns ; interrupt_handler:nobody|WERTE[2][36] ; FB_AD[18] ; MAIN_CLK ; -; -11.478 ns ; 1.000 ns ; 12.478 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[2] ; YM_QB ; MAIN_CLK ; -; -11.470 ns ; 1.000 ns ; 12.470 ns ; interrupt_handler:nobody|WERTE[2][15] ; FB_AD[18] ; MAIN_CLK ; -; -11.461 ns ; 1.000 ns ; 12.461 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[11] ; FB_AD[27] ; MAIN_CLK ; -; -11.460 ns ; 1.000 ns ; 12.460 ns ; interrupt_handler:nobody|WERTE[2][8] ; FB_AD[18] ; MAIN_CLK ; -; -11.459 ns ; 1.000 ns ; 12.459 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[12] ; FB_AD[27] ; MAIN_CLK ; -; -11.455 ns ; 1.000 ns ; 12.455 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|CTRL_REG[0] ; YM_QA ; MAIN_CLK ; -; -11.455 ns ; 1.000 ns ; 12.455 ns ; interrupt_handler:nobody|RTC_ADR[4] ; FB_AD[22] ; MAIN_CLK ; -; -11.451 ns ; 1.000 ns ; 12.451 ns ; interrupt_handler:nobody|WERTE[2][50] ; FB_AD[18] ; MAIN_CLK ; -; -11.447 ns ; 1.000 ns ; 12.447 ns ; interrupt_handler:nobody|WERTE[2][52] ; FB_AD[18] ; MAIN_CLK ; -; -11.444 ns ; 1.000 ns ; 12.444 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[5] ; FB_AD[27] ; MAIN_CLK ; -; -11.443 ns ; 1.000 ns ; 12.443 ns ; interrupt_handler:nobody|RTC_ADR[0] ; FB_AD[20] ; MAIN_CLK ; -; -11.441 ns ; 1.000 ns ; 12.441 ns ; lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[13] ; FB_AD[18] ; MAIN_CLK ; -; -11.435 ns ; 1.000 ns ; 12.435 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S3 ; FB_AD[18] ; MAIN_CLK ; -; -11.433 ns ; 1.000 ns ; 12.433 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|WF2149IP_WAVE:I_PSG_WAVE|VOL_ENV[4] ; YM_QB ; MAIN_CLK ; -; -11.432 ns ; 1.000 ns ; 12.432 ns ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|IMRB[5] ; FB_AD[7] ; MAIN_CLK ; -; -11.431 ns ; 1.000 ns ; 12.431 ns ; Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|FR_S1 ; FB_AD[20] ; MAIN_CLK ; -; -11.429 ns ; 1.000 ns ; 12.429 ns ; interrupt_handler:nobody|WERTE[2][55] ; FB_AD[18] ; MAIN_CLK ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+-----------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; tpd ; -+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ -; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ; -+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ -; -11.944 ns ; 1.000 ns ; 12.944 ns ; nFB_CS1 ; FB_AD[18] ; -; -11.849 ns ; 1.000 ns ; 12.849 ns ; FB_SIZE0 ; FB_AD[27] ; -; -11.785 ns ; 1.000 ns ; 12.785 ns ; nFB_CS1 ; FB_AD[27] ; -; -11.694 ns ; 1.000 ns ; 12.694 ns ; nFB_CS1 ; FB_AD[7] ; -; -11.672 ns ; 1.000 ns ; 12.672 ns ; FB_SIZE1 ; FB_AD[27] ; -; -11.625 ns ; 1.000 ns ; 12.625 ns ; nFB_WR ; FB_AD[7] ; -; -11.514 ns ; 1.000 ns ; 12.514 ns ; FB_SIZE0 ; FB_AD[18] ; -; -11.464 ns ; 1.000 ns ; 12.464 ns ; IDE_INT ; FB_AD[7] ; -; -11.450 ns ; 1.000 ns ; 12.450 ns ; SRD[11] ; FB_AD[27] ; -; -11.438 ns ; 1.000 ns ; 12.438 ns ; nFB_OE ; FB_AD[27] ; -; -11.420 ns ; 1.000 ns ; 12.420 ns ; nFB_CS2 ; FB_AD[27] ; -; -11.399 ns ; 1.000 ns ; 12.399 ns ; nFB_WR ; FB_AD[27] ; -; -11.376 ns ; 1.000 ns ; 12.376 ns ; nFB_WR ; FB_AD[18] ; -; -11.337 ns ; 1.000 ns ; 12.337 ns ; FB_SIZE1 ; FB_AD[18] ; -; -11.243 ns ; 1.000 ns ; 12.243 ns ; nFB_CS2 ; FB_AD[18] ; -; -10.918 ns ; 1.000 ns ; 11.918 ns ; nFB_CS1 ; FB_AD[20] ; -; -10.824 ns ; 1.000 ns ; 11.824 ns ; nFB_CS2 ; FB_AD[7] ; -; -10.814 ns ; 1.000 ns ; 11.814 ns ; FB_SIZE0 ; FB_AD[7] ; -; -10.798 ns ; 1.000 ns ; 11.798 ns ; nFB_OE ; FB_AD[7] ; -; -10.779 ns ; 1.000 ns ; 11.779 ns ; CTS ; FB_AD[18] ; -; -10.758 ns ; 1.000 ns ; 11.758 ns ; FB_SIZE1 ; FB_AD[7] ; -; -10.658 ns ; 1.000 ns ; 11.658 ns ; MAIN_CLK ; FB_AD[27] ; -; -10.631 ns ; 1.000 ns ; 11.631 ns ; nFB_OE ; FB_AD[18] ; -; -10.578 ns ; 1.000 ns ; 11.578 ns ; MAIN_CLK ; FB_AD[7] ; -; -10.573 ns ; 1.000 ns ; 11.573 ns ; nFB_CS2 ; FB_AD[20] ; -; -10.561 ns ; 1.000 ns ; 11.561 ns ; nFB_CS1 ; FB_AD[6] ; -; -10.549 ns ; 1.000 ns ; 11.549 ns ; FB_SIZE0 ; FB_AD[20] ; -; -10.543 ns ; 1.000 ns ; 11.543 ns ; nFB_CS1 ; FB_AD[9] ; -; -10.529 ns ; 1.000 ns ; 11.529 ns ; FB_SIZE0 ; FB_AD[23] ; -; -10.521 ns ; 1.000 ns ; 11.521 ns ; nFB_CS1 ; FB_AD[23] ; -; -10.471 ns ; 1.000 ns ; 11.471 ns ; FB_SIZE1 ; FB_AD[20] ; -; -10.451 ns ; 1.000 ns ; 11.451 ns ; FB_SIZE1 ; FB_AD[23] ; -; -10.425 ns ; 1.000 ns ; 11.425 ns ; nFB_WR ; FB_AD[9] ; -; -10.420 ns ; 1.000 ns ; 11.420 ns ; nFB_CS1 ; FB_AD[17] ; -; -10.415 ns ; 1.000 ns ; 11.415 ns ; nFB_CS1 ; FB_AD[25] ; -; -10.412 ns ; 1.000 ns ; 11.412 ns ; nFB_CS1 ; FB_AD[21] ; -; -10.370 ns ; 1.000 ns ; 11.370 ns ; nFB_OE ; FB_AD[20] ; -; -10.364 ns ; 1.000 ns ; 11.364 ns ; nFB_WR ; FB_AD[25] ; -; -10.362 ns ; 1.000 ns ; 11.362 ns ; nFB_CS1 ; FB_AD[26] ; -; -10.361 ns ; 1.000 ns ; 11.361 ns ; nFB_WR ; FB_AD[20] ; -; -10.335 ns ; 1.000 ns ; 11.335 ns ; nFB_CS2 ; FB_AD[23] ; -; -10.318 ns ; 1.000 ns ; 11.318 ns ; nFB_CS2 ; FB_AD[21] ; -; -10.317 ns ; 1.000 ns ; 11.317 ns ; nFB_WR ; FB_AD[22] ; -; -10.312 ns ; 1.000 ns ; 11.312 ns ; nFB_CS1 ; FB_AD[22] ; -; -10.311 ns ; 1.000 ns ; 11.311 ns ; nFB_WR ; FB_AD[26] ; -; -10.291 ns ; 1.000 ns ; 11.291 ns ; nFB_WR ; FB_AD[23] ; -; -10.278 ns ; 1.000 ns ; 11.278 ns ; FB_SIZE0 ; FB_AD[17] ; -; -10.277 ns ; 1.000 ns ; 11.277 ns ; MAIN_CLK ; FB_AD[18] ; -; -10.221 ns ; 1.000 ns ; 11.221 ns ; FB_SIZE0 ; FB_AD[29] ; -; -10.220 ns ; 1.000 ns ; 11.220 ns ; nFB_CS2 ; FB_AD[22] ; -; -10.178 ns ; 1.000 ns ; 11.178 ns ; FB_SIZE0 ; FB_AD[19] ; -; -10.146 ns ; 1.000 ns ; 11.146 ns ; FB_SIZE0 ; FB_AD[31] ; -; -10.136 ns ; 1.000 ns ; 11.136 ns ; nFB_CS1 ; FB_AD[24] ; -; -10.123 ns ; 1.000 ns ; 11.123 ns ; nFB_CS1 ; FB_AD[19] ; -; -10.101 ns ; 1.000 ns ; 11.101 ns ; FB_SIZE1 ; FB_AD[17] ; -; -10.085 ns ; 1.000 ns ; 11.085 ns ; nFB_WR ; FB_AD[24] ; -; -10.081 ns ; 1.000 ns ; 11.081 ns ; nFB_CS1 ; FB_AD[16] ; -; -10.077 ns ; 1.000 ns ; 11.077 ns ; nFB_CS2 ; FB_AD[19] ; -; -10.077 ns ; 1.000 ns ; 11.077 ns ; FB_SIZE0 ; FB_AD[21] ; -; -10.076 ns ; 1.000 ns ; 11.076 ns ; FB_SIZE1 ; FB_AD[19] ; -; -10.074 ns ; 1.000 ns ; 11.074 ns ; SRD[9] ; FB_AD[25] ; -; -10.070 ns ; 1.000 ns ; 11.070 ns ; nFB_CS1 ; FB_AD[29] ; -; -10.061 ns ; 1.000 ns ; 11.061 ns ; nFB_OE ; FB_AD[21] ; -; -10.060 ns ; 1.000 ns ; 11.060 ns ; nFB_WR ; FB_AD[21] ; -; -10.051 ns ; 1.000 ns ; 11.051 ns ; nFB_WR ; FB_AD[19] ; -; -10.044 ns ; 1.000 ns ; 11.044 ns ; FB_SIZE1 ; FB_AD[29] ; -; -10.041 ns ; 1.000 ns ; 11.041 ns ; FB_SIZE0 ; FB_AD[30] ; -; -10.021 ns ; 1.000 ns ; 11.021 ns ; FB_SIZE1 ; FB_AD[21] ; -; -10.019 ns ; 1.000 ns ; 11.019 ns ; nFB_WR ; FB_AD[29] ; -; -10.004 ns ; 1.000 ns ; 11.004 ns ; nFB_WR ; FB_AD[6] ; -; -9.969 ns ; 1.000 ns ; 10.969 ns ; FB_SIZE1 ; FB_AD[31] ; -; -9.951 ns ; 1.000 ns ; 10.951 ns ; FB_SIZE0 ; FB_AD[22] ; -; -9.938 ns ; 1.000 ns ; 10.938 ns ; nFB_CS2 ; FB_AD[26] ; -; -9.918 ns ; 1.000 ns ; 10.918 ns ; nFB_CS1 ; FB_AD[31] ; -; -9.914 ns ; 1.000 ns ; 10.914 ns ; nFB_CS2 ; FB_AD[17] ; -; -9.903 ns ; 1.000 ns ; 10.903 ns ; FB_SIZE0 ; FB_AD[25] ; -; -9.899 ns ; 1.000 ns ; 10.899 ns ; IDE_INT ; FB_AD[21] ; -; -9.876 ns ; 1.000 ns ; 10.876 ns ; nFB_CS2 ; FB_AD[31] ; -; -9.864 ns ; 1.000 ns ; 10.864 ns ; FB_SIZE1 ; FB_AD[30] ; -; -9.835 ns ; 1.000 ns ; 10.835 ns ; LP_D[3] ; FB_AD[27] ; -; -9.823 ns ; 1.000 ns ; 10.823 ns ; nFB_WR ; FB_AD[17] ; -; -9.820 ns ; 1.000 ns ; 10.820 ns ; nFB_CS2 ; FB_AD[30] ; -; -9.813 ns ; 1.000 ns ; 10.813 ns ; MAIN_CLK ; FB_AD[20] ; -; -9.802 ns ; 1.000 ns ; 10.802 ns ; nFB_CS2 ; FB_AD[25] ; -; -9.801 ns ; 1.000 ns ; 10.801 ns ; FB_SIZE1 ; FB_AD[25] ; -; -9.792 ns ; 1.000 ns ; 10.792 ns ; nFB_CS2 ; FB_AD[29] ; -; -9.791 ns ; 1.000 ns ; 10.791 ns ; nFB_OE ; FB_AD[25] ; -; -9.778 ns ; 1.000 ns ; 10.778 ns ; FB_SIZE1 ; FB_AD[22] ; -; -9.770 ns ; 1.000 ns ; 10.770 ns ; nFB_OE ; FB_AD[23] ; -; -9.763 ns ; 1.000 ns ; 10.763 ns ; nFB_CS1 ; FB_AD[2] ; -; -9.750 ns ; 1.000 ns ; 10.750 ns ; nFB_WR ; FB_AD[31] ; -; -9.729 ns ; 1.000 ns ; 10.729 ns ; FB_SIZE0 ; FB_AD[9] ; -; -9.729 ns ; 1.000 ns ; 10.729 ns ; nFB_CS1 ; FB_AD[30] ; -; -9.701 ns ; 1.000 ns ; 10.701 ns ; MAIN_CLK ; FB_AD[21] ; -; -9.699 ns ; 1.000 ns ; 10.699 ns ; FB_SIZE0 ; FB_AD[24] ; -; -9.692 ns ; 1.000 ns ; 10.692 ns ; nFB_OE ; FB_AD[22] ; -; -9.685 ns ; 1.000 ns ; 10.685 ns ; nFB_OE ; FB_AD[31] ; -; -9.684 ns ; 1.000 ns ; 10.684 ns ; nFB_OE ; FB_AD[19] ; -; -9.671 ns ; 1.000 ns ; 10.671 ns ; nFB_OE ; FB_AD[17] ; -; -9.634 ns ; 1.000 ns ; 10.634 ns ; nFB_CS2 ; FB_AD[24] ; -; -9.630 ns ; 1.000 ns ; 10.630 ns ; SRD[2] ; FB_AD[18] ; -; -9.629 ns ; 1.000 ns ; 10.629 ns ; nFB_WR ; FB_AD[30] ; -; -9.628 ns ; 1.000 ns ; 10.628 ns ; nFB_CS2 ; FB_AD[9] ; -; -9.627 ns ; 1.000 ns ; 10.627 ns ; FB_SIZE1 ; FB_AD[9] ; -; -9.600 ns ; 1.000 ns ; 10.600 ns ; nFB_CS1 ; FB_AD[28] ; -; -9.597 ns ; 1.000 ns ; 10.597 ns ; FB_SIZE1 ; FB_AD[24] ; -; -9.593 ns ; 1.000 ns ; 10.593 ns ; nFB_WR ; FB_AD[16] ; -; -9.574 ns ; 1.000 ns ; 10.574 ns ; FB_SIZE0 ; FB_AD[28] ; -; -9.572 ns ; 1.000 ns ; 10.572 ns ; DCD ; FB_AD[17] ; -; -9.565 ns ; 1.000 ns ; 10.565 ns ; nFB_OE ; FB_AD[24] ; -; -9.559 ns ; 1.000 ns ; 10.559 ns ; nFB_WR ; FB_AD[8] ; -; -9.554 ns ; 1.000 ns ; 10.554 ns ; nFB_CS1 ; FB_AD[8] ; -; -9.521 ns ; 1.000 ns ; 10.521 ns ; nFB_CS1 ; FB_AD[3] ; -; -9.491 ns ; 1.000 ns ; 10.491 ns ; nFB_WR ; FB_AD[28] ; -; -9.477 ns ; 1.000 ns ; 10.477 ns ; nFB_CS2 ; FB_AD[3] ; -; -9.455 ns ; 1.000 ns ; 10.455 ns ; FB_SIZE0 ; FB_AD[26] ; -; -9.418 ns ; 1.000 ns ; 10.418 ns ; RI ; FB_AD[22] ; -; -9.410 ns ; 1.000 ns ; 10.410 ns ; nFB_CS1 ; FB_AD[5] ; -; -9.398 ns ; 1.000 ns ; 10.398 ns ; MAIN_CLK ; FB_AD[26] ; -; -9.397 ns ; 1.000 ns ; 10.397 ns ; FB_SIZE1 ; FB_AD[28] ; -; -9.394 ns ; 1.000 ns ; 10.394 ns ; SRD[8] ; FB_AD[24] ; -; -9.381 ns ; 1.000 ns ; 10.381 ns ; nFB_OE ; FB_AD[26] ; -; -9.380 ns ; 1.000 ns ; 10.380 ns ; nFB_CS2 ; FB_AD[11] ; -; -9.371 ns ; 1.000 ns ; 10.371 ns ; FB_SIZE0 ; FB_AD[4] ; -; -9.370 ns ; 1.000 ns ; 10.370 ns ; nFB_WR ; FB_AD[5] ; -; -9.355 ns ; 1.000 ns ; 10.355 ns ; nFB_OE ; FB_AD[4] ; -; -9.344 ns ; 1.000 ns ; 10.344 ns ; nFB_CS2 ; FB_AD[5] ; -; -9.333 ns ; 1.000 ns ; 10.333 ns ; FB_SIZE0 ; FB_AD[16] ; -; -9.328 ns ; 1.000 ns ; 10.328 ns ; FB_SIZE0 ; FB_AD[2] ; -; -9.315 ns ; 1.000 ns ; 10.315 ns ; FB_SIZE1 ; FB_AD[4] ; -; -9.312 ns ; 1.000 ns ; 10.312 ns ; FB_SIZE0 ; FB_AD[3] ; -; -9.312 ns ; 1.000 ns ; 10.312 ns ; nFB_OE ; FB_AD[2] ; -; -9.309 ns ; 1.000 ns ; 10.309 ns ; MAIN_CLK ; FB_AD[22] ; -; -9.305 ns ; 1.000 ns ; 10.305 ns ; MAIN_CLK ; FB_AD[25] ; -; -9.296 ns ; 1.000 ns ; 10.296 ns ; nFB_OE ; FB_AD[3] ; -; -9.278 ns ; 1.000 ns ; 10.278 ns ; FB_SIZE1 ; FB_AD[26] ; -; -9.275 ns ; 1.000 ns ; 10.275 ns ; nFB_WR ; FB_AD[2] ; -; -9.273 ns ; 1.000 ns ; 10.273 ns ; nFB_CS1 ; nFB_TA ; -; -9.272 ns ; 1.000 ns ; 10.272 ns ; FB_SIZE1 ; FB_AD[2] ; -; -9.271 ns ; 1.000 ns ; 10.271 ns ; nFB_CS2 ; FB_AD[16] ; -; -9.262 ns ; 1.000 ns ; 10.262 ns ; nFB_OE ; FB_AD[28] ; -; -9.256 ns ; 1.000 ns ; 10.256 ns ; FB_SIZE1 ; FB_AD[3] ; -; -9.245 ns ; 1.000 ns ; 10.245 ns ; nFB_CS2 ; FB_AD[2] ; -; -9.231 ns ; 1.000 ns ; 10.231 ns ; CLK33M ; VB[7] ; -; -9.210 ns ; 1.000 ns ; 10.210 ns ; nFB_CS2 ; FB_AD[4] ; -; -9.203 ns ; 1.000 ns ; 10.203 ns ; nFB_OE ; FB_AD[9] ; -; -9.201 ns ; 1.000 ns ; 10.201 ns ; nFB_CS2 ; FB_AD[8] ; -; -9.199 ns ; 1.000 ns ; 10.199 ns ; MAIN_CLK ; FB_AD[31] ; -; -9.198 ns ; 1.000 ns ; 10.198 ns ; CLK33M ; VSYNC_PAD ; -; -9.193 ns ; 1.000 ns ; 10.193 ns ; CLK33M ; VR[6] ; -; -9.191 ns ; 1.000 ns ; 10.191 ns ; CLK33M ; VG[3] ; -; -9.176 ns ; 1.000 ns ; 10.176 ns ; nFB_CS1 ; FB_AD[4] ; -; -9.168 ns ; 1.000 ns ; 10.168 ns ; LP_D[7] ; FB_AD[31] ; -; -9.156 ns ; 1.000 ns ; 10.156 ns ; FB_SIZE1 ; FB_AD[16] ; -; -9.145 ns ; 1.000 ns ; 10.145 ns ; MAIN_CLK ; FB_AD[23] ; -; -9.145 ns ; 1.000 ns ; 10.145 ns ; nFB_CS2 ; FB_AD[28] ; -; -9.112 ns ; 1.000 ns ; 10.112 ns ; nFB_WR ; FB_AD[3] ; -; -9.099 ns ; 1.000 ns ; 10.099 ns ; MAIN_CLK ; FB_AD[19] ; -; -9.089 ns ; 1.000 ns ; 10.089 ns ; nFB_OE ; FB_AD[5] ; -; -9.088 ns ; 1.000 ns ; 10.088 ns ; SRD[5] ; FB_AD[21] ; -; -9.081 ns ; 1.000 ns ; 10.081 ns ; nFB_OE ; FB_AD[16] ; -; -9.079 ns ; 1.000 ns ; 10.079 ns ; MAIN_CLK ; FB_AD[24] ; -; -9.047 ns ; 1.000 ns ; 10.047 ns ; nFB_CS2 ; FB_AD[10] ; -; -9.019 ns ; 1.000 ns ; 10.019 ns ; nFB_CS2 ; FB_AD[13] ; -; -9.004 ns ; 1.000 ns ; 10.004 ns ; FB_SIZE0 ; FB_AD[8] ; -; -8.984 ns ; 1.000 ns ; 9.984 ns ; LP_D[5] ; FB_AD[29] ; -; -8.935 ns ; 1.000 ns ; 9.935 ns ; SRD[4] ; FB_AD[20] ; -; -8.933 ns ; 1.000 ns ; 9.933 ns ; nFB_OE ; FB_AD[30] ; -; -8.927 ns ; 1.000 ns ; 9.927 ns ; SRD[10] ; FB_AD[26] ; -; -8.926 ns ; 1.000 ns ; 9.926 ns ; nFB_OE ; FB_AD[8] ; -; -8.924 ns ; 1.000 ns ; 9.924 ns ; nFB_CS2 ; FB_AD[6] ; -; -8.921 ns ; 1.000 ns ; 9.921 ns ; nFB_WR ; FB_AD[4] ; -; -8.916 ns ; 1.000 ns ; 9.916 ns ; LP_D[6] ; FB_AD[30] ; -; -8.909 ns ; 1.000 ns ; 9.909 ns ; nFB_CS2 ; FB_AD[15] ; -; -8.902 ns ; 1.000 ns ; 9.902 ns ; FB_SIZE1 ; FB_AD[8] ; -; -8.896 ns ; 1.000 ns ; 9.896 ns ; FB_SIZE0 ; FB_AD[5] ; -; -8.876 ns ; 1.000 ns ; 9.876 ns ; nFB_CS2 ; FB_AD[14] ; -; -8.873 ns ; 1.000 ns ; 9.873 ns ; LP_BUSY ; FB_AD[16] ; -; -8.869 ns ; 1.000 ns ; 9.869 ns ; MAIN_CLK ; FB_AD[4] ; -; -8.864 ns ; 1.000 ns ; 9.864 ns ; nFB_OE ; FB_AD[29] ; -; -8.852 ns ; 1.000 ns ; 9.852 ns ; nFB_CS2 ; FB_AD[12] ; -; -8.840 ns ; 1.000 ns ; 9.840 ns ; FB_SIZE1 ; FB_AD[5] ; -; -8.826 ns ; 1.000 ns ; 9.826 ns ; MAIN_CLK ; FB_AD[2] ; -; -8.819 ns ; 1.000 ns ; 9.819 ns ; DCD ; FB_AD[3] ; -; -8.810 ns ; 1.000 ns ; 9.810 ns ; MAIN_CLK ; FB_AD[3] ; -; -8.804 ns ; 1.000 ns ; 9.804 ns ; nFB_OE ; FB_AD[13] ; -; -8.803 ns ; 1.000 ns ; 9.803 ns ; SRD[7] ; FB_AD[23] ; -; -8.780 ns ; 1.000 ns ; 9.780 ns ; nFB_CS2 ; FB_AD[1] ; -; -8.776 ns ; 1.000 ns ; 9.776 ns ; MAIN_CLK ; FB_AD[28] ; -; -8.715 ns ; 1.000 ns ; 9.715 ns ; FB_SIZE0 ; FB_AD[12] ; -; -8.715 ns ; 1.000 ns ; 9.715 ns ; FB_SIZE0 ; FB_AD[11] ; -; -8.699 ns ; 1.000 ns ; 9.699 ns ; FB_SIZE0 ; BA[0] ; -; -8.699 ns ; 1.000 ns ; 9.699 ns ; nFB_OE ; FB_AD[12] ; -; -8.699 ns ; 1.000 ns ; 9.699 ns ; nFB_OE ; FB_AD[11] ; -; -8.672 ns ; 1.000 ns ; 9.672 ns ; FB_SIZE0 ; FB_AD[6] ; -; -8.660 ns ; 1.000 ns ; 9.660 ns ; RI ; FB_AD[8] ; -; -8.659 ns ; 1.000 ns ; 9.659 ns ; FB_SIZE1 ; FB_AD[12] ; -; -8.659 ns ; 1.000 ns ; 9.659 ns ; FB_SIZE1 ; FB_AD[11] ; -; -8.656 ns ; 1.000 ns ; 9.656 ns ; nFB_OE ; FB_AD[6] ; -; -8.651 ns ; 1.000 ns ; 9.651 ns ; FB_SIZE0 ; FB_AD[0] ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+-----------------+----------+-----------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; th ; -+-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ -; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; -+-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ -; -0.401 ns ; 1.000 ns ; 1.401 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] ; MAIN_CLK ; -; -0.386 ns ; 1.000 ns ; 1.386 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[9] ; MAIN_CLK ; -; -0.383 ns ; 1.000 ns ; 1.383 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[5] ; MAIN_CLK ; -; -0.383 ns ; 1.000 ns ; 1.383 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[21] ; MAIN_CLK ; -; -0.370 ns ; 1.000 ns ; 1.370 ns ; CTS ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[2] ; MAIN_CLK ; -; -0.339 ns ; 1.000 ns ; 1.339 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[2] ; MAIN_CLK ; -; -0.333 ns ; 1.000 ns ; 1.333 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[22] ; MAIN_CLK ; -; -0.328 ns ; 1.000 ns ; 1.328 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[9] ; MAIN_CLK ; -; -0.325 ns ; 1.000 ns ; 1.325 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[11] ; MAIN_CLK ; -; -0.325 ns ; 1.000 ns ; 1.325 ns ; RI ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|INT_SRC_EDGE[14] ; MAIN_CLK ; -; -0.321 ns ; 1.000 ns ; 1.321 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[5] ; MAIN_CLK ; -; -0.320 ns ; 1.000 ns ; 1.320 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[25] ; MAIN_CLK ; -; -0.310 ns ; 1.000 ns ; 1.310 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[5] ; MAIN_CLK ; -; -0.302 ns ; 1.000 ns ; 1.302 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[11] ; MAIN_CLK ; -; -0.302 ns ; 1.000 ns ; 1.302 ns ; CTS ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[2] ; MAIN_CLK ; -; -0.293 ns ; 1.000 ns ; 1.293 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[2] ; MAIN_CLK ; -; -0.285 ns ; 1.000 ns ; 1.285 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[6] ; MAIN_CLK ; -; -0.283 ns ; 1.000 ns ; 1.283 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[9] ; MAIN_CLK ; -; -0.275 ns ; 1.000 ns ; 1.275 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[17] ; MAIN_CLK ; -; -0.272 ns ; 1.000 ns ; 1.272 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[8] ; MAIN_CLK ; -; -0.269 ns ; 1.000 ns ; 1.269 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[4] ; MAIN_CLK ; -; -0.265 ns ; 1.000 ns ; 1.265 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[4] ; MAIN_CLK ; -; -0.252 ns ; 1.000 ns ; 1.252 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[3] ; MAIN_CLK ; -; -0.247 ns ; 1.000 ns ; 1.247 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[8] ; MAIN_CLK ; -; -0.246 ns ; 1.000 ns ; 1.246 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[26] ; MAIN_CLK ; -; -0.245 ns ; 1.000 ns ; 1.245 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[23] ; MAIN_CLK ; -; -0.238 ns ; 1.000 ns ; 1.238 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[16] ; MAIN_CLK ; -; -0.235 ns ; 1.000 ns ; 1.235 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[3] ; MAIN_CLK ; -; -0.235 ns ; 1.000 ns ; 1.235 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[8] ; MAIN_CLK ; -; -0.227 ns ; 1.000 ns ; 1.227 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[18] ; MAIN_CLK ; -; -0.226 ns ; 1.000 ns ; 1.226 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[10] ; MAIN_CLK ; -; -0.224 ns ; 1.000 ns ; 1.224 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[18] ; MAIN_CLK ; -; -0.223 ns ; 1.000 ns ; 1.223 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[0] ; MAIN_CLK ; -; -0.222 ns ; 1.000 ns ; 1.222 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[0] ; MAIN_CLK ; -; -0.216 ns ; 1.000 ns ; 1.216 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[10] ; MAIN_CLK ; -; -0.208 ns ; 1.000 ns ; 1.208 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[8] ; MAIN_CLK ; -; -0.202 ns ; 1.000 ns ; 1.202 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[22] ; MAIN_CLK ; -; -0.197 ns ; 1.000 ns ; 1.197 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[9] ; MAIN_CLK ; -; -0.194 ns ; 1.000 ns ; 1.194 ns ; FB_AD[15] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[15] ; MAIN_CLK ; -; -0.191 ns ; 1.000 ns ; 1.191 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[5] ; MAIN_CLK ; -; -0.189 ns ; 1.000 ns ; 1.189 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[6] ; MAIN_CLK ; -; -0.187 ns ; 1.000 ns ; 1.187 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[1] ; MAIN_CLK ; -; -0.181 ns ; 1.000 ns ; 1.181 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[4] ; MAIN_CLK ; -; -0.179 ns ; 1.000 ns ; 1.179 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[3] ; MAIN_CLK ; -; -0.173 ns ; 1.000 ns ; 1.173 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[18] ; MAIN_CLK ; -; -0.172 ns ; 1.000 ns ; 1.172 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[0] ; MAIN_CLK ; -; -0.166 ns ; 1.000 ns ; 1.166 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[10] ; MAIN_CLK ; -; -0.165 ns ; 1.000 ns ; 1.165 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[10] ; MAIN_CLK ; -; -0.162 ns ; 1.000 ns ; 1.162 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[6] ; MAIN_CLK ; -; -0.159 ns ; 1.000 ns ; 1.159 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[19] ; MAIN_CLK ; -; -0.159 ns ; 1.000 ns ; 1.159 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[27] ; MAIN_CLK ; -; -0.154 ns ; 1.000 ns ; 1.154 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[19] ; MAIN_CLK ; -; -0.151 ns ; 1.000 ns ; 1.151 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[9] ; MAIN_CLK ; -; -0.149 ns ; 1.000 ns ; 1.149 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[26] ; MAIN_CLK ; -; -0.146 ns ; 1.000 ns ; 1.146 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[1] ; MAIN_CLK ; -; -0.145 ns ; 1.000 ns ; 1.145 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[5] ; MAIN_CLK ; -; -0.142 ns ; 1.000 ns ; 1.142 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[9] ; MAIN_CLK ; -; -0.141 ns ; 1.000 ns ; 1.141 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[10] ; MAIN_CLK ; -; -0.140 ns ; 1.000 ns ; 1.140 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[4] ; MAIN_CLK ; -; -0.137 ns ; 1.000 ns ; 1.137 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[3] ; MAIN_CLK ; -; -0.134 ns ; 1.000 ns ; 1.134 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[7] ; MAIN_CLK ; -; -0.130 ns ; 1.000 ns ; 1.130 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[22] ; MAIN_CLK ; -; -0.130 ns ; 1.000 ns ; 1.130 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[10] ; MAIN_CLK ; -; -0.125 ns ; 1.000 ns ; 1.125 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[7] ; MAIN_CLK ; -; -0.121 ns ; 1.000 ns ; 1.121 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[0] ; MAIN_CLK ; -; -0.121 ns ; 1.000 ns ; 1.121 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[2] ; MAIN_CLK ; -; -0.113 ns ; 1.000 ns ; 1.113 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[5] ; MAIN_CLK ; -; -0.109 ns ; 1.000 ns ; 1.109 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[7] ; MAIN_CLK ; -; -0.108 ns ; 1.000 ns ; 1.108 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[2] ; MAIN_CLK ; -; -0.099 ns ; 1.000 ns ; 1.099 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[10] ; MAIN_CLK ; -; -0.094 ns ; 1.000 ns ; 1.094 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[19] ; MAIN_CLK ; -; -0.092 ns ; 1.000 ns ; 1.092 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[9] ; MAIN_CLK ; -; -0.090 ns ; 1.000 ns ; 1.090 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[10] ; MAIN_CLK ; -; -0.089 ns ; 1.000 ns ; 1.089 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[23] ; MAIN_CLK ; -; -0.087 ns ; 1.000 ns ; 1.087 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[3] ; MAIN_CLK ; -; -0.086 ns ; 1.000 ns ; 1.086 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[5] ; MAIN_CLK ; -; -0.085 ns ; 1.000 ns ; 1.085 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[9] ; MAIN_CLK ; -; -0.081 ns ; 1.000 ns ; 1.081 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; -; -0.079 ns ; 1.000 ns ; 1.079 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[24] ; MAIN_CLK ; -; -0.078 ns ; 1.000 ns ; 1.078 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[9] ; MAIN_CLK ; -; -0.077 ns ; 1.000 ns ; 1.077 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[9] ; MAIN_CLK ; -; -0.075 ns ; 1.000 ns ; 1.075 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[2] ; MAIN_CLK ; -; -0.074 ns ; 1.000 ns ; 1.074 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[21] ; MAIN_CLK ; -; -0.070 ns ; 1.000 ns ; 1.070 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[1] ; MAIN_CLK ; -; -0.070 ns ; 1.000 ns ; 1.070 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[14] ; MAIN_CLK ; -; -0.068 ns ; 1.000 ns ; 1.068 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[5] ; MAIN_CLK ; -; -0.068 ns ; 1.000 ns ; 1.068 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; -; -0.065 ns ; 1.000 ns ; 1.065 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[14] ; MAIN_CLK ; -; -0.064 ns ; 1.000 ns ; 1.064 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[7] ; MAIN_CLK ; -; -0.064 ns ; 1.000 ns ; 1.064 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[10] ; MAIN_CLK ; -; -0.062 ns ; 1.000 ns ; 1.062 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[27] ; MAIN_CLK ; -; -0.059 ns ; 1.000 ns ; 1.059 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[3] ; MAIN_CLK ; -; -0.057 ns ; 1.000 ns ; 1.057 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[4] ; MAIN_CLK ; -; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[18] ; MAIN_CLK ; -; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[6] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[6] ; MAIN_CLK ; -; -0.055 ns ; 1.000 ns ; 1.055 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[25] ; MAIN_CLK ; -; -0.053 ns ; 1.000 ns ; 1.053 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[9] ; MAIN_CLK ; -; -0.047 ns ; 1.000 ns ; 1.047 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[3] ; MAIN_CLK ; -; -0.047 ns ; 1.000 ns ; 1.047 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[9] ; MAIN_CLK ; -; -0.046 ns ; 1.000 ns ; 1.046 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[7] ; MAIN_CLK ; -; -0.042 ns ; 1.000 ns ; 1.042 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[18] ; MAIN_CLK ; -; -0.042 ns ; 1.000 ns ; 1.042 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[8] ; MAIN_CLK ; -; -0.039 ns ; 1.000 ns ; 1.039 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[21] ; MAIN_CLK ; -; -0.037 ns ; 1.000 ns ; 1.037 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[7] ; MAIN_CLK ; -; -0.037 ns ; 1.000 ns ; 1.037 ns ; FB_AD[4] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[4] ; MAIN_CLK ; -; -0.035 ns ; 1.000 ns ; 1.035 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[14] ; MAIN_CLK ; -; -0.033 ns ; 1.000 ns ; 1.033 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[20] ; MAIN_CLK ; -; -0.028 ns ; 1.000 ns ; 1.028 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[4] ; MAIN_CLK ; -; -0.026 ns ; 1.000 ns ; 1.026 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[2] ; MAIN_CLK ; -; -0.022 ns ; 1.000 ns ; 1.022 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[0] ; MAIN_CLK ; -; -0.018 ns ; 1.000 ns ; 1.018 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[7] ; MAIN_CLK ; -; -0.018 ns ; 1.000 ns ; 1.018 ns ; FB_AD[12] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[12] ; MAIN_CLK ; -; -0.017 ns ; 1.000 ns ; 1.017 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[17] ; MAIN_CLK ; -; -0.017 ns ; 1.000 ns ; 1.017 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[7] ; MAIN_CLK ; -; -0.011 ns ; 1.000 ns ; 1.011 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[3] ; MAIN_CLK ; -; -0.010 ns ; 1.000 ns ; 1.010 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[3] ; MAIN_CLK ; -; -0.004 ns ; 1.000 ns ; 1.004 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[3] ; MAIN_CLK ; -; 0.007 ns ; 1.000 ns ; 0.993 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[2] ; MAIN_CLK ; -; 0.008 ns ; 1.000 ns ; 0.992 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[25] ; MAIN_CLK ; -; 0.009 ns ; 1.000 ns ; 0.991 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[10] ; MAIN_CLK ; -; 0.009 ns ; 1.000 ns ; 0.991 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VSS[10] ; MAIN_CLK ; -; 0.010 ns ; 1.000 ns ; 0.990 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[25] ; MAIN_CLK ; -; 0.015 ns ; 1.000 ns ; 0.985 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[2] ; MAIN_CLK ; -; 0.018 ns ; 1.000 ns ; 0.982 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[2] ; MAIN_CLK ; -; 0.021 ns ; 1.000 ns ; 0.979 ns ; FB_AD[1] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[1] ; MAIN_CLK ; -; 0.022 ns ; 1.000 ns ; 0.978 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[2] ; MAIN_CLK ; -; 0.027 ns ; 1.000 ns ; 0.973 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[7] ; MAIN_CLK ; -; 0.033 ns ; 1.000 ns ; 0.967 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[2] ; MAIN_CLK ; -; 0.036 ns ; 1.000 ns ; 0.964 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[6] ; MAIN_CLK ; -; 0.042 ns ; 1.000 ns ; 0.958 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[8] ; MAIN_CLK ; -; 0.044 ns ; 1.000 ns ; 0.956 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[0] ; MAIN_CLK ; -; 0.045 ns ; 1.000 ns ; 0.955 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[22] ; MAIN_CLK ; -; 0.045 ns ; 1.000 ns ; 0.955 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[10] ; MAIN_CLK ; -; 0.046 ns ; 1.000 ns ; 0.954 ns ; FB_AD[14] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[14] ; MAIN_CLK ; -; 0.047 ns ; 1.000 ns ; 0.953 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[3] ; MAIN_CLK ; -; 0.049 ns ; 1.000 ns ; 0.951 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[6] ; MAIN_CLK ; -; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[14] ; MAIN_CLK ; -; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[5] ; MAIN_CLK ; -; 0.049 ns ; 1.000 ns ; 0.951 ns ; VD[5] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[5] ; MAIN_CLK ; -; 0.050 ns ; 1.000 ns ; 0.950 ns ; VD[14] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[14] ; MAIN_CLK ; -; 0.050 ns ; 1.000 ns ; 0.950 ns ; RI ; FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[14] ; MAIN_CLK ; -; 0.054 ns ; 1.000 ns ; 0.946 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[3] ; MAIN_CLK ; -; 0.054 ns ; 1.000 ns ; 0.946 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBB[2] ; MAIN_CLK ; -; 0.055 ns ; 1.000 ns ; 0.945 ns ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[29] ; MAIN_CLK ; -; 0.055 ns ; 1.000 ns ; 0.945 ns ; VD[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[4] ; MAIN_CLK ; -; 0.057 ns ; 1.000 ns ; 0.943 ns ; VD[4] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[4] ; MAIN_CLK ; -; 0.064 ns ; 1.000 ns ; 0.936 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[20] ; MAIN_CLK ; -; 0.078 ns ; 1.000 ns ; 0.922 ns ; FB_AD[18] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VR_FRQ[2] ; MAIN_CLK ; -; 0.079 ns ; 1.000 ns ; 0.921 ns ; FB_AD[19] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[3] ; MAIN_CLK ; -; 0.079 ns ; 1.000 ns ; 0.921 ns ; VD[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] ; MAIN_CLK ; -; 0.079 ns ; 1.000 ns ; 0.921 ns ; VD[8] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[8] ; MAIN_CLK ; -; 0.081 ns ; 1.000 ns ; 0.919 ns ; VD[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[7] ; MAIN_CLK ; -; 0.082 ns ; 1.000 ns ; 0.918 ns ; VD[7] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[7] ; MAIN_CLK ; -; 0.091 ns ; 1.000 ns ; 0.909 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB[1] ; MAIN_CLK ; -; 0.098 ns ; 1.000 ns ; 0.902 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[3] ; MAIN_CLK ; -; 0.106 ns ; 1.000 ns ; 0.894 ns ; FB_AD[25] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[9] ; MAIN_CLK ; -; 0.107 ns ; 1.000 ns ; 0.893 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[16] ; MAIN_CLK ; -; 0.109 ns ; 1.000 ns ; 0.891 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[0] ; MAIN_CLK ; -; 0.110 ns ; 1.000 ns ; 0.890 ns ; FB_AD[27] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[27] ; MAIN_CLK ; -; 0.114 ns ; 1.000 ns ; 0.886 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; -; 0.119 ns ; 1.000 ns ; 0.881 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[21] ; MAIN_CLK ; -; 0.125 ns ; 1.000 ns ; 0.875 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[4] ; MAIN_CLK ; -; 0.125 ns ; 1.000 ns ; 0.875 ns ; FB_AD[5] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[5] ; MAIN_CLK ; -; 0.128 ns ; 1.000 ns ; 0.872 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HL[2] ; MAIN_CLK ; -; 0.131 ns ; 1.000 ns ; 0.869 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[21] ; MAIN_CLK ; -; 0.131 ns ; 1.000 ns ; 0.869 ns ; FB_AD[29] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[29] ; MAIN_CLK ; -; 0.132 ns ; 1.000 ns ; 0.868 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; -; 0.133 ns ; 1.000 ns ; 0.867 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[8] ; MAIN_CLK ; -; 0.136 ns ; 1.000 ns ; 0.864 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VBE[0] ; MAIN_CLK ; -; 0.148 ns ; 1.000 ns ; 0.852 ns ; FB_AD[9] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VH[9] ; MAIN_CLK ; -; 0.149 ns ; 1.000 ns ; 0.851 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[6] ; MAIN_CLK ; -; 0.151 ns ; 1.000 ns ; 0.849 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HSS[0] ; MAIN_CLK ; -; 0.151 ns ; 1.000 ns ; 0.849 ns ; FB_AD[2] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[2] ; MAIN_CLK ; -; 0.158 ns ; 1.000 ns ; 0.842 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[7] ; MAIN_CLK ; -; 0.159 ns ; 1.000 ns ; 0.841 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[7] ; MAIN_CLK ; -; 0.159 ns ; 1.000 ns ; 0.841 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[22] ; MAIN_CLK ; -; 0.161 ns ; 1.000 ns ; 0.839 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[4] ; MAIN_CLK ; -; 0.163 ns ; 1.000 ns ; 0.837 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[0] ; MAIN_CLK ; -; 0.168 ns ; 1.000 ns ; 0.832 ns ; FB_AD[7] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[7] ; MAIN_CLK ; -; 0.170 ns ; 1.000 ns ; 0.830 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; -; 0.170 ns ; 1.000 ns ; 0.830 ns ; FB_AD[22] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDE[6] ; MAIN_CLK ; -; 0.172 ns ; 1.000 ns ; 0.828 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[8] ; MAIN_CLK ; -; 0.178 ns ; 1.000 ns ; 0.822 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[10] ; MAIN_CLK ; -; 0.180 ns ; 1.000 ns ; 0.820 ns ; FB_AD[10] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[10] ; MAIN_CLK ; -; 0.181 ns ; 1.000 ns ; 0.819 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[1] ; MAIN_CLK ; -; 0.186 ns ; 1.000 ns ; 0.814 ns ; FB_AD[0] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[0] ; MAIN_CLK ; -; 0.188 ns ; 1.000 ns ; 0.812 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|FALCON_SHIFT_MODE[0] ; MAIN_CLK ; -; 0.191 ns ; 1.000 ns ; 0.809 ns ; FB_AD[26] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[26] ; MAIN_CLK ; -; 0.195 ns ; 1.000 ns ; 0.805 ns ; FB_AD[23] ; Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ram_block1a0~porta_datain_reg0 ; MAIN_CLK ; -; 0.198 ns ; 1.000 ns ; 0.802 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBB[5] ; MAIN_CLK ; -; 0.201 ns ; 1.000 ns ; 0.799 ns ; FB_AD[8] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_VL[8] ; MAIN_CLK ; -; 0.202 ns ; 1.000 ns ; 0.798 ns ; FB_AD[17] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HHT[1] ; MAIN_CLK ; -; 0.209 ns ; 1.000 ns ; 0.791 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VFT[4] ; MAIN_CLK ; -; 0.213 ns ; 1.000 ns ; 0.787 ns ; FB_AD[24] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ST_SHIFT_MODE[0] ; MAIN_CLK ; -; 0.216 ns ; 1.000 ns ; 0.784 ns ; FB_AD[20] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CCR[20] ; MAIN_CLK ; -; 0.220 ns ; 1.000 ns ; 0.780 ns ; VD[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[26] ; MAIN_CLK ; -; 0.221 ns ; 1.000 ns ; 0.779 ns ; VD[26] ; Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_h[26] ; MAIN_CLK ; -; 0.228 ns ; 1.000 ns ; 0.772 ns ; FB_AD[16] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VDB[0] ; MAIN_CLK ; -; 0.228 ns ; 1.000 ns ; 0.772 ns ; FB_AD[21] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDE[5] ; MAIN_CLK ; -; 0.233 ns ; 1.000 ns ; 0.767 ns ; FB_AD[3] ; Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ATARI_HH[3] ; MAIN_CLK ; -; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; -+-----------------------------------------+-----------------------------------------------------+-----------+-----------+-----------------------------------------------------------------------------------------------------------------------------------------------+----------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Board Trace Model Assignments ; -+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ -; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; -+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ -; CLK24M576 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_STR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; CLK25M ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nACSI_ACK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nACSI_RESET ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nACSI_CS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_A1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSCSI_ACK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSCSI_ATN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; MIDI_OLR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; MIDI_TLR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; TxD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; RTS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; DTR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; AMKB_TX ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IDE_RES ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIDE_CS0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIDE_CS1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIDE_WR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIDE_RD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nCF_CS0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nCF_CS1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nROM3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nROM4 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nRP_UDS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nRP_LDS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSDSEL ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nWR_GATE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nWR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; YM_QA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; YM_QB ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; YM_QC ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SD_CLK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; DSA_D ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nVWE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nVCAS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nVRAS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nVCS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nPD_VGA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; TIN0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSRCS ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSRBLE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSRBHE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSRWE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nDREQ1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LED_FPGA_OK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSROE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VCKE ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nFB_TA ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nDDR_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; DDR_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VSYNC_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; HSYNC_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nBLANK_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSYNC ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nMOT_ON ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSTEP_DIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSTEP ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; CLKUSB ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LPDIR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; BA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; BA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIRQ[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIRQ[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIRQ[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIRQ[4] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIRQ[3] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nIRQ[2] ; 3.0-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VA[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VB[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDM[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDM[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDM[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDM[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VG[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[7] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[6] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[5] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[4] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[3] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[2] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[1] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VR[0] ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[31] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[30] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[29] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[28] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[27] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[26] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[25] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[24] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[23] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[22] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[21] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[20] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[19] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[18] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; FB_AD[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[31] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[30] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[29] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[28] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[27] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[26] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[25] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[24] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[23] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[22] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[21] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[20] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[19] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[18] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[17] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[16] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[15] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[14] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[13] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[12] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[11] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[10] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VD[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDQS[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDQS[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDQS[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; VDQS[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[17] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[16] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; IO[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[15] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[14] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[13] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[12] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[11] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[10] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[9] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[8] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SRD[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_PAR ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSCSI_SEL ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSCSI_BUSY ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; nSCSI_RST ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SD_CMD_D1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ACSI_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; LP_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[7] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[6] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[5] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[4] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[3] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[2] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[1] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; SCSI_D[0] ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; -+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+ - - -+----------------------------------------------------------------------------+ -; Input Transition Times ; -+-------------------------+--------------+-----------------+-----------------+ -; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; -+-------------------------+--------------+-----------------+-----------------+ -; nFB_BURST ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nACSI_DRQ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nACSI_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_DRQ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_MSG ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nDCHG ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_DATA0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_DATA1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_DATA2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_CARD_DEDECT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_WP ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nDACK0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; WP_CF_CARD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_C_D ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_I_O ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nFB_CS3 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; TOUT0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nMASTER ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[31] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[30] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[29] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[28] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[27] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[26] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[25] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[24] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[23] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[22] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[21] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[20] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[19] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[18] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_AD[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; VD[31] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[30] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[29] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[28] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[27] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[26] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[25] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[24] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[23] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[22] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[21] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[20] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[19] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[18] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[17] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[16] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[15] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[14] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[13] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[12] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[11] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[10] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[9] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[8] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[7] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[6] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[5] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[4] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VD[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VDQS[3] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VDQS[2] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VDQS[1] ; 2.5 V ; 2000 ps ; 2000 ps ; -; VDQS[0] ; 2.5 V ; 2000 ps ; 2000 ps ; -; IO[17] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[16] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IO[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[15] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[14] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[13] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[12] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[11] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[10] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[9] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[8] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SRD[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_PAR ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_SEL ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_BUSY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nSCSI_RST ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_CD_DATA3 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SD_CMD_D1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ACSI_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[7] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[6] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[5] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[4] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[3] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[2] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[1] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; SCSI_D[0] ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nRSTO_MCF ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nFB_WR ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nFB_CS1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_SIZE1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_SIZE0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; FB_ALE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nFB_CS2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; MAIN_CLK ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nDACK1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nFB_OE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IDE_RDY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; CLK33M ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; HD_DD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nINDEX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; RxD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nWP ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; LP_BUSY ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; DCD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; CTS ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; TRACK00 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; IDE_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; RI ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nPCI_INTD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nPCI_INTC ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nPCI_INTB ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nPCI_INTA ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; DVI_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; E0_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; PIC_INT ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; PIC_AMKB_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; MIDI_IN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; nRD_DATA ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; AMKB_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; -; ~ALTERA_DEV_OE~ ; 2.5 V ; 2000 ps ; 2000 ps ; -; ~ALTERA_DEV_CLRn~ ; 2.5 V ; 2000 ps ; 2000 ps ; -+-------------------------+--------------+-----------------+-----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Slow Corner Signal Integrity Metrics ; -+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; CLK24M576 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_STR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; CLK25M ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; -; nACSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nACSI_RESET ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nACSI_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_A1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nSCSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nSCSI_ATN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; MIDI_OLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; -; MIDI_TLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; TxD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; RTS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; DTR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; AMKB_TX ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.36e-006 V ; 3.09 V ; -0.013 V ; 0.103 V ; 0.224 V ; 1.59e-009 s ; 1.71e-009 s ; Yes ; Yes ; 3.08 V ; 3.36e-006 V ; 3.09 V ; -0.013 V ; 0.103 V ; 0.224 V ; 1.59e-009 s ; 1.71e-009 s ; Yes ; Yes ; -; IDE_RES ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; -; nIDE_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nIDE_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nIDE_WR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nIDE_RD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nCF_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nCF_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nROM3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nROM4 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nRP_UDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nRP_LDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0394 V ; 0.292 V ; 0.188 V ; 9.15e-010 s ; 8.35e-010 s ; No ; Yes ; -; nSDSEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nWR_GATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; nWR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; YM_QA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; YM_QB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; YM_QC ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; DSA_D ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nVWE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; nVCAS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; nVRAS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; nVCS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; -; nPD_VGA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; TIN0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; -; nSRCS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nSRBLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nSRBHE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nSRWE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nDREQ1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LED_FPGA_OK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.97e-006 V ; 2.34 V ; -0.00258 V ; 0.168 V ; 0.069 V ; 1.53e-009 s ; 1.92e-009 s ; No ; Yes ; 2.32 V ; 1.97e-006 V ; 2.34 V ; -0.00258 V ; 0.168 V ; 0.069 V ; 1.53e-009 s ; 1.92e-009 s ; No ; Yes ; -; nSROE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; VCKE ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; nFB_TA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nDDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; DDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; -; HSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; nBLANK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; nSYNC ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 6.97e-007 V ; 2.86 V ; -0.0234 V ; 0.145 V ; 0.061 V ; 4.67e-010 s ; 4.98e-010 s ; Yes ; Yes ; 2.8 V ; 6.97e-007 V ; 2.86 V ; -0.0234 V ; 0.145 V ; 0.061 V ; 4.67e-010 s ; 4.98e-010 s ; Yes ; Yes ; -; nMOT_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nSTEP_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; nSTEP ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; CLKUSB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; LPDIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; -; nIRQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nIRQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nIRQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; -; nIRQ[4] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; -; nIRQ[3] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; -; nIRQ[2] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; 2.8 V ; 1.1e-006 V ; 2.84 V ; -0.0267 V ; 0.263 V ; 0.124 V ; 7.35e-010 s ; 8.02e-010 s ; Yes ; Yes ; -; VA[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; -; VA[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VA[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VA[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VA[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VA[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; -; VB[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; -; VB[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VB[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VB[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VB[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VB[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VB[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VB[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VDM[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; -; VDM[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VDM[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; -; VDM[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VG[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VG[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VG[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VG[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VG[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; -; VG[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VG[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VG[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.81 V ; -0.00874 V ; 0.219 V ; 0.11 V ; 1.91e-009 s ; 2.08e-009 s ; Yes ; Yes ; -; VR[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; VR[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; 2.8 V ; 6.88e-007 V ; 2.86 V ; -0.0441 V ; 0.132 V ; 0.083 V ; 4.56e-010 s ; 4.87e-010 s ; Yes ; Yes ; -; FB_AD[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; FB_AD[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; FB_AD[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; FB_AD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; FB_AD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; VD[31] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[30] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; -; VD[29] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[28] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[27] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[26] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[25] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[24] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[23] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[22] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.33 V ; -0.00282 V ; 0.119 V ; 0.046 V ; 2.08e-009 s ; 2.71e-009 s ; Yes ; Yes ; -; VD[21] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[20] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[19] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[18] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[17] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[16] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VD[15] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[14] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[13] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; -; VD[12] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[11] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[10] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.37 V ; -0.00683 V ; 0.081 V ; 0.016 V ; 4.14e-010 s ; 5.19e-010 s ; Yes ; Yes ; -; VD[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.33 V ; -0.00279 V ; 0.14 V ; 0.06 V ; 2.15e-009 s ; 2.83e-009 s ; Yes ; Yes ; -; VD[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VD[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VDQS[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VDQS[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; 2.32 V ; 6.14e-007 V ; 2.36 V ; -0.00551 V ; 0.142 V ; 0.014 V ; 4.9e-010 s ; 6.6e-010 s ; Yes ; Yes ; -; VDQS[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; VDQS[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; 2.32 V ; 9.13e-007 V ; 2.36 V ; -0.00797 V ; 0.096 V ; 0.016 V ; 2.7e-010 s ; 3.71e-010 s ; Yes ; Yes ; -; IO[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; IO[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; IO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; IO[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; SRD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SRD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; SCSI_PAR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nSCSI_SEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nSCSI_BUSY ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; nSCSI_RST ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SD_CMD_D1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; ACSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; -; ACSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ACSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.08 V ; -0.0041 V ; 0.274 V ; 0.267 V ; 5.67e-009 s ; 4.62e-009 s ; No ; Yes ; -; ACSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; LP_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; 3.08 V ; 3.08e-006 V ; 3.08 V ; -0.00548 V ; 0.305 V ; 0.267 V ; 5.3e-009 s ; 4.39e-009 s ; Yes ; Yes ; -; LP_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; LP_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; 3.08 V ; 3.08e-006 V ; 3.13 V ; -0.0541 V ; 0.237 V ; 0.168 V ; 6.67e-010 s ; 6.12e-010 s ; No ; No ; -; SCSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; SCSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; 3.08 V ; 2.06e-006 V ; 3.12 V ; -0.0308 V ; 0.224 V ; 0.218 V ; 1.32e-009 s ; 1.07e-009 s ; No ; Yes ; -; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 s ; 0 s ; 2.8 V ; 1.43e-006 V ; 2.84 V ; -0.0141 V ; 0.183 V ; 0.066 V ; 8.84e-010 s ; 1.02e-009 s ; No ; Yes ; 2.8 V ; 1.43e-006 V ; 2.84 V ; -0.0141 V ; 0.183 V ; 0.066 V ; 8.84e-010 s ; 1.02e-009 s ; No ; Yes ; -+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fast Corner Signal Integrity Metrics ; -+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; -+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ -; CLK24M576 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_STR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; CLK25M ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; -; nACSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nACSI_RESET ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nACSI_CS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_A1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nSCSI_ACK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nSCSI_ATN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; MIDI_OLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; -; MIDI_TLR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; TxD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; RTS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; DTR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; AMKB_TX ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.46 V ; 2.1e-007 V ; 3.5 V ; -0.042 V ; 0.297 V ; 0.24 V ; 1.12e-009 s ; 1.29e-009 s ; No ; No ; 3.46 V ; 2.1e-007 V ; 3.5 V ; -0.042 V ; 0.297 V ; 0.24 V ; 1.12e-009 s ; 1.29e-009 s ; No ; No ; -; IDE_RES ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; -; nIDE_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nIDE_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nIDE_WR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nIDE_RD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nCF_CS0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nCF_CS1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nROM3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nROM4 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nRP_UDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nRP_LDS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; 3.46 V ; 1.29e-007 V ; 3.57 V ; -0.0649 V ; 0.332 V ; 0.165 V ; 6.78e-010 s ; 6.19e-010 s ; No ; Yes ; -; nSDSEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nWR_GATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; nWR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; YM_QA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; YM_QB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; YM_QC ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SD_CLK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; DSA_D ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nVWE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; nVCAS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; nVRAS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; nVCS ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; -; nPD_VGA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; TIN0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; -; nSRCS ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nSRBLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nSRBHE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nSRWE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nDREQ1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LED_FPGA_OK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 7.2e-008 V ; 2.68 V ; -0.0147 V ; 0.295 V ; 0.167 V ; 9.36e-010 s ; 1.3e-009 s ; No ; Yes ; 2.62 V ; 7.2e-008 V ; 2.68 V ; -0.0147 V ; 0.295 V ; 0.167 V ; 9.36e-010 s ; 1.3e-009 s ; No ; Yes ; -; nSROE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; VCKE ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; nFB_TA ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nDDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; DDR_CLK ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; -; HSYNC_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; nBLANK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; PIXEL_CLK_PAD ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; nSYNC ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 3.66e-008 V ; 3.29 V ; -0.0256 V ; 0.236 V ; 0.049 V ; 2.86e-010 s ; 3.59e-010 s ; Yes ; Yes ; 3.15 V ; 3.66e-008 V ; 3.29 V ; -0.0256 V ; 0.236 V ; 0.049 V ; 2.86e-010 s ; 3.59e-010 s ; Yes ; Yes ; -; nMOT_ON ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nSTEP_DIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; nSTEP ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; CLKUSB ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; LPDIR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; BA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; BA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; -; nIRQ[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nIRQ[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nIRQ[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; -; nIRQ[4] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; -; nIRQ[3] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; -; nIRQ[2] ; 3.0-V LVCMOS ; 0 s ; 0 s ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; 3.15 V ; 5.7e-008 V ; 3.25 V ; -0.0382 V ; 0.318 V ; 0.098 V ; 5.02e-010 s ; 5.55e-010 s ; No ; Yes ; -; VA[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; -; VA[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VA[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VA[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VA[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VA[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; -; VB[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; -; VB[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VB[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VB[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VB[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VB[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VB[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VB[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VDM[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; -; VDM[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VDM[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; -; VDM[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VG[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VG[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VG[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VG[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VG[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; -; VG[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VG[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VG[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[7] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[6] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; 3.15 V ; 3.57e-008 V ; 3.19 V ; -0.0203 V ; 0.22 V ; 0.194 V ; 1.43e-009 s ; 1.59e-009 s ; No ; Yes ; -; VR[5] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[4] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[3] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[2] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[1] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; VR[0] ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; 3.15 V ; 3.57e-008 V ; 3.27 V ; -0.0618 V ; 0.21 V ; 0.097 V ; 2.81e-010 s ; 3.83e-010 s ; Yes ; Yes ; -; FB_AD[31] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[30] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[29] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[28] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[27] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; FB_AD[26] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[25] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[24] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[23] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[22] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[21] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[20] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[19] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[18] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; FB_AD[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; FB_AD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; FB_AD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; VD[31] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[30] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; -; VD[29] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[28] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[27] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[26] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[25] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[24] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[23] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[22] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.65 V ; -0.00976 V ; 0.206 V ; 0.133 V ; 1.45e-009 s ; 1.89e-009 s ; No ; Yes ; -; VD[21] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[20] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[19] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[18] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[17] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[16] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VD[15] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[14] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[13] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; -; VD[12] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[11] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[10] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.73 V ; -0.0168 V ; 0.137 V ; 0.024 V ; 2.65e-010 s ; 3.37e-010 s ; Yes ; Yes ; -; VD[9] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[8] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; 2.62 V ; 2.33e-008 V ; 2.65 V ; -0.00959 V ; 0.236 V ; 0.105 V ; 1.48e-009 s ; 2e-009 s ; No ; Yes ; -; VD[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VD[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VDQS[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VDQS[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; 2.62 V ; 2.33e-008 V ; 2.72 V ; -0.00806 V ; 0.218 V ; 0.013 V ; 2.92e-010 s ; 4.58e-010 s ; Yes ; Yes ; -; VDQS[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; VDQS[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; 2.62 V ; 3.47e-008 V ; 2.83 V ; -0.0265 V ; 0.321 V ; 0.029 V ; 1.21e-010 s ; 2.36e-010 s ; No ; Yes ; -; IO[17] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[16] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; IO[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; IO[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; IO[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[15] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[14] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[13] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[12] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[11] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[10] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[9] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[8] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; SRD[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SRD[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; SCSI_PAR ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nSCSI_SEL ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nSCSI_BUSY ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; nSCSI_RST ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SD_CD_DATA3 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SD_CMD_D1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; ACSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; -; ACSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ACSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.48 V ; -0.0136 V ; 0.352 V ; 0.347 V ; 4.12e-009 s ; 3.35e-009 s ; No ; No ; -; ACSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; LP_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; 3.46 V ; 1.9e-007 V ; 3.48 V ; -0.0145 V ; 0.362 V ; 0.287 V ; 3.89e-009 s ; 3.26e-009 s ; No ; No ; -; LP_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; LP_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; 3.46 V ; 1.9e-007 V ; 3.59 V ; -0.0877 V ; 0.332 V ; 0.187 V ; 4.6e-010 s ; 4.2e-010 s ; No ; Yes ; -; SCSI_D[7] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[6] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[5] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[4] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[3] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[2] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[1] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; SCSI_D[0] ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; 3.46 V ; 1.29e-007 V ; 3.55 V ; -0.053 V ; 0.341 V ; 0.351 V ; 9.04e-010 s ; 7.28e-010 s ; No ; No ; -; ~ALTERA_nCEO~ ; 3.0-V LVTTL ; 0 s ; 0 s ; 3.15 V ; 7.44e-008 V ; 3.24 V ; -0.0384 V ; 0.38 V ; 0.235 V ; 5.22e-010 s ; 7e-010 s ; No ; Yes ; 3.15 V ; 7.44e-008 V ; 3.24 V ; -0.0384 V ; 0.38 V ; 0.235 V ; 5.22e-010 s ; 7e-010 s ; No ; Yes ; -+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Ignored Timing Assignments ; -+-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ -; Option ; Setting ; From ; To ; Entity Name ; Help ; -+-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ -; Cut Timing Path ; On ; delayed_wrptr_g ; rs_dgwp|dffpipe15|dffe16a ; dcfifo_8fi1 ; Node named delayed_wrptr_g removed during synthesis ; -; Clock Settings ; fast ; ; DDRCLK ; ; Node named DDRCLK removed during synthesis ; -; Clock Settings ; fast ; ; DDRCLK[0] ; ; Node named DDRCLK[0] removed during synthesis ; -; Clock Settings ; fast ; ; DDRCLK[1] ; ; Node named DDRCLK[1] removed during synthesis ; -; Clock Settings ; fast ; ; DDRCLK[2] ; ; Node named DDRCLK[2] removed during synthesis ; -; Clock Settings ; fast ; ; DDRCLK[3] ; ; Node named DDRCLK[3] removed during synthesis ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK ; ; Node named Video:Fredi_Aschwanden|DDRCLK removed during synthesis ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[0] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[0] removed during synthesis ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[1] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[1] removed during synthesis ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[2] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[2] removed during synthesis ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDRCLK[3] ; ; Node named Video:Fredi_Aschwanden|DDRCLK[3] removed during synthesis ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK was found in the netlist ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0] was found in the netlist ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1] was found in the netlist ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2] was found in the netlist ; -; Clock Settings ; fast ; ; Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] ; ; No element named Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3] was found in the netlist ; -; Maximum Delay ; 5 ns ; VD ; FB_AD ; ; No timing path applicable to specified source and destination ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; BA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[3] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[7] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[16] ; VA[2] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[12] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[22] ; VA[8] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[8] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[10] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[17] ; VA[3] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[5] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[9] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[9] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[7] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[18] ; nVRAS ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[18] ; VA[4] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[6] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[10] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[2] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[24] ; VA[10] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[10] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[2] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[8] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[7] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[15] ; VA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; BA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[11] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[3] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[25] ; VA[11] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; BA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[11] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[3] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[5] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; nVRAS ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; nVRAS ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[8] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; BA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[12] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[4] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; BA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[12] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[4] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[6] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[19] ; VA[5] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[23] ; VA[9] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[9] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[5] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[5] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; BA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[11] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[3] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; nVRAS ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[10] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[2] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[14] ; VA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[6] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[26] ; VA[12] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[6] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; BA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[12] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[4] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[21] ; VA[7] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[11] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[7] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[9] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; nVRAS ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[20] ; VA[6] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; BA[1] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[13] ; VA[4] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[12] ; VA[8] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[30] ; VA[0] ; ; Assignment is illegal for node and/or path ; -; MAX_DELAY ; 5.000 ns ; FB_AD[31] ; VA[2] ; ; Assignment is illegal for node and/or path ; -+-----------------+----------+-----------------+------------------------------------------------------------------+-------------+------------------------------------------------------------------------------------------------------------+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus II Classic Timing Analyzer - Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - Info: Processing started: Wed Dec 15 02:25:14 2010 -Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 --timing_analysis_only -Warning: Timing Analysis is analyzing one or more combinational loops as latches - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[31]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[30]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[29]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[28]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[27]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[26]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[25]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[24]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[23]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[22]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[21]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[20]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[19]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[18]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[17]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[16]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[15]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[14]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[13]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[12]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[11]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[10]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[9]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[8]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[7]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[6]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[5]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[4]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[3]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[2]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[1]" is a latch - Warning: Node "Video:Fredi_Aschwanden|lpm_latch0:inst27|lpm_latch:lpm_latch_component|latches[0]" is a latch -Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled -Warning: Clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" frequency requirement of 47.96 MHz overrides "Cyclone III" PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 48.0 MHz -Warning: Clock Setting "fast" is unassigned -Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" input frequency requirement of 0.5 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" input frequency requirement of 2.46 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" input frequency requirement of 24.57 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" input frequency requirement of 2.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" input frequency requirement of 15.99 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" input frequency requirement of 24.98 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" input frequency requirement of 47.96 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" input frequency requirement of 132.01 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" input frequency requirement of 66.0 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: PLL "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" input frequency requirement of 95.92 MHz overrides default required fmax of 33.33 MHz -- Slack information will be reported -Warning: Found 38 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[3]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[1]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[4]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[2]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[5]" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[3]~23" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[1]~25" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[4]~22" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[2]~24" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[0]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[6]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[9]" as buffer - Info: Detected ripple clock "interrupt_handler:nobody|INT_ENA[8]" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[5]~21" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[0]~26" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[6]~20" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[9]~18" as buffer - Info: Detected gated clock "interrupt_handler:nobody|INT_LATCH[8]~19" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VMD[2]" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[0]" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[8]" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~31" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~30" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK13M" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~2" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[2]" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[7]" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6]" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]" as buffer - Info: Detected ripple clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[9]" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|_~29" as buffer - Info: Detected gated clock "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1" as buffer -Info: Found timing assignments -- calculating delays -Info: Slack time is 1.997 us for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]" - Info: Fmax is 362.45 MHz (period= 2.759 ns) - Info: + Largest register to register requirement is 1999.813 ns - Info: + Setup relationship between source and destination is 1999.998 ns - Info: + Latch edge is 1990.420 ns - Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is -9.578 ns - Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is -0.001 ns - Info: + Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' - Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.997 ns ( 84.88 % ) - Info: - Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.532 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' - Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.084 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.998 ns ( 84.88 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest register to register delay is 2.574 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y16_N15; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0]' - Info: 2: + IC(0.325 ns) + CELL(0.446 ns) = 0.771 ns; Loc. = LCCOMB_X65_Y16_N14; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita0~COUT' - Info: 3: + IC(0.000 ns) + CELL(0.058 ns) = 0.829 ns; Loc. = LCCOMB_X65_Y16_N16; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita1~COUT' - Info: 4: + IC(0.000 ns) + CELL(0.058 ns) = 0.887 ns; Loc. = LCCOMB_X65_Y16_N18; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita2~COUT' - Info: 5: + IC(0.000 ns) + CELL(0.058 ns) = 0.945 ns; Loc. = LCCOMB_X65_Y16_N20; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita3~COUT' - Info: 6: + IC(0.000 ns) + CELL(0.058 ns) = 1.003 ns; Loc. = LCCOMB_X65_Y16_N22; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita4~COUT' - Info: 7: + IC(0.000 ns) + CELL(0.058 ns) = 1.061 ns; Loc. = LCCOMB_X65_Y16_N24; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita5~COUT' - Info: 8: + IC(0.000 ns) + CELL(0.058 ns) = 1.119 ns; Loc. = LCCOMB_X65_Y16_N26; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita6~COUT' - Info: 9: + IC(0.000 ns) + CELL(0.058 ns) = 1.177 ns; Loc. = LCCOMB_X65_Y16_N28; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita7~COUT' - Info: 10: + IC(0.000 ns) + CELL(0.058 ns) = 1.235 ns; Loc. = LCCOMB_X65_Y16_N30; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita8~COUT' - Info: 11: + IC(0.000 ns) + CELL(0.058 ns) = 1.293 ns; Loc. = LCCOMB_X65_Y15_N0; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita9~COUT' - Info: 12: + IC(0.000 ns) + CELL(0.058 ns) = 1.351 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10~COUT' - Info: 13: + IC(0.000 ns) + CELL(0.058 ns) = 1.409 ns; Loc. = LCCOMB_X65_Y15_N4; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita11~COUT' - Info: 14: + IC(0.000 ns) + CELL(0.058 ns) = 1.467 ns; Loc. = LCCOMB_X65_Y15_N6; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita12~COUT' - Info: 15: + IC(0.000 ns) + CELL(0.058 ns) = 1.525 ns; Loc. = LCCOMB_X65_Y15_N8; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita13~COUT' - Info: 16: + IC(0.000 ns) + CELL(0.058 ns) = 1.583 ns; Loc. = LCCOMB_X65_Y15_N10; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita14~COUT' - Info: 17: + IC(0.000 ns) + CELL(0.058 ns) = 1.641 ns; Loc. = LCCOMB_X65_Y15_N12; Fanout = 2; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita15~COUT' - Info: 18: + IC(0.000 ns) + CELL(0.058 ns) = 1.699 ns; Loc. = LCCOMB_X65_Y15_N14; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita16~COUT' - Info: 19: + IC(0.000 ns) + CELL(0.455 ns) = 2.154 ns; Loc. = LCCOMB_X65_Y15_N16; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita17' - Info: 20: + IC(0.199 ns) + CELL(0.130 ns) = 2.483 ns; Loc. = LCCOMB_X65_Y15_N26; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]~feeder' - Info: 21: + IC(0.000 ns) + CELL(0.091 ns) = 2.574 ns; Loc. = FF_X65_Y15_N27; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17]' - Info: Total cell delay = 2.050 ns ( 79.64 % ) - Info: Total interconnect delay = 0.524 ns ( 20.36 % ) -Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[1]" -Info: No valid register-to-register data paths exist for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[2]" -Info: Slack time is 498.663 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]" - Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits - Info: + Largest register to register requirement is 500.232 ns - Info: + Setup relationship between source and destination is 500.416 ns - Info: + Latch edge is 498.552 ns - Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is -1.864 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is 0.000 ns - Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]' - Info: Total cell delay = 0.534 ns ( 15.16 % ) - Info: Total interconnect delay = 2.988 ns ( 84.84 % ) - Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' - Info: Total cell delay = 0.534 ns ( 15.16 % ) - Info: Total interconnect delay = 2.988 ns ( 84.84 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest register to register delay is 1.569 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' - Info: 2: + IC(0.344 ns) + CELL(0.376 ns) = 0.720 ns; Loc. = LCCOMB_X1_Y10_N14; Fanout = 5; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[3]~13' - Info: 3: + IC(0.240 ns) + CELL(0.609 ns) = 1.569 ns; Loc. = FF_X1_Y10_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0]' - Info: Total cell delay = 0.985 ns ( 62.78 % ) - Info: Total interconnect delay = 0.584 ns ( 37.22 % ) -Info: Slack time is 28.59 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK" - Info: Fmax is 186.15 MHz (period= 5.372 ns) - Info: + Largest register to register requirement is 31.135 ns - Info: + Setup relationship between source and destination is 31.276 ns - Info: + Latch edge is 60.688 ns - Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 29.412 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with inverted offset of 29.412 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is 0.020 ns - Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.508 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.065 ns) + CELL(0.534 ns) = 3.508 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK' - Info: Total cell delay = 0.534 ns ( 15.22 % ) - Info: Total interconnect delay = 2.974 ns ( 84.78 % ) - Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.488 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.131 ns) + CELL(0.448 ns) = 3.488 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In' - Info: Total cell delay = 0.448 ns ( 12.84 % ) - Info: Total interconnect delay = 3.040 ns ( 87.16 % ) - Info: - Micro clock to output delay of source is 0.176 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest register to register delay is 2.545 ns - Info: 1: + IC(0.000 ns) + CELL(0.418 ns) = 0.418 ns; Loc. = FF_X59_Y43_N10; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In' - Info: 2: + IC(1.655 ns) + CELL(0.381 ns) = 2.454 ns; Loc. = LCCOMB_X30_Y32_N2; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK~0' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 2.545 ns; Loc. = FF_X30_Y32_N3; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK' - Info: Total cell delay = 0.890 ns ( 34.97 % ) - Info: Total interconnect delay = 1.655 ns ( 65.03 % ) -Info: Slack time is -4.615 ns for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" - Info: + Largest memory to register requirement is -0.928 ns - Info: + Setup relationship between source and destination is 0.145 ns - Info: + Latch edge is 0.221 ns - Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 0.076 ns - Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is -0.862 ns - Info: + Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 7.507 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' - Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 7.507 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' - Info: Total cell delay = 1.084 ns ( 14.44 % ) - Info: Total interconnect delay = 6.423 ns ( 85.56 % ) - Info: - Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source memory is 8.369 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' - Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.112 ns) + CELL(0.816 ns) = 8.369 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' - Info: Total cell delay = 1.525 ns ( 18.22 % ) - Info: Total interconnect delay = 6.844 ns ( 81.78 % ) - Info: - Micro clock to output delay of source is 0.226 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest memory to register delay is 3.687 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' - Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' - Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' - Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' - Info: Total cell delay = 2.700 ns ( 73.23 % ) - Info: Total interconnect delay = 0.987 ns ( 26.77 % ) -Warning: Can't achieve timing requirement Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' along 3741 path(s). See Report window for details. -Info: No valid register-to-register data paths exist for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[3]" -Info: Slack time is -2.673 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC" - Info: + Largest pin to register requirement is 0.814 ns - Info: + Setup relationship between source and destination is 1.262 ns - Info: + Latch edge is 3.955 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 2.693 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is 3.537 ns - Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.537 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.102 ns) + CELL(0.534 ns) = 3.537 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC' - Info: Total cell delay = 0.534 ns ( 15.10 % ) - Info: Total interconnect delay = 3.003 ns ( 84.90 % ) - Info: - Micro setup delay of destination is -0.015 ns - Info: - Max Input delay of pin is 4.0 ns - Info: - Longest pin to register delay is 3.487 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' - Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' - Info: 3: + IC(1.144 ns) + CELL(0.130 ns) = 2.215 ns; Loc. = LCCOMB_X22_Y6_N18; Fanout = 18; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|_~5' - Info: 4: + IC(0.241 ns) + CELL(0.130 ns) = 2.586 ns; Loc. = LCCOMB_X22_Y6_N24; Fanout = 19; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_S[10]~0' - Info: 5: + IC(0.680 ns) + CELL(0.130 ns) = 3.396 ns; Loc. = LCCOMB_X25_Y6_N20; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC~1' - Info: 6: + IC(0.000 ns) + CELL(0.091 ns) = 3.487 ns; Loc. = FF_X25_Y6_N21; Fanout = 6; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC' - Info: Total cell delay = 1.422 ns ( 40.78 % ) - Info: Total interconnect delay = 2.065 ns ( 59.22 % ) -Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' along 86 path(s). See Report window for details. -Info: Slack time is 2.965 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]" - Info: Fmax is restricted to 500.0 MHz due to tcl and tch limits - Info: + Largest register to register requirement is 3.604 ns - Info: + Setup relationship between source and destination is 3.788 ns - Info: + Latch edge is 6.481 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 2.693 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is 0.000 ns - Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.531 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.997 ns ( 84.88 % ) - Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.531 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.096 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.997 ns ( 84.88 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest register to register delay is 0.639 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6]' - Info: 2: + IC(0.297 ns) + CELL(0.342 ns) = 0.639 ns; Loc. = FF_X66_Y12_N3; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6]' - Info: Total cell delay = 0.342 ns ( 53.52 % ) - Info: Total interconnect delay = 0.297 ns ( 46.48 % ) -Info: Slack time is 5.299 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]" - Info: + Largest register to register requirement is 6.118 ns - Info: + Setup relationship between source and destination is 6.313 ns - Info: + Latch edge is 10.268 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 3.955 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is -0.011 ns - Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.532 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.097 ns) + CELL(0.534 ns) = 3.532 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.998 ns ( 84.88 % ) - Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]' - Info: Total cell delay = 0.534 ns ( 15.07 % ) - Info: Total interconnect delay = 3.009 ns ( 84.93 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest register to register delay is 0.819 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N27; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3]' - Info: 2: + IC(0.598 ns) + CELL(0.130 ns) = 0.728 ns; Loc. = LCCOMB_X28_Y12_N28; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]~feeder' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.819 ns; Loc. = FF_X28_Y12_N29; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3]' - Info: Total cell delay = 0.221 ns ( 26.98 % ) - Info: Total interconnect delay = 0.598 ns ( 73.02 % ) -Info: Slack time is 1.672 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI" - Info: + Largest register to register requirement is 5.308 ns - Info: + Setup relationship between source and destination is 5.999 ns - Info: + Latch edge is 8.690 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 2.691 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is -0.064 ns - Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.487 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl' - Info: 3: + IC(1.098 ns) + CELL(0.488 ns) = 3.487 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI' - Info: Total cell delay = 0.488 ns ( 13.99 % ) - Info: Total interconnect delay = 2.999 ns ( 86.01 % ) - Info: - Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.551 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' - Info: 3: + IC(1.116 ns) + CELL(0.534 ns) = 3.551 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]' - Info: Total cell delay = 0.534 ns ( 15.04 % ) - Info: Total interconnect delay = 3.017 ns ( 84.96 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: - Micro setup delay of destination is 0.428 ns - Info: - Longest register to register delay is 3.636 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X22_Y2_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2]' - Info: 2: + IC(0.330 ns) + CELL(0.367 ns) = 0.697 ns; Loc. = LCCOMB_X22_Y2_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[34]~59' - Info: 3: + IC(2.591 ns) + CELL(0.348 ns) = 3.636 ns; Loc. = DDIOOUTCELL_X67_Y14_N11; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI' - Info: Total cell delay = 0.715 ns ( 19.66 % ) - Info: Total interconnect delay = 2.921 ns ( 80.34 % ) -Info: Slack time is -1.712 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ" - Info: + Largest pin to register requirement is 1.118 ns - Info: + Setup relationship between source and destination is 1.576 ns - Info: + Latch edge is 2.691 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 1.115 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is 3.527 ns - Info: + Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.527 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' - Info: 3: + IC(1.092 ns) + CELL(0.534 ns) = 3.527 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ' - Info: Total cell delay = 0.534 ns ( 15.14 % ) - Info: Total interconnect delay = 2.993 ns ( 84.86 % ) - Info: - Micro setup delay of destination is -0.015 ns - Info: - Max Input delay of pin is 4.0 ns - Info: - Longest pin to register delay is 2.830 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' - Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' - Info: 3: + IC(1.138 ns) + CELL(0.130 ns) = 2.209 ns; Loc. = LCCOMB_X22_Y6_N4; Fanout = 7; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|DDR_SEL' - Info: 4: + IC(0.400 ns) + CELL(0.130 ns) = 2.739 ns; Loc. = LCCOMB_X21_Y6_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ~2' - Info: 5: + IC(0.000 ns) + CELL(0.091 ns) = 2.830 ns; Loc. = FF_X21_Y6_N19; Fanout = 19; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ' - Info: Total cell delay = 1.292 ns ( 45.65 % ) - Info: Total interconnect delay = 1.538 ns ( 54.35 % ) -Warning: Can't achieve timing requirement Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' along 29 path(s). See Report window for details. -Info: Slack time is -4.294 ns for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" - Info: + Largest memory to register requirement is -0.607 ns - Info: + Setup relationship between source and destination is 0.272 ns - Info: + Latch edge is 0.493 ns - Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 0.221 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is -0.668 ns - Info: + Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.082 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' - Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 8.082 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' - Info: Total cell delay = 1.243 ns ( 15.38 % ) - Info: Total interconnect delay = 6.839 ns ( 84.62 % ) - Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' - Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' - Info: Total cell delay = 1.680 ns ( 19.20 % ) - Info: Total interconnect delay = 7.070 ns ( 80.80 % ) - Info: - Micro clock to output delay of source is 0.226 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest memory to register delay is 3.687 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' - Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' - Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' - Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' - Info: Total cell delay = 2.700 ns ( 73.23 % ) - Info: Total interconnect delay = 0.987 ns ( 26.77 % ) -Warning: Can't achieve timing requirement Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' along 3741 path(s). See Report window for details. -Info: Slack time is -5.966 ns for clock "CLK33M" between source memory "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0" and destination register "Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]" - Info: + Largest memory to register requirement is -2.279 ns - Info: + Setup relationship between source and destination is 0.196 ns - Info: + Latch edge is 0.278 ns - Info: Clock period of Destination clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 0.082 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is -2.264 ns - Info: + Shortest clock path from clock "CLK33M" to destination register is 6.486 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' - Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' - Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' - Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.107 ns) + CELL(0.534 ns) = 6.486 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' - Info: Total cell delay = 2.006 ns ( 30.93 % ) - Info: Total interconnect delay = 4.480 ns ( 69.07 % ) - Info: - Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source memory is 8.750 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' - Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 7: + IC(1.112 ns) + CELL(0.816 ns) = 8.750 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' - Info: Total cell delay = 1.680 ns ( 19.20 % ) - Info: Total interconnect delay = 7.070 ns ( 80.80 % ) - Info: - Micro clock to output delay of source is 0.226 ns - Info: - Micro setup delay of destination is -0.015 ns - Info: - Longest memory to register delay is 3.687 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M9K_X40_Y20_N0; Fanout = 36; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0' - Info: 2: + IC(0.000 ns) + CELL(2.479 ns) = 2.479 ns; Loc. = M9K_X40_Y20_N0; Fanout = 1; MEM Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|q_b[35]' - Info: 3: + IC(0.987 ns) + CELL(0.130 ns) = 3.596 ns; Loc. = LCCOMB_X41_Y18_N14; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|result_node[35]~67' - Info: 4: + IC(0.000 ns) + CELL(0.091 ns) = 3.687 ns; Loc. = FF_X41_Y18_N15; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35]' - Info: Total cell delay = 2.700 ns ( 73.23 % ) - Info: Total interconnect delay = 0.987 ns ( 26.77 % ) -Warning: Can't achieve timing requirement Clock Setup: 'CLK33M' along 3741 path(s). See Report window for details. -Info: Slack time is -4.261 ns for clock "MAIN_CLK" between source pin "FB_ALE" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7" - Info: + Largest pin to register requirement is 0.057 ns - Info: + Setup relationship between source and destination is 1.094 ns - Info: + Latch edge is 7.575 ns - Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: - Launch edge is 6.481 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: + Largest clock skew is 2.948 ns - Info: + Shortest clock path from clock "MAIN_CLK" to destination register is 2.948 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(1.433 ns) + CELL(0.534 ns) = 2.948 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7' - Info: Total cell delay = 1.515 ns ( 51.39 % ) - Info: Total interconnect delay = 1.433 ns ( 48.61 % ) - Info: - Micro setup delay of destination is -0.015 ns - Info: - Max Input delay of pin is 4.0 ns - Info: - Longest pin to register delay is 4.318 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' - Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' - Info: 3: + IC(1.524 ns) + CELL(0.130 ns) = 2.595 ns; Loc. = LCCOMB_X23_Y7_N20; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FCF_APH~2' - Info: 4: + IC(0.212 ns) + CELL(0.130 ns) = 2.937 ns; Loc. = LCCOMB_X23_Y7_N18; Fanout = 52; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|valid_rdreq~1' - Info: 5: + IC(0.445 ns) + CELL(0.130 ns) = 3.512 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 4; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~2' - Info: 6: + IC(0.235 ns) + CELL(0.130 ns) = 3.877 ns; Loc. = LCCOMB_X22_Y7_N28; Fanout = 3; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|_~4' - Info: 7: + IC(0.220 ns) + CELL(0.130 ns) = 4.227 ns; Loc. = LCCOMB_X22_Y7_N16; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7~0' - Info: 8: + IC(0.000 ns) + CELL(0.091 ns) = 4.318 ns; Loc. = FF_X22_Y7_N17; Fanout = 5; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7' - Info: Total cell delay = 1.682 ns ( 38.95 % ) - Info: Total interconnect delay = 2.636 ns ( 61.05 % ) -Warning: Can't achieve timing requirement Clock Setup: 'MAIN_CLK' along 27347 path(s). See Report window for details. -Info: Minimum slack time is 825 ps for clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" between source register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" and destination register "lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]" - Info: + Shortest register to register delay is 0.783 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' - Info: 2: + IC(0.323 ns) + CELL(0.369 ns) = 0.692 ns; Loc. = LCCOMB_X65_Y15_N2; Fanout = 1; COMB Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_comb_bita10' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.783 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' - Info: Total cell delay = 0.460 ns ( 58.75 % ) - Info: Total interconnect delay = 0.323 ns ( 41.25 % ) - Info: - Smallest register to register requirement is -0.042 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -9.578 ns - Info: Clock period of Destination clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -9.578 ns - Info: Clock period of Source clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" is 1999.998 ns with offset of -9.578 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.000 ns - Info: + Longest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to destination register is 3.531 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' - Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.997 ns ( 84.88 % ) - Info: - Shortest clock path from clock "altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]" to source register is 3.531 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_3; Fanout = 1; CLK Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' - Info: 2: + IC(1.914 ns) + CELL(0.000 ns) = 1.914 ns; Loc. = CLKCTRL_G14; Fanout = 52; COMB Node = 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.531 ns; Loc. = FF_X65_Y15_N3; Fanout = 2; REG Node = 'lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10]' - Info: Total cell delay = 0.534 ns ( 15.12 % ) - Info: Total interconnect delay = 2.997 ns ( 84.88 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is 564 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]" - Info: + Shortest register to register delay is 0.522 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' - Info: 2: + IC(0.301 ns) + CELL(0.130 ns) = 0.431 ns; Loc. = LCCOMB_X1_Y10_N10; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]~14' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' - Info: Total cell delay = 0.221 ns ( 42.34 % ) - Info: Total interconnect delay = 0.301 ns ( 57.66 % ) - Info: - Smallest register to register requirement is -0.042 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -1.864 ns - Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -1.864 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" is 500.416 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.000 ns - Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to destination register is 3.522 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' - Info: Total cell delay = 0.534 ns ( 15.16 % ) - Info: Total interconnect delay = 2.988 ns ( 84.84 % ) - Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]" to source register is 3.522 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G16; Fanout = 7; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.079 ns) + CELL(0.534 ns) = 3.522 ns; Loc. = FF_X1_Y10_N11; Fanout = 2; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4]' - Info: Total cell delay = 0.534 ns ( 15.16 % ) - Info: Total interconnect delay = 2.988 ns ( 84.84 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is 502 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" between source register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" and destination register "FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1" - Info: + Shortest register to register delay is 0.460 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' - Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y28_N4; Fanout = 2; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|Selector77~1' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' - Info: Total cell delay = 0.460 ns ( 100.00 % ) - Info: - Smallest register to register requirement is -0.042 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -1.864 ns - Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -1.864 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" is 62.552 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.000 ns - Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to destination register is 3.526 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' - Info: Total cell delay = 0.534 ns ( 15.14 % ) - Info: Total interconnect delay = 2.992 ns ( 84.86 % ) - Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]" to source register is 3.526 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G17; Fanout = 595; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.083 ns) + CELL(0.534 ns) = 3.526 ns; Loc. = FF_X34_Y28_N5; Fanout = 1; REG Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1' - Info: Total cell delay = 0.534 ns ( 15.14 % ) - Info: Total interconnect delay = 2.992 ns ( 84.86 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is -454 ps for clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" - Info: + Shortest register to register delay is 0.460 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 0.460 ns ( 100.00 % ) - Info: - Smallest register to register requirement is 0.914 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -1.864 ns - Info: Clock period of Destination clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -1.864 ns - Info: Clock period of Source clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" is 40.033 ns with offset of -1.864 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.956 ns - Info: + Longest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to destination register is 8.469 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.466 ns) + CELL(0.367 ns) = 3.742 ns; Loc. = LCCOMB_X22_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~0' - Info: 4: + IC(0.201 ns) + CELL(0.130 ns) = 4.073 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.090 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.822 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 8.469 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 1.398 ns ( 16.51 % ) - Info: Total interconnect delay = 7.071 ns ( 83.49 % ) - Info: - Shortest clock path from clock "altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]" to source register is 7.513 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_4; Fanout = 1; CLK Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' - Info: 2: + IC(1.909 ns) + CELL(0.000 ns) = 1.909 ns; Loc. = CLKCTRL_G18; Fanout = 4; COMB Node = 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.472 ns) + CELL(0.307 ns) = 3.688 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' - Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 4.134 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 5.866 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 7.513 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 1.084 ns ( 14.43 % ) - Info: Total interconnect delay = 6.429 ns ( 85.57 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Warning: Can't achieve minimum setup and hold requirement altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] along 26 path(s). See Report window for details. -Info: Minimum slack time is 502 ps for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]" - Info: + Shortest register to register delay is 0.460 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' - Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X45_Y15_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]~3' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' - Info: Total cell delay = 0.460 ns ( 100.00 % ) - Info: - Smallest register to register requirement is -0.042 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -3.620 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -3.620 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.000 ns - Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to destination register is 3.559 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' - Info: Total cell delay = 0.534 ns ( 15.00 % ) - Info: Total interconnect delay = 3.025 ns ( 85.00 % ) - Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.559 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.124 ns) + CELL(0.534 ns) = 3.559 ns; Loc. = FF_X45_Y15_N13; Fanout = 14; REG Node = 'Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6]' - Info: Total cell delay = 0.534 ns ( 15.00 % ) - Info: Total interconnect delay = 3.025 ns ( 85.00 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is 4.336 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" between source register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]" - Info: + Shortest register to register delay is 0.507 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]' - Info: 2: + IC(0.286 ns) + CELL(0.130 ns) = 0.416 ns; Loc. = LCCOMB_X66_Y14_N30; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]~feeder' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.507 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]' - Info: Total cell delay = 0.221 ns ( 43.59 % ) - Info: Total interconnect delay = 0.286 ns ( 56.41 % ) - Info: - Smallest register to register requirement is -3.829 ns - Info: + Hold relationship between source and destination is -3.787 ns - Info: + Latch edge is -1.094 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with offset of -1.094 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is 2.693 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" is 7.575 ns with inverted offset of 2.693 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.000 ns - Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to destination register is 3.538 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N31; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2]' - Info: Total cell delay = 0.534 ns ( 15.09 % ) - Info: Total interconnect delay = 3.004 ns ( 84.91 % ) - Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]" to source register is 3.538 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G1; Fanout = 96; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]~clkctrl' - Info: 3: + IC(1.103 ns) + CELL(0.534 ns) = 3.538 ns; Loc. = FF_X66_Y14_N29; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2]' - Info: Total cell delay = 0.534 ns ( 15.09 % ) - Info: Total interconnect delay = 3.004 ns ( 84.91 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is 1.825 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" between source register "Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]" and destination register "Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]" - Info: + Shortest register to register delay is 0.508 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]' - Info: 2: + IC(0.287 ns) + CELL(0.130 ns) = 0.417 ns; Loc. = LCCOMB_X25_Y12_N6; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]~feeder' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.508 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]' - Info: Total cell delay = 0.221 ns ( 43.50 % ) - Info: Total interconnect delay = 0.287 ns ( 56.50 % ) - Info: - Smallest register to register requirement is -1.317 ns - Info: + Hold relationship between source and destination is -1.262 ns - Info: + Latch edge is 2.693 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" is 7.575 ns with offset of 2.693 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is 3.955 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" is 7.575 ns with offset of -3.620 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is -0.013 ns - Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]" to destination register is 3.530 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G0; Fanout = 5; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]~clkctrl' - Info: 3: + IC(1.095 ns) + CELL(0.534 ns) = 3.530 ns; Loc. = FF_X25_Y12_N7; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6]' - Info: Total cell delay = 0.534 ns ( 15.13 % ) - Info: Total interconnect delay = 2.996 ns ( 84.87 % ) - Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]" to source register is 3.543 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G3; Fanout = 707; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.108 ns) + CELL(0.534 ns) = 3.543 ns; Loc. = FF_X25_Y12_N19; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6]' - Info: Total cell delay = 0.534 ns ( 15.07 % ) - Info: Total interconnect delay = 3.009 ns ( 84.93 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is 3.263 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" between source register "Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]" and destination register "Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO" - Info: + Shortest register to register delay is 1.570 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]' - Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X34_Y2_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|lpm_mux5:inst22|lpm_mux:lpm_mux_component|mux_58e:auto_generated|result_node[29]~4' - Info: 3: + IC(0.737 ns) + CELL(0.464 ns) = 1.570 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO' - Info: Total cell delay = 0.833 ns ( 53.06 % ) - Info: Total interconnect delay = 0.737 ns ( 46.94 % ) - Info: - Smallest register to register requirement is -1.693 ns - Info: + Hold relationship between source and destination is -1.576 ns - Info: + Latch edge is 1.115 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" is 7.575 ns with offset of 1.115 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is 2.691 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is -0.019 ns - Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]" to destination register is 3.543 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G2; Fanout = 113; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]~clkctrl' - Info: 3: + IC(1.154 ns) + CELL(0.488 ns) = 3.543 ns; Loc. = DDIOOUTCELL_X38_Y0_N25; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO' - Info: Total cell delay = 0.488 ns ( 13.77 % ) - Info: Total interconnect delay = 3.055 ns ( 86.23 % ) - Info: - Shortest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to source register is 3.562 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' - Info: 3: + IC(1.127 ns) + CELL(0.534 ns) = 3.562 ns; Loc. = FF_X34_Y2_N1; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29]' - Info: Total cell delay = 0.534 ns ( 14.99 % ) - Info: Total interconnect delay = 3.028 ns ( 85.01 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.101 ns -Info: Minimum slack time is 2.664 ns for clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" between source pin "FB_ALE" and destination register "lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]" - Info: + Shortest pin to register delay is 2.216 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_R7; Fanout = 1; PIN Node = 'FB_ALE' - Info: 2: + IC(0.000 ns) + CELL(0.941 ns) = 0.941 ns; Loc. = IOIBUF_X0_Y2_N1; Fanout = 33; COMB Node = 'FB_ALE~input' - Info: 3: + IC(0.929 ns) + CELL(0.346 ns) = 2.216 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]' - Info: Total cell delay = 1.287 ns ( 58.08 % ) - Info: Total interconnect delay = 0.929 ns ( 41.92 % ) - Info: - Smallest pin to register requirement is -0.448 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -4.884 ns - Info: Clock period of Destination clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -4.884 ns - Info: Clock period of Source clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" is 15.151 ns with offset of -4.884 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 3.500 ns - Info: + Longest clock path from clock "altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]" to destination register is 3.500 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' - Info: 2: + IC(1.901 ns) + CELL(0.000 ns) = 1.901 ns; Loc. = CLKCTRL_G4; Fanout = 189; COMB Node = 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]~clkctrl' - Info: 3: + IC(1.151 ns) + CELL(0.448 ns) = 3.500 ns; Loc. = FF_X7_Y0_N31; Fanout = 120; REG Node = 'lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2]' - Info: Total cell delay = 0.448 ns ( 12.80 % ) - Info: Total interconnect delay = 3.052 ns ( 87.20 % ) - Info: + Micro hold delay of destination is 0.052 ns - Info: - Min Input delay of pin is 4.0 ns -Info: Minimum slack time is 502 ps for clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" - Info: + Shortest register to register delay is 0.460 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 0.460 ns ( 100.00 % ) - Info: - Smallest register to register requirement is -0.042 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is -2.843 ns - Info: Clock period of Destination clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is -2.843 ns - Info: Clock period of Source clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" is 10.425 ns with offset of -2.843 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 0.000 ns - Info: + Longest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to destination register is 8.088 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' - Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 1.243 ns ( 15.37 % ) - Info: Total interconnect delay = 6.845 ns ( 84.63 % ) - Info: - Shortest clock path from clock "altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]" to source register is 8.088 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 1; CLK Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' - Info: 2: + IC(1.881 ns) + CELL(0.000 ns) = 1.881 ns; Loc. = CLKCTRL_G8; Fanout = 1; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]~clkctrl' - Info: 3: + IC(1.469 ns) + CELL(0.342 ns) = 3.692 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 4: + IC(0.650 ns) + CELL(0.367 ns) = 4.709 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 6.441 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 8.088 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 1.243 ns ( 15.37 % ) - Info: Total interconnect delay = 6.845 ns ( 84.63 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Info: Minimum slack time is -687 ps for clock "CLK33M" between source register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" and destination register "Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]" - Info: + Shortest register to register delay is 0.460 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: 2: + IC(0.000 ns) + CELL(0.369 ns) = 0.369 ns; Loc. = LCCOMB_X37_Y20_N12; Fanout = 5; COMB Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|ram_read_address[6]~6' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 0.460 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 0.460 ns ( 100.00 % ) - Info: - Smallest register to register requirement is 1.147 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is 0.000 ns - Info: Clock period of Destination clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is 0.000 ns - Info: Clock period of Source clock "CLK33M" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 1.189 ns - Info: + Longest clock path from clock "CLK33M" to destination register is 7.681 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' - Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' - Info: 3: + IC(1.161 ns) + CELL(0.733 ns) = 2.812 ns; Loc. = FF_X33_Y18_N25; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|CLK17M' - Info: 4: + IC(0.852 ns) + CELL(0.311 ns) = 3.975 ns; Loc. = LCCOMB_X26_Y18_N0; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~4' - Info: 5: + IC(0.197 ns) + CELL(0.130 ns) = 4.302 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.034 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 7: + IC(1.113 ns) + CELL(0.534 ns) = 7.681 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 2.626 ns ( 34.19 % ) - Info: Total interconnect delay = 5.055 ns ( 65.81 % ) - Info: - Shortest clock path from clock "CLK33M" to source register is 6.492 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AB12; Fanout = 1; CLK Node = 'CLK33M' - Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X36_Y0_N1; Fanout = 8; COMB Node = 'CLK33M~input' - Info: 3: + IC(1.438 ns) + CELL(0.311 ns) = 2.667 ns; Loc. = LCCOMB_X26_Y18_N8; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~3' - Info: 4: + IC(0.203 ns) + CELL(0.243 ns) = 3.113 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 5: + IC(1.732 ns) + CELL(0.000 ns) = 4.845 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 6: + IC(1.113 ns) + CELL(0.534 ns) = 6.492 ns; Loc. = FF_X37_Y20_N13; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6]' - Info: Total cell delay = 2.006 ns ( 30.90 % ) - Info: Total interconnect delay = 4.486 ns ( 69.10 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Warning: Can't achieve minimum setup and hold requirement CLK33M along 26 path(s). See Report window for details. -Info: Minimum slack time is -3.786 ns for clock "MAIN_CLK" between source register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]" - Info: + Shortest register to register delay is 1.930 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]' - Info: 2: + IC(1.597 ns) + CELL(0.242 ns) = 1.839 ns; Loc. = LCCOMB_X34_Y15_N4; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]~1' - Info: 3: + IC(0.000 ns) + CELL(0.091 ns) = 1.930 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]' - Info: Total cell delay = 0.333 ns ( 17.25 % ) - Info: Total interconnect delay = 1.597 ns ( 82.75 % ) - Info: - Smallest register to register requirement is 5.716 ns - Info: + Hold relationship between source and destination is 0.000 ns - Info: + Latch edge is 0.000 ns - Info: Clock period of Destination clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 - Info: Multicycle Setup factor for Destination register is 1 - Info: Multicycle Hold factor for Destination register is 1 - Info: - Launch edge is 0.000 ns - Info: Clock period of Source clock "MAIN_CLK" is 30.303 ns with offset of 0.000 ns and duty cycle of 50 - Info: Multicycle Setup factor for Source register is 1 - Info: Multicycle Hold factor for Source register is 1 - Info: + Smallest clock skew is 5.758 ns - Info: + Longest clock path from clock "MAIN_CLK" to destination register is 8.630 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]' - Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 6: + IC(1.732 ns) + CELL(0.000 ns) = 6.988 ns; Loc. = CLKCTRL_G6; Fanout = 1105; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~clkctrl' - Info: 7: + IC(1.108 ns) + CELL(0.534 ns) = 8.630 ns; Loc. = FF_X34_Y15_N5; Fanout = 1; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0]' - Info: Total cell delay = 2.858 ns ( 33.12 % ) - Info: Total interconnect delay = 5.772 ns ( 66.88 % ) - Info: - Shortest clock path from clock "MAIN_CLK" to source register is 2.872 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(1.357 ns) + CELL(0.534 ns) = 2.872 ns; Loc. = FF_X26_Y18_N19; Fanout = 2; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6]' - Info: Total cell delay = 1.515 ns ( 52.75 % ) - Info: Total interconnect delay = 1.357 ns ( 47.25 % ) - Info: - Micro clock to output delay of source is 0.199 ns - Info: + Micro hold delay of destination is 0.157 ns -Warning: Can't achieve minimum setup and hold requirement MAIN_CLK along 108 path(s). See Report window for details. -Warning: Can't achieve timing requirement tsu along 6867 path(s). See Report window for details. -Info: Slack time is -4.528 ns for clock "MAIN_CLK" between source clock "MAIN_CLK" and destination register "altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state" - Info: + tsu requirement for source pin and destination register is 1.000 ns - Info: - tsu from clock to input pin is 5.528 ns - Info: + Longest clock to register delay is 8.706 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(4.109 ns) + CELL(0.869 ns) = 5.959 ns; Loc. = PLL_2; Fanout = 4; COMB Node = 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|scandone' - Info: 4: + IC(1.722 ns) + CELL(0.130 ns) = 7.811 ns; Loc. = LCCOMB_X21_Y26_N18; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~0' - Info: 5: + IC(0.198 ns) + CELL(0.130 ns) = 8.139 ns; Loc. = LCCOMB_X21_Y26_N28; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~1' - Info: 6: + IC(0.346 ns) + CELL(0.130 ns) = 8.615 ns; Loc. = LCCOMB_X22_Y26_N16; Fanout = 1; COMB Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state~2' - Info: 7: + IC(0.000 ns) + CELL(0.091 ns) = 8.706 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state' - Info: Total cell delay = 2.331 ns ( 26.77 % ) - Info: Total interconnect delay = 6.375 ns ( 73.23 % ) - Info: + Micro setup delay of destination is -0.015 ns - Info: - Shortest clock path from clock "MAIN_CLK" to destination register is 3.163 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(1.648 ns) + CELL(0.534 ns) = 3.163 ns; Loc. = FF_X22_Y26_N17; Fanout = 8; REG Node = 'altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state' - Info: Total cell delay = 1.515 ns ( 47.90 % ) - Info: Total interconnect delay = 1.648 ns ( 52.10 % ) -Warning: Can't achieve timing requirement tco along 4976 path(s). See Report window for details. -Info: Slack time is -14.84 ns for clock "MAIN_CLK" between source register "interrupt_handler:nobody|INT_LATCH[8]" and destination pin "nIRQ[5]" - Info: + tco requirement for source register and destination pin is 1.000 ns - Info: - tco from clock to output pin is 15.840 ns - Info: + Longest clock path from clock "MAIN_CLK" to source register is 9.460 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(1.360 ns) + CELL(0.733 ns) = 3.074 ns; Loc. = FF_X28_Y18_N31; Fanout = 208; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[0]' - Info: 4: + IC(0.922 ns) + CELL(0.243 ns) = 4.239 ns; Loc. = LCCOMB_X22_Y18_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK~1' - Info: 5: + IC(0.650 ns) + CELL(0.367 ns) = 5.256 ns; Loc. = LCCOMB_X26_Y18_N4; Fanout = 3; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|PIXEL_CLK' - Info: 6: + IC(1.232 ns) + CELL(0.733 ns) = 7.221 ns; Loc. = FF_X18_Y15_N21; Fanout = 5; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' - Info: 7: + IC(0.716 ns) + CELL(0.308 ns) = 8.245 ns; Loc. = LCCOMB_X15_Y15_N6; Fanout = 1; COMB Node = 'interrupt_handler:nobody|INT_LATCH[8]~19' - Info: 8: + IC(0.681 ns) + CELL(0.534 ns) = 9.460 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]' - Info: Total cell delay = 3.899 ns ( 41.22 % ) - Info: Total interconnect delay = 5.561 ns ( 58.78 % ) - Info: + Micro clock to output delay of source is 0.199 ns - Info: + Longest register to pin delay is 6.181 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X16_Y12_N5; Fanout = 3; REG Node = 'interrupt_handler:nobody|INT_LATCH[8]' - Info: 2: + IC(0.325 ns) + CELL(0.241 ns) = 0.566 ns; Loc. = LCCOMB_X16_Y12_N20; Fanout = 1; COMB Node = 'interrupt_handler:nobody|_~17' - Info: 3: + IC(0.198 ns) + CELL(0.130 ns) = 0.894 ns; Loc. = LCCOMB_X16_Y12_N22; Fanout = 1; COMB Node = 'interrupt_handler:nobody|nIRQ[5]' - Info: 4: + IC(1.158 ns) + CELL(4.129 ns) = 6.181 ns; Loc. = IOOBUF_X0_Y12_N16; Fanout = 1; COMB Node = 'nIRQ[5]~output' - Info: 5: + IC(0.000 ns) + CELL(0.000 ns) = 6.181 ns; Loc. = PIN_P5; Fanout = 0; PIN Node = 'nIRQ[5]' - Info: Total cell delay = 4.500 ns ( 72.80 % ) - Info: Total interconnect delay = 1.681 ns ( 27.20 % ) -Info: Slack time is -11.944 ns between source pin "nFB_CS1" and destination pin "FB_AD[18]" - Info: + Longest pin to pin requirement is 1.000 ns - Info: - Longest pin to pin delay is 12.944 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_T8; Fanout = 1; PIN Node = 'nFB_CS1' - Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X14_Y0_N29; Fanout = 59; COMB Node = 'nFB_CS1~input' - Info: 3: + IC(1.591 ns) + CELL(0.241 ns) = 2.750 ns; Loc. = LCCOMB_X27_Y14_N12; Fanout = 68; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE_CS~1' - Info: 4: + IC(0.915 ns) + CELL(0.130 ns) = 3.795 ns; Loc. = LCCOMB_X29_Y10_N14; Fanout = 12; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HDB_CS' - Info: 5: + IC(0.302 ns) + CELL(0.342 ns) = 4.439 ns; Loc. = LCCOMB_X29_Y10_N18; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~44' - Info: 6: + IC(0.648 ns) + CELL(0.243 ns) = 5.330 ns; Loc. = LCCOMB_X30_Y13_N24; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~48' - Info: 7: + IC(0.807 ns) + CELL(0.243 ns) = 6.380 ns; Loc. = LCCOMB_X28_Y12_N12; Fanout = 1; COMB Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|lpm_bustri_WORD:$00000|lpm_bustri:lpm_bustri_component|dout[2]~55' - Info: 8: + IC(0.200 ns) + CELL(0.130 ns) = 6.710 ns; Loc. = LCCOMB_X28_Y12_N30; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180_RESYN4_BDD5' - Info: 9: + IC(1.088 ns) + CELL(0.242 ns) = 8.040 ns; Loc. = LCCOMB_X21_Y14_N4; Fanout = 1; COMB Node = 'FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|FB_AD[18]~180' - Info: 10: + IC(0.876 ns) + CELL(4.028 ns) = 12.944 ns; Loc. = IOOBUF_X20_Y0_N23; Fanout = 1; COMB Node = 'FB_AD[18]~output' - Info: 11: + IC(0.000 ns) + CELL(0.000 ns) = 12.944 ns; Loc. = PIN_V9; Fanout = 0; PIN Node = 'FB_AD[18]' - Info: Total cell delay = 6.517 ns ( 50.35 % ) - Info: Total interconnect delay = 6.427 ns ( 49.65 % ) -Warning: Can't achieve timing requirement tpd along 514 path(s). See Report window for details. -Warning: Can't achieve timing requirement th along 117 path(s). See Report window for details. -Info: Minimum slack time is -401 ps for clock "MAIN_CLK" between source pin "FB_AD[25]" and destination register "Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]" - Info: + th requirement for source pin and destination register is 1.000 ns - Info: - th from clock to input pin is 1.401 ns - Info: + Longest clock path from clock "MAIN_CLK" to destination register is 4.679 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_G2; Fanout = 1; CLK Node = 'MAIN_CLK' - Info: 2: + IC(0.000 ns) + CELL(0.981 ns) = 0.981 ns; Loc. = IOIBUF_X0_Y21_N1; Fanout = 2380; COMB Node = 'MAIN_CLK~input' - Info: 3: + IC(3.164 ns) + CELL(0.534 ns) = 4.679 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]' - Info: Total cell delay = 1.515 ns ( 32.38 % ) - Info: Total interconnect delay = 3.164 ns ( 67.62 % ) - Info: + Micro hold delay of destination is 0.157 ns - Info: - Shortest pin to register delay is 3.435 ns - Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_AA9; Fanout = 1; PIN Node = 'FB_AD[25]' - Info: 2: + IC(0.000 ns) + CELL(0.918 ns) = 0.918 ns; Loc. = IOIBUF_X27_Y0_N8; Fanout = 59; COMB Node = 'FB_AD[25]~input' - Info: 3: + IC(2.175 ns) + CELL(0.342 ns) = 3.435 ns; Loc. = FF_X30_Y10_N5; Fanout = 4; REG Node = 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9]' - Info: Total cell delay = 1.260 ns ( 36.68 % ) - Info: Total interconnect delay = 2.175 ns ( 63.32 % ) -Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details. -Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details -Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 65 warnings - Info: Peak virtual memory: 238 megabytes - Info: Processing ended: Wed Dec 15 02:25:23 2010 - Info: Elapsed time: 00:00:09 - Info: Total CPU time (on all processors): 00:00:11 - - diff --git a/FPGA_Quartus_13.1/lpm_counter0_waveforms.html b/FPGA_Quartus_13.1/lpm_counter0_waveforms.html deleted file mode 100644 index b166f94..0000000 --- a/FPGA_Quartus_13.1/lpm_counter0_waveforms.html +++ /dev/null @@ -1,13 +0,0 @@ - - -Sample Waveforms for lpm_counter0.vhd - - -

Sample behavioral waveforms for design file lpm_counter0.vhd

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The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter0.vhd. The design lpm_counter0.vhd is a 18 bit up counter.

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-

Fig. 1 : Wave showing counter operation.

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- - diff --git a/FPGA_Quartus_13.1/lpm_counter1_waveforms.html b/FPGA_Quartus_13.1/lpm_counter1_waveforms.html deleted file mode 100644 index cea3320..0000000 --- a/FPGA_Quartus_13.1/lpm_counter1_waveforms.html +++ /dev/null @@ -1,16 +0,0 @@ - - -Sample Waveforms for lpm_counter1.vhd - - -

Sample behavioral waveforms for design file lpm_counter1.vhd

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The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design lpm_counter1.vhd. The design lpm_counter1.vhd is a 4 bit up modulus 8 counter.

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Fig. 1 : Wave showing counter operation.

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Fig. 2 : Wave showing counter cout and/or modulus operation.

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The counter counts till the modulus value 7.

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- - diff --git a/FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html b/FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html deleted file mode 100644 index 12ad5c2..0000000 --- a/FPGA_Quartus_13.1/lpm_fifo_dc0_waveforms.html +++ /dev/null @@ -1,16 +0,0 @@ - - -Sample Waveforms for "lpm_fifo_dc0.vhd" - - -

Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd"

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The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd". The design "lpm_fifo_dc0.vhd" has a write-side depth of 32 words of 8 bits each. a read-side width of 32. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

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Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions .

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Fig. 2 : Wave showing FIFO full operation.

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The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.

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- - From a6392069924ef3c194486fcb537c2df298382b21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 05:49:54 +0000 Subject: [PATCH 005/127] get rid of more generated files --- FPGA_Quartus_13.1/firebee1.fit.summary | 16 -- FPGA_Quartus_13.1/firebee1.map.summary | 14 -- FPGA_Quartus_13.1/firebee1.tan.summary | 296 ------------------------- FPGA_Quartus_13.1/serv_req_info.txt | 115 ---------- FPGA_Quartus_13.1/undo_redo.txt | 0 5 files changed, 441 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebee1.fit.summary delete mode 100644 FPGA_Quartus_13.1/firebee1.map.summary delete mode 100644 FPGA_Quartus_13.1/firebee1.tan.summary delete mode 100644 FPGA_Quartus_13.1/serv_req_info.txt delete mode 100644 FPGA_Quartus_13.1/undo_redo.txt diff --git a/FPGA_Quartus_13.1/firebee1.fit.summary b/FPGA_Quartus_13.1/firebee1.fit.summary deleted file mode 100644 index f177099..0000000 --- a/FPGA_Quartus_13.1/firebee1.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Wed Dec 15 02:25:02 2010 -Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -Revision Name : firebee1 -Top-level Entity Name : firebee1 -Family : Cyclone III -Device : EP3C40F484C6 -Timing Models : Final -Total logic elements : 9,526 / 39,600 ( 24 % ) - Total combinational functions : 8,061 / 39,600 ( 20 % ) - Dedicated logic registers : 4,563 / 39,600 ( 12 % ) -Total registers : 4749 -Total pins : 295 / 332 ( 89 % ) -Total virtual pins : 0 -Total memory bits : 109,344 / 1,161,216 ( 9 % ) -Embedded Multiplier 9-bit elements : 6 / 252 ( 2 % ) -Total PLLs : 4 / 4 ( 100 % ) diff --git a/FPGA_Quartus_13.1/firebee1.map.summary b/FPGA_Quartus_13.1/firebee1.map.summary deleted file mode 100644 index f8da91e..0000000 --- a/FPGA_Quartus_13.1/firebee1.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Wed Dec 15 02:21:55 2010 -Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -Revision Name : firebee1 -Top-level Entity Name : firebee1 -Family : Cyclone III -Total logic elements : 10,706 - Total combinational functions : 8,060 - Dedicated logic registers : 4,612 -Total registers : 4740 -Total pins : 295 -Total virtual pins : 0 -Total memory bits : 109,344 -Embedded Multiplier 9-bit elements : 6 -Total PLLs : 4 diff --git a/FPGA_Quartus_13.1/firebee1.tan.summary b/FPGA_Quartus_13.1/firebee1.tan.summary deleted file mode 100644 index 219f117..0000000 --- a/FPGA_Quartus_13.1/firebee1.tan.summary +++ /dev/null @@ -1,296 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tsu -Slack : -4.528 ns -Required Time : 1.000 ns -Actual Time : 5.528 ns -From : MAIN_CLK -To : altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|idle_state -From Clock : -- -To Clock : MAIN_CLK -Failed Paths : 6867 - -Type : Worst-case tco -Slack : -14.840 ns -Required Time : 1.000 ns -Actual Time : 15.840 ns -From : interrupt_handler:nobody|INT_LATCH[8] -To : nIRQ[5] -From Clock : MAIN_CLK -To Clock : -- -Failed Paths : 4976 - -Type : Worst-case tpd -Slack : -11.944 ns -Required Time : 1.000 ns -Actual Time : 12.944 ns -From : nFB_CS1 -To : FB_AD[18] -From Clock : -- -To Clock : -- -Failed Paths : 514 - -Type : Worst-case th -Slack : -0.401 ns -Required Time : 1.000 ns -Actual Time : 1.401 ns -From : FB_AD[25] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_HBE[9] -From Clock : -- -To Clock : MAIN_CLK -Failed Paths : 117 - -Type : Clock Setup: 'CLK33M' -Slack : -5.966 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 -To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] -To Clock : CLK33M -Failed Paths : 3741 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' -Slack : -4.615 ns -Required Time : 24.98 MHz ( period = 40.033 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 -To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] -From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] -Failed Paths : 3741 - -Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' -Slack : -4.294 ns -Required Time : 95.92 MHz ( period = 10.425 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ram_block1a1~portb_address_reg0 -To : Video:Fredi_Aschwanden|lpm_muxDZ:inst62|lpm_mux:lpm_mux_component|mux_dcf:auto_generated|external_latency_ffsa[35] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] -To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -Failed Paths : 3741 - -Type : Clock Setup: 'MAIN_CLK' -Slack : -4.261 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : FB_ALE -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|a_graycounter_k47:rdptr_g1p|counter5a7 -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : MAIN_CLK -Failed Paths : 27347 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' -Slack : -2.673 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : FB_ALE -To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|BUS_CYC -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -Failed Paths : 86 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' -Slack : -1.712 ns -Required Time : 66.00 MHz ( period = 15.151 ns ) -Actual Time : N/A -From : FB_ALE -To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -Failed Paths : 29 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' -Slack : 1.672 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_ff0:inst13|lpm_ff:lpm_ff_component|dffs[2] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[2]~DFFHI -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -Failed Paths : 0 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' -Slack : 2.965 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) -From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[6] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[6] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' -Slack : 5.299 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[3] -To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[3] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' -Slack : 28.590 ns -Required Time : 15.99 MHz ( period = 62.552 ns ) -Actual Time : 186.15 MHz ( period = 5.372 ns ) -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|RD_In -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_DIGITAL_PLL:I_DIGITAL_PLL|\EDGEDETECT:LOCK -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' -Slack : 498.663 ns -Required Time : 2.00 MHz ( period = 500.416 ns ) -Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' -Slack : 1997.239 ns -Required Time : 0.50 MHz ( period = 1999.998 ns ) -Actual Time : 362.45 MHz ( period = 2.759 ns ) -From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[0] -To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[17] -From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] -To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'MAIN_CLK' -Slack : -3.786 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VDL_VCT[6] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VERZ[1][0] -From Clock : MAIN_CLK -To Clock : MAIN_CLK -Failed Paths : 108 - -Type : Clock Hold: 'CLK33M' -Slack : -0.687 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] -To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] -From Clock : CLK33M -To Clock : CLK33M -Failed Paths : 26 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2]' -Slack : -0.454 ns -Required Time : 24.98 MHz ( period = 40.033 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] -To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[2] -Failed Paths : 26 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1]' -Slack : 0.502 ns -Required Time : 15.99 MHz ( period = 62.552 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_CONTROL:I_CONTROL|WG~_Duplicate_1 -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' -Slack : 0.502 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] -To : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|a_graycounter_njc:wrptr_gp|counter13a[6] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' -Slack : 0.502 ns -Required Time : 95.92 MHz ( period = 10.425 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] -To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|low_addressa[6] -From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0]' -Slack : 0.564 ns -Required Time : 2.00 MHz ( period = 500.416 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[4] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_41p2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0]' -Slack : 0.825 ns -Required Time : 0.50 MHz ( period = 1999.998 ns ) -Actual Time : N/A -From : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] -To : lpm_counter0:inst18|lpm_counter:lpm_counter_component|cntr_mph:auto_generated|counter_reg_bit[10] -From Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] -To Clock : altpll1:inst|altpll:altpll_component|altpll_pul2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' -Slack : 1.825 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] -To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' -Slack : 2.664 ns -Required Time : 66.00 MHz ( period = 15.151 ns ) -Actual Time : N/A -From : FB_ALE -To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[2] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' -Slack : 3.263 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_ff0:inst14|lpm_ff:lpm_ff_component|dffs[29] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[29]~DFFLO -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' -Slack : 4.336 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[2] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[2] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 51319 - --------------------------------------------------------------------------------------- - diff --git a/FPGA_Quartus_13.1/serv_req_info.txt b/FPGA_Quartus_13.1/serv_req_info.txt deleted file mode 100644 index 51a4176..0000000 --- a/FPGA_Quartus_13.1/serv_req_info.txt +++ /dev/null @@ -1,115 +0,0 @@ - - quartus.exe - VDB - /quartus/db/vdb/vdb_value_bus.cpp - 4101 - - 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) - - loc < m_value->size() - Tue Oct 13 17:01:46 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - loc < m_value->size() -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - VDB - /quartus/db/vdb/vdb_value_bus.cpp - 4101 - - 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) - - loc < m_value->size() - Tue Oct 13 17:11:00 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - loc < m_value->size() -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - unknown - unknown - 0 - Current editor: GED - Wed Oct 14 23:17:06 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - Access Violation at 00000000 -Current editor: GED -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - unknown - unknown - 0 - Current editor: SFW, STED - Thu Oct 15 19:23:19 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - Access Violation at 00000000 -Current editor: SFW, STED -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - unknown - unknown - 0 - - 0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6) - - Current editor: RPW, SFW -Current dockable window: PJN - Fri Oct 16 00:14:03 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - Access Violation at 0X1002D196 -Current editor: RPW, SFW -Current dockable window: PJN -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - unknown - unknown - 0 - Current editor: SFW - Sat Oct 17 19:01:54 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - Access Violation at 00000000 -Current editor: SFW -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - AFC - /quartus/gcl/afc/afc_child_frame.cpp - 1940 - - 0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a) - - (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) - Mon Oct 19 21:58:36 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - - - quartus.exe - unknown - unknown - 0 - Current editor: RPW, GED - Tue Oct 20 00:53:11 2009 - Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - Access Violation at 00000000 -Current editor: RPW, GED -Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition - - diff --git a/FPGA_Quartus_13.1/undo_redo.txt b/FPGA_Quartus_13.1/undo_redo.txt deleted file mode 100644 index e69de29..0000000 From 428c51b9eed15a41e52a12985026978f855b3899 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 05:52:52 +0000 Subject: [PATCH 006/127] remove absolute paths in project file --- FPGA_Quartus_13.1/firebee1.qsf | 340 ++++++++++++++++----------------- 1 file changed, 170 insertions(+), 170 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 86e8842..41d4d37 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -41,173 +41,8 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name BDF_FILE firebee1.bdf -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\FalconIO_SDCard_IDE_CF\\FalconIO_SDCard_IDE_CF.vhd" -set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\DSP\\DSP.vhd" -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name AHDL_FILE "C:\\firebee\\FPGA\\Interrupt_Handler\\interrupt_handler.tdf" -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name VHDL_FILE "C:\\firebee\\FPGA\\Video\\BLITTER\\BLITTER.vhd" -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt # Pin & Location Assignments # ========================== @@ -515,7 +350,6 @@ set_global_assignment -name TSU_REQUIREMENT "1 ns" set_global_assignment -name TCO_REQUIREMENT "1 ns" set_global_assignment -name TH_REQUIREMENT "1 ns" set_global_assignment -name FMAX_REQUIREMENT "30 ns" -set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF # Analysis & Synthesis Assignments # ================================ @@ -733,8 +567,174 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end ENTITY(firebee1) # -------------------- set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" -set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name QIP_FILE altpll4.qip set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name QIP_FILE altpll4.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top \ No newline at end of file From f60e37521b03dfe3a9c4a24c8e0105da9f408968 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 06:21:11 +0000 Subject: [PATCH 007/127] reordered files in project --- FPGA_Quartus_13.1/firebee1.qsf | 177 +++++++++++++++++---------------- 1 file changed, 91 insertions(+), 86 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 41d4d37..4a7939a 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -569,108 +569,56 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name DISABLE_OCP_HW_EVAL ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE altpll0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp @@ -683,11 +631,11 @@ set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name BDF_FILE firebee1.bdf -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip set_global_assignment -name QIP_FILE Video/altdpram0.qip set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip @@ -710,13 +658,13 @@ set_global_assignment -name QIP_FILE Video/lpm_latch1.qip set_global_assignment -name QIP_FILE Video/lpm_constant4.qip set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp set_global_assignment -name QIP_FILE Video/lpm_ff4.qip set_global_assignment -name QIP_FILE Video/lpm_ff5.qip set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip set_global_assignment -name QIP_FILE Video/altddio_out0.qip @@ -726,15 +674,72 @@ set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip set_global_assignment -name QIP_FILE Video/altddio_out1.qip set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf +set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name QIP_FILE altpll4.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top \ No newline at end of file +set_global_assignment -name QIP_FILE altpll4.qip \ No newline at end of file From 7efdf33216e0e8665a64e3b63768b08951e3f3a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 07:00:34 +0000 Subject: [PATCH 008/127] get rid of more generated files --- FPGA_Quartus_13.1/firebee1.done | 1 - FPGA_Quartus_13.1/firebee1.pin | 557 -------------------------------- FPGA_Quartus_13.1/firebee1.qsf | 35 +- FPGA_Quartus_13.1/firebee1.rbf | Bin 428953 -> 0 bytes FPGA_Quartus_13.1/firebee1.sof | Bin 1171297 -> 0 bytes 5 files changed, 18 insertions(+), 575 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebee1.done delete mode 100644 FPGA_Quartus_13.1/firebee1.pin delete mode 100644 FPGA_Quartus_13.1/firebee1.rbf delete mode 100644 FPGA_Quartus_13.1/firebee1.sof diff --git a/FPGA_Quartus_13.1/firebee1.done b/FPGA_Quartus_13.1/firebee1.done deleted file mode 100644 index 1674c93..0000000 --- a/FPGA_Quartus_13.1/firebee1.done +++ /dev/null @@ -1 +0,0 @@ -Wed Dec 15 02:25:24 2010 diff --git a/FPGA_Quartus_13.1/firebee1.pin b/FPGA_Quartus_13.1/firebee1.pin deleted file mode 100644 index 50b8dd7..0000000 --- a/FPGA_Quartus_13.1/firebee1.pin +++ /dev/null @@ -1,557 +0,0 @@ - -- Copyright (C) 1991-2010 Altera Corporation - -- Your use of Altera Corporation's design tools, logic functions - -- and other software and tools, and its AMPP partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Altera Program License - -- Subscription Agreement, Altera MegaCore Function License - -- Agreement, or other applicable license agreement, including, - -- without limitation, that your use is for the sole purpose of - -- programming logic devices manufactured by Altera and sold by - -- Altera or its authorized distributors. Please refer to the - -- applicable agreement for further details. - -- - -- This is a Quartus II output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus II input file. This file cannot be used - -- to make Quartus II pin assignments - for instructions on how to make pin - -- assignments, please see Quartus II help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- Bank 3: 3.3V - -- Bank 4: 2.5V - -- Bank 5: 2.5V - -- Bank 6: 3.0V - -- Bank 7: 3.3V - -- Bank 8: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* - -- either individually through a 10k Ohm resistor to GND or tie all pins - -- together and connect through a single 10k Ohm resistor to GND. - -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition -CHIP "firebee1" ASSIGNED TO AN: EP3C40F484C6 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -GND : A1 : gnd : : : : -VCCIO8 : A2 : power : : 3.3V : 8 : -LP_D[6] : A3 : bidir : 3.3-V LVTTL : : 8 : Y -nSRBLE : A4 : output : 3.3-V LVTTL : : 8 : Y -SRD[1] : A5 : bidir : 3.3-V LVTTL : : 8 : Y -IO[3] : A6 : bidir : 3.3-V LVTTL : : 8 : Y -IO[1] : A7 : bidir : 3.3-V LVTTL : : 8 : Y -IO[0] : A8 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[10] : A9 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[9] : A10 : bidir : 3.3-V LVTTL : : 8 : Y -DVI_INT : A11 : input : 3.3-V LVTTL : : 8 : Y -nDACK1 : A12 : input : 3.3-V LVTTL : : 7 : Y -IO[16] : A13 : bidir : 3.3-V LVTTL : : 7 : Y -IO[14] : A14 : bidir : 3.3-V LVTTL : : 7 : Y -IO[9] : A15 : bidir : 3.3-V LVTTL : : 7 : Y -SD_DATA1 : A16 : input : 3.3-V LVTTL : : 7 : Y -YM_QA : A17 : output : 3.3-V LVTTL : : 7 : Y -TxD : A18 : output : 3.3-V LVTTL : : 7 : Y -DCD : A19 : input : 3.3-V LVTTL : : 7 : Y -nRD_DATA : A20 : input : 3.3-V LVTTL : : 7 : Y -VCCIO7 : A21 : power : : 3.3V : 7 : -GND : A22 : gnd : : : : -nPCI_INTA : AA1 : input : 3.3-V LVTTL : : 2 : Y -PIC_INT : AA2 : input : 3.3-V LVTTL : : 2 : Y -FB_AD[2] : AA3 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[6] : AA4 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[8] : AA5 : bidir : 3.3-V LVTTL : : 3 : Y -VCCIO3 : AA6 : power : : 3.3V : 3 : -FB_AD[15] : AA7 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[22] : AA8 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[25] : AA9 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[31] : AA10 : bidir : 3.3-V LVTTL : : 3 : Y -GND+ : AA11 : : : : 3 : -GND+ : AA12 : : : : 4 : -VD[18] : AA13 : bidir : 2.5 V : : 4 : Y -VD[25] : AA14 : bidir : 2.5 V : : 4 : Y -VDQS[0] : AA15 : bidir : 2.5 V : : 4 : Y -VDM[0] : AA16 : output : 2.5 V : : 4 : Y -nDDR_CLK : AA17 : output : 2.5 V : : 4 : Y -VA[12] : AA18 : output : 2.5 V : : 4 : Y -BA[1] : AA19 : output : 2.5 V : : 4 : Y -VA[7] : AA20 : output : 2.5 V : : 4 : Y -VA[6] : AA21 : output : 2.5 V : : 5 : Y -VA[4] : AA22 : output : 2.5 V : : 5 : Y -GND : AB1 : gnd : : : : -VCCIO3 : AB2 : power : : 3.3V : 3 : -FB_AD[3] : AB3 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[7] : AB4 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[9] : AB5 : bidir : 3.3-V LVTTL : : 3 : Y -GND : AB6 : gnd : : : : -FB_AD[16] : AB7 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[23] : AB8 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[26] : AB9 : bidir : 3.3-V LVTTL : : 3 : Y -CLK24M576 : AB10 : output : 3.3-V LVTTL : : 3 : Y -GND+ : AB11 : : : : 3 : -CLK33M : AB12 : input : 3.3-V LVTTL : : 4 : Y -VD[29] : AB13 : bidir : 2.5 V : : 4 : Y -VD[26] : AB14 : bidir : 2.5 V : : 4 : Y -VD[24] : AB15 : bidir : 2.5 V : : 4 : Y -VD[23] : AB16 : bidir : 2.5 V : : 4 : Y -DDR_CLK : AB17 : output : 2.5 V : : 4 : Y -nVCAS : AB18 : output : 2.5 V : : 4 : Y -VA[9] : AB19 : output : 2.5 V : : 4 : Y -VA[8] : AB20 : output : 2.5 V : : 4 : Y -VCCIO4 : AB21 : power : : 2.5V : 4 : -GND : AB22 : gnd : : : : -ACSI_D[0] : B1 : bidir : 3.3-V LVTTL : : 1 : Y -MIDI_TLR : B2 : output : 3.3-V LVTTL : : 1 : Y -LP_D[5] : B3 : bidir : 3.3-V LVTTL : : 8 : Y -nSRBHE : B4 : output : 3.3-V LVTTL : : 8 : Y -SRD[0] : B5 : bidir : 3.3-V LVTTL : : 8 : Y -IO[4] : B6 : bidir : 3.3-V LVTTL : : 8 : Y -IO[2] : B7 : bidir : 3.3-V LVTTL : : 8 : Y -nSRCS : B8 : output : 3.3-V LVTTL : : 8 : Y -SRD[8] : B9 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[11] : B10 : bidir : 3.3-V LVTTL : : 8 : Y -nRSTO_MCF : B11 : input : 3.3-V LVTTL : : 8 : Y -nDACK0 : B12 : input : 3.3-V LVTTL : : 7 : Y -IO[17] : B13 : bidir : 3.3-V LVTTL : : 7 : Y -IO[15] : B14 : bidir : 3.3-V LVTTL : : 7 : Y -IO[10] : B15 : bidir : 3.3-V LVTTL : : 7 : Y -SD_DATA0 : B16 : input : 3.3-V LVTTL : : 7 : Y -SD_DATA2 : B17 : input : 3.3-V LVTTL : : 7 : Y -RTS : B18 : output : 3.3-V LVTTL : : 7 : Y -RI : B19 : input : 3.3-V LVTTL : : 7 : Y -nSDSEL : B20 : output : 3.3-V LVTTL : : 7 : Y -VB[5] : B21 : output : 3.0-V LVTTL : : 6 : Y -VB[4] : B22 : output : 3.0-V LVTTL : : 6 : Y -ACSI_D[4] : C1 : bidir : 3.3-V LVTTL : : 1 : Y -ACSI_D[3] : C2 : bidir : 3.3-V LVTTL : : 1 : Y -LP_D[2] : C3 : bidir : 3.3-V LVTTL : : 8 : Y -LP_D[1] : C4 : bidir : 3.3-V LVTTL : : 8 : Y -GND : C5 : gnd : : : : -SRD[2] : C6 : bidir : 3.3-V LVTTL : : 8 : Y -IO[7] : C7 : bidir : 3.3-V LVTTL : : 8 : Y -IO[6] : C8 : bidir : 3.3-V LVTTL : : 8 : Y -GND : C9 : gnd : : : : -SRD[4] : C10 : bidir : 3.3-V LVTTL : : 8 : Y -GND : C11 : gnd : : : : -GND : C12 : gnd : : : : -IO[11] : C13 : bidir : 3.3-V LVTTL : : 7 : Y -GND : C14 : gnd : : : : -SD_CLK : C15 : output : 3.3-V LVTTL : : 7 : Y -GND : C16 : gnd : : : : -nDCHG : C17 : input : 3.3-V LVTTL : : 7 : Y -GND : C18 : gnd : : : : -TRACK00 : C19 : input : 3.3-V LVTTL : : 7 : Y -VB[6] : C20 : output : 3.0-V LVTTL : : 6 : Y -VB[3] : C21 : output : 3.0-V LVTTL : : 6 : Y -VB[2] : C22 : output : 3.0-V LVTTL : : 6 : Y -~ALTERA_ASDO_DATA1~ / RESERVED_INPUT : D1 : input : 3.3-V LVTTL : : 1 : N -ACSI_D[5] : D2 : bidir : 3.3-V LVTTL : : 1 : Y -GND : D3 : gnd : : : : -VCCIO1 : D4 : power : : 3.3V : 1 : -VCCIO8 : D5 : power : : 3.3V : 8 : -LP_D[4] : D6 : bidir : 3.3-V LVTTL : : 8 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8 : -GND : D8 : gnd : : : : -VCCIO8 : D9 : power : : 3.3V : 8 : -SRD[12] : D10 : bidir : 3.3-V LVTTL : : 8 : Y -VCCIO8 : D11 : power : : 3.3V : 8 : -VCCIO7 : D12 : power : : 3.3V : 7 : -IO[12] : D13 : bidir : 3.3-V LVTTL : : 7 : Y -VCCIO7 : D14 : power : : 3.3V : 7 : -DTR : D15 : output : 3.3-V LVTTL : : 7 : Y -VCCIO7 : D16 : power : : 3.3V : 7 : -nWR_GATE : D17 : output : 3.3-V LVTTL : : 7 : Y -VCCIO7 : D18 : power : : 3.3V : 7 : -nWP : D19 : input : 3.3-V LVTTL : : 7 : Y -VB[7] : D20 : output : 3.0-V LVTTL : : 6 : Y -VG[7] : D21 : output : 3.0-V LVTTL : : 6 : Y -VG[6] : D22 : output : 3.0-V LVTTL : : 6 : Y -SCSI_D[1] : E1 : bidir : 3.3-V LVTTL : : 1 : Y -~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT : E2 : input : 3.3-V LVTTL : : 1 : N -ACSI_D[2] : E3 : bidir : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 1 : -LPDIR : E5 : output : 3.3-V LVTTL : : 8 : Y -LP_STR : E6 : output : 3.3-V LVTTL : : 8 : Y -LP_D[3] : E7 : bidir : 3.3-V LVTTL : : 8 : Y -VCCIO8 : E8 : power : : 3.3V : 8 : -IO[5] : E9 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[6] : E10 : bidir : 3.3-V LVTTL : : 8 : Y -nDREQ1 : E11 : output : 3.3-V LVTTL : : 7 : Y -MIDI_IN : E12 : input : 3.3-V LVTTL : : 7 : Y -IO[13] : E13 : bidir : 3.3-V LVTTL : : 7 : Y -SD_CMD_D1 : E14 : bidir : 3.3-V LVTTL : : 7 : Y -YM_QC : E15 : output : 3.3-V LVTTL : : 7 : Y -nINDEX : E16 : input : 3.3-V LVTTL : : 7 : Y -VCCD_PLL2 : E17 : power : : 1.2V : : -GNDA2 : E18 : gnd : : : : -VCCIO6 : E19 : power : : 3.0V : 6 : -GND : E20 : gnd : : : : -VG[2] : E21 : output : 3.0-V LVTTL : : 6 : Y -VG[1] : E22 : output : 3.0-V LVTTL : : 6 : Y -SCSI_D[3] : F1 : bidir : 3.3-V LVTTL : : 1 : Y -SCSI_D[2] : F2 : bidir : 3.3-V LVTTL : : 1 : Y -GND : F3 : gnd : : : : -VCCIO1 : F4 : power : : 3.3V : 1 : -GNDA3 : F5 : gnd : : : : -VCCD_PLL3 : F6 : power : : 1.2V : : -LP_D[0] : F7 : bidir : 3.3-V LVTTL : : 8 : Y -nSRWE : F8 : output : 3.3-V LVTTL : : 8 : Y -SRD[5] : F9 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[13] : F10 : bidir : 3.3-V LVTTL : : 8 : Y -nSROE : F11 : output : 3.3-V LVTTL : : 7 : Y -GND : F12 : gnd : : : : -SD_CD_DATA3 : F13 : bidir : 3.3-V LVTTL : : 7 : Y -nSTEP : F14 : output : 3.3-V LVTTL : : 7 : Y -DSA_D : F15 : output : 3.3-V LVTTL : : 7 : Y -HD_DD : F16 : input : 3.3-V LVTTL : : 7 : Y -nSYNC : F17 : output : 3.0-V LVCMOS : : 6 : Y -VCCA2 : F18 : power : : 2.5V : : -PIXEL_CLK_PAD : F19 : output : 3.0-V LVTTL : : 6 : Y -nIRQ[4] : F20 : output : 3.0-V LVCMOS : : 6 : Y -nIRQ[2] : F21 : output : 3.0-V LVCMOS : : 6 : Y -VR[7] : F22 : output : 3.0-V LVTTL : : 6 : Y -GND+ : G1 : : : : 1 : -MAIN_CLK : G2 : input : 3.3-V LVTTL : : 1 : Y -SCSI_D[5] : G3 : bidir : 3.3-V LVTTL : : 1 : Y -SCSI_D[4] : G4 : bidir : 3.3-V LVTTL : : 1 : Y -ACSI_D[1] : G5 : bidir : 3.3-V LVTTL : : 1 : Y -VCCA3 : G6 : power : : 2.5V : : -LP_BUSY : G7 : input : 3.3-V LVTTL : : 8 : Y -LP_D[7] : G8 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[14] : G9 : bidir : 3.3-V LVTTL : : 8 : Y -IO[8] : G10 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[3] : G11 : bidir : 3.3-V LVTTL : : 8 : Y -VCCINT : G12 : power : : 1.2V : : -YM_QB : G13 : output : 3.3-V LVTTL : : 7 : Y -nWR : G14 : output : 3.3-V LVTTL : : 7 : Y -nSTEP_DIR : G15 : output : 3.3-V LVTTL : : 7 : Y -nMOT_ON : G16 : output : 3.3-V LVTTL : : 7 : Y -nBLANK_PAD : G17 : output : 3.0-V LVTTL : : 6 : Y -VB[0] : G18 : output : 3.0-V LVTTL : : 6 : Y -VCCIO6 : G19 : power : : 3.0V : 6 : -GND : G20 : gnd : : : : -E0_INT : G21 : input : 3.3-V LVTTL : : 6 : Y -IDE_INT : G22 : input : 3.3-V LVTTL : : 6 : Y -nSCSI_C_D : H1 : input : 3.3-V LVTTL : : 1 : Y -nSCSI_MSG : H2 : input : 3.3-V LVTTL : : 1 : Y -GND : H3 : gnd : : : : -VCCIO1 : H4 : power : : 3.3V : 1 : -MIDI_OLR : H5 : output : 3.3-V LVTTL : : 1 : Y -ACSI_D[7] : H6 : bidir : 3.3-V LVTTL : : 1 : Y -ACSI_D[6] : H7 : bidir : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 1 : -VCCINT : H9 : power : : 1.2V : : -SRD[15] : H10 : bidir : 3.3-V LVTTL : : 8 : Y -SRD[7] : H11 : bidir : 3.3-V LVTTL : : 8 : Y -GND : H12 : gnd : : : : -GND : H13 : gnd : : : : -CTS : H14 : input : 3.3-V LVTTL : : 7 : Y -RxD : H15 : input : 3.3-V LVTTL : : 7 : Y -VG[5] : H16 : output : 3.0-V LVTTL : : 6 : Y -VB[1] : H17 : output : 3.0-V LVTTL : : 6 : Y -VG[3] : H18 : output : 3.0-V LVTTL : : 6 : Y -VG[0] : H19 : output : 3.0-V LVTTL : : 6 : Y -nIRQ[3] : H20 : output : 3.0-V LVCMOS : : 6 : Y -VR[3] : H21 : output : 3.0-V LVTTL : : 6 : Y -VR[2] : H22 : output : 3.0-V LVTTL : : 6 : Y -CLKUSB : J1 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : J2 : : : : 1 : -nSCSI_I_O : J3 : input : 3.3-V LVTTL : : 1 : Y -nACSI_INT : J4 : input : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : J5 : : : : 1 : -SCSI_D[0] : J6 : bidir : 3.3-V LVTTL : : 1 : Y -SCSI_DIR : J7 : output : 3.3-V LVTTL : : 1 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : J8 : : : : 1 : -GND : J9 : gnd : : : : -VCCINT : J10 : power : : 1.2V : : -VCCINT : J11 : power : : 1.2V : : -VCCINT : J12 : power : : 1.2V : : -VCCINT : J13 : power : : 1.2V : : -VCCINT : J14 : power : : 1.2V : : -GND : J15 : gnd : : : : -VCCINT : J16 : power : : 1.2V : : -VG[4] : J17 : output : 3.0-V LVTTL : : 6 : Y -VR[6] : J18 : output : 3.0-V LVTTL : : 6 : Y -GND : J19 : gnd : : : : -VCCIO6 : J20 : power : : 3.0V : 6 : -VR[1] : J21 : output : 3.0-V LVTTL : : 6 : Y -VR[0] : J22 : output : 3.0-V LVTTL : : 6 : Y -~ALTERA_DATA0~ / RESERVED_INPUT : K1 : input : 3.3-V LVTTL : : 1 : N -~ALTERA_DCLK~ / RESERVED_INPUT : K2 : input : 3.3-V LVTTL : : 1 : N -GND : K3 : gnd : : : : -VCCIO1 : K4 : power : : 3.3V : 1 : -nCONFIG : K5 : : : : 1 : -nSTATUS : K6 : : : : 1 : -nACSI_DRQ : K7 : input : 3.3-V LVTTL : : 1 : Y -SCSI_D[7] : K8 : bidir : 3.3-V LVTTL : : 1 : Y -VCCINT : K9 : power : : 1.2V : : -GND : K10 : gnd : : : : -GND : K11 : gnd : : : : -GND : K12 : gnd : : : : -GND : K13 : gnd : : : : -VCCINT : K14 : power : : 1.2V : : -VCCINT : K15 : power : : 1.2V : : -GND : K16 : gnd : : : : -VR[4] : K17 : output : 3.0-V LVTTL : : 6 : Y -VR[5] : K18 : output : 3.0-V LVTTL : : 6 : Y -VSYNC_PAD : K19 : output : 3.0-V LVTTL : : 6 : Y -MSEL3 : K20 : : : : 6 : -HSYNC_PAD : K21 : output : 3.0-V LVTTL : : 6 : Y -~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : K22 : output : 3.0-V LVTTL : : 6 : N -TMS : L1 : input : : : 1 : -TCK : L2 : input : : : 1 : -nCE : L3 : : : : 1 : -TDO : L4 : output : : : 1 : -TDI : L5 : input : : : 1 : -ACSI_DIR : L6 : output : 3.3-V LVTTL : : 2 : Y -PIC_AMKB_RX : L7 : input : 3.3-V LVTTL : : 2 : Y -SCSI_D[6] : L8 : bidir : 3.3-V LVTTL : : 1 : Y -VCCINT : L9 : power : : 1.2V : : -GND : L10 : gnd : : : : -GND : L11 : gnd : : : : -GND : L12 : gnd : : : : -GND : L13 : gnd : : : : -VCCINT : L14 : power : : 1.2V : : -GND : L15 : gnd : : : : -VCCINT : L16 : power : : 1.2V : : -MSEL2 : L17 : : : : 6 : -MSEL1 : L18 : : : : 6 : -VCCIO6 : L19 : power : : 3.0V : 6 : -GND : L20 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : -RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : -nACSI_RESET : M1 : output : 3.3-V LVTTL : : 2 : Y -nACSI_CS : M2 : output : 3.3-V LVTTL : : 2 : Y -nSCSI_ATN : M3 : output : 3.3-V LVTTL : : 2 : Y -nACSI_ACK : M4 : output : 3.3-V LVTTL : : 2 : Y -IDE_RES : M5 : output : 3.3-V LVTTL : : 2 : Y -ACSI_A1 : M6 : output : 3.3-V LVTTL : : 2 : Y -SCSI_PAR : M7 : bidir : 3.3-V LVTTL : : 2 : Y -nSCSI_SEL : M8 : bidir : 3.3-V LVTTL : : 2 : Y -VCCINT : M9 : power : : 1.2V : : -GND : M10 : gnd : : : : -GND : M11 : gnd : : : : -GND : M12 : gnd : : : : -GND : M13 : gnd : : : : -VCCINT : M14 : power : : 1.2V : : -VCCINT : M15 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : M16 : : : : 5 : -MSEL0 : M17 : : : : 6 : -CONF_DONE : M18 : : : : 6 : -SD_WP : M19 : input : 3.3-V LVTTL : : 5 : Y -SD_CARD_DEDECT : M20 : input : 3.3-V LVTTL : : 5 : Y -VD[1] : M21 : bidir : 2.5 V : : 5 : Y -VD[0] : M22 : bidir : 2.5 V : : 5 : Y -AMKB_TX : N1 : output : 3.3-V LVCMOS : : 2 : Y -nSCSI_ACK : N2 : output : 3.3-V LVTTL : : 2 : Y -GND : N3 : gnd : : : : -VCCIO2 : N4 : power : : 3.3V : 2 : -nRP_LDS : N5 : output : 3.3-V LVTTL : : 2 : Y -nSCSI_RST : N6 : bidir : 3.3-V LVTTL : : 2 : Y -nIRQ[7] : N7 : output : 3.3-V LVTTL : : 2 : Y -nSCSI_BUSY : N8 : bidir : 3.3-V LVTTL : : 2 : Y -VCCINT : N9 : power : : 1.2V : : -GND : N10 : gnd : : : : -GND : N11 : gnd : : : : -GND : N12 : gnd : : : : -GND : N13 : gnd : : : : -VCCINT : N14 : power : : 1.2V : : -GND : N15 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 5 : -VD[12] : N17 : bidir : 2.5 V : : 5 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 5 : -LED_FPGA_OK : N19 : output : 2.5 V : : 5 : Y -VD[15] : N20 : bidir : 2.5 V : : 5 : Y -~ALTERA_DEV_CLRn~ / RESERVED_INPUT : N21 : input : 2.5 V : : 5 : N -~ALTERA_DEV_OE~ / RESERVED_INPUT : N22 : input : 2.5 V : : 5 : N -nIDE_RD : P1 : output : 3.3-V LVTTL : : 2 : Y -nIDE_WR : P2 : output : 3.3-V LVTTL : : 2 : Y -nROM3 : P3 : output : 3.3-V LVTTL : : 2 : Y -nRP_UDS : P4 : output : 3.3-V LVTTL : : 2 : Y -nIRQ[5] : P5 : output : 3.3-V LVTTL : : 2 : Y -nPCI_INTD : P6 : input : 3.3-V LVTTL : : 2 : Y -nIRQ[6] : P7 : output : 3.3-V LVTTL : : 2 : Y -GND : P8 : gnd : : : : -VCCINT : P9 : power : : 1.2V : : -VCCINT : P10 : power : : 1.2V : : -VCCINT : P11 : power : : 1.2V : : -VCCINT : P12 : power : : 1.2V : : -VCCINT : P13 : power : : 1.2V : : -VCCINT : P14 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : P15 : : : : 5 : -RESERVED_INPUT_WITH_WEAK_PULLUP : P16 : : : : 5 : -VD[10] : P17 : bidir : 2.5 V : : 5 : Y -VCCIO5 : P18 : power : : 2.5V : 5 : -GND : P19 : gnd : : : : -VD[13] : P20 : bidir : 2.5 V : : 5 : Y -VD[4] : P21 : bidir : 2.5 V : : 5 : Y -VD[2] : P22 : bidir : 2.5 V : : 5 : Y -nIDE_CS1 : R1 : output : 3.3-V LVTTL : : 2 : Y -nIDE_CS0 : R2 : output : 3.3-V LVTTL : : 2 : Y -GND : R3 : gnd : : : : -VCCIO2 : R4 : power : : 3.3V : 2 : -TIN0 : R5 : output : 3.3-V LVTTL : : 2 : Y -nFB_OE : R6 : input : 3.3-V LVTTL : : 2 : Y -FB_ALE : R7 : input : 3.3-V LVTTL : : 2 : Y -VCCINT : R8 : power : : 1.2V : : -GND : R9 : gnd : : : : -VCCINT : R10 : power : : 1.2V : : -GND : R11 : gnd : : : : -VCCINT : R12 : power : : 1.2V : : -GND : R13 : gnd : : : : -RESERVED_INPUT_WITH_WEAK_PULLUP : R14 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R15 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : R16 : : : : 4 : -VD[5] : R17 : bidir : 2.5 V : : 5 : Y -VD[9] : R18 : bidir : 2.5 V : : 5 : Y -VD[6] : R19 : bidir : 2.5 V : : 5 : Y -VD[3] : R20 : bidir : 2.5 V : : 5 : Y -VD[11] : R21 : bidir : 2.5 V : : 5 : Y -VD[14] : R22 : bidir : 2.5 V : : 5 : Y -WP_CF_CARD : T1 : input : 3.3-V LVTTL : : 2 : Y -GND+ : T2 : : : : 2 : -nFB_BURST : T3 : input : 3.3-V LVTTL : : 2 : Y -CLK25M : T4 : output : 3.3-V LVTTL : : 2 : Y -nFB_WR : T5 : input : 3.3-V LVTTL : : 2 : Y -VCCA1 : T6 : power : : 2.5V : : -nFB_TA : T7 : output : 3.3-V LVTTL : : 2 : Y -nFB_CS1 : T8 : input : 3.3-V LVTTL : : 3 : Y -nFB_CS2 : T9 : input : 3.3-V LVTTL : : 3 : Y -FB_AD[20] : T10 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[24] : T11 : bidir : 3.3-V LVTTL : : 3 : Y -VD[16] : T12 : bidir : 2.5 V : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : T13 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T14 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : T15 : : : : 4 : -VDQS[3] : T16 : bidir : 2.5 V : : 4 : Y -VDM[3] : T17 : output : 2.5 V : : 5 : Y -nVCS : T18 : output : 2.5 V : : 5 : Y -VCCIO5 : T19 : power : : 2.5V : 5 : -GND : T20 : gnd : : : : -nMASTER : T21 : input : 3.3-V LVTTL : : 5 : Y -TOUT0 : T22 : input : 3.3-V LVTTL : : 5 : Y -nSCSI_DRQ : U1 : input : 3.3-V LVTTL : : 2 : Y -nROM4 : U2 : output : 3.3-V LVTTL : : 2 : Y -GND : U3 : gnd : : : : -VCCIO2 : U4 : power : : 3.3V : 2 : -GNDA1 : U5 : gnd : : : : -VCCD_PLL1 : U6 : power : : 1.2V : : -RESERVED_INPUT_WITH_WEAK_PULLUP : U7 : : : : 3 : -FB_SIZE0 : U8 : input : 3.3-V LVTTL : : 3 : Y -FB_AD[12] : U9 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[21] : U10 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[27] : U11 : bidir : 3.3-V LVTTL : : 3 : Y -VD[31] : U12 : bidir : 2.5 V : : 4 : Y -VD[20] : U13 : bidir : 2.5 V : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : U14 : : : : 4 : -VCKE : U15 : output : 2.5 V : : 4 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : U16 : : : : 4 : -RESERVED_INPUT_WITH_WEAK_PULLUP : U17 : : : : 4 : -VCCA4 : U18 : power : : 2.5V : : -VA[11] : U19 : output : 2.5 V : : 5 : Y -VDM[2] : U20 : output : 2.5 V : : 5 : Y -VD[7] : U21 : bidir : 2.5 V : : 5 : Y -VDQS[2] : U22 : bidir : 2.5 V : : 5 : Y -nPD_VGA : V1 : output : 3.3-V LVTTL : : 2 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : V2 : : : : 2 : -nPCI_INTC : V3 : input : 3.3-V LVTTL : : 2 : Y -nPCI_INTB : V4 : input : 3.3-V LVTTL : : 2 : Y -RESERVED_INPUT_WITH_WEAK_PULLUP : V5 : : : : 3 : -nFB_CS3 : V6 : input : 3.3-V LVTTL : : 3 : Y -FB_AD[5] : V7 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[13] : V8 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[18] : V9 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[19] : V10 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[28] : V11 : bidir : 3.3-V LVTTL : : 3 : Y -VD[30] : V12 : bidir : 2.5 V : : 4 : Y -VD[27] : V13 : bidir : 2.5 V : : 4 : Y -VD[19] : V14 : bidir : 2.5 V : : 4 : Y -VD[21] : V15 : bidir : 2.5 V : : 4 : Y -VDM[1] : V16 : output : 2.5 V : : 4 : Y -VCCD_PLL4 : V17 : power : : 1.2V : : -GNDA4 : V18 : gnd : : : : -VCCIO5 : V19 : power : : 2.5V : 5 : -GND : V20 : gnd : : : : -VA[10] : V21 : output : 2.5 V : : 5 : Y -VD[8] : V22 : bidir : 2.5 V : : 5 : Y -nCF_CS1 : W1 : output : 3.3-V LVTTL : : 2 : Y -nCF_CS0 : W2 : output : 3.3-V LVTTL : : 2 : Y -GND : W3 : gnd : : : : -VCCIO2 : W4 : power : : 3.3V : 2 : -VCCIO3 : W5 : power : : 3.3V : 3 : -FB_AD[4] : W6 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[10] : W7 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[14] : W8 : bidir : 3.3-V LVTTL : : 3 : Y -VCCIO3 : W9 : power : : 3.3V : 3 : -FB_AD[29] : W10 : bidir : 3.3-V LVTTL : : 3 : Y -VCCIO3 : W11 : power : : 3.3V : 3 : -VCCIO4 : W12 : power : : 2.5V : 4 : -VD[28] : W13 : bidir : 2.5 V : : 4 : Y -VD[22] : W14 : bidir : 2.5 V : : 4 : Y -VDQS[1] : W15 : bidir : 2.5 V : : 4 : Y -VCCIO4 : W16 : power : : 2.5V : 4 : -nVRAS : W17 : output : 2.5 V : : 4 : Y -VCCIO4 : W18 : power : : 2.5V : 4 : -BA[0] : W19 : output : 2.5 V : : 5 : Y -VA[0] : W20 : output : 2.5 V : : 5 : Y -VA[2] : W21 : output : 2.5 V : : 5 : Y -VA[1] : W22 : output : 2.5 V : : 5 : Y -IDE_RDY : Y1 : input : 3.3-V LVTTL : : 2 : Y -AMKB_RX : Y2 : input : 3.3-V LVTTL : : 2 : Y -FB_AD[0] : Y3 : bidir : 3.3-V LVTTL : : 3 : Y -FB_SIZE1 : Y4 : input : 3.3-V LVTTL : : 3 : Y -GND : Y5 : gnd : : : : -FB_AD[1] : Y6 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[11] : Y7 : bidir : 3.3-V LVTTL : : 3 : Y -FB_AD[17] : Y8 : bidir : 3.3-V LVTTL : : 3 : Y -GND : Y9 : gnd : : : : -FB_AD[30] : Y10 : bidir : 3.3-V LVTTL : : 3 : Y -GND : Y11 : gnd : : : : -GND : Y12 : gnd : : : : -VD[17] : Y13 : bidir : 2.5 V : : 4 : Y -VCCIO4 : Y14 : power : : 2.5V : 4 : -GND : Y15 : gnd : : : : -GND : Y16 : gnd : : : : -nVWE : Y17 : output : 2.5 V : : 4 : Y -GND : Y18 : gnd : : : : -VCCIO5 : Y19 : power : : 2.5V : 5 : -GND : Y20 : gnd : : : : -VA[5] : Y21 : output : 2.5 V : : 5 : Y -VA[3] : Y22 : output : 2.5 V : : 5 : Y diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 4a7939a..ef227ea 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -569,13 +569,13 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name DISABLE_OCP_HW_EVAL ON set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name SDC_FILE firebee1.sdc set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf set_global_assignment -name VHDL_FILE DSP/DSP.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd @@ -617,7 +617,6 @@ set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp @@ -632,7 +631,6 @@ set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd set_global_assignment -name BDF_FILE Video/Video.bdf set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp @@ -682,6 +680,8 @@ set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd @@ -721,19 +721,21 @@ set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip set_global_assignment -name VHDL_FILE lpm_latch0.vhd set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name BDF_FILE firebee1.bdf set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name BDF_FILE firebee1.bdf set_global_assignment -name QIP_FILE lpm_counter0.qip set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip @@ -741,5 +743,4 @@ set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name QIP_FILE altpll4.qip \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.rbf b/FPGA_Quartus_13.1/firebee1.rbf deleted file mode 100644 index 63c16f1d687e91f02187b06b1c5e3ecfe12b2e04..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 428953 zcmeFaeY_l3dFNSGw>q^PJ~A=Q+=L>QwvdU;pNC;{O8v_HQ5i>SJI1 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Sample behavioral waveforms for design file altdpram0.vhd

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The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

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Fig. 1 : Wave showing read operation.

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The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

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Fig. 2 : Waveform showing write operation

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The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

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zpZhYz=TR0wc$OwW%DTrC2%p^WMhL$K0@hac&wNnx2q1hy1*_Yg57M4r2*y&0pC8T| zAbjYzjp@Zxl>eTV|L3)g7P>gTi!Gm`$08ed zw)&84@$|jebc8g)k?OBMJV$Es=Kd17h9H|MiDMcp8o#Oke)tT9w>WWMS-Lsl@m49r zCJT0Qu+{Bj7te(>`;7YL(a$s$SvF%mu><+BX|C6py);*a%=sdt2fb7`X`5KN?668| z7d$ODhIy#0p9 - -Sample Waveforms for altdpram1.vhd - - -

Sample behavioral waveforms for design file altdpram1.vhd

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The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

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Fig. 1 : Wave showing read operation.

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The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

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Fig. 2 : Waveform showing write operation

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The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

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Sample behavioral waveforms for design file altdpram2.vhd

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The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

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Fig. 1 : Wave showing read operation.

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The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

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Fig. 2 : Waveform showing write operation

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The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

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Sample behavioral waveforms for design file lpm_compare1.vhd

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The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator.

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-

Fig. 1 : Wave showing comparator operation.

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Sample behavioral waveforms for design file "lpm_fifoDZ.vhd"

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The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 128 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

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-

Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions with aclr .

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Sample behavioral waveforms for design file lpm_fifo_dc0.vhd

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The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design lpm_fifo_dc0.vhd. The design lpm_fifo_dc0.vhd has a depth of 512 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

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Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions with aclr .

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-- Entity Declaration -ENTITY BLITTER IS +ENTITY blitter IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( @@ -61,7 +61,7 @@ END BLITTER; -- Architecture Body -ARCHITECTURE BLITTER_architecture OF BLITTER IS +ARCHITECTURE BLITTER_architecture OF blitter IS BEGIN diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index d5b5ec2..b100fe6 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -225,15 +225,16 @@ BEGIN DDR_CS.CLK = MAIN_CLK; DDR_CS.ENA = FB_ALE; DDR_CS = DDR_SEL; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP�TER CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS - # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP�TER CPU_REQ.CLK = DDR_SYNC_66M; CPU_REQ = CPU_SIG # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG BUS_CYC.CLK = DDRCLK0; BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- MCS[].CLK = DDRCLK0; MCS0 = MAIN_CLK; @@ -341,7 +342,7 @@ BEGIN CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; VCAS = VCC; - SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_DDR_FB = CPU_AC; -- READ DATEN F�R CPU SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN DDR_SM = DS_T5R; @@ -383,7 +384,7 @@ BEGIN VCAS = VCC; VWE = VCC; SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL = VCC; -- 2. H�LFTE WRITE DATEN SELEKTIEREN SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV DDR_SM = DS_T7W; @@ -391,7 +392,7 @@ BEGIN CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL = VCC; -- 2. H�LFTE WRITE DATEN SELEKTIEREN DDR_SM = DS_T8W; WHEN DS_T8W => @@ -523,12 +524,12 @@ BEGIN -- CLOSE FIFO BANK WHEN DS_CB6 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN + VRAS = VCC; -- B�NKE SCHLIESSEN VWE = VCC; DDR_SM = DS_N7; WHEN DS_CB8 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN + VRAS = VCC; -- B�NKE SCHLIESSEN VWE = VCC; DDR_SM = DS_T1; -- REFRESH 70NS = 10 ZYCLEN @@ -584,14 +585,14 @@ BEGIN FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00"); FIFO_BANK_OK.CLK = DDRCLK0; FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK; - -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + -- Z�HLER R�CKSETZEN WENN CLR FIFO ---------------- CLR_FIFO_SYNC.CLK =DDRCLK0; CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN CLEAR_FIFO_CNT.CLK = DDRCLK0; CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE; STOP.CLK = DDRCLK0; STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT; - -- ZÄHLEN ----------------------------------------------- + -- Z�HLEN ----------------------------------------------- VIDEO_ADR_CNT[].CLK = DDRCLK0; VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT; VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] @@ -608,12 +609,12 @@ BEGIN -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS ----------------------------------------------------------------------------------------- DDR_REFRESH_CNT[].CLK = CLK33M; - DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z�HLEN 0-2047 REFRESH_TIME.CLK = DDRCLK0; REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC DDR_REFRESH_SIG[].CLK = DDRCLK0; DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; - DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST�CK (8 REFRESH UND 1 ALS VORLAUF) # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT DDR_REFRESH_REQ.CLK = DDRCLK0; DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 2b777db..eafe6c2 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -8,7 +8,7 @@ INCLUDE "lpm_bustri_BYT.inc"; -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -SUBDESIGN VIDEO_MOD_MUX_CLUTCTR +SUBDESIGN video_mod_mux_clutctr ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! nRSTO : INPUT; diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index b3c16e6..d945879 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -57,23 +57,6 @@ applicable agreement for further details. (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) (annotation_block (location)(rect 944 952 1000 968)) ) -(pin - (input) - (rect 168 296 336 312) - (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) - (text "CLK33M" (rect 9 0 53 11)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 168 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 104 312 176 328)) -) (pin (input) (rect 992 960 1160 976) @@ -856,23 +839,6 @@ applicable agreement for further details. (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) (annotation_block (location)(rect 808 1632 872 1648)) ) -(pin - (input) - (rect 96 -288 264 -272) - (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) - (text "MAIN_CLK" (rect 9 0 66 11)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 168 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 56 -304 120 -288)) -) (pin (input) (rect 664 440 840 456) @@ -890,6 +856,23 @@ applicable agreement for further details. (text "VCC" (rect 144 7 165 17)(font "Arial" (font_size 6))) (annotation_block (location)(rect 600 448 664 464)) ) +(pin + (input) + (rect 168 296 336 312) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "MAIN_CLK" (rect 5 0 63 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 104 312 176 328)) +) (pin (output) (rect 864 288 1040 304) @@ -4379,11 +4362,6 @@ applicable agreement for further details. (pt 1152 800) (pt 1264 800) ) -(connector - (text "CLK33M" (rect 1210 760 1254 771)(font "Arial" )) - (pt 1200 776) - (pt 1264 776) -) (connector (text "CLK2M" (rect 1202 808 1240 819)(font "Arial" )) (pt 1192 824) @@ -5042,11 +5020,6 @@ applicable agreement for further details. (pt 776 1496) (pt 1264 1496) ) -(connector - (text "CLK33M" (rect 346 288 390 299)(font "Arial" )) - (pt 336 304) - (pt 400 304) -) (connector (text "CLK25M" (rect 1202 608 1246 619)(font "Arial" )) (pt 1192 624) @@ -5662,11 +5635,6 @@ applicable agreement for further details. (pt 984 568) (pt 1264 568) ) -(connector - (text "CLK33M" (rect 1202 584 1246 595)(font "Arial" )) - (pt 1264 600) - (pt 1192 600) -) (connector (text "CLK500k" (rect 802 232 849 243)(font "Arial" )) (pt 768 248) @@ -5734,11 +5702,6 @@ applicable agreement for further details. (pt 1152 3024) (pt 1264 3024) ) -(connector - (text "CLK33M" (rect 1210 2984 1254 2995)(font "Arial" )) - (pt 1200 3000) - (pt 1264 3000) -) (connector (text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" )) (pt 1264 3072) @@ -5831,6 +5794,26 @@ applicable agreement for further details. (pt 1264 3144) (pt 1160 3144) ) +(connector + (text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" )) + (pt 336 304) + (pt 400 304) +) +(connector + (text "MAIN_CLK" (rect 1202 584 1259 595)(font "Arial" )) + (pt 1264 600) + (pt 1192 600) +) +(connector + (text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" )) + (pt 1200 776) + (pt 1264 776) +) +(connector + (text "MAIN_CLK" (rect 1210 2984 1267 2995)(font "Arial" )) + (pt 1200 3000) + (pt 1264 3000) +) (junction (pt 2504 760)) (junction (pt 400 248)) (junction (pt 1856 -64)) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 4560656..dde4b54 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -19,7 +19,7 @@ ## PROGRAM "Quartus II" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" -## DATE "Sun Sep 20 08:38:08 2015" +## DATE "Sun Sep 20 10:41:57 2015" ## ## DEVICE "EP3C40F484C6" @@ -38,37 +38,14 @@ set_time_format -unit ns -decimal_places 3 # Create Clock #************************************************************** -create_clock -name {CLK33M} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK33M}] create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] -create_clock -name {E0_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {E0_INT}] -create_clock -name {nPCI_INTB} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTB}] -create_clock -name {nPCI_INTA} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTA}] -create_clock -name {DVI_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {DVI_INT}] -create_clock -name {nPCI_INTC} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTC}] -create_clock -name {nPCI_INTD} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTD}] -create_clock -name {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC} -period 1.000 -waveform { 0.000 0.500 } [get_registers {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -create_clock -name {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC} -period 1.000 -waveform { 0.000 0.500 } [get_registers {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -create_clock -name {PIC_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {PIC_INT}] #************************************************************** # Create Generated Clock #************************************************************** -create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 66 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[0]}] -create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 67 -divide_by 900 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[1]}] -create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 67 -divide_by 90 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[2]}] -create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 1800 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[0]}] -create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 225 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[1]}] -create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 144 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[2]}] -create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 75 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[3]}] -create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 240.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[0]}] -create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[1]}] -create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 180.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[2]}] -create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 105.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[3]}] -create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -phase 270.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[4]}] -create_generated_clock -name {inst22|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst22|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {inst13|altpll_component|auto_generated|pll1|clk[3]} [get_pins {inst22|altpll_component|auto_generated|pll1|clk[0]}] - +derive_pll_clocks #************************************************************** # Set Clock Latency @@ -80,382 +57,8 @@ create_generated_clock -name {inst22|altpll_component|auto_generated|pll1|clk[0] # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.110 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.110 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.110 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.110 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {PIC_INT}] -rise_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {PIC_INT}] -fall_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {PIC_INT}] -rise_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {PIC_INT}] -fall_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.140 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.140 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -setup 0.130 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -setup 0.130 -set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.140 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.140 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -setup 0.130 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -setup 0.130 -set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {PIC_INT}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {PIC_INT}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTD}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTD}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTC}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTC}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {DVI_INT}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {DVI_INT}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTA}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTA}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTB}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTB}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {E0_INT}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {E0_INT}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {CLK33M}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {CLK33M}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {PIC_INT}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {PIC_INT}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTD}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTD}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTC}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTC}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {DVI_INT}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {DVI_INT}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTA}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTA}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTB}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTB}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {E0_INT}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {E0_INT}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {CLK33M}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {CLK33M}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -hold 0.060 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -hold 0.060 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {MAIN_CLK}] 0.030 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {CLK33M}] 0.020 -set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.050 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.050 #************************************************************** @@ -480,7 +83,6 @@ set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK # Set False Path #************************************************************** -set_false_path -from [get_clocks {CLK33M}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] @@ -492,6 +94,7 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip # Set Multicycle Path #************************************************************** +set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2 #************************************************************** From 6288a1e16b532693773eae902bbd203fbf8db546 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 14:54:16 +0000 Subject: [PATCH 014/127] reformatted. --- .../FalconIO_SDCard_IDE_CF.vhd | 1160 +++++++++-------- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 207 ++- FPGA_Quartus_13.1/Video/Video.bdf | 580 +++++---- FPGA_Quartus_13.1/firebee1.bdf | 64 +- FPGA_Quartus_13.1/firebee1.sdc | 9 +- 5 files changed, 1104 insertions(+), 916 deletions(-) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index b2b8dbb..f0c67ac 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -1,5 +1,5 @@ -- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in +-- editor IF you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2008 Altera Corporation @@ -33,333 +33,333 @@ use ieee.std_logic_unsigned.all; -- Entity Declaration -ENTITY FalconIO_SDCard_IDE_CF IS +ENTITY falconio_sdcard_ide_cf IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - CLK2M : IN STD_LOGIC; - CLK500k : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - LP_BUSY : IN STD_LOGIC; - nACSI_DRQ : IN STD_LOGIC; - nACSI_INT : IN STD_LOGIC; - nSCSI_DRQ : IN STD_LOGIC; - nSCSI_MSG : IN STD_LOGIC; - MIDI_IN : IN STD_LOGIC; - RxD : IN STD_LOGIC; - CTS : IN STD_LOGIC; - RI : IN STD_LOGIC; - DCD : IN STD_LOGIC; - AMKB_RX : IN STD_LOGIC; - PIC_AMKB_RX : IN STD_LOGIC; - IDE_RDY : IN STD_LOGIC; - IDE_INT : IN STD_LOGIC; - WP_CS_CARD : IN STD_LOGIC; - nINDEX : IN STD_LOGIC; - TRACK00 : IN STD_LOGIC; - nRD_DATA : IN STD_LOGIC; - nDCHG : IN STD_LOGIC; - SD_DATA0 : IN STD_LOGIC; - SD_DATA1 : IN STD_LOGIC; - SD_DATA2 : IN STD_LOGIC; - SD_CARD_DEDECT : IN STD_LOGIC; - SD_WP : IN STD_LOGIC; - nDACK0 : IN STD_LOGIC; - nFB_WR : INOUT STD_LOGIC; - WP_CF_CARD : IN STD_LOGIC; - nWP : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - HD_DD : IN STD_LOGIC; - nSCSI_C_D : IN STD_LOGIC; - nSCSI_I_O : IN STD_LOGIC; - CLK2M4576 : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - VSYNC : IN STD_LOGIC; - HSYNC : IN STD_LOGIC; - DSP_INT : IN STD_LOGIC; - nBLANK : IN STD_LOGIC; - FDC_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); - nIDE_CS1 : OUT STD_LOGIC; - nIDE_CS0 : OUT STD_LOGIC; - LP_STR : OUT STD_LOGIC; - LP_DIR : OUT STD_LOGIC; - nACSI_ACK : OUT STD_LOGIC; - nACSI_RESET : OUT STD_LOGIC; - nACSI_CS : OUT STD_LOGIC; - ACSI_DIR : OUT STD_LOGIC; - ACSI_A1 : OUT STD_LOGIC; - nSCSI_ACK : OUT STD_LOGIC; - nSCSI_ATN : OUT STD_LOGIC; - SCSI_DIR : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - YM_QA : OUT STD_LOGIC; - YM_QC : OUT STD_LOGIC; - YM_QB : OUT STD_LOGIC; - nSDSEL : OUT STD_LOGIC; - STEP : OUT STD_LOGIC; - MOT_ON : OUT STD_LOGIC; - nRP_LDS : OUT STD_LOGIC; - nRP_UDS : OUT STD_LOGIC; - nROM4 : OUT STD_LOGIC; - nROM3 : OUT STD_LOGIC; - nCF_CS1 : OUT STD_LOGIC; - nCF_CS0 : OUT STD_LOGIC; - nIDE_RD : INOUT STD_LOGIC; - nIDE_WR : INOUT STD_LOGIC; - AMKB_TX : OUT STD_LOGIC; - IDE_RES : OUT STD_LOGIC; - DTR : OUT STD_LOGIC; - RTS : OUT STD_LOGIC; - TxD : OUT STD_LOGIC; - MIDI_OLR : OUT STD_LOGIC; - MIDI_TLR : OUT STD_LOGIC; - nDREQ0 : OUT STD_LOGIC; - DSA_D : OUT STD_LOGIC; - nMFP_INT : OUT STD_LOGIC; - FALCON_IO_TA : OUT STD_LOGIC; - STEP_DIR : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC; - WR_GATE : OUT STD_LOGIC; - DMA_DRQ : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_PAR : INOUT STD_LOGIC; - nSCSI_SEL : INOUT STD_LOGIC; - nSCSI_BUSY : INOUT STD_LOGIC; - nSCSI_RST : INOUT STD_LOGIC; - SD_CD_DATA3 : INOUT STD_LOGIC; - SD_CDM_D1 : INOUT STD_LOGIC + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + CLK2M : IN std_logic; + CLK500k : IN std_logic; + nFB_CS1 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + nSCSI_DRQ : IN std_logic; + nSCSI_MSG : IN std_logic; + MIDI_IN : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CS_CARD : IN std_logic; + nINDEX : IN std_logic; + TRACK00 : IN std_logic; + nRD_DATA : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + SD_WP : IN std_logic; + nDACK0 : IN std_logic; + nFB_WR : INOUT std_logic; + WP_CF_CARD : IN std_logic; + nWP : IN std_logic; + nFB_CS2 : IN std_logic; + nRSTO : IN std_logic; + HD_DD : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + CLK2M4576 : IN std_logic; + nFB_OE : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DSP_INT : IN std_logic; + nBLANK : IN std_logic; + FDC_CLK : IN std_logic; + FB_ALE : IN std_logic; + ACP_CONF : IN std_logic_vector(31 DOWNTO 24); + nIDE_CS1 : OUT std_logic; + nIDE_CS0 : OUT std_logic; + LP_STR : OUT std_logic; + LP_DIR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + SD_CLK : OUT std_logic; + YM_QA : OUT std_logic; + YM_QC : OUT std_logic; + YM_QB : OUT std_logic; + nSDSEL : OUT std_logic; + STEP : OUT std_logic; + MOT_ON : OUT std_logic; + nRP_LDS : OUT std_logic; + nRP_UDS : OUT std_logic; + nROM4 : OUT std_logic; + nROM3 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nCF_CS0 : OUT std_logic; + nIDE_RD : INOUT std_logic; + nIDE_WR : INOUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + DTR : OUT std_logic; + RTS : OUT std_logic; + TxD : OUT std_logic; + MIDI_OLR : OUT std_logic; + MIDI_TLR : OUT std_logic; + nDREQ0 : OUT std_logic; + DSA_D : OUT std_logic; + nMFP_INT : OUT std_logic; + FALCON_IO_TA : OUT std_logic; + STEP_DIR : OUT std_logic; + WR_DATA : OUT std_logic; + WR_GATE : OUT std_logic; + DMA_DRQ : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_PAR : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CDM_D1 : INOUT std_logic ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -END FalconIO_SDCard_IDE_CF; +END falconio_sdcard_ide_cf; -- Architecture Body -ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS --- system -signal SYS_CLK : STD_LOGIC; -signal RESETn : STD_LOGIC; -signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS -signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS -signal BYT : STD_LOGIC; -- WENN BYT -> 1 -signal LONG : STD_LOGIC; -- WENN -> 1 --- KEYBOARD MIDI -signal ACIA_CS_I : STD_LOGIC; -signal IRQ_KEYBDn : STD_LOGIC; -signal IRQ_MIDIn : STD_LOGIC; -signal KEYB_RxD : STD_LOGIC; -signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); -signal MIDI_OUT : STD_LOGIC; -signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); -signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); --- MFP -signal MFP_CS : STD_LOGIC; -signal MFP_INTACK : STD_LOGIC; -signal LDS : STD_LOGIC; -signal DTACK_OUT_MFPn : STD_LOGIC; -signal IRQ_ACIAn : STD_LOGIC; -signal DINTn : STD_LOGIC; -signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); -signal TDO : STD_LOGIC; --- SOUND -signal SNDCS : STD_LOGIC; -signal SNDCS_I : STD_LOGIC; -signal SNDIR_I : STD_LOGIC; -signal LP_DIR_X : STD_LOGIC; -signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); -signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); --- DIV -signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE -signal ROM_CS : STD_LOGIC; --- DMA UND FLOPPY -signal DMA_DATEN_CS : STD_LOGIC; -signal DMA_MODUS_CS : STD_LOGIC; -signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); -signal WDC_BSL_CS : STD_LOGIC; -signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); -signal HD_DD_OUT : STD_LOGIC; -signal FDCS_In : STD_LOGIC; -signal CA0 : STD_LOGIC; -signal CA1 : STD_LOGIC; -signal CA2 : STD_LOGIC; -signal FDINT : STD_LOGIC; -signal FDRQ : STD_LOGIC; -signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_TOP_CS : STD_LOGIC; -signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_HIGH_CS : STD_LOGIC; -signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_MID_CS : STD_LOGIC; -signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_LOW_CS : STD_LOGIC; -signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_DIRM_CS : STD_LOGIC; -signal DMA_ADR_CS : STD_LOGIC; -signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); -signal DMA_DIR_OLD : STD_LOGIC; -signal DMA_BYT_CNT_CS : STD_LOGIC; -signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); -signal CLR_FIFO : STD_LOGIC; -signal DMA_DRQ_I : STD_LOGIC; -signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); -signal DMA_DRQQ : STD_LOGIC; -signal DMA_DRQ_Q : STD_LOGIC; -signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); -signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal RDF_RDE : STD_LOGIC; -signal RDF_WRE : STD_LOGIC; -signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal WRF_RDE : STD_LOGIC; -signal WRF_WRE : STD_LOGIC; -signal nFDC_WR : STD_LOGIC; -type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); -signal FCF_STATE : FCF_STATES; -signal NEXT_FCF_STATE : FCF_STATES; -signal DMA_REQ : STD_LOGIC; -signal FDC_CS : STD_LOGIC; -signal FCF_CS : STD_LOGIC; -signal FCF_APH : STD_LOGIC; -signal DMA_AZ_CS : STD_LOGIC; -signal DMA_ACTIV : STD_LOGIC; -signal DMA_ACTIV_NEW : STD_LOGIC; -signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); --- SCSI -signal SCSI_CS : STD_LOGIC; -signal SCSI_CSn : STD_LOGIC; -signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal nSCSI_DACK : STD_LOGIC; -signal SCSI_DRQ : STD_LOGIC; -signal SCSI_INT : STD_LOGIC; -signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); -signal DB_EN : STD_LOGIC; -signal DBP_OUTn : STD_LOGIC; -signal DBP_EN : STD_LOGIC; -signal RST_OUTn : STD_LOGIC; -signal RST_EN : STD_LOGIC; -signal BSY_OUTn : STD_LOGIC; -signal BSY_EN : STD_LOGIC; -signal SEL_OUTn : STD_LOGIC; -signal SEL_EN : STD_LOGIC; --- IDE -signal nnIDE_RES : STD_LOGIC; -signal IDE_CF_CS : STD_LOGIC; -signal IDE_CF_TA : STD_LOGIC; -signal NEXT_nIDE_RD : STD_LOGIC; -signal NEXT_nIDE_WR : STD_LOGIC; -type CMD_STATES is( IDLE, T1, T6, T7); -signal CMD_STATE : CMD_STATES; -signal NEXT_CMD_STATE : CMD_STATES; - - + ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS + -- system + SIGNAL SYS_CLK : std_logic; + SIGNAL RESETn : std_logic; + SIGNAL FB_B0 : std_logic; -- UPPER BYT BEI 16BIT BUS + SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS + SIGNAL BYT : std_logic; -- WENN BYT -> 1 + SIGNAL LONG : std_logic; -- WENN -> 1 + -- KEYBOARD MIDI + SIGNAL ACIA_CS_I : std_logic; + SIGNAL IRQ_KEYBDn : std_logic; + SIGNAL IRQ_MIDIn : std_logic; + SIGNAL KEYB_RxD : std_logic; + SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); + SIGNAL MIDI_OUT : std_logic; + SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); + SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); + -- MFP + SIGNAL MFP_CS : std_logic; + SIGNAL MFP_INTACK : std_logic; + SIGNAL LDS : std_logic; + SIGNAL DTACK_OUT_MFPn : std_logic; + SIGNAL IRQ_ACIAn : std_logic; + SIGNAL DINTn : std_logic; + SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0); + SIGNAL TDO : std_logic; + -- SOUND + SIGNAL SNDCS : std_logic; + SIGNAL SNDCS_I : std_logic; + SIGNAL SNDIR_I : std_logic; + SIGNAL LP_DIR_X : std_logic; + SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0); + SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0); + -- DIV + SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE + SIGNAL ROM_CS : std_logic; + -- DMA UND FLOPPY + SIGNAL DMA_DATEN_CS : std_logic; + SIGNAL DMA_MODUS_CS : std_logic; + SIGNAL DMA_MODUS : std_logic_vector(15 DOWNTO 0); + SIGNAL WDC_BSL_CS : std_logic; + SIGNAL WDC_BSL : std_logic_vector(1 DOWNTO 0); + SIGNAL HD_DD_OUT : std_logic; + SIGNAL FDCS_In : std_logic; + SIGNAL CA0 : std_logic; + SIGNAL CA1 : std_logic; + SIGNAL CA2 : std_logic; + SIGNAL FDINT : std_logic; + SIGNAL FDRQ : std_logic; + SIGNAL CD_OUT_FDC : std_logic_vector(7 DOWNTO 0); + SIGNAL CD_IN_FDC : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_TOP_CS : std_logic; + SIGNAL DMA_TOP : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_HIGH_CS : std_logic; + SIGNAL DMA_HIGH : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_MID_CS : std_logic; + SIGNAL DMA_MID : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_LOW_CS : std_logic; + SIGNAL DMA_LOW : std_logic_vector(7 DOWNTO 0); + SIGNAL DMA_DIRM_CS : std_logic; + SIGNAL DMA_ADR_CS : std_logic; + SIGNAL DMA_STATUS : std_logic_vector(2 DOWNTO 0); + SIGNAL DMA_DIR_OLD : std_logic; + SIGNAL DMA_BYT_CNT_CS : std_logic; + SIGNAL DMA_BYT_CNT : std_logic_vector(31 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL DMA_DRQ_I : std_logic; + SIGNAL DMA_DRQ_REG : std_logic_vector(1 DOWNTO 0); + SIGNAL DMA_DRQQ : std_logic; + SIGNAL DMA_DRQ_Q : std_logic; + SIGNAL RDF_DOUT : std_logic_vector(31 DOWNTO 0); + SIGNAL RDF_AZ : std_logic_vector(9 DOWNTO 0); + SIGNAL RDF_RDE : std_logic; + SIGNAL RDF_WRE : std_logic; + SIGNAL RDF_DIN : std_logic_vector(7 DOWNTO 0); + SIGNAL WRF_DOUT : std_logic_vector(7 DOWNTO 0); + SIGNAL WRF_AZ : std_logic_vector(9 DOWNTO 0); + SIGNAL WRF_RDE : std_logic; + SIGNAL WRF_WRE : std_logic; + SIGNAL nFDC_WR : std_logic; + type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); + SIGNAL FCF_STATE : FCF_STATES; + SIGNAL NEXT_FCF_STATE : FCF_STATES; + SIGNAL DMA_REQ : std_logic; + SIGNAL FDC_CS : std_logic; + SIGNAL FCF_CS : std_logic; + SIGNAL FCF_APH : std_logic; + SIGNAL DMA_AZ_CS : std_logic; + SIGNAL DMA_ACTIV : std_logic; + SIGNAL DMA_ACTIV_NEW : std_logic; + SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0); + -- SCSI + SIGNAL SCSI_CS : std_logic; + SIGNAL SCSI_CSn : std_logic; + SIGNAL SCSI_DOUT : std_logic_vector(7 DOWNTO 0); + SIGNAL nSCSI_DACK : std_logic; + SIGNAL SCSI_DRQ : std_logic; + SIGNAL SCSI_INT : std_logic; + SIGNAL DB_OUTn : std_logic_vector(7 DOWNTO 0); + SIGNAL DB_EN : std_logic; + SIGNAL DBP_OUTn : std_logic; + SIGNAL DBP_EN : std_logic; + SIGNAL RST_OUTn : std_logic; + SIGNAL RST_EN : std_logic; + SIGNAL BSY_OUTn : std_logic; + SIGNAL BSY_EN : std_logic; + SIGNAL SEL_OUTn : std_logic; + SIGNAL SEL_EN : std_logic; + -- IDE + SIGNAL nnIDE_RES : std_logic; + SIGNAL IDE_CF_CS : std_logic; + SIGNAL IDE_CF_TA : std_logic; + SIGNAL NEXT_nIDE_RD : std_logic; + SIGNAL NEXT_nIDE_WR : std_logic; + type CMD_STATES is( IDLE, T1, T6, T7); + SIGNAL CMD_STATE : CMD_STATES; + SIGNAL NEXT_CMD_STATE : CMD_STATES; + + BEGIN -LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; -BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; -FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; -FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; - -FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' - or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; -SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE - '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE - '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; -nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; -nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; -nDREQ0 <= '0'; ----------------------------------------------------------------------------- --- SD ----------------------------------------------------------------------------- -SD_CLK <= 'Z'; -SD_CD_DATA3 <= 'Z'; -SD_CDM_D1 <= 'Z'; ----------------------------------------------------------------------------- --- IDE ----------------------------------------------------------------------------- -CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) - begin - if nRSTO = '0' then + LONG <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '0' ELSE '0'; + BYT <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '1' ELSE '0'; + FB_B0 <= '1' WHEN FB_ADR(0) = '0' or BYT = '0' ELSE '0'; + FB_B1 <= '1' WHEN FB_ADR(0) = '1' or BYT = '0' ELSE '0'; + + FALCON_IO_TA <= '1' WHEN SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' ELSE '0'; + SUB_BUS <= '1' WHEN nFB_WR = '1' and ROM_CS = '1' ELSE + '1' WHEN nFB_WR = '1' and IDE_CF_CS = '1' ELSE + '1' WHEN nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; + nRP_UDS <= '0' WHEN SUB_BUS = '1' and FB_B0 = '1' ELSE '1'; + nRP_LDS <= '0' WHEN SUB_BUS = '1' and FB_B1 = '1' ELSE '1'; + nDREQ0 <= '0'; + ---------------------------------------------------------------------------- + -- SD + ---------------------------------------------------------------------------- + SD_CLK <= 'Z'; + SD_CD_DATA3 <= 'Z'; + SD_CDM_D1 <= 'Z'; + ---------------------------------------------------------------------------- + -- IDE + ---------------------------------------------------------------------------- + CMD_REG: PROCESS(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) + BEGIN + IF nRSTO = '0' THEN CMD_STATE <= IDLE; - elsif rising_edge(MAIN_CLK) then + ELSIF rising_edge(MAIN_CLK) THEN CMD_STATE <= NEXT_CMD_STATE; -- go to next nIDE_RD <= NEXT_nIDE_RD; -- go to next nIDE_WR <= NEXT_nIDE_WR; -- go to next - else + ELSE CMD_STATE <= CMD_STATE; -- halten nIDE_RD <= nIDE_RD; -- halten nIDE_WR <= nIDE_WR; -- halten - end if; - end process CMD_REG; + END IF; + END PROCESS CMD_REG; - CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) - begin + CMD_DECODER: PROCESS(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) + BEGIN case CMD_STATE is - when IDLE => + WHEN IDLE => IDE_CF_TA <= '0'; - if IDE_CF_CS = '1' then + IF IDE_CF_CS = '1' THEN NEXT_nIDE_RD <= not nFB_WR; NEXT_nIDE_WR <= nFB_WR; NEXT_CMD_STATE <= T1; - else + ELSE NEXT_nIDE_RD <= '1'; NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= IDLE; - end if; - when T1 => + END IF; + WHEN T1 => IDE_CF_TA <= '0'; NEXT_nIDE_RD <= not nFB_WR; NEXT_nIDE_WR <= nFB_WR; NEXT_CMD_STATE <= T6; - when T6 => - IF IDE_RDY = '1' then + WHEN T6 => + IF IDE_RDY = '1' THEN IDE_CF_TA <= '1'; NEXT_nIDE_RD <= '1'; NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= T7; - else + ELSE IDE_CF_TA <= '0'; NEXT_nIDE_RD <= not nFB_WR; NEXT_nIDE_WR <= nFB_WR; NEXT_CMD_STATE <= T6; - end if; - when T7 => + END IF; + WHEN T7 => IDE_CF_TA <= '0'; NEXT_nIDE_RD <= '1'; NEXT_nIDE_WR <= '1'; NEXT_CMD_STATE <= IDLE; - end case; - end process CMD_DECODER; + END CASE; + END PROCESS CMD_DECODER; -IDE_RES <= not nnIDE_RES and nRSTO; -IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 -nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F -nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F -nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F -nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F ------------------------------------------------------------------------------------------------------------------------------------------ --- ACSI, SCSI UND FLOPPY WD1772 -------------------------------------------------------------------------------------------------------------------------------------------- --- daten read fifo + IDE_RES <= not nnIDE_RES and nRSTO; + IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 + nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F + '0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F + nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F + '0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F + nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F + '0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F + nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F + '0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F + ----------------------------------------------------------------------------------------------------------------------------------------- + -- ACSI, SCSI UND FLOPPY WD1772 + ------------------------------------------------------------------------------------------------------------------------------------------- + -- daten read fifo RDF: dcfifo0 - port map( + PORT MAP( aclr => CLR_FIFO, data => RDF_DIN, rdclk => MAIN_CLK, @@ -369,16 +369,16 @@ nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else q => RDF_DOUT, wrusedw => RDF_AZ ); -FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY -FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY -RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE -FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; --- daten write fifo + FCF_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"0020110" and LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY + FCF_APH <= '1' WHEN FB_ALE = '1' and FB_AD(31 DOWNTO 0) = x"F0020110" and LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY + RDF_RDE <= '1' WHEN FCF_APH = '1' and nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE + FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; + -- daten write fifo WRF: dcfifo1 - port map( + PORT MAP( aclr => CLR_FIFO, - data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), + data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), rdclk => FDC_CLK, rdreq => WRF_RDE, wrclk => MAIN_CLK, @@ -386,84 +386,86 @@ RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; q => WRF_DOUT, rdusedw => WRF_AZ ); -CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB -DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG -FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) - begin - if nRSTO = '0' THEN + + CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB + DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG + FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; + + -- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + BEGIN + IF nRSTO = '0' THEN WRF_WRE <= '0'; - elsif rising_edge(MAIN_CLK) then - IF FCF_APH = '1' and nFB_WR = '0' then - WRF_WRE <= '1'; - else - WRF_WRE <= '0'; - end if; - else - WRF_WRE <= WRF_WRE; - end if; + ELSIF rising_edge(MAIN_CLK) THEN + IF FCF_APH = '1' and nFB_WR = '0' THEN + WRF_WRE <= '1'; + ELSE + WRF_WRE <= '0'; + END IF; + ELSE + WRF_WRE <= WRF_WRE; + END IF; END PROCESS; -FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) - begin - if nRSTO = '0' then + FCF_REG: PROCESS(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) + BEGIN + IF nRSTO = '0' THEN FCF_STATE <= FCF_IDLE; DMA_ACTIV <= '0'; - elsif rising_edge(FDC_CLK) then - FCF_STATE <= NEXT_FCF_STATE; -- go to next - DMA_ACTIV <= DMA_ACTIV_NEW; - else - FCF_STATE <= FCF_STATE; -- halten - DMA_ACTIV <= DMA_ACTIV; - end if; - end process FCF_REG; + ELSIF rising_edge(FDC_CLK) THEN + FCF_STATE <= NEXT_FCF_STATE; -- go to next + DMA_ACTIV <= DMA_ACTIV_NEW; + ELSE + FCF_STATE <= FCF_STATE; -- halten + DMA_ACTIV <= DMA_ACTIV; + END IF; + END PROCESS FCF_REG; -FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) - begin - if nRSTO = '0' then + FDC_REG: PROCESS(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) + BEGIN + IF nRSTO = '0' THEN FDC_OUT <= x"00"; - elsif rising_edge(FDC_CLK) and FDCS_In = '0' then - FDC_OUT <= CD_OUT_FDC; -- set - else - FDC_OUT <= FDC_OUT; -- halten - end if; - end process FDC_REG; + ELSIF rising_edge(FDC_CLK) and FDCS_In = '0' THEN + FDC_OUT <= CD_OUT_FDC; -- set + ELSE + FDC_OUT <= FDC_OUT; -- halten + END IF; + END PROCESS FDC_REG; -DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; -FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; -SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; + DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' ELSE '0'; + FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and FB_B1 = '1' ELSE '0'; + SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and FB_B1 = '1' ELSE '0'; - FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) - begin + FCF_DECODER: PROCESS(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) + BEGIN case FCF_STATE is - when FCF_IDLE => + WHEN FCF_IDLE => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; nSCSI_DACK <= '1'; - if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then + IF DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' THEN DMA_ACTIV_NEW <= DMA_REQ; NEXT_FCF_STATE <= FCF_T0; - else + ELSE DMA_ACTIV_NEW <= '0'; NEXT_FCF_STATE <= FCF_IDLE; - end if; - when FCF_T0 => + END IF; + WHEN FCF_T0 => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; nSCSI_DACK <= '1'; DMA_ACTIV_NEW <= DMA_REQ; WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO - if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + IF DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start - else + ELSE NEXT_FCF_STATE <= FCF_T1; - end if; - when FCF_T1 => + END IF; + WHEN FCF_T1 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; @@ -471,7 +473,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; NEXT_FCF_STATE <= FCF_T2; - when FCF_T2 => + WHEN FCF_T2 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; @@ -479,7 +481,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; NEXT_FCF_STATE <= FCF_T3; - when FCF_T3 => + WHEN FCF_T3 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; @@ -487,7 +489,7 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; NEXT_FCF_STATE <= FCF_T6; - when FCF_T6 => + WHEN FCF_T6 => WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; SCSI_CSn <= not SCSI_CS; @@ -495,23 +497,23 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO NEXT_FCF_STATE <= FCF_T7; - when FCF_T7 => + WHEN FCF_T7 => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; nSCSI_DACK <= '1'; DMA_ACTIV_NEW <= '0'; - if FDC_CS = '1' and DMA_REQ = '0' then + IF FDC_CS = '1' and DMA_REQ = '0' THEN NEXT_FCF_STATE <= FCF_T7; - else + ELSE NEXT_FCF_STATE <= FCF_IDLE; - end if; - end case; - end process FCF_DECODER; + END IF; + END CASE; + END PROCESS FCF_DECODER; I_FDC: WF1772IP_TOP_SOC - port map( + PORT MAP( CLK => FDC_CLK, RESETn => nRSTO, CSn => FDCS_In, @@ -535,165 +537,187 @@ SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_ DRQ => DMA_DRQ_I, INTRQ => FDINT ); -DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 -DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 -WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 -HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); -nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; -CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); -CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); -CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); -FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else - SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else - DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ---- WDC BSL REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN + + DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 + DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 + WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 + + HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); + nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR; + + CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0); + CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); + CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); + + FB_AD(23 DOWNTO 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and nFB_OE = '0' ELSE + SCSI_DOUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and nFB_OE = '0' ELSE + DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + + --- WDC BSL REGISTER ------------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) + BEGIN + IF nRSTO = '0' THEN WDC_BSL <= "00"; - elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then + ELSIF rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' THEN IF FB_B0 = '1' THEN WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); - else + ELSE WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); - end if; - end if; + END IF; + END IF; END PROCESS; + --- DMA MODUS REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN + PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) + BEGIN + IF nRSTO = '0' THEN DMA_MODUS <= x"0000"; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then + ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' THEN IF FB_B0 = '1' THEN - DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); - else - DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); - end if; + DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24); + ELSE + DMA_MODUS(15 DOWNTO 8) <= DMA_MODUS(15 DOWNTO 8); + END IF; IF FB_B1 = '1' THEN - DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); - else - DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); - end if; - else + DMA_MODUS(7 DOWNTO 0) <= FB_AD(23 DOWNTO 16); + ELSE + DMA_MODUS(7 DOWNTO 0) <= DMA_MODUS(7 DOWNTO 0); + END IF; + ELSE DMA_MODUS <= DMA_MODUS; - end if; + END IF; END PROCESS; --- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) - begin - if nRSTO = '0' or CLR_FIFO = '1' THEN + + -- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- + PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) + BEGIN + IF nRSTO = '0' or CLR_FIFO = '1' THEN DMA_BYT_CNT <= x"00000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then - DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); - DMA_BYT_CNT(8 downto 0) <= "000000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then - DMA_BYT_CNT <= FB_AD; - else - DMA_BYT_CNT <= DMA_BYT_CNT; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' THEN + DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z'); + DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); + DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z'); + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' THEN + DMA_BYT_CNT <= FB_AD; + ELSE + DMA_BYT_CNT <= DMA_BYT_CNT; + END IF; END PROCESS; --------------------------------------------------------------------- -FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -DMA_STATUS(0) <= '1'; -- DMA OK -DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS -DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; -DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else - '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; -DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ - process(FDC_CLK, nRSTO, DMA_DRQ_REG) - begin - if nRSTO = '0' THEN + -------------------------------------------------------------------- + FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + DMA_STATUS(0) <= '1'; -- DMA OK + DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS + DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' or SCSI_DRQ = '1' ELSE '0'; + DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' ELSE + '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' ELSE '0'; + DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; + + -- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG) + BEGIN + IF nRSTO = '0' THEN DMA_DRQ_REG <= "00"; - elsif rising_edge(FDC_CLK) then - DMA_DRQ_REG(0) <= DMA_DRQQ; - DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; - else - DMA_DRQ_REG <= DMA_DRQ_REG; - end if; + ELSIF rising_edge(FDC_CLK) THEN + DMA_DRQ_REG(0) <= DMA_DRQQ; + DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; + ELSE + DMA_DRQ_REG <= DMA_DRQ_REG; + END IF; END PROCESS; --- DMA ADRESSE ------------------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN + + -- DMA ADRESSE ------------------------------------------------------ + PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) + BEGIN + IF nRSTO = '0' THEN DMA_TOP <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then - DMA_TOP <= FB_AD(31 downto 24); - else - DMA_TOP <= DMA_TOP; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') THEN + DMA_TOP <= FB_AD(31 DOWNTO 24); + ELSE + DMA_TOP <= DMA_TOP; + END IF; END PROCESS; - process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN + + PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) + BEGIN + IF nRSTO = '0' THEN DMA_HIGH <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then - DMA_HIGH <= FB_AD(23 downto 16); - else - DMA_HIGH <= DMA_HIGH; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') THEN + DMA_HIGH <= FB_AD(23 DOWNTO 16); + ELSE + DMA_HIGH <= DMA_HIGH; + END IF; END PROCESS; - process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) - begin + + PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) + BEGIN DMA_MID <= DMA_MID; - if nRSTO = '0' THEN + IF nRSTO = '0' THEN DMA_MID <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_MID_CS = '1' then - DMA_MID <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_MID <= FB_AD(15 downto 8); - end if; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN + IF DMA_MID_CS = '1' THEN + DMA_MID <= FB_AD(23 DOWNTO 16); + ELSIF DMA_ADR_CS = '1' THEN + DMA_MID <= FB_AD(15 DOWNTO 8); + END IF; + END IF; END PROCESS; - process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) - begin + + PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) + BEGIN DMA_LOW <= DMA_LOW; - if nRSTO = '0' THEN + IF nRSTO = '0' THEN DMA_LOW <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_LOW_CS = '1'then - DMA_LOW <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_LOW <= FB_AD(7 downto 0); - end if; - end if; + ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN + IF DMA_LOW_CS = '1'THEN + DMA_LOW <= FB_AD(23 DOWNTO 16); + ELSIF DMA_ADR_CS = '1' THEN + DMA_LOW <= FB_AD(7 DOWNTO 0); + END IF; + END IF; END PROCESS; --------------------------------------------------------------------------------------------- -DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 -DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 -DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 -DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 -FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- DIRECTZUGRIFF -DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD -DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG -DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG -FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; --- DMA RW TOGGLE ------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) - begin - if nRSTO = '0' THEN + + -------------------------------------------------------------------------------------------- + DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B0 = '1' ELSE '0'; -- F8608/2 + DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B1 = '1' ELSE '0'; -- F8609/2 + DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C305" and FB_B1 = '1' ELSE '0'; -- F860B/2 + DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C306" and FB_B1 = '1' ELSE '0'; -- F860D/2 + + FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + -- DIRECTZUGRIFF + DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD + DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG + DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG + + FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + + -- DMA RW TOGGLE ------------------------------------------ + + PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) + BEGIN + IF nRSTO = '0' THEN DMA_DIR_OLD <= '0'; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then + ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' THEN DMA_DIR_OLD <= DMA_MODUS(8); - else + ELSE DMA_DIR_OLD <= DMA_DIR_OLD; - end if; + END IF; END PROCESS; -CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; --- SCSI ---------------------------------------------------------------------------------- + + CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; + + -- SCSI ---------------------------------------------------------------------------------- I_SCSI: WF5380_TOP_SOC - port map( + PORT MAP( CLK => FDC_CLK, RESETn => nRSTO, ADR => CA2 & CA1 & CA0, @@ -744,30 +768,35 @@ CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; -- MSG_OUTn => MSG_OUTn, -- MSG_EN => MSG_EN ); --- SCSI ACSI --------------------------------------------------------------- -SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; -SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET -SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; -nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; -nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; -nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; -ACSI_DIR <= '0'; -ACSI_D <= "ZZZZZZZZ"; -nACSI_CS <= '1'; -ACSI_A1 <= CA1; -nACSI_RESET <= nRSTO; -nACSI_ACK <= '1'; ----------------------------------------------------------------------------- --- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ----------------------------------------------------------------------------- -ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 -nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; -nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; ----------------------------------------------------------------------------- --- ACIA KEYBOARD ----------------------------------------------------------------------------- + + -- SCSI ACSI --------------------------------------------------------------- + SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z'); + SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET + SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z'; + nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z'; + nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z'; + nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z'; + ACSI_DIR <= '0'; + ACSI_D <= (OTHERS => 'Z'); + nACSI_CS <= '1'; + ACSI_A1 <= CA1; + nACSI_RESET <= nRSTO; + nACSI_ACK <= '1'; + + + ---------------------------------------------------------------------------- + -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns + ---------------------------------------------------------------------------- + ROM_CS <= '1' WHEN nFB_CS1 = '0' AND nFB_WR = '1' AND FB_ADR(19 DOWNTO 17) = x"5" ELSE '0'; -- FFF A'0000/2'0000 + nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1'; + nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1'; + + + ---------------------------------------------------------------------------- + -- ACIA KEYBOARD + ---------------------------------------------------------------------------- I_ACIA_KEYBOARD: WF6850IP_TOP_SOC - port map( + PORT MAP( CLK => MAIN_CLK, RESETn => nRSTO, @@ -778,7 +807,7 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 downto 24), + DATA_IN => FB_AD(31 DOWNTO 24), DATA_OUT => DATA_OUT_ACIA_I, -- DATA_EN => DATA_EN_ACIA_I, @@ -793,13 +822,15 @@ nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; TXDATA => AMKB_TX --RTSn => -- Not used. ); -ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 -KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL -FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; --- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ - process(CLK2M, AMKB_RX, AMKB_REG) - begin - if rising_edge(CLK2M) then + + ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 + KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ"; + + -- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(CLK2M, AMKB_RX, AMKB_REG) + BEGIN + IF rising_edge(CLK2M) THEN IF AMKB_RX = '0' THEN IF AMKB_REG < 16 THEN AMKB_REG <= "00000"; @@ -815,13 +846,14 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' END IF; ELSE AMKB_REG <= AMKB_REG; - end if; + END IF; END PROCESS; ----------------------------------------------------------------------------- --- ACIA MIDI ----------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + -- ACIA MIDI + ---------------------------------------------------------------------------- I_ACIA_MIDI: WF6850IP_TOP_SOC - port map( + PORT MAP( CLK => MAIN_CLK, RESETn => nRSTO, @@ -832,7 +864,7 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 downto 24), + DATA_IN => FB_AD(31 DOWNTO 24), DATA_OUT => DATA_OUT_ACIA_II, -- DATA_EN => DATA_EN_ACIA_II, @@ -845,15 +877,17 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' IRQn => IRQ_MIDIn, TXDATA => MIDI_OUT --RTSn => -- Not used. - ); -MIDI_TLR <= MIDI_OUT; -MIDI_OLR <= MIDI_OUT; -FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ----------------------------------------------------------------------------- --- MFP ----------------------------------------------------------------------------- + ); + + MIDI_TLR <= MIDI_OUT; + MIDI_OLR <= MIDI_OUT; + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + ---------------------------------------------------------------------------- + -- MFP + ---------------------------------------------------------------------------- I_MFP: WF68901IP_TOP_SOC - port map( + PORT MAP( -- System control: CLK => MAIN_CLK, RESETn => nRSTO, @@ -863,8 +897,8 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' RWn => nFB_WR, DTACKn => DTACK_OUT_MFPn, -- Data and Adresses: - RS => FB_ADR(5 downto 1), - DATA_IN => FB_AD(23 downto 16), + RS => FB_ADR(5 DOWNTO 1), + DATA_IN => FB_AD(23 DOWNTO 16), DATA_OUT => DATA_OUT_MFP, -- DATA_EN => DATA_EN_MFP, GPIP_IN(7) => not DMA_DRQ_Q, @@ -901,32 +935,36 @@ FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' -- TRn => ); -MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 -MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 -LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; -FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; -DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else - '0' when FDINT = '1' else - '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1'; --- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) - begin - if nRSTO = '0' THEN + MFP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 6) = x"3FE8" ELSE '0'; -- FFA00/40 + MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 + LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; + + FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ; + FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; + + DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE + '0' WHEN FDINT = '1' ELSE + '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; + + -- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ + PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn) + BEGIN + IF nRSTO = '0' THEN IRQ_ACIAn <= '1'; - elsif rising_edge(MAIN_CLK) then - IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; - else + ELSIF rising_edge(MAIN_CLK) THEN + IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn; + ELSE IRQ_ACIAn <= IRQ_ACIAn; - end if; + END IF; END PROCESS; ----------------------------------------------------------------------------- --- Sound ----------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + -- Sound + ---------------------------------------------------------------------------- I_SOUND: WF2149IP_TOP_SOC - port map( + PORT MAP( SYS_CLK => MAIN_CLK, RESETn => nRSTO, @@ -939,7 +977,7 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else A9n => '0', A8 => '1', - DA_IN => FB_AD(31 downto 24), + DA_IN => FB_AD(31 DOWNTO 24), DA_OUT => DA_OUT_X, IO_A_IN => x"00", -- All port pins are dedicated outputs. @@ -951,21 +989,21 @@ DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else -- IO_A_OUT(2) => FDD_D1SEL, IO_A_OUT(1) => DSA_D, IO_A_OUT(0) => nSDSEL, - -- IO_A_EN =>, -- Not required. +-- IO_A_EN =>, -- Not required. IO_B_IN => LP_D, IO_B_OUT => LP_D_X, - -- IO_B_EN => IO_B_EN, +-- IO_B_EN => IO_B_EN, OUT_A => YM_QA, OUT_B => YM_QB, OUT_C => YM_QC ); -SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 -SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; -SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; -FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; -LP_DIR <= LP_DIR_X; - -END FalconIO_SDCard_IDE_CF_architecture; + SNDCS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 + SNDCS_I <= '1' WHEN SNDCS = '1' and FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; + SNDIR_I <= '1' WHEN SNDCS = '1' and nFB_WR = '0' ELSE '0'; + FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z'); + LP_DIR <= LP_DIR_X; +END rtl; diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index eafe6c2..40b2fe6 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -98,12 +98,12 @@ VARIABLE VDL_LWD[15..0] :DFFE; VDL_LWD_CS :NODE; -- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT + CLUT_TA :DFF; -- needs one wait state HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- L�NGE HSYNC PULS IN PIXEL_CLK + HSY_LEN[7..0] :DFF; -- length of hsync pulse in pixel_clk HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT + LAST :DFF; -- reached last pixel of a line VSYNC :DFF; VSYNC_START :DFFE; VSYNC_I[2..0] :DFFE; @@ -194,7 +194,7 @@ VARIABLE ACP_VCTR6_DUP : NODE; BEGIN --- BYT SELECT 32 BIT + -- BYT SELECT 32 BIT FB_B0 = FB_ADR[1..0]==0; -- ADR==0 FB_B1 = FB_ADR[1..0]==1 -- ADR==1 # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD @@ -204,46 +204,75 @@ BEGIN FB_B3 = FB_ADR[1..0]==3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT + + -- BYT SELECT 16 BIT FB_16B0 = FB_ADR[0]==0; -- ADR==0 FB_16B1 = FB_ADR[0]==1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT --- ACP CLUT -- + + -- ACP CLUT -- ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; + + CLUT_TA.CLK = MAIN_CLK; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; ---FALCON CLUT -- + + + --FALCON CLUT -- FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; --- ST CLUT -- + + + -- ST CLUT -- ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; --- ST SHIFT MODE + + + -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 ST_SHIFT_MODE[] = FB_AD[25..24]; ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + + COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN --- FALCON SHIFT MODE + + + -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE[] = FB_AD[26..16]; FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; + + CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; + + COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + + + -- ACP VIDEO CONTROL + -- BIT 0=ACP VIDEO ON, + -- 1=POWER ON VIDEO DAC, + -- 2=ACP 24BIT, + -- 3=ACP 16BIT, + -- 4=ACP 8BIT, + -- 5=ACP 1BIT, + -- 6=FALCON SHIFT MODE, + -- 7=ST SHIFT MODE, + -- 9..8= VCLK FREQUENZ, + -- 15=-SYNC ALLOWED, + -- 31..16=VIDEO_RAM_CTR, + -- 25=RANDFARBE EINSCHALTEN, + -- 26=STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; @@ -254,9 +283,11 @@ BEGIN ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; - -- ATARI MODUS + + -- ATARI MODUS ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL�SUNG - -- HORIZONTAL TIMING 640x480 + + -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 ATARI_HH[] = FB_AD[]; @@ -264,7 +295,8 @@ BEGIN ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 + + -- VERTIKAL TIMING 640x480 ATARI_VH[].CLK = MAIN_CLK; ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 ATARI_VH[] = FB_AD[]; @@ -272,7 +304,8 @@ BEGIN ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 + + -- HORIZONTAL TIMING 320x240 ATARI_HL[].CLK = MAIN_CLK; ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 ATARI_HL[] = FB_AD[]; @@ -280,7 +313,8 @@ BEGIN ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 + + -- VERTIKAL TIMING 320x240 ATARI_VL[].CLK = MAIN_CLK; ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 ATARI_VL[] = FB_AD[]; @@ -288,7 +322,9 @@ BEGIN ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; --- VIDEO PLL CONFIG + + + -- VIDEO PLL CONFIG VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VR_WR.CLK = MAIN_CLK; VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; @@ -299,22 +335,26 @@ BEGIN VR_FRQ[].CLK = MAIN_CLK; VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; VR_FRQ[] = FB_AD[23..16]; --- VIDEO PLL RECONFIG + + -- VIDEO PLL RECONFIG VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------- + + ------------------------------------------------------------------------------------------------------------------------ VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; --------------- COLOR MODE IM ACP SETZEN + + -------------- COLOR MODE IM ACP SETZEN COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + + -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - -- duplicate ACP_VCTR6 according to TimeQuest reccomendations + -- duplicate ACP_VCTR6 according to TimeQuest recommendations ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR6 = ACP_VCTR6_DUP; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; @@ -329,118 +369,140 @@ BEGIN # B"101" & COLOR16 # B"110" & COLOR24 # B"111" & RAND_ON; --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE + + -- DIVERSE (VIDEO)-REGISTER ---------------------------- + + -- RANDFARBE CCR[].CLK = MAIN_CLK; CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 CCR[] = FB_AD[23..0]; CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; ---SYS CTR + + --SYS CTR SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; BLITTER_ON = !SYS_CTR3; ---VDL_LOF + + --VDL_LOF VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 VDL_LOF[].CLK = MAIN_CLK; VDL_LOF[] = FB_AD[31..16]; VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; ---VDL_LWD + + --VDL_LWD VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 VDL_LWD[].CLK = MAIN_CLK; VDL_LWD[] = FB_AD[31..16]; VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; --- HORIZONTAL --- VDL_HHT + + -- HORIZONTAL + + -- VDL_HHT VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 VDL_HHT[].CLK = MAIN_CLK; VDL_HHT[] = FB_AD[27..16]; VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; --- VDL_HBE + + -- VDL_HBE VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 VDL_HBE[].CLK = MAIN_CLK; VDL_HBE[] = FB_AD[27..16]; VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; --- VDL_HDB + + -- VDL_HDB VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 VDL_HDB[].CLK = MAIN_CLK; VDL_HDB[] = FB_AD[27..16]; VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; --- VDL_HDE + + -- VDL_HDE VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 VDL_HDE[].CLK = MAIN_CLK; VDL_HDE[] = FB_AD[27..16]; VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; --- VDL_HBB + + -- VDL_HBB VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 VDL_HBB[].CLK = MAIN_CLK; VDL_HBB[] = FB_AD[27..16]; VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; --- VDL_HSS + + -- VDL_HSS VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 VDL_HSS[].CLK = MAIN_CLK; VDL_HSS[] = FB_AD[27..16]; VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; --- VERTIKAL --- VDL_VBE + + -- VERTIKAL + + -- VDL_VBE VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 VDL_VBE[].CLK = MAIN_CLK; VDL_VBE[] = FB_AD[26..16]; VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; --- VDL_VDB + + -- VDL_VDB VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 VDL_VDB[].CLK = MAIN_CLK; VDL_VDB[] = FB_AD[26..16]; VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; --- VDL_VDE + + -- VDL_VDE VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 VDL_VDE[].CLK = MAIN_CLK; VDL_VDE[] = FB_AD[26..16]; VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; --- VDL_VBB + + -- VDL_VBB VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 VDL_VBB[].CLK = MAIN_CLK; VDL_VBB[] = FB_AD[26..16]; VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; --- VDL_VSS + + -- VDL_VSS VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 VDL_VSS[].CLK = MAIN_CLK; VDL_VSS[] = FB_AD[26..16]; VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; --- VDL_VFT + + -- VDL_VFT VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 VDL_VFT[].CLK = MAIN_CLK; VDL_VFT[] = FB_AD[26..16]; VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; --- VDL_VCT + + -- VDL_VCT VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 VDL_VCT[].CLK = MAIN_CLK; VDL_VCT[] = FB_AD[24..16]; VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; --- VDL_VMD + + -- VDL_VMD VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 VDL_VMD[].CLK = MAIN_CLK; VDL_VMD[] = FB_AD[19..16]; VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; ---- REGISTER OUT + + --- REGISTER OUT FB_AD[31..16] = lpm_bustri_WORD( ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) @@ -488,7 +550,8 @@ BEGIN # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; --- VIDEO AUSGABE SETZEN + + -- VIDEO AUSGABE SETZEN CLK17M.CLK = CLK33M; CLK17M = !CLK17M; CLK13M.CLK = CLK25M; @@ -500,9 +563,10 @@ BEGIN # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; --------------------------------------------------------------- --- HORIZONTALE SYNC L�NGE in PIXEL_CLK ----------------------------------------------------------------- + + -------------------------------------------------------------- + -- HORIZONTALE SYNC L�NGE in PIXEL_CLK + ---------------------------------------------------------------- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) @@ -521,7 +585,8 @@ BEGIN HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN # 640 & !VDL_VMD2; --- DOPPELZEILENMODUS + + -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS INTER_ZEI.CLK = PIXEL_CLK; @@ -570,7 +635,8 @@ BEGIN # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- Z�HLER + + -- Z�HLER LAST.CLK = PIXEL_CLK; LAST = VHCNT[]==(H_TOTAL[]-2); VHCNT[].CLK = PIXEL_CLK; @@ -578,7 +644,8 @@ BEGIN VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); --- DISPLAY ON OFF + + -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[] Date: Sun, 20 Sep 2015 15:07:18 +0000 Subject: [PATCH 015/127] renamed components to lower case --- FPGA_Quartus_13.1/DSP/DSP.vhd | 10 +- FPGA_Quartus_13.1/firebee1.bdf | 1112 ++++++++++++++++++-------------- 2 files changed, 631 insertions(+), 491 deletions(-) diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 26f8e2e..5dc95de 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -21,12 +21,12 @@ -- Created on Tue Sep 08 16:24:57 2009 LIBRARY ieee; -USE ieee.std_logic_1164.all; + USE ieee.std_logic_1164.all; -- Entity Declaration -ENTITY DSP IS +ENTITY dsp IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( @@ -55,12 +55,12 @@ ENTITY DSP IS ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -END DSP; +END dsp; -- Architecture Body -ARCHITECTURE DSP_architecture OF DSP IS +ARCHITECTURE rtl OF DSP IS BEGIN @@ -76,4 +76,4 @@ BEGIN FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; -END DSP_architecture; +END rtl; diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index 93c5f32..966f327 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -3377,119 +3377,6 @@ applicable agreement for further details. (line (pt 16 24)(pt 16 273)) ) ) -(block - (rect 1264 2944 1672 3560) - (text "DSP" (rect 5 5 32 18)(font "Arial" (font_size 8))) (text "i_dsp" (rect 5 602 33 613)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "nFB_OE" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "nRSTO" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nSRCS" (output)) - (block_io "nSRBLE" (output)) - (block_io "nSRBHE" (output)) - (block_io "nSRWE" (output)) - (block_io "nSROE" (output)) - (block_io "DSP_INT" (output)) - (block_io "DSP_TA" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "IO[17..0]" (bidir)) - (block_io "SRD[15..0]" (bidir)) - (mapper - (pt 408 416) - (bidir) - ) - (mapper - (pt 408 392) - (bidir) - ) - (mapper - (pt 408 368) - (bidir) - ) - (mapper - (pt 408 320) - (bidir) - ) - (mapper - (pt 408 440) - (bidir) - ) - (mapper - (pt 408 344) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 40) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 576) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) -) (block (rect 1264 2344 1672 2904) (text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input)) @@ -3618,9 +3505,222 @@ applicable agreement for further details. (bidir) ) ) +(block + (rect 1264 -40 1672 736) + (text "video" (rect 5 5 36 18)(font "Arial" (font_size 8))) (text "i_video" (rect 5 762 41 773)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nFB_CS3" (input)) + (block_io "nFB_WR" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nRSTO" (input)) + (block_io "nFB_OE" (input)) + (block_io "FB_ALE" (input)) + (block_io "DDRCLK[3..0]" (input)) + (block_io "DDR_SYNC_66M" (input)) + (block_io "CLK33M" (input)) + (block_io "CLK25M" (input)) + (block_io "CLK_VIDEO" (input)) + (block_io "VR_D[8..0]" (input)) + (block_io "VR_BUSY" (input)) + (block_io "VR_RD" (output)) + (block_io "VG[7..0]" (output)) + (block_io "VB[7..0]" (output)) + (block_io "VR[7..0]" (output)) + (block_io "nBLANK" (output)) + (block_io "VA[12..0]" (output)) + (block_io "nVWE" (output)) + (block_io "nVCAS" (output)) + (block_io "nVRAS" (output)) + (block_io "nVCS" (output)) + (block_io "VDM[3..0]" (output)) + (block_io "nPD_VGA" (output)) + (block_io "VCKE" (output)) + (block_io "VSYNC" (output)) + (block_io "HSYNC" (output)) + (block_io "nSYNC" (output)) + (block_io "VIDEO_TA" (output)) + (block_io "PIXEL_CLK" (output)) + (block_io "BA[1..0]" (output)) + (block_io "VIDEO_RECONFIG" (output)) + (block_io "VR_WR" (output)) + (block_io "VDQS[3..0]" (bidir)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "VD[31..0]" (bidir)) + (mapper + (pt 408 448) + (bidir) + ) + (mapper + (pt 408 496) + (bidir) + ) + (mapper + (pt 408 592) + (bidir) + ) + (mapper + (pt 408 352) + (bidir) + ) + (mapper + (pt 408 760) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 0 392) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 344) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 128) + (bidir) + ) + (mapper + (pt 408 152) + (bidir) + ) + (mapper + (pt 408 176) + (bidir) + ) + (mapper + (pt 408 200) + (bidir) + ) + (mapper + (pt 408 224) + (bidir) + ) + (mapper + (pt 408 248) + (bidir) + ) + (mapper + (pt 408 272) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 0 416) + (bidir) + ) + (mapper + (pt 408 320) + (bidir) + ) + (mapper + (pt 408 472) + (bidir) + ) + (mapper + (pt 408 424) + (bidir) + ) + (mapper + (pt 408 400) + (bidir) + ) + (mapper + (pt 408 376) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 368) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 408 568) + (bidir) + ) + (mapper + (pt 408 520) + (bidir) + ) + (mapper + (pt 0 648) + (bidir) + ) + (mapper + (pt 0 672) + (bidir) + ) + (mapper + (pt 0 616) + (bidir) + ) + (mapper + (pt 0 528) + (bidir) + ) + (mapper + (pt 408 656) + (bidir) + ) + (mapper + (pt 408 640) + (bidir) + ) + (mapper + (pt 408 624) + (bidir) + ) + (mapper + (pt 0 512) + (bidir) + ) +) (block (rect 1264 744 1672 2264) - (text "FalconIO_SDCard_IDE_CF" (rect 5 5 160 18)(font "Arial" (font_size 8))) (text "i_falcon_io_sdcard_ide_cf" (rect 5 1506 133 1517)(font "Arial" )) (block_io "CLK33M" (input)) + (text "falconio_sdcard_ide_cf" (rect 5 5 135 18)(font "Arial" (font_size 8))) (text "i_falcon_io_sdcard_ide_cf" (rect 5 1506 133 1517)(font "Arial" )) (block_io "CLK33M" (input)) (block_io "MAIN_CLK" (input)) (block_io "CLK2M" (input)) (block_io "CLK500k" (input)) @@ -4133,139 +4233,39 @@ applicable agreement for further details. ) ) (block - (rect 1264 -48 1672 728) - (text "Video" (rect 5 5 39 18)(font "Arial" (font_size 8))) (text "i_video" (rect 5 762 41 773)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) + (rect 1264 2944 1672 3560) + (text "dsp" (rect 5 5 27 18)(font "Arial" (font_size 8))) (text "i_dsp" (rect 5 602 33 613)(font "Arial" )) (block_io "CLK33M" (input)) (block_io "MAIN_CLK" (input)) + (block_io "nFB_OE" (input)) + (block_io "nFB_WR" (input)) (block_io "nFB_CS1" (input)) (block_io "nFB_CS2" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nFB_WR" (input)) (block_io "FB_SIZE0" (input)) (block_io "FB_SIZE1" (input)) + (block_io "nFB_BURST" (input)) + (block_io "FB_ADR[31..0]" (input)) (block_io "nRSTO" (input)) - (block_io "nFB_OE" (input)) - (block_io "FB_ALE" (input)) - (block_io "DDRCLK[3..0]" (input)) - (block_io "DDR_SYNC_66M" (input)) - (block_io "CLK33M" (input)) - (block_io "CLK25M" (input)) - (block_io "CLK_VIDEO" (input)) - (block_io "VR_D[8..0]" (input)) - (block_io "VR_BUSY" (input)) - (block_io "VR_RD" (output)) - (block_io "VG[7..0]" (output)) - (block_io "VB[7..0]" (output)) - (block_io "VR[7..0]" (output)) - (block_io "nBLANK" (output)) - (block_io "VA[12..0]" (output)) - (block_io "nVWE" (output)) - (block_io "nVCAS" (output)) - (block_io "nVRAS" (output)) - (block_io "nVCS" (output)) - (block_io "VDM[3..0]" (output)) - (block_io "nPD_VGA" (output)) - (block_io "VCKE" (output)) - (block_io "VSYNC" (output)) - (block_io "HSYNC" (output)) - (block_io "nSYNC" (output)) - (block_io "VIDEO_TA" (output)) - (block_io "PIXEL_CLK" (output)) - (block_io "BA[1..0]" (output)) - (block_io "VIDEO_RECONFIG" (output)) - (block_io "VR_WR" (output)) - (block_io "VDQS[3..0]" (bidir)) + (block_io "nFB_CS3" (input)) + (block_io "nSRCS" (output)) + (block_io "nSRBLE" (output)) + (block_io "nSRBHE" (output)) + (block_io "nSRWE" (output)) + (block_io "nSROE" (output)) + (block_io "DSP_INT" (output)) + (block_io "DSP_TA" (output)) (block_io "FB_AD[31..0]" (bidir)) - (block_io "VD[31..0]" (bidir)) + (block_io "IO[17..0]" (bidir)) + (block_io "SRD[15..0]" (bidir)) (mapper - (pt 408 448) + (pt 408 416) (bidir) ) (mapper - (pt 408 496) + (pt 408 392) (bidir) ) (mapper - (pt 408 592) - (bidir) - ) - (mapper - (pt 408 352) - (bidir) - ) - (mapper - (pt 408 760) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 0 392) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 344) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 128) - (bidir) - ) - (mapper - (pt 408 152) - (bidir) - ) - (mapper - (pt 408 176) - (bidir) - ) - (mapper - (pt 408 200) - (bidir) - ) - (mapper - (pt 408 224) - (bidir) - ) - (mapper - (pt 408 248) - (bidir) - ) - (mapper - (pt 408 272) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 0 416) + (pt 408 368) (bidir) ) (mapper @@ -4273,31 +4273,39 @@ applicable agreement for further details. (bidir) ) (mapper - (pt 408 472) + (pt 408 440) (bidir) ) (mapper - (pt 408 424) + (pt 408 344) (bidir) ) (mapper - (pt 408 400) + (pt 408 296) (bidir) ) (mapper - (pt 408 376) + (pt 408 40) (bidir) ) (mapper - (pt 0 224) + (pt 0 56) (bidir) ) (mapper - (pt 0 368) + (pt 0 80) (bidir) ) (mapper - (pt 0 200) + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 152) (bidir) ) (mapper @@ -4305,43 +4313,35 @@ applicable agreement for further details. (bidir) ) (mapper - (pt 408 568) + (pt 0 248) (bidir) ) (mapper - (pt 408 520) + (pt 0 224) (bidir) ) (mapper - (pt 0 648) + (pt 0 272) (bidir) ) (mapper - (pt 0 672) + (pt 0 296) (bidir) ) (mapper - (pt 0 616) + (pt 408 72) (bidir) ) (mapper - (pt 0 528) + (pt 408 576) (bidir) ) (mapper - (pt 408 656) + (pt 0 320) (bidir) ) (mapper - (pt 408 640) - (bidir) - ) - (mapper - (pt 408 624) - (bidir) - ) - (mapper - (pt 0 512) + (pt 0 200) (bidir) ) ) @@ -4734,58 +4734,6 @@ applicable agreement for further details. (pt 1672 1720) (pt 1856 1720) ) -(connector - (text "FB_AD[31..0]" (rect 1682 8 1748 19)(font "Arial" )) - (pt 1832 24) - (pt 1672 24) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 328 1220 339)(font "Arial" )) - (pt 1112 344) - (pt 1264 344) - (bus) -) -(connector - (text "nFB_WR" (rect 1162 184 1208 195)(font "Arial" )) - (pt 1152 200) - (pt 1264 200) -) -(connector - (text "nFB_CS1" (rect 1154 208 1202 219)(font "Arial" )) - (pt 1152 224) - (pt 1264 224) -) -(connector - (text "FB_SIZE0" (rect 1154 256 1205 267)(font "Arial" )) - (pt 1152 272) - (pt 1264 272) -) -(connector - (text "FB_SIZE1" (rect 1154 280 1204 291)(font "Arial" )) - (pt 1152 296) - (pt 1264 296) -) -(connector - (text "nFB_CS2" (rect 1162 232 1211 243)(font "Arial" )) - (pt 1152 248) - (pt 1264 248) -) -(connector - (text "nBLANK" (rect 1682 184 1726 195)(font "Arial" )) - (pt 1672 200) - (pt 1832 200) -) -(connector - (text "nSYNC" (rect 1682 208 1720 219)(font "Arial" )) - (pt 1672 224) - (pt 1832 224) -) -(connector - (text "nFB_CS3" (rect 1186 352 1235 363)(font "Arial" )) - (pt 1264 368) - (pt 1176 368) -) (connector (text "nFB_WR" (rect 1170 928 1216 939)(font "Arial" )) (pt 1264 944) @@ -4826,11 +4774,6 @@ applicable agreement for further details. (pt 1264 1136) (pt 1160 1136) ) -(connector - (text "nPD_VGA" (rect 1682 256 1736 267)(font "Arial" )) - (pt 1672 272) - (pt 1832 272) -) (connector (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) (pt 1152 2600) @@ -4852,11 +4795,6 @@ applicable agreement for further details. (pt 1264 920) (pt 1160 920) ) -(connector - (text "nFB_OE" (rect 1170 160 1213 171)(font "Arial" )) - (pt 1264 176) - (pt 1160 176) -) (connector (text "nFB_OE" (rect 1170 2392 1213 2403)(font "Arial" )) (pt 1264 2408) @@ -4916,87 +4854,6 @@ applicable agreement for further details. (pt 528 2416) (pt 616 2416) ) -(connector - (text "FB_ALE" (rect 1194 304 1236 315)(font "Arial" )) - (pt 1264 320) - (pt 1184 320) -) -(connector - (text "DDRCLK[3..0]" (rect 1162 136 1232 147)(font "Arial" )) - (pt 1152 152) - (pt 1264 152) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 1178 112 1267 123)(font "Arial" )) - (pt 1168 128) - (pt 1264 128) -) -(connector - (text "VD[31..0]" (rect 1682 288 1728 299)(font "Arial" )) - (pt 1672 304) - (pt 2648 304) - (bus) -) -(connector - (text "VA[12..0]" (rect 1682 312 1728 323)(font "Arial" )) - (pt 1672 328) - (pt 2528 328) - (bus) -) -(connector - (text "nVWE" (rect 1682 336 1715 347)(font "Arial" )) - (pt 1672 352) - (pt 2400 352) -) -(connector - (text "nVCAS" (rect 1690 360 1727 371)(font "Arial" )) - (pt 1672 376) - (pt 2304 376) -) -(connector - (text "nVRAS" (rect 1690 384 1727 395)(font "Arial" )) - (pt 1672 400) - (pt 2208 400) -) -(connector - (text "nVCS" (rect 1690 408 1720 419)(font "Arial" )) - (pt 1672 424) - (pt 2040 424) -) -(connector - (text "VCKE" (rect 1690 432 1721 443)(font "Arial" )) - (pt 1672 448) - (pt 1944 448) -) -(connector - (text "VSYNC" (rect 1682 136 1722 147)(font "Arial" )) - (pt 1672 152) - (pt 1832 152) -) -(connector - (text "HSYNC" (rect 1682 160 1722 171)(font "Arial" )) - (pt 1672 176) - (pt 1832 176) -) -(connector - (text "VB[7..0]" (rect 1754 112 1794 123)(font "Arial" )) - (pt 1672 128) - (pt 1912 128) - (bus) -) -(connector - (text "VG[7..0]" (rect 1842 88 1883 99)(font "Arial" )) - (pt 1672 104) - (pt 2000 104) - (bus) -) -(connector - (text "VR[7..0]" (rect 1922 64 1962 75)(font "Arial" )) - (pt 1672 80) - (pt 2080 80) - (bus) -) (connector (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) (pt 1672 1072) @@ -5020,11 +4877,6 @@ applicable agreement for further details. (pt 776 1496) (pt 1264 1496) ) -(connector - (text "CLK25M" (rect 1202 608 1246 619)(font "Arial" )) - (pt 1192 624) - (pt 1264 624) -) (connector (text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" )) (pt 440 2136) @@ -5070,11 +4922,6 @@ applicable agreement for further details. (pt 1672 2848) (pt 1808 2848) ) -(connector - (text "Video_TA" (rect 1682 696 1732 707)(font "Arial" )) - (pt 1672 712) - (pt 1880 712) -) (connector (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) (pt 1672 760) @@ -5111,22 +4958,6 @@ applicable agreement for further details. (pt 2504 760) (pt 2536 760) ) -(connector - (text "MAIN_CLK" (rect 1186 88 1243 99)(font "Arial" )) - (pt 1184 104) - (pt 1264 104) -) -(connector - (text "nRSTO" (rect 1194 40 1232 51)(font "Arial" )) - (pt 1184 56) - (pt 1264 56) -) -(connector - (text "BA[1..0]" (rect 1682 456 1722 467)(font "Arial" )) - (pt 1672 472) - (pt 1832 472) - (bus) -) (connector (text "PIXEL_CLK" (rect 2394 -64 2455 -53)(font "Arial" )) (pt 2384 -48) @@ -5164,11 +4995,6 @@ applicable agreement for further details. (pt 2128 -64) (pt 2136 -64) ) -(connector - (text "PIXEL_CLK" (rect 1682 232 1743 243)(font "Arial" )) - (pt 1744 248) - (pt 1672 248) -) (connector (text "PIXEL_CLK" (rect 2394 184 2455 195)(font "Arial" )) (pt 2384 200) @@ -5517,69 +5343,23 @@ applicable agreement for further details. (pt 64 544) (pt 192 544) ) -(connector - (text "VR_D[8..0]" (rect 1170 464 1224 475)(font "Arial" )) - (pt 1144 480) - (pt 1264 480) - (bus) -) (connector (text "VDQS[3..0]" (rect 1674 504 1730 515)(font "Arial" )) (pt 2040 544) (pt 1960 544) (bus) ) -(connector - (pt 1672 544) - (pt 1888 544) - (bus) -) -(connector - (pt 1888 544) - (pt 1888 568) - (bus) -) (connector (text "VDM[3..0]" (rect 1682 528 1731 539)(font "Arial" )) (pt 1944 568) (pt 1888 568) (bus) ) -(connector - (pt 1672 520) - (pt 1960 520) - (bus) -) -(connector - (pt 1960 544) - (pt 1960 520) - (bus) -) -(connector - (text "VIDEO_RECONFIG" (rect 1674 560 1774 571)(font "Arial" )) - (pt 1672 576) - (pt 1792 576) -) -(connector - (text "VR_WR" (rect 1698 592 1739 603)(font "Arial" )) - (pt 1672 608) - (pt 1792 608) -) (connector (text "VR_BUSY" (rect 418 496 472 507)(font "Arial" )) (pt 408 512) (pt 480 512) ) -(connector - (text "VR_BUSY" (rect 1170 448 1224 459)(font "Arial" )) - (pt 1144 464) - (pt 1264 464) -) -(connector - (text "VR_RD" (rect 1698 576 1736 587)(font "Arial" )) - (pt 1792 592) - (pt 1672 592) -) (connector (text "nRSTO" (rect -86 680 -48 691)(font "Arial" )) (pt -96 696) @@ -5600,11 +5380,6 @@ applicable agreement for further details. (pt 528 568) (pt 608 568) ) -(connector - (text "CLK_VIDEO" (rect 1162 552 1225 563)(font "Arial" )) - (pt 984 568) - (pt 1264 568) -) (connector (text "CLK500k" (rect 802 232 849 243)(font "Arial" )) (pt 768 248) @@ -5769,11 +5544,6 @@ applicable agreement for further details. (pt 336 304) (pt 400 304) ) -(connector - (text "MAIN_CLK" (rect 1202 584 1259 595)(font "Arial" )) - (pt 1264 600) - (pt 1192 600) -) (connector (text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" )) (pt 1200 776) @@ -5814,6 +5584,376 @@ applicable agreement for further details. (pt 272 -280) (pt 456 -280) ) +(connector + (text "FB_AD[31..0]" (rect 1682 16 1748 27)(font "Arial" )) + (pt 1832 32) + (pt 1672 32) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 336 1220 347)(font "Arial" )) + (pt 1112 352) + (pt 1264 352) + (bus) +) +(connector + (text "nFB_WR" (rect 1162 192 1208 203)(font "Arial" )) + (pt 1152 208) + (pt 1264 208) +) +(connector + (text "nFB_CS1" (rect 1154 216 1202 227)(font "Arial" )) + (pt 1152 232) + (pt 1264 232) +) +(connector + (text "FB_SIZE0" (rect 1154 264 1205 275)(font "Arial" )) + (pt 1152 280) + (pt 1264 280) +) +(connector + (text "FB_SIZE1" (rect 1154 288 1204 299)(font "Arial" )) + (pt 1152 304) + (pt 1264 304) +) +(connector + (text "nFB_CS2" (rect 1162 240 1211 251)(font "Arial" )) + (pt 1152 256) + (pt 1264 256) +) +(connector + (text "nBLANK" (rect 1682 192 1726 203)(font "Arial" )) + (pt 1672 208) + (pt 1832 208) +) +(connector + (pt 1680 80) + (pt 1680 88) + (bus) +) +(connector + (pt 2080 80) + (pt 1680 80) + (bus) +) +(connector + (text "VR[7..0]" (rect 1922 72 1962 83)(font "Arial" )) + (pt 1680 88) + (pt 1672 88) + (bus) +) +(connector + (pt 1688 104) + (pt 1688 112) + (bus) +) +(connector + (pt 2000 104) + (pt 1688 104) + (bus) +) +(connector + (text "VG[7..0]" (rect 1842 96 1883 107)(font "Arial" )) + (pt 1688 112) + (pt 1672 112) + (bus) +) +(connector + (pt 1696 128) + (pt 1696 136) + (bus) +) +(connector + (pt 1912 128) + (pt 1696 128) + (bus) +) +(connector + (text "VB[7..0]" (rect 1754 120 1794 131)(font "Arial" )) + (pt 1696 136) + (pt 1672 136) + (bus) +) +(connector + (pt 1704 224) + (pt 1704 232) +) +(connector + (pt 1832 224) + (pt 1704 224) +) +(connector + (text "nSYNC" (rect 1682 216 1720 227)(font "Arial" )) + (pt 1704 232) + (pt 1672 232) +) +(connector + (pt 1712 272) + (pt 1712 280) +) +(connector + (pt 1832 272) + (pt 1712 272) +) +(connector + (text "nPD_VGA" (rect 1682 264 1736 275)(font "Arial" )) + (pt 1712 280) + (pt 1672 280) +) +(connector + (pt 1720 328) + (pt 1720 336) + (bus) +) +(connector + (pt 2528 328) + (pt 1720 328) + (bus) +) +(connector + (text "VA[12..0]" (rect 1682 320 1728 331)(font "Arial" )) + (pt 1720 336) + (pt 1672 336) + (bus) +) +(connector + (pt 1728 352) + (pt 1728 360) +) +(connector + (pt 2400 352) + (pt 1728 352) +) +(connector + (text "nVWE" (rect 1682 344 1715 355)(font "Arial" )) + (pt 1728 360) + (pt 1672 360) +) +(connector + (pt 1256 368) + (pt 1256 376) +) +(connector + (pt 1176 368) + (pt 1256 368) +) +(connector + (text "nFB_CS3" (rect 1186 360 1235 371)(font "Arial" )) + (pt 1256 376) + (pt 1264 376) +) +(connector + (text "nFB_OE" (rect 1170 168 1213 179)(font "Arial" )) + (pt 1264 184) + (pt 1160 184) +) +(connector + (text "FB_ALE" (rect 1194 312 1236 323)(font "Arial" )) + (pt 1264 328) + (pt 1184 328) +) +(connector + (text "DDRCLK[3..0]" (rect 1162 144 1232 155)(font "Arial" )) + (pt 1152 160) + (pt 1264 160) + (bus) +) +(connector + (text "DDR_SYNC_66M" (rect 1178 120 1267 131)(font "Arial" )) + (pt 1168 136) + (pt 1264 136) +) +(connector + (pt 1736 304) + (pt 1736 312) + (bus) +) +(connector + (pt 2648 304) + (pt 1736 304) + (bus) +) +(connector + (text "VD[31..0]" (rect 1682 296 1728 307)(font "Arial" )) + (pt 1736 312) + (pt 1672 312) + (bus) +) +(connector + (pt 1744 376) + (pt 1744 384) +) +(connector + (pt 2304 376) + (pt 1744 376) +) +(connector + (text "nVCAS" (rect 1690 368 1727 379)(font "Arial" )) + (pt 1744 384) + (pt 1672 384) +) +(connector + (pt 1752 400) + (pt 1752 408) +) +(connector + (pt 2208 400) + (pt 1752 400) +) +(connector + (text "nVRAS" (rect 1690 392 1727 403)(font "Arial" )) + (pt 1752 408) + (pt 1672 408) +) +(connector + (pt 1760 424) + (pt 1760 432) +) +(connector + (pt 2040 424) + (pt 1760 424) +) +(connector + (text "nVCS" (rect 1690 416 1720 427)(font "Arial" )) + (pt 1760 432) + (pt 1672 432) +) +(connector + (pt 1768 448) + (pt 1768 456) +) +(connector + (pt 1944 448) + (pt 1768 448) +) +(connector + (text "VCKE" (rect 1690 440 1721 451)(font "Arial" )) + (pt 1768 456) + (pt 1672 456) +) +(connector + (text "VSYNC" (rect 1682 144 1722 155)(font "Arial" )) + (pt 1672 160) + (pt 1832 160) +) +(connector + (text "HSYNC" (rect 1682 168 1722 179)(font "Arial" )) + (pt 1672 184) + (pt 1832 184) +) +(connector + (text "CLK25M" (rect 1202 616 1246 627)(font "Arial" )) + (pt 1192 632) + (pt 1264 632) +) +(connector + (pt 1776 712) + (pt 1776 720) +) +(connector + (pt 1880 712) + (pt 1776 712) +) +(connector + (text "Video_TA" (rect 1682 704 1732 715)(font "Arial" )) + (pt 1776 720) + (pt 1672 720) +) +(connector + (text "MAIN_CLK" (rect 1186 96 1243 107)(font "Arial" )) + (pt 1184 112) + (pt 1264 112) +) +(connector + (text "nRSTO" (rect 1194 48 1232 59)(font "Arial" )) + (pt 1184 64) + (pt 1264 64) +) +(connector + (pt 1784 472) + (pt 1784 480) + (bus) +) +(connector + (pt 1832 472) + (pt 1784 472) + (bus) +) +(connector + (text "BA[1..0]" (rect 1682 464 1722 475)(font "Arial" )) + (pt 1784 480) + (pt 1672 480) + (bus) +) +(connector + (text "PIXEL_CLK" (rect 1682 240 1743 251)(font "Arial" )) + (pt 1744 256) + (pt 1672 256) +) +(connector + (text "VR_D[8..0]" (rect 1170 472 1224 483)(font "Arial" )) + (pt 1144 488) + (pt 1264 488) + (bus) +) +(connector + (pt 1888 552) + (pt 1672 552) + (bus) +) +(connector + (pt 1888 568) + (pt 1888 552) + (bus) +) +(connector + (pt 1960 528) + (pt 1672 528) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 528) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1674 568 1774 579)(font "Arial" )) + (pt 1672 584) + (pt 1792 584) +) +(connector + (text "VR_WR" (rect 1698 600 1739 611)(font "Arial" )) + (pt 1672 616) + (pt 1792 616) +) +(connector + (text "VR_BUSY" (rect 1170 456 1224 467)(font "Arial" )) + (pt 1144 472) + (pt 1264 472) +) +(connector + (text "VR_RD" (rect 1698 584 1736 595)(font "Arial" )) + (pt 1792 600) + (pt 1672 600) +) +(connector + (pt 1248 568) + (pt 1248 576) +) +(connector + (pt 984 568) + (pt 1248 568) +) +(connector + (text "CLK_VIDEO" (rect 1162 560 1225 571)(font "Arial" )) + (pt 1248 576) + (pt 1264 576) +) +(connector + (text "MAIN_CLK" (rect 1202 592 1259 603)(font "Arial" )) + (pt 1264 608) + (pt 1192 608) +) (junction (pt 2504 760)) (junction (pt 400 248)) (junction (pt 1856 -64)) From fb3fcdf996251d79bb1b0e7fe4b1055360ef5a56 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 16:23:52 +0000 Subject: [PATCH 016/127] add false paths to design constraints --- .../FalconIO_SDCard_IDE_CF.vhd | 429 +++---- .../WF_UART6850_IP/wf6850ip_top_soc.vhd | 4 +- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 128 +- FPGA_Quartus_13.1/Video/Video.bdf | 1044 ++++++++--------- FPGA_Quartus_13.1/altpll3.bsf | 210 ++-- FPGA_Quartus_13.1/altpll3.cmp | 50 +- FPGA_Quartus_13.1/altpll3.inc | 52 +- FPGA_Quartus_13.1/altpll3.ppf | 24 +- FPGA_Quartus_13.1/altpll3.qip | 14 +- FPGA_Quartus_13.1/altpll3.vhd | 890 +++++++------- FPGA_Quartus_13.1/firebee1.qsf | 897 +++++++------- FPGA_Quartus_13.1/firebee1.sdc | 5 +- 12 files changed, 1883 insertions(+), 1864 deletions(-) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index f0c67ac..d05719b 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -37,109 +37,109 @@ ENTITY falconio_sdcard_ide_cf IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - CLK33M : IN std_logic; - MAIN_CLK : IN std_logic; - CLK2M : IN std_logic; - CLK500k : IN std_logic; - nFB_CS1 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - LP_BUSY : IN std_logic; - nACSI_DRQ : IN std_logic; - nACSI_INT : IN std_logic; - nSCSI_DRQ : IN std_logic; - nSCSI_MSG : IN std_logic; - MIDI_IN : IN std_logic; - RxD : IN std_logic; - CTS : IN std_logic; - RI : IN std_logic; - DCD : IN std_logic; - AMKB_RX : IN std_logic; - PIC_AMKB_RX : IN std_logic; - IDE_RDY : IN std_logic; - IDE_INT : IN std_logic; - WP_CS_CARD : IN std_logic; - nINDEX : IN std_logic; - TRACK00 : IN std_logic; - nRD_DATA : IN std_logic; - nDCHG : IN std_logic; - SD_DATA0 : IN std_logic; - SD_DATA1 : IN std_logic; - SD_DATA2 : IN std_logic; - SD_CARD_DEDECT : IN std_logic; - SD_WP : IN std_logic; - nDACK0 : IN std_logic; - nFB_WR : INOUT std_logic; - WP_CF_CARD : IN std_logic; - nWP : IN std_logic; - nFB_CS2 : IN std_logic; - nRSTO : IN std_logic; - HD_DD : IN std_logic; - nSCSI_C_D : IN std_logic; - nSCSI_I_O : IN std_logic; - CLK2M4576 : IN std_logic; - nFB_OE : IN std_logic; - VSYNC : IN std_logic; - HSYNC : IN std_logic; - DSP_INT : IN std_logic; - nBLANK : IN std_logic; - FDC_CLK : IN std_logic; - FB_ALE : IN std_logic; - ACP_CONF : IN std_logic_vector(31 DOWNTO 24); - nIDE_CS1 : OUT std_logic; - nIDE_CS0 : OUT std_logic; - LP_STR : OUT std_logic; - LP_DIR : OUT std_logic; - nACSI_ACK : OUT std_logic; - nACSI_RESET : OUT std_logic; - nACSI_CS : OUT std_logic; - ACSI_DIR : OUT std_logic; - ACSI_A1 : OUT std_logic; - nSCSI_ACK : OUT std_logic; - nSCSI_ATN : OUT std_logic; - SCSI_DIR : OUT std_logic; - SD_CLK : OUT std_logic; - YM_QA : OUT std_logic; - YM_QC : OUT std_logic; - YM_QB : OUT std_logic; - nSDSEL : OUT std_logic; - STEP : OUT std_logic; - MOT_ON : OUT std_logic; - nRP_LDS : OUT std_logic; - nRP_UDS : OUT std_logic; - nROM4 : OUT std_logic; - nROM3 : OUT std_logic; - nCF_CS1 : OUT std_logic; - nCF_CS0 : OUT std_logic; - nIDE_RD : INOUT std_logic; - nIDE_WR : INOUT std_logic; - AMKB_TX : OUT std_logic; - IDE_RES : OUT std_logic; - DTR : OUT std_logic; - RTS : OUT std_logic; - TxD : OUT std_logic; - MIDI_OLR : OUT std_logic; - MIDI_TLR : OUT std_logic; - nDREQ0 : OUT std_logic; - DSA_D : OUT std_logic; - nMFP_INT : OUT std_logic; - FALCON_IO_TA : OUT std_logic; - STEP_DIR : OUT std_logic; - WR_DATA : OUT std_logic; - WR_GATE : OUT std_logic; - DMA_DRQ : OUT std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - LP_D : INOUT std_logic_vector(7 DOWNTO 0); - ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); - SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); - SCSI_PAR : INOUT std_logic; - nSCSI_SEL : INOUT std_logic; - nSCSI_BUSY : INOUT std_logic; - nSCSI_RST : INOUT std_logic; - SD_CD_DATA3 : INOUT std_logic; - SD_CDM_D1 : INOUT std_logic + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + CLK2M : IN std_logic; + CLK500k : IN std_logic; + nFB_CS1 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + nSCSI_DRQ : IN std_logic; + nSCSI_MSG : IN std_logic; + MIDI_IN : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CS_CARD : IN std_logic; + nINDEX : IN std_logic; + TRACK00 : IN std_logic; + nRD_DATA : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + SD_WP : IN std_logic; + nDACK0 : IN std_logic; + nFB_WR : INOUT std_logic; + WP_CF_CARD : IN std_logic; + nWP : IN std_logic; + nFB_CS2 : IN std_logic; + nRSTO : IN std_logic; + HD_DD : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + CLK2M4576 : IN std_logic; + nFB_OE : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DSP_INT : IN std_logic; + nBLANK : IN std_logic; + FDC_CLK : IN std_logic; + FB_ALE : IN std_logic; + ACP_CONF : IN std_logic_vector(31 DOWNTO 24); + nIDE_CS1 : OUT std_logic; + nIDE_CS0 : OUT std_logic; + LP_STR : OUT std_logic; + LP_DIR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + SD_CLK : OUT std_logic; + YM_QA : OUT std_logic; + YM_QC : OUT std_logic; + YM_QB : OUT std_logic; + nSDSEL : OUT std_logic; + STEP : OUT std_logic; + MOT_ON : OUT std_logic; + nRP_LDS : OUT std_logic; + nRP_UDS : OUT std_logic; + nROM4 : OUT std_logic; + nROM3 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nCF_CS0 : OUT std_logic; + nIDE_RD : INOUT std_logic; + nIDE_WR : INOUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + DTR : OUT std_logic; + RTS : OUT std_logic; + TxD : OUT std_logic; + MIDI_OLR : OUT std_logic; + MIDI_TLR : OUT std_logic; + nDREQ0 : OUT std_logic; + DSA_D : OUT std_logic; + nMFP_INT : OUT std_logic; + FALCON_IO_TA : OUT std_logic; + STEP_DIR : OUT std_logic; + WR_DATA : OUT std_logic; + WR_GATE : OUT std_logic; + DMA_DRQ : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_PAR : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CDM_D1 : INOUT std_logic ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! @@ -228,7 +228,9 @@ END falconio_sdcard_ide_cf; SIGNAL WRF_RDE : std_logic; SIGNAL WRF_WRE : std_logic; SIGNAL nFDC_WR : std_logic; - type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); + + TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); + SIGNAL FCF_STATE : FCF_STATES; SIGNAL NEXT_FCF_STATE : FCF_STATES; SIGNAL DMA_REQ : std_logic; @@ -239,6 +241,7 @@ END falconio_sdcard_ide_cf; SIGNAL DMA_ACTIV : std_logic; SIGNAL DMA_ACTIV_NEW : std_logic; SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0); + -- SCSI SIGNAL SCSI_CS : std_logic; SIGNAL SCSI_CSn : std_logic; @@ -256,6 +259,7 @@ END falconio_sdcard_ide_cf; SIGNAL BSY_EN : std_logic; SIGNAL SEL_OUTn : std_logic; SIGNAL SEL_EN : std_logic; + -- IDE SIGNAL nnIDE_RES : std_logic; SIGNAL IDE_CF_CS : std_logic; @@ -268,25 +272,28 @@ END falconio_sdcard_ide_cf; BEGIN - LONG <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '0' ELSE '0'; - BYT <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '1' ELSE '0'; - FB_B0 <= '1' WHEN FB_ADR(0) = '0' or BYT = '0' ELSE '0'; - FB_B1 <= '1' WHEN FB_ADR(0) = '1' or BYT = '0' ELSE '0'; + LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0'; + BYT <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; + FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0'; + FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0'; - FALCON_IO_TA <= '1' WHEN SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' - or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' ELSE '0'; - SUB_BUS <= '1' WHEN nFB_WR = '1' and ROM_CS = '1' ELSE - '1' WHEN nFB_WR = '1' and IDE_CF_CS = '1' ELSE - '1' WHEN nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; - nRP_UDS <= '0' WHEN SUB_BUS = '1' and FB_B0 = '1' ELSE '1'; - nRP_LDS <= '0' WHEN SUB_BUS = '1' and FB_B1 = '1' ELSE '1'; + FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1' + OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0'; + + SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE + '1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE + '1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0'; + nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1'; + nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1'; nDREQ0 <= '0'; + ---------------------------------------------------------------------------- -- SD ---------------------------------------------------------------------------- SD_CLK <= 'Z'; SD_CD_DATA3 <= 'Z'; SD_CDM_D1 <= 'Z'; + ---------------------------------------------------------------------------- -- IDE ---------------------------------------------------------------------------- @@ -344,16 +351,21 @@ BEGIN END CASE; END PROCESS CMD_DECODER; - IDE_RES <= not nnIDE_RES and nRSTO; - IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 - nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F - '0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F - nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F - '0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F - nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F - '0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F - nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F - '0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F + IDE_RES <= NOT nnIDE_RES AND nRSTO; + IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 + + nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F + '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F + + nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F + '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F + + nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F + '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F + + nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F + '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F + ----------------------------------------------------------------------------------------------------------------------------------------- -- ACSI, SCSI UND FLOPPY WD1772 ------------------------------------------------------------------------------------------------------------------------------------------- @@ -368,12 +380,15 @@ BEGIN wrreq => RDF_WRE, q => RDF_DOUT, wrusedw => RDF_AZ - ); - FCF_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"0020110" and LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY - FCF_APH <= '1' WHEN FB_ALE = '1' and FB_AD(31 DOWNTO 0) = x"F0020110" and LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY - RDF_RDE <= '1' WHEN FCF_APH = '1' and nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE - FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + ); + + FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY + FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY + RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE + + FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; + -- daten write fifo WRF: dcfifo1 PORT MAP( @@ -385,11 +400,11 @@ BEGIN wrreq => WRF_WRE, q => WRF_DOUT, rdusedw => WRF_AZ - ); + ); - CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB - DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG - FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB + DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG + FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; -- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- @@ -398,7 +413,7 @@ BEGIN IF nRSTO = '0' THEN WRF_WRE <= '0'; ELSIF rising_edge(MAIN_CLK) THEN - IF FCF_APH = '1' and nFB_WR = '0' THEN + IF FCF_APH = '1' AND nFB_WR = '0' THEN WRF_WRE <= '1'; ELSE WRF_WRE <= '0'; @@ -426,27 +441,27 @@ BEGIN BEGIN IF nRSTO = '0' THEN FDC_OUT <= x"00"; - ELSIF rising_edge(FDC_CLK) and FDCS_In = '0' THEN + ELSIF rising_edge(FDC_CLK) AND FDCS_In = '0' THEN FDC_OUT <= CD_OUT_FDC; -- set ELSE FDC_OUT <= FDC_OUT; -- halten END IF; END PROCESS FDC_REG; - DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' ELSE '0'; - FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and FB_B1 = '1' ELSE '0'; - SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and FB_B1 = '1' ELSE '0'; + DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' AND DMA_MODUS(7) = '1') OR (SCSI_DRQ = '1' AND DMA_MODUS(7) = '0')) AND DMA_STATUS(1) = '1' AND DMA_MODUS(6) = '0' AND CLR_FIFO = '0' ELSE '0'; + FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND FB_B1 = '1' ELSE '0'; + SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND FB_B1 = '1' ELSE '0'; FCF_DECODER: PROCESS(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) BEGIN - case FCF_STATE is + CASE FCF_STATE IS WHEN FCF_IDLE => SCSI_CSn <= '1'; FDCS_In <= '1'; RDF_WRE <= '0'; WRF_RDE <= '0'; nSCSI_DACK <= '1'; - IF DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' THEN + IF DMA_REQ = '1' OR FDC_CS = '1' OR SCSI_CS = '1' THEN DMA_ACTIV_NEW <= DMA_REQ; NEXT_FCF_STATE <= FCF_T0; ELSE @@ -459,8 +474,8 @@ BEGIN RDF_WRE <= '0'; nSCSI_DACK <= '1'; DMA_ACTIV_NEW <= DMA_REQ; - WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO - IF DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? + WRF_RDE <= DMA_MODUS(8) AND DMA_REQ; -- WRITE -> READ FROM FIFO + IF DMA_REQ = '0' AND DMA_ACTIV = '1' THEN -- spike? NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start ELSE NEXT_FCF_STATE <= FCF_T1; @@ -469,33 +484,33 @@ BEGIN RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; NEXT_FCF_STATE <= FCF_T2; WHEN FCF_T2 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; NEXT_FCF_STATE <= FCF_T3; WHEN FCF_T3 => RDF_WRE <= '0'; WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; NEXT_FCF_STATE <= FCF_T6; WHEN FCF_T6 => WRF_RDE <= '0'; DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO + SCSI_CSn <= NOT SCSI_CS; + FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3); + nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV; + RDF_WRE <= NOT DMA_MODUS(8) AND DMA_ACTIV; -- READ -> WRITE IN FIFO NEXT_FCF_STATE <= FCF_T7; WHEN FCF_T7 => SCSI_CSn <= '1'; @@ -504,7 +519,7 @@ BEGIN WRF_RDE <= '0'; nSCSI_DACK <= '1'; DMA_ACTIV_NEW <= '0'; - IF FDC_CS = '1' and DMA_REQ = '0' THEN + IF FDC_CS = '1' AND DMA_REQ = '0' THEN NEXT_FCF_STATE <= FCF_T7; ELSE NEXT_FCF_STATE <= FCF_IDLE; @@ -538,22 +553,22 @@ BEGIN INTRQ => FDINT ); - DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 - DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 - WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 + DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 + DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 + WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); - nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR; + nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR; CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0); CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); - FB_AD(23 DOWNTO 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and nFB_OE = '0' ELSE - SCSI_DOUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and nFB_OE = '0' ELSE - DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE + SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE + DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); --- WDC BSL REGISTER ------------------------------------------------------- @@ -561,7 +576,7 @@ BEGIN BEGIN IF nRSTO = '0' THEN WDC_BSL <= "00"; - ELSIF rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' THEN + ELSIF rising_edge(MAIN_CLK) AND WDC_BSL_CS = '1' AND nFB_WR = '0' THEN IF FB_B0 = '1' THEN WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); ELSE @@ -575,7 +590,7 @@ BEGIN BEGIN IF nRSTO = '0' THEN DMA_MODUS <= x"0000"; - ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' THEN + ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '1' AND nFB_WR = '0' THEN IF FB_B0 = '1' THEN DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24); ELSE @@ -594,13 +609,13 @@ BEGIN -- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) BEGIN - IF nRSTO = '0' or CLR_FIFO = '1' THEN + IF nRSTO = '0' OR CLR_FIFO = '1' THEN DMA_BYT_CNT <= x"00000000"; - ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' THEN + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z'); DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z'); - ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' THEN + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN DMA_BYT_CNT <= FB_AD; ELSE DMA_BYT_CNT <= DMA_BYT_CNT; @@ -610,11 +625,11 @@ BEGIN FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); DMA_STATUS(0) <= '1'; -- DMA OK - DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS - DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' or SCSI_DRQ = '1' ELSE '0'; - DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' ELSE - '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' ELSE '0'; - DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; + DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS + DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0'; + DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE + '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0'; + DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0'; -- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG) @@ -634,7 +649,7 @@ BEGIN BEGIN IF nRSTO = '0' THEN DMA_TOP <= x"00"; - ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') THEN + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_TOP_CS = '1' OR DMA_ADR_CS = '1') THEN DMA_TOP <= FB_AD(31 DOWNTO 24); ELSE DMA_TOP <= DMA_TOP; @@ -645,7 +660,7 @@ BEGIN BEGIN IF nRSTO = '0' THEN DMA_HIGH <= x"00"; - ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') THEN + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_HIGH_CS = '1' OR DMA_ADR_CS = '1') THEN DMA_HIGH <= FB_AD(23 DOWNTO 16); ELSE DMA_HIGH <= DMA_HIGH; @@ -657,7 +672,7 @@ BEGIN DMA_MID <= DMA_MID; IF nRSTO = '0' THEN DMA_MID <= x"00"; - ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN IF DMA_MID_CS = '1' THEN DMA_MID <= FB_AD(23 DOWNTO 16); ELSIF DMA_ADR_CS = '1' THEN @@ -671,7 +686,7 @@ BEGIN DMA_LOW <= DMA_LOW; IF nRSTO = '0' THEN DMA_LOW <= x"00"; - ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN + ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN IF DMA_LOW_CS = '1'THEN DMA_LOW <= FB_AD(23 DOWNTO 16); ELSIF DMA_ADR_CS = '1' THEN @@ -681,23 +696,23 @@ BEGIN END PROCESS; -------------------------------------------------------------------------------------------- - DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B0 = '1' ELSE '0'; -- F8608/2 - DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B1 = '1' ELSE '0'; -- F8609/2 - DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C305" and FB_B1 = '1' ELSE '0'; -- F860B/2 - DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C306" and FB_B1 = '1' ELSE '0'; -- F860D/2 + DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 + DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 + DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 + DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 - FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); -- DIRECTZUGRIFF - DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD - DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG - DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG + DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD + DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG + DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG - FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); -- DMA RW TOGGLE ------------------------------------------ @@ -706,14 +721,14 @@ BEGIN BEGIN IF nRSTO = '0' THEN DMA_DIR_OLD <= '0'; - ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' THEN + ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '0' THEN DMA_DIR_OLD <= DMA_MODUS(8); ELSE DMA_DIR_OLD <= DMA_DIR_OLD; END IF; END PROCESS; - CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; + CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; -- SCSI ---------------------------------------------------------------------------------- I_SCSI: WF5380_TOP_SOC @@ -892,8 +907,8 @@ BEGIN CLK => MAIN_CLK, RESETn => nRSTO, -- Asynchronous bus control: - DSn => not LDS, - CSn => not MFP_CS, + DSn => NOT LDS, + CSn => NOT MFP_CS, RWn => nFB_WR, DTACKn => DTACK_OUT_MFPn, -- Data and Adresses: @@ -901,18 +916,18 @@ BEGIN DATA_IN => FB_AD(23 DOWNTO 16), DATA_OUT => DATA_OUT_MFP, -- DATA_EN => DATA_EN_MFP, - GPIP_IN(7) => not DMA_DRQ_Q, - GPIP_IN(6) => not RI, + GPIP_IN(7) => NOT DMA_DRQ_Q, + GPIP_IN(6) => NOT RI, GPIP_IN(5) => DINTn, GPIP_IN(4) => IRQ_ACIAn, GPIP_IN(3) => DSP_INT, - GPIP_IN(2) => not CTS, - GPIP_IN(1) => not DCD, + GPIP_IN(2) => NOT CTS, + GPIP_IN(1) => NOT DCD, GPIP_IN(0) => LP_BUSY, -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. -- GPIP_EN =>, -- Not used; all GPIPs are direction input. -- Interrupt control: - IACKn => not MFP_INTACK, + IACKn => NOT MFP_INTACK, IEIn => '0', -- IEOn =>, -- Not used. IRQn => nMFP_INT, @@ -999,10 +1014,10 @@ BEGIN OUT_C => YM_QC ); - SNDCS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 - SNDCS_I <= '1' WHEN SNDCS = '1' and FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; - SNDIR_I <= '1' WHEN SNDCS = '1' and nFB_WR = '0' ELSE '0'; - FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); + SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 + SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; + SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0'; + FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z'); LP_DIR <= LP_DIR_X; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd index cbca6bd..bb806d6 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -60,8 +60,8 @@ -- library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; + use ieee.std_logic_1164.all; + use ieee.std_logic_unsigned.all; entity WF6850IP_TOP_SOC is port ( diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 40b2fe6..078cd89 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -11,55 +11,55 @@ INCLUDE "lpm_bustri_BYT.inc"; SUBDESIGN video_mod_mux_clutctr ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nFB_BURST : INPUT; - FB_ADR[31..0] : INPUT; - CLK33M : INPUT; - CLK25M : INPUT; - BLITTER_RUN : INPUT; - CLK_VIDEO : INPUT; - VR_D[8..0] : INPUT; - VR_BUSY : INPUT; - COLOR8 : OUTPUT; - ACP_CLUT_RD : OUTPUT; - COLOR1 : OUTPUT; - FALCON_CLUT_RDH : OUTPUT; - FALCON_CLUT_RDL : OUTPUT; - FALCON_CLUT_WR[3..0] : OUTPUT; - ST_CLUT_RD : OUTPUT; - ST_CLUT_WR[1..0] : OUTPUT; - CLUT_MUX_ADR[3..0] : OUTPUT; - HSYNC : OUTPUT; - VSYNC : OUTPUT; - nBLANK : OUTPUT; - nSYNC : OUTPUT; - nPD_VGA : OUTPUT; - FIFO_RDE : OUTPUT; - COLOR2 : OUTPUT; - COLOR4 : OUTPUT; - PIXEL_CLK : OUTPUT; - CLUT_OFF[3..0] : OUTPUT; - BLITTER_ON : OUTPUT; - VIDEO_RAM_CTR[15..0] : OUTPUT; - VIDEO_MOD_TA : OUTPUT; - CCR[23..0] : OUTPUT; - CCSEL[2..0] : OUTPUT; - ACP_CLUT_WR[3..0] : OUTPUT; - INTER_ZEI : OUTPUT; - DOP_FIFO_CLR : OUTPUT; - VIDEO_RECONFIG : OUTPUT; - VR_WR : OUTPUT; - VR_RD : OUTPUT; - CLR_FIFO : OUTPUT; - FB_AD[31..0] : BIDIR; + nRSTO : INPUT; + MAIN_CLK : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_WR : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nFB_BURST : INPUT; + FB_ADR[31..0] : INPUT; + CLK33M : INPUT; + CLK25M : INPUT; + BLITTER_RUN : INPUT; + CLK_VIDEO : INPUT; + VR_D[8..0] : INPUT; + VR_BUSY : INPUT; + COLOR8 : OUTPUT; + ACP_CLUT_RD : OUTPUT; + COLOR1 : OUTPUT; + FALCON_CLUT_RDH : OUTPUT; + FALCON_CLUT_RDL : OUTPUT; + FALCON_CLUT_WR[3..0] : OUTPUT; + ST_CLUT_RD : OUTPUT; + ST_CLUT_WR[1..0] : OUTPUT; + CLUT_MUX_ADR[3..0] : OUTPUT; + HSYNC : OUTPUT; + VSYNC : OUTPUT; + nBLANK : OUTPUT; + nSYNC : OUTPUT; + nPD_VGA : OUTPUT; + FIFO_RDE : OUTPUT; + COLOR2 : OUTPUT; + COLOR4 : OUTPUT; + PIXEL_CLK : OUTPUT; + CLUT_OFF[3..0] : OUTPUT; + BLITTER_ON : OUTPUT; + VIDEO_RAM_CTR[15..0] : OUTPUT; + VIDEO_MOD_TA : OUTPUT; + CCR[23..0] : OUTPUT; + CCSEL[2..0] : OUTPUT; + ACP_CLUT_WR[3..0] : OUTPUT; + INTER_ZEI : OUTPUT; + DOP_FIFO_CLR : OUTPUT; + VIDEO_RECONFIG : OUTPUT; + VR_WR : OUTPUT; + VR_RD : OUTPUT; + CLR_FIFO : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) @@ -195,23 +195,23 @@ VARIABLE BEGIN -- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + FB_B0 = FB_ADR[1..0] == 0; -- ADR==0 + FB_B1 = FB_ADR[1..0] == 1 -- ADR==1 # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + FB_B2 = FB_ADR[1..0] == 2 -- ADR==2 # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE -- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- ADR==1 + FB_16B0 = FB_ADR[0] == 0; -- ADR==0 + FB_16B1 = FB_ADR[0] == 1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT -- ACP CLUT -- - ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 + ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; @@ -220,7 +220,7 @@ BEGIN --FALCON CLUT -- - FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 + FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; @@ -228,25 +228,25 @@ BEGIN -- ST CLUT -- - ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 + ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; - ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 + ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 ST_SHIFT_MODE[] = FB_AD[25..24]; ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO - COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN - COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN + COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN + COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; - FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 + FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE[] = FB_AD[26..16]; FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; @@ -274,7 +274,7 @@ BEGIN -- 25=RANDFARBE EINSCHALTEN, -- 26=STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; - ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 + ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; ACP_VCTR[5..0] = FB_AD[5..0]; ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; diff --git a/FPGA_Quartus_13.1/Video/Video.bdf b/FPGA_Quartus_13.1/Video/Video.bdf index 1b1821e..265ea14 100644 --- a/FPGA_Quartus_13.1/Video/Video.bdf +++ b/FPGA_Quartus_13.1/Video/Video.bdf @@ -6758,322 +6758,6 @@ applicable agreement for further details. (line (pt 168 96)(pt 184 96)(line_width 3)) ) ) -(block - (rect 296 1872 560 2536) - (text "DDR_CTR" (rect 5 5 66 18)(font "Arial" (font_size 8))) (text "i_ddr_ctr" (rect 5 650 51 661)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nFB_OE" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nRSTO" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "FB_ALE" (input)) - (block_io "nFB_WR" (input)) - (block_io "DDR_SYNC_66M" (input)) - (block_io "VIDEO_RAM_CTR[15..0]" (input)) - (block_io "BLITTER_ADR[31..0]" (input)) - (block_io "BLITTER_SIG" (input)) - (block_io "BLITTER_WR" (input)) - (block_io "DDRCLK0" (input)) - (block_io "CLK33M" (input)) - (block_io "FIFO_MW[8..0]" (input)) - (block_io "CLR_FIFO" (input)) - (block_io "VA[12..0]" (output)) - (block_io "nVWE" (output)) - (block_io "nVRAS" (output)) - (block_io "nVCS" (output)) - (block_io "VCKE" (output)) - (block_io "nVCAS" (output)) - (block_io "FB_LE[3..0]" (output)) - (block_io "FB_VDOE[3..0]" (output)) - (block_io "SR_FIFO_WRE" (output)) - (block_io "SR_DDR_FB" (output)) - (block_io "SR_DDR_WR" (output)) - (block_io "SR_DDRWR_D_SEL" (output)) - (block_io "SR_VDMP[7..0]" (output)) - (block_io "VIDEO_DDR_TA" (output)) - (block_io "SR_BLITTER_DACK" (output)) - (block_io "BA[1..0]" (output)) - (block_io "DDRWR_D_SEL1" (output)) - (block_io "VDM_SEL[3..0]" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (mapper - (pt 264 560) - (bidir) - ) - (mapper - (pt 264 48) - (bidir) - ) - (mapper - (pt 0 208) - (bidir) - ) - (mapper - (pt 0 256) - (bidir) - ) - (mapper - (pt 0 304) - (bidir) - ) - (mapper - (pt 264 312) - (bidir) - ) - (mapper - (pt 264 264) - (bidir) - ) - (mapper - (pt 264 536) - (bidir) - ) - (mapper - (pt 264 360) - (bidir) - ) - (mapper - (pt 264 384) - (bidir) - ) - (mapper - (pt 264 408) - (bidir) - ) - (mapper - (pt 264 432) - (bidir) - ) - (mapper - (pt 0 88) - (bidir) - ) - (mapper - (pt 0 160) - (bidir) - ) - (mapper - (pt 264 120) - (bidir) - ) - (mapper - (pt 264 144) - (bidir) - ) - (mapper - (pt 0 112) - (bidir) - ) - (mapper - (pt 0 360) - (bidir) - ) - (mapper - (pt 0 136) - (bidir) - ) - (mapper - (pt 0 40) - (bidir) - ) - (mapper - (pt 0 384) - (bidir) - ) - (mapper - (pt 0 432) - (bidir) - ) - (mapper - (pt 0 456) - (bidir) - ) - (mapper - (pt 0 480) - (bidir) - ) - (mapper - (pt 264 216) - (bidir) - ) - (mapper - (pt 264 456) - (bidir) - ) - (mapper - (pt 264 168) - (bidir) - ) - (mapper - (pt 264 480) - (bidir) - ) - (mapper - (pt 264 504) - (bidir) - ) - (mapper - (pt 0 64) - (bidir) - ) - (mapper - (pt 264 632) - (bidir) - ) - (mapper - (pt 264 608) - (bidir) - ) - (mapper - (pt 0 576) - (bidir) - ) - (mapper - (pt 0 520) - (bidir) - ) - (mapper - (pt 0 184) - (bidir) - ) - (mapper - (pt 0 232) - (bidir) - ) - (mapper - (pt 0 280) - (bidir) - ) - (mapper - (pt 0 328) - (bidir) - ) - (mapper - (pt 264 336) - (bidir) - ) -) -(block - (rect 296 2552 568 3000) - (text "BLITTER" (rect 5 5 58 18)(font "Arial" (font_size 8))) (text "i_blitter" (rect 5 434 42 445)(font "Arial" )) (block_io "nRSTO" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "FB_ALE" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_OE" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "VIDEO_RAM_CTR[15..0]" (input)) - (block_io "BLITTER_ON" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nFB_CS3" (input)) - (block_io "DDRCLK0" (input)) - (block_io "BLITTER_DIN[127..0]" (input)) - (block_io "BLITTER_DACK[4..0]" (input)) - (block_io "BLITTER_RUN" (output)) - (block_io "BLITTER_DOUT[127..0]" (output)) - (block_io "BLITTER_ADR[31..0]" (output)) - (block_io "BLITTER_SIG" (output)) - (block_io "BLITTER_WR" (output)) - (block_io "BLITTER_TA" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (mapper - (pt 272 176) - (bidir) - ) - (mapper - (pt 272 208) - (bidir) - ) - (mapper - (pt 272 240) - (bidir) - ) - (mapper - (pt 272 264) - (bidir) - ) - (mapper - (pt 272 288) - (bidir) - ) - (mapper - (pt 0 384) - (bidir) - ) - (mapper - (pt 272 72) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 32) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 360) - (bidir) - ) - (mapper - (pt 0 328) - (bidir) - ) - (mapper - (pt 272 424) - (bidir) - ) - (mapper - (pt 0 408) - (bidir) - ) -) (block (rect 1664 1656 2016 2592) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 183 18)(font "Arial" (font_size 8))) (text "i_video_mod_mux_clutctr" (rect 5 922 132 933)(font "Arial" )) (block_io "nRSTO" (input)) @@ -7322,6 +7006,322 @@ applicable agreement for further details. (bidir) ) ) +(block + (rect 296 1880 560 2544) + (text "ddr_ctr" (rect 5 5 46 18)(font "Arial" (font_size 8))) (text "i_ddr_ctr" (rect 5 650 51 661)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nFB_CS3" (input)) + (block_io "nFB_OE" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nRSTO" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "FB_ALE" (input)) + (block_io "nFB_WR" (input)) + (block_io "DDR_SYNC_66M" (input)) + (block_io "VIDEO_RAM_CTR[15..0]" (input)) + (block_io "BLITTER_ADR[31..0]" (input)) + (block_io "BLITTER_SIG" (input)) + (block_io "BLITTER_WR" (input)) + (block_io "DDRCLK0" (input)) + (block_io "CLK33M" (input)) + (block_io "FIFO_MW[8..0]" (input)) + (block_io "CLR_FIFO" (input)) + (block_io "VA[12..0]" (output)) + (block_io "nVWE" (output)) + (block_io "nVRAS" (output)) + (block_io "nVCS" (output)) + (block_io "VCKE" (output)) + (block_io "nVCAS" (output)) + (block_io "FB_LE[3..0]" (output)) + (block_io "FB_VDOE[3..0]" (output)) + (block_io "SR_FIFO_WRE" (output)) + (block_io "SR_DDR_FB" (output)) + (block_io "SR_DDR_WR" (output)) + (block_io "SR_DDRWR_D_SEL" (output)) + (block_io "SR_VDMP[7..0]" (output)) + (block_io "VIDEO_DDR_TA" (output)) + (block_io "SR_BLITTER_DACK" (output)) + (block_io "BA[1..0]" (output)) + (block_io "DDRWR_D_SEL1" (output)) + (block_io "VDM_SEL[3..0]" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (mapper + (pt 264 560) + (bidir) + ) + (mapper + (pt 264 48) + (bidir) + ) + (mapper + (pt 0 208) + (bidir) + ) + (mapper + (pt 0 256) + (bidir) + ) + (mapper + (pt 0 304) + (bidir) + ) + (mapper + (pt 264 312) + (bidir) + ) + (mapper + (pt 264 264) + (bidir) + ) + (mapper + (pt 264 536) + (bidir) + ) + (mapper + (pt 264 360) + (bidir) + ) + (mapper + (pt 264 384) + (bidir) + ) + (mapper + (pt 264 408) + (bidir) + ) + (mapper + (pt 264 432) + (bidir) + ) + (mapper + (pt 0 88) + (bidir) + ) + (mapper + (pt 0 160) + (bidir) + ) + (mapper + (pt 264 120) + (bidir) + ) + (mapper + (pt 264 144) + (bidir) + ) + (mapper + (pt 0 112) + (bidir) + ) + (mapper + (pt 0 360) + (bidir) + ) + (mapper + (pt 0 136) + (bidir) + ) + (mapper + (pt 0 40) + (bidir) + ) + (mapper + (pt 0 384) + (bidir) + ) + (mapper + (pt 0 432) + (bidir) + ) + (mapper + (pt 0 456) + (bidir) + ) + (mapper + (pt 0 480) + (bidir) + ) + (mapper + (pt 264 216) + (bidir) + ) + (mapper + (pt 264 456) + (bidir) + ) + (mapper + (pt 264 168) + (bidir) + ) + (mapper + (pt 264 480) + (bidir) + ) + (mapper + (pt 264 504) + (bidir) + ) + (mapper + (pt 0 64) + (bidir) + ) + (mapper + (pt 264 632) + (bidir) + ) + (mapper + (pt 264 608) + (bidir) + ) + (mapper + (pt 0 576) + (bidir) + ) + (mapper + (pt 0 520) + (bidir) + ) + (mapper + (pt 0 184) + (bidir) + ) + (mapper + (pt 0 232) + (bidir) + ) + (mapper + (pt 0 280) + (bidir) + ) + (mapper + (pt 0 328) + (bidir) + ) + (mapper + (pt 264 336) + (bidir) + ) +) +(block + (rect 296 2552 568 3000) + (text "blitter" (rect 5 5 38 18)(font "Arial" (font_size 8))) (text "i_blitter" (rect 5 434 42 445)(font "Arial" )) (block_io "nRSTO" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "FB_ALE" (input)) + (block_io "nFB_WR" (input)) + (block_io "nFB_OE" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "VIDEO_RAM_CTR[15..0]" (input)) + (block_io "BLITTER_ON" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nFB_CS3" (input)) + (block_io "DDRCLK0" (input)) + (block_io "BLITTER_DIN[127..0]" (input)) + (block_io "BLITTER_DACK[4..0]" (input)) + (block_io "BLITTER_RUN" (output)) + (block_io "BLITTER_DOUT[127..0]" (output)) + (block_io "BLITTER_ADR[31..0]" (output)) + (block_io "BLITTER_SIG" (output)) + (block_io "BLITTER_WR" (output)) + (block_io "BLITTER_TA" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (mapper + (pt 272 176) + (bidir) + ) + (mapper + (pt 272 208) + (bidir) + ) + (mapper + (pt 272 240) + (bidir) + ) + (mapper + (pt 272 264) + (bidir) + ) + (mapper + (pt 272 288) + (bidir) + ) + (mapper + (pt 0 384) + (bidir) + ) + (mapper + (pt 272 72) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 32) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 360) + (bidir) + ) + (mapper + (pt 0 328) + (bidir) + ) + (mapper + (pt 272 424) + (bidir) + ) + (mapper + (pt 0 408) + (bidir) + ) +) (connector (text "CLUT_ADR0" (rect 2786 1272 2852 1283)(font "Arial" )) (pt 2776 1288) @@ -8020,122 +8020,6 @@ applicable agreement for further details. (pt 2904 2896) (bus) ) -(connector - (text "FB_AD[31..0]" (rect 570 1904 636 1915)(font "Arial" )) - (pt 680 1920) - (pt 560 1920) - (bus) -) -(connector - (text "nFB_CS1" (rect 202 2040 250 2051)(font "Arial" )) - (pt 192 2056) - (pt 296 2056) -) -(connector - (text "nFB_CS2" (rect 202 2064 251 2075)(font "Arial" )) - (pt 192 2080) - (pt 296 2080) -) -(connector - (text "nFB_CS3" (rect 202 2088 251 2099)(font "Arial" )) - (pt 192 2104) - (pt 296 2104) -) -(connector - (text "nFB_WR" (rect 202 2112 248 2123)(font "Arial" )) - (pt 192 2128) - (pt 296 2128) -) -(connector - (text "FB_SIZE0" (rect 202 2136 253 2147)(font "Arial" )) - (pt 192 2152) - (pt 296 2152) -) -(connector - (text "FB_SIZE1" (rect 202 2160 252 2171)(font "Arial" )) - (pt 192 2176) - (pt 296 2176) -) -(connector - (text "nFB_OE" (rect 202 2184 245 2195)(font "Arial" )) - (pt 192 2200) - (pt 296 2200) -) -(connector - (text "VA[12..0]" (rect 570 2168 616 2179)(font "Arial" )) - (pt 632 2184) - (pt 560 2184) - (bus) -) -(connector - (text "nVWE" (rect 570 2192 603 2203)(font "Arial" )) - (pt 632 2208) - (pt 560 2208) -) -(connector - (text "nVCAS" (rect 570 2216 607 2227)(font "Arial" )) - (pt 632 2232) - (pt 560 2232) -) -(connector - (text "nVRAS" (rect 570 2240 607 2251)(font "Arial" )) - (pt 632 2256) - (pt 560 2256) -) -(connector - (text "nVCS" (rect 570 2264 600 2275)(font "Arial" )) - (pt 632 2280) - (pt 560 2280) -) -(connector - (text "VCKE" (rect 570 2288 601 2299)(font "Arial" )) - (pt 632 2304) - (pt 560 2304) -) -(connector - (text "MAIN_CLK" (rect 202 1944 259 1955)(font "Arial" )) - (pt 296 1960) - (pt 192 1960) -) -(connector - (text "FB_ALE" (rect 202 2016 244 2027)(font "Arial" )) - (pt 296 2032) - (pt 192 2032) -) -(connector - (text "FB_LE[3..0]" (rect 570 1976 629 1987)(font "Arial" )) - (pt 560 1992) - (pt 680 1992) - (bus) -) -(connector - (text "FB_VDOE[3..0]" (rect 570 2000 646 2011)(font "Arial" )) - (pt 560 2016) - (pt 680 2016) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 210 1968 299 1979)(font "Arial" )) - (pt 200 1984) - (pt 296 1984) -) -(connector - (text "FB_ADR[31..0]" (rect 202 1992 276 2003)(font "Arial" )) - (pt 192 2008) - (pt 296 2008) - (bus) -) -(connector - (text "nRSTO" (rect 202 1896 240 1907)(font "Arial" )) - (pt 192 1912) - (pt 296 1912) -) -(connector - (text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 303 2251)(font "Arial" )) - (pt 296 2256) - (pt 168 2256) - (bus) -) (connector (pt 792 1648) (pt 920 1648) @@ -8316,53 +8200,11 @@ applicable agreement for further details. (pt 1160 1672) (bus) ) -(connector - (text "BLITTER_ADR[31..0]" (rect 194 2288 300 2299)(font "Arial" )) - (pt 184 2304) - (pt 296 2304) - (bus) -) -(connector - (text "BLITTER_SIG" (rect 194 2312 265 2323)(font "Arial" )) - (pt 184 2328) - (pt 296 2328) -) -(connector - (text "BLITTER_WR" (rect 194 2336 265 2347)(font "Arial" )) - (pt 184 2352) - (pt 296 2352) -) -(connector - (text "SR_FIFO_WRE" (rect 570 2072 650 2083)(font "Arial" )) - (pt 648 2088) - (pt 560 2088) -) -(connector - (text "SR_DDR_FB" (rect 570 2312 637 2323)(font "Arial" )) - (pt 640 2328) - (pt 560 2328) -) (connector (text "SR_FIFO_WRE" (rect 842 2280 922 2291)(font "Arial" )) (pt 920 2296) (pt 832 2296) ) -(connector - (text "SR_DDR_WR" (rect 570 2024 641 2035)(font "Arial" )) - (pt 664 2040) - (pt 560 2040) -) -(connector - (text "SR_VDMP[7..0]" (rect 570 2336 647 2347)(font "Arial" )) - (pt 560 2352) - (pt 664 2352) - (bus) -) -(connector - (text "SR_DDRWR_D_SEL" (rect 570 2360 676 2371)(font "Arial" )) - (pt 560 2376) - (pt 664 2376) -) (connector (text "BLITTER_ON" (rect 226 2920 294 2931)(font "Arial" )) (pt 296 2936) @@ -8510,16 +8352,6 @@ applicable agreement for further details. (pt 296 2608) (pt 184 2608) ) -(connector - (text "DDRCLK0" (rect 194 1920 247 1931)(font "Arial" )) - (pt 296 1936) - (pt 184 1936) -) -(connector - (text "VIDEO_DDR_TA" (rect 570 2488 657 2499)(font "Arial" )) - (pt 560 2504) - (pt 664 2504) -) (connector (text "BLITTER_TA" (rect 578 2960 646 2971)(font "Arial" )) (pt 568 2976) @@ -8630,11 +8462,6 @@ applicable agreement for further details. (pt 184 2960) (bus) ) -(connector - (text "SR_BLITTER_DACK" (rect 570 2464 676 2475)(font "Arial" )) - (pt 664 2480) - (pt 560 2480) -) (connector (text "DDRCLK0" (rect 1114 1528 1167 1539)(font "Arial" )) (pt 1104 1544) @@ -8677,11 +8504,6 @@ applicable agreement for further details. (pt 296 2880) (bus) ) -(connector - (text "CLK33M" (rect 218 2432 262 2443)(font "Arial" )) - (pt 208 2448) - (pt 296 2448) -) (connector (text "FIFO_D[127..0]" (rect 2170 1416 2246 1427)(font "Arial" )) (pt 2168 1432) @@ -8909,12 +8731,6 @@ applicable agreement for further details. (pt 1304 2688) (bus) ) -(connector - (text "BA[1..0]" (rect 570 2120 610 2131)(font "Arial" )) - (pt 632 2136) - (pt 560 2136) - (bus) -) (connector (text "DDRWR_D_SEL0" (rect 1066 2768 1156 2779)(font "Arial" )) (pt 1056 2784) @@ -8936,11 +8752,6 @@ applicable agreement for further details. (pt 888 2784) (pt 992 2784) ) -(connector - (text "DDRWR_D_SEL1" (rect 570 2392 659 2403)(font "Arial" )) - (pt 656 2408) - (pt 560 2408) -) (connector (text "VDOUT_OE" (rect 1386 2328 1448 2339)(font "Arial" )) (pt 1376 2344) @@ -9400,12 +9211,6 @@ applicable agreement for further details. (pt 3112 2960) (pt 3192 2960) ) -(connector - (text "FIFO_MW[8..0]" (rect 194 2376 269 2387)(font "Arial" )) - (pt 296 2392) - (pt 184 2392) - (bus) -) (connector (text "MAIN_CLK" (rect 3370 2208 3427 2219)(font "Arial" )) (pt 3448 2224) @@ -10188,12 +9993,6 @@ applicable agreement for further details. (pt 2040 976) (bus) ) -(connector - (text "VDM_SEL[3..0]" (rect 570 2416 646 2427)(font "Arial" )) - (pt 560 2432) - (pt 656 2432) - (bus) -) (connector (text "VDMB[127..0]" (rect 1586 1080 1654 1091)(font "Arial" )) (pt 1576 1096) @@ -10359,11 +10158,6 @@ applicable agreement for further details. (pt 264 1832) (pt 360 1832) ) -(connector - (text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" )) - (pt 296 2232) - (pt 192 2232) -) (connector (text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" )) (pt 1712 1472) @@ -10691,6 +10485,212 @@ applicable agreement for further details. (pt 2016 1760) (pt 2112 1760) ) +(connector + (text "FB_AD[31..0]" (rect 570 1912 636 1923)(font "Arial" )) + (pt 680 1928) + (pt 560 1928) + (bus) +) +(connector + (text "nFB_CS1" (rect 202 2048 250 2059)(font "Arial" )) + (pt 192 2064) + (pt 296 2064) +) +(connector + (text "nFB_CS2" (rect 202 2072 251 2083)(font "Arial" )) + (pt 192 2088) + (pt 296 2088) +) +(connector + (text "nFB_CS3" (rect 202 2096 251 2107)(font "Arial" )) + (pt 192 2112) + (pt 296 2112) +) +(connector + (text "nFB_WR" (rect 202 2120 248 2131)(font "Arial" )) + (pt 192 2136) + (pt 296 2136) +) +(connector + (text "FB_SIZE0" (rect 202 2144 253 2155)(font "Arial" )) + (pt 192 2160) + (pt 296 2160) +) +(connector + (text "FB_SIZE1" (rect 202 2168 252 2179)(font "Arial" )) + (pt 192 2184) + (pt 296 2184) +) +(connector + (text "nFB_OE" (rect 202 2192 245 2203)(font "Arial" )) + (pt 192 2208) + (pt 296 2208) +) +(connector + (text "VA[12..0]" (rect 570 2176 616 2187)(font "Arial" )) + (pt 632 2192) + (pt 560 2192) + (bus) +) +(connector + (text "nVWE" (rect 570 2200 603 2211)(font "Arial" )) + (pt 632 2216) + (pt 560 2216) +) +(connector + (text "nVCAS" (rect 570 2224 607 2235)(font "Arial" )) + (pt 632 2240) + (pt 560 2240) +) +(connector + (text "nVRAS" (rect 570 2248 607 2259)(font "Arial" )) + (pt 632 2264) + (pt 560 2264) +) +(connector + (text "nVCS" (rect 570 2272 600 2283)(font "Arial" )) + (pt 632 2288) + (pt 560 2288) +) +(connector + (text "VCKE" (rect 570 2296 601 2307)(font "Arial" )) + (pt 632 2312) + (pt 560 2312) +) +(connector + (text "MAIN_CLK" (rect 202 1952 259 1963)(font "Arial" )) + (pt 296 1968) + (pt 192 1968) +) +(connector + (text "FB_ALE" (rect 202 2024 244 2035)(font "Arial" )) + (pt 296 2040) + (pt 192 2040) +) +(connector + (text "FB_LE[3..0]" (rect 570 1984 629 1995)(font "Arial" )) + (pt 560 2000) + (pt 680 2000) + (bus) +) +(connector + (text "FB_VDOE[3..0]" (rect 570 2008 646 2019)(font "Arial" )) + (pt 560 2024) + (pt 680 2024) + (bus) +) +(connector + (text "DDR_SYNC_66M" (rect 210 1976 299 1987)(font "Arial" )) + (pt 200 1992) + (pt 296 1992) +) +(connector + (text "FB_ADR[31..0]" (rect 202 2000 276 2011)(font "Arial" )) + (pt 192 2016) + (pt 296 2016) + (bus) +) +(connector + (text "nRSTO" (rect 202 1904 240 1915)(font "Arial" )) + (pt 192 1920) + (pt 296 1920) +) +(connector + (text "VIDEO_RAM_CTR[15..0]" (rect 178 2248 303 2259)(font "Arial" )) + (pt 296 2264) + (pt 168 2264) + (bus) +) +(connector + (text "BLITTER_ADR[31..0]" (rect 194 2296 300 2307)(font "Arial" )) + (pt 184 2312) + (pt 296 2312) + (bus) +) +(connector + (text "BLITTER_SIG" (rect 194 2320 265 2331)(font "Arial" )) + (pt 184 2336) + (pt 296 2336) +) +(connector + (text "BLITTER_WR" (rect 194 2344 265 2355)(font "Arial" )) + (pt 184 2360) + (pt 296 2360) +) +(connector + (text "SR_FIFO_WRE" (rect 570 2080 650 2091)(font "Arial" )) + (pt 648 2096) + (pt 560 2096) +) +(connector + (text "SR_DDR_FB" (rect 570 2320 637 2331)(font "Arial" )) + (pt 640 2336) + (pt 560 2336) +) +(connector + (text "SR_DDR_WR" (rect 570 2032 641 2043)(font "Arial" )) + (pt 664 2048) + (pt 560 2048) +) +(connector + (text "SR_VDMP[7..0]" (rect 570 2344 647 2355)(font "Arial" )) + (pt 560 2360) + (pt 664 2360) + (bus) +) +(connector + (text "SR_DDRWR_D_SEL" (rect 570 2368 676 2379)(font "Arial" )) + (pt 560 2384) + (pt 664 2384) +) +(connector + (text "DDRCLK0" (rect 194 1928 247 1939)(font "Arial" )) + (pt 296 1944) + (pt 184 1944) +) +(connector + (text "VIDEO_DDR_TA" (rect 570 2496 657 2507)(font "Arial" )) + (pt 560 2512) + (pt 664 2512) +) +(connector + (text "SR_BLITTER_DACK" (rect 570 2472 676 2483)(font "Arial" )) + (pt 664 2488) + (pt 560 2488) +) +(connector + (text "CLK33M" (rect 218 2440 262 2451)(font "Arial" )) + (pt 208 2456) + (pt 296 2456) +) +(connector + (text "BA[1..0]" (rect 570 2128 610 2139)(font "Arial" )) + (pt 632 2144) + (pt 560 2144) + (bus) +) +(connector + (text "DDRWR_D_SEL1" (rect 570 2400 659 2411)(font "Arial" )) + (pt 656 2416) + (pt 560 2416) +) +(connector + (text "FIFO_MW[8..0]" (rect 194 2384 269 2395)(font "Arial" )) + (pt 296 2400) + (pt 184 2400) + (bus) +) +(connector + (text "VDM_SEL[3..0]" (rect 570 2424 646 2435)(font "Arial" )) + (pt 560 2440) + (pt 656 2440) + (bus) +) +(connector + (text "CLR_FIFO" (rect 202 2224 257 2235)(font "Arial" )) + (pt 296 2240) + (pt 192 2240) +) (junction (pt 2984 1688)) (junction (pt 792 1192)) (junction (pt 792 1312)) diff --git a/FPGA_Quartus_13.1/altpll3.bsf b/FPGA_Quartus_13.1/altpll3.bsf index da30b0c..75fabaa 100644 --- a/FPGA_Quartus_13.1/altpll3.bsf +++ b/FPGA_Quartus_13.1/altpll3.bsf @@ -1,105 +1,105 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 304 232) - (text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 213 31 228)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 304 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) - (line (pt 304 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 304 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) - (line (pt 304 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 304 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) - (line (pt 304 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 304 144) - (output) - (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) - (line (pt 304 144)(pt 272 144)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 229 214 277 228)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) - (text "Clk " (rect 59 111 76 125)(font "Arial" )) - (text "Ratio" (rect 86 111 110 125)(font "Arial" )) - (text "Ph (dg)" (rect 121 111 156 125)(font "Arial" )) - (text "DC (%)" (rect 166 111 201 125)(font "Arial" )) - (text "c0" (rect 63 129 75 143)(font "Arial" )) - (text "2/33" (rect 88 129 109 143)(font "Arial" )) - (text "0.00" (rect 129 129 150 143)(font "Arial" )) - (text "50.00" (rect 171 129 198 143)(font "Arial" )) - (text "c1" (rect 63 147 75 161)(font "Arial" )) - (text "16/33" (rect 85 147 112 161)(font "Arial" )) - (text "0.00" (rect 129 147 150 161)(font "Arial" )) - (text "50.00" (rect 171 147 198 161)(font "Arial" )) - (text "c2" (rect 63 165 75 179)(font "Arial" )) - (text "25/33" (rect 85 165 112 179)(font "Arial" )) - (text "0.00" (rect 129 165 150 179)(font "Arial" )) - (text "50.00" (rect 171 165 198 179)(font "Arial" )) - (text "c3" (rect 63 183 75 197)(font "Arial" )) - (text "16/11" (rect 85 183 112 197)(font "Arial" )) - (text "0.00" (rect 129 183 150 197)(font "Arial" )) - (text "50.00" (rect 171 183 198 197)(font "Arial" )) - (line (pt 0 0)(pt 305 0)(line_width 1)) - (line (pt 305 0)(pt 305 233)(line_width 1)) - (line (pt 0 233)(pt 305 233)(line_width 1)) - (line (pt 0 0)(pt 0 233)(line_width 1)) - (line (pt 56 108)(pt 208 108)(line_width 1)) - (line (pt 56 125)(pt 208 125)(line_width 1)) - (line (pt 56 143)(pt 208 143)(line_width 1)) - (line (pt 56 161)(pt 208 161)(line_width 1)) - (line (pt 56 179)(pt 208 179)(line_width 1)) - (line (pt 56 197)(pt 208 197)(line_width 1)) - (line (pt 56 108)(pt 56 197)(line_width 1)) - (line (pt 82 108)(pt 82 197)(line_width 3)) - (line (pt 118 108)(pt 118 197)(line_width 3)) - (line (pt 163 108)(pt 163 197)(line_width 3)) - (line (pt 207 108)(pt 207 197)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 216)(line_width 1)) - (line (pt 48 216)(pt 272 216)(line_width 1)) - (line (pt 48 56)(pt 48 216)(line_width 1)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2014 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 256 184) + (text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 169 26 180)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 256 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + ) + (port + (pt 256 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) + ) + (port + (pt 256 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8))) + ) + (port + (pt 256 112) + (output) + (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone III" (rect 198 170 442 350)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) + (text "Clk " (rect 51 91 117 192)(font "Arial" )) + (text "Ratio" (rect 77 91 177 192)(font "Arial" )) + (text "Ph (dg)" (rect 109 91 249 192)(font "Arial" )) + (text "DC (%)" (rect 144 91 320 192)(font "Arial" )) + (text "c0" (rect 54 104 119 218)(font "Arial" )) + (text "2/33" (rect 79 104 177 218)(font "Arial" )) + (text "0.00" (rect 115 104 249 218)(font "Arial" )) + (text "50.00" (rect 148 104 320 218)(font "Arial" )) + (text "c1" (rect 54 117 118 244)(font "Arial" )) + (text "16/33" (rect 77 117 177 244)(font "Arial" )) + (text "0.00" (rect 115 117 249 244)(font "Arial" )) + (text "50.00" (rect 148 117 320 244)(font "Arial" )) + (text "c2" (rect 54 130 119 270)(font "Arial" )) + (text "109/144" (rect 71 130 175 270)(font "Arial" )) + (text "0.00" (rect 115 130 249 270)(font "Arial" )) + (text "50.00" (rect 148 130 320 270)(font "Arial" )) + (text "c3" (rect 54 143 119 296)(font "Arial" )) + (text "16/11" (rect 77 143 176 296)(font "Arial" )) + (text "0.00" (rect 115 143 249 296)(font "Arial" )) + (text "50.00" (rect 148 143 320 296)(font "Arial" )) + (line (pt 0 0)(pt 257 0)) + (line (pt 257 0)(pt 257 185)) + (line (pt 0 185)(pt 257 185)) + (line (pt 0 0)(pt 0 185)) + (line (pt 48 89)(pt 176 89)) + (line (pt 48 101)(pt 176 101)) + (line (pt 48 114)(pt 176 114)) + (line (pt 48 127)(pt 176 127)) + (line (pt 48 140)(pt 176 140)) + (line (pt 48 153)(pt 176 153)) + (line (pt 48 89)(pt 48 153)) + (line (pt 68 89)(pt 68 153)(line_width 3)) + (line (pt 106 89)(pt 106 153)(line_width 3)) + (line (pt 141 89)(pt 141 153)(line_width 3)) + (line (pt 175 89)(pt 175 153)) + (line (pt 40 48)(pt 223 48)) + (line (pt 223 48)(pt 223 167)) + (line (pt 40 167)(pt 223 167)) + (line (pt 40 48)(pt 40 167)) + (line (pt 255 64)(pt 223 64)) + (line (pt 255 80)(pt 223 80)) + (line (pt 255 96)(pt 223 96)) + (line (pt 255 112)(pt 223 112)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll3.cmp b/FPGA_Quartus_13.1/altpll3.cmp index 44b3f2e..233616a 100644 --- a/FPGA_Quartus_13.1/altpll3.cmp +++ b/FPGA_Quartus_13.1/altpll3.cmp @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altpll3 - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll3 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll3.inc b/FPGA_Quartus_13.1/altpll3.inc index 160ecad..66f8ef8 100644 --- a/FPGA_Quartus_13.1/altpll3.inc +++ b/FPGA_Quartus_13.1/altpll3.inc @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altpll3 -( - inclk0 -) - -RETURNS ( - c0, - c1, - c2, - c3 -); +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll3 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3 +); diff --git a/FPGA_Quartus_13.1/altpll3.ppf b/FPGA_Quartus_13.1/altpll3.ppf index 2a7b695..c840c97 100644 --- a/FPGA_Quartus_13.1/altpll3.ppf +++ b/FPGA_Quartus_13.1/altpll3.ppf @@ -1,12 +1,12 @@ - - - - - - - - - - - - + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll3.qip b/FPGA_Quartus_13.1/altpll3.qip index 8dd2955..0b0f8f4 100644 --- a/FPGA_Quartus_13.1/altpll3.qip +++ b/FPGA_Quartus_13.1/altpll3.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"] diff --git a/FPGA_Quartus_13.1/altpll3.vhd b/FPGA_Quartus_13.1/altpll3.vhd index 6ead1f5..8d19aba 100644 --- a/FPGA_Quartus_13.1/altpll3.vhd +++ b/FPGA_Quartus_13.1/altpll3.vhd @@ -1,445 +1,445 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: altpll3.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY altpll3 IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC - ); -END altpll3; - - -ARCHITECTURE SYN OF altpll3 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(3); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - c3 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 33, - clk0_duty_cycle => 50, - clk0_multiply_by => 2, - clk0_phase_shift => "0", - clk1_divide_by => 33, - clk1_duty_cycle => 50, - clk1_multiply_by => 16, - clk1_phase_shift => "0", - clk2_divide_by => 33, - clk2_duty_cycle => 50, - clk2_multiply_by => 25, - clk2_phase_shift => "0", - clk3_divide_by => 11, - clk3_duty_cycle => 50, - clk3_multiply_by => 16, - clk3_phase_shift => "0", - compensate_clock => "CLK1", - inclk0_input_frequency => 30303, - intended_device_family => "Cyclone III", - lpm_type => "altpll", - operation_mode => "SOURCE_SYNCHRONOUS", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll3.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll3 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC + ); +END altpll3; + + +ARCHITECTURE SYN OF altpll3 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 33, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + clk1_divide_by => 33, + clk1_duty_cycle => 50, + clk1_multiply_by => 16, + clk1_phase_shift => "0", + clk2_divide_by => 144, + clk2_duty_cycle => 50, + clk2_multiply_by => 109, + clk2_phase_shift => "0", + clk3_divide_by => 11, + clk3_duty_cycle => 50, + clk3_multiply_by => 16, + clk3_phase_shift => "0", + compensate_clock => "CLK1", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "144" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.979166" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "144" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "109" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index efe0772..522c2fc 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,394 +39,394 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== -set_location_assignment PIN_AB12 -to CLK33M -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_E12 -to MIDI_IN -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_AB12 -to CLK33M +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_E12 -to MIDI_IN +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -436,7 +436,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -446,21 +446,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -470,85 +470,85 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- # LogicLock Region Assignments # ============================ -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # end LOGICLOCK_REGION(Root Region) # --------------------------------- @@ -558,17 +558,17 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(firebee1) # -------------------- -set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL @@ -742,4 +742,5 @@ set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index b0d03b1..7e9fe9a 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -19,7 +19,7 @@ ## PROGRAM "Quartus II" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" -## DATE "Sun Sep 20 14:58:25 2015" +## DATE "Sun Sep 20 18:14:49 2015" ## ## DEVICE "EP3C40F484C6" @@ -88,11 +88,14 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clock_ set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] +set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] +set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|nBLANK}] -to [get_keepers {falconio_sdcard_ide_cf:i_falcon_io_sdcard_ide_cf|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]}] #************************************************************** From bb0f702a45e8a61bfefe32fb0085fe834a604edb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 17:13:10 +0000 Subject: [PATCH 017/127] reformatted, forced tighter timing Config works, but screen is still scrambled --- FPGA_Quartus_13.1/DSP/DSP.vhd | 76 ++++++----- .../FalconIO_SDCard_IDE_CF.vhd | 12 +- .../Interrupt_Handler/interrupt_handler.tdf | 123 ++++++++++-------- FPGA_Quartus_13.1/firebee1.qsf | 8 +- FPGA_Quartus_13.1/firebee1.sdc | 11 +- 5 files changed, 125 insertions(+), 105 deletions(-) diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 5dc95de..22ae2ee 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -1,18 +1,18 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text +-- WARNING: Do NOT edit the input AND output ports in this file in a text -- editor if you plan to continue editing the block that represents it in -- the Block Editor! File corruption is VERY likely to occur. -- Copyright (C) 1991-2008 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any +-- AND other software AND tools, AND its AMPP partner logic +-- functions, AND any output files from any of the foregoing +-- (including device programming or simulation files), AND any -- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License +-- to the terms AND conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by +-- programming logic devices manufactured by Altera AND sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. @@ -30,28 +30,28 @@ ENTITY dsp IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nRSTO : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nSRCS : INOUT STD_LOGIC; - nSRBLE : OUT STD_LOGIC; - nSRBHE : OUT STD_LOGIC; - nSRWE : OUT STD_LOGIC; - nSROE : OUT STD_LOGIC; - DSP_INT : OUT STD_LOGIC; - DSP_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - IO : INOUT STD_LOGIC_VECTOR(17 downto 0); - SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_OE : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nRSTO : IN std_logic; + nFB_CS3 : IN std_logic; + nSRCS : INOUT std_logic; + nSRBLE : OUT std_logic; + nSRBHE : OUT std_logic; + nSRWE : OUT std_logic; + nSROE : OUT std_logic; + DSP_INT : OUT std_logic; + DSP_TA : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + IO : INOUT std_logic_vector(17 DOWNTO 0); + SRD : INOUT std_logic_vector(15 DOWNTO 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! @@ -60,20 +60,18 @@ END dsp; -- Architecture Body -ARCHITECTURE rtl OF DSP IS +ARCHITECTURE rtl OF dsp IS BEGIN - nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; - nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; - nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; - nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; - nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; + nSRCS <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1'; --nFB_CS3; + nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1'; + nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; + nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1'; + nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1'; DSP_INT <= '0'; DSP_TA <= '0'; - IO(17 downto 0) <= FB_ADR(18 downto 1); - SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - - + IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); + SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index d05719b..523161b 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -20,12 +20,12 @@ -- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) -- Created on Tue Sep 08 16:24:20 2009 -library work; -use work.FalconIO_SDCard_IDE_CF_pkg.all; +LIBRARY work; + USE work.FalconIO_SDCard_IDE_CF_pkg.ALL; -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; -- Entity Declaration @@ -148,7 +148,7 @@ END falconio_sdcard_ide_cf; -- Architecture Body - ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS +ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS -- system SIGNAL SYS_CLK : std_logic; SIGNAL RESETn : std_logic; diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf index 5131b0f..b569002 100644 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -17,64 +17,64 @@ INCLUDE "lpm_bustri_BYT.inc"; SUBDESIGN interrupt_handler ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - MAIN_CLK : INPUT; - nFB_WR : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - FB_ADR[31..0] : INPUT; - PIC_INT : INPUT; - E0_INT : INPUT; - DVI_INT : INPUT; - nPCI_INTA : INPUT; - nPCI_INTB : INPUT; - nPCI_INTC : INPUT; - nPCI_INTD : INPUT; - nMFP_INT : INPUT; - nFB_OE : INPUT; - DSP_INT : INPUT; - VSYNC : INPUT; - HSYNC : INPUT; - DMA_DRQ : INPUT; - nIRQ[7..2] : OUTPUT; - INT_HANDLER_TA : OUTPUT; - ACP_CONF[31..0] : OUTPUT; - TIN0 : OUTPUT; - FB_AD[31..0] : BIDIR; + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) VARIABLE - FB_B[3..0] :NODE; - INT_CTR[31..0] :DFFE; - INT_CTR_CS :NODE; - INT_LATCH[31..0] :DFF; - INT_LATCH_CS :NODE; - INT_CLEAR[31..0] :DFF; - INT_CLEAR_CS :NODE; - INT_IN[31..0] :NODE; - INT_ENA[31..0] :DFFE; - INT_ENA_CS :NODE; - ACP_CONF[31..0] :DFFE; - ACP_CONF_CS :NODE; - PSEUDO_BUS_ERROR :NODE; - UHR_AS :NODE; - UHR_DS :NODE; - RTC_ADR[5..0] :DFFE; - ACHTELSEKUNDEN[2..0] :DFFE; - WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 - PIC_INT_SYNC[2..0] :DFF; - INC_SEC :NODE; - INC_MIN :NODE; - INC_STD :NODE; - INC_TAG :NODE; + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; ANZAHL_TAGE_DES_MONATS[7..0]:NODE; - WINTERZEIT :NODE; - SOMMERZEIT :NODE; - INC_MONAT :NODE; - INC_JAHR :NODE; - UPDATE_ON :NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; BEGIN -- BYT SELECT @@ -99,6 +99,7 @@ BEGIN INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; + -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA[].CLK = MAIN_CLK; INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 @@ -107,6 +108,7 @@ BEGIN INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; + -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 @@ -114,8 +116,10 @@ BEGIN INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; + -- INTERRUPT LATCH REGISTER READ ONLY INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 + -- INTERRUPT !nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ3 = INT_CTR0 & INT_ENA[27]; @@ -139,6 +143,7 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..4]==H"F890" -- DMA SOUND # FB_ADR[19..4]==H"F891" -- DMA SOUND # FB_ADR[19..4]==H"F892"); -- DMA SOUND + -- IF VIDEO ADR CHANGE TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 @@ -176,6 +181,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN30 = !nMFP_INT; INT_IN31 = DMA_DRQ; + --*************************************************************************************** -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE ACP_CONF[].CLK = MAIN_CLK; @@ -337,28 +343,34 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG + -- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER + -- ACHTELSEKUNDEN ACHTELSEKUNDEN[].CLK = MAIN_CLK; ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; + -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); + -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- + -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER @@ -370,15 +382,18 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- + -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); + -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); + -- TRISTATE OUTPUT FB_AD[31..24] = lpm_bustri_BYT( @@ -460,6 +475,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[23..16] # ACP_CONF_CS & ACP_CONF[23..16] ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[15..8] # INT_ENA_CS & INT_ENA[15..8] @@ -467,6 +483,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[15..8] # ACP_CONF_CS & ACP_CONF[15..8] ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[7..0] # INT_ENA_CS & INT_ENA[7..0] diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 522c2fc..6f21306 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -372,9 +372,9 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK @@ -743,4 +743,6 @@ set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE altddio_out3.qip set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 7e9fe9a..c1b6396 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -19,7 +19,7 @@ ## PROGRAM "Quartus II" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" -## DATE "Sun Sep 20 18:14:49 2015" +## DATE "Sun Sep 20 18:51:37 2015" ## ## DEVICE "EP3C40F484C6" @@ -58,8 +58,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.050 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.050 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.080 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.080 #************************************************************** @@ -90,6 +90,8 @@ set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_genera set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] @@ -103,7 +105,8 @@ set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_m #************************************************************** set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8 -set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2 +set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] 4 +#set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2 set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8 From 5d4920f8496026d26e9b9c838f25e457d012cf7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 18:08:31 +0000 Subject: [PATCH 018/127] upgrade lpm components --- FPGA_Quartus_13.1/firebee1.bdf | 1710 ++++++++++++++++++-------------- FPGA_Quartus_13.1/firebee1.sdc | 4 +- 2 files changed, 975 insertions(+), 739 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index 966f327..d4dc2f5 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -25,82 +25,82 @@ applicable agreement for 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(line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2120 576 2192 656)) + (annotation_block (location)(rect 2120 576 2192 592)) ) (pin (output) @@ -1653,11 +1653,11 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 2432 2112 2576)) + (annotation_block (location)(rect 2008 2432 2064 2448)) ) (pin (output) - (rect 864 24 1040 40) + (rect 776 0 952 16) (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "CLK25M" (rect 90 0 134 11)(font "Arial" )) (pt 0 8) @@ -1670,7 +1670,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 1040 40 1096 56)) + (annotation_block (location)(rect 952 16 1008 32)) ) (pin (output) @@ -1772,7 +1772,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 792 2424 856 2440)) + (annotation_block (location)(rect 792 2424 848 2440)) ) (pin (output) @@ -1789,7 +1789,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 784 2144 848 2176)) + (annotation_block (location)(rect 784 2144 848 2160)) ) (pin (output) @@ -1806,7 +1806,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3392 2064 3408)) + (annotation_block (location)(rect 2000 3392 2056 3408)) ) (pin (output) @@ -1823,7 +1823,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2120 456 2184 488)) + (annotation_block (location)(rect 2120 456 2184 472)) ) (pin (output) @@ -1857,7 +1857,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 896 2960 928)) + (annotation_block (location)(rect 2888 896 2960 912)) ) (pin (output) @@ -1874,7 +1874,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2712 768 2784 800)) + (annotation_block (location)(rect 2712 768 2784 784)) ) (pin (output) @@ -1891,7 +1891,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 480 2080 528)) + (annotation_block (location)(rect 2008 480 2072 496)) ) (pin (output) @@ -1908,7 +1908,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 -56 2400 -24)) + (annotation_block (location)(rect 2312 -56 2376 -40)) ) (pin (output) @@ -1925,7 +1925,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 -72 2976 -40)) + (annotation_block (location)(rect 2888 -72 2952 -56)) ) (pin (output) @@ -1942,11 +1942,11 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 48 2976 80)) + (annotation_block (location)(rect 2888 48 2952 64)) ) (pin (output) - (rect 2712 160 2891 176) + (rect 2712 160 2888 176) (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "PIXEL_CLK_PAD" (rect 90 0 179 11)(font "Arial" )) (pt 0 8) @@ -1959,7 +1959,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 176 2976 208)) + (annotation_block (location)(rect 2888 176 2952 192)) ) (pin (output) @@ -1976,7 +1976,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 232 2112 264)) + (annotation_block (location)(rect 2008 232 2072 248)) ) (pin (output) @@ -2044,7 +2044,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 1000 64 1056 80)) + (annotation_block (location)(rect 1016 64 1072 80)) ) (pin (output) @@ -2061,7 +2061,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 864 2064 880)) + (annotation_block (location)(rect 2008 872 2064 888)) ) (pin (bidir) @@ -2079,7 +2079,7 @@ applicable agreement for further details. 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(line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2080 904 2144 1032)) + (annotation_block (location)(rect 2080 904 2136 920)) ) (pin (bidir) @@ -2223,13 +2223,13 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2136 824 2200 952)) + (annotation_block (location)(rect 2136 824 2192 840)) ) (pin (bidir) (rect 176 1360 352 1376) - (text "BIDIR" (rect 151 0 178 10)(font "Arial" (font_size 6))) - (text "FB_AD[31..0]" (rect 5 0 71 11)(font "Arial" )) + (text "BIDIR" (rect 148 0 175 10)(font "Arial" (font_size 6))) + (text "FB_AD[31..0]" (rect 20 0 86 11)(font "Arial" )) (pt 176 8) (drawing (line (pt 120 4)(pt 98 4)) @@ -2241,8 +2241,8 @@ applicable agreement for further details. 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(pt 64 40) (output) (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 31 65 42)(font "Courier New" (bold))(invisible)) (line (pt 56 40)(pt 64 40)) ) (drawing @@ -2475,7 +2475,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2514,7 +2514,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2557,7 +2557,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2600,7 +2600,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2643,7 +2643,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2660,12 +2660,12 @@ applicable agreement for further details. (symbol (rect 2368 120 2400 152) (text "GND" (rect 6 8 16 30)(font "Arial" (font_size 6))(vertical)) - (text "inst10" (rect -1 3 10 33)(font "Arial" )(vertical)(invisible)) + (text "inst10" (rect 0 3 11 33)(font "Arial" )(vertical)(invisible)) (port (pt 32 16) (output) (text "1" (rect 18 0 25 11)(font "Courier New" (bold))(invisible)) - (text "1" (rect 20 18 31 25)(font "Courier New" (bold))(vertical)(invisible)) + (text "1" (rect 21 18 32 25)(font "Courier New" (bold))(vertical)(invisible)) (line (pt 24 16)(pt 32 16)) ) (drawing @@ -2706,7 +2706,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2731,7 +2731,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2756,7 +2756,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2781,7 +2781,7 @@ applicable agreement for further details. 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(text "c4" (rect 287 152 302 165)(font "Arial" (font_size 8))) + (text "c4" (rect 287 152 299 165)(font "Arial" (font_size 8))) (line (pt 304 168)(pt 272 168)) ) (drawing @@ -3074,87 +3074,87 @@ applicable agreement for further details. ) ) (symbol - (rect 440 -88 744 144) - (text "altpll3" (rect 132 1 174 17)(font "Arial" (font_size 10))) - (text "i_atari_clk_pll" (rect 8 213 76 224)(font "Arial" )) + (rect 448 -88 704 96) + (text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10))) + (text "i_atari_clk_pll" (rect 8 169 76 180)(font "Arial" )) (port - (pt 0 72) + (pt 0 64) (input) (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)) + (text "inclk0" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) ) (port - (pt 304 72) + (pt 256 64) (output) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 302 69)(font "Arial" (font_size 8))) - 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(text "Operation Mode: Src Sync Comp" (rect 58 84 220 95)(font "Arial" )) - (text "Clk " (rect 59 111 79 122)(font "Arial" )) - (text "Ratio" (rect 86 111 113 122)(font "Arial" )) - (text "Ph (dg)" (rect 121 111 158 122)(font "Arial" )) - (text "DC (%)" (rect 166 111 203 122)(font "Arial" )) - (text "c0" (rect 63 129 75 140)(font "Arial" )) - (text "2/33" (rect 88 129 111 140)(font "Arial" )) - (text "0.00" (rect 129 129 152 140)(font "Arial" )) - (text "50.00" (rect 171 129 200 140)(font "Arial" )) - (text "c1" (rect 63 147 74 158)(font "Arial" )) - (text "16/33" (rect 85 147 114 158)(font "Arial" )) - (text "0.00" (rect 129 147 152 158)(font "Arial" )) - (text "50.00" (rect 171 147 200 158)(font "Arial" )) - (text "c2" (rect 63 165 75 176)(font "Arial" )) - (text "25/33" (rect 85 165 114 176)(font "Arial" )) - (text "0.00" (rect 129 165 152 176)(font "Arial" )) - (text "50.00" (rect 171 165 200 176)(font "Arial" )) - (text "c3" (rect 63 183 75 194)(font "Arial" )) - (text "16/11" (rect 85 183 113 194)(font "Arial" )) - (text "0.00" (rect 129 183 152 194)(font "Arial" )) - (text "50.00" (rect 171 183 200 194)(font "Arial" )) - (line (pt 0 0)(pt 305 0)) - (line (pt 305 0)(pt 305 233)) - (line (pt 0 233)(pt 305 233)) - (line (pt 0 0)(pt 0 233)) - (line (pt 56 108)(pt 208 108)) - (line (pt 56 125)(pt 208 125)) - (line (pt 56 143)(pt 208 143)) - (line (pt 56 161)(pt 208 161)) - (line (pt 56 179)(pt 208 179)) - (line (pt 56 197)(pt 208 197)) - (line (pt 56 108)(pt 56 197)) - (line (pt 82 108)(pt 82 197)(line_width 3)) - (line (pt 118 108)(pt 118 197)(line_width 3)) - (line (pt 163 108)(pt 163 197)(line_width 3)) - (line (pt 207 108)(pt 207 197)) - (line (pt 48 56)(pt 272 56)) - (line (pt 272 56)(pt 272 216)) - (line (pt 48 216)(pt 272 216)) - (line (pt 48 56)(pt 48 216)) + (text "Cyclone III" (rect 198 170 249 181)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 60 196 71)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 72 212 83)(font "Arial" )) + (text "Clk " (rect 51 91 71 102)(font "Arial" )) + (text "Ratio" (rect 77 91 104 102)(font "Arial" )) + (text "Ph (dg)" (rect 109 91 146 102)(font "Arial" )) + (text "DC (%)" (rect 144 91 181 102)(font "Arial" )) + (text "c0" (rect 54 104 66 115)(font "Arial" )) + (text "2/33" (rect 79 104 102 115)(font "Arial" )) + (text "0.00" (rect 115 104 138 115)(font "Arial" )) + (text "50.00" (rect 148 104 177 115)(font "Arial" )) + (text "c1" (rect 54 117 65 128)(font "Arial" )) + (text "16/33" (rect 77 117 106 128)(font "Arial" )) + (text "0.00" (rect 115 117 138 128)(font "Arial" )) + (text "50.00" (rect 148 117 177 128)(font "Arial" )) + (text "c2" (rect 54 130 66 141)(font "Arial" )) + (text "109/144" (rect 71 130 112 141)(font "Arial" )) + (text "0.00" (rect 115 130 138 141)(font "Arial" )) + (text "50.00" (rect 148 130 177 141)(font "Arial" )) + (text "c3" (rect 54 143 66 154)(font "Arial" )) + (text "16/11" (rect 77 143 105 154)(font "Arial" )) + (text "0.00" (rect 115 143 138 154)(font "Arial" )) + (text "50.00" (rect 148 143 177 154)(font "Arial" )) + (line (pt 0 0)(pt 257 0)) + (line (pt 257 0)(pt 257 185)) + (line (pt 0 185)(pt 257 185)) + (line (pt 0 0)(pt 0 185)) + (line (pt 48 89)(pt 176 89)) + (line (pt 48 101)(pt 176 101)) + (line (pt 48 114)(pt 176 114)) + (line (pt 48 127)(pt 176 127)) + (line (pt 48 140)(pt 176 140)) + (line (pt 48 153)(pt 176 153)) + (line (pt 48 89)(pt 48 153)) + (line (pt 68 89)(pt 68 153)(line_width 3)) + (line (pt 106 89)(pt 106 153)(line_width 3)) + (line (pt 141 89)(pt 141 153)(line_width 3)) + (line (pt 175 89)(pt 175 153)) + (line (pt 40 48)(pt 223 48)) + (line (pt 223 48)(pt 223 167)) + (line (pt 40 167)(pt 223 167)) + (line (pt 40 48)(pt 40 167)) + (line (pt 255 64)(pt 223 64)) + (line (pt 255 80)(pt 223 80)) + (line (pt 255 96)(pt 223 96)) + (line (pt 255 112)(pt 223 112)) ) ) (symbol @@ -3172,28 +3172,28 @@ applicable agreement for further details. (pt 328 72) (output) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 311 56 326 69)(font "Arial" (font_size 8))) + (text "c0" (rect 311 56 323 69)(font "Arial" (font_size 8))) (line (pt 328 72)(pt 272 72)) ) (port (pt 328 96) (output) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 311 80 325 93)(font "Arial" (font_size 8))) + (text "c1" (rect 311 80 322 93)(font "Arial" (font_size 8))) (line (pt 328 96)(pt 272 96)) ) (port (pt 328 120) (output) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 311 104 326 117)(font "Arial" (font_size 8))) + (text "c2" (rect 311 104 323 117)(font "Arial" (font_size 8))) (line (pt 328 120)(pt 272 120)) ) (port (pt 328 144) (output) (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) - (text "locked" (rect 287 128 324 141)(font "Arial" (font_size 8))) + (text "locked" (rect 287 128 318 141)(font "Arial" (font_size 8))) (line (pt 328 144)(pt 272 144)) ) (drawing @@ -3321,49 +3321,49 @@ applicable agreement for further details. (pt 216 40) (output) (text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8))) - (text "busy" (rect 169 32 198 45)(font "Arial" (font_size 8))) + (text "busy" (rect 171 32 195 45)(font "Arial" (font_size 8))) (line (pt 216 40)(pt 200 40)) ) (port (pt 216 96) (output) (text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8))) - (text "data_out[8..0]" (rect 117 88 196 101)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 129 88 195 101)(font "Arial" (font_size 8))) (line (pt 216 96)(pt 200 96)(line_width 3)) ) (port (pt 216 152) (output) (text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8))) - (text "pll_scandata" (rect 124 144 195 157)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 135 144 195 157)(font "Arial" (font_size 8))) (line (pt 216 152)(pt 200 152)) ) (port (pt 216 168) (output) (text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8))) - (text "pll_scanclk" (rect 132 160 196 173)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 141 160 195 173)(font "Arial" (font_size 8))) (line (pt 216 168)(pt 200 168)) ) (port (pt 216 200) (output) (text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8))) - (text "pll_scanclkena" (rect 111 192 194 205)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 125 192 195 205)(font "Arial" (font_size 8))) (line (pt 216 200)(pt 200 200)) ) (port (pt 216 216) (output) (text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8))) - (text "pll_configupdate" (rect 104 208 197 221)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 117 208 195 221)(font "Arial" (font_size 8))) (line (pt 216 216)(pt 200 216)) ) (port (pt 216 248) (output) (text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8))) - (text "pll_areset" (rect 141 240 197 253)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 148 240 195 253)(font "Arial" (font_size 8))) (line (pt 216 248)(pt 200 248)) ) (drawing @@ -4417,16 +4417,6 @@ applicable agreement for further details. (pt 1672 1168) (pt 1840 1168) ) -(connector - (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) - (pt 1264 1264) - (pt 1104 1264) -) -(connector - (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) - (pt 1104 1336) - (pt 1264 1336) -) (connector (text "nSCSI_RST" (rect 1682 1176 1743 1187)(font "Arial" )) (pt 1672 1192) @@ -4457,31 +4447,6 @@ applicable agreement for further details. (pt 1672 1376) (pt 1848 1376) ) -(connector - (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) - (pt 1104 1424) - (pt 1264 1424) -) -(connector - (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) - (pt 1104 1448) - (pt 1264 1448) -) -(connector - (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) - (pt 1104 1472) - (pt 1264 1472) -) -(connector - (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) - (pt 1264 1552) - (pt 1104 1552) -) -(connector - (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) - (pt 1104 1576) - (pt 1264 1576) -) (connector (text "IDE_RES" (rect 1682 1424 1730 1435)(font "Arial" )) (pt 1672 1440) @@ -4517,11 +4482,6 @@ applicable agreement for further details. (pt 1672 1584) (pt 1848 1584) ) -(connector - (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) - (pt 1104 1600) - (pt 1264 1600) -) (connector (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) (pt 1672 1864) @@ -4537,26 +4497,6 @@ applicable agreement for further details. (pt 1856 2048) (pt 1672 2048) ) -(connector - (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) - (pt 1104 1784) - (pt 1264 1784) -) -(connector - (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) - (pt 1104 1808) - (pt 1264 1808) -) -(connector - (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) - (pt 1104 1832) - (pt 1264 1832) -) -(connector - (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) - (pt 1104 1880) - (pt 1264 1880) -) (connector (text "FB_ADR[31..0]" (rect 1146 2536 1220 2547)(font "Arial" )) (pt 1112 2552) @@ -4654,56 +4594,6 @@ applicable agreement for further details. (pt 1672 1968) (pt 1928 1968) ) -(connector - (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) - (pt 1264 1176) - (pt 1104 1176) -) -(connector - (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) - (pt 1024 1208) - (pt 1264 1208) -) -(connector - (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) - (pt 1024 1232) - (pt 1264 1232) -) -(connector - (text "MIDI_IN" (rect 1050 1352 1091 1363)(font "Arial" )) - (pt 1040 1368) - (pt 1264 1368) -) -(connector - (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) - (pt 1264 1400) - (pt 1104 1400) -) -(connector - (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) - (pt 1040 1656) - (pt 1264 1656) -) -(connector - (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) - (pt 1040 1680) - (pt 1264 1680) -) -(connector - (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) - (pt 1040 1704) - (pt 1264 1704) -) -(connector - (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) - (pt 1040 1728) - (pt 1264 1728) -) -(connector - (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) - (pt 1040 1752) - (pt 1264 1752) -) (connector (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) (pt 1264 1856) @@ -4719,66 +4609,16 @@ applicable agreement for further details. (pt 1672 2024) (pt 1856 2024) ) -(connector - (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) - (pt 1104 1288) - (pt 1264 1288) -) -(connector - (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) - (pt 1104 1312) - (pt 1264 1312) -) (connector (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) (pt 1672 1720) (pt 1856 1720) ) -(connector - (text "nFB_WR" (rect 1170 928 1216 939)(font "Arial" )) - (pt 1264 944) - (pt 1160 944) -) -(connector - (text "nFB_CS1" (rect 1162 952 1210 963)(font "Arial" )) - (pt 1264 968) - (pt 1160 968) -) -(connector - (text "nFB_CS2" (rect 1170 976 1219 987)(font "Arial" )) - (pt 1264 992) - (pt 1160 992) -) -(connector - (text "FB_SIZE0" (rect 1162 1000 1213 1011)(font "Arial" )) - (pt 1264 1016) - (pt 1160 1016) -) -(connector - (text "FB_SIZE1" (rect 1162 1024 1212 1035)(font "Arial" )) - (pt 1264 1040) - (pt 1160 1040) -) -(connector - (text "nFB_BURST" (rect 1162 1048 1226 1059)(font "Arial" )) - (pt 1264 1064) - (pt 1160 1064) -) -(connector - (text "nDACK0" (rect 1250 1096 1294 1107)(font "Arial" )) - (pt 1264 1112) - (pt 1160 1112) -) (connector (text "nRSTO" (rect 1170 1120 1208 1131)(font "Arial" )) (pt 1264 1136) (pt 1160 1136) ) -(connector - (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) - (pt 1152 2600) - (pt 1264 2600) -) (connector (text "nIRQ[7..2]" (rect 1682 2408 1732 2419)(font "Arial" )) (pt 1672 2424) @@ -4790,41 +4630,11 @@ applicable agreement for further details. (pt 1192 872) (pt 1264 872) ) -(connector - (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) - (pt 1264 920) - (pt 1160 920) -) (connector (text "nFB_OE" (rect 1170 2392 1213 2403)(font "Arial" )) (pt 1264 2408) (pt 1160 2408) ) -(connector - (text "DVI_INT" (rect 1162 2632 1205 2643)(font "Arial" )) - (pt 1152 2648) - (pt 1264 2648) -) -(connector - (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) - (pt 1152 2744) - (pt 1264 2744) -) -(connector - (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) - (pt 1152 2720) - (pt 1264 2720) -) -(connector - (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) - (pt 1152 2696) - (pt 1264 2696) -) -(connector - (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) - (pt 1152 2672) - (pt 1264 2672) -) (connector (text "nMFP_INT" (rect 1162 2760 1217 2771)(font "Arial" )) (pt 1152 2776) @@ -4835,11 +4645,6 @@ applicable agreement for further details. (pt 1672 2088) (pt 1784 2088) ) -(connector - (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) - (pt 1152 2624) - (pt 1264 2624) -) (connector (text "DSP_INT" (rect 1130 2832 1178 2843)(font "Arial" )) (pt 1264 2848) @@ -4850,10 +4655,6 @@ applicable agreement for further details. (pt 472 2056) (pt 544 2056) ) -(connector - (pt 528 2416) - (pt 616 2416) -) (connector (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) (pt 1672 1072) @@ -4872,11 +4673,6 @@ applicable agreement for further details. (pt 1960 816) (bus) ) -(connector - (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) - (pt 776 1496) - (pt 1264 1496) -) (connector (text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" )) (pt 440 2136) @@ -5108,37 +4904,10 @@ applicable agreement for further details. (pt 1672 1408) (pt 2112 1408) ) -(connector - (text "PIC_AMKB_RX" (rect 786 1504 866 1515)(font "Arial" )) - (pt 776 1520) - (pt 1264 1520) -) -(connector - (pt 400 -16) - (pt 440 -16) -) (connector (pt 440 248) (pt 400 248) ) -(connector - (pt 400 -16) - (pt 400 248) -) -(connector - (pt 400 248) - (pt 400 304) -) -(connector - (text "CLK2M" (rect 754 -32 792 -21)(font "Arial" )) - (pt 744 -16) - (pt 816 -16) -) -(connector - (text "FDC_CLK" (rect 754 -8 807 3)(font "Arial" )) - (pt 744 8) - (pt 816 8) -) (connector (text "FB_AD[31..0]" (rect 370 1352 436 1363)(font "Arial" )) (pt 352 1368) @@ -5156,11 +4925,6 @@ applicable agreement for further details. (pt 368 1384) (pt 464 1384) ) -(connector - (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) - (pt 376 1400) - (pt 464 1400) -) (connector (text "ACP_CONF[31..0]" (rect 1682 2568 1772 2579)(font "Arial" )) (pt 1672 2584) @@ -5198,21 +4962,6 @@ applicable agreement for further details. (pt 2424 -80) (pt 2424 -64) ) -(connector - (text "HD_DD" (rect 1050 1616 1090 1627)(font "Arial" )) - (pt 1040 1632) - (pt 1264 1632) -) -(connector - (text "CLK48M" (rect 754 40 798 51)(font "Arial" )) - (pt 744 56) - (pt 840 56) -) -(connector - (text "CLK25M" (rect 754 16 798 27)(font "Arial" )) - (pt 744 32) - (pt 864 32) -) (connector (pt 408 672) (pt 472 672) @@ -5375,11 +5124,6 @@ applicable agreement for further details. (pt 192 568) (bus) ) -(connector - (text "CLK48M" (rect 538 552 582 563)(font "Arial" )) - (pt 528 568) - (pt 608 568) -) (connector (text "CLK500k" (rect 802 232 849 243)(font "Arial" )) (pt 768 248) @@ -5539,11 +5283,6 @@ applicable agreement for further details. (pt 1264 3144) (pt 1160 3144) ) -(connector - (text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" )) - (pt 336 304) - (pt 400 304) -) (connector (text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" )) (pt 1200 776) @@ -5733,10 +5472,6 @@ applicable agreement for further details. (pt 1256 368) (pt 1256 376) ) -(connector - (pt 1176 368) - (pt 1256 368) -) (connector (text "nFB_CS3" (rect 1186 360 1235 371)(font "Arial" )) (pt 1256 376) @@ -5841,11 +5576,6 @@ applicable agreement for further details. (pt 1672 184) (pt 1832 184) ) -(connector - (text "CLK25M" (rect 1202 616 1246 627)(font "Arial" )) - (pt 1192 632) - (pt 1264 632) -) (connector (pt 1776 712) (pt 1776 720) @@ -5954,7 +5684,513 @@ applicable agreement for further details. (pt 1264 608) (pt 1192 608) ) +(connector + (pt 1264 1264) + (pt 1112 1264) +) +(connector + (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) + (pt 1112 1264) + (pt 1104 1264) +) +(connector + (pt 1104 1336) + (pt 1112 1336) +) +(connector + (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) + (pt 1112 1336) + (pt 1264 1336) +) +(connector + (pt 1104 1424) + (pt 1112 1424) +) +(connector + (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) + (pt 1112 1424) + (pt 1264 1424) +) +(connector + (pt 1104 1448) + (pt 1112 1448) +) +(connector + (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) + (pt 1112 1448) + (pt 1264 1448) +) +(connector + (pt 1104 1472) + (pt 1112 1472) +) +(connector + (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) + (pt 1112 1472) + (pt 1264 1472) +) +(connector + (pt 1264 1552) + (pt 1112 1552) +) +(connector + (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) + (pt 1112 1552) + (pt 1104 1552) +) +(connector + (pt 1104 1576) + (pt 1112 1576) +) +(connector + (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) + (pt 1112 1576) + (pt 1264 1576) +) +(connector + (pt 1104 1600) + (pt 1112 1600) +) +(connector + (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) + (pt 1112 1600) + (pt 1264 1600) +) +(connector + (pt 1104 1784) + (pt 1112 1784) +) +(connector + (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) + (pt 1112 1784) + (pt 1264 1784) +) +(connector + (pt 1104 1808) + (pt 1112 1808) +) +(connector + (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) + (pt 1112 1808) + (pt 1264 1808) +) +(connector + (pt 1104 1832) + (pt 1112 1832) +) +(connector + (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) + (pt 1112 1832) + (pt 1264 1832) +) +(connector + (pt 1104 1880) + (pt 1112 1880) +) +(connector + (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) + (pt 1112 1880) + (pt 1264 1880) +) +(connector + (pt 1264 1176) + (pt 1112 1176) +) +(connector + (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) + (pt 1112 1176) + (pt 1104 1176) +) +(connector + (pt 1024 1208) + (pt 1032 1208) +) +(connector + (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) + (pt 1032 1208) + (pt 1264 1208) +) +(connector + (pt 1024 1232) + (pt 1032 1232) +) +(connector + (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) + (pt 1032 1232) + (pt 1264 1232) +) +(connector + (pt 1040 1368) + (pt 1048 1368) +) +(connector + (text "MIDI_IN" (rect 1050 1352 1091 1363)(font "Arial" )) + (pt 1048 1368) + (pt 1264 1368) +) +(connector + (pt 1264 1400) + (pt 1112 1400) +) +(connector + (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) + (pt 1112 1400) + (pt 1104 1400) +) +(connector + (pt 1040 1656) + (pt 1048 1656) +) +(connector + (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) + (pt 1048 1656) + (pt 1264 1656) +) +(connector + (pt 1040 1680) + (pt 1048 1680) +) +(connector + (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) + (pt 1048 1680) + (pt 1264 1680) +) +(connector + (pt 1040 1704) + (pt 1048 1704) +) +(connector + (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) + (pt 1048 1704) + (pt 1264 1704) +) +(connector + (pt 1040 1728) + (pt 1048 1728) +) +(connector + (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) + (pt 1048 1728) + (pt 1264 1728) +) +(connector + (pt 1040 1752) + (pt 1048 1752) +) +(connector + (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) + (pt 1048 1752) + (pt 1264 1752) +) +(connector + (pt 1104 1288) + (pt 1112 1288) +) +(connector + (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) + (pt 1112 1288) + (pt 1264 1288) +) +(connector + (pt 1104 1312) + (pt 1112 1312) +) +(connector + (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) + (pt 1112 1312) + (pt 1264 1312) +) +(connector + (pt 1264 944) + (pt 1168 944) +) +(connector + (text "nFB_WR" (rect 1170 928 1216 939)(font "Arial" )) + (pt 1168 944) + (pt 1160 944) +) +(connector + (pt 1264 968) + (pt 1168 968) +) +(connector + (text "nFB_CS1" (rect 1162 952 1210 963)(font "Arial" )) + (pt 1168 968) + (pt 1160 968) +) +(connector + (pt 1264 992) + (pt 1168 992) +) +(connector + (text "nFB_CS2" (rect 1170 976 1219 987)(font "Arial" )) + (pt 1168 992) + (pt 1160 992) +) +(connector + (pt 1264 1016) + (pt 1168 1016) +) +(connector + (text "FB_SIZE0" (rect 1162 1000 1213 1011)(font "Arial" )) + (pt 1168 1016) + (pt 1160 1016) +) +(connector + (pt 1264 1040) + (pt 1168 1040) +) +(connector + (text "FB_SIZE1" (rect 1162 1024 1212 1035)(font "Arial" )) + (pt 1168 1040) + (pt 1160 1040) +) +(connector + (pt 1264 1064) + (pt 1168 1064) +) +(connector + (text "nFB_BURST" (rect 1162 1048 1226 1059)(font "Arial" )) + (pt 1168 1064) + (pt 1160 1064) +) +(connector + (pt 1264 1112) + (pt 1168 1112) +) +(connector + (text "nDACK0" (rect 1250 1096 1294 1107)(font "Arial" )) + (pt 1168 1112) + (pt 1160 1112) +) +(connector + (pt 1152 2600) + (pt 1160 2600) +) +(connector + (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) + (pt 1160 2600) + (pt 1264 2600) +) +(connector + (pt 1264 920) + (pt 1168 920) +) +(connector + (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) + (pt 1168 920) + (pt 1160 920) +) +(connector + (pt 1152 2648) + (pt 1160 2648) +) +(connector + (text "DVI_INT" (rect 1162 2632 1205 2643)(font "Arial" )) + (pt 1160 2648) + (pt 1264 2648) +) +(connector + (pt 1152 2744) + (pt 1160 2744) +) +(connector + (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) + (pt 1160 2744) + (pt 1264 2744) +) +(connector + (pt 1152 2720) + (pt 1160 2720) +) +(connector + (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) + (pt 1160 2720) + (pt 1264 2720) +) +(connector + (pt 1152 2696) + (pt 1160 2696) +) +(connector + (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) + (pt 1160 2696) + (pt 1264 2696) +) +(connector + (pt 1152 2672) + (pt 1160 2672) +) +(connector + (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) + (pt 1160 2672) + (pt 1264 2672) +) +(connector + (pt 1152 2624) + (pt 1160 2624) +) +(connector + (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) + (pt 1160 2624) + (pt 1264 2624) +) +(connector + (pt 528 2416) + (pt 536 2416) +) +(connector + (pt 536 2416) + (pt 616 2416) +) +(connector + (pt 776 1496) + (pt 784 1496) +) +(connector + (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) + (pt 784 1496) + (pt 1264 1496) +) +(connector + (pt 776 1520) + (pt 784 1520) +) +(connector + (text "PIC_AMKB_RX" (rect 786 1504 866 1515)(font "Arial" )) + (pt 784 1520) + (pt 1264 1520) +) +(connector + (pt 376 1400) + (pt 384 1400) +) +(connector + (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) + (pt 384 1400) + (pt 464 1400) +) +(connector + (pt 1040 1632) + (pt 1048 1632) +) +(connector + (text "HD_DD" (rect 1050 1616 1090 1627)(font "Arial" )) + (pt 1048 1632) + (pt 1264 1632) +) +(connector + (pt 336 304) + (pt 344 304) +) +(connector + (text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" )) + (pt 344 304) + (pt 400 304) +) +(connector + (pt 1176 368) + (pt 1184 368) +) +(connector + (pt 1184 368) + (pt 1256 368) +) +(connector + (text "CLK2M" (rect 906 -40 944 -29)(font "Arial" )) + (pt 704 -24) + (pt 944 -24) +) +(connector + (text "FDC_CLK" (rect 954 -24 1007 -13)(font "Arial" )) + (pt 704 -8) + (pt 944 -8) +) +(connector + (pt 832 56) + (pt 832 24) +) +(connector + (pt 840 56) + (pt 832 56) +) +(connector + (pt 832 24) + (pt 704 24) +) +(connector + (pt 400 -24) + (pt 400 248) +) +(connector + (pt 400 248) + (pt 400 304) +) +(connector + (pt 448 -24) + (pt 400 -24) +) +(connector + (text "CLK25M" (rect 1210 616 1254 627)(font "Arial" )) + (pt 1264 632) + (pt 1200 632) +) +(connector + (pt 776 8) + (pt 704 8) +) +(connector + (text "CLKUSB" (rect 538 552 584 563)(font "Arial" )) + (pt 528 568) + (pt 608 568) +) (junction (pt 2504 760)) (junction (pt 400 248)) (junction (pt 1856 -64)) (junction (pt 2424 -80)) +(junction (pt 1112 1264)) +(junction (pt 1112 1336)) +(junction (pt 1112 1424)) +(junction (pt 1112 1448)) +(junction (pt 1112 1472)) +(junction (pt 1112 1552)) +(junction (pt 1112 1576)) +(junction (pt 1112 1600)) +(junction (pt 1112 1784)) +(junction (pt 1112 1808)) +(junction (pt 1112 1832)) +(junction (pt 1112 1880)) +(junction (pt 1112 1176)) +(junction (pt 1032 1208)) +(junction (pt 1032 1232)) +(junction (pt 1048 1368)) +(junction (pt 1112 1400)) +(junction (pt 1048 1656)) +(junction (pt 1048 1680)) +(junction (pt 1048 1704)) +(junction (pt 1048 1728)) +(junction (pt 1048 1752)) +(junction (pt 1112 1288)) +(junction (pt 1112 1312)) +(junction (pt 1168 944)) +(junction (pt 1168 968)) +(junction (pt 1168 992)) +(junction (pt 1168 1016)) +(junction (pt 1168 1040)) +(junction (pt 1168 1064)) +(junction (pt 1168 1112)) +(junction (pt 1160 2600)) +(junction (pt 1168 920)) +(junction (pt 1160 2648)) +(junction (pt 1160 2744)) +(junction (pt 1160 2720)) +(junction (pt 1160 2696)) +(junction (pt 1160 2672)) +(junction (pt 1160 2624)) +(junction (pt 536 2416)) +(junction (pt 784 1496)) +(junction (pt 784 1520)) +(junction (pt 384 1400)) +(junction (pt 1048 1632)) +(junction (pt 344 304)) +(junction (pt 1184 368)) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index c1b6396..a795aaa 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -58,8 +58,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.080 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.080 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.10 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.10 #************************************************************** From d9364d9da5820fd85741d912e4261d2705455d49 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 19:24:59 +0000 Subject: [PATCH 019/127] more false_path settings --- FPGA_Quartus_13.1/firebee1.sdc | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index a795aaa..b4e2637 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -19,7 +19,7 @@ ## PROGRAM "Quartus II" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" -## DATE "Sun Sep 20 18:51:37 2015" +## DATE "Sun Sep 20 21:23:37 2015" ## ## DEVICE "EP3C40F484C6" @@ -58,8 +58,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.10 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.10 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.100 #************************************************************** @@ -91,7 +91,15 @@ set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generate set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] - +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] @@ -106,7 +114,6 @@ set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_m set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8 set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] 4 -#set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2 set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8 From 6f0464a1c7da78f497e959ffaf397183851bc42a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 19:50:38 +0000 Subject: [PATCH 020/127] added derive_clock_uncertainty --- FPGA_Quartus_13.1/firebee1.qws | Bin 4717 -> 7010 bytes FPGA_Quartus_13.1/firebee1.sdc | 1 + 2 files changed, 1 insertion(+) diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index c338aba0201bdaba1b064ec006014f596c6b3b80..c422e6822462699cd0e9c3feebdc13054bbe201d 100644 GIT binary patch literal 7010 zcmeI0&ref95XYwlBS%lhg9l=aAtt3QJSe?^6buPQq6NK}ru4PaP$;%lNDS!NgYoJ= zVB$Z(!GFPvSG{;Q{s*G?ndy7{cr*}5lRlvPvb%3)=k3nUerMm#jt_{RZc0V+QkRD0 zWL>IKlVzwicm*jUbd~%=;<7~B3Y<7)38^Y?8OmjOY5Y}s(AEs)D{_UlwY`>ji@xJB zEpu{TCK&kzz2xb&L0yMdJ<9Yp4Yz_ORauo8c}UA+Mwm2N7itD-ih2^s(@77a<&wC} z?gL+TW_Bg!Si@F}Xg)ytj`$E3bLa%doAZ%UY%+ z2JOJrw?ss3+bnCUTyR!Bu#|rnb5s%2 zO=9KrBMwHsfBR}3=@^!xZ|M1_PcfszwBkL5DU)Ei2$~hQG4di$@d)0>tTl-D5oGn> zqj(RKU)x_;Bz5a}G+I9#KTZN5!VRH1u z?GSd3$)^7YJRGJePDqhw{ED`AG!T#cp}0j*o#%*GVVr)#mJ;P8b@L)y%ewbvbPI7; z&wvCFS?vY-Vq8n;49^_!wLeTl8%uVy)ms2d82+DTCG3)>xoIj`Ttc&y-8RGk&nTdA z0f+-fZzA+=O>Y$yQVEthZI6RY34Yq@u-!G-9ilEv_eRXSyz?=D_wA*Q24JSe35VPN DC&rj2 delta 793 zcmZWnO-mb56g_X!iAj}|B8_069a>$*k7RI~b`c1;ks=htRs@TVaTKYT(qt#%s+%rK zg7?7p3B+KcP@4Zd~*aSljg6H{(am8}7XOb*1tn{&?BEYxV1lmFiw5AV38}n2(?b*PBYu;$$4h8XNOu ze+(BsEx;gh`~*12N}jt*&o?>oq$*#TwqSObzKiuXg^m%f6rg5VY|-#Xen89ttozMU z&$QZ@U|eMC4O3s~&(O+@*BF1IA1;yV8HtZ5*Q5Cq<6#5^BQTVjkEHq+2XQIUXSeiw z=2!vNTU-!bC&0#~Fe@CT?r`${nMBra{<<(hx>vl=*QgN%hejmX$Riy$F-iI=UZN_j zw`kwa>)c~Ne4D#I6SNXU3Zvv(CFX7gD+r{(W!koc7O>xn4BpXm!lQmr(?zU1J71`_2Uu+0>#C~<()FFEkm>so J>Pjq}{{T;wq4)p* diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index b4e2637..49c93c7 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -61,6 +61,7 @@ derive_pll_clocks set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.100 set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.100 +derive_clock_uncertainty #************************************************************** # Set Input Delay From 865bbf15c52957d44c3dcef846f4c23c33195ee9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 20:14:42 +0000 Subject: [PATCH 021/127] reformatted --- .../WF_SND2149_IP/wf2149ip_pkg.vhd | 2 +- .../WF_SND2149_IP/wf2149ip_top_soc.vhd | 195 +++++++++--------- .../WF_SND2149_IP/wf2149ip_wave.vhd | 2 +- 3 files changed, 100 insertions(+), 99 deletions(-) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd index 9d048de..a140e29 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd @@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS); component WF2149IP_WAVE port( RESETn : in bit; - SYS_CLK : in bit; + SYS_CLK : in std_logic; WAV_STRB : in bit; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd index 77ea5ef..060058c 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd @@ -76,129 +76,130 @@ -- Minor changes. -- -library ieee; -use ieee.std_logic_1164.all; -use work.wf2149ip_pkg.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE work.wf2149ip_pkg.ALL; -entity WF2149IP_TOP_SOC is - port( +ENTITY WF2149IP_TOP_SOC IS + PORT( - SYS_CLK : in bit; -- Read the inforation in the header! - RESETn : in bit; + SYS_CLK : IN std_logic; -- Read the inforation in the header! + RESETn : IN bit; - WAV_CLK : in bit; -- Read the inforation in the header! - SELn : in bit; + WAV_CLK : IN bit; -- Read the inforation in the header! + SELn : IN bit; - BDIR : in bit; - BC2, BC1 : in bit; + BDIR : IN bit; + BC2, BC1 : IN bit; - A9n, A8 : in bit; - DA_IN : in std_logic_vector(7 downto 0); - DA_OUT : out std_logic_vector(7 downto 0); - DA_EN : out bit; + A9n, A8 : IN bit; + DA_IN : IN std_logic_vector(7 DOWNTO 0); + DA_OUT : OUT std_logic_vector(7 DOWNTO 0); + DA_EN : OUT bit; - IO_A_IN : in bit_vector(7 downto 0); - IO_A_OUT : out bit_vector(7 downto 0); - IO_A_EN : out bit; - IO_B_IN : in bit_vector(7 downto 0); - IO_B_OUT : out bit_vector(7 downto 0); - IO_B_EN : out bit; + IO_A_IN : IN bit_vector(7 DOWNTO 0); + IO_A_OUT : OUT bit_vector(7 DOWNTO 0); + IO_A_EN : OUT bit; + IO_B_IN : IN bit_vector(7 DOWNTO 0); + IO_B_OUT : OUT bit_vector(7 DOWNTO 0); + IO_B_EN : OUT bit; - OUT_A : out bit; -- Analog (PWM) outputs. - OUT_B : out bit; - OUT_C : out bit + OUT_A : OUT bit; -- Analog (PWM) outputs. + OUT_B : OUT bit; + OUT_C : OUT bit ); -end WF2149IP_TOP_SOC; +END WF2149IP_TOP_SOC; -architecture STRUCTURE of WF2149IP_TOP_SOC is -signal BUSCYCLE : BUSCYCLES; -signal DATA_OUT_I : std_logic_vector(7 downto 0); -signal DATA_EN_I : bit; -signal WAV_STRB : bit; -signal ADR_I : bit_vector(3 downto 0); -signal CTRL_REG : bit_vector(7 downto 0); -signal PORT_A : bit_vector(7 downto 0); -signal PORT_B : bit_vector(7 downto 0); -begin - P_WAVSTRB: process(RESETn, SYS_CLK) - variable LOCK : boolean; - variable TMP : bit; - begin - if RESETn = '0' then +ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS + SIGNAL BUSCYCLE : BUSCYCLES; + SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0); + SIGNAL DATA_EN_I : bit; + SIGNAL WAV_STRB : bit; + SIGNAL ADR_I : bit_vector(3 DOWNTO 0); + SIGNAL CTRL_REG : bit_vector(7 DOWNTO 0); + SIGNAL PORT_A : bit_vector(7 DOWNTO 0); + SIGNAL PORT_B : bit_vector(7 DOWNTO 0); +BEGIN + P_WAVSTRB: PROCESS(RESETn, SYS_CLK) + VARIABLE LOCK : boolean; + VARIABLE TMP : bit; + BEGIN + IF RESETn = '0' THEN LOCK := false; TMP := '0'; - elsif SYS_CLK = '1' and SYS_CLK' event then - if WAV_CLK = '1' and LOCK = false then + ELSIF rising_edge(SYS_CLK) THEN + IF WAV_CLK = '1' and LOCK = false THEN LOCK := true; TMP := not TMP; -- Divider by 2. - case SELn is - when '1' => WAV_STRB <= '1'; - when others => WAV_STRB <= TMP; - end case; - elsif WAV_CLK = '0' then + + CASE SELn IS + WHEN '1' => WAV_STRB <= '1'; + WHEN OTHERS => WAV_STRB <= TMP; + END CASE; + ELSIF WAV_CLK = '0' THEN LOCK := false; WAV_STRB <= '0'; - else + ELSE WAV_STRB <= '0'; - end if; - end if; - end process P_WAVSTRB; + END IF; + END IF; + END PROCESS P_WAVSTRB; - with BDIR & BC2 & BC1 select - BUSCYCLE <= INACTIVE when "000" | "010" | "101", - ADDRESS when "001" | "100" | "111", - R_READ when "011", - R_WRITE when "110"; + WITH BDIR & BC2 & BC1 SELECT + BUSCYCLE <= INACTIVE WHEN "000" | "010" | "101", + ADDRESS WHEN "001" | "100" | "111", + R_READ WHEN "011", + R_WRITE WHEN "110"; - ADDRESSLATCH: process(RESETn, SYS_CLK) + ADDRESSLATCH: PROCESS(RESETn, SYS_CLK) -- This process is responsible to store the desired register -- address. The default (after reset) is channel A fine tone -- adjustment. - begin - if RESETn = '0' then - ADR_I <= (others => '0'); - elsif SYS_CLK = '1' and SYS_CLK' event then - if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then - ADR_I <= To_BitVector(DA_IN(3 downto 0)); - end if; - end if; - end process ADDRESSLATCH; + BEGIN + IF RESETn = '0' THEN + ADR_I <= (OTHERS => '0'); + ELSIF rising_edge(SYS_CLK) THEN + IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN + ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0)); + END IF; + END IF; + END PROCESS ADDRESSLATCH; - P_CTRL_REG: process(RESETn, SYS_CLK) + P_CTRL_REG: PROCESS(RESETn, SYS_CLK) -- THIS is the Control register for the mixer and for the I/O ports. - begin - if RESETn = '0' then + BEGIN + IF RESETn = '0' THEN CTRL_REG <= x"00"; - elsif SYS_CLK = '1' and SYS_CLK' event then - if BUSCYCLE = R_WRITE and ADR_I = x"7" then + ELSIF rising_edge(SYS_CLK) THEN + IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN CTRL_REG <= To_BitVector(DA_IN); - end if; - end if; - end process P_CTRL_REG; + END IF; + END IF; + END PROCESS P_CTRL_REG; - DIG_PORTS: process(RESETn, SYS_CLK) - begin - if RESETn = '0' then + DIG_PORTS: PROCESS(RESETn, SYS_CLK) + BEGIN + IF RESETn = '0' THEN PORT_A <= x"00"; PORT_B <= x"00"; - elsif SYS_CLK = '1' and SYS_CLK' event then - if BUSCYCLE = R_WRITE and ADR_I = x"E" then + ELSIF rising_edge(SYS_CLK) THEN + IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN PORT_A <= To_BitVector(DA_IN); - elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then + ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN PORT_B <= To_BitVector(DA_IN); - end if; - end if; - end process DIG_PORTS; + END IF; + END IF; + END PROCESS DIG_PORTS; -- Set port direction to input or to output: - IO_A_EN <= '1' when CTRL_REG(6) = '1' else '0'; - IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0'; + IO_A_EN <= '1' WHEN CTRL_REG(6) = '1' ELSE '0'; + IO_B_EN <= '1' WHEN CTRL_REG(7) = '1' ELSE '0'; IO_A_OUT <= PORT_A; IO_B_OUT <= PORT_B; I_PSG_WAVE: WF2149IP_WAVE - port map( + PORT MAP( RESETn => RESETn, - SYS_CLK => SYS_CLK, + SYS_CLK => SYS_CLK, WAV_STRB => WAV_STRB, @@ -208,7 +209,7 @@ begin DATA_EN => DATA_EN_I, BUSCYCLE => BUSCYCLE, - CTRL_REG => CTRL_REG(5 downto 0), + CTRL_REG => CTRL_REG(5 DOWNTO 0), OUT_A => OUT_A, OUT_B => OUT_B, @@ -216,14 +217,14 @@ begin ); -- Read the ports and registers: - DA_EN <= '1' when DATA_EN_I = '1' else - '1' when BUSCYCLE = R_READ and ADR_I = x"7" else - '1' when BUSCYCLE = R_READ and ADR_I = x"E" else - '1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0'; + DA_EN <= '1' WHEN DATA_EN_I = '1' ELSE + '1' WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE + '1' WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE + '1' WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE '0'; - DA_OUT <= DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff. - To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else - To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else - To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0'); + DA_OUT <= DATA_OUT_I WHEN DATA_EN_I = '1' ELSE -- WAV stuff. + To_StdLogicVector(IO_A_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"E" ELSE + To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE + To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0'); -end STRUCTURE; +END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd index d829f9b..8744213 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd @@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all; entity WF2149IP_WAVE is port( RESETn : in bit; - SYS_CLK : in bit; + SYS_CLK : in std_logic; WAV_STRB : in bit; From a640ef35f602373f5b6408163697b6ea18c6b463 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 21:41:31 +0000 Subject: [PATCH 022/127] removed absolute DOS path --- FPGA_Quartus_13.1/firebee1.qsf | 2 -- 1 file changed, 2 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 6f21306..06c7dc9 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -42,7 +42,6 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== @@ -566,7 +565,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end ENTITY(firebee1) # -------------------- -set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top From 988bf013404bf59c686a8f3bcae0b496734d4a92 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 21 Sep 2015 05:16:42 +0000 Subject: [PATCH 023/127] cleanup --- FPGA_Quartus_13.1/UNUSED | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 FPGA_Quartus_13.1/UNUSED diff --git a/FPGA_Quartus_13.1/UNUSED b/FPGA_Quartus_13.1/UNUSED deleted file mode 100644 index 3a7d9e6..0000000 --- a/FPGA_Quartus_13.1/UNUSED +++ /dev/null @@ -1,27 +0,0 @@ - --- Clearbox generated Memory Initialization File (.mif) - -WIDTH=3; -DEPTH=16; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - 00 : 7; - 01 : 6; - 02 : 5; - 03 : 4; - 04 : 3; - 05 : 2; - 06 : 1; - 07 : 0; - 08 : 7; - 09 : 6; - 0a : 5; - 0b : 4; - 0c : 3; - 0d : 2; - 0e : 1; - 0f : 0; -END; From 32b95cf9586a870e03e26460ebb90d79540100d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 21 Sep 2015 05:21:50 +0000 Subject: [PATCH 024/127] cleanup --- FPGA_Quartus_13.1/Coldari1.qsf | 44 ------ FPGA_Quartus_13.1/Video/UNUSED | 267 --------------------------------- 2 files changed, 311 deletions(-) delete mode 100644 FPGA_Quartus_13.1/Coldari1.qsf delete mode 100644 FPGA_Quartus_13.1/Video/UNUSED diff --git a/FPGA_Quartus_13.1/Coldari1.qsf b/FPGA_Quartus_13.1/Coldari1.qsf deleted file mode 100644 index da581cf..0000000 --- a/FPGA_Quartus_13.1/Coldari1.qsf +++ /dev/null @@ -1,44 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2009 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II -# Version 9.1 Build 222 10/21/2009 SJ Web Edition -# Date created = 12:11:46 March 06, 2010 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# Coldari1_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Stratix II" -set_global_assignment -name DEVICE AUTO -set_global_assignment -name TOP_LEVEL_ENTITY Coldari1 -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:11:46 MARCH 06, 2010" -set_global_assignment -name LAST_QUARTUS_VERSION 9.1 \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/UNUSED b/FPGA_Quartus_13.1/Video/UNUSED deleted file mode 100644 index 12f424b..0000000 --- a/FPGA_Quartus_13.1/Video/UNUSED +++ /dev/null @@ -1,267 +0,0 @@ - --- Clearbox generated Memory Initialization File (.mif) - -WIDTH=6; -DEPTH=256; - -ADDRESS_RADIX=HEX; -DATA_RADIX=HEX; - -CONTENT BEGIN - 000 : 0F; - 001 : 0E; - 002 : 0D; - 003 : 0C; - 004 : 0B; - 005 : 0A; - 006 : 09; - 007 : 08; - 008 : 07; - 009 : 06; - 00a : 05; - 00b : 04; - 00c : 03; - 00d : 02; - 00e : 01; - 00f : 00; - 010 : 0F; - 011 : 0E; - 012 : 0D; - 013 : 0C; - 014 : 0B; - 015 : 0A; - 016 : 09; - 017 : 08; - 018 : 07; - 019 : 06; - 01a : 05; - 01b : 04; - 01c : 03; - 01d : 02; - 01e : 01; - 01f : 00; - 020 : 0F; - 021 : 0E; - 022 : 0D; - 023 : 0C; - 024 : 0B; - 025 : 0A; - 026 : 09; - 027 : 08; - 028 : 07; - 029 : 06; - 02a : 05; - 02b : 04; - 02c : 03; - 02d : 02; - 02e : 01; - 02f : 00; - 030 : 0F; - 031 : 0E; - 032 : 0D; - 033 : 0C; - 034 : 0B; - 035 : 0A; - 036 : 09; - 037 : 08; - 038 : 07; - 039 : 06; - 03a : 05; - 03b : 04; - 03c : 03; - 03d : 02; - 03e : 01; - 03f : 00; - 040 : 0F; - 041 : 0E; - 042 : 0D; - 043 : 0C; - 044 : 0B; - 045 : 0A; - 046 : 09; - 047 : 08; - 048 : 07; - 049 : 06; - 04a : 05; - 04b : 04; - 04c : 03; - 04d : 02; - 04e : 01; - 04f : 00; - 050 : 0F; - 051 : 0E; - 052 : 0D; - 053 : 0C; - 054 : 0B; - 055 : 0A; - 056 : 09; - 057 : 08; - 058 : 07; - 059 : 06; - 05a : 05; - 05b : 04; - 05c : 03; - 05d : 02; - 05e : 01; - 05f : 00; - 060 : 0F; - 061 : 0E; - 062 : 0D; - 063 : 0C; - 064 : 0B; - 065 : 0A; - 066 : 09; - 067 : 08; - 068 : 07; - 069 : 06; - 06a : 05; - 06b : 04; - 06c : 03; - 06d : 02; - 06e : 01; - 06f : 00; - 070 : 0F; - 071 : 0E; - 072 : 0D; - 073 : 0C; - 074 : 0B; - 075 : 0A; - 076 : 09; - 077 : 08; - 078 : 07; - 079 : 06; - 07a : 05; - 07b : 04; - 07c : 03; - 07d : 02; - 07e : 01; - 07f : 00; - 080 : 0F; - 081 : 0E; - 082 : 0D; - 083 : 0C; - 084 : 0B; - 085 : 0A; - 086 : 09; - 087 : 08; - 088 : 07; - 089 : 06; - 08a : 05; - 08b : 04; - 08c : 03; - 08d : 02; - 08e : 01; - 08f : 00; - 090 : 0F; - 091 : 0E; - 092 : 0D; - 093 : 0C; - 094 : 0B; - 095 : 0A; - 096 : 09; - 097 : 08; - 098 : 07; - 099 : 06; - 09a : 05; - 09b : 04; - 09c : 03; - 09d : 02; - 09e : 01; - 09f : 00; - 0a0 : 0F; - 0a1 : 0E; - 0a2 : 0D; - 0a3 : 0C; - 0a4 : 0B; - 0a5 : 0A; - 0a6 : 09; - 0a7 : 08; - 0a8 : 07; - 0a9 : 06; - 0aa : 05; - 0ab : 04; - 0ac : 03; - 0ad : 02; - 0ae : 01; - 0af : 00; - 0b0 : 0F; - 0b1 : 0E; - 0b2 : 0D; - 0b3 : 0C; - 0b4 : 0B; - 0b5 : 0A; - 0b6 : 09; - 0b7 : 08; - 0b8 : 07; - 0b9 : 06; - 0ba : 05; - 0bb : 04; - 0bc : 03; - 0bd : 02; - 0be : 01; - 0bf : 00; - 0c0 : 0F; - 0c1 : 0E; - 0c2 : 0D; - 0c3 : 0C; - 0c4 : 0B; - 0c5 : 0A; - 0c6 : 09; - 0c7 : 08; - 0c8 : 07; - 0c9 : 06; - 0ca : 05; - 0cb : 04; - 0cc : 03; - 0cd : 02; - 0ce : 01; - 0cf : 00; - 0d0 : 0F; - 0d1 : 0E; - 0d2 : 0D; - 0d3 : 0C; - 0d4 : 0B; - 0d5 : 0A; - 0d6 : 09; - 0d7 : 08; - 0d8 : 07; - 0d9 : 06; - 0da : 05; - 0db : 04; - 0dc : 03; - 0dd : 02; - 0de : 01; - 0df : 00; - 0e0 : 0F; - 0e1 : 0E; - 0e2 : 0D; - 0e3 : 0C; - 0e4 : 0B; - 0e5 : 0A; - 0e6 : 09; - 0e7 : 08; - 0e8 : 07; - 0e9 : 06; - 0ea : 05; - 0eb : 04; - 0ec : 03; - 0ed : 02; - 0ee : 01; - 0ef : 00; - 0f0 : 0F; - 0f1 : 0E; - 0f2 : 0D; - 0f3 : 0C; - 0f4 : 0B; - 0f5 : 0A; - 0f6 : 09; - 0f7 : 08; - 0f8 : 07; - 0f9 : 06; - 0fa : 05; - 0fb : 04; - 0fc : 03; - 0fd : 02; - 0fe : 01; - 0ff : 00; -END; From ad05ca852324b1c07f3a9536e1a281aea70b0903 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 21 Sep 2015 05:32:56 +0000 Subject: [PATCH 025/127] cleanup --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 48 +++++++++++++++++++---------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index b100fe6..d22c642 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -58,9 +58,9 @@ SUBDESIGN DDR_CTR ) VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) - DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + FB_REGDDR :MACHINE WITH STATES(FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG DS_T4R,DS_T5R, -- READ CPU UND BLITTER, DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO @@ -129,7 +129,8 @@ VARIABLE BEGIN LINE = FB_SIZE0 & FB_SIZE1; --- BYT SELECT + + -- BYT SELECT FB_B0 = FB_ADR[1..0]==0 -- ADR==0 # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE FB_B1 = FB_ADR[1..0]==1 -- ADR==1 @@ -140,7 +141,8 @@ BEGIN FB_B3 = FB_ADR[1..0]==3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + + -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- FB_REGDDR.CLK = MAIN_CLK; CASE FB_REGDDR IS WHEN FR_WAIT => @@ -198,7 +200,8 @@ BEGIN FB_REGDDR = FR_WAIT; END IF; END CASE; --- DDR STEUERUNG ----------------------------------------------------- + + -- DDR STEUERUNG ----------------------------------------------------- -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; VCKE = VIDEO_RAM_CTR0; nVCS = !VIDEO_RAM_CTR1; @@ -220,12 +223,14 @@ BEGIN FIFO_AC.CLK = DDRCLK0; BLITTER_AC.CLK = DDRCLK0; DDRWR_D_SEL1 = BLITTER_AC; --- SELECT LOGIC + + -- SELECT LOGIC DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; DDR_CS.CLK = MAIN_CLK; DDR_CS.ENA = FB_ALE; DDR_CS = DDR_SEL; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP�TER + + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP�TER CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP�TER @@ -241,14 +246,16 @@ BEGIN MCS1 = MCS0; CPU_DDR_SYNC.CLK = DDRCLK0; CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN - --------------------------------------------------- + + --------------------------------------------------- VA_S[].CLK = DDRCLK0; BA_S[].CLK = DDRCLK0; VA[] = VA_S[]; BA[] = BA_S[]; VA_P[].CLK = DDRCLK0; BA_P[].CLK = DDRCLK0; --- DDR STATE MACHINE ----------------------------------------------- + + -- DDR STATE MACHINE ----------------------------------------------- DDR_SM.CLK = DDRCLK0; CASE DDR_SM IS WHEN DS_T1 => @@ -337,7 +344,8 @@ BEGIN END IF; END IF; END IF; --- READ + + -- READ WHEN DS_T4R => CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; @@ -358,7 +366,8 @@ BEGIN VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN DDR_SM = DS_CB6; END IF; --- WRITE + + -- WRITE WHEN DS_T4W => CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; @@ -408,7 +417,8 @@ BEGIN VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN DDR_SM = DS_CB6; END IF; --- FIFO READ + + -- FIFO READ WHEN DS_T4F => VCAS = VCC; SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO @@ -498,7 +508,8 @@ BEGIN DDR_SM = DS_T7F; END IF; --- CONFIG CYCLUS + + -- CONFIG CYCLUS WHEN DS_C2 => DDR_SM = DS_C3; WHEN DS_C3 => @@ -521,7 +532,8 @@ BEGIN VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE DDR_SM = DS_N8; --- CLOSE FIFO BANK + + -- CLOSE FIFO BANK WHEN DS_CB6 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK VRAS = VCC; -- B�NKE SCHLIESSEN @@ -532,7 +544,8 @@ BEGIN VRAS = VCC; -- B�NKE SCHLIESSEN VWE = VCC; DDR_SM = DS_T1; --- REFRESH 70NS = 10 ZYCLEN + + -- REFRESH 70NS = 10 ZYCLEN WHEN DS_R2 => IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN VRAS = VCC; -- ALLE BANKS SCHLIESSEN @@ -553,7 +566,8 @@ BEGIN DDR_SM = DS_R6; WHEN DS_R6 => DDR_SM = DS_N5; --- LEERSCHLAUFE + + -- LEERSCHLAUFE WHEN DS_N5 => DDR_SM = DS_N6; WHEN DS_N6 => From 7e2181fbc93458efd651414a028124eed1344649 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 23 Sep 2015 09:49:05 +0000 Subject: [PATCH 026/127] improved timing, added timing constraints, got rid of CLK_33M Design compiles and runs, but still has issues with different screen resolutions and video clocks --- .../FalconIO_SDCard_IDE_CF.vhd | 32 +- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 2 +- FPGA_Quartus_13.1/altpll1.bsf | 200 +-- FPGA_Quartus_13.1/altpll1.cmp | 50 +- FPGA_Quartus_13.1/altpll1.inc | 52 +- FPGA_Quartus_13.1/altpll1.ppf | 24 +- FPGA_Quartus_13.1/altpll1.qip | 14 +- FPGA_Quartus_13.1/altpll1.vhd | 846 +++++------ FPGA_Quartus_13.1/altpll3.bsf | 4 +- FPGA_Quartus_13.1/altpll3.vhd | 38 +- FPGA_Quartus_13.1/altpll4.bsf | 152 +- FPGA_Quartus_13.1/altpll4.cmp | 2 +- FPGA_Quartus_13.1/altpll4.inc | 2 +- FPGA_Quartus_13.1/altpll4.mif | 6 +- FPGA_Quartus_13.1/altpll4.qip | 2 +- FPGA_Quartus_13.1/altpll4.tdf | 46 +- FPGA_Quartus_13.1/firebee1.bdf | 270 ++-- FPGA_Quartus_13.1/firebee1.qsf | 1258 +++++++++-------- FPGA_Quartus_13.1/firebee1.sdc | 150 +- 19 files changed, 1631 insertions(+), 1519 deletions(-) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index 523161b..b994a78 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -150,21 +150,21 @@ END falconio_sdcard_ide_cf; ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS -- system - SIGNAL SYS_CLK : std_logic; + SIGNAL SYS_CLK : std_logic; SIGNAL RESETn : std_logic; SIGNAL FB_B0 : std_logic; -- UPPER BYT BEI 16BIT BUS SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS SIGNAL BYT : std_logic; -- WENN BYT -> 1 - SIGNAL LONG : std_logic; -- WENN -> 1 + SIGNAL LONG : std_logic; -- WENN -> 1 -- KEYBOARD MIDI SIGNAL ACIA_CS_I : std_logic; - SIGNAL IRQ_KEYBDn : std_logic; + SIGNAL IRQ_KEYBDn : std_logic; SIGNAL IRQ_MIDIn : std_logic; - SIGNAL KEYB_RxD : std_logic; - SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); - SIGNAL MIDI_OUT : std_logic; - SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); - SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); + SIGNAL KEYB_RxD : std_logic; + SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); + SIGNAL MIDI_OUT : std_logic; + SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); + SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); -- MFP SIGNAL MFP_CS : std_logic; SIGNAL MFP_INTACK : std_logic; @@ -370,7 +370,7 @@ BEGIN -- ACSI, SCSI UND FLOPPY WD1772 ------------------------------------------------------------------------------------------------------------------------------------------- -- daten read fifo - RDF: dcfifo0 + i_data_read_fifo: dcfifo0 PORT MAP( aclr => CLR_FIFO, data => RDF_DIN, @@ -390,7 +390,7 @@ BEGIN RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; -- daten write fifo - WRF: dcfifo1 + i_data_write_fifo: dcfifo1 PORT MAP( aclr => CLR_FIFO, data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), @@ -527,7 +527,7 @@ BEGIN END CASE; END PROCESS FCF_DECODER; - I_FDC: WF1772IP_TOP_SOC + i_fdc : WF1772IP_TOP_SOC PORT MAP( CLK => FDC_CLK, RESETn => nRSTO, @@ -731,7 +731,7 @@ BEGIN CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; -- SCSI ---------------------------------------------------------------------------------- - I_SCSI: WF5380_TOP_SOC + i_scsi : WF5380_TOP_SOC PORT MAP( CLK => FDC_CLK, RESETn => nRSTO, @@ -810,7 +810,7 @@ BEGIN ---------------------------------------------------------------------------- -- ACIA KEYBOARD ---------------------------------------------------------------------------- - I_ACIA_KEYBOARD: WF6850IP_TOP_SOC + i_acia_keyboard : WF6850IP_TOP_SOC PORT MAP( CLK => MAIN_CLK, RESETn => nRSTO, @@ -867,7 +867,7 @@ BEGIN ---------------------------------------------------------------------------- -- ACIA MIDI ---------------------------------------------------------------------------- - I_ACIA_MIDI: WF6850IP_TOP_SOC + i_acia_midi : WF6850IP_TOP_SOC PORT MAP( CLK => MAIN_CLK, RESETn => nRSTO, @@ -901,7 +901,7 @@ BEGIN ---------------------------------------------------------------------------- -- MFP ---------------------------------------------------------------------------- - I_MFP: WF68901IP_TOP_SOC + i_mfp : WF68901IP_TOP_SOC PORT MAP( -- System control: CLK => MAIN_CLK, @@ -978,7 +978,7 @@ BEGIN ---------------------------------------------------------------------------- -- Sound ---------------------------------------------------------------------------- - I_SOUND: WF2149IP_TOP_SOC + i_sound : WF2149IP_TOP_SOC PORT MAP( SYS_CLK => MAIN_CLK, RESETn => nRSTO, diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 078cd89..f74f1dd 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -552,7 +552,7 @@ BEGIN -- VIDEO AUSGABE SETZEN - CLK17M.CLK = CLK33M; + CLK17M.CLK = MAIN_CLK; CLK17M = !CLK17M; CLK13M.CLK = CLK25M; CLK13M = !CLK13M; diff --git a/FPGA_Quartus_13.1/altpll1.bsf b/FPGA_Quartus_13.1/altpll1.bsf index d1e4a9e..c19a3a7 100644 --- a/FPGA_Quartus_13.1/altpll1.bsf +++ b/FPGA_Quartus_13.1/altpll1.bsf @@ -1,100 +1,100 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 328 216) - (text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 197 31 212)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 328 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8))) - (line (pt 328 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 328 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8))) - (line (pt 328 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 328 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8))) - (line (pt 328 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 328 144) - (output) - (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8))) - (line (pt 328 144)(pt 272 144)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 253 198 301 212)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) - (text "Clk " (rect 59 111 76 125)(font "Arial" )) - (text "Ratio" (rect 90 111 114 125)(font "Arial" )) - (text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) - (text "DC (%)" (rect 173 111 208 125)(font "Arial" )) - (text "c0" (rect 63 129 75 143)(font "Arial" )) - (text "1/66" (rect 92 129 113 143)(font "Arial" )) - (text "0.00" (rect 136 129 157 143)(font "Arial" )) - (text "50.00" (rect 178 129 205 143)(font "Arial" )) - (text "c1" (rect 63 147 75 161)(font "Arial" )) - (text "67/900" (rect 85 147 118 161)(font "Arial" )) - (text "0.00" (rect 136 147 157 161)(font "Arial" )) - (text "50.00" (rect 178 147 205 161)(font "Arial" )) - (text "c2" (rect 63 165 75 179)(font "Arial" )) - (text "67/90" (rect 89 165 116 179)(font "Arial" )) - (text "0.00" (rect 136 165 157 179)(font "Arial" )) - (text "50.00" (rect 178 165 205 179)(font "Arial" )) - (line (pt 0 0)(pt 329 0)(line_width 1)) - (line (pt 329 0)(pt 329 217)(line_width 1)) - (line (pt 0 217)(pt 329 217)(line_width 1)) - (line (pt 0 0)(pt 0 217)(line_width 1)) - (line (pt 56 108)(pt 215 108)(line_width 1)) - (line (pt 56 125)(pt 215 125)(line_width 1)) - (line (pt 56 143)(pt 215 143)(line_width 1)) - (line (pt 56 161)(pt 215 161)(line_width 1)) - (line (pt 56 179)(pt 215 179)(line_width 1)) - (line (pt 56 108)(pt 56 179)(line_width 1)) - (line (pt 82 108)(pt 82 179)(line_width 3)) - (line (pt 125 108)(pt 125 179)(line_width 3)) - (line (pt 170 108)(pt 170 179)(line_width 3)) - (line (pt 214 108)(pt 214 179)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 200)(line_width 1)) - (line (pt 48 200)(pt 272 200)(line_width 1)) - (line (pt 48 56)(pt 48 200)(line_width 1)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2014 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 272 176) + (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 161 26 172)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 272 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8))) + ) + (port + (pt 272 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8))) + ) + (port + (pt 272 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8))) + ) + (port + (pt 272 112) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone III" (rect 214 162 474 334)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) + (text "Clk " (rect 51 91 117 192)(font "Arial" )) + (text "Ratio" (rect 82 91 187 192)(font "Arial" )) + (text "Ph (dg)" (rect 119 91 269 192)(font "Arial" )) + (text "DC (%)" (rect 154 91 340 192)(font "Arial" )) + (text "c0" (rect 54 104 119 218)(font "Arial" )) + (text "1/66" (rect 84 104 186 218)(font "Arial" )) + (text "0.00" (rect 125 104 269 218)(font "Arial" )) + (text "50.00" (rect 158 104 340 218)(font "Arial" )) + (text "c1" (rect 54 117 118 244)(font "Arial" )) + (text "512/6875" (rect 74 117 187 244)(font "Arial" )) + (text "0.00" (rect 125 117 269 244)(font "Arial" )) + (text "50.00" (rect 158 117 340 244)(font "Arial" )) + (text "c2" (rect 54 130 119 270)(font "Arial" )) + (text "1024/1375" (rect 71 130 185 270)(font "Arial" )) + (text "0.00" (rect 125 130 269 270)(font "Arial" )) + (text "50.00" (rect 158 130 340 270)(font "Arial" )) + (line (pt 0 0)(pt 273 0)) + (line (pt 273 0)(pt 273 177)) + (line (pt 0 177)(pt 273 177)) + (line (pt 0 0)(pt 0 177)) + (line (pt 48 89)(pt 186 89)) + (line (pt 48 101)(pt 186 101)) + (line (pt 48 114)(pt 186 114)) + (line (pt 48 127)(pt 186 127)) + (line (pt 48 140)(pt 186 140)) + (line (pt 48 89)(pt 48 140)) + (line (pt 68 89)(pt 68 140)(line_width 3)) + (line (pt 116 89)(pt 116 140)(line_width 3)) + (line (pt 151 89)(pt 151 140)(line_width 3)) + (line (pt 185 89)(pt 185 140)) + (line (pt 40 48)(pt 223 48)) + (line (pt 223 48)(pt 223 159)) + (line (pt 40 159)(pt 223 159)) + (line (pt 40 48)(pt 40 159)) + (line (pt 271 64)(pt 223 64)) + (line (pt 271 80)(pt 223 80)) + (line (pt 271 96)(pt 223 96)) + (line (pt 271 112)(pt 223 112)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll1.cmp b/FPGA_Quartus_13.1/altpll1.cmp index 300576d..75df12e 100644 --- a/FPGA_Quartus_13.1/altpll1.cmp +++ b/FPGA_Quartus_13.1/altpll1.cmp @@ -1,25 +1,25 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altpll1 - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll1 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll1.inc b/FPGA_Quartus_13.1/altpll1.inc index 0923ad2..aafe483 100644 --- a/FPGA_Quartus_13.1/altpll1.inc +++ b/FPGA_Quartus_13.1/altpll1.inc @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altpll1 -( - inclk0 -) - -RETURNS ( - c0, - c1, - c2, - locked -); +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll1 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + locked +); diff --git a/FPGA_Quartus_13.1/altpll1.ppf b/FPGA_Quartus_13.1/altpll1.ppf index 0f38a28..d292d4b 100644 --- a/FPGA_Quartus_13.1/altpll1.ppf +++ b/FPGA_Quartus_13.1/altpll1.ppf @@ -1,12 +1,12 @@ - - - - - - - - - - - - + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll1.qip b/FPGA_Quartus_13.1/altpll1.qip index ec03f05..01791b7 100644 --- a/FPGA_Quartus_13.1/altpll1.qip +++ b/FPGA_Quartus_13.1/altpll1.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] diff --git a/FPGA_Quartus_13.1/altpll1.vhd b/FPGA_Quartus_13.1/altpll1.vhd index ab9bfaf..967a797 100644 --- a/FPGA_Quartus_13.1/altpll1.vhd +++ b/FPGA_Quartus_13.1/altpll1.vhd @@ -1,423 +1,423 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: altpll1.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY altpll1 IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END altpll1; - - -ARCHITECTURE SYN OF altpll1 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - locked <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 66, - clk0_duty_cycle => 50, - clk0_multiply_by => 1, - clk0_phase_shift => "0", - clk1_divide_by => 900, - clk1_duty_cycle => 50, - clk1_multiply_by => 67, - clk1_phase_shift => "0", - clk2_divide_by => 90, - clk2_duty_cycle => 50, - clk2_multiply_by => 67, - clk2_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 30303, - intended_device_family => "Cyclone III", - lpm_type => "altpll", - operation_mode => "SOURCE_SYNCHRONOUS", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire4 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll1.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll1 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END altpll1; + + +ARCHITECTURE SYN OF altpll1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire7_bv(0 DOWNTO 0) <= "0"; + sub_wire7 <= To_stdlogicvector(sub_wire7_bv); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + sub_wire5 <= inclk0; + sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 66, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 6875, + clk1_duty_cycle => 50, + clk1_multiply_by => 512, + clk1_phase_shift => "0", + clk2_divide_by => 1375, + clk2_duty_cycle => 50, + clk2_multiply_by => 1024, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire6, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll3.bsf b/FPGA_Quartus_13.1/altpll3.bsf index 75fabaa..98eb9cf 100644 --- a/FPGA_Quartus_13.1/altpll3.bsf +++ b/FPGA_Quartus_13.1/altpll3.bsf @@ -71,11 +71,11 @@ applicable agreement for further details. (text "0.00" (rect 115 117 249 244)(font "Arial" )) (text "50.00" (rect 148 117 320 244)(font "Arial" )) (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "109/144" (rect 71 130 175 270)(font "Arial" )) + (text "227/300" (rect 71 130 176 270)(font "Arial" )) (text "0.00" (rect 115 130 249 270)(font "Arial" )) (text "50.00" (rect 148 130 320 270)(font "Arial" )) (text "c3" (rect 54 143 119 296)(font "Arial" )) - (text "16/11" (rect 77 143 176 296)(font "Arial" )) + (text "227/156" (rect 71 143 176 296)(font "Arial" )) (text "0.00" (rect 115 143 249 296)(font "Arial" )) (text "50.00" (rect 148 143 320 296)(font "Arial" )) (line (pt 0 0)(pt 257 0)) diff --git a/FPGA_Quartus_13.1/altpll3.vhd b/FPGA_Quartus_13.1/altpll3.vhd index 8d19aba..be0649b 100644 --- a/FPGA_Quartus_13.1/altpll3.vhd +++ b/FPGA_Quartus_13.1/altpll3.vhd @@ -164,13 +164,13 @@ BEGIN clk1_duty_cycle => 50, clk1_multiply_by => 16, clk1_phase_shift => "0", - clk2_divide_by => 144, + clk2_divide_by => 300, clk2_duty_cycle => 50, - clk2_multiply_by => 109, + clk2_multiply_by => 227, clk2_phase_shift => "0", - clk3_divide_by => 11, + clk3_divide_by => 156, clk3_duty_cycle => 50, - clk3_multiply_by => 16, + clk3_multiply_by => 227, clk3_phase_shift => "0", compensate_clock => "CLK1", inclk0_input_frequency => 30303, @@ -249,18 +249,18 @@ END SYN; -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "144" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.979166" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -289,16 +289,16 @@ END SYN; -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" @@ -365,13 +365,13 @@ END SYN; -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "144" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "109" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" @@ -440,6 +440,6 @@ END SYN; -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll4.bsf b/FPGA_Quartus_13.1/altpll4.bsf index e071d43..f74527e 100644 --- a/FPGA_Quartus_13.1/altpll4.bsf +++ b/FPGA_Quartus_13.1/altpll4.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2010 Altera Corporation +Copyright (C) 1991-2014 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.1")) +(header "symbol" (version "1.2")) (symbol - (rect 0 0 376 232) - (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 213 31 228)(font "Arial" )) + (rect 0 0 312 184) + (text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 168 25 180)(font "Arial" )) (port - (pt 0 72) + (pt 0 64) (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 88 72)(line_width 1)) + (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 72 64)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 72 80)) ) (port (pt 0 96) (input) - (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) - (text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 88 96)(line_width 1)) + (text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 72 96)) ) (port - (pt 0 120) + (pt 0 112) (input) - (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 88 120)(line_width 1)) + (text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 72 112)) + ) + (port + (pt 0 128) + (input) + (text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 72 128)) ) (port (pt 0 144) (input) - (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) - (text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 88 144)(line_width 1)) + (text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 72 144)) ) (port - (pt 0 168) - (input) - (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) - (text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 88 168)(line_width 1)) - ) - (port - (pt 0 192) - (input) - (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) - (text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8))) - (line (pt 0 192)(pt 88 192)(line_width 1)) - ) - (port - (pt 376 72) + (pt 312 64) (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) - (line (pt 376 72)(pt 288 72)(line_width 1)) + (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8))) ) (port - (pt 376 96) + (pt 312 80) (output) - (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) - (text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) - (line (pt 376 96)(pt 288 96)(line_width 1)) + (text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8))) + (text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8))) ) (port - (pt 376 120) + (pt 312 96) (output) - (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) - (text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) - (line (pt 376 120)(pt 288 120)(line_width 1)) + (text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8))) + (text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8))) ) (port - (pt 376 144) + (pt 312 112) (output) - (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) - (line (pt 376 144)(pt 288 144)(line_width 1)) + (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8))) ) (drawing - (text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) - (text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) - (text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) - (text "Clk " (rect 99 167 116 181)(font "Arial" )) - (text "Ratio" (rect 125 167 149 181)(font "Arial" )) - (text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) - (text "DC (%)" (rect 204 167 239 181)(font "Arial" )) - (text "c0" (rect 103 185 115 199)(font "Arial" )) - (text "2/1" (rect 131 185 146 199)(font "Arial" )) - (text "0.00" (rect 167 185 188 199)(font "Arial" )) - (text "50.00" (rect 209 185 236 199)(font "Arial" )) - (line (pt 0 0)(pt 377 0)(line_width 1)) - (line (pt 377 0)(pt 377 233)(line_width 1)) - (line (pt 0 233)(pt 377 233)(line_width 1)) - (line (pt 0 0)(pt 0 233)(line_width 1)) - (line (pt 96 164)(pt 246 164)(line_width 1)) - (line (pt 96 181)(pt 246 181)(line_width 1)) - (line (pt 96 199)(pt 246 199)(line_width 1)) - (line (pt 96 164)(pt 96 199)(line_width 1)) - (line (pt 122 164)(pt 122 199)(line_width 3)) - (line (pt 156 164)(pt 156 199)(line_width 3)) - (line (pt 201 164)(pt 201 199)(line_width 3)) - (line (pt 245 164)(pt 245 199)(line_width 1)) - (line (pt 88 56)(pt 288 56)(line_width 1)) - (line (pt 288 56)(pt 288 216)(line_width 1)) - (line (pt 88 216)(pt 288 216)(line_width 1)) - (line (pt 88 56)(pt 88 216)(line_width 1)) + (text "Cyclone III" (rect 250 169 545 349)(font "Arial" )) + (text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" )) + (text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" )) + (text "Clk " (rect 83 126 180 263)(font "Arial" )) + (text "Ratio" (rect 104 126 228 263)(font "Arial" )) + (text "Ph (dg)" (rect 130 126 289 263)(font "Arial" )) + (text "DC (%)" (rect 164 126 358 263)(font "Arial" )) + (text "c0" (rect 86 140 180 291)(font "Arial" )) + (text "2/1" (rect 109 140 228 291)(font "Arial" )) + (text "0.00" (rect 136 140 288 291)(font "Arial" )) + (text "50.00" (rect 168 140 357 291)(font "Arial" )) + (line (pt 0 0)(pt 313 0)) + (line (pt 313 0)(pt 313 186)) + (line (pt 0 186)(pt 313 186)) + (line (pt 0 0)(pt 0 186)) + (line (pt 80 124)(pt 196 124)) + (line (pt 80 137)(pt 196 137)) + (line (pt 80 151)(pt 196 151)) + (line (pt 80 124)(pt 80 151)) + (line (pt 101 124)(pt 101 151)(line_width 3)) + (line (pt 127 124)(pt 127 151)(line_width 3)) + (line (pt 161 124)(pt 161 151)(line_width 3)) + (line (pt 195 124)(pt 195 151)) + (line (pt 72 48)(pt 239 48)) + (line (pt 239 48)(pt 239 168)) + (line (pt 72 168)(pt 239 168)) + (line (pt 72 48)(pt 72 168)) + (line (pt 311 64)(pt 239 64)) + (line (pt 311 80)(pt 239 80)) + (line (pt 311 96)(pt 239 96)) + (line (pt 311 112)(pt 239 112)) ) ) diff --git a/FPGA_Quartus_13.1/altpll4.cmp b/FPGA_Quartus_13.1/altpll4.cmp index 83b3c1e..ac5def2 100644 --- a/FPGA_Quartus_13.1/altpll4.cmp +++ b/FPGA_Quartus_13.1/altpll4.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/FPGA_Quartus_13.1/altpll4.inc b/FPGA_Quartus_13.1/altpll4.inc index 39f54c9..c622d5e 100644 --- a/FPGA_Quartus_13.1/altpll4.inc +++ b/FPGA_Quartus_13.1/altpll4.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/FPGA_Quartus_13.1/altpll4.mif b/FPGA_Quartus_13.1/altpll4.mif index e50eda2..b526227 100644 --- a/FPGA_Quartus_13.1/altpll4.mif +++ b/FPGA_Quartus_13.1/altpll4.mif @@ -1,4 +1,4 @@ --- Copyright (C) 1991-2010 Altera Corporation +-- Copyright (C) 1991-2014 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing @@ -17,8 +17,8 @@ -- Device Part: - -- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) --- File Name: C:\FireBee\FPGA\altpll4.mif --- Generated: Mon Dec 06 01:47:24 2010 +-- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif +-- Generated: Mon Sep 21 17:50:54 2015 WIDTH=1; DEPTH=144; diff --git a/FPGA_Quartus_13.1/altpll4.qip b/FPGA_Quartus_13.1/altpll4.qip index f44acdc..ded02bb 100644 --- a/FPGA_Quartus_13.1/altpll4.qip +++ b/FPGA_Quartus_13.1/altpll4.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name IP_TOOL_VERSION "13.1" set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] diff --git a/FPGA_Quartus_13.1/altpll4.tdf b/FPGA_Quartus_13.1/altpll4.tdf index 3ec77d4..8e72bcc 100644 --- a/FPGA_Quartus_13.1/altpll4.tdf +++ b/FPGA_Quartus_13.1/altpll4.tdf @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -59,7 +59,7 @@ VARIABLE CLK0_MULTIPLY_BY = 2, CLK0_PHASE_SHIFT = "0", COMPENSATE_CLOCK = "CLK0", - INCLK0_INPUT_FREQUENCY = 20833, + INCLK0_INPUT_FREQUENCY = 20824, INTENDED_DEVICE_FAMILY = "Cyclone III", LPM_TYPE = "altpll", OPERATION_MODE = "NORMAL", @@ -113,16 +113,16 @@ VARIABLE BEGIN c0 = altpll_component.clk[0..0]; - scandone = altpll_component.scandone; scandataout = altpll_component.scandataout; + scandone = altpll_component.scandone; locked = altpll_component.locked; - altpll_component.scanclkena = scanclkena; + altpll_component.areset = areset; + altpll_component.configupdate = configupdate; altpll_component.inclk[0..0] = inclk0; altpll_component.inclk[1..1] = GND; - altpll_component.scandata = scandata; - altpll_component.areset = areset; altpll_component.scanclk = scanclk; - altpll_component.configupdate = configupdate; + altpll_component.scanclkena = scanclkena; + altpll_component.scandata = scandata; END; @@ -148,7 +148,7 @@ END; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -156,7 +156,7 @@ END; -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" @@ -166,7 +166,7 @@ END; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" @@ -217,7 +217,7 @@ END; -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" @@ -277,22 +277,22 @@ END; -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 --- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 --- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 --- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 -- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index d4dc2f5..abc22f8 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -2373,7 +2373,7 @@ applicable agreement for further details. (pt 144 40) (output) (text "q[17..0]" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "q[17..0]" (rect 87 34 123 47)(font "Arial" (font_size 8))) + (text "q[17..0]" (rect 87 34 130 47)(font "Arial" (font_size 8))) (line (pt 144 40)(pt 128 40)(line_width 3)) ) (drawing @@ -2401,7 +2401,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 32 16)(pt 48 16)) ) (drawing @@ -2446,7 +2446,7 @@ applicable agreement for further details. (pt 64 40) (output) (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 48 31 65 42)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 31 69 42)(font "Courier New" (bold))(invisible)) (line (pt 56 40)(pt 64 40)) ) (drawing @@ -2475,7 +2475,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2514,7 +2514,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2557,7 +2557,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2600,7 +2600,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2643,7 +2643,7 @@ applicable agreement for further details. (pt 232 24) (output) (text "dataout" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) + (text "dataout" (rect 193 11 236 24)(font "Arial" (font_size 8))) (line (pt 232 24)(pt 152 24)) ) (drawing @@ -2706,7 +2706,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2731,7 +2731,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2756,7 +2756,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2781,7 +2781,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2806,7 +2806,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2831,7 +2831,7 @@ applicable agreement for further details. (pt 48 16) (output) (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 49 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) (line (pt 39 16)(pt 48 16)) ) (drawing @@ -2863,7 +2863,7 @@ applicable agreement for further details. (pt 64 24) (output) (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 48 15 65 26)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) (line (pt 42 24)(pt 64 24)) ) (drawing @@ -2873,110 +2873,6 @@ applicable agreement for further details. (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) ) ) -(symbol - (rect 608 496 984 728) - (text "altpll4" (rect 168 1 210 17)(font "Arial" (font_size 10))) - (text "i_video_clock_pll" (rect 8 213 92 224)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 88 72)) - ) - (port - (pt 0 96) - (input) - (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) - (text "areset" (rect 4 80 40 93)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 88 96)) - ) - (port - (pt 0 120) - (input) - (text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8))) - (text "scanclk" (rect 4 104 48 117)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 88 120)) - ) - (port - (pt 0 144) - (input) - (text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8))) - (text "scandata" (rect 4 128 57 141)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 88 144)) - ) - (port - (pt 0 168) - (input) - (text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8))) - (text "scanclkena" (rect 4 152 68 165)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 88 168)) - ) - (port - (pt 0 192) - (input) - (text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8))) - (text "configupdate" (rect 4 176 77 189)(font "Arial" (font_size 8))) - (line (pt 0 192)(pt 88 192)) - ) - (port - (pt 376 72) - (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 359 56 371 69)(font "Arial" (font_size 8))) - (line (pt 376 72)(pt 288 72)) - ) - (port - (pt 376 96) - (output) - (text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8))) - (text "scandataout" (rect 302 80 361 93)(font "Arial" (font_size 8))) - (line (pt 376 96)(pt 288 96)) - ) - (port - (pt 376 120) - (output) - (text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8))) - (text "scandone" (rect 317 104 364 117)(font "Arial" (font_size 8))) - (line (pt 376 120)(pt 288 120)) - ) - (port - (pt 376 144) - (output) - (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) - (text "locked" (rect 335 128 366 141)(font "Arial" (font_size 8))) - (line (pt 376 144)(pt 288 144)) - ) - (drawing - (text "Cyclone III" (rect 301 214 352 225)(font "Arial" )) - (text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" )) - (text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" )) - (text "Clk " (rect 99 167 119 178)(font "Arial" )) - (text "Ratio" (rect 125 167 152 178)(font "Arial" )) - (text "Ph (dg)" (rect 159 167 196 178)(font "Arial" )) - (text "DC (%)" (rect 204 167 241 178)(font "Arial" )) - (text "c0" (rect 103 185 115 196)(font "Arial" )) - (text "2/1" (rect 131 185 146 196)(font "Arial" )) - (text "0.00" (rect 167 185 190 196)(font "Arial" )) - (text "50.00" (rect 209 185 238 196)(font "Arial" )) - (line (pt 0 0)(pt 377 0)) - (line (pt 377 0)(pt 377 233)) - (line (pt 0 233)(pt 377 233)) - (line (pt 0 0)(pt 0 233)) - (line (pt 96 164)(pt 246 164)) - (line (pt 96 181)(pt 246 181)) - (line (pt 96 199)(pt 246 199)) - (line (pt 96 164)(pt 96 199)) - (line (pt 122 164)(pt 122 199)(line_width 3)) - (line (pt 156 164)(pt 156 199)(line_width 3)) - (line (pt 201 164)(pt 201 199)(line_width 3)) - (line (pt 245 164)(pt 245 199)) - (line (pt 88 56)(pt 288 56)) - (line (pt 288 56)(pt 288 216)) - (line (pt 88 216)(pt 288 216)) - (line (pt 88 56)(pt 88 216)) - ) -) (symbol (rect 456 -352 760 -104) (text "altpll2" (rect 132 1 174 17)(font "Arial" (font_size 10))) @@ -2992,35 +2888,35 @@ applicable agreement for further details. (pt 304 72) (output) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 299 69)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 302 69)(font "Arial" (font_size 8))) (line (pt 304 72)(pt 272 72)) ) (port (pt 304 96) (output) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 287 80 298 93)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 93)(font "Arial" (font_size 8))) (line (pt 304 96)(pt 272 96)) ) (port (pt 304 120) (output) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 287 104 299 117)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 302 117)(font "Arial" (font_size 8))) (line (pt 304 120)(pt 272 120)) ) (port (pt 304 144) (output) (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c3" (rect 287 128 299 141)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 302 141)(font "Arial" (font_size 8))) (line (pt 304 144)(pt 272 144)) ) (port (pt 304 168) (output) (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c4" (rect 287 152 299 165)(font "Arial" (font_size 8))) + (text "c4" (rect 287 152 302 165)(font "Arial" (font_size 8))) (line (pt 304 168)(pt 272 168)) ) (drawing @@ -3172,28 +3068,28 @@ applicable agreement for further details. (pt 328 72) (output) (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 311 56 323 69)(font "Arial" (font_size 8))) + (text "c0" (rect 311 56 326 69)(font "Arial" (font_size 8))) (line (pt 328 72)(pt 272 72)) ) (port (pt 328 96) (output) (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 311 80 322 93)(font "Arial" (font_size 8))) + (text "c1" (rect 311 80 325 93)(font "Arial" (font_size 8))) (line (pt 328 96)(pt 272 96)) ) (port (pt 328 120) (output) (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 311 104 323 117)(font "Arial" (font_size 8))) + (text "c2" (rect 311 104 326 117)(font "Arial" (font_size 8))) (line (pt 328 120)(pt 272 120)) ) (port (pt 328 144) (output) (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) - (text "locked" (rect 287 128 318 141)(font "Arial" (font_size 8))) + (text "locked" (rect 287 128 324 141)(font "Arial" (font_size 8))) (line (pt 328 144)(pt 272 144)) ) (drawing @@ -3321,49 +3217,49 @@ applicable agreement for further details. (pt 216 40) (output) (text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8))) - (text "busy" (rect 171 32 195 45)(font "Arial" (font_size 8))) + (text "busy" (rect 171 32 200 45)(font "Arial" (font_size 8))) (line (pt 216 40)(pt 200 40)) ) (port (pt 216 96) (output) (text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8))) - (text "data_out[8..0]" (rect 129 88 195 101)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 129 88 208 101)(font "Arial" (font_size 8))) (line (pt 216 96)(pt 200 96)(line_width 3)) ) (port (pt 216 152) (output) (text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8))) - (text "pll_scandata" (rect 135 144 195 157)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 135 144 206 157)(font "Arial" (font_size 8))) (line (pt 216 152)(pt 200 152)) ) (port (pt 216 168) (output) (text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8))) - (text "pll_scanclk" (rect 141 160 195 173)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 141 160 205 173)(font "Arial" (font_size 8))) (line (pt 216 168)(pt 200 168)) ) (port (pt 216 200) (output) (text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8))) - (text "pll_scanclkena" (rect 125 192 195 205)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 125 192 208 205)(font "Arial" (font_size 8))) (line (pt 216 200)(pt 200 200)) ) (port (pt 216 216) (output) (text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8))) - (text "pll_configupdate" (rect 117 208 195 221)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 117 208 210 221)(font "Arial" (font_size 8))) (line (pt 216 216)(pt 200 216)) ) (port (pt 216 248) (output) (text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8))) - (text "pll_areset" (rect 148 240 195 253)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 148 240 204 253)(font "Arial" (font_size 8))) (line (pt 216 248)(pt 200 248)) ) (drawing @@ -3377,6 +3273,110 @@ applicable agreement for further details. (line (pt 16 24)(pt 16 273)) ) ) +(symbol + (rect 608 496 984 728) + (text "altpll4" (rect 168 1 210 17)(font "Arial" (font_size 10))) + (text "i_video_clk_pll" (rect 8 213 81 224)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 88 72)) + ) + (port + (pt 0 96) + (input) + (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "areset" (rect 4 80 40 93)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 88 96)) + ) + (port + (pt 0 120) + (input) + (text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 104 48 117)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 88 120)) + ) + (port + (pt 0 144) + (input) + (text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 128 57 141)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 88 144)) + ) + (port + (pt 0 168) + (input) + (text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 152 68 165)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 88 168)) + ) + (port + (pt 0 192) + (input) + (text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 176 77 189)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 88 192)) + ) + (port + (pt 376 72) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 359 56 374 69)(font "Arial" (font_size 8))) + (line (pt 376 72)(pt 288 72)) + ) + (port + (pt 376 96) + (output) + (text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8))) + (text "scandataout" (rect 302 80 372 93)(font "Arial" (font_size 8))) + (line (pt 376 96)(pt 288 96)) + ) + (port + (pt 376 120) + (output) + (text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8))) + (text "scandone" (rect 317 104 373 117)(font "Arial" (font_size 8))) + (line (pt 376 120)(pt 288 120)) + ) + (port + (pt 376 144) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 335 128 372 141)(font "Arial" (font_size 8))) + (line (pt 376 144)(pt 288 144)) + ) + (drawing + (text "Cyclone III" (rect 301 214 352 225)(font "Arial" )) + (text "inclk0 frequency: 48.000 MHz" (rect 98 123 244 134)(font "Arial" )) + (text "Operation Mode: Normal" (rect 98 140 220 151)(font "Arial" )) + (text "Clk " (rect 99 167 119 178)(font "Arial" )) + (text "Ratio" (rect 125 167 152 178)(font "Arial" )) + (text "Ph (dg)" (rect 159 167 196 178)(font "Arial" )) + (text "DC (%)" (rect 204 167 241 178)(font "Arial" )) + (text "c0" (rect 103 185 115 196)(font "Arial" )) + (text "2/1" (rect 131 185 146 196)(font "Arial" )) + (text "0.00" (rect 167 185 190 196)(font "Arial" )) + (text "50.00" (rect 209 185 238 196)(font "Arial" )) + (line (pt 0 0)(pt 377 0)) + (line (pt 377 0)(pt 377 233)) + (line (pt 0 233)(pt 377 233)) + (line (pt 0 0)(pt 0 233)) + (line (pt 96 164)(pt 246 164)) + (line (pt 96 181)(pt 246 181)) + (line (pt 96 199)(pt 246 199)) + (line (pt 96 164)(pt 96 199)) + (line (pt 122 164)(pt 122 199)(line_width 3)) + (line (pt 156 164)(pt 156 199)(line_width 3)) + (line (pt 201 164)(pt 201 199)(line_width 3)) + (line (pt 245 164)(pt 245 199)) + (line (pt 88 56)(pt 288 56)) + (line (pt 288 56)(pt 288 216)) + (line (pt 88 216)(pt 288 216)) + (line (pt 88 56)(pt 88 216)) + ) +) (block (rect 1264 2344 1672 2904) (text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input)) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 06c7dc9..695f220 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,393 +39,393 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_AB12 -to CLK33M -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_E12 -to MIDI_IN -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_AB12 -to CLK33M +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_E12 -to MIDI_IN +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -435,7 +435,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -445,21 +445,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -469,85 +469,85 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- # LogicLock Region Assignments # ============================ -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # end LOGICLOCK_REGION(Root Region) # --------------------------------- @@ -557,190 +557,198 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name DISABLE_OCP_HW_EVAL ON -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name BDF_FILE firebee1.bdf -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt - -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name DISABLE_OCP_HW_EVAL ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON + +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5 +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 49c93c7..3544483 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -19,7 +19,7 @@ ## PROGRAM "Quartus II" ## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" -## DATE "Sun Sep 20 21:23:37 2015" +## DATE "Mon Sep 21 20:39:03 2015" ## ## DEVICE "EP3C40F484C6" @@ -40,13 +40,47 @@ set_time_format -unit ns -decimal_places 3 create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] - +# Clocks used: +# MAIN_CLK 33MHz +# +# PLL1: i_mfp_acia_clk_pll +# input: MAIN_CLK +# c0: 500 kHz +# c1: 2.4576 MHz +# c2: 24.576 MHz +# +# PLL2: i_ddr_clock_pll +# input: MAIN_CLK +# c0: 132 MHz +# c1: 132 MHz +# c2: 132 MHz +# c3: 132 MHz +# c4: 66 MHz +# +# PLL3: i_atari_clk_pll +# input: MAIN_CLK +# c0: 2 MHz +# c1: 16 MHz +# c2: 25 MHz +# c3: 48 MHz +# +# PLL4_ i_video_clk_pll +# input: USB_CLK (48 MHz, PLL3 c3) +# c0: 96 MHz, programmable in 1MHz steps +# #************************************************************** # Create Generated Clock #************************************************************** derive_pll_clocks +# PIXEL_CLK is either +# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO +# where CLK13M is half of CLK25M, +# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable +# clock of i_video_clk_pll +# + #************************************************************** # Set Clock Latency @@ -58,21 +92,23 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.100 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.100 - +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00 derive_clock_uncertainty + #************************************************************** # Set Input Delay #************************************************************** +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}] #************************************************************** # Set Output Delay #************************************************************** +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}] #************************************************************** @@ -85,52 +121,120 @@ derive_clock_uncertainty # Set False Path #************************************************************** -set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] +# +# i_videl_clk is freely programmable +# +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +# MAIN_CLK to 16 MHz clk -> false_path set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] + +# MAIN_CLK to DDR clk and v.v. +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] + + +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] + +# 2 MHz to 33 MHz +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] + +# 16 MHz to 33 MHz +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] + +# 25 MHz to 33 MHz +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] + +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] + +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] -set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|nBLANK}] -to [get_keepers {falconio_sdcard_ide_cf:i_falcon_io_sdcard_ide_cf|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]}] #************************************************************** # Set Multicycle Path #************************************************************** -set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] 8 -set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] 4 -set_multicycle_path -setup -end -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|VDL_VMD[2]}] -to [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|DPO_OFF}] 8 +# Clocks used: +# MAIN_CLK 33MHz +# +# PLL1: i_mfp_acia_clk_pll +# input: MAIN_CLK +# c0: 500 kHz +# c1: 2.4576 MHz +# c2: 24.576 MHz +# +# PLL2: i_ddr_clock_pll +# input: MAIN_CLK +# c0: 132 MHz +# c1: 132 MHz +# c2: 132 MHz +# c3: 132 MHz +# c4: 66 MHz +# +# PLL3: i_atari_clk_pll +# input: MAIN_CLK +# c0: 2 MHz +# c1: 16 MHz +# c2: 25 MHz +# c3: 48 MHz +# +# PLL4_ i_video_clk_pll +# input: USB_CLK (48 MHz, PLL3 c3) +# c0: 96 MHz, programmable in 1MHz steps +# 66 MHz to 33 MHz +set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2 +set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2 +# 33 MHz to 66 MHz +set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 +set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 +# 132 MHz to 33 MHz +set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4 +set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4 +# 33 MHz to 132 MHz +set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4 +set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4 + #************************************************************** # Set Maximum Delay #************************************************************** +# from here to the end of the file statements are just an experiment +#set_max_delay 25 -from [get_ports {*}] #************************************************************** # Set Minimum Delay #************************************************************** - +#set_min_delay 0.5 -from [get_ports {*}] #************************************************************** # Set Input Transition #************************************************************** +#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 +#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 +#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 +#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 From 9180cca701e20ce05aa358f29340ded682ac3c04 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 17 Oct 2015 09:40:48 +0000 Subject: [PATCH 027/127] basically working config. Resolution changes still scramble the screen, however --- FPGA_Quartus_13.1/altpll2.bsf | 234 +++--- FPGA_Quartus_13.1/altpll2.cmp | 52 +- FPGA_Quartus_13.1/altpll2.inc | 54 +- FPGA_Quartus_13.1/altpll2.ppf | 26 +- FPGA_Quartus_13.1/altpll2.qip | 14 +- FPGA_Quartus_13.1/altpll2.vhd | 954 +++++++++++------------ FPGA_Quartus_13.1/firebee1.qsf | 1271 ++++++++++++++++--------------- FPGA_Quartus_13.1/firebee1.qws | Bin 7010 -> 6339 bytes FPGA_Quartus_13.1/firebee1.sdc | 144 ++-- FPGA_Quartus_13.1/firebeei1.qpf | 23 - FPGA_Quartus_13.1/firebeei1.qws | 27 - 11 files changed, 1370 insertions(+), 1429 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebeei1.qpf delete mode 100644 FPGA_Quartus_13.1/firebeei1.qws diff --git a/FPGA_Quartus_13.1/altpll2.bsf b/FPGA_Quartus_13.1/altpll2.bsf index 79679d7..4bad59d 100644 --- a/FPGA_Quartus_13.1/altpll2.bsf +++ b/FPGA_Quartus_13.1/altpll2.bsf @@ -1,117 +1,117 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 304 248) - (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 229 31 244)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 304 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) - (line (pt 304 72)(pt 272 72)(line_width 1)) - ) - (port - (pt 304 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) - (line (pt 304 96)(pt 272 96)(line_width 1)) - ) - (port - (pt 304 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) - (line (pt 304 120)(pt 272 120)(line_width 1)) - ) - (port - (pt 304 144) - (output) - (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) - (line (pt 304 144)(pt 272 144)(line_width 1)) - ) - (port - (pt 304 168) - (output) - (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8))) - (line (pt 304 168)(pt 272 168)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 229 230 277 244)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) - (text "Clk " (rect 59 111 76 125)(font "Arial" )) - (text "Ratio" (rect 85 111 109 125)(font "Arial" )) - (text "Ph (dg)" (rect 119 111 154 125)(font "Arial" )) - (text "DC (%)" (rect 164 111 199 125)(font "Arial" )) - (text "c0" (rect 63 129 75 143)(font "Arial" )) - (text "4/1" (rect 91 129 106 143)(font "Arial" )) - (text "240.00" (rect 120 129 153 143)(font "Arial" )) - (text "50.00" (rect 169 129 196 143)(font "Arial" )) - (text "c1" (rect 63 147 75 161)(font "Arial" )) - (text "4/1" (rect 91 147 106 161)(font "Arial" )) - (text "0.00" (rect 127 147 148 161)(font "Arial" )) - (text "50.00" (rect 169 147 196 161)(font "Arial" )) - (text "c2" (rect 63 165 75 179)(font "Arial" )) - (text "4/1" (rect 91 165 106 179)(font "Arial" )) - (text "180.00" (rect 120 165 153 179)(font "Arial" )) - (text "50.00" (rect 169 165 196 179)(font "Arial" )) - (text "c3" (rect 63 183 75 197)(font "Arial" )) - (text "4/1" (rect 91 183 106 197)(font "Arial" )) - (text "105.00" (rect 120 183 153 197)(font "Arial" )) - (text "50.00" (rect 169 183 196 197)(font "Arial" )) - (text "c4" (rect 63 201 75 215)(font "Arial" )) - (text "2/1" (rect 91 201 106 215)(font "Arial" )) - (text "270.00" (rect 120 201 153 215)(font "Arial" )) - (text "50.00" (rect 169 201 196 215)(font "Arial" )) - (line (pt 0 0)(pt 305 0)(line_width 1)) - (line (pt 305 0)(pt 305 249)(line_width 1)) - (line (pt 0 249)(pt 305 249)(line_width 1)) - (line (pt 0 0)(pt 0 249)(line_width 1)) - (line (pt 56 108)(pt 206 108)(line_width 1)) - (line (pt 56 125)(pt 206 125)(line_width 1)) - (line (pt 56 143)(pt 206 143)(line_width 1)) - (line (pt 56 161)(pt 206 161)(line_width 1)) - (line (pt 56 179)(pt 206 179)(line_width 1)) - (line (pt 56 197)(pt 206 197)(line_width 1)) - (line (pt 56 215)(pt 206 215)(line_width 1)) - (line (pt 56 108)(pt 56 215)(line_width 1)) - (line (pt 82 108)(pt 82 215)(line_width 3)) - (line (pt 116 108)(pt 116 215)(line_width 3)) - (line (pt 161 108)(pt 161 215)(line_width 3)) - (line (pt 205 108)(pt 205 215)(line_width 1)) - (line (pt 48 56)(pt 272 56)(line_width 1)) - (line (pt 272 56)(pt 272 232)(line_width 1)) - (line (pt 48 232)(pt 272 232)(line_width 1)) - (line (pt 48 56)(pt 48 232)(line_width 1)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2014 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 256 200) + (text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 185 26 196)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 256 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + ) + (port + (pt 256 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) + ) + (port + (pt 256 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8))) + ) + (port + (pt 256 112) + (output) + (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8))) + ) + (port + (pt 256 128) + (output) + (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone III" (rect 198 186 442 382)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) + (text "Clk " (rect 51 91 117 192)(font "Arial" )) + (text "Ratio" (rect 71 91 165 192)(font "Arial" )) + (text "Ph (dg)" (rect 97 91 225 192)(font "Arial" )) + (text "DC (%)" (rect 132 91 296 192)(font "Arial" )) + (text "c0" (rect 54 104 119 218)(font "Arial" )) + (text "4/1" (rect 76 104 165 218)(font "Arial" )) + (text "240.00" (rect 98 104 225 218)(font "Arial" )) + (text "50.00" (rect 136 104 296 218)(font "Arial" )) + (text "c1" (rect 54 117 118 244)(font "Arial" )) + (text "4/1" (rect 76 117 165 244)(font "Arial" )) + (text "0.00" (rect 103 117 225 244)(font "Arial" )) + (text "50.00" (rect 136 117 296 244)(font "Arial" )) + (text "c2" (rect 54 130 119 270)(font "Arial" )) + (text "4/1" (rect 76 130 165 270)(font "Arial" )) + (text "180.00" (rect 98 130 224 270)(font "Arial" )) + (text "50.00" (rect 136 130 296 270)(font "Arial" )) + (text "c3" (rect 54 143 119 296)(font "Arial" )) + (text "4/1" (rect 76 143 165 296)(font "Arial" )) + (text "105.00" (rect 98 143 224 296)(font "Arial" )) + (text "50.00" (rect 136 143 296 296)(font "Arial" )) + (text "c4" (rect 54 156 119 322)(font "Arial" )) + (text "2/1" (rect 76 156 165 322)(font "Arial" )) + (text "270.00" (rect 98 156 225 322)(font "Arial" )) + (text "50.00" (rect 136 156 296 322)(font "Arial" )) + (line (pt 0 0)(pt 257 0)) + (line (pt 257 0)(pt 257 201)) + (line (pt 0 201)(pt 257 201)) + (line (pt 0 0)(pt 0 201)) + (line (pt 48 89)(pt 164 89)) + (line (pt 48 101)(pt 164 101)) + (line (pt 48 114)(pt 164 114)) + (line (pt 48 127)(pt 164 127)) + (line (pt 48 140)(pt 164 140)) + (line (pt 48 153)(pt 164 153)) + (line (pt 48 166)(pt 164 166)) + (line (pt 48 89)(pt 48 166)) + (line (pt 68 89)(pt 68 166)(line_width 3)) + (line (pt 94 89)(pt 94 166)(line_width 3)) + (line (pt 129 89)(pt 129 166)(line_width 3)) + (line (pt 163 89)(pt 163 166)) + (line (pt 40 48)(pt 223 48)) + (line (pt 223 48)(pt 223 183)) + (line (pt 40 183)(pt 223 183)) + (line (pt 40 48)(pt 40 183)) + (line (pt 255 64)(pt 223 64)) + (line (pt 255 80)(pt 223 80)) + (line (pt 255 96)(pt 223 96)) + (line (pt 255 112)(pt 223 112)) + (line (pt 255 128)(pt 223 128)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll2.cmp b/FPGA_Quartus_13.1/altpll2.cmp index c6fe758..2a70d95 100644 --- a/FPGA_Quartus_13.1/altpll2.cmp +++ b/FPGA_Quartus_13.1/altpll2.cmp @@ -1,26 +1,26 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altpll2 - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; - c4 : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll2 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll2.inc b/FPGA_Quartus_13.1/altpll2.inc index e75913b..db081f6 100644 --- a/FPGA_Quartus_13.1/altpll2.inc +++ b/FPGA_Quartus_13.1/altpll2.inc @@ -1,27 +1,27 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altpll2 -( - inclk0 -) - -RETURNS ( - c0, - c1, - c2, - c3, - c4 -); +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll2 +( + inclk0 +) + +RETURNS ( + c0, + c1, + c2, + c3, + c4 +); diff --git a/FPGA_Quartus_13.1/altpll2.ppf b/FPGA_Quartus_13.1/altpll2.ppf index b1c71cc..0e421c1 100644 --- a/FPGA_Quartus_13.1/altpll2.ppf +++ b/FPGA_Quartus_13.1/altpll2.ppf @@ -1,13 +1,13 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll2.qip b/FPGA_Quartus_13.1/altpll2.qip index 74cc641..294e5db 100644 --- a/FPGA_Quartus_13.1/altpll2.qip +++ b/FPGA_Quartus_13.1/altpll2.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"] diff --git a/FPGA_Quartus_13.1/altpll2.vhd b/FPGA_Quartus_13.1/altpll2.vhd index 2c55f08..c79f465 100644 --- a/FPGA_Quartus_13.1/altpll2.vhd +++ b/FPGA_Quartus_13.1/altpll2.vhd @@ -1,477 +1,477 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: altpll2.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY altpll2 IS - PORT - ( - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC ; - c4 : OUT STD_LOGIC - ); -END altpll2; - - -ARCHITECTURE SYN OF altpll2 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC ; - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - clk3_divide_by : NATURAL; - clk3_duty_cycle : NATURAL; - clk3_multiply_by : NATURAL; - clk3_phase_shift : STRING; - clk4_divide_by : NATURAL; - clk4_duty_cycle : NATURAL; - clk4_multiply_by : NATURAL; - clk4_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - width_clock : NATURAL - ); - PORT ( - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - sub_wire8_bv(0 DOWNTO 0) <= "0"; - sub_wire8 <= To_stdlogicvector(sub_wire8_bv); - sub_wire5 <= sub_wire0(4); - sub_wire4 <= sub_wire0(3); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - c3 <= sub_wire4; - c4 <= sub_wire5; - sub_wire6 <= inclk0; - sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 1, - clk0_duty_cycle => 50, - clk0_multiply_by => 4, - clk0_phase_shift => "5051", - clk1_divide_by => 1, - clk1_duty_cycle => 50, - clk1_multiply_by => 4, - clk1_phase_shift => "0", - clk2_divide_by => 1, - clk2_duty_cycle => 50, - clk2_multiply_by => 4, - clk2_phase_shift => "3788", - clk3_divide_by => 1, - clk3_duty_cycle => 50, - clk3_multiply_by => 4, - clk3_phase_shift => "2210", - clk4_divide_by => 1, - clk4_duty_cycle => 50, - clk4_multiply_by => 2, - clk4_phase_shift => "11364", - compensate_clock => "CLK0", - inclk0_input_frequency => 30303, - intended_device_family => "Cyclone III", - lpm_type => "altpll", - operation_mode => "SOURCE_SYNCHRONOUS", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_UNUSED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_USED", - port_clk4 => "PORT_USED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - width_clock => 5 - ) - PORT MAP ( - inclk => sub_wire7, - clk => sub_wire0 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" --- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000" --- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLK3 STRING "1" --- Retrieval info: PRIVATE: USE_CLK4 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" --- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210" --- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" --- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll2.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY altpll2 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + c4 : OUT STD_LOGIC + ); +END altpll2; + + +ARCHITECTURE SYN OF altpll2 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + clk4_divide_by : NATURAL; + clk4_duty_cycle : NATURAL; + clk4_multiply_by : NATURAL; + clk4_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire5 <= sub_wire0(4); + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; + c4 <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "5051", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + clk2_divide_by => 1, + clk2_duty_cycle => 50, + clk2_multiply_by => 4, + clk2_phase_shift => "3788", + clk3_divide_by => 1, + clk3_duty_cycle => 50, + clk3_multiply_by => 4, + clk3_phase_shift => "2210", + clk4_divide_by => 1, + clk4_duty_cycle => 50, + clk4_multiply_by => 2, + clk4_phase_shift => "11364", + compensate_clock => "CLK0", + inclk0_input_frequency => 30303, + intended_device_family => "Cyclone III", + lpm_type => "altpll", + operation_mode => "SOURCE_SYNCHRONOUS", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_USED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire7, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4" +-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK4 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210" +-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 695f220..f167edb 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,393 +39,393 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_AB12 -to CLK33M -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_E12 -to MIDI_IN -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_AB12 -to CLK33M +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_E12 -to MIDI_IN +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -435,7 +435,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -445,21 +445,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -469,85 +469,85 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- # LogicLock Region Assignments # ============================ -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # end LOGICLOCK_REGION(Root Region) # --------------------------------- @@ -557,198 +557,205 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name DISABLE_OCP_HW_EVAL ON -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name DISABLE_OCP_HW_EVAL ON +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5 -set_global_assignment -name ECO_OPTIMIZE_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name BDF_FILE firebee1.bdf -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5 +set_global_assignment -name ECO_OPTIMIZE_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation + +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index c422e6822462699cd0e9c3feebdc13054bbe201d..45ccb00133c94c66c2f6abd890f9ae092b620d40 100644 GIT binary patch delta 828 zcma)3&nrYx6#nj;=U0kQ!(&V`Q5L-SX2wu97VJhT3JVRxOhZIW79^Cg5?yPiZ0#ni zvGWi31C)}#LNUI3XQG)JyxTeNp6{Ofo$sFW8hLatY;kt!Y;@X4Vg*}BAWlob#Q>JD zOcbb?u+4;}VuI|bvrO)<$ku1`APyUgSVJ0{^lOM=Snq>mP8XSfNnXVcw(-wom&!w2 zKg=hTabRN%Q<$WX!he9ADV7FmX;JJ^l1q_c)=BVs5dB1k_@)SVF4r=xpBWCH<8bG2 z1!;?HOp-oCuWs(EF0f7t8(1e|(1Q?Gn-c{LAY{thD`#q>1*D^H!Vs#zJ^va;He+22zvqpt z&pPNR+iqwpYERG?qu+bk#Z0jC}VFHf5L_M?TM7^GTtcz=H7UF5K`;e?0zF HrUCIKlVzwicm*jUbd~%=;<7~B3Y<7)38^Y?8OmjOY5Y}s(AEs)D{_UlwY`>ji@xJB zEpu{TCK&kzz2xb&L0yMdJ<9Yp4Yz_ORauo8c}UA+Mwm2N7itD-ih2^s(@77a<&wC} z?gL+TW_Bg!Si@F}Xg)ytj`$E3bLa%doAZ%UY%+ z2JOJrw?ss3+bnCUTyR!Bu#|rnb5s%2 zO=9KrBMwHsfBR}3=@^!xZ|M1_PcfszwBkL5DU)Ei2$~hQG4di$@d)0>tTl-D5oGn> zqj(RKU)x_;Bz5a}G+I9#KTZN5!VRH1u z?GSd3$)^7YJRGJePDqhw{ED`AG!T#cp}0j*o#%*GVVr)#mJ;P8b@L)y%ewbvbPI7; z&wvCFS?vY-Vq8n;49^_!wLeTl8%uVy)ms2d82+DTCG3)>xoIj`Ttc&y-8RGk&nTdA z0f+-fZzA+=O>Y$yQVEthZI6RY34Yq@u-!G-9ilEv_eRXSyz?=D_wA*Q24JSe35VPN DC&rj2 diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 3544483..5e6d787 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -1,30 +1,47 @@ -## Generated SDC file "firebee1.sdc" - -## Copyright (C) 1991-2014 Altera Corporation -## Your use of Altera Corporation's design tools, logic functions -## and other software and tools, and its AMPP partner logic -## functions, and any output files from any of the foregoing -## (including device programming or simulation files), and any -## associated documentation or information are expressly subject -## to the terms and conditions of the Altera Program License -## Subscription Agreement, Altera MegaCore Function License -## Agreement, or other applicable license agreement, including, -## without limitation, that your use is for the sole purpose of -## programming logic devices manufactured by Altera and sold by -## Altera or its authorized distributors. Please refer to the -## applicable agreement for further details. - - -## VENDOR "Altera" -## PROGRAM "Quartus II" -## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" - -## DATE "Mon Sep 21 20:39:03 2015" - -## -## DEVICE "EP3C40F484C6" -## - +#--------------------------------------------------------------# +# # +# Synopsis design constraints for the Firebee project # +# # +# This file is part of the Firebee ACP project. # +# http://www.experiment-s.de # +# # +# Description: # +# timing constraints for the Firebee VHDL config # +# # +# # +# # +# To Do: # +# - # +# # +# Author(s): # +# Markus Fröschle, mfro@mubf.de # +# # +#--------------------------------------------------------------# +# # +# Copyright (C) 2015 Markus Fröschle & the ACP project # +# # +# This source file may be used and distributed without # +# restriction provided that this copyright statement is not # +# removed from the file and that any derivative work contains # +# the original copyright notice and the associated disclaimer. # +# # +# This source file is free software; you can redistribute it # +# and/or modify it under the terms of the GNU Lesser General # +# Public License as published by the Free Software Foundation; # +# either version 2.1 of the License, or (at your option) any # +# later version. # +# # +# This source is distributed in the hope that it will be # +# useful, but WITHOUT ANY WARRANTY; without even the implied # +# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR # +# PURPOSE. See the GNU Lesser General Public License for more # +# details. # +# # +# You should have received a copy of the GNU Lesser General # +# Public License along with this source; if not, download it # +# from http://www.gnu.org/licenses/lgpl.html # +# # +################################################################ #************************************************************** # Time Information @@ -51,11 +68,11 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por # # PLL2: i_ddr_clock_pll # input: MAIN_CLK -# c0: 132 MHz -# c1: 132 MHz -# c2: 132 MHz -# c3: 132 MHz -# c4: 66 MHz +# c0: 132 MHz 190° +# c1: 132 MHz 0° +# c2: 132 MHz 180° +# c3: 132 MHz 105° +# c4: 66 MHz 270° # # PLL3: i_atari_clk_pll # input: MAIN_CLK @@ -101,14 +118,14 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs] #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs] #************************************************************** @@ -122,7 +139,7 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {F #************************************************************** # -# i_videl_clk is freely programmable +# i_video_clk is freely programmable # set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] @@ -133,9 +150,6 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl # MAIN_CLK to DDR clk and v.v. set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] - set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] @@ -174,48 +188,6 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip # Set Multicycle Path #************************************************************** -# Clocks used: -# MAIN_CLK 33MHz -# -# PLL1: i_mfp_acia_clk_pll -# input: MAIN_CLK -# c0: 500 kHz -# c1: 2.4576 MHz -# c2: 24.576 MHz -# -# PLL2: i_ddr_clock_pll -# input: MAIN_CLK -# c0: 132 MHz -# c1: 132 MHz -# c2: 132 MHz -# c3: 132 MHz -# c4: 66 MHz -# -# PLL3: i_atari_clk_pll -# input: MAIN_CLK -# c0: 2 MHz -# c1: 16 MHz -# c2: 25 MHz -# c3: 48 MHz -# -# PLL4_ i_video_clk_pll -# input: USB_CLK (48 MHz, PLL3 c3) -# c0: 96 MHz, programmable in 1MHz steps - - -# 66 MHz to 33 MHz -set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2 -set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2 -# 33 MHz to 66 MHz -set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 -set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 -# 132 MHz to 33 MHz -set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4 -set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4 -# 33 MHz to 132 MHz -set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4 -set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4 - #************************************************************** # Set Maximum Delay #************************************************************** @@ -238,3 +210,15 @@ set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks { #set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 #set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 +# restrict timing of video controller + +#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}] +#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}] + +#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}] +#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}] + +#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}] +#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}] +#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}] +#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}] diff --git a/FPGA_Quartus_13.1/firebeei1.qpf b/FPGA_Quartus_13.1/firebeei1.qpf deleted file mode 100644 index 8ab6c97..0000000 --- a/FPGA_Quartus_13.1/firebeei1.qpf +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (C) 1991-2008 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - - -QUARTUS_VERSION = "8.1" -DATE = "10:07:29 September 03, 2009" - - -# Revisions - -PROJECT_REVISION = "firebee1" diff --git a/FPGA_Quartus_13.1/firebeei1.qws b/FPGA_Quartus_13.1/firebeei1.qws deleted file mode 100644 index 89bdcec..0000000 --- a/FPGA_Quartus_13.1/firebeei1.qws +++ /dev/null @@ -1,27 +0,0 @@ -[ProjectWorkspace] -ptn_Child1=Frames -[ProjectWorkspace.Frames] -ptn_Child1=ChildFrames -[ProjectWorkspace.Frames.ChildFrames] -ptn_Child1=Document-0 -ptn_Child2=Document-1 -ptn_Child3=Document-2 -ptn_Child4=Document-3 -[ProjectWorkspace.Frames.ChildFrames.Document-0] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=firebee1.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} -IsChildFrameDetached=False -IsActiveChildFrame=False -ptn_Child1=StateMap -[ProjectWorkspace.Frames.ChildFrames.Document-1] -ptn_Child1=ViewFrame-0 -[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0] -DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2} -IsChildFrameDetached=False -IsActiveChildFrame=False -ptn_Child1=StateMap -[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap] -AFC_IN_REPORT=False From 602c20bb303a2efc65c7ee393a60d6117e7dfbce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 17 Oct 2015 10:58:27 +0000 Subject: [PATCH 028/127] add missing project file --- FPGA_Quartus_13.1/firebee1.qpf | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 FPGA_Quartus_13.1/firebee1.qpf diff --git a/FPGA_Quartus_13.1/firebee1.qpf b/FPGA_Quartus_13.1/firebee1.qpf new file mode 100644 index 0000000..8ab6c97 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2008 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "8.1" +DATE = "10:07:29 September 03, 2009" + + +# Revisions + +PROJECT_REVISION = "firebee1" From 7f4b30f48314cab90ebaee6cb4f86c1bccc6e319 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 17 Oct 2015 16:10:06 +0000 Subject: [PATCH 029/127] changed component name to lower case --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index d22c642..a9a9be7 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -1,4 +1,4 @@ -TITLE "DDR_CTR"; +TITLE "ddr_ctr"; -- CREATED BY FREDI ASCHWANDEN @@ -12,7 +12,7 @@ CONSTANT FIFO_HWM = 500; -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -SUBDESIGN DDR_CTR +SUBDESIGN ddr_ctr ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! FB_ADR[31..0] : INPUT; From 8b7fe5f731076450126924e7635b7b4f450fe25b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 18 Oct 2015 00:57:04 +0000 Subject: [PATCH 030/127] fix timing (set_false_path was missing) --- FPGA_Quartus_13.1/firebee1.sdc | 1 + 1 file changed, 1 insertion(+) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 5e6d787..9ea7e2a 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -150,6 +150,7 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl # MAIN_CLK to DDR clk and v.v. set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] From 56adcdd21803a0dedb61cc8cbc34674d261bffcc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 18 Oct 2015 01:02:05 +0000 Subject: [PATCH 031/127] added another false path to fix timing --- FPGA_Quartus_13.1/firebee1.sdc | 1 + 1 file changed, 1 insertion(+) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 9ea7e2a..a28e73e 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -150,6 +150,7 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl # MAIN_CLK to DDR clk and v.v. set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] From 13032a8635319a38349d1a4b590b07f5aee822db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 18 Oct 2015 19:27:57 +0000 Subject: [PATCH 032/127] reformat --- .../WF_UART6850_IP/wf6850ip_top_soc.vhd | 238 +++++++++--------- 1 file changed, 121 insertions(+), 117 deletions(-) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd index bb806d6..be34852 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -59,121 +59,122 @@ -- Introduced a minor RTSn correction. -- -library ieee; - use ieee.std_logic_1164.all; - use ieee.std_logic_unsigned.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; -entity WF6850IP_TOP_SOC is - port ( - CLK : in bit; +ENTITY WF6850IP_TOP_SOC IS + PORT ( + CLK : IN bit; RESETn : in bit; - CS2n, CS1, CS0 : in bit; - E : in bit; - RWn : in bit; + CS2n, CS1, CS0 : IN bit; + E : IN bit; + RWn : IN bit; RS : in bit; - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out bit; + DATA_IN : IN std_logic_vector(7 DOWNTO 0); + DATA_OUT : OUT std_logic_vector(7 DOWNTO 0); + DATA_EN : OUT bit; - TXCLK : in bit; - RXCLK : in bit; - RXDATA : in bit; - CTSn : in bit; - DCDn : in bit; + TXCLK : IN bit; + RXCLK : IN bit; + RXDATA : IN bit; + CTSn : IN bit; + DCDn : IN bit; - IRQn : out bit; - TXDATA : out bit; - RTSn : out bit + IRQn : OUT bit; + TXDATA : OUT bit; + RTSn : OUT bit ); -end entity WF6850IP_TOP_SOC; +END ENTITY WF6850IP_TOP_SOC; -architecture STRUCTURE of WF6850IP_TOP_SOC is -component WF6850IP_CTRL_STATUS - port ( - CLK : in bit; - RESETn : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - RDRF : in bit; - TDRE : in bit; - DCDn : in bit; - CTSn : in bit; - FE : in bit; - OVR : in bit; - PE : in bit; - MCLR : out bit; - RTSn : out bit; - CDS : out bit_vector(1 downto 0); - WS : out bit_vector(2 downto 0); - TC : out bit_vector(1 downto 0); - IRQn : out bit +ARCHITECTURE structure OF WF6850IP_TOP_SOC IS + COMPONENT WF6850IP_CTRL_STATUS + PORT ( + CLK : IN bit; + RESETn : IN bit; + CS : IN bit_vector(2 DOWNTO 0); + E : IN bit; + RWn : IN bit; + RS : IN bit; + DATA_IN : IN bit_vector(7 DOWNTO 0); + DATA_OUT : OUT bit_vector(7 DOWNTO 0); + DATA_EN : OUT bit; + RDRF : IN bit; + TDRE : IN bit; + DCDn : IN bit; + CTSn : IN bit; + FE : IN bit; + OVR : IN bit; + PE : IN bit; + MCLR : OUT bit; + RTSn : OUT bit; + CDS : OUT bit_vector(1 DOWNTO 0); + WS : OUT bit_vector(2 DOWNTO 0); + TC : OUT bit_vector(1 DOWNTO 0); + IRQn : OUT bit ); -end component; + END COMPONENT; -component WF6850IP_RECEIVE - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - RXCLK : in bit; - RXDATA : in bit; - RDRF : out bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end component; - -component WF6850IP_TRANSMIT - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - CTSn : in bit; - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - TXCLK : in bit; - TDRE : out bit; - TXDATA : out bit - ); -end component; -signal DATA_IN_I : bit_vector(7 downto 0); -signal DATA_RX : bit_vector(7 downto 0); -signal DATA_RX_EN : bit; -signal DATA_CTRL : bit_vector(7 downto 0); -signal DATA_CTRL_EN : bit; -signal RDRF_I : bit; -signal TDRE_I : bit; -signal FE_I : bit; -signal OVR_I : bit; -signal PE_I : bit; -signal MCLR_I : bit; -signal CDS_I : bit_vector(1 downto 0); -signal WS_I : bit_vector(2 downto 0); -signal TC_I : bit_vector(1 downto 0); -signal IRQ_In : bit; -begin + COMPONENT WF6850IP_RECEIVE + PORT ( + CLK : IN bit; + RESETn : IN bit; + MCLR : IN bit; + CS : IN bit_vector(2 DOWNTO 0); + E : IN bit; + RWn : IN bit; + RS : IN bit; + DATA_OUT : OUT bit_vector(7 DOWNTO 0); + DATA_EN : OUT bit; + WS : IN bit_vector(2 DOWNTO 0); + CDS : IN bit_vector(1 DOWNTO 0); + RXCLK : IN bit; + RXDATA : IN bit; + RDRF : OUT bit; + OVR : OUT bit; + PE : OUT bit; + FE : OUT bit + ); + END COMPONENT; + + COMPONENT WF6850IP_TRANSMIT + PORT ( + CLK : IN bit; + RESETn : IN bit; + MCLR : IN bit; + CS : IN bit_vector(2 DOWNTO 0); + E : IN bit; + RWn : IN bit; + RS : IN bit; + DATA_IN : IN bit_vector(7 DOWNTO 0); + CTSn : IN bit; + TC : IN bit_vector(1 DOWNTO 0); + WS : IN bit_vector(2 DOWNTO 0); + CDS : IN bit_vector(1 DOWNTO 0); + TXCLK : IN bit; + TDRE : OUT bit; + TXDATA : OUT bit + ); + END COMPONENT; + + SIGNAL DATA_IN_I : bit_vector(7 DOWNTO 0); + SIGNAL DATA_RX : bit_vector(7 DOWNTO 0); + SIGNAL DATA_RX_EN : bit; + SIGNAL DATA_CTRL : bit_vector(7 DOWNTO 0); + SIGNAL DATA_CTRL_EN : bit; + SIGNAL RDRF_I : bit; + SIGNAL TDRE_I : bit; + SIGNAL FE_I : bit; + SIGNAL OVR_I : bit; + SIGNAL PE_I : bit; + SIGNAL MCLR_I : bit; + SIGNAL CDS_I : bit_vector(1 DOWNTO 0); + SIGNAL WS_I : bit_vector(2 DOWNTO 0); + SIGNAL TC_I : bit_vector(1 DOWNTO 0); + SIGNAL IRQ_In : bit; +BEGIN DATA_IN_I <= To_BitVector(DATA_IN); DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else @@ -182,13 +183,14 @@ begin IRQn <= '0' when IRQ_In = '0' else '1'; I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS - port map( - CLK => CLK, - RESETn => RESETn, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, + PORT MAP + ( + CLK => CLK, + RESETn => RESETn, + CS(2) => CS2n, + CS(1) => CS1, + CS(0) => CS0, + E => E, RWn => RWn, RS => RS, DATA_IN => DATA_IN_I, @@ -207,10 +209,11 @@ begin WS => WS_I, TC => TC_I, IRQn => IRQ_In - ); + ); I_UART_RECEIVE: WF6850IP_RECEIVE - port map ( + PORT MAP + ( CLK => CLK, RESETn => RESETn, MCLR => MCLR_I, @@ -230,10 +233,11 @@ begin OVR => OVR_I, PE => PE_I, FE => FE_I - ); + ); I_UART_TRANSMIT: WF6850IP_TRANSMIT - port map ( + PORT MAP + ( CLK => CLK, RESETn => RESETn, MCLR => MCLR_I, @@ -251,5 +255,5 @@ begin TDRE => TDRE_I, TXCLK => TXCLK, TXDATA => TXDATA - ); -end architecture STRUCTURE; \ No newline at end of file + ); +END ARCHITECTURE structure; \ No newline at end of file From 1c661c8052ffe029269e98a675ee88fe942a4c00 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 18 Oct 2015 19:33:25 +0000 Subject: [PATCH 033/127] formatting --- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 58 ++++++++++----------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index 63cc93f..04aeb66 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -21,47 +21,43 @@ -- Created on Fri Oct 16 15:40:59 2009 LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; ENTITY blitter IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); - BLITTER_ON : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); + BLITTER_ON : IN STD_LOGIC; + FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END BLITTER; --- Architecture Body - -ARCHITECTURE BLITTER_architecture OF blitter IS +ARCHITECTURE rtl OF blitter IS BEGIN @@ -72,4 +68,4 @@ BEGIN BLITTER_WR <= '0'; BLITTER_TA <= '0'; -END BLITTER_architecture; +END rtl; From fc8034d93b16d353f6ba7379142d0afe8d038cb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 26 Oct 2015 06:48:18 +0000 Subject: [PATCH 034/127] patch with Fredi's lp fix (and others) --- .../FalconIO_SDCard_IDE_CF.vhd | 435 +- .../WF_SND2149_IP/wf2149ip_pkg.vhd | 2 +- .../WF_SND2149_IP/wf2149ip_top_soc.vhd | 15 +- .../WF_SND2149_IP/wf2149ip_wave.vhd | 2 +- .../WF_UART6850_IP/wf6850ip_ctrl_status.vhd | 96 +- .../WF_UART6850_IP/wf6850ip_receive.vhd | 619 +-- .../WF_UART6850_IP/wf6850ip_top_soc.vhd | 10 +- .../WF_UART6850_IP/wf6850ip_transmit.vhd | 45 +- .../Interrupt_Handler/interrupt_handler.tdf | 216 +- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 47 +- .../Video/BLITTER/altsyncram0.qip | 6 + .../Video/BLITTER/lpm_clshift0.qip | 6 + .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 127 +- FPGA_Quartus_13.1/Video/Video.bdf | 4080 +++++++------- FPGA_Quartus_13.1/altiobuf_bidir0.qip | 6 + FPGA_Quartus_13.1/altpll1.bsf | 114 +- FPGA_Quartus_13.1/altpll1.cmp | 2 +- FPGA_Quartus_13.1/altpll1.inc | 2 +- FPGA_Quartus_13.1/altpll1.qip | 2 +- FPGA_Quartus_13.1/altpll1.vhd | 64 +- FPGA_Quartus_13.1/altpll2.bsf | 152 +- FPGA_Quartus_13.1/altpll2.cmp | 2 +- FPGA_Quartus_13.1/altpll2.inc | 2 +- FPGA_Quartus_13.1/altpll2.qip | 2 +- FPGA_Quartus_13.1/altpll2.vhd | 32 +- FPGA_Quartus_13.1/altpll3.bsf | 139 +- FPGA_Quartus_13.1/altpll3.cmp | 5 +- FPGA_Quartus_13.1/altpll3.inc | 5 +- FPGA_Quartus_13.1/altpll3.ppf | 1 + FPGA_Quartus_13.1/altpll3.qip | 2 +- FPGA_Quartus_13.1/altpll3.vhd | 140 +- FPGA_Quartus_13.1/altpll4.bsf | 156 +- FPGA_Quartus_13.1/altpll4.cmp | 2 +- FPGA_Quartus_13.1/altpll4.inc | 2 +- FPGA_Quartus_13.1/altpll4.mif | 6 +- FPGA_Quartus_13.1/altpll4.qip | 2 +- FPGA_Quartus_13.1/altpll4.tdf | 44 +- FPGA_Quartus_13.1/firebee1.bdf | 4805 ++++++++--------- FPGA_Quartus_13.1/firebee1.qsf | 291 +- FPGA_Quartus_13.1/firebee1.sdc | 17 +- FPGA_Quartus_13.1/lpm_counter1.qip | 6 + FPGA_Quartus_13.1/lpm_mux0.qip | 6 + FPGA_Quartus_13.1/lpm_shiftreg0.qip | 6 + 43 files changed, 5765 insertions(+), 5956 deletions(-) create mode 100644 FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip create mode 100644 FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip create mode 100644 FPGA_Quartus_13.1/altiobuf_bidir0.qip create mode 100644 FPGA_Quartus_13.1/lpm_counter1.qip create mode 100644 FPGA_Quartus_13.1/lpm_mux0.qip create mode 100644 FPGA_Quartus_13.1/lpm_shiftreg0.qip diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index b994a78..a5dbf21 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -115,7 +115,7 @@ ENTITY falconio_sdcard_ide_cf IS nCF_CS0 : OUT std_logic; nIDE_RD : INOUT std_logic; nIDE_WR : INOUT std_logic; - AMKB_TX : OUT std_logic; + AMKB_TX : buffer std_logic; IDE_RES : OUT std_logic; DTR : OUT std_logic; RTS : OUT std_logic; @@ -132,6 +132,7 @@ ENTITY falconio_sdcard_ide_cf IS DMA_DRQ : OUT std_logic; FB_AD : INOUT std_logic_vector(31 DOWNTO 0); LP_D : INOUT std_logic_vector(7 DOWNTO 0); + SND_A : INOUT std_logic_vector(7 downto 0); ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); SCSI_PAR : INOUT std_logic; @@ -141,14 +142,13 @@ ENTITY falconio_sdcard_ide_cf IS SD_CD_DATA3 : INOUT std_logic; SD_CDM_D1 : INOUT std_logic ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END falconio_sdcard_ide_cf; -- Architecture Body -ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS +ARCHITECTURE rtl OF FalconIO_SDCard_IDE_CF IS -- system SIGNAL SYS_CLK : std_logic; SIGNAL RESETn : std_logic; @@ -156,12 +156,15 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS SIGNAL BYT : std_logic; -- WENN BYT -> 1 SIGNAL LONG : std_logic; -- WENN -> 1 +signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten +signal nResetatio : STD_LOGIC; -- reset atari bausteine -- KEYBOARD MIDI SIGNAL ACIA_CS_I : std_logic; SIGNAL IRQ_KEYBDn : std_logic; SIGNAL IRQ_MIDIn : std_logic; SIGNAL KEYB_RxD : std_logic; - SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); +signal AMKB_REG : STD_LOGIC_VECTOR(3 downto 0); +signal AMKB_TX_sync : std_logic; SIGNAL MIDI_OUT : std_logic; SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); @@ -169,8 +172,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL MFP_CS : std_logic; SIGNAL MFP_INTACK : std_logic; SIGNAL LDS : std_logic; +signal acia_irq : STD_LOGIC; SIGNAL DTACK_OUT_MFPn : std_logic; - SIGNAL IRQ_ACIAn : std_logic; SIGNAL DINTn : std_logic; SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0); SIGNAL TDO : std_logic; @@ -180,7 +183,22 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL SNDIR_I : std_logic; SIGNAL LP_DIR_X : std_logic; SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0); +signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0); +signal nLP_STR : STD_LOGIC; +-- DMA SOUND +signal dma_snd_cs : STD_LOGIC; +signal sndmactl : STD_LOGIC_VECTOR(7 downto 0); +signal sndbashi : STD_LOGIC_VECTOR(7 downto 0); +signal sndbasmi : STD_LOGIC_VECTOR(7 downto 0); +signal sndbaslo : STD_LOGIC_VECTOR(7 downto 0); +signal sndadrhi : STD_LOGIC_VECTOR(7 downto 0); +signal sndadrmi : STD_LOGIC_VECTOR(7 downto 0); +signal sndadrlo : STD_LOGIC_VECTOR(7 downto 0); +signal sndendhi : STD_LOGIC_VECTOR(7 downto 0); +signal sndendmi : STD_LOGIC_VECTOR(7 downto 0); +signal sndendlo : STD_LOGIC_VECTOR(7 downto 0); +signal sndmode : STD_LOGIC_VECTOR(7 downto 0); -- DIV SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE SIGNAL ROM_CS : std_logic; @@ -228,9 +246,7 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL WRF_RDE : std_logic; SIGNAL WRF_WRE : std_logic; SIGNAL nFDC_WR : std_logic; - TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); - SIGNAL FCF_STATE : FCF_STATES; SIGNAL NEXT_FCF_STATE : FCF_STATES; SIGNAL DMA_REQ : std_logic; @@ -241,7 +257,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL DMA_ACTIV : std_logic; SIGNAL DMA_ACTIV_NEW : std_logic; SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0); - -- SCSI SIGNAL SCSI_CS : std_logic; SIGNAL SCSI_CSn : std_logic; @@ -259,7 +274,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL BSY_EN : std_logic; SIGNAL SEL_OUTn : std_logic; SIGNAL SEL_EN : std_logic; - -- IDE SIGNAL nnIDE_RES : std_logic; SIGNAL IDE_CF_CS : std_logic; @@ -269,7 +283,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS type CMD_STATES is( IDLE, T1, T6, T7); SIGNAL CMD_STATE : CMD_STATES; SIGNAL NEXT_CMD_STATE : CMD_STATES; - +-- Paddle + SIGNAL paddle_cs : std_logic; BEGIN LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0'; @@ -277,23 +292,34 @@ BEGIN FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0'; FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0'; - FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1' - OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0'; - + FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE '1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE '1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0'; - nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1'; - nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1'; + nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; + nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; nDREQ0 <= '0'; - + + -- input daten halten + p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0)) + BEGIN + IF rising_edge(MAIN_CLK) THEN + IF nFB_WR = '0' THEN + FB_ADI <= FB_AD(31 downto 16); + ELSE + FB_ADI <= FB_ADI; + END IF; + ELSE + FB_ADI <= FB_ADI; + END IF; + END PROCESS; ---------------------------------------------------------------------------- -- SD ---------------------------------------------------------------------------- SD_CLK <= 'Z'; SD_CD_DATA3 <= 'Z'; SD_CDM_D1 <= 'Z'; - ---------------------------------------------------------------------------- -- IDE ---------------------------------------------------------------------------- @@ -353,24 +379,19 @@ BEGIN IDE_RES <= NOT nnIDE_RES AND nRSTO; IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 - nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F - nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F - nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F - nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F - ----------------------------------------------------------------------------------------------------------------------------------------- -- ACSI, SCSI UND FLOPPY WD1772 ------------------------------------------------------------------------------------------------------------------------------------------- -- daten read fifo - i_data_read_fifo: dcfifo0 + RDF: dcfifo0 PORT MAP( aclr => CLR_FIFO, data => RDF_DIN, @@ -381,16 +402,15 @@ BEGIN q => RDF_DOUT, wrusedw => RDF_AZ ); - FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE - - FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' + ELSE (OTHERS => 'Z'); + RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; - -- daten write fifo - i_data_write_fifo: dcfifo1 + WRF: dcfifo1 PORT MAP( aclr => CLR_FIFO, data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), @@ -401,14 +421,14 @@ BEGIN q => WRF_DOUT, rdusedw => WRF_AZ ); - - CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB + CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG - FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' + ELSE (OTHERS => 'Z'); DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; - + -- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + p_fifo_write : PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) BEGIN IF nRSTO = '0' THEN WRF_WRE <= '0'; @@ -530,7 +550,7 @@ BEGIN i_fdc : WF1772IP_TOP_SOC PORT MAP( CLK => FDC_CLK, - RESETn => nRSTO, + RESETn => nResetatio, CSn => FDCS_In, RWn => nFDC_WR, A1 => CA2, @@ -552,25 +572,20 @@ BEGIN DRQ => DMA_DRQ_I, INTRQ => FDINT ); - DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 - HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); - nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR; - + nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR; CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0); CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); - FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z'); + FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE - DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - - + DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- WDC BSL REGISTER ------------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) BEGIN @@ -584,7 +599,6 @@ BEGIN END IF; END IF; END PROCESS; - --- DMA MODUS REGISTER ------------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) BEGIN @@ -605,16 +619,15 @@ BEGIN DMA_MODUS <= DMA_MODUS; END IF; END PROCESS; - -- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) BEGIN IF nRSTO = '0' OR CLR_FIFO = '1' THEN DMA_BYT_CNT <= x"00000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN - DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z'); + DMA_BYT_CNT(31 downto 17) <= "000000000000000"; DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); - DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z'); + DMA_BYT_CNT(8 downto 0) <= "000000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN DMA_BYT_CNT <= FB_AD; ELSE @@ -622,15 +635,13 @@ BEGIN END IF; END PROCESS; -------------------------------------------------------------------- - FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - + FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; DMA_STATUS(0) <= '1'; -- DMA OK DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0'; DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0'; DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0'; - -- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG) BEGIN @@ -643,7 +654,6 @@ BEGIN DMA_DRQ_REG <= DMA_DRQ_REG; END IF; END PROCESS; - -- DMA ADRESSE ------------------------------------------------------ PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) BEGIN @@ -655,7 +665,6 @@ BEGIN DMA_TOP <= DMA_TOP; END IF; END PROCESS; - PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) BEGIN IF nRSTO = '0' THEN @@ -666,7 +675,6 @@ BEGIN DMA_HIGH <= DMA_HIGH; END IF; END PROCESS; - PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) BEGIN DMA_MID <= DMA_MID; @@ -680,7 +688,6 @@ BEGIN END IF; END IF; END PROCESS; - PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) BEGIN DMA_LOW <= DMA_LOW; @@ -694,29 +701,26 @@ BEGIN END IF; END IF; END PROCESS; - -------------------------------------------------------------------------------------------- DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 - - FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; -- DIRECTZUGRIFF DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG - - FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - - + + FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + -- DMA RW TOGGLE ------------------------------------------ - PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) BEGIN IF nRSTO = '0' THEN @@ -727,20 +731,18 @@ BEGIN DMA_DIR_OLD <= DMA_DIR_OLD; END IF; END PROCESS; - CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; - -- SCSI ---------------------------------------------------------------------------------- i_scsi : WF5380_TOP_SOC PORT MAP( CLK => FDC_CLK, - RESETn => nRSTO, + RESETn => nResetatio, ADR => CA2 & CA1 & CA0, DATA_IN => CD_IN_FDC, DATA_OUT => SCSI_DOUT, --DATA_EN : out bit; -- Bus and DMA controls: - CSn => '1', --SCSI_CSn, ABGESCHALTET + CSn => SCSI_CSn, RDn => (not nFDC_WR) or (not SCSI_CS), WRn => nFDC_WR or (not SCSI_CS), EOPn => '1', @@ -783,37 +785,36 @@ BEGIN -- MSG_OUTn => MSG_OUTn, -- MSG_EN => MSG_EN ); - -- SCSI ACSI --------------------------------------------------------------- - SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z'); - SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET + SCSI_D <= "ZZZZZZZZ"; --DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; + SCSI_DIR <= '1';-- when DB_EN = '1' else '1'; SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z'; - nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z'; - nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z'; - nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z'; + nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z'; + nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z'; + nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z'; + ACSI_DIR <= '0'; - ACSI_D <= (OTHERS => 'Z'); + ACSI_D <= "ZZZZZZZZ"; nACSI_CS <= '1'; ACSI_A1 <= CA1; nACSI_RESET <= nRSTO; nACSI_ACK <= '1'; - - + nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1'; + ---------------------------------------------------------------------------- -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ---------------------------------------------------------------------------- ROM_CS <= '1' WHEN nFB_CS1 = '0' AND nFB_WR = '1' AND FB_ADR(19 DOWNTO 17) = x"5" ELSE '0'; -- FFF A'0000/2'0000 nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1'; nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1'; - - + ---------------------------------------------------------------------------- -- ACIA KEYBOARD ---------------------------------------------------------------------------- i_acia_keyboard : WF6850IP_TOP_SOC PORT MAP( CLK => MAIN_CLK, - RESETn => nRSTO, + RESETn => nResetatio, CS2n => FB_ADR(2), CS1 => '1', @@ -822,7 +823,7 @@ BEGIN RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 DOWNTO 24), + DATA_IN => FB_ADI(15 downto 8), DATA_OUT => DATA_OUT_ACIA_I, -- DATA_EN => DATA_EN_ACIA_I, @@ -834,43 +835,48 @@ BEGIN DCDn => '0', IRQn => IRQ_KEYBDn, - TXDATA => AMKB_TX + TXDATA => AMKB_TX_sync --RTSn => -- Not used. ); - ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 - KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL - FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ"; - - -- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL // + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE + DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + -- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------ PROCESS(CLK2M, AMKB_RX, AMKB_REG) BEGIN - IF rising_edge(CLK2M) THEN + if rising_edge(CLK500k) then + AMKB_TX <= AMKB_TX_sync; IF AMKB_RX = '0' THEN - IF AMKB_REG < 16 THEN - AMKB_REG <= "00000"; + IF AMKB_REG < 8 THEN + AMKB_REG <= "0000"; ELSE AMKB_REG <= AMKB_REG - 1; END IF; ELSE - IF AMKB_REG > 15 THEN - AMKB_REG <= "11111"; + IF AMKB_REG > 7 THEN + AMKB_REG <= "1111"; ELSE AMKB_REG <= AMKB_REG + 1; END IF; END IF; ELSE + AMKB_TX <= AMKB_TX; AMKB_REG <= AMKB_REG; END IF; END PROCESS; + -- acia interrupt ------------------------------------------ + acia_irq <= '0' WHEN IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' ELSE '1'; + ---------------------------------------------------------------------------- -- ACIA MIDI ---------------------------------------------------------------------------- i_acia_midi : WF6850IP_TOP_SOC PORT MAP( CLK => MAIN_CLK, - RESETn => nRSTO, + RESETn => nResetatio, CS2n => '0', CS1 => FB_ADR(2), @@ -879,7 +885,7 @@ BEGIN RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 DOWNTO 24), + DATA_IN => FB_ADI(15 downto 8), DATA_OUT => DATA_OUT_ACIA_II, -- DATA_EN => DATA_EN_ACIA_II, @@ -893,19 +899,16 @@ BEGIN TXDATA => MIDI_OUT --RTSn => -- Not used. ); - - MIDI_TLR <= MIDI_OUT; + MIDI_TLR <= MIDI_IN; MIDI_OLR <= MIDI_OUT; - FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - ---------------------------------------------------------------------------- -- MFP ---------------------------------------------------------------------------- i_mfp : WF68901IP_TOP_SOC PORT MAP( -- System control: - CLK => MAIN_CLK, - RESETn => nRSTO, + CLK => not MAIN_CLK, + RESETn => nResetatio, -- Asynchronous bus control: DSn => NOT LDS, CSn => NOT MFP_CS, @@ -919,7 +922,7 @@ BEGIN GPIP_IN(7) => NOT DMA_DRQ_Q, GPIP_IN(6) => NOT RI, GPIP_IN(5) => DINTn, - GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(4) => acia_irq, GPIP_IN(3) => DSP_INT, GPIP_IN(2) => NOT CTS, GPIP_IN(1) => NOT DCD, @@ -953,35 +956,21 @@ BEGIN MFP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 6) = x"3FE8" ELSE '0'; -- FFA00/40 MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; - - FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ; + + FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ"; + FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; - DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE '0' WHEN FDINT = '1' ELSE '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; - - -- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn) - BEGIN - IF nRSTO = '0' THEN - IRQ_ACIAn <= '1'; - ELSIF rising_edge(MAIN_CLK) THEN - IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn; - ELSE - IRQ_ACIAn <= IRQ_ACIAn; - END IF; - END PROCESS; - ---------------------------------------------------------------------------- -- Sound ---------------------------------------------------------------------------- i_sound : WF2149IP_TOP_SOC PORT MAP( - SYS_CLK => MAIN_CLK, - RESETn => nRSTO, + SYS_CLK => not MAIN_CLK, + RESETn => nResetatio, WAV_CLK => CLK2M, SELn => '1', @@ -992,18 +981,11 @@ BEGIN A9n => '0', A8 => '1', - DA_IN => FB_AD(31 DOWNTO 24), + DA_IN => FB_ADI(15 downto 8), DA_OUT => DA_OUT_X, - IO_A_IN => x"00", -- All port pins are dedicated outputs. - IO_A_OUT(7) => nnIDE_RES, - IO_A_OUT(6) => LP_DIR_X, - IO_A_OUT(5) => LP_STR, - IO_A_OUT(4) => DTR, - IO_A_OUT(3) => RTS, --- IO_A_OUT(2) => FDD_D1SEL, - IO_A_OUT(1) => DSA_D, - IO_A_OUT(0) => nSDSEL, + IO_A_IN => SND_A, + IO_A_OUT => SND_A_X, -- IO_A_EN =>, -- Not required. IO_B_IN => LP_D, IO_B_OUT => LP_D_X, @@ -1017,8 +999,185 @@ BEGIN SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0'; - FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - - LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z'); + + FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + nnIDE_RES <= SND_A_X(7); + LP_DIR_X <= SND_A_X(6); + LP_STR <= SND_A_X(5); + DTR <= SND_A_X(4); + RTS <= SND_A_X(3); + + -- FDD_D1SEL <= SND_A_X(2) + DSA_D <= SND_A_X(1); + nSDSEL <= SND_A_X(0); + SND_A <= SND_A_X; + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ"; LP_DIR <= LP_DIR_X; + + + ---------------------------------------------------------------------------- + -- DMA Sound register + ---------------------------------------------------------------------------- + + dma_snd_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E24" ELSE '0'; -- F8900-F893F + + PROCESS(nRSTO,MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndmactl <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN + sndmactl <= FB_AD(23 DOWNTO 16); + ELSE + sndmactl <= sndmactl; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + begin + IF nRSTO = '0' THEN + sndbashi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN + sndbashi <= FB_AD(23 DOWNTO 16); + ELSE + sndbashi <= sndbashi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndbasmi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN + sndbasmi <= FB_AD(23 DOWNTO 16); + ELSE + sndbasmi <= sndbasmi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndbaslo <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN + sndbaslo <= FB_AD(23 DOWNTO 16); + ELSE + sndbaslo <= sndbaslo; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndadrhi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN + sndadrhi <= FB_AD(23 DOWNTO 16); + ELSE + sndadrhi <= sndadrhi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndadrmi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN + sndadrmi <= FB_AD(23 DOWNTO 16); + ELSE + sndadrmi <= sndadrmi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndadrlo <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN + sndadrlo <= FB_AD(23 DOWNTO 16); + ELSE + sndadrlo <= sndadrlo; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndendhi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN + sndendhi <= FB_AD(23 DOWNTO 16); + ELSE + sndendhi <= sndendhi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndendmi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN + sndendmi <= FB_AD(23 DOWNTO 16); + ELSE + sndendmi <= sndendmi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndendlo <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN + sndendlo <= FB_AD(23 DOWNTO 16); + ELSE + sndendlo <= sndendlo; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndmode <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN + sndmode <= FB_AD(23 DOWNTO 16); + ELSE + sndmode <= sndmode; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + ---------------------------------------------------------------------------- + -- Paddle + ---------------------------------------------------------------------------- + + paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F + + FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd index a140e29..9d048de 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd @@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS); component WF2149IP_WAVE port( RESETn : in bit; - SYS_CLK : in std_logic; + SYS_CLK : in bit; WAV_STRB : in bit; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd index 060058c..c2705dc 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd @@ -83,7 +83,7 @@ LIBRARY ieee; ENTITY WF2149IP_TOP_SOC IS PORT( - SYS_CLK : IN std_logic; -- Read the inforation in the header! + SYS_CLK : in bit; -- Read the inforation in the header! RESETn : IN bit; WAV_CLK : IN bit; -- Read the inforation in the header! @@ -110,7 +110,7 @@ ENTITY WF2149IP_TOP_SOC IS ); END WF2149IP_TOP_SOC; -ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS +architecture STRUCTURE of WF2149IP_TOP_SOC is SIGNAL BUSCYCLE : BUSCYCLES; SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0); SIGNAL DATA_EN_I : bit; @@ -127,11 +127,10 @@ BEGIN IF RESETn = '0' THEN LOCK := false; TMP := '0'; - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF WAV_CLK = '1' and LOCK = false THEN LOCK := true; TMP := not TMP; -- Divider by 2. - CASE SELn IS WHEN '1' => WAV_STRB <= '1'; WHEN OTHERS => WAV_STRB <= TMP; @@ -158,7 +157,7 @@ BEGIN BEGIN IF RESETn = '0' THEN ADR_I <= (OTHERS => '0'); - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0)); END IF; @@ -170,7 +169,7 @@ BEGIN BEGIN IF RESETn = '0' THEN CTRL_REG <= x"00"; - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN CTRL_REG <= To_BitVector(DA_IN); END IF; @@ -182,7 +181,7 @@ BEGIN IF RESETn = '0' THEN PORT_A <= x"00"; PORT_B <= x"00"; - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN PORT_A <= To_BitVector(DA_IN); ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN @@ -227,4 +226,4 @@ BEGIN To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0'); -END rtl; +end STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd index 8744213..d829f9b 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd @@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all; entity WF2149IP_WAVE is port( RESETn : in bit; - SYS_CLK : in std_logic; + SYS_CLK : in bit; WAV_STRB : in bit; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd index e60cc43..3d5e2cf 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd @@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all; entity WF6850IP_CTRL_STATUS is port ( - CLK : in bit; + CLK : in std_logic; RESETn : in bit; CS : in bit_vector(2 downto 0); -- Active if "011". @@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is CDS : out bit_vector(1 downto 0); -- Clock control. WS : out bit_vector(2 downto 0); -- Word select. TC : out bit_vector(1 downto 0); -- Transmit control. - IRQn : out bit -- Interrupt request. + IRQn : buffer bit -- Interrupt request. ); end entity WF6850IP_CTRL_STATUS; @@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is signal CTRL_REG : bit_vector(7 downto 0); signal STATUS_REG : bit_vector(7 downto 0); signal RIE : bit; -signal IRQ_I : bit; signal CTS_In : bit; signal DCD_In : bit; signal DCD_FLAGn : bit; begin - P_SAMPLE: process - begin - wait until CLK = '0' and CLK' event; - CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. - DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. - end process P_SAMPLE; + CTS_In <= CTSn; + DCD_In <= DCDn; -- immer 0 - STATUS_REG(7) <= IRQ_I; + STATUS_REG(7) <= not IRQn; STATUS_REG(6) <= PE; STATUS_REG(5) <= OVR; STATUS_REG(4) <= FE; @@ -123,8 +118,8 @@ begin STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. - DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; + DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0'; MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; @@ -134,90 +129,52 @@ begin TC <= CTRL_REG(6 downto 5); RIE <= CTRL_REG(7); - P_IRQ: process - variable DCD_OVR_LOCK : boolean; - variable DCD_LOCK : boolean; - variable DCD_TRANS : boolean; + P_IRQ: process(CLK) begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - DCD_OVR_LOCK := false; - IRQn <= '1'; - IRQ_I <= '0'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then - DCD_OVR_LOCK := false; -- Enable reset by reading the status. - end if; - - -- Clear interrupts when disabled. - if CTRL_REG(7) = '0' then + if rising_edge(CLK) then + if RESETn = '0' or MCLR = '1' then IRQn <= '1'; - IRQ_I <= '0'; - elsif CTRL_REG(6 downto 5) /= "01" then - IRQn <= '1'; - IRQ_I <= '0'; - end if; - + else -- Transmitter interrupt: - if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then + if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by writing to the transmit data register. end if; - -- Receiver interrupts: - if RDRF = '1' and RIE = '1' and DCD_In = '0' then + if RDRF = '1' and RIE = '1' then IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by reading the receive data register. end if; - + -- Overrun if OVR = '1' and RIE = '1' then IRQn <= '0'; - IRQ_I <= '1'; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. end if; - - if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then - IRQn <= '0'; - IRQ_I <= '1'; - -- DCD_TRANS is used to detect a low to high transition of DCDn. - DCD_TRANS := true; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. - elsif DCD_In = '0' then - DCD_TRANS := false; - end if; - -- The reset of the IRQ status flag: -- Clear by writing to the transmit data register. -- Clear by reading the receive data register. - if CS = "011" and RS = '1' and E = '1' then - IRQ_I <= '0'; + if CS = "011" and RS = '1' then + IRQn <= '1'; + end if; + end if; end if; end process P_IRQ; - CONTROL: process + CONTROL: process(CLK) begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if RESETn = '0' then CTRL_REG <= "01000000"; - elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then + elsif CS = "011" and RWn = '0' and RS = '0' then CTRL_REG <= DATA_IN; end if; + end if; end process CONTROL; - P_DCD: process + P_DCD: process(CLK) -- This process is some kind of tricky. Refer to the MC6850 data -- sheet for more information. variable READ_LOCK : boolean; variable DCD_RELEASE : boolean; begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if RESETn = '0' then DCD_FLAGn <= '0'; -- This interrupt source must initialise low. READ_LOCK := true; @@ -227,9 +184,9 @@ begin READ_LOCK := true; elsif DCD_In = '1' then DCD_FLAGn <= '1'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + elsif CS = "011" and RWn = '1' and RS = '0' then READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then + elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then -- Clear if receiver status register read access. -- After data register has ben read and READ_LOCK again. DCD_RELEASE := true; @@ -239,6 +196,7 @@ begin DCD_FLAGn <= '0'; DCD_RELEASE := false; end if; + end if; end process P_DCD; end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd index 755e018..989447c 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd @@ -54,362 +54,379 @@ -- Minor changes. -- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; -entity WF6850IP_RECEIVE is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; +ENTITY WF6850IP_RECEIVE IS + PORT + ( + CLK : IN std_logic; + RESETn : IN bit; + MCLR : IN bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; + CS : IN bit_vector(2 DOWNTO 0); + E : IN bit; + RWn : IN bit; + RS : IN bit; - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; + DATA_OUT : OUT bit_vector(7 DOWNTO 0); + DATA_EN : OUT bit; - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); + WS : IN bit_vector(2 DOWNTO 0); + CDS : IN bit_vector(1 DOWNTO 0); - RXCLK : in bit; - RXDATA : in bit; + RXCLK : IN bit; + RXDATA : IN bit; - RDRF : buffer bit; - OVR : out bit; - PE : out bit; - FE : out bit + RDRF : BUFFER bit; + OVR : OUT bit; + PE : OUT bit; + FE : OUT bit ); -end entity WF6850IP_RECEIVE; +END ENTITY WF6850IP_RECEIVE; -architecture BEHAVIOR of WF6850IP_RECEIVE is -type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); -signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; -signal RXDATA_I : bit; -signal RXDATA_S : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal CLK_STRB : bit; -signal BITCNT : std_logic_vector(2 downto 0); -begin - P_SAMPLE: process - -- This filter provides a synchronisation to the system - -- clock, even for random baud rates of the received data - -- stream. - variable FLT_TMP : integer range 0 to 2; - begin - wait until CLK = '1' and CLK' event; - -- - RXDATA_I <= RXDATA; - -- - if RXDATA_I = '1' and FLT_TMP < 2 then - FLT_TMP := FLT_TMP + 1; - elsif RXDATA_I = '1' then - RXDATA_S <= '1'; - elsif RXDATA_I = '0' and FLT_TMP > 0 then - FLT_TMP := FLT_TMP - 1; - elsif RXDATA_I = '0' then - RXDATA_S <= '0'; - end if; - end process P_SAMPLE; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- Divider off. - if RXCLK = '1' and STRB_LOCK = false then - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif RXCLK = '0' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif RCV_STATE = IDLE then - -- Preset the CLKDIV with the start delays. - if CDS = "01" then - CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. - elsif CDS = "10" then - CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. - end if; - CLK_STRB <= '0'; - else - if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - -- - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif RXCLK = '0' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; +ARCHITECTURE rtl OF WF6850IP_RECEIVE IS + TYPE RCV_STATES IS (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); + SIGNAL RCV_STATE, RCV_NEXT_STATE : RCV_STATES; + SIGNAL RXDATA_I : bit; + SIGNAL RXDATA_S : bit; + SIGNAL DATA_REG : bit_vector(7 DOWNTO 0); + SIGNAL SHIFT_REG : bit_vector(7 DOWNTO 0); + SIGNAL CLK_STRB : bit; + SIGNAL BITCNT : std_logic_vector(2 DOWNTO 0); +BEGIN + p_sample : PROCESS(CLK) + -- This filter provides a synchronisation to the system + -- clock, even for random baud rates of the received data + -- stream. + VARIABLE FLT_TMP : integer RANGE 0 TO 2; + BEGIN + IF rising_edge(CLK) THEN + -- + RXDATA_I <= RXDATA; + -- + IF RXDATA_I = '1' and FLT_TMP < 2 THEN + FLT_TMP := FLT_TMP + 1; + ELSIF RXDATA_I = '1' THEN + RXDATA_S <= '1'; + ELSIF RXDATA_I = '0' and FLT_TMP > 0 THEN + FLT_TMP := FLT_TMP - 1; + ELSIF RXDATA_I = '0' THEN + RXDATA_S <= '0'; + END IF; + END IF; + END PROCESS p_sample; + + clkdiv : PROCESS(CLK) + VARIABLE CLK_LOCK : boolean; + VARIABLE STRB_LOCK : boolean; + VARIABLE CLK_DIVCNT : std_logic_vector(6 DOWNTO 0); + BEGIN + IF rising_edge(CLK) THEN + IF CDS = "00" THEN -- Divider off. + IF RXCLK = '1' and STRB_LOCK = false THEN + CLK_STRB <= '1'; + STRB_LOCK := true; + ELSIF RXCLK = '0' THEN + CLK_STRB <= '0'; + STRB_LOCK := false; + ELSE + CLK_STRB <= '0'; + END IF; + ELSIF RCV_STATE = IDLE THEN + -- Preset the CLKDIV with the start delays. + IF CDS = "01" THEN + CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. + ELSIF CDS = "10" THEN + CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. + END IF; + CLK_STRB <= '0'; + ELSE + IF CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false THEN + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + ELSIF CDS = "01" and CLK_DIVCNT = "0000000" THEN + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + -- + IF STRB_LOCK = false THEN + STRB_LOCK := true; + CLK_STRB <= '1'; + ELSE + CLK_STRB <= '0'; + END IF; + ELSIF CDS = "10" and CLK_DIVCNT = "0000000" THEN + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + IF STRB_LOCK = false THEN + STRB_LOCK := true; + CLK_STRB <= '1'; + ELSE + CLK_STRB <= '0'; + END IF; + ELSIF RXCLK = '0' THEN + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + ELSE + CLK_STRB <= '0'; + END IF; + END IF; + END IF; + END PROCESS clkdiv; - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then + datareg : PROCESS(RESETn, CLK) + BEGIN + IF RESETn = '0' or MCLR = '1' THEN DATA_REG <= x"00"; - elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= '0' & SHIFT_REG(7 downto 1); - elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= SHIFT_REG; - end if; - end if; - end process DATAREG; - DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; + ELSE + IF rising_edge(CLK) THEN + IF RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' THEN -- 7 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= '0' & SHIFT_REG(7 downto 1); + ELSIF RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' THEN -- 8 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= SHIFT_REG; + END IF; + END IF; + END IF; + END PROCESS datareg; + + DATA_OUT <= DATA_REG WHEN CS = "011" and RWn = '1' and RS = '1' ELSE (OTHERS => '0'); + DATA_EN <= '1' WHEN CS = "011" and RWn = '1' and RS = '1' ELSE '0'; - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then + shiftreg : PROCESS(RESETn, CLK) + BEGIN + IF RESETn = '0' or MCLR = '1' THEN SHIFT_REG <= x"00"; - elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then - SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; + ELSE + IF rising_edge(CLK) THEN + IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN + SHIFT_REG <= RXDATA_S & SHIFT_REG(7 DOWNTO 1); -- Shift right. + END IF; + END IF; + END IF; + END PROCESS shiftreg; - P_BITCNT: process - begin - wait until CLK = '1' and CLK' event; - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif RCV_STATE /= SAMPLE then - BITCNT <= (others => '0'); - end if; - end process P_BITCNT; + p_bitcnt : PROCESS(CLK) + BEGIN + IF rising_edge(CLK) THEN + IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN + BITCNT <= BITCNT + '1'; + ELSIF RCV_STATE /= SAMPLE THEN + BITCNT <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS p_bitcnt; - FRAME_ERR: process(RESETn, CLK) + p_frame_err: PROCESS(RESETn, CLK) -- This module detects a framing error -- during stop bit 1 and stop bit 2. - variable FE_I: bit; - begin - if RESETn = '0' then + VARIABLE FE_I: bit; + BEGIN + IF RESETn = '0' THEN FE_I := '0'; FE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - FE_I := '0'; - FE <= '0'; - elsif CLK_STRB = '1' then - if RCV_STATE = STOP1 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP2 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then - FE_I := '0'; -- Error resets when correct data appears. - end if; - end if; - if RCV_STATE = SYNC then - FE <= FE_I; -- Update the FE every SYNC time. - end if; - end if; - end process FRAME_ERR; + ELSE + IF rising_edge(CLK) THEN + IF MCLR = '1' THEN + FE_I := '0'; + FE <= '0'; + ELSIF CLK_STRB = '1' THEN + IF RCV_STATE = STOP1 and RXDATA_S = '0' THEN + FE_I := '1'; + ELSIF RCV_STATE = STOP2 and RXDATA_S = '0' THEN + FE_I := '1'; + ELSIF RCV_STATE = STOP1 or RCV_STATE = STOP2 THEN + FE_I := '0'; -- Error resets when correct data appears. + END IF; + END IF; + IF RCV_STATE = SYNC THEN + FE <= FE_I; -- Update the FE every SYNC time. + END IF; + END IF; + END IF; + END PROCESS p_frame_err; - OVERRUN: process(RESETn, CLK) - variable OVR_I : bit; - variable FIRST_READ : boolean; - begin - if RESETn = '0' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then + p_overrun : PROCESS(RESETn, CLK) + VARIABLE OVR_I : bit; + VARIABLE FIRST_READ : boolean; + BEGIN + IF rising_edge(CLK) THEN + IF RESETn = '0' or MCLR = '1' THEN OVR_I := '0'; OVR <= '0'; FIRST_READ := false; - elsif CLK_STRB = '1' and RCV_STATE = STOP1 then - -- Overrun appears if RDRF is '1' in this state. - OVR_I := RDRF; - end if; - if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then - -- If an overrun was detected, the concerning flag is - -- set when the valid data word in the receiver data - -- register is read. Thereafter the RDRF flag is reset - -- and the overrun disappears (OVR_I goes low) after - -- a second read (in time) of the receiver data register. - if FIRST_READ = false then - OVR <= '1'; - FIRST_READ := true; - else - OVR <= '0'; + ELSE + IF CLK_STRB = '1' and RCV_STATE = STOP1 THEN + -- Overrun appears if RDRF is '1' in this state. + OVR_I := RDRF; + END IF; + IF CS = "011" and RWn = '1' and RS = '1' THEN + -- If an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OVR_I goes low) after + -- a second read (in time) of the receiver data register. + IF FIRST_READ = false THEN + IF OVR_I = '1' THEN + OVR <= '1'; + OVR_I := '0'; + FIRST_READ := true; + ELSE + OVR <= '0'; + END IF; + END IF; + ELSE FIRST_READ := false; - end if; - end if; - end if; - end process OVERRUN; + END IF; + END IF; + END IF; + END PROCESS p_overrun; - PARITY_TEST: process(RESETn, CLK) - variable PAR_TMP : bit; - variable PE_I : bit; - begin - if RESETn = '0' then + p_parity_test : PROCESS(RESETn,MCLR,CLK) + VARIABLE PAR_TMP : bit; + VARIABLE PE_I : bit; + BEGIN + IF RESETn = '0' or MCLR = '1' THEN PE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - PE <= '0'; - elsif CLK_STRB = '1' then -- Sample parity on clock strobe. - PE_I := '0'; -- Initialise. - if RCV_STATE = PARITY then - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PE_I := PAR_TMP xor RXDATA_S; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PE_I := not PAR_TMP xor RXDATA_S; - else -- No parity for WS = "100" and WS = "101". - PE_I := '0'; - end if; - end if; - end if; + ELSE + IF rising_edge(CLK) THEN + IF CLK_STRB = '1' THEN -- Sample parity on clock strobe. + PE_I := '0'; -- Initialise. + IF RCV_STATE = PARITY THEN + FOR i in 1 TO 7 LOOP + IF i = 1 THEN + PAR_TMP := SHIFT_REG(i - 1) xor SHIFT_REG(i); + ELSE + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + END IF; + END LOOP; + IF WS = "000" or WS = "010" or WS = "110" THEN -- Even parity. + PE_I := PAR_TMP xor RXDATA_S; + ELSIF WS = "001" or WS = "011" or WS = "111" THEN -- Odd parity. + PE_I := not PAR_TMP xor RXDATA_S; + ELSE -- No parity for WS = "100" and WS = "101". + PE_I := '0'; + END IF; + END IF; + END IF; + END IF; -- Transmit the parity flag together with the data -- In other words: no parity to the status register -- when RDRF inhibits the data transfer to the -- receiver data register. - if RCV_STATE = SYNC and RDRF = '0' then + IF RCV_STATE = SYNC and RDRF = '0' THEN PE <= PE_I; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + ELSIF CS = "011" and RWn = '1' and RS = '1' THEN PE <= '0'; -- Clear when reading the data register. - end if; - end if; - end process PARITY_TEST; + END IF; + END IF; + END PROCESS p_parity_test; - P_RDRF: process(RESETn, CLK) + p_rdrf : process(RESETn, CLK) -- Receive data register full flag. - begin - if RESETn = '0' then - RDRF <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RDRF <= '0'; - elsif RCV_STATE = SYNC then - RDRF <= '1'; -- Data register is full until now! - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - RDRF <= '0'; -- After reading the data register ... - end if; - end if; - end process P_RDRF; + BEGIN + IF rising_edge(CLK) THEN + IF RESETn = '0' or MCLR = '1' THEN + RDRF <= '0'; + ELSE + IF RCV_STATE = SYNC THEN + RDRF <= '1'; -- Data register is full until now! + END IF; + IF CS = "011" and RWn = '1' and RS = '1' THEN + RDRF <= '0'; -- when reading the data register ... + END IF; + END IF; + END IF; + END PROCESS p_rdrf; - RCV_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then + p_rcv_statereg : PROCESS(RESETn, CLK) + BEGIN + IF RESETn = '0' THEN RCV_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RCV_STATE <= IDLE; - else - RCV_STATE <= RCV_NEXT_STATE; - end if; - end if; - end process RCV_STATEREG; + ELSE + IF rising_edge(CLK) THEN + IF MCLR = '1' THEN + RCV_STATE <= IDLE; + ELSE + RCV_STATE <= RCV_NEXT_STATE; + END IF; + END IF; + END IF; + END PROCESS p_rcv_statereg; - RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) - begin - case RCV_STATE is - when IDLE => - if RXDATA_S = '0' and CDS = "00" then + p_rcv_statedec : PROCESS(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) + BEGIN + CASE RCV_STATE IS + WHEN IDLE => + IF RXDATA_S = '0' and CDS = "00" THEN RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. - elsif RXDATA_S = '0' and CDS = "01" then + ELSIF RXDATA_S = '0' and CDS = "01" THEN RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. - elsif RXDATA_S = '0' and CDS = "10" then + ELSIF RXDATA_S = '0' and CDS = "10" THEN RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. - else + ELSE RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) - end if; - when WAIT_START => - if CLK_STRB = '1' then - if RXDATA_S = '0' then + END IF; + + WHEN WAIT_START => + IF CLK_STRB = '1' THEN + IF RXDATA_S = '0' THEN RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. - else + ELSE RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. - end if; - else + END IF; + ELSE RCV_NEXT_STATE <= WAIT_START; -- Stay. - end if; - when SAMPLE => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then + END IF; + + WHEN SAMPLE => + IF CLK_STRB = '1' THEN + IF BITCNT < "110" and WS(2) = '0' THEN RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then + ELSIF BITCNT < "111" and WS(2) = '1' THEN RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. - elsif WS = "100" or WS = "101" then + ELSIF WS = "100" or WS = "101" THEN RCV_NEXT_STATE <= STOP1; -- No parity check enabled. - else + ELSE RCV_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else + END IF; + ELSE RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. - end if; - when PARITY => - if CLK_STRB = '1' then + END IF; + + WHEN PARITY => + IF CLK_STRB = '1' THEN RCV_NEXT_STATE <= STOP1; - else + ELSE RCV_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' then - if RXDATA_S = '0' then + END IF; + + WHEN STOP1 => + IF CLK_STRB = '1' THEN + IF RXDATA_S = '0' THEN RCV_NEXT_STATE <= SYNC; -- Framing error detected. - elsif WS = "000" or WS = "001" or WS = "100" then + ELSIF WS = "000" or WS = "001" or WS = "100" THEN RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. - else + ELSE RCV_NEXT_STATE <= SYNC; -- One stop bit selected. - end if; - else + END IF; + ELSE RCV_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then + END IF; + + WHEN STOP2 => + IF CLK_STRB = '1' THEN RCV_NEXT_STATE <= SYNC; - else + ELSE RCV_NEXT_STATE <= STOP2; - end if; - when SYNC => + END IF; + WHEN SYNC => RCV_NEXT_STATE <= IDLE; - end case; - end process RCV_STATEDEC; -end architecture BEHAVIOR; + END CASE; + END PROCESS p_rcv_statedec; +END ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd index be34852..ed96d8f 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -158,7 +158,6 @@ ARCHITECTURE structure OF WF6850IP_TOP_SOC IS TXDATA : OUT bit ); END COMPONENT; - SIGNAL DATA_IN_I : bit_vector(7 DOWNTO 0); SIGNAL DATA_RX : bit_vector(7 DOWNTO 0); SIGNAL DATA_RX_EN : bit; @@ -183,8 +182,7 @@ BEGIN IRQn <= '0' when IRQ_In = '0' else '1'; I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS - PORT MAP - ( + port map( CLK => CLK, RESETn => RESETn, CS(2) => CS2n, @@ -212,8 +210,7 @@ BEGIN ); I_UART_RECEIVE: WF6850IP_RECEIVE - PORT MAP - ( + port map ( CLK => CLK, RESETn => RESETn, MCLR => MCLR_I, @@ -236,8 +233,7 @@ BEGIN ); I_UART_TRANSMIT: WF6850IP_TRANSMIT - PORT MAP - ( + port map ( CLK => CLK, RESETn => RESETn, MCLR => MCLR_I, diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd index c8ae6fc..3de110a 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd @@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all; entity WF6850IP_TRANSMIT is port ( - CLK : in bit; + CLK : in std_logic; RESETn : in bit; MCLR : in bit; @@ -108,12 +108,12 @@ begin '1' when TR_STATE = STOP1 else '1' when TR_STATE = STOP2 else '1'; - CLKDIV: process + CLKDIV: process(CLK) variable CLK_LOCK : boolean; variable STRB_LOCK : boolean; variable CLK_DIVCNT : std_logic_vector(6 downto 0); begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if CDS = "00" then -- divider off if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. CLK_STRB <= '1'; @@ -162,13 +162,14 @@ begin CLK_STRB <= '0'; end if; end if; + end if; end process CLKDIV; DATAREG: process(RESETn, CLK) begin if RESETn = '0' then DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then + elsif rising_edge(CLK) then if MCLR = '1' then DATA_REG <= x"00"; elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then @@ -183,7 +184,7 @@ begin begin if RESETn = '0' then SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then + elsif rising_edge(CLK) then if MCLR = '1' then SHIFT_REG <= x"00"; elsif TR_STATE = LOAD_SHFT and TDRE = '0' then @@ -198,47 +199,42 @@ begin end if; end process SHIFTREG; - P_BITCNT: process + P_BITCNT: process(CLK) -- Counter for the data bits transmitted. begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if TR_STATE = SHIFTOUT and CLK_STRB = '1' then BITCNT <= BITCNT + '1'; elsif TR_STATE /= SHIFTOUT then BITCNT <= "000"; end if; + end if; end process P_BITCNT; P_TDRE: process(RESETn, CLK) -- Transmit data register empty flag. - variable LOCK : boolean; begin - if RESETn = '0' then + if rising_edge(CLK) then + if RESETn = '0' or MCLR = '1' then TDRE <= '1'; - LOCK := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - TDRE <= '1'; - elsif TR_NEXT_STATE = START and TR_STATE /= START then + else + if TR_NEXT_STATE = START and TR_STATE /= START then -- Data has been loaded to shift register, thus data register is free again. -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once -- entering the state now. TDRE <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then - LOCK := true; - elsif E = '0' and LOCK = true then - -- This construction clears TDRE after the falling edge of E - -- and after the transmit data register has been written to. + end if; + if CS = "011" and RWn = '0' and RS = '1' then TDRE <= '0'; - LOCK := false; + end if; end if; end if; end process P_TDRE; - PARITY_GEN: process + PARITY_GEN: process(CLK) variable PAR_TMP : bit; begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if TR_STATE = START then -- Calculate the parity during the start phase. for i in 1 to 7 loop if i = 1 then @@ -255,19 +251,22 @@ begin PARITY_I <= '0'; end if; end if; + end if; end process PARITY_GEN; TR_STATEREG: process(RESETn, CLK) begin if RESETn = '0' then TR_STATE <= IDLE; - elsif CLK = '1' and CLK' event then + else + if rising_edge(CLK) then if MCLR = '1' then TR_STATE <= IDLE; else TR_STATE <= TR_NEXT_STATE; end if; end if; + end if; end process TR_STATEREG; TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf index b569002..fd3cd47 100644 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler VSYNC : INPUT; HSYNC : INPUT; DMA_DRQ : INPUT; + nRSTO : INPUT; nIRQ[7..2] : OUTPUT; INT_HANDLER_TA : OUTPUT; ACP_CONF[31..0] : OUTPUT; @@ -56,6 +57,8 @@ VARIABLE INT_IN[31..0] :NODE; INT_ENA[31..0] :DFFE; INT_ENA_CS :NODE; + INT_L[9..0] :DFF; + INT_LA[9..0][3..0] :DFF; ACP_CONF[31..0] :DFFE; ACP_CONF_CS :NODE; PSEUDO_BUS_ERROR :NODE; @@ -91,7 +94,7 @@ BEGIN # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL�SEN, 1=INT7 AUSL�SEN +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN INT_CTR[].CLK = MAIN_CLK; INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 INT_CTR[] = FB_AD[]; @@ -99,16 +102,15 @@ BEGIN INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; - -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA[].CLK = MAIN_CLK; + INT_ENA[].CLRN = nRSTO; INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 INT_ENA[] = FB_AD[]; INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; - -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 @@ -116,23 +118,21 @@ BEGIN INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; - -- INTERRUPT LATCH REGISTER READ ONLY INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 - -- INTERRUPT !nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ3 = INT_CTR0 & INT_ENA[27]; !nIRQ4 = VSYNC & INT_ENA[28]; - nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; + !nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29]; !nIRQ6 = !nMFP_INT & INT_ENA[30]; !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..4]==H"F8E0" -- VME - # FB_ADR[19..4]==H"F920" -- PADDLE - # FB_ADR[19..4]==H"F921" -- PADDLE - # FB_ADR[19..4]==H"F922" -- PADDLE +-- # FB_ADR[19..4]==H"F920" -- PADDLE +-- # FB_ADR[19..4]==H"F921" -- PADDLE +-- # FB_ADR[19..4]==H"F922" -- PADDLE # FB_ADR[19..4]==H"FFA8" -- MFP2 # FB_ADR[19..4]==H"FFA9" -- MFP2 # FB_ADR[19..4]==H"FFAA" -- MFP2 @@ -140,28 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..8]==H"F87" -- TT SCSI # FB_ADR[19..4]==H"FFC2" -- ST UHR # FB_ADR[19..4]==H"FFC3" -- ST UHR - # FB_ADR[19..4]==H"F890" -- DMA SOUND - # FB_ADR[19..4]==H"F891" -- DMA SOUND - # FB_ADR[19..4]==H"F892"); -- DMA SOUND - +-- # FB_ADR[19..4]==H"F890" -- DMA SOUND +-- # FB_ADR[19..4]==H"F891" -- DMA SOUND +-- # FB_ADR[19..4]==H"F892" -- DMA SOUND + ); -- IF VIDEO ADR CHANGE TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 -- INTERRUPT LATCH - INT_LATCH[] = H"FFFFFFFF"; - INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; - INT_LATCH1.CLK = E0_INT & INT_ENA[1]; - INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; - INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; - INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; - INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; - INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; - INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; - INT_LATCH8.CLK = VSYNC & INT_ENA[8]; - INT_LATCH9.CLK = HSYNC & INT_ENA[9]; + INT_L[].CLK = MAIN_CLK; + INT_L[].CLRN = nRSTO; + INT_L0 = PIC_INT & INT_ENA[0]; + INT_L1 = E0_INT & INT_ENA[1]; + INT_L2 = DVI_INT & INT_ENA[2]; + INT_L3 = !nPCI_INTA & INT_ENA[3]; + INT_L4 = !nPCI_INTB & INT_ENA[4]; + INT_L5 = !nPCI_INTC & INT_ENA[5]; + INT_L6 = !nPCI_INTD & INT_ENA[6]; + INT_L7 = DSP_INT & INT_ENA[7]; + INT_L8 = VSYNC & INT_ENA[8]; + INT_L9 = HSYNC & INT_ENA[9]; --- INTERRUPT CLEAR - INT_LATCH[].CLRN = !INT_CLEAR[]; + INT_LA[][].CLK = MAIN_CLK; + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO; + FOR I IN 0 TO 9 GENERATE + INT_LA[I][].CLRN = INT_ENA[I] & nRSTO; + INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7 + # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8 + # 15 & INT_L[I] & INT_LA[I][]>6 + # 0 & !INT_L[I] & INT_LA[I][]<9; + INT_LATCH[I].CLK = INT_LA[I][3]; + END GENERATE; -- INT_IN INT_IN0 = PIC_INT; @@ -181,7 +191,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN30 = !nMFP_INT; INT_IN31 = DMA_DRQ; - --*************************************************************************************** -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE ACP_CONF[].CLK = MAIN_CLK; @@ -212,130 +221,16 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[7..0][10] = FB_AD[23..16]; - WERTE[7..0][11] = FB_AD[23..16]; - WERTE[7..0][12] = FB_AD[23..16]; - WERTE[7..0][13] = FB_AD[23..16]; - WERTE[7..0][14] = FB_AD[23..16]; - WERTE[7..0][15] = FB_AD[23..16]; - WERTE[7..0][16] = FB_AD[23..16]; - WERTE[7..0][17] = FB_AD[23..16]; - WERTE[7..0][18] = FB_AD[23..16]; - WERTE[7..0][19] = FB_AD[23..16]; - WERTE[7..0][20] = FB_AD[23..16]; - WERTE[7..0][21] = FB_AD[23..16]; - WERTE[7..0][22] = FB_AD[23..16]; - WERTE[7..0][23] = FB_AD[23..16]; - WERTE[7..0][24] = FB_AD[23..16]; - WERTE[7..0][25] = FB_AD[23..16]; - WERTE[7..0][26] = FB_AD[23..16]; - WERTE[7..0][27] = FB_AD[23..16]; - WERTE[7..0][28] = FB_AD[23..16]; - WERTE[7..0][29] = FB_AD[23..16]; - WERTE[7..0][30] = FB_AD[23..16]; - WERTE[7..0][31] = FB_AD[23..16]; - WERTE[7..0][32] = FB_AD[23..16]; - WERTE[7..0][33] = FB_AD[23..16]; - WERTE[7..0][34] = FB_AD[23..16]; - WERTE[7..0][35] = FB_AD[23..16]; - WERTE[7..0][36] = FB_AD[23..16]; - WERTE[7..0][37] = FB_AD[23..16]; - WERTE[7..0][38] = FB_AD[23..16]; - WERTE[7..0][39] = FB_AD[23..16]; - WERTE[7..0][40] = FB_AD[23..16]; - WERTE[7..0][41] = FB_AD[23..16]; - WERTE[7..0][42] = FB_AD[23..16]; - WERTE[7..0][43] = FB_AD[23..16]; - WERTE[7..0][44] = FB_AD[23..16]; - WERTE[7..0][45] = FB_AD[23..16]; - WERTE[7..0][46] = FB_AD[23..16]; - WERTE[7..0][47] = FB_AD[23..16]; - WERTE[7..0][48] = FB_AD[23..16]; - WERTE[7..0][49] = FB_AD[23..16]; - WERTE[7..0][50] = FB_AD[23..16]; - WERTE[7..0][51] = FB_AD[23..16]; - WERTE[7..0][52] = FB_AD[23..16]; - WERTE[7..0][53] = FB_AD[23..16]; - WERTE[7..0][54] = FB_AD[23..16]; - WERTE[7..0][55] = FB_AD[23..16]; - WERTE[7..0][56] = FB_AD[23..16]; - WERTE[7..0][57] = FB_AD[23..16]; - WERTE[7..0][58] = FB_AD[23..16]; - WERTE[7..0][59] = FB_AD[23..16]; - WERTE[7..0][60] = FB_AD[23..16]; - WERTE[7..0][61] = FB_AD[23..16]; - WERTE[7..0][62] = FB_AD[23..16]; - WERTE[7..0][63] = FB_AD[23..16]; - WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; - WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; - WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; - WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; - WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; - WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; - WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; - WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; - WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; - WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; - WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; - WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; - WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; - WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; - WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; - WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; - WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; - WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; - WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; - WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; - WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; - WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; - WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; - WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; - WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; - WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; - WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; - WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; - WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; - WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; - WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; - WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; - WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; - WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; - WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; - WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; - WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; - WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; - WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; - WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; - WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; - WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; - WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; - WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; - WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; - WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; - WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; - WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; - WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; - WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; - WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; - WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; - WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; - WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; - WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; - WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; - WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; - WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; - WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; - WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; - WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; - WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; - WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; - + FOR I IN 10 TO 63 GENERATE + WERTE[7..0][I] = FB_AD[23..16]; + END GENERATE; + FOR I IN 0 TO 63 GENERATE + WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR; + END GENERATE; PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; - UPDATE_ON = !WERTE[7][11]; WERTE[6][10].CLRN = GND; -- KEIN UIP UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF @@ -343,57 +238,48 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG - --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER - -- ACHTELSEKUNDEN ACHTELSEKUNDEN[].CLK = MAIN_CLK; ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; - -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); - -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- - -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG - INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- - -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); - -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); - -- TRISTATE OUTPUT FB_AD[31..24] = lpm_bustri_BYT( @@ -475,7 +361,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[23..16] # ACP_CONF_CS & ACP_CONF[23..16] ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[15..8] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[15..8] # INT_ENA_CS & INT_ENA[15..8] @@ -483,7 +368,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[15..8] # ACP_CONF_CS & ACP_CONF[15..8] ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[7..0] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[7..0] # INT_ENA_CS & INT_ENA[7..0] diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index 04aeb66..b083539 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -28,29 +28,30 @@ ENTITY blitter IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); - BLITTER_ON : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + BLITTER_ON : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + DDRCLK0 : IN std_logic; + BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); + BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); + SR_BLITTER_DACK : IN std_logic; + BLITTER_RUN : OUT std_logic; + BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0); + BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); + BLITTER_SIG : OUT std_logic; + BLITTER_WR : OUT std_logic; + BLITTER_TA : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! diff --git a/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip b/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip new file mode 100644 index 0000000..c42bd21 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip b/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip new file mode 100644 index 0000000..737f0c0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index f74f1dd..28c1ef3 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -1,4 +1,4 @@ -TITLE "VIDEO MODI AND CLUT CONTROL"; +TITLE "VIDEO MODUSE UND CLUT CONTROL"; -- CREATED BY FREDI ASCHWANDEN @@ -98,12 +98,12 @@ VARIABLE VDL_LWD[15..0] :DFFE; VDL_LWD_CS :NODE; -- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- needs one wait state + CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- length of hsync pulse in pixel_clk + HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK HSYNC_START :DFF; - LAST :DFF; -- reached last pixel of a line + LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT VSYNC :DFF; VSYNC_START :DFFE; VSYNC_I[2..0] :DFFE; @@ -191,7 +191,6 @@ VARIABLE VDL_VCT_CS :NODE; VDL_VMD[3..0] :DFFE; VDL_VMD_CS :NODE; - ACP_VCTR6_DUP : NODE; BEGIN -- BYT SELECT 32 BIT @@ -204,75 +203,46 @@ BEGIN FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - -- BYT SELECT 16 BIT FB_16B0 = FB_ADR[0] == 0; -- ADR==0 FB_16B1 = FB_ADR[0] == 1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT - -- ACP CLUT -- ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; - - --FALCON CLUT -- FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - - -- ST CLUT -- ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; - - -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 ST_SHIFT_MODE[] = FB_AD[25..24]; ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN - - -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE[] = FB_AD[26..16]; FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; - - - -- ACP VIDEO CONTROL - -- BIT 0=ACP VIDEO ON, - -- 1=POWER ON VIDEO DAC, - -- 2=ACP 24BIT, - -- 3=ACP 16BIT, - -- 4=ACP 8BIT, - -- 5=ACP 1BIT, - -- 6=FALCON SHIFT MODE, - -- 7=ST SHIFT MODE, - -- 9..8= VCLK FREQUENZ, - -- 15=-SYNC ALLOWED, - -- 31..16=VIDEO_RAM_CTR, - -- 25=RANDFARBE EINSCHALTEN, - -- 26=STANDARD ATARI SYNCS +-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; @@ -283,10 +253,8 @@ BEGIN ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; - -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL�SUNG - + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 @@ -295,7 +263,6 @@ BEGIN ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 ATARI_VH[].CLK = MAIN_CLK; ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 @@ -304,7 +271,6 @@ BEGIN ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 ATARI_HL[].CLK = MAIN_CLK; ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 @@ -313,7 +279,6 @@ BEGIN ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 ATARI_VL[].CLK = MAIN_CLK; ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 @@ -322,8 +287,6 @@ BEGIN ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; - - -- VIDEO PLL CONFIG VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VR_WR.CLK = MAIN_CLK; @@ -335,28 +298,21 @@ BEGIN VR_FRQ[].CLK = MAIN_CLK; VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; VR_FRQ[] = FB_AD[23..16]; - -- VIDEO PLL RECONFIG VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; - ------------------------------------------------------------------------------------------------------------------------ VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; - -------------- COLOR MODE IM ACP SETZEN COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; - -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - - -- duplicate ACP_VCTR6 according to TimeQuest recommendations - ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ACP_VCTR6_DUP; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; FALCON_VIDEO = ACP_VCTR7; FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; @@ -369,9 +325,7 @@ BEGIN # B"101" & COLOR16 # B"110" & COLOR24 # B"111" & RAND_ON; - -- DIVERSE (VIDEO)-REGISTER ---------------------------- - -- RANDFARBE CCR[].CLK = MAIN_CLK; CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 @@ -379,129 +333,109 @@ BEGIN CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; - --SYS CTR SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; BLITTER_ON = !SYS_CTR3; - --VDL_LOF VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 VDL_LOF[].CLK = MAIN_CLK; VDL_LOF[] = FB_AD[31..16]; VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; - --VDL_LWD VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 VDL_LWD[].CLK = MAIN_CLK; VDL_LWD[] = FB_AD[31..16]; VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; - -- HORIZONTAL - -- VDL_HHT VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 VDL_HHT[].CLK = MAIN_CLK; VDL_HHT[] = FB_AD[27..16]; VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; - -- VDL_HBE VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 VDL_HBE[].CLK = MAIN_CLK; VDL_HBE[] = FB_AD[27..16]; VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; - -- VDL_HDB VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 VDL_HDB[].CLK = MAIN_CLK; VDL_HDB[] = FB_AD[27..16]; VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; - -- VDL_HDE VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 VDL_HDE[].CLK = MAIN_CLK; VDL_HDE[] = FB_AD[27..16]; VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; - -- VDL_HBB VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 VDL_HBB[].CLK = MAIN_CLK; VDL_HBB[] = FB_AD[27..16]; VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; - -- VDL_HSS VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 VDL_HSS[].CLK = MAIN_CLK; VDL_HSS[] = FB_AD[27..16]; VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; - -- VERTIKAL - -- VDL_VBE VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 VDL_VBE[].CLK = MAIN_CLK; VDL_VBE[] = FB_AD[26..16]; VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; - -- VDL_VDB VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 VDL_VDB[].CLK = MAIN_CLK; VDL_VDB[] = FB_AD[26..16]; VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; - -- VDL_VDE VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 VDL_VDE[].CLK = MAIN_CLK; VDL_VDE[] = FB_AD[26..16]; VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; - -- VDL_VBB VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 VDL_VBB[].CLK = MAIN_CLK; VDL_VBB[] = FB_AD[26..16]; VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; - -- VDL_VSS VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 VDL_VSS[].CLK = MAIN_CLK; VDL_VSS[] = FB_AD[26..16]; VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; - -- VDL_VFT VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 VDL_VFT[].CLK = MAIN_CLK; VDL_VFT[] = FB_AD[26..16]; VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; - -- VDL_VCT VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 VDL_VCT[].CLK = MAIN_CLK; VDL_VCT[] = FB_AD[24..16]; VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; - -- VDL_VMD VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 VDL_VMD[].CLK = MAIN_CLK; VDL_VMD[] = FB_AD[19..16]; VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; - --- REGISTER OUT FB_AD[31..16] = lpm_bustri_WORD( ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") @@ -550,9 +484,8 @@ BEGIN # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; - -- VIDEO AUSGABE SETZEN - CLK17M.CLK = MAIN_CLK; + CLK17M.CLK = CLK33M; CLK17M = !CLK17M; CLK13M.CLK = CLK25M; CLK13M = !CLK13M; @@ -563,9 +496,8 @@ BEGIN # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; - -------------------------------------------------------------- - -- HORIZONTALE SYNC L�NGE in PIXEL_CLK +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ---------------------------------------------------------------- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) @@ -585,7 +517,6 @@ BEGIN HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN # 640 & !VDL_VMD2; - -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS @@ -593,7 +524,7 @@ BEGIN INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L�SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 @@ -635,8 +566,7 @@ BEGIN # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - - -- Z�HLER +-- ZÄHLER LAST.CLK = PIXEL_CLK; LAST = VHCNT[]==(H_TOTAL[]-2); VHCNT[].CLK = PIXEL_CLK; @@ -644,11 +574,10 @@ BEGIN VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); - -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] "AUTO", - clk0_divide_by => 66, + clk0_divide_by => 11, clk0_duty_cycle => 50, - clk0_multiply_by => 1, + clk0_multiply_by => 16, clk0_phase_shift => "0", - clk1_divide_by => 6875, + clk1_divide_by => 33, clk1_duty_cycle => 50, - clk1_multiply_by => 512, + clk1_multiply_by => 16, clk1_phase_shift => "0", clk2_divide_by => 1375, clk2_duty_cycle => 50, @@ -218,7 +218,7 @@ BEGIN PORT MAP ( inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire2 + locked => sub_wire4 ); @@ -244,14 +244,14 @@ END SYN; -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" @@ -270,21 +270,21 @@ END SYN; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" @@ -298,7 +298,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" @@ -338,13 +338,13 @@ END SYN; -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" @@ -406,17 +406,17 @@ END SYN; -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE diff --git a/FPGA_Quartus_13.1/altpll2.bsf b/FPGA_Quartus_13.1/altpll2.bsf index 4bad59d..ac3d77f 100644 --- a/FPGA_Quartus_13.1/altpll2.bsf +++ b/FPGA_Quartus_13.1/altpll2.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2014 Altera Corporation +Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.2")) +(header "symbol" (version "1.1")) (symbol - (rect 0 0 256 200) - (text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 185 26 196)(font "Arial" )) + (rect 0 0 304 248) + (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 229 31 244)(font "Arial" )) (port - (pt 0 64) + (pt 0 72) (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) ) (port - (pt 256 64) + (pt 304 72) (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)(line_width 1)) ) (port - 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DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS width_clock : NATURAL ); PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) ); END COMPONENT; @@ -149,14 +149,14 @@ BEGIN sub_wire8_bv(0 DOWNTO 0) <= "0"; sub_wire8 <= To_stdlogicvector(sub_wire8_bv); sub_wire5 <= sub_wire0(4); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; c4 <= sub_wire5; sub_wire6 <= inclk0; sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; @@ -293,7 +293,7 @@ END SYN; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" @@ -459,18 +459,18 @@ END SYN; -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE diff --git a/FPGA_Quartus_13.1/altpll3.bsf b/FPGA_Quartus_13.1/altpll3.bsf index 98eb9cf..1665956 100644 --- a/FPGA_Quartus_13.1/altpll3.bsf +++ b/FPGA_Quartus_13.1/altpll3.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2014 Altera Corporation +Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,88 +18,95 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.2")) +(header "symbol" (version "1.1")) (symbol - (rect 0 0 256 184) - (text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 169 26 180)(font "Arial" )) + (rect 0 0 272 200) + (text "altpll3" (rect 119 0 159 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 184 25 196)(font "Arial" )) (port (pt 0 64) (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) + (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)(line_width 1)) ) (port - (pt 256 64) + (pt 272 64) (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8))) + (line (pt 272 64)(pt 224 64)(line_width 1)) ) (port - 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c3 : OUT STD_LOGIC + c3 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ); end component; diff --git a/FPGA_Quartus_13.1/altpll3.inc b/FPGA_Quartus_13.1/altpll3.inc index 66f8ef8..9b8ca64 100644 --- a/FPGA_Quartus_13.1/altpll3.inc +++ b/FPGA_Quartus_13.1/altpll3.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -22,5 +22,6 @@ RETURNS ( c0, c1, c2, - c3 + c3, + locked ); diff --git a/FPGA_Quartus_13.1/altpll3.ppf b/FPGA_Quartus_13.1/altpll3.ppf index c840c97..a771350 100644 --- a/FPGA_Quartus_13.1/altpll3.ppf +++ b/FPGA_Quartus_13.1/altpll3.ppf @@ -7,6 +7,7 @@ + diff --git a/FPGA_Quartus_13.1/altpll3.qip b/FPGA_Quartus_13.1/altpll3.qip index 0b0f8f4..adefea9 100644 --- a/FPGA_Quartus_13.1/altpll3.qip +++ b/FPGA_Quartus_13.1/altpll3.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] diff --git a/FPGA_Quartus_13.1/altpll3.vhd b/FPGA_Quartus_13.1/altpll3.vhd index be0649b..9176b7a 100644 --- a/FPGA_Quartus_13.1/altpll3.vhd +++ b/FPGA_Quartus_13.1/altpll3.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -46,7 +46,8 @@ ENTITY altpll3 IS c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC + c3 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ); END altpll3; @@ -59,9 +60,10 @@ ARCHITECTURE SYN OF altpll3 IS SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -131,48 +133,51 @@ ARCHITECTURE SYN OF altpll3 IS port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; width_clock : NATURAL ); PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) ); END COMPONENT; BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + locked <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", clk0_divide_by => 33, clk0_duty_cycle => 50, - clk0_multiply_by => 2, + clk0_multiply_by => 25, clk0_phase_shift => "0", clk1_divide_by => 33, clk1_duty_cycle => 50, - clk1_multiply_by => 16, + clk1_multiply_by => 2, clk1_phase_shift => "0", - clk2_divide_by => 300, + clk2_divide_by => 66, clk2_duty_cycle => 50, - clk2_multiply_by => 227, + clk2_multiply_by => 1, clk2_phase_shift => "0", - clk3_divide_by => 156, + clk3_divide_by => 6875, clk3_duty_cycle => 50, - clk3_multiply_by => 227, + clk3_multiply_by => 512, clk3_phase_shift => "0", - compensate_clock => "CLK1", + compensate_clock => "CLK0", inclk0_input_frequency => 30303, intended_device_family => "Cyclone III", lpm_type => "altpll", @@ -188,7 +193,7 @@ BEGIN port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", + port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", @@ -219,11 +224,13 @@ BEGIN port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", width_clock => 5 ) PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0 + inclk => sub_wire7, + clk => sub_wire0, + locked => sub_wire5 ); @@ -246,21 +253,21 @@ END SYN; -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "72" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "906" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3072" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "738" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -276,9 +283,9 @@ END SYN; -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" @@ -289,19 +296,19 @@ END SYN; -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" @@ -316,7 +323,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -359,21 +366,21 @@ END SYN; -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "66" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6875" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" @@ -389,7 +396,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" @@ -420,6 +427,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" @@ -428,18 +436,20 @@ END SYN; -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll4.bsf b/FPGA_Quartus_13.1/altpll4.bsf index f74527e..e071d43 100644 --- a/FPGA_Quartus_13.1/altpll4.bsf +++ b/FPGA_Quartus_13.1/altpll4.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2014 Altera Corporation +Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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-- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) --- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif --- Generated: Mon Sep 21 17:50:54 2015 +-- File Name: C:\FireBee\FPGA\altpll4.mif +-- Generated: Mon Dec 06 01:47:24 2010 WIDTH=1; DEPTH=144; diff --git a/FPGA_Quartus_13.1/altpll4.qip b/FPGA_Quartus_13.1/altpll4.qip index ded02bb..f44acdc 100644 --- a/FPGA_Quartus_13.1/altpll4.qip +++ b/FPGA_Quartus_13.1/altpll4.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] diff --git a/FPGA_Quartus_13.1/altpll4.tdf b/FPGA_Quartus_13.1/altpll4.tdf index 8e72bcc..3ec77d4 100644 --- a/FPGA_Quartus_13.1/altpll4.tdf +++ b/FPGA_Quartus_13.1/altpll4.tdf @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -59,7 +59,7 @@ VARIABLE CLK0_MULTIPLY_BY = 2, CLK0_PHASE_SHIFT = "0", COMPENSATE_CLOCK = "CLK0", - INCLK0_INPUT_FREQUENCY = 20824, + INCLK0_INPUT_FREQUENCY = 20833, INTENDED_DEVICE_FAMILY = "Cyclone III", LPM_TYPE = "altpll", OPERATION_MODE = "NORMAL", @@ -113,16 +113,16 @@ VARIABLE BEGIN c0 = altpll_component.clk[0..0]; - scandataout = altpll_component.scandataout; scandone = altpll_component.scandone; + scandataout = altpll_component.scandataout; locked = altpll_component.locked; - altpll_component.areset = areset; - altpll_component.configupdate = configupdate; + altpll_component.scanclkena = scanclkena; altpll_component.inclk[0..0] = inclk0; altpll_component.inclk[1..1] = GND; - altpll_component.scanclk = scanclk; - altpll_component.scanclkena = scanclkena; altpll_component.scandata = scandata; + altpll_component.areset = areset; + altpll_component.scanclk = scanclk; + altpll_component.configupdate = configupdate; END; @@ -148,7 +148,7 @@ END; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -156,7 +156,7 @@ END; -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" @@ -166,7 +166,7 @@ END; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" @@ -217,7 +217,7 @@ END; -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" @@ -277,22 +277,22 @@ END; -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 --- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 --- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 -- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index abc22f8..4f32a08 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -25,660 +25,643 @@ applicable agreement for further details. ) (pin (input) - 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(line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 600 456 664 472)) -) -(pin - (input) - (rect 168 296 344 312) + (rect 96 -288 264 -272) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "MAIN_CLK" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 112 312 168 328)) + (annotation_block (location)(rect 48 -272 96 -256)) ) (pin - (output) - (rect 864 288 1040 304) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "CLK24M576" (rect 90 0 152 11)(font "Arial" )) - (pt 0 8) + (input) + (rect 592 440 760 456) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nRSTO_MCF" (rect 9 0 77 11)(font "Arial" )) + (pt 168 8) (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) ) - (annotation_block (location)(rect 1040 304 1112 320)) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 536 456 592 472)) +) +(pin + (input) + (rect 56 304 224 320) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "CLK33MDIR" (rect 9 0 72 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect -8 320 56 336)) ) (pin (output) @@ -905,7 +888,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 848 2064 864)) + (annotation_block (location)(rect 2008 848 2096 880)) ) (pin (output) @@ -922,7 +905,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 952 2064 968)) + (annotation_block (location)(rect 2008 952 2056 968)) ) (pin (output) @@ -939,7 +922,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 976 2064 992)) + (annotation_block (location)(rect 2008 976 2056 992)) ) (pin (output) @@ -956,7 +939,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 1000 2064 1016)) + (annotation_block (location)(rect 2008 1000 2056 1016)) ) (pin (output) @@ -973,7 +956,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 1024 2064 1040)) + (annotation_block (location)(rect 2008 1024 2056 1040)) ) (pin (output) @@ -990,7 +973,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 1048 2064 1064)) + (annotation_block (location)(rect 2008 1048 2056 1064)) ) (pin (output) @@ -1007,7 +990,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1128 2072 1144)) + (annotation_block (location)(rect 2016 1128 2064 1144)) ) (pin (output) @@ -1024,7 +1007,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1152 2072 1168)) + (annotation_block (location)(rect 2016 1152 2064 1168)) ) (pin (output) @@ -1041,28 +1024,11 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1176 2072 1192)) + (annotation_block (location)(rect 2016 1176 2064 1192)) ) (pin (output) - (rect 1920 1264 2096 1280) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "MIDI_OLR" (rect 90 0 144 11)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) - ) - (annotation_block (location)(rect 2096 1280 2152 1296)) -) -(pin - (output) - (rect 1920 1288 2096 1304) + (rect 1832 2240 2008 2256) (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "MIDI_TLR" (rect 90 0 141 11)(font "Arial" )) (pt 0 8) @@ -1075,7 +1041,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1304 2152 1320)) + (annotation_block (location)(rect 2008 2256 2056 2272)) ) (pin (output) @@ -1092,7 +1058,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1336 2080 1352)) + (annotation_block (location)(rect 2016 1336 2072 1352)) ) (pin (output) @@ -1109,7 +1075,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1360 2080 1376)) + (annotation_block (location)(rect 2016 1360 2072 1376)) ) (pin (output) @@ -1126,7 +1092,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1384 2088 1400)) + (annotation_block (location)(rect 2024 1384 2080 1400)) ) (pin (output) @@ -1143,7 +1109,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2288 1416 2344 1432)) + (annotation_block (location)(rect 2288 1416 2376 1448)) ) (pin (output) @@ -1160,7 +1126,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1448 2080 1464)) + (annotation_block (location)(rect 2024 1448 2072 1464)) ) (pin (output) @@ -1177,7 +1143,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1472 2080 1488)) + (annotation_block (location)(rect 2024 1472 2072 1488)) ) (pin (output) @@ -1194,7 +1160,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 1496 2088 1512)) + (annotation_block (location)(rect 2032 1496 2080 1512)) ) (pin (output) @@ -1211,7 +1177,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1520 2080 1536)) + (annotation_block (location)(rect 2024 1520 2072 1536)) ) (pin (output) @@ -1228,7 +1194,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1544 2080 1560)) + (annotation_block (location)(rect 2024 1544 2072 1560)) ) (pin (output) @@ -1279,7 +1245,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1624 2152 1640)) + (annotation_block (location)(rect 2096 1624 2144 1640)) ) (pin (output) @@ -1296,7 +1262,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1648 2152 1664)) + (annotation_block (location)(rect 2096 1648 2144 1664)) ) (pin (output) @@ -1313,7 +1279,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1672 2152 1688)) + (annotation_block (location)(rect 2096 1672 2144 1688)) ) (pin (output) @@ -1330,7 +1296,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1696 2152 1712)) + (annotation_block (location)(rect 2096 1696 2144 1712)) ) (pin (output) @@ -1347,7 +1313,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 1872 2096 1888)) + (annotation_block (location)(rect 2032 1872 2088 1888)) ) (pin (output) @@ -1364,7 +1330,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1848 2376 1864)) + (annotation_block (location)(rect 2312 1848 2368 1864)) ) (pin (output) @@ -1381,7 +1347,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1824 2376 1840)) + (annotation_block (location)(rect 2312 1824 2368 1840)) ) (pin (output) @@ -1398,7 +1364,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2104 1928 2168 1944)) + (annotation_block (location)(rect 2104 1928 2160 1944)) ) (pin (output) @@ -1415,7 +1381,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2104 1952 2168 1968)) + (annotation_block (location)(rect 2104 1952 2160 1968)) ) (pin (output) @@ -1432,7 +1398,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2104 1976 2168 1992)) + (annotation_block (location)(rect 2104 1976 2160 1992)) ) (pin (output) @@ -1449,7 +1415,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 2056 2096 2072)) + (annotation_block (location)(rect 2032 2056 2088 2072)) ) (pin (output) @@ -1466,7 +1432,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 1728 2096 1744)) + (annotation_block (location)(rect 2032 1728 2088 1744)) ) (pin (output) @@ -1483,7 +1449,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2256 88 2312 104)) + (annotation_block (location)(rect 2280 24 2360 152)) ) (pin (output) @@ -1500,7 +1466,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2176 112 2240 128)) + (annotation_block (location)(rect 2192 112 2272 240)) ) (pin (output) @@ -1517,7 +1483,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2088 136 2152 152)) + (annotation_block (location)(rect 2104 144 2184 272)) ) (pin (output) @@ -1534,7 +1500,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2704 336 2768 352)) + (annotation_block (location)(rect 2736 344 2800 544)) ) (pin (output) @@ -1551,7 +1517,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2576 360 2640 376)) + (annotation_block (location)(rect 2576 360 2632 392)) ) (pin (output) @@ -1568,7 +1534,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2480 384 2552 400)) + (annotation_block (location)(rect 2480 384 2544 416)) ) (pin (output) @@ -1585,7 +1551,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2384 408 2448 424)) + (annotation_block (location)(rect 2384 408 2440 440)) ) (pin (output) @@ -1602,7 +1568,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2216 432 2280 448)) + (annotation_block (location)(rect 2216 432 2272 464)) ) (pin (output) @@ -1619,7 +1585,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2120 576 2192 592)) + (annotation_block (location)(rect 2144 592 2208 664)) ) (pin (output) @@ -1636,7 +1602,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 280 2064 296)) + (annotation_block (location)(rect 2008 280 2056 296)) ) (pin (output) @@ -1653,24 +1619,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 2432 2064 2448)) -) -(pin - (output) - (rect 776 0 952 16) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "CLK25M" (rect 90 0 134 11)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) - ) - (annotation_block (location)(rect 952 16 1008 32)) + (annotation_block (location)(rect 2008 2432 2096 2560)) ) (pin (output) @@ -1687,7 +1636,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 2648 2064 2664)) + (annotation_block (location)(rect 2008 2648 2056 2664)) ) (pin (output) @@ -1704,7 +1653,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3296 2056 3312)) + (annotation_block (location)(rect 2000 3296 2088 3328)) ) (pin (output) @@ -1721,7 +1670,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3320 2056 3336)) + (annotation_block (location)(rect 2000 3320 2088 3352)) ) (pin (output) @@ -1738,7 +1687,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3344 2056 3360)) + (annotation_block (location)(rect 2000 3344 2088 3376)) ) (pin (output) @@ -1755,7 +1704,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3368 2056 3384)) + (annotation_block (location)(rect 2000 3368 2088 3400)) ) (pin (output) @@ -1789,7 +1738,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 784 2144 848 2160)) + (annotation_block (location)(rect 784 2144 840 2176)) ) (pin (output) @@ -1823,7 +1772,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2120 456 2184 472)) + (annotation_block (location)(rect 2120 456 2176 488)) ) (pin (output) @@ -1840,7 +1789,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2232 744 2288 760)) + (annotation_block (location)(rect 2232 744 2280 760)) ) (pin (output) @@ -1857,7 +1806,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 896 2960 912)) + (annotation_block (location)(rect 2888 896 2952 928)) ) (pin (output) @@ -1874,7 +1823,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2712 768 2784 784)) + (annotation_block (location)(rect 2712 768 2776 800)) ) (pin (output) @@ -1891,7 +1840,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 480 2072 496)) + (annotation_block (location)(rect 2008 480 2072 528)) ) (pin (output) @@ -1908,7 +1857,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 -56 2376 -40)) + (annotation_block (location)(rect 2232 -32 2312 0)) ) (pin (output) @@ -1925,7 +1874,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 -72 2952 -56)) + (annotation_block (location)(rect 2888 -72 2968 -40)) ) (pin (output) @@ -1942,7 +1891,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 48 2952 64)) + (annotation_block (location)(rect 2888 48 2968 80)) ) (pin (output) @@ -1959,7 +1908,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 176 2952 192)) + (annotation_block (location)(rect 2888 176 2968 208)) ) (pin (output) @@ -1976,7 +1925,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 232 2072 248)) + (annotation_block (location)(rect 2008 232 2096 264)) ) (pin (output) @@ -1993,7 +1942,7 @@ applicable agreement for further details. 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(block_io "nIDE_WR" (output)) + (block_io "AMKB_TX" (output)) + (block_io "IDE_RES" (output)) + (block_io "DTR" (output)) + (block_io "RTS" (output)) + (block_io "TxD" (output)) + (block_io "MIDI_OLR" (output)) + (block_io "nDREQ0" (output)) + (block_io "DSA_D" (output)) + (block_io "nMFP_INT" (output)) + (block_io "FALCON_IO_TA" (output)) + (block_io "STEP_DIR" (output)) + (block_io "WR_DATA" (output)) + (block_io "WR_GATE" (output)) + (block_io "DMA_DRQ" (output)) + (block_io "MIDI_TLR" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "LP_D[7..0]" (bidir)) + (block_io "ACSI_D[7..0]" (bidir)) + (block_io "SCSI_D[7..0]" (bidir)) + (block_io "SCSI_PAR" (bidir)) + (block_io "nSCSI_SEL" (bidir)) + (block_io "nSCSI_BUSY" (bidir)) + (block_io "nSCSI_RST" (bidir)) + (block_io "SD_CD_DATA3" (bidir)) + (block_io "SD_CDM_D1" (bidir)) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 408 96) + (bidir) + ) + (mapper + (pt 408 120) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 408 152) + (bidir) + ) + (mapper + (pt 408 200) + (bidir) + ) + (mapper + (pt 408 224) + (bidir) + ) + (mapper + (pt 408 248) + (bidir) + ) + (mapper + (pt 408 272) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 408 424) + (bidir) + ) + (mapper + (pt 408 352) + (bidir) + ) + (mapper + (pt 408 328) + (bidir) + ) + (mapper + (pt 408 448) + (bidir) + ) + (mapper + (pt 408 400) + (bidir) + ) + (mapper + (pt 408 376) + (bidir) + ) + (mapper + (pt 408 472) + (bidir) + ) + (mapper + (pt 408 496) + (bidir) + ) + (mapper + (pt 408 608) + (bidir) + ) + (mapper + (pt 408 632) + (bidir) + ) + (mapper + (pt 408 584) + (bidir) + ) + (mapper + (pt 0 656) + (bidir) + ) + (mapper + (pt 0 680) + (bidir) + ) + (mapper + (pt 0 704) + (bidir) + ) + (mapper + (pt 0 728) + (bidir) + ) + (mapper + (pt 0 752) + (bidir) + ) + (mapper + (pt 0 776) + (bidir) + ) + (mapper + (pt 408 664) + (bidir) + ) + (mapper + (pt 0 808) + (bidir) + ) + (mapper + (pt 0 832) + (bidir) + ) + (mapper + (pt 408 696) + (bidir) + ) + (mapper + (pt 408 720) + (bidir) + ) + (mapper + (pt 408 744) + (bidir) + ) + (mapper + (pt 408 768) + (bidir) + ) + (mapper + (pt 408 792) + (bidir) + ) + (mapper + (pt 408 816) + (bidir) + ) + (mapper + (pt 408 840) + (bidir) + ) + (mapper + (pt 0 856) + (bidir) + ) + (mapper + (pt 408 872) + (bidir) + ) + (mapper + (pt 408 896) + (bidir) + ) + (mapper + (pt 408 920) + (bidir) + ) + (mapper + (pt 408 944) + (bidir) + ) + (mapper + (pt 0 912) + (bidir) + ) + (mapper + (pt 0 936) + (bidir) + ) + (mapper + (pt 0 960) + (bidir) + ) + (mapper + (pt 0 984) + (bidir) + ) + (mapper + (pt 0 1008) + (bidir) + ) + (mapper + (pt 408 976) + (bidir) + ) + (mapper + (pt 408 1000) + (bidir) + ) + (mapper + (pt 408 1072) + (bidir) + ) + (mapper + (pt 408 1096) + (bidir) + ) + (mapper + (pt 408 1176) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 1256) + (bidir) + ) + (mapper + (pt 0 1040) + (bidir) + ) + (mapper + (pt 0 1064) + (bidir) + ) + (mapper + (pt 0 1088) + (bidir) + ) + (mapper + (pt 0 1112) + (bidir) + ) + (mapper + (pt 0 1136) + (bidir) + ) + (mapper + (pt 0 432) + (bidir) + ) + (mapper + (pt 0 464) + (bidir) + ) + (mapper + (pt 0 488) + (bidir) + ) + (mapper + (pt 0 520) + (bidir) + ) + (mapper + (pt 0 544) + (bidir) + ) + (mapper + (pt 0 568) + (bidir) + ) + (mapper + (pt 0 592) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 344) + (bidir) + ) + (mapper + (pt 0 1168) + (bidir) + ) + (mapper + (pt 0 1192) + (bidir) + ) + (mapper + (pt 0 368) + (bidir) + ) + (mapper + (pt 0 392) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 1216) + (bidir) + ) + (mapper + (pt 408 48) + (bidir) + ) + (mapper + (pt 408 16) + (bidir) + ) + (mapper + (pt 0 1240) + (bidir) + ) + (mapper + (pt 408 1304) + (bidir) + ) + (mapper + (pt 408 1200) + (bidir) + ) + (mapper + (pt 408 1344) + (bidir) + ) + (mapper + (pt 408 1280) + (bidir) + ) + (mapper + (pt 408 1224) + (bidir) + ) + (mapper + (pt 408 1120) + (bidir) + ) + (mapper + (pt 408 1048) + (bidir) + ) + (mapper + (pt 408 1024) + (bidir) + ) + (mapper + (pt 0 32) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 408 1368) + (bidir) + ) + (mapper + (pt 0 1264) + (bidir) + ) + (mapper + (pt 0 1336) + (bidir) + ) + (mapper + (pt 0 888) + (bidir) + ) + (mapper + (pt 408 1480) + (bidir) + ) + (mapper + (pt 408 1504) + (bidir) + ) + (mapper + (pt 408 1392) + (bidir) + ) + (mapper + (pt 408 1544) + (bidir) + ) +) +(block + (rect 1264 -48 1672 728) (text "video" (rect 5 5 36 18)(font "Arial" (font_size 8))) (text "i_video" (rect 5 762 41 773)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) (block_io "MAIN_CLK" (input)) (block_io "nFB_CS1" (input)) @@ -3718,821 +4450,6 @@ applicable agreement for further details. (bidir) ) ) -(block - (rect 1264 744 1672 2264) - (text "falconio_sdcard_ide_cf" (rect 5 5 135 18)(font "Arial" (font_size 8))) (text "i_falcon_io_sdcard_ide_cf" (rect 5 1506 133 1517)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "CLK2M" (input)) - (block_io "CLK500k" (input)) - (block_io "nFB_CS1" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "LP_BUSY" (input)) - (block_io "nACSI_DRQ" (input)) - (block_io "nACSI_INT" (input)) - (block_io "nSCSI_DRQ" (input)) - (block_io "nSCSI_MSG" (input)) - (block_io "MIDI_IN" (input)) - (block_io "RxD" (input)) - (block_io "CTS" (input)) - (block_io "RI" (input)) - (block_io "DCD" (input)) - (block_io "AMKB_RX" (input)) - (block_io "PIC_AMKB_RX" (input)) - (block_io "IDE_RDY" (input)) - (block_io "IDE_INT" (input)) - (block_io "WP_CS_CARD" (input)) - (block_io "nINDEX" (input)) - (block_io "TRACK00" (input)) - (block_io "nRD_DATA" (input)) - (block_io "nDCHG" (input)) - (block_io "SD_DATA0" (input)) - (block_io "SD_DATA1" (input)) - (block_io "SD_DATA2" (input)) - (block_io "SD_CARD_DEDECT" (input)) - (block_io "SD_WP" (input)) - (block_io "nDACK0" (input)) - (block_io "nFB_WR" (input)) - (block_io "WP_CF_CARD" (input)) - (block_io "nWP" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nRSTO" (input)) - (block_io "nSCSI_C_D" (input)) - (block_io "nSCSI_I_O" (input)) - (block_io "CLK2M4576" (input)) - (block_io "nFB_OE" (input)) - (block_io "VSYNC" (input)) - (block_io "HSYNC" (input)) - (block_io "DSP_INT" (input)) - (block_io "nBLANK" (input)) - (block_io "FDC_CLK" (input)) - (block_io "FB_ALE" (input)) - (block_io "ACP_CONF[31..24]" (input)) - (block_io "HD_DD" (input)) - (block_io "nIDE_CS1" (output)) - (block_io "nIDE_CS0" (output)) - (block_io "LP_STR" (output)) - (block_io "LP_DIR" (output)) - (block_io "nACSI_ACK" (output)) - (block_io "nACSI_RESET" (output)) - (block_io "nACSI_CS" (output)) - (block_io "ACSI_DIR" (output)) - (block_io "ACSI_A1" (output)) - (block_io "nSCSI_ACK" (output)) - (block_io "nSCSI_ATN" (output)) - (block_io "SCSI_DIR" (output)) - (block_io "SD_CLK" (output)) - (block_io "YM_QA" (output)) - (block_io "YM_QC" (output)) - (block_io "YM_QB" (output)) - (block_io "nSDSEL" (output)) - (block_io "STEP" (output)) - (block_io "MOT_ON" (output)) - (block_io "nRP_LDS" (output)) - (block_io "nRP_UDS" (output)) - (block_io "nROM4" (output)) - (block_io "nROM3" (output)) - (block_io "nCF_CS1" (output)) - (block_io "nCF_CS0" (output)) - (block_io "nIDE_RD" (output)) - (block_io "nIDE_WR" (output)) - (block_io "AMKB_TX" (output)) - (block_io "IDE_RES" (output)) - (block_io "DTR" (output)) - (block_io "RTS" (output)) - (block_io "TxD" (output)) - (block_io "MIDI_OLR" (output)) - (block_io "MIDI_TLR" (output)) - (block_io "nDREQ0" (output)) - (block_io "DSA_D" (output)) - (block_io "nMFP_INT" (output)) - (block_io "FALCON_IO_TA" (output)) - (block_io "STEP_DIR" (output)) - (block_io "WR_DATA" (output)) - (block_io "WR_GATE" (output)) - (block_io "DMA_DRQ" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "LP_D[7..0]" (bidir)) - (block_io "ACSI_D[7..0]" (bidir)) - (block_io "SCSI_D[7..0]" (bidir)) - (block_io "SCSI_PAR" (bidir)) - (block_io "nSCSI_SEL" (bidir)) - (block_io "nSCSI_BUSY" (bidir)) - (block_io "nSCSI_RST" (bidir)) - (block_io "SD_CD_DATA3" (bidir)) - (block_io "SD_CDM_D1" (bidir)) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 408 96) - (bidir) - ) - (mapper - (pt 408 120) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 152) - (bidir) - ) - (mapper - (pt 408 200) - (bidir) - ) - (mapper - (pt 408 224) - (bidir) - ) - (mapper - (pt 408 248) - (bidir) - ) - (mapper - (pt 408 272) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 424) - (bidir) - ) - (mapper - (pt 408 352) - (bidir) - ) - (mapper - (pt 408 328) - (bidir) - ) - (mapper - (pt 408 448) - (bidir) - ) - (mapper - (pt 408 400) - (bidir) - ) - (mapper - (pt 408 376) - (bidir) - ) - (mapper - (pt 408 472) - (bidir) - ) - (mapper - (pt 408 496) - (bidir) - ) - (mapper - (pt 408 608) - (bidir) - ) - (mapper - (pt 408 632) - (bidir) - ) - (mapper - (pt 408 528) - (bidir) - ) - (mapper - (pt 408 552) - (bidir) - ) - (mapper - (pt 408 584) - (bidir) - ) - (mapper - (pt 0 624) - (bidir) - ) - (mapper - (pt 0 656) - (bidir) - ) - (mapper - (pt 0 680) - (bidir) - ) - (mapper - (pt 0 704) - (bidir) - ) - (mapper - (pt 0 728) - (bidir) - ) - (mapper - (pt 0 752) - (bidir) - ) - (mapper - (pt 0 776) - (bidir) - ) - (mapper - (pt 408 664) - (bidir) - ) - (mapper - (pt 0 808) - (bidir) - ) - (mapper - (pt 0 832) - (bidir) - ) - (mapper - (pt 408 696) - (bidir) - ) - (mapper - (pt 408 720) - (bidir) - ) - (mapper - (pt 408 744) - (bidir) - ) - (mapper - (pt 408 768) - (bidir) - ) - (mapper - (pt 408 792) - (bidir) - ) - (mapper - (pt 408 816) - (bidir) - ) - (mapper - (pt 408 840) - (bidir) - ) - (mapper - (pt 0 856) - (bidir) - ) - (mapper - (pt 408 872) - (bidir) - ) - (mapper - (pt 408 896) - (bidir) - ) - (mapper - (pt 408 920) - (bidir) - ) - (mapper - (pt 408 944) - (bidir) - ) - (mapper - (pt 0 912) - (bidir) - ) - (mapper - (pt 0 936) - (bidir) - ) - (mapper - (pt 0 960) - (bidir) - ) - (mapper - (pt 0 984) - (bidir) - ) - (mapper - (pt 0 1008) - (bidir) - ) - (mapper - (pt 408 976) - (bidir) - ) - (mapper - (pt 408 1000) - (bidir) - ) - (mapper - (pt 408 1072) - (bidir) - ) - (mapper - (pt 408 1096) - (bidir) - ) - (mapper - (pt 408 1176) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 1256) - (bidir) - ) - (mapper - (pt 0 1040) - (bidir) - ) - (mapper - (pt 0 1064) - (bidir) - ) - (mapper - (pt 0 1088) - (bidir) - ) - (mapper - (pt 0 1112) - (bidir) - ) - (mapper - (pt 0 1136) - (bidir) - ) - (mapper - (pt 0 432) - (bidir) - ) - (mapper - (pt 0 464) - (bidir) - ) - (mapper - (pt 0 488) - (bidir) - ) - (mapper - (pt 0 520) - (bidir) - ) - (mapper - (pt 0 544) - (bidir) - ) - (mapper - (pt 0 568) - (bidir) - ) - (mapper - (pt 0 592) - (bidir) - ) - (mapper - (pt 408 1424) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) - (mapper - (pt 0 344) - (bidir) - ) - (mapper - (pt 0 1168) - (bidir) - ) - (mapper - (pt 0 1192) - (bidir) - ) - (mapper - (pt 0 368) - (bidir) - ) - (mapper - (pt 0 392) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 1216) - (bidir) - ) - (mapper - (pt 408 48) - (bidir) - ) - (mapper - (pt 408 16) - (bidir) - ) - (mapper - (pt 0 1240) - (bidir) - ) - (mapper - (pt 408 1304) - (bidir) - ) - (mapper - (pt 408 1200) - (bidir) - ) - (mapper - (pt 408 1344) - (bidir) - ) - (mapper - (pt 408 1280) - (bidir) - ) - (mapper - (pt 408 1224) - (bidir) - ) - (mapper - (pt 408 1120) - (bidir) - ) - (mapper - (pt 408 1048) - (bidir) - ) - (mapper - (pt 408 1024) - (bidir) - ) - (mapper - (pt 0 32) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 408 1368) - (bidir) - ) - (mapper - (pt 0 1264) - (bidir) - ) - (mapper - (pt 0 1336) - (bidir) - ) - (mapper - (pt 0 888) - (bidir) - ) -) -(block - (rect 1264 2944 1672 3560) - (text "dsp" (rect 5 5 27 18)(font "Arial" (font_size 8))) (text "i_dsp" (rect 5 602 33 613)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "nFB_OE" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "nRSTO" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nSRCS" (output)) - (block_io "nSRBLE" (output)) - (block_io "nSRBHE" (output)) - (block_io "nSRWE" (output)) - (block_io "nSROE" (output)) - (block_io "DSP_INT" (output)) - (block_io "DSP_TA" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "IO[17..0]" (bidir)) - (block_io "SRD[15..0]" (bidir)) - (mapper - (pt 408 416) - (bidir) - ) - (mapper - (pt 408 392) - (bidir) - ) - (mapper - (pt 408 368) - (bidir) - ) - (mapper - (pt 408 320) - (bidir) - ) - (mapper - (pt 408 440) - (bidir) - ) - (mapper - (pt 408 344) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 40) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 576) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) -) -(connector - (text "FB_AD[31..0]" (rect 1682 776 1748 787)(font "Arial" )) - (pt 1832 792) - (pt 1672 792) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 1072 1220 1083)(font "Arial" )) - (pt 1112 1088) - (pt 1264 1088) - (bus) -) -(connector - (text "MAIN_CLK" (rect 1162 784 1219 795)(font "Arial" )) - (pt 1152 800) - (pt 1264 800) -) -(connector - (text "CLK2M" (rect 1202 808 1240 819)(font "Arial" )) - (pt 1192 824) - (pt 1264 824) -) -(connector - (text "CLK500k" (rect 1202 832 1249 843)(font "Arial" )) - (pt 1192 848) - (pt 1264 848) -) -(connector - (text "LP_DIR" (rect 1682 848 1722 859)(font "Arial" )) - (pt 1672 864) - (pt 1832 864) -) -(connector - (text "LP_STR" (rect 1682 824 1725 835)(font "Arial" )) - (pt 1672 840) - (pt 1832 840) -) -(connector - (text "nACSI_ACK" (rect 1682 928 1745 939)(font "Arial" )) - (pt 1672 944) - (pt 1832 944) -) -(connector - (text "nACSI_RESET" (rect 1682 952 1758 963)(font "Arial" )) - (pt 1672 968) - (pt 1832 968) -) -(connector - (text "nACSI_CS" (rect 1682 976 1737 987)(font "Arial" )) - (pt 1672 992) - (pt 1832 992) -) -(connector - (text "ACSI_DIR" (rect 1682 1000 1733 1011)(font "Arial" )) - (pt 1672 1016) - (pt 1832 1016) -) -(connector - (text "ACSI_A1" (rect 1682 1024 1728 1035)(font "Arial" )) - (pt 1672 1040) - (pt 1832 1040) -) -(connector - (text "nSCSI_ATN" (rect 1682 1128 1742 1139)(font "Arial" )) - (pt 1672 1144) - (pt 1840 1144) -) -(connector - (text "SCSI_DIR" (rect 1682 1152 1733 1163)(font "Arial" )) - (pt 1672 1168) - (pt 1840 1168) -) -(connector - (text "nSCSI_RST" (rect 1682 1176 1743 1187)(font "Arial" )) - (pt 1672 1192) - (pt 1840 1192) -) -(connector - (text "nSCSI_SEL" (rect 1680 1200 1740 1211)(font "Arial" )) - (pt 1672 1216) - (pt 1840 1216) -) -(connector - (text "nSCSI_BUSY" (rect 1682 1224 1752 1235)(font "Arial" )) - (pt 1672 1240) - (pt 1840 1240) -) -(connector - (text "TxD" (rect 1682 1312 1704 1323)(font "Arial" )) - (pt 1672 1328) - (pt 1840 1328) -) -(connector - (text "RTS" (rect 1682 1336 1705 1347)(font "Arial" )) - (pt 1672 1352) - (pt 1840 1352) -) -(connector - (text "DTR" (rect 1680 1360 1704 1371)(font "Arial" )) - (pt 1672 1376) - (pt 1848 1376) -) -(connector - (text "IDE_RES" (rect 1682 1424 1730 1435)(font "Arial" )) - (pt 1672 1440) - (pt 1848 1440) -) -(connector - (text "nIDE_CS0" (rect 1682 1448 1736 1459)(font "Arial" )) - (pt 1672 1464) - (pt 1848 1464) -) -(connector - (text "nIDE_CS1" (rect 1682 1472 1735 1483)(font "Arial" )) - (pt 1672 1488) - (pt 1856 1488) -) -(connector - (text "nIDE_WR" (rect 1682 1496 1732 1507)(font "Arial" )) - (pt 1672 1512) - (pt 1848 1512) -) -(connector - (text "nIDE_RD" (rect 1682 1520 1730 1531)(font "Arial" )) - (pt 1672 1536) - (pt 1848 1536) -) -(connector - (text "nCF_CS0" (rect 1682 1544 1731 1555)(font "Arial" )) - (pt 1672 1560) - (pt 1848 1560) -) -(connector - (text "nCF_CS1" (rect 1682 1568 1730 1579)(font "Arial" )) - (pt 1672 1584) - (pt 1848 1584) -) -(connector - (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) - (pt 1672 1864) - (pt 1856 1864) -) -(connector - (text "nDREQ0" (rect 1682 2152 1728 2163)(font "Arial" )) - (pt 1672 2168) - (pt 1856 2168) -) -(connector - (text "SD_CLK" (rect 1682 2032 1728 2043)(font "Arial" )) - (pt 1856 2048) - (pt 1672 2048) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 2536 1220 2547)(font "Arial" )) - (pt 1112 2552) - (pt 1264 2552) - (bus) -) -(connector - (text "nFB_WR" (rect 1162 2416 1208 2427)(font "Arial" )) - (pt 1152 2432) - (pt 1264 2432) -) -(connector - (text "nFB_CS1" (rect 1154 2440 1202 2451)(font "Arial" )) - (pt 1152 2456) - (pt 1264 2456) -) -(connector - (text "FB_SIZE0" (rect 1154 2488 1205 2499)(font "Arial" )) - (pt 1152 2504) - (pt 1264 2504) -) -(connector - (text "FB_SIZE1" (rect 1154 2512 1204 2523)(font "Arial" )) - (pt 1152 2528) - (pt 1264 2528) -) -(connector - (text "MAIN_CLK" (rect 1162 2368 1219 2379)(font "Arial" )) - (pt 1152 2384) - (pt 1264 2384) -) -(connector - (text "nFB_CS2" (rect 1162 2464 1211 2475)(font "Arial" )) - (pt 1152 2480) - (pt 1264 2480) -) (connector (text "FB_AD[31..0]" (rect 1682 2384 1748 2395)(font "Arial" )) (pt 1832 2400) @@ -4540,84 +4457,66 @@ applicable agreement for further details. (bus) ) (connector - (text "nSCSI_ACK" (rect 1682 1104 1745 1115)(font "Arial" )) - (pt 1672 1120) - (pt 1840 1120) + (text "FB_AD[31..0]" (rect 1682 8 1748 19)(font "Arial" )) + (pt 1832 24) + (pt 1672 24) + (bus) ) (connector - (text "SCSI_PAR" (rect 1682 1080 1738 1091)(font "Arial" )) - (pt 1672 1096) - (pt 1840 1096) + (text "FB_ADR[31..0]" (rect 1146 328 1220 339)(font "Arial" )) + (pt 1112 344) + (pt 1264 344) + (bus) ) (connector - (text "MIDI_OLR" (rect 1762 1256 1816 1267)(font "Arial" )) - (pt 1672 1272) - (pt 1920 1272) + (text "nFB_WR" (rect 1162 184 1208 195)(font "Arial" )) + (pt 1152 200) + (pt 1264 200) ) (connector - (text "MIDI_TLR" (rect 1770 1280 1821 1291)(font "Arial" )) - (pt 1672 1296) - (pt 1920 1296) + (text "nFB_CS1" (rect 1154 208 1202 219)(font "Arial" )) + (pt 1152 224) + (pt 1264 224) ) (connector - (text "nROM3" (rect 1754 1600 1794 1611)(font "Arial" )) - (pt 1672 1616) - (pt 1920 1616) + (text "FB_SIZE0" (rect 1154 256 1205 267)(font "Arial" )) + (pt 1152 272) + (pt 1264 272) ) (connector - (text "nROM4" (rect 1754 1624 1794 1635)(font "Arial" )) - (pt 1672 1640) - (pt 1920 1640) + (text "FB_SIZE1" (rect 1154 280 1204 291)(font "Arial" )) + (pt 1152 296) + (pt 1264 296) ) (connector - (text "nRP_UDS" (rect 1744 1648 1797 1659)(font "Arial" )) - (pt 1672 1664) - (pt 1920 1664) + (text "nFB_CS2" (rect 1162 232 1211 243)(font "Arial" )) + (pt 1152 248) + (pt 1264 248) ) (connector - (text "nRP_LDS" (rect 1746 1672 1796 1683)(font "Arial" )) - (pt 1672 1688) - (pt 1920 1688) + (text "nBLANK" (rect 1682 184 1726 195)(font "Arial" )) + (pt 1672 200) + (pt 1832 200) ) (connector - (text "YM_QA" (rect 1762 1904 1803 1915)(font "Arial" )) - (pt 1672 1920) - (pt 1928 1920) + (text "nSYNC" (rect 1682 208 1720 219)(font "Arial" )) + (pt 1672 224) + (pt 1832 224) ) (connector - (text "YM_QB" (rect 1762 1928 1802 1939)(font "Arial" )) - (pt 1672 1944) - (pt 1928 1944) + (text "nFB_CS3" (rect 1186 352 1235 363)(font "Arial" )) + (pt 1264 368) + (pt 1176 368) ) (connector - (text "YM_QC" (rect 1762 1952 1803 1963)(font "Arial" )) - (pt 1672 1968) - (pt 1928 1968) + (text "nPD_VGA" (rect 1682 256 1736 267)(font "Arial" )) + (pt 1672 272) + (pt 1832 272) ) (connector - (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) - (pt 1264 1856) - (pt 1128 1856) -) -(connector - (text "SD_CD_DATA3" (rect 1682 1984 1762 1995)(font "Arial" )) - (pt 1672 2000) - (pt 1856 2000) -) -(connector - (text "SD_CDM_D1" (rect 1682 2008 1749 2019)(font "Arial" )) - (pt 1672 2024) - (pt 1856 2024) -) -(connector - (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) - (pt 1672 1720) - (pt 1856 1720) -) -(connector - (text "nRSTO" (rect 1170 1120 1208 1131)(font "Arial" )) - (pt 1264 1136) - (pt 1160 1136) + (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) + (pt 1152 2600) + (pt 1264 2600) ) (connector (text "nIRQ[7..2]" (rect 1682 2408 1732 2419)(font "Arial" )) @@ -4626,14 +4525,29 @@ applicable agreement for further details. (bus) ) (connector - (text "CLK2M4576" (rect 1202 856 1264 867)(font "Arial" )) - (pt 1192 872) - (pt 1264 872) + (text "nFB_OE" (rect 1170 160 1213 171)(font "Arial" )) + (pt 1264 176) + (pt 1160 176) ) (connector - (text "nFB_OE" (rect 1170 2392 1213 2403)(font "Arial" )) - (pt 1264 2408) - (pt 1160 2408) + (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) + (pt 1152 2744) + (pt 1264 2744) +) +(connector + (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) + (pt 1152 2720) + (pt 1264 2720) +) +(connector + (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) + (pt 1152 2696) + (pt 1264 2696) +) +(connector + (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) + (pt 1152 2672) + (pt 1264 2672) ) (connector (text "nMFP_INT" (rect 1162 2760 1217 2771)(font "Arial" )) @@ -4641,9 +4555,96 @@ applicable agreement for further details. (pt 1264 2776) ) (connector - (text "nMFP_INT" (rect 1682 2072 1737 2083)(font "Arial" )) - (pt 1672 2088) - (pt 1784 2088) + (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) + (pt 1152 2624) + (pt 1264 2624) +) +(connector + (text "FB_AD[31..0]" (rect 1682 2968 1748 2979)(font "Arial" )) + (pt 1832 2984) + (pt 1672 2984) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 3224 1220 3235)(font "Arial" )) + (pt 1112 3240) + (pt 1264 3240) + (bus) +) +(connector + (text "MAIN_CLK" (rect 1162 3008 1219 3019)(font "Arial" )) + (pt 1152 3024) + (pt 1264 3024) +) +(connector + (text "CLK33M" (rect 1210 2984 1254 2995)(font "Arial" )) + (pt 1200 3000) + (pt 1264 3000) +) +(connector + (text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" )) + (pt 1264 3072) + (pt 1160 3072) +) +(connector + (text "nFB_CS1" (rect 1162 3080 1210 3091)(font "Arial" )) + (pt 1264 3096) + (pt 1160 3096) +) +(connector + (text "nFB_CS2" (rect 1170 3104 1219 3115)(font "Arial" )) + (pt 1264 3120) + (pt 1160 3120) +) +(connector + (text "FB_SIZE0" (rect 1162 3152 1213 3163)(font "Arial" )) + (pt 1264 3168) + (pt 1160 3168) +) +(connector + (text "FB_SIZE1" (rect 1162 3176 1212 3187)(font "Arial" )) + (pt 1264 3192) + (pt 1160 3192) +) +(connector + (text "nFB_BURST" (rect 1162 3200 1226 3211)(font "Arial" )) + (pt 1264 3216) + (pt 1160 3216) +) +(connector + (text "nRSTO" (rect 1170 3248 1208 3259)(font "Arial" )) + (pt 1264 3264) + (pt 1160 3264) +) +(connector + (text "nFB_OE" (rect 1170 3032 1213 3043)(font "Arial" )) + (pt 1264 3048) + (pt 1160 3048) +) +(connector + (text "nSRCS" (rect 1682 3272 1720 3283)(font "Arial" )) + (pt 1824 3288) + (pt 1672 3288) +) +(connector + (text "nSRBLE" (rect 1682 3296 1725 3307)(font "Arial" )) + (pt 1824 3312) + (pt 1672 3312) +) +(connector + (text "nSRBHE" (rect 1682 3320 1728 3331)(font "Arial" )) + (pt 1824 3336) + (pt 1672 3336) +) +(connector + (text "nSRWE" (rect 1682 3344 1723 3355)(font "Arial" )) + (pt 1824 3360) + (pt 1672 3360) +) +(connector + (text "nSROE" (rect 1682 3368 1720 3379)(font "Arial" )) + (pt 1824 3384) + (pt 1672 3384) ) (connector (text "DSP_INT" (rect 1130 2832 1178 2843)(font "Arial" )) @@ -4651,39 +4652,117 @@ applicable agreement for further details. (pt 1120 2848) ) (connector - (text "CLK500k" (rect 482 2040 529 2051)(font "Arial" )) - (pt 472 2056) - (pt 544 2056) + (text "DSP_INT" (rect 1682 3000 1730 3011)(font "Arial" )) + (pt 1816 3016) + (pt 1672 3016) ) (connector - (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) - (pt 1672 1072) - (pt 1936 1072) + (pt 528 2416) + (pt 616 2416) +) +(connector + (text "FB_ALE" (rect 1194 304 1236 315)(font "Arial" )) + (pt 1264 320) + (pt 1184 320) +) +(connector + (text "DDRCLK[3..0]" (rect 1162 136 1232 147)(font "Arial" )) + (pt 1152 152) + (pt 1264 152) (bus) ) (connector - (text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" )) - (pt 1672 896) - (pt 1904 896) + (text "DDR_SYNC_66M" (rect 1178 112 1267 123)(font "Arial" )) + (pt 1168 128) + (pt 1264 128) +) +(connector + (text "VD[31..0]" (rect 1682 288 1728 299)(font "Arial" )) + (pt 1672 304) + (pt 2648 304) (bus) ) (connector - (text "LP_D[7..0]" (rect 1810 800 1863 811)(font "Arial" )) - (pt 1672 816) - (pt 1960 816) + (text "VA[12..0]" (rect 1682 312 1728 323)(font "Arial" )) + (pt 1672 328) + (pt 2528 328) (bus) ) +(connector + (text "nVWE" (rect 1682 336 1715 347)(font "Arial" )) + (pt 1672 352) + (pt 2400 352) +) +(connector + (text "nVCAS" (rect 1690 360 1727 371)(font "Arial" )) + (pt 1672 376) + (pt 2304 376) +) +(connector + (text "nVRAS" (rect 1690 384 1727 395)(font "Arial" )) + (pt 1672 400) + (pt 2208 400) +) +(connector + (text "nVCS" (rect 1690 408 1720 419)(font "Arial" )) + (pt 1672 424) + (pt 2040 424) +) +(connector + (text "VCKE" (rect 1690 432 1721 443)(font "Arial" )) + (pt 1672 448) + (pt 1944 448) +) +(connector + (text "VSYNC" (rect 1682 136 1722 147)(font "Arial" )) + (pt 1672 152) + (pt 1832 152) +) +(connector + (text "HSYNC" (rect 1682 160 1722 171)(font "Arial" )) + (pt 1672 176) + (pt 1832 176) +) +(connector + (text "VB[7..0]" (rect 1754 112 1794 123)(font "Arial" )) + (pt 1672 128) + (pt 1912 128) + (bus) +) +(connector + (text "VG[7..0]" (rect 1842 88 1883 99)(font "Arial" )) + (pt 1672 104) + (pt 2000 104) + (bus) +) +(connector + (text "VR[7..0]" (rect 1922 64 1962 75)(font "Arial" )) + (pt 1672 80) + (pt 2080 80) + (bus) +) +(connector + (text "IO[17..0]" (rect 1962 3224 2004 3235)(font "Arial" )) + (pt 1672 3240) + (pt 2104 3240) + (bus) +) +(connector + (text "SRD[15..0]" (rect 1802 3248 1856 3259)(font "Arial" )) + (pt 1672 3264) + (pt 1944 3264) + (bus) +) +(connector + (text "CLK25M" (rect 1202 608 1246 619)(font "Arial" )) + (pt 1192 624) + (pt 1264 624) +) (connector (text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" )) (pt 440 2136) (pt 344 2136) ) -(connector - (text "TIMEBASE[17..0]" (rect 706 2048 792 2059)(font "Arial" )) - (pt 688 2064) - (pt 808 2064) - (bus) -) (connector (text "HSYNC" (rect 1130 2784 1170 2795)(font "Arial" )) (pt 1264 2800) @@ -4694,16 +4773,6 @@ applicable agreement for further details. (pt 1264 2824) (pt 1120 2824) ) -(connector - (text "VSYNC" (rect 1130 1920 1170 1931)(font "Arial" )) - (pt 1264 1936) - (pt 1120 1936) -) -(connector - (text "HSYNC" (rect 1130 1896 1170 1907)(font "Arial" )) - (pt 1264 1912) - (pt 1120 1912) -) (connector (pt 488 2136) (pt 608 2136) @@ -4719,9 +4788,14 @@ applicable agreement for further details. (pt 1808 2848) ) (connector - (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) - (pt 1672 760) - (pt 1880 760) + (text "DSP_TA" (rect 1682 3504 1728 3515)(font "Arial" )) + (pt 1672 3520) + (pt 1792 3520) +) +(connector + (text "Video_TA" (rect 1682 696 1732 707)(font "Arial" )) + (pt 1672 712) + (pt 1880 712) ) (connector (text "INT_HANDLER_TA" (rect 1810 728 1909 739)(font "Arial" )) @@ -4754,6 +4828,22 @@ applicable agreement for further details. (pt 2504 760) (pt 2536 760) ) +(connector + (text "MAIN_CLK" (rect 1186 88 1243 99)(font "Arial" )) + (pt 1184 104) + (pt 1264 104) +) +(connector + (text "nRSTO" (rect 1194 40 1232 51)(font "Arial" )) + (pt 1184 56) + (pt 1264 56) +) +(connector + (text "BA[1..0]" (rect 1682 456 1722 467)(font "Arial" )) + (pt 1672 472) + (pt 1832 472) + (bus) +) (connector (text "PIXEL_CLK" (rect 2394 -64 2455 -53)(font "Arial" )) (pt 2384 -48) @@ -4791,6 +4881,11 @@ applicable agreement for further details. (pt 2128 -64) (pt 2136 -64) ) +(connector + (text "PIXEL_CLK" (rect 1682 232 1743 243)(font "Arial" )) + (pt 1744 248) + (pt 1672 248) +) (connector (text "PIXEL_CLK" (rect 2394 184 2455 195)(font "Arial" )) (pt 2384 200) @@ -4825,19 +4920,9 @@ applicable agreement for further details. (pt 2440 160) ) (connector - (text "nBLANK" (rect 1154 1968 1198 1979)(font "Arial" )) - (pt 1264 1984) - (pt 1144 1984) -) -(connector - (text "DSP_INT" (rect 1154 1944 1202 1955)(font "Arial" )) - (pt 1264 1960) - (pt 1144 1960) -) -(connector - (text "STEP_DIR" (rect 1682 1752 1737 1763)(font "Arial" )) - (pt 1672 1768) - (pt 1856 1768) + (text "nFB_CS3" (rect 1170 3128 1219 3139)(font "Arial" )) + (pt 1264 3144) + (pt 1160 3144) ) (connector (pt 1904 1768) @@ -4847,67 +4932,23 @@ applicable agreement for further details. (pt 1904 1816) (pt 2136 1816) ) -(connector - (text "WR_DATA" (rect 1682 1800 1738 1811)(font "Arial" )) - (pt 1672 1816) - (pt 1856 1816) -) (connector (text "DMA_DRQ" (rect 1130 2856 1186 2867)(font "Arial" )) (pt 1264 2872) (pt 1120 2872) ) -(connector - (text "DMA_DRQ" (rect 1682 2096 1738 2107)(font "Arial" )) - (pt 1784 2112) - (pt 1672 2112) -) -(connector - (text "FDC_CLK" (rect 1202 880 1255 891)(font "Arial" )) - (pt 1192 896) - (pt 1264 896) -) -(connector - (text "MOT_ON" (rect 1626 1728 1673 1739)(font "Arial" )) - (pt 1672 1744) - (pt 1800 1744) -) (connector (pt 1848 1744) (pt 2136 1744) ) -(connector - (text "STEP" (rect 1626 1776 1656 1787)(font "Arial" )) - (pt 1672 1792) - (pt 1800 1792) -) (connector (pt 1848 1792) (pt 2136 1792) ) -(connector - (text "WR_GATE" (rect 1690 1824 1746 1835)(font "Arial" )) - (pt 1672 1840) - (pt 1800 1840) -) (connector (pt 1848 1840) (pt 2136 1840) ) -(connector - (text "FB_ALE" (rect 1186 1992 1228 2003)(font "Arial" )) - (pt 1144 2008) - (pt 1264 2008) -) -(connector - (text "AMKB_TX" (rect 1946 1392 2000 1403)(font "Arial" )) - (pt 1672 1408) - (pt 2112 1408) -) -(connector - (pt 440 248) - (pt 400 248) -) (connector (text "FB_AD[31..0]" (rect 370 1352 436 1363)(font "Arial" )) (pt 352 1368) @@ -4925,18 +4966,17 @@ applicable agreement for further details. (pt 368 1384) (pt 464 1384) ) +(connector + (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) + (pt 376 1400) + (pt 464 1400) +) (connector (text "ACP_CONF[31..0]" (rect 1682 2568 1772 2579)(font "Arial" )) (pt 1672 2584) (pt 1832 2584) (bus) ) -(connector - (text "ACP_CONF[31..24]" (rect 1146 2064 1242 2075)(font "Arial" )) - (pt 1136 2080) - (pt 1264 2080) - (bus) -) (connector (text "TIN0" (rect 1682 2624 1707 2635)(font "Arial" )) (pt 1832 2640) @@ -4962,6 +5002,31 @@ applicable agreement for further details. (pt 2424 -80) (pt 2424 -64) ) +(connector + (text "DDRCLK[0]" (rect 762 -296 819 -285)(font "Arial" )) + (pt 752 -280) + (pt 848 -280) +) +(connector + (text "DDRCLK[1]" (rect 762 -272 819 -261)(font "Arial" )) + (pt 752 -256) + (pt 848 -256) +) +(connector + (text "DDRCLK[2]" (rect 762 -248 819 -237)(font "Arial" )) + (pt 752 -232) + (pt 848 -232) +) +(connector + (text "DDRCLK[3]" (rect 762 -224 819 -213)(font "Arial" )) + (pt 752 -208) + (pt 848 -208) +) +(connector + (text "DDR_SYNC_66M" (rect 762 -200 851 -189)(font "Arial" )) + (pt 752 -184) + (pt 848 -184) +) (connector (pt 408 672) (pt 472 672) @@ -5092,23 +5157,69 @@ applicable agreement for further details. (pt 64 544) (pt 192 544) ) +(connector + (text "VR_D[8..0]" (rect 1170 464 1224 475)(font "Arial" )) + (pt 1144 480) + (pt 1264 480) + (bus) +) (connector (text "VDQS[3..0]" (rect 1674 504 1730 515)(font "Arial" )) (pt 2040 544) (pt 1960 544) (bus) ) +(connector + (pt 1672 544) + (pt 1888 544) + (bus) +) +(connector + (pt 1888 544) + (pt 1888 568) + (bus) +) (connector (text "VDM[3..0]" (rect 1682 528 1731 539)(font "Arial" )) (pt 1944 568) (pt 1888 568) (bus) ) +(connector + (pt 1672 520) + (pt 1960 520) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 520) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1674 560 1774 571)(font "Arial" )) + (pt 1672 576) + (pt 1792 576) +) +(connector + (text "VR_WR" (rect 1698 592 1739 603)(font "Arial" )) + (pt 1672 608) + (pt 1792 608) +) (connector (text "VR_BUSY" (rect 418 496 472 507)(font "Arial" )) (pt 408 512) (pt 480 512) ) +(connector + (text "VR_BUSY" (rect 1170 448 1224 459)(font "Arial" )) + (pt 1144 464) + (pt 1264 464) +) +(connector + (text "VR_RD" (rect 1698 576 1736 587)(font "Arial" )) + (pt 1792 592) + (pt 1672 592) +) (connector (text "nRSTO" (rect -86 680 -48 691)(font "Arial" )) (pt -96 696) @@ -5125,40 +5236,19 @@ applicable agreement for further details. (bus) ) (connector - (text "CLK500k" (rect 802 232 849 243)(font "Arial" )) - (pt 768 248) - (pt 864 248) + (text "CLK48M" (rect 538 552 582 563)(font "Arial" )) + (pt 528 568) + (pt 608 568) ) (connector - (text "CLK2M4576" (rect 802 256 864 267)(font "Arial" )) - (pt 768 272) - (pt 864 272) + (text "CLK_VIDEO" (rect 1162 552 1225 563)(font "Arial" )) + (pt 984 568) + (pt 1264 568) ) (connector - (text "CLK24M576" (rect 802 280 864 291)(font "Arial" )) - (pt 768 296) - (pt 864 296) -) -(connector - (text "nRSTO" (rect 1018 424 1056 435)(font "Arial" )) - (pt 1008 440) - (pt 1096 440) -) -(connector - (pt 768 320) - (pt 872 320) -) -(connector - (pt 872 432) - (pt 944 432) -) -(connector - (pt 840 448) - (pt 944 448) -) -(connector - (pt 872 320) - (pt 872 432) + (text "CLK33M" (rect 1202 584 1246 595)(font "Arial" )) + (pt 1264 600) + (pt 1192 600) ) (connector (text "HSYNC" (rect 2314 -96 2354 -85)(font "Arial" )) @@ -5175,1022 +5265,731 @@ applicable agreement for further details. (pt 1856 -64) ) (connector - (text "FB_AD[31..0]" (rect 1682 2968 1748 2979)(font "Arial" )) - (pt 1832 2984) - (pt 1672 2984) + (text "DVI_INT" (rect 858 2632 901 2643)(font "Arial" )) + (pt 848 2648) + (pt 1264 2648) +) +(connector + (text "MAIN_CLK" (rect 330 -296 387 -285)(font "Arial" )) + (pt 264 -280) + (pt 400 -280) +) +(connector + (pt 400 -280) + (pt 448 -280) +) +(connector + (text "CLK33MDIR" (rect 234 296 297 307)(font "Arial" )) + (pt 224 312) + (pt 288 312) +) +(connector + (pt 800 160) + (pt 400 160) +) +(connector + (text "CLK33M" (rect 858 144 902 155)(font "Arial" )) + (pt 848 160) + (pt 952 160) +) +(connector + (text "FB_AD[31..0]" (rect 1682 776 1748 787)(font "Arial" )) + (pt 1832 792) + (pt 1672 792) (bus) ) (connector - (text "FB_ADR[31..0]" (rect 1146 3224 1220 3235)(font "Arial" )) - (pt 1112 3240) - (pt 1264 3240) + (text "FB_ADR[31..0]" (rect 1146 1072 1220 1083)(font "Arial" )) + (pt 1112 1088) + (pt 1264 1088) (bus) ) (connector - (text "MAIN_CLK" (rect 1162 3008 1219 3019)(font "Arial" )) - (pt 1152 3024) - (pt 1264 3024) + (text "MAIN_CLK" (rect 1162 784 1219 795)(font "Arial" )) + (pt 1152 800) + (pt 1264 800) ) (connector - (text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" )) - (pt 1264 3072) - (pt 1160 3072) -) -(connector - (text "nFB_CS1" (rect 1162 3080 1210 3091)(font "Arial" )) - (pt 1264 3096) - (pt 1160 3096) -) -(connector - (text "nFB_CS2" (rect 1170 3104 1219 3115)(font "Arial" )) - (pt 1264 3120) - (pt 1160 3120) -) -(connector - (text "FB_SIZE0" (rect 1162 3152 1213 3163)(font "Arial" )) - (pt 1264 3168) - (pt 1160 3168) -) -(connector - (text "FB_SIZE1" (rect 1162 3176 1212 3187)(font "Arial" )) - (pt 1264 3192) - (pt 1160 3192) -) -(connector - (text "nFB_BURST" (rect 1162 3200 1226 3211)(font "Arial" )) - (pt 1264 3216) - (pt 1160 3216) -) -(connector - (text "nRSTO" (rect 1170 3248 1208 3259)(font "Arial" )) - (pt 1264 3264) - (pt 1160 3264) -) -(connector - (text "nFB_OE" (rect 1170 3032 1213 3043)(font "Arial" )) - (pt 1264 3048) - (pt 1160 3048) -) -(connector - (text "IO[17..0]" (rect 1962 3224 2004 3235)(font "Arial" )) - (pt 2104 3240) - (pt 1672 3240) - (bus) -) -(connector - (text "SRD[15..0]" (rect 1802 3248 1856 3259)(font "Arial" )) - (pt 1944 3264) - (pt 1672 3264) - (bus) -) -(connector - (text "nSRCS" (rect 1682 3272 1720 3283)(font "Arial" )) - (pt 1824 3288) - (pt 1672 3288) -) -(connector - (text "nSRBLE" (rect 1682 3296 1725 3307)(font "Arial" )) - (pt 1824 3312) - (pt 1672 3312) -) -(connector - (text "nSRBHE" (rect 1682 3320 1728 3331)(font "Arial" )) - (pt 1824 3336) - (pt 1672 3336) -) -(connector - (text "nSRWE" (rect 1682 3344 1723 3355)(font "Arial" )) - (pt 1824 3360) - (pt 1672 3360) -) -(connector - (text "nSROE" (rect 1682 3368 1720 3379)(font "Arial" )) - (pt 1824 3384) - (pt 1672 3384) -) -(connector - (text "DSP_INT" (rect 1682 3000 1730 3011)(font "Arial" )) - (pt 1816 3016) - (pt 1672 3016) -) -(connector - (text "DSP_TA" (rect 1682 3504 1728 3515)(font "Arial" )) - (pt 1672 3520) - (pt 1792 3520) -) -(connector - (text "nFB_CS3" (rect 1170 3128 1219 3139)(font "Arial" )) - (pt 1264 3144) - (pt 1160 3144) -) -(connector - (text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" )) + (text "CLK33M" (rect 1210 760 1254 771)(font "Arial" )) (pt 1200 776) (pt 1264 776) ) (connector - (text "MAIN_CLK" (rect 1210 2984 1267 2995)(font "Arial" )) - (pt 1200 3000) - (pt 1264 3000) + (text "CLK2M" (rect 1202 808 1240 819)(font "Arial" )) + (pt 1192 824) + (pt 1264 824) ) (connector - (text "DDRCLK[0]" (rect 770 -296 827 -285)(font "Arial" )) - (pt 760 -280) - (pt 856 -280) + (text "CLK500k" (rect 1202 832 1249 843)(font "Arial" )) + (pt 1192 848) + (pt 1264 848) ) (connector - (text "DDRCLK[1]" (rect 770 -272 827 -261)(font "Arial" )) - (pt 760 -256) - (pt 856 -256) + (text "nRSTO" (rect 1170 1120 1208 1131)(font "Arial" )) + (pt 1264 1136) + (pt 1160 1136) ) (connector - (text "DDRCLK[2]" (rect 770 -248 827 -237)(font "Arial" )) - (pt 760 -232) - (pt 856 -232) + (text "CLK2M4576" (rect 1202 856 1264 867)(font "Arial" )) + (pt 1192 872) + (pt 1264 872) ) (connector - (text "DDRCLK[3]" (rect 770 -224 827 -213)(font "Arial" )) - (pt 760 -208) - (pt 856 -208) + (text "nMFP_INT" (rect 1682 2072 1737 2083)(font "Arial" )) + (pt 1672 2088) + (pt 1784 2088) ) (connector - (text "DDR_SYNC_66M" (rect 770 -200 859 -189)(font "Arial" )) - (pt 760 -184) - (pt 856 -184) + (text "VSYNC" (rect 1130 1920 1170 1931)(font "Arial" )) + (pt 1264 1936) + (pt 1120 1936) ) (connector - (text "MAIN_CLK" (rect 338 -296 395 -285)(font "Arial" )) - (pt 272 -280) - (pt 456 -280) + (text "HSYNC" (rect 1130 1896 1170 1907)(font "Arial" )) + (pt 1264 1912) + (pt 1120 1912) ) (connector - (text "FB_AD[31..0]" (rect 1682 16 1748 27)(font "Arial" )) - (pt 1832 32) - (pt 1672 32) + (text "nBLANK" (rect 1154 1968 1198 1979)(font "Arial" )) + (pt 1264 1984) + (pt 1144 1984) +) +(connector + (text "DSP_INT" (rect 1154 1944 1202 1955)(font "Arial" )) + (pt 1264 1960) + (pt 1144 1960) +) +(connector + (text "DMA_DRQ" (rect 1682 2096 1738 2107)(font "Arial" )) + (pt 1784 2112) + (pt 1672 2112) +) +(connector + (text "FDC_CLK" (rect 1202 880 1255 891)(font "Arial" )) + (pt 1192 896) + (pt 1264 896) +) +(connector + (text "FB_ALE" (rect 1186 1992 1228 2003)(font "Arial" )) + (pt 1144 2008) + (pt 1264 2008) +) +(connector + (text "ACP_CONF[31..24]" (rect 1146 2064 1242 2075)(font "Arial" )) + (pt 1136 2080) + (pt 1264 2080) (bus) ) (connector - (text "FB_ADR[31..0]" (rect 1146 336 1220 347)(font "Arial" )) - (pt 1112 352) - (pt 1264 352) - (bus) + (text "LP_STR" (rect 1682 824 1725 835)(font "Arial" )) + (pt 1672 840) + (pt 1832 840) ) (connector - (text "nFB_WR" (rect 1162 192 1208 203)(font "Arial" )) - (pt 1152 208) - (pt 1264 208) + (text "LP_DIR" (rect 1682 848 1722 859)(font "Arial" )) + (pt 1672 864) + (pt 1832 864) ) (connector - (text "nFB_CS1" (rect 1154 216 1202 227)(font "Arial" )) - (pt 1152 232) - (pt 1264 232) -) -(connector - (text "FB_SIZE0" (rect 1154 264 1205 275)(font "Arial" )) - (pt 1152 280) - (pt 1264 280) -) -(connector - (text "FB_SIZE1" (rect 1154 288 1204 299)(font "Arial" )) - (pt 1152 304) - (pt 1264 304) -) -(connector - (text "nFB_CS2" (rect 1162 240 1211 251)(font "Arial" )) - (pt 1152 256) - (pt 1264 256) -) -(connector - (text "nBLANK" (rect 1682 192 1726 203)(font "Arial" )) - (pt 1672 208) - (pt 1832 208) -) -(connector - (pt 1680 80) - (pt 1680 88) - (bus) -) -(connector - (pt 2080 80) - (pt 1680 80) - (bus) -) -(connector - (text "VR[7..0]" (rect 1922 72 1962 83)(font "Arial" )) - (pt 1680 88) - (pt 1672 88) - (bus) -) -(connector - (pt 1688 104) - (pt 1688 112) - (bus) -) -(connector - (pt 2000 104) - (pt 1688 104) - (bus) -) -(connector - (text "VG[7..0]" (rect 1842 96 1883 107)(font "Arial" )) - (pt 1688 112) - (pt 1672 112) - (bus) -) -(connector - (pt 1696 128) - (pt 1696 136) - (bus) -) -(connector - (pt 1912 128) - (pt 1696 128) - (bus) -) -(connector - (text "VB[7..0]" (rect 1754 120 1794 131)(font "Arial" )) - (pt 1696 136) - (pt 1672 136) - (bus) -) -(connector - (pt 1704 224) - (pt 1704 232) -) -(connector - (pt 1832 224) - (pt 1704 224) -) -(connector - (text "nSYNC" (rect 1682 216 1720 227)(font "Arial" )) - (pt 1704 232) - (pt 1672 232) -) -(connector - (pt 1712 272) - (pt 1712 280) -) -(connector - (pt 1832 272) - (pt 1712 272) -) -(connector - (text "nPD_VGA" (rect 1682 264 1736 275)(font "Arial" )) - (pt 1712 280) - (pt 1672 280) -) -(connector - (pt 1720 328) - (pt 1720 336) - (bus) -) -(connector - (pt 2528 328) - (pt 1720 328) - (bus) -) -(connector - (text "VA[12..0]" (rect 1682 320 1728 331)(font "Arial" )) - (pt 1720 336) - (pt 1672 336) - (bus) -) -(connector - (pt 1728 352) - (pt 1728 360) -) -(connector - (pt 2400 352) - (pt 1728 352) -) -(connector - (text "nVWE" (rect 1682 344 1715 355)(font "Arial" )) - (pt 1728 360) - (pt 1672 360) -) -(connector - (pt 1256 368) - (pt 1256 376) -) -(connector - (text "nFB_CS3" (rect 1186 360 1235 371)(font "Arial" )) - (pt 1256 376) - (pt 1264 376) -) -(connector - (text "nFB_OE" (rect 1170 168 1213 179)(font "Arial" )) - (pt 1264 184) - (pt 1160 184) -) -(connector - (text "FB_ALE" (rect 1194 312 1236 323)(font "Arial" )) - (pt 1264 328) - (pt 1184 328) -) -(connector - (text "DDRCLK[3..0]" (rect 1162 144 1232 155)(font "Arial" )) - (pt 1152 160) - (pt 1264 160) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 1178 120 1267 131)(font "Arial" )) - (pt 1168 136) - (pt 1264 136) -) -(connector - (pt 1736 304) - (pt 1736 312) - (bus) -) -(connector - (pt 2648 304) - (pt 1736 304) - (bus) -) -(connector - (text "VD[31..0]" (rect 1682 296 1728 307)(font "Arial" )) - (pt 1736 312) - (pt 1672 312) - (bus) -) -(connector - (pt 1744 376) - (pt 1744 384) -) -(connector - (pt 2304 376) - (pt 1744 376) -) -(connector - (text "nVCAS" (rect 1690 368 1727 379)(font "Arial" )) - (pt 1744 384) - (pt 1672 384) -) -(connector - (pt 1752 400) - (pt 1752 408) -) -(connector - (pt 2208 400) - (pt 1752 400) -) -(connector - (text "nVRAS" (rect 1690 392 1727 403)(font "Arial" )) - (pt 1752 408) - (pt 1672 408) -) -(connector - (pt 1760 424) - (pt 1760 432) -) -(connector - (pt 2040 424) - (pt 1760 424) -) -(connector - (text "nVCS" (rect 1690 416 1720 427)(font "Arial" )) - (pt 1760 432) - (pt 1672 432) -) -(connector - (pt 1768 448) - (pt 1768 456) -) -(connector - (pt 1944 448) - (pt 1768 448) -) -(connector - (text "VCKE" (rect 1690 440 1721 451)(font "Arial" )) - (pt 1768 456) - (pt 1672 456) -) -(connector - (text "VSYNC" (rect 1682 144 1722 155)(font "Arial" )) - (pt 1672 160) - (pt 1832 160) -) -(connector - (text "HSYNC" (rect 1682 168 1722 179)(font "Arial" )) - (pt 1672 184) - (pt 1832 184) -) -(connector - (pt 1776 712) - (pt 1776 720) -) -(connector - (pt 1880 712) - (pt 1776 712) -) -(connector - (text "Video_TA" (rect 1682 704 1732 715)(font "Arial" )) - (pt 1776 720) - (pt 1672 720) -) -(connector - (text "MAIN_CLK" (rect 1186 96 1243 107)(font "Arial" )) - (pt 1184 112) - (pt 1264 112) -) -(connector - (text "nRSTO" (rect 1194 48 1232 59)(font "Arial" )) - (pt 1184 64) - (pt 1264 64) -) -(connector - (pt 1784 472) - (pt 1784 480) - (bus) -) -(connector - (pt 1832 472) - (pt 1784 472) - (bus) -) -(connector - (text "BA[1..0]" (rect 1682 464 1722 475)(font "Arial" )) - (pt 1784 480) - (pt 1672 480) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 1682 240 1743 251)(font "Arial" )) - (pt 1744 256) - (pt 1672 256) -) -(connector - (text "VR_D[8..0]" (rect 1170 472 1224 483)(font "Arial" )) - (pt 1144 488) - (pt 1264 488) - (bus) -) -(connector - (pt 1888 552) - (pt 1672 552) - (bus) -) -(connector - (pt 1888 568) - (pt 1888 552) - (bus) -) -(connector - (pt 1960 528) - (pt 1672 528) - (bus) -) -(connector - (pt 1960 544) - (pt 1960 528) - (bus) -) -(connector - (text "VIDEO_RECONFIG" (rect 1674 568 1774 579)(font "Arial" )) - (pt 1672 584) - (pt 1792 584) -) -(connector - (text "VR_WR" (rect 1698 600 1739 611)(font "Arial" )) - (pt 1672 616) - (pt 1792 616) -) -(connector - (text "VR_BUSY" (rect 1170 456 1224 467)(font "Arial" )) - (pt 1144 472) - (pt 1264 472) -) -(connector - (text "VR_RD" (rect 1698 584 1736 595)(font "Arial" )) - (pt 1792 600) - (pt 1672 600) -) -(connector - (pt 1248 568) - (pt 1248 576) -) -(connector - (pt 984 568) - (pt 1248 568) -) -(connector - (text "CLK_VIDEO" (rect 1162 560 1225 571)(font "Arial" )) - (pt 1248 576) - (pt 1264 576) -) -(connector - (text "MAIN_CLK" (rect 1202 592 1259 603)(font "Arial" )) - (pt 1264 608) - (pt 1192 608) -) -(connector - (pt 1264 1264) - (pt 1112 1264) -) -(connector - (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) - (pt 1112 1264) - (pt 1104 1264) -) -(connector - (pt 1104 1336) - (pt 1112 1336) -) -(connector - (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) - (pt 1112 1336) - (pt 1264 1336) -) -(connector - (pt 1104 1424) - (pt 1112 1424) -) -(connector - (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) - (pt 1112 1424) - (pt 1264 1424) -) -(connector - (pt 1104 1448) - (pt 1112 1448) -) -(connector - (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) - (pt 1112 1448) - (pt 1264 1448) -) -(connector - (pt 1104 1472) - (pt 1112 1472) -) -(connector - (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) - (pt 1112 1472) - (pt 1264 1472) -) -(connector - (pt 1264 1552) - (pt 1112 1552) -) -(connector - (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) - (pt 1112 1552) - (pt 1104 1552) -) -(connector - (pt 1104 1576) - (pt 1112 1576) -) -(connector - (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) - (pt 1112 1576) - (pt 1264 1576) -) -(connector - (pt 1104 1600) - (pt 1112 1600) -) -(connector - (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) - (pt 1112 1600) - (pt 1264 1600) -) -(connector - (pt 1104 1784) - (pt 1112 1784) -) -(connector - (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) - (pt 1112 1784) - (pt 1264 1784) -) -(connector - (pt 1104 1808) - (pt 1112 1808) -) -(connector - (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) - (pt 1112 1808) - (pt 1264 1808) -) -(connector - (pt 1104 1832) - (pt 1112 1832) -) -(connector - (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) - (pt 1112 1832) - (pt 1264 1832) -) -(connector - (pt 1104 1880) - (pt 1112 1880) -) -(connector - (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) - (pt 1112 1880) - (pt 1264 1880) -) -(connector - (pt 1264 1176) - (pt 1112 1176) -) -(connector - (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) - (pt 1112 1176) - (pt 1104 1176) -) -(connector - (pt 1024 1208) - (pt 1032 1208) -) -(connector - (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) - (pt 1032 1208) - (pt 1264 1208) -) -(connector - (pt 1024 1232) - (pt 1032 1232) -) -(connector - (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) - (pt 1032 1232) - (pt 1264 1232) -) -(connector - (pt 1040 1368) - (pt 1048 1368) -) -(connector - (text "MIDI_IN" (rect 1050 1352 1091 1363)(font "Arial" )) - (pt 1048 1368) - (pt 1264 1368) -) -(connector - (pt 1264 1400) - (pt 1112 1400) -) -(connector - (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) - (pt 1112 1400) - (pt 1104 1400) -) -(connector - (pt 1040 1656) - (pt 1048 1656) -) -(connector - (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) - (pt 1048 1656) - (pt 1264 1656) -) -(connector - (pt 1040 1680) - (pt 1048 1680) -) -(connector - (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) - (pt 1048 1680) - (pt 1264 1680) -) -(connector - (pt 1040 1704) - (pt 1048 1704) -) -(connector - (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) - (pt 1048 1704) - (pt 1264 1704) -) -(connector - (pt 1040 1728) - (pt 1048 1728) -) -(connector - (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) - (pt 1048 1728) - (pt 1264 1728) -) -(connector - (pt 1040 1752) - (pt 1048 1752) -) -(connector - (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) - (pt 1048 1752) - (pt 1264 1752) -) -(connector - (pt 1104 1288) - (pt 1112 1288) -) -(connector - (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) - (pt 1112 1288) - (pt 1264 1288) -) -(connector - (pt 1104 1312) - (pt 1112 1312) -) -(connector - (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) - (pt 1112 1312) - (pt 1264 1312) -) -(connector - (pt 1264 944) - (pt 1168 944) + (text "nACSI_ACK" (rect 1682 928 1745 939)(font "Arial" )) + (pt 1672 944) + (pt 1832 944) ) (connector (text "nFB_WR" (rect 1170 928 1216 939)(font "Arial" )) - (pt 1168 944) (pt 1160 944) + (pt 1264 944) ) (connector - (pt 1264 968) - (pt 1168 968) + (text "nACSI_RESET" (rect 1682 952 1758 963)(font "Arial" )) + (pt 1672 968) + (pt 1832 968) ) (connector (text "nFB_CS1" (rect 1162 952 1210 963)(font "Arial" )) - (pt 1168 968) (pt 1160 968) + (pt 1264 968) ) (connector - (pt 1264 992) - (pt 1168 992) + (text "nACSI_CS" (rect 1682 976 1737 987)(font "Arial" )) + (pt 1672 992) + (pt 1832 992) ) (connector (text "nFB_CS2" (rect 1170 976 1219 987)(font "Arial" )) - (pt 1168 992) (pt 1160 992) + (pt 1264 992) ) (connector - (pt 1264 1016) - (pt 1168 1016) + (text "ACSI_DIR" (rect 1682 1000 1733 1011)(font "Arial" )) + (pt 1672 1016) + (pt 1832 1016) ) (connector (text "FB_SIZE0" (rect 1162 1000 1213 1011)(font "Arial" )) - (pt 1168 1016) (pt 1160 1016) + (pt 1264 1016) ) (connector - (pt 1264 1040) - (pt 1168 1040) + (text "ACSI_A1" (rect 1682 1024 1728 1035)(font "Arial" )) + (pt 1672 1040) + (pt 1832 1040) ) (connector (text "FB_SIZE1" (rect 1162 1024 1212 1035)(font "Arial" )) - (pt 1168 1040) (pt 1160 1040) -) -(connector - (pt 1264 1064) - (pt 1168 1064) + (pt 1264 1040) ) (connector (text "nFB_BURST" (rect 1162 1048 1226 1059)(font "Arial" )) - (pt 1168 1064) (pt 1160 1064) + (pt 1264 1064) ) (connector - (pt 1264 1112) - (pt 1168 1112) + (text "SCSI_PAR" (rect 1682 1080 1738 1091)(font "Arial" )) + (pt 1672 1096) + (pt 1840 1096) ) (connector - (text "nDACK0" (rect 1250 1096 1294 1107)(font "Arial" )) - (pt 1168 1112) + (text "nDACK0" (rect 1202 1096 1246 1107)(font "Arial" )) (pt 1160 1112) + (pt 1264 1112) ) (connector - (pt 1152 2600) - (pt 1160 2600) + (text "nSCSI_ACK" (rect 1682 1104 1745 1115)(font "Arial" )) + (pt 1672 1120) + (pt 1840 1120) ) (connector - (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) - (pt 1160 2600) - (pt 1264 2600) + (text "nSCSI_ATN" (rect 1682 1128 1742 1139)(font "Arial" )) + (pt 1672 1144) + (pt 1840 1144) ) (connector - (pt 1264 920) - (pt 1168 920) + (text "SCSI_DIR" (rect 1682 1152 1733 1163)(font "Arial" )) + (pt 1672 1168) + (pt 1840 1168) ) (connector - (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) - (pt 1168 920) - (pt 1160 920) + (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) + (pt 1104 1176) + (pt 1264 1176) ) (connector - (pt 1152 2648) - (pt 1160 2648) + (text "nSCSI_RST" (rect 1682 1176 1743 1187)(font "Arial" )) + (pt 1672 1192) + (pt 1840 1192) ) (connector - (text "DVI_INT" (rect 1162 2632 1205 2643)(font "Arial" )) - (pt 1160 2648) - (pt 1264 2648) + (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) + (pt 1024 1208) + (pt 1264 1208) ) (connector - (pt 1152 2744) - (pt 1160 2744) + (text "nSCSI_SEL" (rect 1680 1200 1740 1211)(font "Arial" )) + (pt 1672 1216) + (pt 1840 1216) ) (connector - (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) - (pt 1160 2744) - (pt 1264 2744) + (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) + (pt 1024 1232) + (pt 1264 1232) ) (connector - (pt 1152 2720) - (pt 1160 2720) + (text "nSCSI_BUSY" (rect 1682 1224 1752 1235)(font "Arial" )) + (pt 1672 1240) + (pt 1840 1240) ) (connector - (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) - (pt 1160 2720) - (pt 1264 2720) + (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) + (pt 1104 1264) + (pt 1264 1264) ) (connector - (pt 1152 2696) - (pt 1160 2696) + (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) + (pt 1104 1288) + (pt 1264 1288) ) (connector - (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) - (pt 1160 2696) - (pt 1264 2696) + (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) + (pt 1104 1312) + (pt 1264 1312) ) (connector - (pt 1152 2672) - (pt 1160 2672) + (text "TxD" (rect 1682 1312 1704 1323)(font "Arial" )) + (pt 1672 1328) + (pt 1840 1328) ) (connector - (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) - (pt 1160 2672) - (pt 1264 2672) + (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) + (pt 1104 1336) + (pt 1264 1336) ) (connector - (pt 1152 2624) - (pt 1160 2624) + (text "RTS" (rect 1682 1336 1705 1347)(font "Arial" )) + (pt 1672 1352) + (pt 1840 1352) ) (connector - (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) - (pt 1160 2624) - (pt 1264 2624) + (text "DTR" (rect 1680 1360 1704 1371)(font "Arial" )) + (pt 1672 1376) + (pt 1848 1376) ) (connector - (pt 528 2416) - (pt 536 2416) + (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) + (pt 1104 1400) + (pt 1264 1400) ) (connector - (pt 536 2416) - (pt 616 2416) + (text "AMKB_TX" (rect 1946 1392 2000 1403)(font "Arial" )) + (pt 1672 1408) + (pt 2112 1408) ) (connector - (pt 776 1496) - (pt 784 1496) + (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) + (pt 1104 1424) + (pt 1264 1424) ) (connector - (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) - (pt 784 1496) - (pt 1264 1496) + (text "IDE_RES" (rect 1682 1424 1730 1435)(font "Arial" )) + (pt 1672 1440) + (pt 1848 1440) ) (connector - (pt 776 1520) - (pt 784 1520) + (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) + (pt 1104 1448) + (pt 1264 1448) +) +(connector + (text "nIDE_CS0" (rect 1682 1448 1736 1459)(font "Arial" )) + (pt 1672 1464) + (pt 1848 1464) +) +(connector + (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) + (pt 1104 1472) + (pt 1264 1472) +) +(connector + (text "nIDE_CS1" (rect 1682 1472 1735 1483)(font "Arial" )) + (pt 1672 1488) + (pt 1856 1488) +) +(connector + (text "nIDE_WR" (rect 1682 1496 1732 1507)(font "Arial" )) + (pt 1672 1512) + (pt 1848 1512) ) (connector (text "PIC_AMKB_RX" (rect 786 1504 866 1515)(font "Arial" )) - (pt 784 1520) + (pt 776 1520) (pt 1264 1520) ) (connector - (pt 376 1400) - (pt 384 1400) + (text "nIDE_RD" (rect 1682 1520 1730 1531)(font "Arial" )) + (pt 1672 1536) + (pt 1848 1536) ) (connector - (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) - (pt 384 1400) - (pt 464 1400) + (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) + (pt 1104 1552) + (pt 1264 1552) ) (connector - (pt 1040 1632) - (pt 1048 1632) + (text "nCF_CS0" (rect 1682 1544 1731 1555)(font "Arial" )) + (pt 1672 1560) + (pt 1848 1560) +) +(connector + (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) + (pt 1104 1576) + (pt 1264 1576) +) +(connector + (text "nCF_CS1" (rect 1682 1568 1730 1579)(font "Arial" )) + (pt 1672 1584) + (pt 1848 1584) +) +(connector + (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) + (pt 1104 1600) + (pt 1264 1600) +) +(connector + (text "nROM3" (rect 1754 1600 1794 1611)(font "Arial" )) + (pt 1672 1616) + (pt 1920 1616) +) +(connector + (text "nROM4" (rect 1754 1624 1794 1635)(font "Arial" )) + (pt 1672 1640) + (pt 1920 1640) +) +(connector + (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) + (pt 1040 1656) + (pt 1264 1656) +) +(connector + (text "nRP_UDS" (rect 1744 1648 1797 1659)(font "Arial" )) + (pt 1672 1664) + (pt 1920 1664) +) +(connector + (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) + (pt 1040 1680) + (pt 1264 1680) +) +(connector + (text "nRP_LDS" (rect 1746 1672 1796 1683)(font "Arial" )) + (pt 1672 1688) + (pt 1920 1688) +) +(connector + (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) + (pt 1040 1704) + (pt 1264 1704) +) +(connector + (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) + (pt 1672 1720) + (pt 1856 1720) +) +(connector + (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) + (pt 1040 1728) + (pt 1264 1728) +) +(connector + (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) + (pt 1040 1752) + (pt 1264 1752) +) +(connector + (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) + (pt 1104 1784) + (pt 1264 1784) +) +(connector + (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) + (pt 1104 1808) + (pt 1264 1808) +) +(connector + (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) + (pt 1104 1832) + (pt 1264 1832) +) +(connector + (text "WR_GATE" (rect 1690 1824 1746 1835)(font "Arial" )) + (pt 1672 1840) + (pt 1800 1840) +) +(connector + (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) + (pt 1128 1856) + (pt 1264 1856) +) +(connector + (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) + (pt 1672 1864) + (pt 1856 1864) +) +(connector + (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) + (pt 1104 1880) + (pt 1264 1880) +) +(connector + (text "YM_QA" (rect 1762 1904 1803 1915)(font "Arial" )) + (pt 1672 1920) + (pt 1928 1920) +) +(connector + (text "YM_QB" (rect 1762 1928 1802 1939)(font "Arial" )) + (pt 1672 1944) + (pt 1928 1944) +) +(connector + (text "YM_QC" (rect 1762 1952 1803 1963)(font "Arial" )) + (pt 1672 1968) + (pt 1928 1968) +) +(connector + (text "SD_CD_DATA3" (rect 1682 1984 1762 1995)(font "Arial" )) + (pt 1672 2000) + (pt 1856 2000) +) +(connector + (text "SD_CDM_D1" (rect 1682 2008 1749 2019)(font "Arial" )) + (pt 1672 2024) + (pt 1856 2024) +) +(connector + (text "SD_CLK" (rect 1682 2032 1728 2043)(font "Arial" )) + (pt 1672 2048) + (pt 1856 2048) +) +(connector + (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) + (pt 1160 920) + (pt 1264 920) +) +(connector + (text "LP_D[7..0]" (rect 1810 800 1863 811)(font "Arial" )) + (pt 1672 816) + (pt 1960 816) + (bus) +) +(connector + (text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" )) + (pt 1672 896) + (pt 1904 896) + (bus) +) +(connector + (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) + (pt 1672 1072) + (pt 1936 1072) + (bus) +) +(connector + (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) + (pt 776 1496) + (pt 1264 1496) +) +(connector + (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) + (pt 1672 760) + (pt 1880 760) +) +(connector + (text "STEP_DIR" (rect 1682 1752 1737 1763)(font "Arial" )) + (pt 1672 1768) + (pt 1856 1768) +) +(connector + (text "WR_DATA" (rect 1682 1800 1738 1811)(font "Arial" )) + (pt 1672 1816) + (pt 1856 1816) +) +(connector + (text "MOT_ON" (rect 1626 1728 1673 1739)(font "Arial" )) + (pt 1672 1744) + (pt 1800 1744) +) +(connector + (text "STEP" (rect 1626 1776 1656 1787)(font "Arial" )) + (pt 1672 1792) + (pt 1800 1792) ) (connector (text "HD_DD" (rect 1050 1616 1090 1627)(font "Arial" )) - (pt 1048 1632) + (pt 1040 1632) (pt 1264 1632) ) (connector - (pt 336 304) - (pt 344 304) + (pt 400 248) + (pt 440 248) ) (connector - (text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" )) - (pt 344 304) - (pt 400 304) -) -(connector - (pt 1176 368) - (pt 1184 368) -) -(connector - (pt 1184 368) - (pt 1256 368) -) -(connector - (text "CLK2M" (rect 906 -40 944 -29)(font "Arial" )) - (pt 704 -24) - (pt 944 -24) -) -(connector - (text "FDC_CLK" (rect 954 -24 1007 -13)(font "Arial" )) - (pt 704 -8) - (pt 944 -8) -) -(connector - (pt 832 56) - (pt 832 24) -) -(connector - (pt 840 56) - (pt 832 56) -) -(connector - (pt 832 24) - (pt 704 24) -) -(connector - (pt 400 -24) + (pt 400 160) (pt 400 248) ) (connector - (pt 400 248) - (pt 400 304) + (text "nRSTO" (rect 1026 424 1064 435)(font "Arial" )) + (pt 1016 440) + (pt 1104 440) ) (connector - (pt 448 -24) - (pt 400 -24) + (pt 920 432) + (pt 952 432) ) (connector - (text "CLK25M" (rect 1210 616 1254 627)(font "Arial" )) - (pt 1264 632) - (pt 1200 632) + (pt 760 448) + (pt 952 448) ) (connector - (pt 776 8) - (pt 704 8) + (pt 824 440) + (pt 952 440) ) (connector - (text "CLKUSB" (rect 538 552 584 563)(font "Arial" )) - (pt 528 568) - (pt 608 568) + (pt 1120 328) + (pt 920 328) +) +(connector + (pt 920 328) + (pt 920 432) +) +(connector + (pt 1888 2192) + (pt 1888 2176) +) +(connector + (pt 1848 2176) + (pt 1888 2176) +) +(connector + (pt 1848 2176) + (pt 1848 2208) +) +(connector + (pt 1848 2208) + (pt 1864 2208) +) +(connector + (text "CLK2M" (rect 1778 2192 1816 2203)(font "Arial" )) + (pt 1768 2208) + (pt 1848 2208) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 2552 1220 2563)(font "Arial" )) + (pt 1112 2568) + (pt 1264 2568) + (bus) +) +(connector + (text "nFB_WR" (rect 1162 2432 1208 2443)(font "Arial" )) + (pt 1152 2448) + (pt 1264 2448) +) +(connector + (text "nFB_CS1" (rect 1154 2456 1202 2467)(font "Arial" )) + (pt 1152 2472) + (pt 1264 2472) +) +(connector + (text "FB_SIZE0" (rect 1154 2504 1205 2515)(font "Arial" )) + (pt 1152 2520) + (pt 1264 2520) +) +(connector + (text "FB_SIZE1" (rect 1154 2528 1204 2539)(font "Arial" )) + (pt 1152 2544) + (pt 1264 2544) +) +(connector + (text "MAIN_CLK" (rect 1162 2384 1219 2395)(font "Arial" )) + (pt 1152 2400) + (pt 1264 2400) +) +(connector + (text "nFB_CS2" (rect 1162 2480 1211 2491)(font "Arial" )) + (pt 1152 2496) + (pt 1264 2496) +) +(connector + (text "nFB_OE" (rect 1170 2408 1213 2419)(font "Arial" )) + (pt 1264 2424) + (pt 1160 2424) +) +(connector + (text "nRSTO" (rect 1170 2360 1208 2371)(font "Arial" )) + (pt 1264 2376) + (pt 1160 2376) +) +(connector + (pt 1912 2208) + (pt 1960 2208) +) +(connector + (text "MIDI_IN" (rect 1682 2208 1723 2219)(font "Arial" )) + (pt 1672 2224) + (pt 1864 2224) +) +(connector + (text "nDREQ0" (rect 1674 2120 1720 2131)(font "Arial" )) + (pt 1672 2136) + (pt 1800 2136) +) +(connector + (text "MIDI_OLR" (rect 1682 2272 1736 2283)(font "Arial" )) + (pt 1672 2288) + (pt 1920 2288) +) +(connector + (text "MIDI_TLR" (rect 1682 2232 1733 2243)(font "Arial" )) + (pt 1672 2248) + (pt 1832 2248) +) +(connector + (pt 824 440) + (pt 824 296) +) +(connector + (pt 824 296) + (pt 712 296) +) +(connector + (pt 1120 328) + (pt 1120 48) +) +(connector + (pt 400 -16) + (pt 464 -16) +) +(connector + (pt 400 -280) + (pt 400 -16) +) +(connector + (pt 400 -16) + (pt 400 160) +) +(connector + (pt 736 48) + (pt 1120 48) +) +(connector + (text "CLK25M" (rect 802 -32 846 -21)(font "Arial" )) + (pt 736 -16) + (pt 920 -16) +) +(connector + (text "CLK2M" (rect 810 -8 848 3)(font "Arial" )) + (pt 736 0) + (pt 808 0) +) +(connector + (text "CLK500k" (rect 834 8 881 19)(font "Arial" )) + (pt 736 16) + (pt 832 16) +) +(connector + (text "CLK2M4576" (rect 810 24 872 35)(font "Arial" )) + (pt 736 32) + (pt 808 32) +) +(connector + (text "CLK48M" (rect 722 232 766 243)(font "Arial" )) + (pt 712 248) + (pt 808 248) +) +(connector + (text "FDC_CLK" (rect 786 256 839 267)(font "Arial" )) + (pt 712 264) + (pt 784 264) +) +(connector + (text "CLK24M576" (rect 722 272 784 283)(font "Arial" )) + (pt 816 280) + (pt 712 280) +) +(connector + (text "TIMEBASE[17..0]" (rect 706 2056 792 2067)(font "Arial" )) + (pt 688 2072) + (pt 808 2072) + (bus) +) +(connector + (text "CLK500k" (rect 482 2048 529 2059)(font "Arial" )) + (pt 472 2064) + (pt 544 2064) ) (junction (pt 2504 760)) -(junction (pt 400 248)) (junction (pt 1856 -64)) (junction (pt 2424 -80)) -(junction (pt 1112 1264)) -(junction (pt 1112 1336)) -(junction (pt 1112 1424)) -(junction (pt 1112 1448)) -(junction (pt 1112 1472)) -(junction (pt 1112 1552)) -(junction (pt 1112 1576)) -(junction (pt 1112 1600)) -(junction (pt 1112 1784)) -(junction (pt 1112 1808)) -(junction (pt 1112 1832)) -(junction (pt 1112 1880)) -(junction (pt 1112 1176)) -(junction (pt 1032 1208)) -(junction (pt 1032 1232)) -(junction (pt 1048 1368)) -(junction (pt 1112 1400)) -(junction (pt 1048 1656)) -(junction (pt 1048 1680)) -(junction (pt 1048 1704)) -(junction (pt 1048 1728)) -(junction (pt 1048 1752)) -(junction (pt 1112 1288)) -(junction (pt 1112 1312)) -(junction (pt 1168 944)) -(junction (pt 1168 968)) -(junction (pt 1168 992)) -(junction (pt 1168 1016)) -(junction (pt 1168 1040)) -(junction (pt 1168 1064)) -(junction (pt 1168 1112)) -(junction (pt 1160 2600)) -(junction (pt 1168 920)) -(junction (pt 1160 2648)) -(junction (pt 1160 2744)) -(junction (pt 1160 2720)) -(junction (pt 1160 2696)) -(junction (pt 1160 2672)) -(junction (pt 1160 2624)) -(junction (pt 536 2416)) -(junction (pt 784 1496)) -(junction (pt 784 1520)) -(junction (pt 384 1400)) -(junction (pt 1048 1632)) -(junction (pt 344 304)) -(junction (pt 1184 368)) +(junction (pt 400 -280)) +(junction (pt 400 160)) +(junction (pt 1848 2208)) +(junction (pt 400 -16)) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index f167edb..6be8aa6 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -42,10 +42,10 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== -set_location_assignment PIN_AB12 -to CLK33M set_location_assignment PIN_G2 -to MAIN_CLK set_location_assignment PIN_Y3 -to FB_AD[0] set_location_assignment PIN_Y6 -to FB_AD[1] @@ -319,7 +319,6 @@ set_location_assignment PIN_A20 -to nRD_DATA set_location_assignment PIN_C17 -to nDCHG set_location_assignment PIN_J4 -to nACSI_INT set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_E12 -to MIDI_IN set_location_assignment PIN_G7 -to LP_BUSY set_location_assignment PIN_Y1 -to IDE_RDY set_location_assignment PIN_G22 -to IDE_INT @@ -353,7 +352,7 @@ set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name TOP_LEVEL_ENTITY firebee1 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED @@ -368,14 +367,14 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to VA set_instance_assignment -name IO_STANDARD "2.5 V" -to VD @@ -495,7 +494,7 @@ set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA @@ -513,15 +512,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M @@ -546,8 +544,6 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # LogicLock Region Assignments # ============================ -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # end LOGICLOCK_REGION(Root Region) # --------------------------------- @@ -557,76 +553,135 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(firebee1) # -------------------- +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name DISABLE_OCP_HW_EVAL ON -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON - -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5 -set_global_assignment -name ECO_OPTIMIZE_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name BDF_FILE firebee1.bdf set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE DSP/DSP.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp @@ -637,12 +692,21 @@ set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip set_global_assignment -name QIP_FILE Video/altdpram0.qip set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip @@ -656,22 +720,6 @@ set_global_assignment -name QIP_FILE Video/lpm_mux1.qip set_global_assignment -name QIP_FILE Video/lpm_mux2.qip set_global_assignment -name QIP_FILE Video/lpm_constant2.qip set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip set_global_assignment -name QIP_FILE Video/altddio_out0.qip @@ -681,23 +729,46 @@ set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip set_global_assignment -name QIP_FILE Video/altddio_out1.qip set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd @@ -725,37 +796,35 @@ set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf214 set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip set_global_assignment -name VHDL_FILE lpm_latch0.vhd set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name VHDL_FILE altpll3.vhd set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip set_global_assignment -name QIP_FILE lpm_counter0.qip set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index a28e73e..2260426 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -118,14 +118,14 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_outputs] #************************************************************** @@ -149,17 +149,22 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl # MAIN_CLK to DDR clk and v.v. set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] + set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] - +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] # 2 MHz to 33 MHz set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}] # 16 MHz to 33 MHz set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] @@ -168,6 +173,9 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|al # 25 MHz to 33 MHz set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] + set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] @@ -178,6 +186,7 @@ set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_genera set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] diff --git a/FPGA_Quartus_13.1/lpm_counter1.qip b/FPGA_Quartus_13.1/lpm_counter1.qip new file mode 100644 index 0000000..2bcc1a0 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_mux0.qip b/FPGA_Quartus_13.1/lpm_mux0.qip new file mode 100644 index 0000000..b46f6a0 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_mux0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_shiftreg0.qip b/FPGA_Quartus_13.1/lpm_shiftreg0.qip new file mode 100644 index 0000000..7fd6c84 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_shiftreg0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"] From 5c933580a2c2a2c2a10252b9714fc88b501a3ab8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 18 Nov 2015 06:41:49 +0000 Subject: [PATCH 035/127] fix ACP web address --- FPGA_Quartus_13.1/altpll1.bsf | 114 +++---- FPGA_Quartus_13.1/altpll1.cmp | 2 +- FPGA_Quartus_13.1/altpll1.inc | 2 +- FPGA_Quartus_13.1/altpll1.qip | 2 +- FPGA_Quartus_13.1/altpll1.vhd | 64 ++-- FPGA_Quartus_13.1/altpll2.bsf | 152 ++++----- FPGA_Quartus_13.1/altpll2.cmp | 2 +- FPGA_Quartus_13.1/altpll2.inc | 2 +- FPGA_Quartus_13.1/altpll2.qip | 2 +- FPGA_Quartus_13.1/altpll2.vhd | 32 +- FPGA_Quartus_13.1/altpll4.bsf | 250 +++++++------- FPGA_Quartus_13.1/altpll4.cmp | 60 ++-- FPGA_Quartus_13.1/altpll4.inc | 62 ++-- FPGA_Quartus_13.1/altpll4.mif | 348 +++++++++---------- FPGA_Quartus_13.1/altpll4.ppf | 34 +- FPGA_Quartus_13.1/altpll4.qip | 14 +- FPGA_Quartus_13.1/altpll4.tdf | 596 ++++++++++++++++----------------- FPGA_Quartus_13.1/firebee1.qsf | 26 +- FPGA_Quartus_13.1/firebee1.sdc | 2 +- 19 files changed, 883 insertions(+), 883 deletions(-) diff --git a/FPGA_Quartus_13.1/altpll1.bsf b/FPGA_Quartus_13.1/altpll1.bsf index 38a83a8..9649e11 100644 --- a/FPGA_Quartus_13.1/altpll1.bsf +++ b/FPGA_Quartus_13.1/altpll1.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2010 Altera Corporation +Copyright (C) 1991-2014 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.1")) +(header "symbol" (version "1.2")) (symbol - (rect 0 0 272 184) - (text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 168 25 180)(font "Arial" )) + (rect 0 0 272 176) + (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 161 26 172)(font "Arial" )) (port (pt 0 64) (input) - (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)(line_width 1)) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) ) (port (pt 272 64) (output) - (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) - (text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8))) - (line (pt 272 64)(pt 224 64)(line_width 1)) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8))) ) (port (pt 272 80) (output) - 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DO NOT EDIT THIS FILE! -- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -131,35 +131,35 @@ ARCHITECTURE SYN OF altpll1 IS width_clock : NATURAL ); PORT ( + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - locked : OUT STD_LOGIC ; - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + locked : OUT STD_LOGIC ); END COMPONENT; BEGIN sub_wire7_bv(0 DOWNTO 0) <= "0"; sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - locked <= sub_wire4; + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + locked <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; sub_wire5 <= inclk0; sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", - clk0_divide_by => 11, + clk0_divide_by => 11, clk0_duty_cycle => 50, - clk0_multiply_by => 16, + clk0_multiply_by => 16, clk0_phase_shift => "0", - clk1_divide_by => 33, + clk1_divide_by => 33, clk1_duty_cycle => 50, - clk1_multiply_by => 16, + clk1_multiply_by => 16, clk1_phase_shift => "0", clk2_divide_by => 1375, clk2_duty_cycle => 50, @@ -218,7 +218,7 @@ BEGIN PORT MAP ( inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire4 + locked => sub_wire2 ); @@ -244,14 +244,14 @@ END SYN; -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" @@ -270,21 +270,21 @@ END SYN; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" @@ -298,7 +298,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" @@ -338,13 +338,13 @@ END SYN; -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" @@ -406,17 +406,17 @@ END SYN; -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE diff --git a/FPGA_Quartus_13.1/altpll2.bsf b/FPGA_Quartus_13.1/altpll2.bsf index ac3d77f..4bad59d 100644 --- a/FPGA_Quartus_13.1/altpll2.bsf +++ b/FPGA_Quartus_13.1/altpll2.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2010 Altera Corporation +Copyright (C) 1991-2014 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. 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DO NOT EDIT THIS FILE! -- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2010 Altera Corporation +--Copyright (C) 1991-2014 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS width_clock : NATURAL ); PORT ( - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) ); END COMPONENT; @@ -149,14 +149,14 @@ BEGIN sub_wire8_bv(0 DOWNTO 0) <= "0"; sub_wire8 <= To_stdlogicvector(sub_wire8_bv); sub_wire5 <= sub_wire0(4); - sub_wire4 <= sub_wire0(3); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - c3 <= sub_wire4; + sub_wire4 <= sub_wire0(2); + sub_wire3 <= sub_wire0(0); + sub_wire2 <= sub_wire0(3); + sub_wire1 <= sub_wire0(1); + c1 <= sub_wire1; + c3 <= sub_wire2; + c0 <= sub_wire3; + c2 <= sub_wire4; c4 <= sub_wire5; sub_wire6 <= inclk0; sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; @@ -293,7 +293,7 @@ END SYN; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" @@ -459,18 +459,18 @@ END SYN; -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE diff --git a/FPGA_Quartus_13.1/altpll4.bsf b/FPGA_Quartus_13.1/altpll4.bsf index e071d43..88f8113 100644 --- a/FPGA_Quartus_13.1/altpll4.bsf +++ b/FPGA_Quartus_13.1/altpll4.bsf @@ -1,125 +1,125 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 376 232) - (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 213 31 228)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 88 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) - (text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 88 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 88 120)(line_width 1)) - ) - (port - (pt 0 144) - (input) - (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) - (text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 88 144)(line_width 1)) - ) - (port - (pt 0 168) - (input) - (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) - (text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 88 168)(line_width 1)) - ) - (port - (pt 0 192) - (input) - (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) - (text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8))) - (line (pt 0 192)(pt 88 192)(line_width 1)) - ) - (port - (pt 376 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) - (line (pt 376 72)(pt 288 72)(line_width 1)) - ) - (port - (pt 376 96) - (output) - (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) - (text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) - (line (pt 376 96)(pt 288 96)(line_width 1)) - ) - (port - (pt 376 120) - (output) - (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) - (text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) - (line (pt 376 120)(pt 288 120)(line_width 1)) - ) - (port - (pt 376 144) - (output) - (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) - (text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) - (line (pt 376 144)(pt 288 144)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) - (text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) - (text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) - (text "Clk " (rect 99 167 116 181)(font "Arial" )) - (text "Ratio" (rect 125 167 149 181)(font "Arial" )) - (text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) - (text "DC (%)" (rect 204 167 239 181)(font "Arial" )) - (text "c0" (rect 103 185 115 199)(font "Arial" )) - (text "2/1" (rect 131 185 146 199)(font "Arial" )) - (text "0.00" (rect 167 185 188 199)(font "Arial" )) - (text "50.00" (rect 209 185 236 199)(font "Arial" )) - (line (pt 0 0)(pt 377 0)(line_width 1)) - (line (pt 377 0)(pt 377 233)(line_width 1)) - (line (pt 0 233)(pt 377 233)(line_width 1)) - (line (pt 0 0)(pt 0 233)(line_width 1)) - (line (pt 96 164)(pt 246 164)(line_width 1)) - (line (pt 96 181)(pt 246 181)(line_width 1)) - (line (pt 96 199)(pt 246 199)(line_width 1)) - (line (pt 96 164)(pt 96 199)(line_width 1)) - (line (pt 122 164)(pt 122 199)(line_width 3)) - (line (pt 156 164)(pt 156 199)(line_width 3)) - (line (pt 201 164)(pt 201 199)(line_width 3)) - (line (pt 245 164)(pt 245 199)(line_width 1)) - (line (pt 88 56)(pt 288 56)(line_width 1)) - (line (pt 288 56)(pt 288 216)(line_width 1)) - (line (pt 88 216)(pt 288 216)(line_width 1)) - (line (pt 88 56)(pt 88 216)(line_width 1)) - ) -) +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2014 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 312 184) + (text "altpll4" (rect 139 0 181 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 169 26 180)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 72 64)) + ) + (port + (pt 0 80) + (input) + (text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8))) + (text "areset" (rect 4 67 35 79)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 72 80)) + ) + (port + (pt 0 96) + (input) + (text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 83 40 95)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 72 96)) + ) + (port + (pt 0 112) + (input) + (text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 99 48 111)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 72 112)) + ) + (port + (pt 0 128) + (input) + (text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 115 57 127)(font "Arial" (font_size 8))) + (line (pt 0 128)(pt 72 128)) + ) + (port + (pt 0 144) + (input) + (text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 131 66 143)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 72 144)) + ) + (port + (pt 312 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 297 51 309 63)(font "Arial" (font_size 8))) + ) + (port + (pt 312 80) + (output) + (text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8))) + (text "scandataout" (rect 250 67 309 79)(font "Arial" (font_size 8))) + ) + (port + (pt 312 96) + (output) + (text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8))) + (text "scandone" (rect 262 83 309 95)(font "Arial" (font_size 8))) + ) + (port + (pt 312 112) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 277 99 308 111)(font "Arial" (font_size 8))) + ) + (drawing + (text "Cyclone III" (rect 254 171 554 352)(font "Arial" )) + (text "inclk0 frequency: 48.000 MHz" (rect 82 93 290 196)(font "Arial" )) + (text "Operation Mode: Normal" (rect 82 105 267 220)(font "Arial" )) + (text "Clk " (rect 83 124 181 258)(font "Arial" )) + (text "Ratio" (rect 103 124 229 258)(font "Arial" )) + (text "Ph (dg)" (rect 129 124 289 258)(font "Arial" )) + (text "DC (%)" (rect 164 124 360 258)(font "Arial" )) + (text "c0" (rect 86 137 183 284)(font "Arial" )) + (text "2/1" (rect 108 137 229 284)(font "Arial" )) + (text "0.00" (rect 135 137 289 284)(font "Arial" )) + (text "50.00" (rect 168 137 360 284)(font "Arial" )) + (line (pt 0 0)(pt 313 0)) + (line (pt 313 0)(pt 313 186)) + (line (pt 0 186)(pt 313 186)) + (line (pt 0 0)(pt 0 186)) + (line (pt 80 122)(pt 196 122)) + (line (pt 80 134)(pt 196 134)) + (line (pt 80 147)(pt 196 147)) + (line (pt 80 122)(pt 80 147)) + (line (pt 100 122)(pt 100 147)(line_width 3)) + (line (pt 126 122)(pt 126 147)(line_width 3)) + (line (pt 161 122)(pt 161 147)(line_width 3)) + (line (pt 195 122)(pt 195 147)) + (line (pt 72 48)(pt 239 48)) + (line (pt 239 48)(pt 239 168)) + (line (pt 72 168)(pt 239 168)) + (line (pt 72 48)(pt 72 168)) + (line (pt 311 64)(pt 239 64)) + (line (pt 311 80)(pt 239 80)) + (line (pt 311 96)(pt 239 96)) + (line (pt 311 112)(pt 239 112)) + ) +) diff --git a/FPGA_Quartus_13.1/altpll4.cmp b/FPGA_Quartus_13.1/altpll4.cmp index 83b3c1e..90deb34 100644 --- a/FPGA_Quartus_13.1/altpll4.cmp +++ b/FPGA_Quartus_13.1/altpll4.cmp @@ -1,30 +1,30 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -component altpll4 - PORT - ( - areset : IN STD_LOGIC := '0'; - configupdate : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - scanclk : IN STD_LOGIC := '1'; - scanclkena : IN STD_LOGIC := '0'; - scandata : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC ; - scandataout : OUT STD_LOGIC ; - scandone : OUT STD_LOGIC - ); -end component; +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component altpll4 + PORT + ( + areset : IN STD_LOGIC := '0'; + configupdate : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + scanclk : IN STD_LOGIC := '1'; + scanclkena : IN STD_LOGIC := '0'; + scandata : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ; + scandataout : OUT STD_LOGIC ; + scandone : OUT STD_LOGIC + ); +end component; diff --git a/FPGA_Quartus_13.1/altpll4.inc b/FPGA_Quartus_13.1/altpll4.inc index 39f54c9..71e74e8 100644 --- a/FPGA_Quartus_13.1/altpll4.inc +++ b/FPGA_Quartus_13.1/altpll4.inc @@ -1,31 +1,31 @@ ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -FUNCTION altpll4 -( - areset, - configupdate, - inclk0, - scanclk, - scanclkena, - scandata -) - -RETURNS ( - c0, - locked, - scandataout, - scandone -); +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +FUNCTION altpll4 +( + areset, + configupdate, + inclk0, + scanclk, + scanclkena, + scandata +) + +RETURNS ( + c0, + locked, + scandataout, + scandone +); diff --git a/FPGA_Quartus_13.1/altpll4.mif b/FPGA_Quartus_13.1/altpll4.mif index e50eda2..432d991 100644 --- a/FPGA_Quartus_13.1/altpll4.mif +++ b/FPGA_Quartus_13.1/altpll4.mif @@ -1,174 +1,174 @@ --- Copyright (C) 1991-2010 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - --- MIF file representing initial state of PLL Scan Chain --- Device Family: Cyclone III --- Device Part: - --- Device Speed Grade: 8 --- PLL Scan Chain: Fast PLL (144 bits) --- File Name: C:\FireBee\FPGA\altpll4.mif --- Generated: Mon Dec 06 01:47:24 2010 - -WIDTH=1; -DEPTH=144; - -ADDRESS_RADIX=UNS; -DATA_RADIX=UNS; - -CONTENT BEGIN - 0 : 0; -- Reserved Bits = 0 (1 bit(s)) - 1 : 0; -- Reserved Bits = 0 (1 bit(s)) - 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) - 3 : 0; - 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) - 5 : 1; - 6 : 0; - 7 : 1; - 8 : 1; - 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) - 10 : 0; -- Reserved Bits = 0 (5 bit(s)) - 11 : 0; - 12 : 0; - 13 : 0; - 14 : 0; - 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) - 16 : 0; - 17 : 1; - 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) - 19 : 0; -- N counter: High Count = 0 (8 bit(s)) - 20 : 0; - 21 : 0; - 22 : 0; - 23 : 0; - 24 : 0; - 25 : 0; - 26 : 0; - 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) - 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) - 29 : 0; - 30 : 0; - 31 : 0; - 32 : 0; - 33 : 0; - 34 : 0; - 35 : 0; - 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) - 37 : 0; -- M counter: High Count = 6 (8 bit(s)) - 38 : 0; - 39 : 0; - 40 : 0; - 41 : 0; - 42 : 1; - 43 : 1; - 44 : 0; - 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) - 46 : 0; -- M counter: Low Count = 6 (8 bit(s)) - 47 : 0; - 48 : 0; - 49 : 0; - 50 : 0; - 51 : 1; - 52 : 1; - 53 : 0; - 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) - 55 : 0; -- clk0 counter: High Count = 3 (8 bit(s)) - 56 : 0; - 57 : 0; - 58 : 0; - 59 : 0; - 60 : 0; - 61 : 1; - 62 : 1; - 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) - 64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s)) - 65 : 0; - 66 : 0; - 67 : 0; - 68 : 0; - 69 : 0; - 70 : 1; - 71 : 1; - 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) - 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) - 74 : 0; - 75 : 0; - 76 : 0; - 77 : 0; - 78 : 0; - 79 : 0; - 80 : 0; - 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) - 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) - 83 : 0; - 84 : 0; - 85 : 0; - 86 : 0; - 87 : 0; - 88 : 0; - 89 : 0; - 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) - 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) - 92 : 0; - 93 : 0; - 94 : 0; - 95 : 0; - 96 : 0; - 97 : 0; - 98 : 0; - 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) - 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) - 101 : 0; - 102 : 0; - 103 : 0; - 104 : 0; - 105 : 0; - 106 : 0; - 107 : 0; - 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) - 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) - 110 : 0; - 111 : 0; - 112 : 0; - 113 : 0; - 114 : 0; - 115 : 0; - 116 : 0; - 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) - 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) - 119 : 0; - 120 : 0; - 121 : 0; - 122 : 0; - 123 : 0; - 124 : 0; - 125 : 0; - 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) - 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) - 128 : 0; - 129 : 0; - 130 : 0; - 131 : 0; - 132 : 0; - 133 : 0; - 134 : 0; - 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) - 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) - 137 : 0; - 138 : 0; - 139 : 0; - 140 : 0; - 141 : 0; - 142 : 0; - 143 : 0; -END; +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- MIF file representing initial state of PLL Scan Chain +-- Device Family: Cyclone III +-- Device Part: - +-- Device Speed Grade: 8 +-- PLL Scan Chain: Fast PLL (144 bits) +-- File Name: /home/mfro/Dokumente/Development/workspace/FPGA_quartus_ori/altpll4.mif +-- Generated: Fri Oct 30 21:50:08 2015 + +WIDTH=1; +DEPTH=144; + +ADDRESS_RADIX=UNS; +DATA_RADIX=UNS; + +CONTENT BEGIN + 0 : 0; -- Reserved Bits = 0 (1 bit(s)) + 1 : 0; -- Reserved Bits = 0 (1 bit(s)) + 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) + 3 : 0; + 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) + 5 : 1; + 6 : 0; + 7 : 1; + 8 : 1; + 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) + 10 : 0; -- Reserved Bits = 0 (5 bit(s)) + 11 : 0; + 12 : 0; + 13 : 0; + 14 : 0; + 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) + 16 : 0; + 17 : 1; + 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) + 19 : 0; -- N counter: High Count = 0 (8 bit(s)) + 20 : 0; + 21 : 0; + 22 : 0; + 23 : 0; + 24 : 0; + 25 : 0; + 26 : 0; + 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) + 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) + 29 : 0; + 30 : 0; + 31 : 0; + 32 : 0; + 33 : 0; + 34 : 0; + 35 : 0; + 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) + 37 : 0; -- M counter: High Count = 6 (8 bit(s)) + 38 : 0; + 39 : 0; + 40 : 0; + 41 : 0; + 42 : 1; + 43 : 1; + 44 : 0; + 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) + 46 : 0; -- M counter: Low Count = 6 (8 bit(s)) + 47 : 0; + 48 : 0; + 49 : 0; + 50 : 0; + 51 : 1; + 52 : 1; + 53 : 0; + 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) + 55 : 0; -- clk0 counter: High Count = 3 (8 bit(s)) + 56 : 0; + 57 : 0; + 58 : 0; + 59 : 0; + 60 : 0; + 61 : 1; + 62 : 1; + 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) + 64 : 0; -- clk0 counter: Low Count = 3 (8 bit(s)) + 65 : 0; + 66 : 0; + 67 : 0; + 68 : 0; + 69 : 0; + 70 : 1; + 71 : 1; + 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 74 : 0; + 75 : 0; + 76 : 0; + 77 : 0; + 78 : 0; + 79 : 0; + 80 : 0; + 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 83 : 0; + 84 : 0; + 85 : 0; + 86 : 0; + 87 : 0; + 88 : 0; + 89 : 0; + 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) + 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) + 92 : 0; + 93 : 0; + 94 : 0; + 95 : 0; + 96 : 0; + 97 : 0; + 98 : 0; + 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s)) + 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s)) + 101 : 0; + 102 : 0; + 103 : 0; + 104 : 0; + 105 : 0; + 106 : 0; + 107 : 0; + 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s)) + 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s)) + 110 : 0; + 111 : 0; + 112 : 0; + 113 : 0; + 114 : 0; + 115 : 0; + 116 : 0; + 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s)) + 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s)) + 119 : 0; + 120 : 0; + 121 : 0; + 122 : 0; + 123 : 0; + 124 : 0; + 125 : 0; + 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s)) + 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s)) + 128 : 0; + 129 : 0; + 130 : 0; + 131 : 0; + 132 : 0; + 133 : 0; + 134 : 0; + 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s)) + 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s)) + 137 : 0; + 138 : 0; + 139 : 0; + 140 : 0; + 141 : 0; + 142 : 0; + 143 : 0; +END; diff --git a/FPGA_Quartus_13.1/altpll4.ppf b/FPGA_Quartus_13.1/altpll4.ppf index 541ce91..03b008b 100644 --- a/FPGA_Quartus_13.1/altpll4.ppf +++ b/FPGA_Quartus_13.1/altpll4.ppf @@ -1,17 +1,17 @@ - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + diff --git a/FPGA_Quartus_13.1/altpll4.qip b/FPGA_Quartus_13.1/altpll4.qip index f44acdc..66c1e6f 100644 --- a/FPGA_Quartus_13.1/altpll4.qip +++ b/FPGA_Quartus_13.1/altpll4.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "9.1" -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"] diff --git a/FPGA_Quartus_13.1/altpll4.tdf b/FPGA_Quartus_13.1/altpll4.tdf index 3ec77d4..69c77ef 100644 --- a/FPGA_Quartus_13.1/altpll4.tdf +++ b/FPGA_Quartus_13.1/altpll4.tdf @@ -1,298 +1,298 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: altpll4.tdf --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2010 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - -INCLUDE "altpll.inc"; - - - -SUBDESIGN altpll4 -( - areset : INPUT = GND; - configupdate : INPUT = GND; - inclk0 : INPUT = GND; - scanclk : INPUT = VCC; - scanclkena : INPUT = GND; - scandata : INPUT = GND; - c0 : OUTPUT; - locked : OUTPUT; - scandataout : OUTPUT; - scandone : OUTPUT; -) - -VARIABLE - - altpll_component : altpll WITH ( - BANDWIDTH_TYPE = "AUTO", - CLK0_DIVIDE_BY = 1, - CLK0_DUTY_CYCLE = 50, - CLK0_MULTIPLY_BY = 2, - CLK0_PHASE_SHIFT = "0", - COMPENSATE_CLOCK = "CLK0", - INCLK0_INPUT_FREQUENCY = 20833, - INTENDED_DEVICE_FAMILY = "Cyclone III", - LPM_TYPE = "altpll", - OPERATION_MODE = "NORMAL", - PLL_TYPE = "AUTO", - PORT_ACTIVECLOCK = "PORT_UNUSED", - PORT_ARESET = "PORT_USED", - PORT_CLKBAD0 = "PORT_UNUSED", - PORT_CLKBAD1 = "PORT_UNUSED", - PORT_CLKLOSS = "PORT_UNUSED", - PORT_CLKSWITCH = "PORT_UNUSED", - PORT_CONFIGUPDATE = "PORT_USED", - PORT_FBIN = "PORT_UNUSED", - PORT_INCLK0 = "PORT_USED", - PORT_INCLK1 = "PORT_UNUSED", - PORT_LOCKED = "PORT_USED", - PORT_PFDENA = "PORT_UNUSED", - PORT_PHASECOUNTERSELECT = "PORT_UNUSED", - PORT_PHASEDONE = "PORT_UNUSED", - PORT_PHASESTEP = "PORT_UNUSED", - PORT_PHASEUPDOWN = "PORT_UNUSED", - PORT_PLLENA = "PORT_UNUSED", - PORT_SCANACLR = "PORT_UNUSED", - PORT_SCANCLK = "PORT_USED", - PORT_SCANCLKENA = "PORT_USED", - PORT_SCANDATA = "PORT_USED", - PORT_SCANDATAOUT = "PORT_USED", - PORT_SCANDONE = "PORT_USED", - PORT_SCANREAD = "PORT_UNUSED", - PORT_SCANWRITE = "PORT_UNUSED", - PORT_clk0 = "PORT_USED", - PORT_clk1 = "PORT_UNUSED", - PORT_clk2 = "PORT_UNUSED", - PORT_clk3 = "PORT_UNUSED", - PORT_clk4 = "PORT_UNUSED", - PORT_clk5 = "PORT_UNUSED", - PORT_clkena0 = "PORT_UNUSED", - PORT_clkena1 = "PORT_UNUSED", - PORT_clkena2 = "PORT_UNUSED", - PORT_clkena3 = "PORT_UNUSED", - PORT_clkena4 = "PORT_UNUSED", - PORT_clkena5 = "PORT_UNUSED", - PORT_extclk0 = "PORT_UNUSED", - PORT_extclk1 = "PORT_UNUSED", - PORT_extclk2 = "PORT_UNUSED", - PORT_extclk3 = "PORT_UNUSED", - SELF_RESET_ON_LOSS_LOCK = "OFF", - WIDTH_CLOCK = 5, - scan_chain_mif_file = "altpll4.mif" - ); - -BEGIN - - c0 = altpll_component.clk[0..0]; - scandone = altpll_component.scandone; - scandataout = altpll_component.scandataout; - locked = altpll_component.locked; - altpll_component.scanclkena = scanclkena; - altpll_component.inclk[0..0] = inclk0; - altpll_component.inclk[1..1] = GND; - altpll_component.scandata = scandata; - altpll_component.areset = areset; - altpll_component.scanclk = scanclk; - altpll_component.configupdate = configupdate; -END; - - - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" --- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" --- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" --- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" --- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 --- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 --- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 --- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE --- Retrieval info: LIB_FILE: altera_mf +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: altpll4.tdf +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + +INCLUDE "altpll.inc"; + + + +SUBDESIGN altpll4 +( + areset : INPUT = GND; + configupdate : INPUT = GND; + inclk0 : INPUT = GND; + scanclk : INPUT = VCC; + scanclkena : INPUT = GND; + scandata : INPUT = GND; + c0 : OUTPUT; + locked : OUTPUT; + scandataout : OUTPUT; + scandone : OUTPUT; +) + +VARIABLE + + altpll_component : altpll WITH ( + BANDWIDTH_TYPE = "AUTO", + CLK0_DIVIDE_BY = 1, + CLK0_DUTY_CYCLE = 50, + CLK0_MULTIPLY_BY = 2, + CLK0_PHASE_SHIFT = "0", + COMPENSATE_CLOCK = "CLK0", + INCLK0_INPUT_FREQUENCY = 20833, + INTENDED_DEVICE_FAMILY = "Cyclone III", + LPM_TYPE = "altpll", + OPERATION_MODE = "NORMAL", + PLL_TYPE = "AUTO", + PORT_ACTIVECLOCK = "PORT_UNUSED", + PORT_ARESET = "PORT_USED", + PORT_CLKBAD0 = "PORT_UNUSED", + PORT_CLKBAD1 = "PORT_UNUSED", + PORT_CLKLOSS = "PORT_UNUSED", + PORT_CLKSWITCH = "PORT_UNUSED", + PORT_CONFIGUPDATE = "PORT_USED", + PORT_FBIN = "PORT_UNUSED", + PORT_INCLK0 = "PORT_USED", + PORT_INCLK1 = "PORT_UNUSED", + PORT_LOCKED = "PORT_USED", + PORT_PFDENA = "PORT_UNUSED", + PORT_PHASECOUNTERSELECT = "PORT_UNUSED", + PORT_PHASEDONE = "PORT_UNUSED", + PORT_PHASESTEP = "PORT_UNUSED", + PORT_PHASEUPDOWN = "PORT_UNUSED", + PORT_PLLENA = "PORT_UNUSED", + PORT_SCANACLR = "PORT_UNUSED", + PORT_SCANCLK = "PORT_USED", + PORT_SCANCLKENA = "PORT_USED", + PORT_SCANDATA = "PORT_USED", + PORT_SCANDATAOUT = "PORT_USED", + PORT_SCANDONE = "PORT_USED", + PORT_SCANREAD = "PORT_UNUSED", + PORT_SCANWRITE = "PORT_UNUSED", + PORT_clk0 = "PORT_USED", + PORT_clk1 = "PORT_UNUSED", + PORT_clk2 = "PORT_UNUSED", + PORT_clk3 = "PORT_UNUSED", + PORT_clk4 = "PORT_UNUSED", + PORT_clk5 = "PORT_UNUSED", + PORT_clkena0 = "PORT_UNUSED", + PORT_clkena1 = "PORT_UNUSED", + PORT_clkena2 = "PORT_UNUSED", + PORT_clkena3 = "PORT_UNUSED", + PORT_clkena4 = "PORT_UNUSED", + PORT_clkena5 = "PORT_UNUSED", + PORT_extclk0 = "PORT_UNUSED", + PORT_extclk1 = "PORT_UNUSED", + PORT_extclk2 = "PORT_UNUSED", + PORT_extclk3 = "PORT_UNUSED", + SELF_RESET_ON_LOSS_LOCK = "OFF", + WIDTH_CLOCK = 5, + scan_chain_mif_file = "altpll4.mif" + ); + +BEGIN + + c0 = altpll_component.clk[0..0]; + scandataout = altpll_component.scandataout; + scandone = altpll_component.scandone; + locked = altpll_component.locked; + altpll_component.areset = areset; + altpll_component.configupdate = configupdate; + altpll_component.inclk[0..0] = inclk0; + altpll_component.inclk[1..1] = GND; + altpll_component.scanclk = scanclk; + altpll_component.scanclkena = scanclkena; + altpll_component.scandata = scandata; +END; + + + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk" +-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena" +-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" +-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" +-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 6be8aa6..e8a559d 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -41,8 +41,8 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== @@ -367,14 +367,14 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to VA set_instance_assignment -name IO_STANDARD "2.5 V" -to VD @@ -559,7 +559,7 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT @@ -568,8 +568,8 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN @@ -603,9 +603,9 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 2260426..3551868 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -3,7 +3,7 @@ # Synopsis design constraints for the Firebee project # # # # This file is part of the Firebee ACP project. # -# http://www.experiment-s.de # +# http://www.firebee.org # # # # Description: # # timing constraints for the Firebee VHDL config # From 7bdeac0860018b92171f17f7dfa481f0000216dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 9 Jan 2016 18:49:18 +0000 Subject: [PATCH 036/127] rename video registers to their Falcon names --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 26 +- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 652 ++++++++++-------- FPGA_Quartus_13.1/Video/Video.bdf | 490 ++++++------- FPGA_Quartus_13.1/firebee1.qsf | 1 + FPGA_Quartus_13.1/firebee1.sdc.groups | 179 +++++ 5 files changed, 819 insertions(+), 529 deletions(-) create mode 100644 FPGA_Quartus_13.1/firebee1.sdc.groups diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index a9a9be7..7c549b2 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -202,7 +202,7 @@ BEGIN END CASE; -- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; VCKE = VIDEO_RAM_CTR0; nVCS = !VIDEO_RAM_CTR1; DDR_REFRESH_ON = VIDEO_RAM_CTR2; @@ -230,10 +230,10 @@ BEGIN DDR_CS.ENA = FB_ALE; DDR_CS = DDR_SEL; - -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP�TER + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS - # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP�TER + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER CPU_REQ.CLK = DDR_SYNC_66M; CPU_REQ = CPU_SIG # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG @@ -350,7 +350,7 @@ BEGIN CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; VCAS = VCC; - SR_DDR_FB = CPU_AC; -- READ DATEN F�R CPU + SR_DDR_FB = CPU_AC; -- READ DATEN FÃœR CPU SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN DDR_SM = DS_T5R; @@ -359,7 +359,7 @@ BEGIN BLITTER_AC = BLITTER_AC; IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- MANUEL PRECHARGE + VA_S[10] = GND; -- MANUELL PRECHARGE BA_S[] = FIFO_BA[]; DDR_SM = DS_T6F; ELSE @@ -393,7 +393,7 @@ BEGIN VCAS = VCC; VWE = VCC; SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDRWR_D_SEL = VCC; -- 2. H�LFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV DDR_SM = DS_T7W; @@ -401,7 +401,7 @@ BEGIN CPU_AC = CPU_AC; BLITTER_AC = BLITTER_AC; SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDRWR_D_SEL = VCC; -- 2. H�LFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN DDR_SM = DS_T8W; WHEN DS_T8W => @@ -536,12 +536,12 @@ BEGIN -- CLOSE FIFO BANK WHEN DS_CB6 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- B�NKE SCHLIESSEN + VRAS = VCC; -- BÄNKE SCHLIESSEN VWE = VCC; DDR_SM = DS_N7; WHEN DS_CB8 => FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- B�NKE SCHLIESSEN + VRAS = VCC; -- BÄNKE SCHLIESSEN VWE = VCC; DDR_SM = DS_T1; @@ -599,14 +599,14 @@ BEGIN FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00"); FIFO_BANK_OK.CLK = DDRCLK0; FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK; - -- Z�HLER R�CKSETZEN WENN CLR FIFO ---------------- + -- ZÄHLER RÃœCKSETZEN WENN CLR FIFO ---------------- CLR_FIFO_SYNC.CLK =DDRCLK0; CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN CLEAR_FIFO_CNT.CLK = DDRCLK0; CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE; STOP.CLK = DDRCLK0; STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT; - -- Z�HLEN ----------------------------------------------- + -- ZÄHLEN ----------------------------------------------- VIDEO_ADR_CNT[].CLK = DDRCLK0; VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT; VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] @@ -623,12 +623,12 @@ BEGIN -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS ----------------------------------------------------------------------------------------- DDR_REFRESH_CNT[].CLK = CLK33M; - DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z�HLEN 0-2047 + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 REFRESH_TIME.CLK = DDRCLK0; REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC DDR_REFRESH_SIG[].CLK = DDRCLK0; DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; - DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST�CK (8 REFRESH UND 1 ALS VORLAUF) + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÃœCK (8 REFRESH UND 1 ALS VORLAUF) # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT DDR_REFRESH_REQ.CLK = DDRCLK0; DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 28c1ef3..802f797 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -93,15 +93,15 @@ VARIABLE ACP_VIDEO_ON :NODE; SYS_CTR[6..0] :DFFE; SYS_CTR_CS :NODE; - VDL_LOF[15..0] :DFFE; - VDL_LOF_CS :NODE; - VDL_LWD[15..0] :DFFE; - VDL_LWD_CS :NODE; + LOF[15..0] :DFFE; + LOF_CS :NODE; + LWD[15..0] :DFFE; + LWD_CS :NODE; -- DIV. CONTROL REGISTER CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK + HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK HSYNC_START :DFF; LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT VSYNC :DFF; @@ -113,9 +113,9 @@ VARIABLE DPO_ON :DFF; DPO_OFF :DFF; VDTRON :DFF; - VDO_ZL :DFFE; - VDO_ON :DFF; - VDO_OFF :DFF; + VCO_ZL :DFFE; + VCO_ON :DFF; + VCO_OFF :DFF; VHCNT[11..0] :DFF; SUB_PIXEL_CNT[6..0] :DFFE; VVCNT[10..0] :DFFE; @@ -150,18 +150,18 @@ VARIABLE H_TOTAL[11..0] :NODE; HDIS_LEN[11..0] :NODE; MULF[5..0] :NODE; - VDL_HHT[11..0] :DFFE; - VDL_HHT_CS :NODE; - VDL_HBE[11..0] :DFFE; - VDL_HBE_CS :NODE; - VDL_HDB[11..0] :DFFE; - VDL_HDB_CS :NODE; - VDL_HDE[11..0] :DFFE; - VDL_HDE_CS :NODE; - VDL_HBB[11..0] :DFFE; - VDL_HBB_CS :NODE; - VDL_HSS[11..0] :DFFE; - VDL_HSS_CS :NODE; + HHT[11..0] :DFFE; + HHT_CS :NODE; + HBE[11..0] :DFFE; + HBE_CS :NODE; + HDB[11..0] :DFFE; + HDB_CS :NODE; + HDE[11..0] :DFFE; + HDE_CS :NODE; + HBB[11..0] :DFFE; + HBB_CS :NODE; + HSS[11..0] :DFFE; + HSS_CS :NODE; -- VERTIKAL RAND_OBEN[10..0] :NODE; VDIS_START[10..0] :NODE; @@ -175,22 +175,22 @@ VARIABLE DOP_ZEI :DFF; DOP_FIFO_CLR :DFF; - VDL_VBE[10..0] :DFFE; - VDL_VBE_CS :NODE; - VDL_VDB[10..0] :DFFE; - VDL_VDB_CS :NODE; - VDL_VDE[10..0] :DFFE; - VDL_VDE_CS :NODE; - VDL_VBB[10..0] :DFFE; - VDL_VBB_CS :NODE; - VDL_VSS[10..0] :DFFE; - VDL_VSS_CS :NODE; - VDL_VFT[10..0] :DFFE; - VDL_VFT_CS :NODE; - VDL_VCT[8..0] :DFFE; - VDL_VCT_CS :NODE; - VDL_VMD[3..0] :DFFE; - VDL_VMD_CS :NODE; + VBE[10..0] :DFFE; + VBE_CS :NODE; + VDB[10..0] :DFFE; + VDB_CS :NODE; + VDE[10..0] :DFFE; + VDE_CS :NODE; + VBB[10..0] :DFFE; + VBB_CS :NODE; + VSS[10..0] :DFFE; + VSS_CS :NODE; + VFT[10..0] :DFFE; + VFT_CS :NODE; + VCO[8..0] :DFFE; + VCO_CS :NODE; + VCNTRL[3..0] :DFFE; + VCNTRL_CS :NODE; BEGIN -- BYT SELECT 32 BIT @@ -242,7 +242,21 @@ BEGIN COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + + -- ACP VIDEO CONTROL + -- BIT 0 = ACP VIDEO ON + -- BIT 1 = POWER ON VIDEO DAC + -- BIT 2 = ACP 24BIT + -- BIT 3 = ACP 16BIT + -- BIT 4 = ACP 8BIT + -- BIT 5 = ACP 1BIT + -- BIT 6 = FALCON SHIFT MODE + -- BIT 7 = ST SHIFT MODE + -- BIT 9..8 = VCLK FREQUENZ + -- BIT 15 =-SYNC ALLOWED + -- BIT 31..16 = VIDEO_RAM_CTR + -- BIT 25 = RANDFARBE EINSCHALTEN + -- BIT 26 = STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; @@ -254,41 +268,46 @@ BEGIN ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG + -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; - ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 + ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2] == H"104"; -- $410/4 ATARI_HH[] = FB_AD[]; ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 640x480 ATARI_VH[].CLK = MAIN_CLK; - ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 + ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2] == H"105"; -- $414/4 ATARI_VH[] = FB_AD[]; ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; + -- HORIZONTAL TIMING 320x240 ATARI_HL[].CLK = MAIN_CLK; - ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 + ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2] == H"106"; -- $418/4 ATARI_HL[] = FB_AD[]; ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 320x240 ATARI_VL[].CLK = MAIN_CLK; - ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 + ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2] == H"107"; -- $41C/4 ATARI_VL[] = FB_AD[]; ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; + -- VIDEO PLL CONFIG - VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9] == H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VR_WR.CLK = MAIN_CLK; VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; @@ -296,10 +315,11 @@ BEGIN VR_DOUT[].ENA = !VR_BUSY; VR_DOUT[] = VR_D[]; VR_FRQ[].CLK = MAIN_CLK; - VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; + VR_FRQ[].ENA = VR_WR & FB_ADR[8..0] == H"04"; VR_FRQ[] = FB_AD[23..16]; + -- VIDEO PLL RECONFIG - VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 + VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0] == H"800" & FB_B0; -- $(F)000'0800 VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------ @@ -310,6 +330,7 @@ BEGIN COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; + -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; @@ -325,6 +346,7 @@ BEGIN # B"101" & COLOR16 # B"110" & COLOR24 # B"111" & RAND_ON; + -- DIVERSE (VIDEO)-REGISTER ---------------------------- -- RANDFARBE CCR[].CLK = MAIN_CLK; @@ -333,282 +355,351 @@ BEGIN CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; - --SYS CTR - SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 + + -- System Config Register + -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi + -- |||||||| + -- |||||||+- RAM Wait Status + -- ||||||| 0 = 1 Wait (default) + -- ||||||| 1 = 0 Wait + -- ||||||+-- Video Bus Width + -- |||||| 0 = 16 Bit + -- |||||| 1 = 32 Bit (default) + -- ||||++--- ROM Wait Status + -- |||| 00 = reserved + -- |||| 01 = 2 Wait (default) + -- |||| 10 = 1 Wait + -- |||| 11 = 0 Wait + -- ||++----- Main Memory Size + -- || 01 = 4 MB + -- || 10 = 16 MB + -- ++------- Monitor Type + -- 00 Monochrome + -- 01 RGB + -- 10 VGA + -- 11 TV + + SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C003"; -- $8006/2 SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; BLITTER_ON = !SYS_CTR3; - --VDL_LOF - VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 - VDL_LOF[].CLK = MAIN_CLK; - VDL_LOF[] = FB_AD[31..16]; - VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; - VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; - --VDL_LWD - VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 - VDL_LWD[].CLK = MAIN_CLK; - VDL_LWD[] = FB_AD[31..16]; - VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; - VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; + + -- LOF + LOF_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C107"; -- $820E/2 + LOF[].CLK = MAIN_CLK; + LOF[] = FB_AD[31..16]; + LOF[15..8].ENA = LOF_CS & !nFB_WR & FB_B2; + LOF[7..0].ENA = LOF_CS & !nFB_WR & FB_B3; + + -- LWD + LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 + LWD[].CLK = MAIN_CLK; + LWD[] = FB_AD[31..16]; + LWD[15..8].ENA = LWD_CS & !nFB_WR & FB_B0; + LWD[7..0].ENA = LWD_CS & !nFB_WR & FB_B1; + -- HORIZONTAL - -- VDL_HHT - VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 - VDL_HHT[].CLK = MAIN_CLK; - VDL_HHT[] = FB_AD[27..16]; - VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; - VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; - -- VDL_HBE - VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 - VDL_HBE[].CLK = MAIN_CLK; - VDL_HBE[] = FB_AD[27..16]; - VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; - VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; - -- VDL_HDB - VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 - VDL_HDB[].CLK = MAIN_CLK; - VDL_HDB[] = FB_AD[27..16]; - VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; - VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; - -- VDL_HDE - VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 - VDL_HDE[].CLK = MAIN_CLK; - VDL_HDE[] = FB_AD[27..16]; - VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; - VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; - -- VDL_HBB - VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 - VDL_HBB[].CLK = MAIN_CLK; - VDL_HBB[] = FB_AD[27..16]; - VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; - VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; - -- VDL_HSS - VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 - VDL_HSS[].CLK = MAIN_CLK; - VDL_HSS[] = FB_AD[27..16]; - VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; - VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; + -- HHT + HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 + HHT[].CLK = MAIN_CLK; + HHT[] = FB_AD[27..16]; + HHT[11..8].ENA = HHT_CS & !nFB_WR & FB_B2; + HHT[7..0].ENA = HHT_CS & !nFB_WR & FB_B3; + + -- HBE + HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 + HBE[].CLK = MAIN_CLK; + HBE[] = FB_AD[27..16]; + HBE[11..8].ENA = HBE_CS & !nFB_WR & FB_B2; + HBE[7..0].ENA = HBE_CS & !nFB_WR & FB_B3; + + -- HDB + HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 + HDB[].CLK = MAIN_CLK; + HDB[] = FB_AD[27..16]; + HDB[11..8].ENA = HDB_CS & !nFB_WR & FB_B0; + HDB[7..0].ENA = HDB_CS & !nFB_WR & FB_B1; + -- HDE + HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 + HDE[].CLK = MAIN_CLK; + HDE[] = FB_AD[27..16]; + HDE[11..8].ENA = HDE_CS & !nFB_WR & FB_B2; + HDE[7..0].ENA = HDE_CS & !nFB_WR & FB_B3; + + -- HBB + HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 + HBB[].CLK = MAIN_CLK; + HBB[] = FB_AD[27..16]; + HBB[11..8].ENA = HBB_CS & !nFB_WR & FB_B0; + HBB[7..0].ENA = HBB_CS & !nFB_WR & FB_B1; + + -- HSS + HSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C146"; -- Videl HSYNC start register $828C / 2 + HSS[].CLK = MAIN_CLK; + HSS[] = FB_AD[27..16]; + HSS[11..8].ENA = HSS_CS & !nFB_WR & FB_B0; + HSS[7..0].ENA = HSS_CS & !nFB_WR & FB_B1; + -- VERTIKAL - -- VDL_VBE - VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 - VDL_VBE[].CLK = MAIN_CLK; - VDL_VBE[] = FB_AD[26..16]; - VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; - VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; - -- VDL_VDB - VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 - VDL_VDB[].CLK = MAIN_CLK; - VDL_VDB[] = FB_AD[26..16]; - VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; - VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; - -- VDL_VDE - VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 - VDL_VDE[].CLK = MAIN_CLK; - VDL_VDE[] = FB_AD[26..16]; - VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; - VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; - -- VDL_VBB - VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 - VDL_VBB[].CLK = MAIN_CLK; - VDL_VBB[] = FB_AD[26..16]; - VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; - VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; - -- VDL_VSS - VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 - VDL_VSS[].CLK = MAIN_CLK; - VDL_VSS[] = FB_AD[26..16]; - VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; - VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; - -- VDL_VFT - VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 - VDL_VFT[].CLK = MAIN_CLK; - VDL_VFT[] = FB_AD[26..16]; - VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; - VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; - -- VDL_VCT - VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 - VDL_VCT[].CLK = MAIN_CLK; - VDL_VCT[] = FB_AD[24..16]; - VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; - VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; - -- VDL_VMD - VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 - VDL_VMD[].CLK = MAIN_CLK; - VDL_VMD[] = FB_AD[19..16]; - VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; + -- VBE + VBE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C153"; -- $82A6/2 + VBE[].CLK = MAIN_CLK; + VBE[] = FB_AD[26..16]; + VBE[10..8].ENA = VBE_CS & !nFB_WR & FB_B2; + VBE[7..0].ENA = VBE_CS & !nFB_WR & FB_B3; + + -- VDB + VDB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C154"; -- $82A8/2 + VDB[].CLK = MAIN_CLK; + VDB[] = FB_AD[26..16]; + VDB[10..8].ENA = VDB_CS & !nFB_WR & FB_B0; + VDB[7..0].ENA = VDB_CS & !nFB_WR & FB_B1; + + -- VDE + VDE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C155"; -- $82AA/2 + VDE[].CLK = MAIN_CLK; + VDE[] = FB_AD[26..16]; + VDE[10..8].ENA = VDE_CS & !nFB_WR & FB_B2; + VDE[7..0].ENA = VDE_CS & !nFB_WR & FB_B3; + -- VBB + VBB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C152"; -- $82A4/2 + VBB[].CLK = MAIN_CLK; + VBB[] = FB_AD[26..16]; + VBB[10..8].ENA = VBB_CS & !nFB_WR & FB_B0; + VBB[7..0].ENA = VBB_CS & !nFB_WR & FB_B1; + + -- VSS + VSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C156"; -- $82AC/2 + VSS[].CLK = MAIN_CLK; + VSS[] = FB_AD[26..16]; + VSS[10..8].ENA = VSS_CS & !nFB_WR & FB_B0; + VSS[7..0].ENA = VSS_CS & !nFB_WR & FB_B1; + + -- VFT + VFT_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C151"; -- $82A2/2 + VFT[].CLK = MAIN_CLK; + VFT[] = FB_AD[26..16]; + VFT[10..8].ENA = VFT_CS & !nFB_WR & FB_B2; + VFT[7..0].ENA = VFT_CS & !nFB_WR & FB_B3; + + -- VCO + VCO_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C160"; -- $82C0 / 2 Falcon clock control register VCO + VCO[].CLK = MAIN_CLK; + VCO[] = FB_AD[24..16]; + VCO[8].ENA = VCO_CS & !nFB_WR & FB_B0; + VCO[7..0].ENA = VCO_CS & !nFB_WR & FB_B1; + + -- VCNTRL + VCNTRL_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C161"; -- $82C2 / 2 Falcon resolution control register VCNTRL + VCNTRL[].CLK = MAIN_CLK; + VCNTRL[] = FB_AD[19..16]; + VCNTRL[3..0].ENA = VCNTRL_CS & !nFB_WR & FB_B3; + --- REGISTER OUT + -- low word register access FB_AD[31..16] = lpm_bustri_WORD( - ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") - # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) - # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) - # VDL_LOF_CS & VDL_LOF[] - # VDL_LWD_CS & VDL_LWD[] - # VDL_HBE_CS & (0,VDL_HBE[]) - # VDL_HDB_CS & (0,VDL_HDB[]) - # VDL_HDE_CS & (0,VDL_HDE[]) - # VDL_HBB_CS & (0,VDL_HBB[]) - # VDL_HSS_CS & (0,VDL_HSS[]) - # VDL_HHT_CS & (0,VDL_HHT[]) - # VDL_VBE_CS & (0,VDL_VBE[]) - # VDL_VDB_CS & (0,VDL_VDB[]) - # VDL_VDE_CS & (0,VDL_VDE[]) - # VDL_VBB_CS & (0,VDL_VBB[]) - # VDL_VSS_CS & (0,VDL_VSS[]) - # VDL_VFT_CS & (0,VDL_VFT[]) - # VDL_VCT_CS & (0,VDL_VCT[]) - # VDL_VMD_CS & (0,VDL_VMD[]) + ST_SHIFT_MODE_CS & (0, ST_SHIFT_MODE[],B"00000000") + # FALCON_SHIFT_MODE_CS & (0, FALCON_SHIFT_MODE[]) + # SYS_CTR_CS & (B"100000000", SYS_CTR[6..4], !BLITTER_RUN, SYS_CTR[2..0]) + # LOF_CS & LOF[] + # LWD_CS & LWD[] + # HBE_CS & (0, HBE[]) + # HDB_CS & (0, HDB[]) + # HDE_CS & (0, HDE[]) + # HBB_CS & (0, HBB[]) + # HSS_CS & (0, HSS[]) + # HHT_CS & (0, HHT[]) + # VBE_CS & (0, VBE[]) + # VDB_CS & (0, VDB[]) + # VDE_CS & (0, VDE[]) + # VBB_CS & (0, VBB[]) + # VSS_CS & (0, VSS[]) + # VFT_CS & (0, VFT[]) + # VCO_CS & (0, VCO[]) + # VCNTRL_CS & (0, VCNTRL[]) # ACP_VCTR_CS & ACP_VCTR[31..16] # ATARI_HH_CS & ATARI_HH[31..16] # ATARI_VH_CS & ATARI_VH[31..16] # ATARI_HL_CS & ATARI_HL[31..16] # ATARI_VL_CS & ATARI_VL[31..16] - # CCR_CS & (0,CCR[23..16]) + # CCR_CS & (0, CCR[23..16]) # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) - # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") - ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS - # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # VIDEO_PLL_RECONFIG_CS & (VR_BUSY, B"0000", VR_WR, VR_RD, VIDEO_RECONFIG, H"FA") + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # LOF_CS # LWD_CS + # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS - # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); + # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS) & !nFB_OE); + -- high word register access FB_AD[15..0] = lpm_bustri_WORD( ACP_VCTR_CS & ACP_VCTR[15..0] # ATARI_HH_CS & ATARI_HH[15..0] # ATARI_VH_CS & ATARI_VH[15..0] # ATARI_HL_CS & ATARI_HL[15..0] # ATARI_VL_CS & ATARI_VL[15..0] - # CCR_CS & CCR[15..0] - ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + # CCR_CS & CCR[15..0], + (ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); - VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS - # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # LOF_CS # LWD_CS + # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS - # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; + # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS; -- VIDEO AUSGABE SETZEN CLK17M.CLK = CLK33M; CLK17M = !CLK17M; + CLK13M.CLK = CLK25M; CLK13M = !CLK13M; - PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) - # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) - # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 - # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 - # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + + PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz, + # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz, + # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, VGA monitor + # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA monitor + # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00" + # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; + -------------------------------------------------------------- --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK + -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ---------------------------------------------------------------- - HSY_LEN[].CLK = MAIN_CLK; - HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) - # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) - # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 - # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 - # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns + -- HSY_LEN[].CLK = MAIN_CLK; + HSY_LEN[].CLK = PIXEL_CLK; -- check if this is better (mfro) + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 640 pixels + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 320 pixels + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels + # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00" + # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01" + # 16 + (0, VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync pulse length in pixeln = frequenz / = 500ns - MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR - # 4 & !ST_VIDEO & !VDL_VMD2 - # 16 & ST_VIDEO & VDL_VMD2 - # 32 & ST_VIDEO & !VDL_VMD2; + MULF[] = 2 & !ST_VIDEO & VCNTRL2 -- MULTIPLIKATIONS FAKTOR + # 4 & !ST_VIDEO & !VCNTRL2 + # 16 & ST_VIDEO & VCNTRL2 + # 32 & ST_VIDEO & !VCNTRL2; - HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN - # 640 & !VDL_VMD2; + HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN + # 640 & !VCNTRL2; -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; - DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS + DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS + INTER_ZEI.CLK = PIXEL_CLK; - INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC - # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC - DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + INTER_ZEI = DOP_ZEI & VVCNT0 != VDIS_START0 & VVCNT[] != 0 & VHCNT[] < (HDIS_END[] - 1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC + # DOP_ZEI & VVCNT0 == VDIS_START0 & VVCNT[] != 0 & VHCNT[] > (HDIS_END[] - 2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + + DOP_FIFO_CLR.CLK = PIXEL_CLK; + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON - # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON - # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- - HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON - # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- - RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON - # HDIS_END[]+1 & !ACP_VIDEO_ON; -- - HS_START[] = VDL_HSS[] & ACP_VIDEO_ON - # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON - # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + RAND_LINKS[] = HBE[] & ACP_VIDEO_ON + # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 + # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 + # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + HDIS_START[] = HDB[] & ACP_VIDEO_ON + # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- + + HDIS_END[] = HDE[] & ACP_VIDEO_ON + # RAND_LINKS[] + HDIS_LEN[] & !ACP_VIDEO_ON; -- + + RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON + # HDIS_END[] + 1 & !ACP_VIDEO_ON; -- + + HS_START[] = HSS[] & ACP_VIDEO_ON + # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 + # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 + # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + H_TOTAL[] = HHT[] & ACP_VIDEO_ON + # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 + # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 + # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON - # 31 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON - # 32 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON - # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO - # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO - # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON - # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - VS_START[] = VDL_VSS[] & ACP_VIDEO_ON - # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON - # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- ZÄHLER + RAND_OBEN[] = VBE[] & ACP_VIDEO_ON + # 31 & !ACP_VIDEO_ON & ATARI_SYNC + # (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + + VDIS_START[] = VDB[] & ACP_VIDEO_ON + # 32 & !ACP_VIDEO_ON & ATARI_SYNC + # (0, VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + + VDIS_END[] = VDE[] & ACP_VIDEO_ON + # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO + # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO + # (0, VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + + RAND_UNTEN[] = VBB[] & ACP_VIDEO_ON + # VDIS_END[] + 1 & !ACP_VIDEO_ON & ATARI_SYNC + # (0, VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + + VS_START[] = VSS[] & ACP_VIDEO_ON + # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 + # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 + # (0, VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + + V_TOTAL[] = VFT[] & ACP_VIDEO_ON + # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 + # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 + # (0, VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + -- ZÄHLER LAST.CLK = PIXEL_CLK; - LAST = VHCNT[]==(H_TOTAL[]-2); + LAST = VHCNT[] == (H_TOTAL[] - 2); + VHCNT[].CLK = PIXEL_CLK; VHCNT[] = (VHCNT[] + 1) & !LAST; VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; - VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); + VVCNT[] = (VVCNT[] + 1) & (VVCNT[] != V_TOTAL[] - 1); + -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[]= (VDIS_START[] - 1)) & (VVCNT[] < VDIS_END[]); -- 1 ZEILE DAVOR ON OFF + VDTRON.CLK = PIXEL_CLK; - VDTRON = VDTRON & !VDO_OFF - # VDO_ON & VDO_ZL; --- VERZÖGERUNG UND SYNC + VDTRON = VDTRON & !VCO_OFF + # VCO_ON & VCO_ZL; + + -- VERZÖGERUNG UND SYNC HSYNC_START.CLK = PIXEL_CLK; - HSYNC_START = VHCNT[]==HS_START[]-3; + HSYNC_START = VHCNT[] == HS_START[] - 3; + HSYNC_I[].CLK = PIXEL_CLK; - HSYNC_I[] = HSY_LEN[] & HSYNC_START - # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0; + HSYNC_I[] = HSY_LEN[] & HSYNC_START + # (HSYNC_I[] - 1) & !HSYNC_START & HSYNC_I[] != 0; + VSYNC_START.CLK = PIXEL_CLK; VSYNC_START.ENA = LAST; - VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync + VSYNC_START = VVCNT[] == (VS_START[] - 3); -- start am ende der Zeile vor dem vsync + VSYNC_I[].CLK = PIXEL_CLK; VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length - # (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterzählen bis 0 + # (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[] != 0; -- runterzählen bis 0 + VERZ[][].CLK = PIXEL_CLK; VERZ[][1] = VERZ[][0]; VERZ[][2] = VERZ[][1]; @@ -620,18 +711,23 @@ BEGIN VERZ[][8] = VERZ[][7]; VERZ[][9] = VERZ[][8]; VERZ[0][0] = DISP_ON; --- VERZ[1][0] = HSYNC_I[]!=0; - VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0 - # ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR MÖGLICH WENN BEIDE - VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0 - # ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR MÖGLICH WENN BEIDE +-- VERZ[1][0] = HSYNC_I[] != 0; + VERZ[1][0] = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0 + # ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE + VERZ[2][0] = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0 + # ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE + nBLANK.CLK = PIXEL_CLK; nBLANK = VERZ[0][8]; + HSYNC.CLK = PIXEL_CLK; HSYNC = VERZ[1][9]; + VSYNC.CLK = PIXEL_CLK; VSYNC = VERZ[2][9]; + nSYNC = GND; + -- RANDFARBE MACHEN ------------------------------------ RAND[].CLK = PIXEL_CLK; RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25; @@ -643,31 +739,37 @@ BEGIN RAND[6] = RAND[5]; RAND_ON = RAND[6]; ---------------------------------------------------------- + CLR_FIFO.CLK = PIXEL_CLK; CLR_FIFO.ENA = LAST; - CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE LÖSCHEN + CLR_FIFO = VVCNT[] == V_TOTAL[] - 2; -- IN LETZTER ZEILE LÖSCHEN + START_ZEILE.CLK = PIXEL_CLK; START_ZEILE.ENA = LAST; - START_ZEILE = VVCNT[]==0; -- ZEILE 1 + START_ZEILE = VVCNT[] == 0; -- ZEILE 1 + SYNC_PIX.CLK = PIXEL_CLK; - SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX = VHCNT[] == 3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX1.CLK = PIXEL_CLK; - SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX1 = VHCNT[] == 5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX2.CLK = PIXEL_CLK; - SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX2 = VHCNT[] == 7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SUB_PIXEL_CNT[].CLK = PIXEL_CLK; SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX; - SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix + SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix + FIFO_RDE.CLK = PIXEL_CLK; - FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1 - # SUB_PIXEL_CNT[5..0]==1 & COLOR2 - # SUB_PIXEL_CNT[4..0]==1 & COLOR4 - # SUB_PIXEL_CNT[3..0]==1 & COLOR8 - # SUB_PIXEL_CNT[2..0]==1 & COLOR16 - # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON - # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + FIFO_RDE = (SUB_PIXEL_CNT[6..0] == 1 & COLOR1 + # SUB_PIXEL_CNT[5..0] == 1 & COLOR2 + # SUB_PIXEL_CNT[4..0] == 1 & COLOR4 + # SUB_PIXEL_CNT[3..0] == 1 & COLOR8 + # SUB_PIXEL_CNT[2..0] == 1 & COLOR16 + # SUB_PIXEL_CNT[1..0] == 1 & COLOR24) & VDTRON + # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION CLUT_MUX_ADR[].CLK = PIXEL_CLK; + CLUT_MUX_AV[][].CLK = PIXEL_CLK; CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0]; CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][]; diff --git a/FPGA_Quartus_13.1/Video/Video.bdf b/FPGA_Quartus_13.1/Video/Video.bdf index 7030b30..eafbf0e 100644 --- a/FPGA_Quartus_13.1/Video/Video.bdf +++ b/FPGA_Quartus_13.1/Video/Video.bdf @@ -6701,7 +6701,7 @@ applicable agreement for further details. ) ) (symbol - (rect 2072 1176 2232 1320) + (rect 2080 1176 2240 1320) (text "lpm_fifoDZ" (rect 41 2 118 18)(font "Arial" (font_size 10))) (text "inst63" (rect 8 125 38 136)(font "Arial" )) (port @@ -9886,36 +9886,6 @@ applicable agreement for further details. (pt 2248 1344) (bus) ) -(connector - (pt 1968 1424) - (pt 1968 1208) - (bus) -) -(connector - (pt 2248 1208) - (pt 2232 1208) - (bus) -) -(connector - (pt 2248 1344) - (pt 2248 1208) - (bus) -) -(connector - (pt 1872 1424) - (pt 1968 1424) - (bus) -) -(connector - (pt 1968 1424) - (pt 2000 1424) - (bus) -) -(connector - (pt 1968 1208) - (pt 2072 1208) - (bus) -) (connector (pt 2512 1248) (pt 2512 1408) @@ -9944,16 +9914,6 @@ applicable agreement for further details. (pt 1160 1136) (bus) ) -(connector - (text "DOP_FIFO_CLR" (rect 1978 1280 2062 1291)(font "Arial" )) - (pt 2072 1296) - (pt 1992 1296) -) -(connector - (text "PIXEL_CLK" (rect 2002 1256 2063 1267)(font "Arial" )) - (pt 2072 1272) - (pt 1992 1272) -) (connector (text "VDVZ[127..96]" (rect 1450 936 1523 947)(font "Arial" )) (pt 1440 952) @@ -10161,6 +10121,205 @@ applicable agreement for further details. (pt 1640 1384) (pt 1712 1384) ) +(connector + (pt 1888 1120) + (pt 1888 1160) + (bus) +) +(connector + (text "VDM_SEL[3..0]" (rect 1810 1144 1886 1155)(font "Arial" )) + (pt 1888 1160) + (pt 1800 1160) + (bus) +) +(connector + (pt 1944 1296) + (pt 1920 1296) +) +(connector + (text "FIFO_RDE" (rect 1770 1272 1826 1283)(font "Arial" )) + (pt 1760 1288) + (pt 1856 1288) +) +(connector + (text "INTER_ZEI" (rect 1762 1288 1818 1299)(font "Arial" )) + (pt 1752 1304) + (pt 1856 1304) +) +(connector + (text "VIDEO_MOD_TA" (rect 258 1816 347 1827)(font "Arial" )) + (pt 264 1832) + (pt 360 1832) +) +(connector + (text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" )) + (pt 296 2232) + (pt 192 2232) +) +(connector + (text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" )) + (pt 1712 1472) + (pt 1632 1472) +) +(connector + (text "SR_BLITTER_DACK" (rect 778 2560 884 2571)(font "Arial" )) + (pt 904 2576) + (pt 768 2576) +) +(connector + (text "DDRCLK0" (rect 794 2544 847 2555)(font "Arial" )) + (pt 904 2560) + (pt 784 2560) +) +(connector + (text "BLITTER_DACK[4..0]" (rect 1058 2560 1165 2571)(font "Arial" )) + (pt 1176 2576) + (pt 1048 2576) + (bus) +) +(connector + (text "BLITTER_DACK[0]" (rect 778 2952 872 2963)(font "Arial" )) + (pt 776 2968) + (pt 888 2968) +) +(connector + (text "BLITTER_DIN[127..0]" (rect 1042 2944 1149 2955)(font "Arial" )) + (pt 1160 2960) + (pt 1032 2960) + (bus) +) +(connector + (text "BLITTER_SIG" (rect 578 2808 649 2819)(font "Arial" )) + (pt 568 2824) + (pt 680 2824) +) +(connector + (text "BLITTER_WR" (rect 578 2832 649 2843)(font "Arial" )) + (pt 568 2848) + (pt 680 2848) +) +(connector + (text "nFB_CS1" (rect 202 2696 250 2707)(font "Arial" )) + (pt 192 2712) + (pt 296 2712) +) +(connector + (text "nFB_CS2" (rect 202 2720 251 2731)(font "Arial" )) + (pt 192 2736) + (pt 296 2736) +) +(connector + (text "nFB_CS3" (rect 202 2744 251 2755)(font "Arial" )) + (pt 192 2760) + (pt 296 2760) +) +(connector + (text "nFB_WR" (rect 202 2768 248 2779)(font "Arial" )) + (pt 192 2784) + (pt 296 2784) +) +(connector + (text "FB_SIZE0" (rect 202 2792 253 2803)(font "Arial" )) + (pt 192 2808) + (pt 296 2808) +) +(connector + (text "FB_SIZE1" (rect 202 2816 252 2827)(font "Arial" )) + (pt 192 2832) + (pt 296 2832) +) +(connector + (text "nFB_OE" (rect 202 2840 245 2851)(font "Arial" )) + (pt 192 2856) + (pt 296 2856) +) +(connector + (text "MAIN_CLK" (rect 202 2624 259 2635)(font "Arial" )) + (pt 296 2640) + (pt 192 2640) +) +(connector + (text "FB_ALE" (rect 202 2672 244 2683)(font "Arial" )) + (pt 296 2688) + (pt 192 2688) +) +(connector + (text "FB_ADR[31..0]" (rect 202 2648 276 2659)(font "Arial" )) + (pt 192 2664) + (pt 296 2664) + (bus) +) +(connector + (text "nRSTO" (rect 202 2576 240 2587)(font "Arial" )) + (pt 192 2592) + (pt 296 2592) +) +(connector + (text "FB_AD[31..0]" (rect 578 2616 644 2627)(font "Arial" )) + (pt 688 2632) + (pt 568 2632) + (bus) +) +(connector + (text "DDRCLK0" (rect 194 2600 247 2611)(font "Arial" )) + (pt 296 2616) + (pt 184 2616) +) +(connector + (text "BLITTER_TA" (rect 578 2968 646 2979)(font "Arial" )) + (pt 568 2984) + (pt 672 2984) +) +(connector + (text "BLITTER_DACK[4..0]" (rect 178 2872 285 2883)(font "Arial" )) + (pt 296 2888) + (pt 184 2888) + (bus) +) +(connector + (text "VIDEO_RAM_CTR[15..0]" (rect 154 2904 279 2915)(font "Arial" )) + (pt 296 2920) + (pt 144 2920) + (bus) +) +(connector + (text "BLITTER_ON" (rect 202 2928 270 2939)(font "Arial" )) + (pt 296 2944) + (pt 192 2944) +) +(connector + (text "BLITTER_DIN[127..0]" (rect 162 2952 269 2963)(font "Arial" )) + (pt 296 2968) + (pt 152 2968) + (bus) +) +(connector + (text "BLITTER_DOUT[127..0]" (rect 578 2752 697 2763)(font "Arial" )) + (pt 712 2768) + (pt 568 2768) + (bus) +) +(connector + (text "BLITTER_ADR[31..0]" (rect 578 2784 684 2795)(font "Arial" )) + (pt 704 2800) + (pt 568 2800) + (bus) +) +(connector + (text "BLITTER_RUN" (rect 578 2720 653 2731)(font "Arial" )) + (pt 672 2736) + (pt 568 2736) +) +(connector + (text "SR_BLITTER_DACK" (rect 170 2984 276 2995)(font "Arial" )) + (pt 296 3000) + (pt 160 3000) +) +(connector + (text "DOP_FIFO_CLR" (rect 1978 1296 2062 1307)(font "Arial" )) + (pt 2064 1312) + (pt 1992 1312) +) (connector (text "nFB_BURST" (rect 1570 1896 1634 1907)(font "Arial" )) (pt 1560 1912) @@ -10347,53 +10506,9 @@ applicable agreement for further details. (pt 1536 2544) ) (connector - (pt 1888 1120) - (pt 1888 1160) - (bus) -) -(connector - (text "VDM_SEL[3..0]" (rect 1810 1144 1886 1155)(font "Arial" )) - (pt 1888 1160) - (pt 1800 1160) - (bus) -) -(connector - (pt 1608 1432) - (pt 1608 1232) -) -(connector - (pt 1600 1432) - (pt 1608 1432) -) -(connector - (pt 1608 1432) - (pt 1712 1432) -) -(connector - (pt 1608 1232) - (pt 2072 1232) -) -(connector - (pt 2072 1248) - (pt 1944 1248) -) -(connector - (pt 1944 1248) - (pt 1944 1296) -) -(connector - (pt 1944 1296) - (pt 1920 1296) -) -(connector - (text "FIFO_RDE" (rect 1770 1272 1826 1283)(font "Arial" )) - (pt 1760 1288) - (pt 1856 1288) -) -(connector - (text "INTER_ZEI" (rect 1762 1288 1818 1299)(font "Arial" )) - (pt 1752 1304) - (pt 1856 1304) + (text "CLK_VIDEO" (rect 1570 2144 1633 2155)(font "Arial" )) + (pt 1512 2160) + (pt 1664 2160) ) (connector (text "CLK33M" (rect 1586 2168 1630 2179)(font "Arial" )) @@ -10405,16 +10520,6 @@ applicable agreement for further details. (pt 1512 2208) (pt 1664 2208) ) -(connector - (text "CLK_VIDEO" (rect 1570 2144 1633 2155)(font "Arial" )) - (pt 1512 2160) - (pt 1664 2160) -) -(connector - (text "VIDEO_MOD_TA" (rect 258 1816 347 1827)(font "Arial" )) - (pt 264 1832) - (pt 360 1832) -) (connector (text "COLOR8" (rect 2026 1912 2073 1923)(font "Arial" )) (pt 2016 1928) @@ -10447,13 +10552,18 @@ applicable agreement for further details. ) (connector (text "VR_WR" (rect 2026 1784 2067 1795)(font "Arial" )) - (pt 2016 1800) (pt 2112 1800) + (pt 2016 1800) ) (connector (text "VR_RD" (rect 2026 1800 2064 1811)(font "Arial" )) - (pt 2016 1816) (pt 2112 1816) + (pt 2016 1816) +) +(connector + (text "VR_BUSY" (rect 1578 2104 1632 2115)(font "Arial" )) + (pt 1512 2120) + (pt 1664 2120) ) (connector (text "VR_D[8..0]" (rect 1570 2120 1624 2131)(font "Arial" )) @@ -10461,179 +10571,77 @@ applicable agreement for further details. (pt 1664 2136) (bus) ) -(connector - (text "VR_BUSY" (rect 1578 2104 1632 2115)(font "Arial" )) - (pt 1512 2120) - (pt 1664 2120) -) -(connector - (text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" )) - (pt 296 2232) - (pt 192 2232) -) (connector (text "CLR_FIFO" (rect 2026 1752 2081 1763)(font "Arial" )) (pt 2016 1768) (pt 2112 1768) ) (connector - (text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" )) - (pt 1712 1472) - (pt 1632 1472) -) -(connector - (text "SR_BLITTER_DACK" (rect 778 2560 884 2571)(font "Arial" )) - (pt 904 2576) - (pt 768 2576) -) -(connector - (text "DDRCLK0" (rect 794 2544 847 2555)(font "Arial" )) - (pt 904 2560) - (pt 784 2560) -) -(connector - (text "BLITTER_DACK[4..0]" (rect 1058 2560 1165 2571)(font "Arial" )) - (pt 1176 2576) - (pt 1048 2576) + (pt 1968 1424) + (pt 1968 1208) (bus) ) (connector - (text "BLITTER_DACK[0]" (rect 778 2952 872 2963)(font "Arial" )) - (pt 776 2968) - (pt 888 2968) -) -(connector - (text "BLITTER_DIN[127..0]" (rect 1042 2944 1149 2955)(font "Arial" )) - (pt 1160 2960) - (pt 1032 2960) + (pt 2248 1208) + (pt 2240 1208) (bus) ) (connector - (text "BLITTER_SIG" (rect 578 2808 649 2819)(font "Arial" )) - (pt 568 2824) - (pt 680 2824) -) -(connector - (text "BLITTER_WR" (rect 578 2832 649 2843)(font "Arial" )) - (pt 568 2848) - (pt 680 2848) -) -(connector - (text "nFB_CS1" (rect 202 2696 250 2707)(font "Arial" )) - (pt 192 2712) - (pt 296 2712) -) -(connector - (text "nFB_CS2" (rect 202 2720 251 2731)(font "Arial" )) - (pt 192 2736) - (pt 296 2736) -) -(connector - (text "nFB_CS3" (rect 202 2744 251 2755)(font "Arial" )) - (pt 192 2760) - (pt 296 2760) -) -(connector - (text "nFB_WR" (rect 202 2768 248 2779)(font "Arial" )) - (pt 192 2784) - (pt 296 2784) -) -(connector - (text "FB_SIZE0" (rect 202 2792 253 2803)(font "Arial" )) - (pt 192 2808) - (pt 296 2808) -) -(connector - (text "FB_SIZE1" (rect 202 2816 252 2827)(font "Arial" )) - (pt 192 2832) - (pt 296 2832) -) -(connector - (text "nFB_OE" (rect 202 2840 245 2851)(font "Arial" )) - (pt 192 2856) - (pt 296 2856) -) -(connector - (text "MAIN_CLK" (rect 202 2624 259 2635)(font "Arial" )) - (pt 296 2640) - (pt 192 2640) -) -(connector - (text "FB_ALE" (rect 202 2672 244 2683)(font "Arial" )) - (pt 296 2688) - (pt 192 2688) -) -(connector - (text "FB_ADR[31..0]" (rect 202 2648 276 2659)(font "Arial" )) - (pt 192 2664) - (pt 296 2664) + (pt 2248 1344) + (pt 2248 1208) (bus) ) (connector - (text "nRSTO" (rect 202 2576 240 2587)(font "Arial" )) - (pt 192 2592) - (pt 296 2592) + (pt 1608 1432) + (pt 1608 1232) ) (connector - (text "FB_AD[31..0]" (rect 578 2616 644 2627)(font "Arial" )) - (pt 688 2632) - (pt 568 2632) + (pt 1944 1296) + (pt 1944 1248) +) +(connector + (pt 2064 1312) + (pt 2064 1296) +) +(connector + (pt 1872 1424) + (pt 1968 1424) (bus) ) (connector - (text "DDRCLK0" (rect 194 2600 247 2611)(font "Arial" )) - (pt 296 2616) - (pt 184 2616) -) -(connector - (text "BLITTER_TA" (rect 578 2968 646 2979)(font "Arial" )) - (pt 568 2984) - (pt 672 2984) -) -(connector - (text "BLITTER_DACK[4..0]" (rect 178 2872 285 2883)(font "Arial" )) - (pt 296 2888) - (pt 184 2888) + (pt 1968 1424) + (pt 2000 1424) (bus) ) (connector - (text "VIDEO_RAM_CTR[15..0]" (rect 154 2904 279 2915)(font "Arial" )) - (pt 296 2920) - (pt 144 2920) + (pt 1600 1432) + (pt 1608 1432) +) +(connector + (pt 1608 1432) + (pt 1712 1432) +) +(connector + (pt 1968 1208) + (pt 2080 1208) (bus) ) (connector - (text "BLITTER_ON" (rect 202 2928 270 2939)(font "Arial" )) - (pt 296 2944) - (pt 192 2944) + (pt 1608 1232) + (pt 2080 1232) ) (connector - (text "BLITTER_DIN[127..0]" (rect 162 2952 269 2963)(font "Arial" )) - (pt 296 2968) - (pt 152 2968) - (bus) + (pt 1944 1248) + (pt 2080 1248) ) (connector - (text "BLITTER_DOUT[127..0]" (rect 578 2752 697 2763)(font "Arial" )) - (pt 712 2768) - (pt 568 2768) - (bus) + (text "PIXEL_CLK" (rect 2010 1256 2071 1267)(font "Arial" )) + (pt 2000 1272) + (pt 2080 1272) ) (connector - (text "BLITTER_ADR[31..0]" (rect 578 2784 684 2795)(font "Arial" )) - (pt 704 2800) - (pt 568 2800) - (bus) -) -(connector - (text "BLITTER_RUN" (rect 578 2720 653 2731)(font "Arial" )) - (pt 672 2736) - (pt 568 2736) -) -(connector - (text "SR_BLITTER_DACK" (rect 170 2984 276 2995)(font "Arial" )) - (pt 296 3000) - (pt 160 3000) + (pt 2064 1296) + (pt 2080 1296) ) (junction (pt 2984 1688)) (junction (pt 792 1192)) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index e8a559d..1d05824 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -827,4 +827,5 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc.groups b/FPGA_Quartus_13.1/firebee1.sdc.groups new file mode 100644 index 0000000..97bcc70 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.sdc.groups @@ -0,0 +1,179 @@ +#--------------------------------------------------------------# +# # +# Synopsis design constraints for the Firebee project # +# # +# This file is part of the Firebee ACP project. # +# http://www.experiment-s.de # +# # +# Description: # +# timing constraints for the Firebee VHDL config # +# # +# # +# # +# To Do: # +# - # +# # +# Author(s): # +# Markus Fröschle, mfro@mubf.de # +# # +#--------------------------------------------------------------# +# # +# Copyright (C) 2015 Markus Fröschle & the ACP project # +# # +# This source file may be used and distributed without # +# restriction provided that this copyright statement is not # +# removed from the file and that any derivative work contains # +# the original copyright notice and the associated disclaimer. # +# # +# This source file is free software; you can redistribute it # +# and/or modify it under the terms of the GNU Lesser General # +# Public License as published by the Free Software Foundation; # +# either version 2.1 of the License, or (at your option) any # +# later version. # +# # +# This source is distributed in the hope that it will be # +# useful, but WITHOUT ANY WARRANTY; without even the implied # +# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR # +# PURPOSE. See the GNU Lesser General Public License for more # +# details. # +# # +# You should have received a copy of the GNU Lesser General # +# Public License along with this source; if not, download it # +# from http://www.gnu.org/licenses/lgpl.html # +# # +################################################################ + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] + +# Clocks used: +# MAIN_CLK 33MHz +# +# PLL1: i_mfp_acia_clk_pll +# input: MAIN_CLK +# c0: 500 kHz +# c1: 2.4576 MHz +# c2: 24.576 MHz +# +# PLL2: i_ddr_clock_pll +# input: MAIN_CLK +# c0: 132 MHz 240° +# c1: 132 MHz 0° +# c2: 132 MHz 180° +# c3: 132 MHz 105° +# c4: 66 MHz 270° +# +# PLL3: i_atari_clk_pll +# input: MAIN_CLK +# c0: 2 MHz +# c1: 16 MHz +# c2: 25 MHz +# c3: 48 MHz +# +# PLL4_ i_video_clk_pll +# input: USB_CLK (48 MHz, PLL3 c3) +# c0: 96 MHz, programmable in 1MHz steps +# +#************************************************************** +# Create Generated Clock +#************************************************************** + +derive_pll_clocks + +# PIXEL_CLK is either +# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO +# where CLK13M is half of CLK25M, +# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable +# clock of i_video_clk_pll +# + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.0 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.0 +derive_clock_uncertainty + + +#************************************************************** +# Set Input Delay +#************************************************************** + +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_inputs] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outputs] + + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] \ + -group [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ + -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ + -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ + -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ + -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ + -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ + -group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] +set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] +set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + +#************************************************************** +# Set Minimum Delay +#************************************************************** + +#************************************************************** +# Set Input Transition +#************************************************************** From f94b5f265ee60de858e8ccd469fc61144b3df883 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 9 Jan 2016 21:36:02 +0000 Subject: [PATCH 037/127] remove delay chains --- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 63 +- FPGA_Quartus_13.1/Video/Video.bdf | 1204 +++++++++-------- FPGA_Quartus_13.1/firebee1.bdf | 462 +++---- 3 files changed, 874 insertions(+), 855 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 802f797..e49d652 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -50,7 +50,7 @@ SUBDESIGN video_mod_mux_clutctr BLITTER_ON : OUTPUT; VIDEO_RAM_CTR[15..0] : OUTPUT; VIDEO_MOD_TA : OUTPUT; - CCR[23..0] : OUTPUT; + BORDER_COLOR[23..0] : OUTPUT; CCSEL[2..0] : OUTPUT; ACP_CLUT_WR[3..0] : OUTPUT; INTER_ZEI : OUTPUT; @@ -88,8 +88,8 @@ VARIABLE CLUT_MUX_AV[1..0][3..0] :DFF; ACP_VCTR_CS :NODE; ACP_VCTR[31..0] :DFFE; - CCR_CS :NODE; - CCR[23..0] :DFFE; + BORDER_COLOR_CS :NODE; + BORDER_COLOR[23..0] :DFFE; ACP_VIDEO_ON :NODE; SYS_CTR[6..0] :DFFE; SYS_CTR_CS :NODE; @@ -267,6 +267,7 @@ BEGIN ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; + -- ATARI MODUS ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG @@ -311,6 +312,7 @@ BEGIN VR_WR.CLK = MAIN_CLK; VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; + VR_DOUT[].CLK = MAIN_CLK; VR_DOUT[].ENA = !VR_BUSY; VR_DOUT[] = VR_D[]; @@ -349,12 +351,12 @@ BEGIN -- DIVERSE (VIDEO)-REGISTER ---------------------------- -- RANDFARBE - CCR[].CLK = MAIN_CLK; - CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 - CCR[] = FB_AD[23..0]; - CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; - CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; - CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; + BORDER_COLOR[].CLK = MAIN_CLK; + BORDER_COLOR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 + BORDER_COLOR[] = FB_AD[23..0]; + BORDER_COLOR[23..16].ENA = BORDER_COLOR_CS & FB_B1 & !nFB_WR; + BORDER_COLOR[15..8].ENA = BORDER_COLOR_CS & FB_B2 & !nFB_WR; + BORDER_COLOR[7..0].ENA = BORDER_COLOR_CS & FB_B3 & !nFB_WR; -- System Config Register -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi @@ -523,10 +525,10 @@ BEGIN # ATARI_VH_CS & ATARI_VH[31..16] # ATARI_HL_CS & ATARI_HL[31..16] # ATARI_VL_CS & ATARI_VL[31..16] - # CCR_CS & (0, CCR[23..16]) + # BORDER_COLOR_CS & (0, BORDER_COLOR[23..16]) # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) # VIDEO_PLL_RECONFIG_CS & (VR_BUSY, B"0000", VR_WR, VR_RD, VIDEO_RECONFIG, H"FA") - ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # LOF_CS # LWD_CS + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # BORDER_COLOR_CS # SYS_CTR_CS # LOF_CS # LWD_CS # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS) & !nFB_OE); @@ -538,8 +540,8 @@ BEGIN # ATARI_VH_CS & ATARI_VH[15..0] # ATARI_HL_CS & ATARI_HL[15..0] # ATARI_VL_CS & ATARI_VL[15..0] - # CCR_CS & CCR[15..0], - (ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + # BORDER_COLOR_CS & BORDER_COLOR[15..0], + (ACP_VCTR_CS # BORDER_COLOR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # LOF_CS # LWD_CS # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS @@ -566,10 +568,10 @@ BEGIN ---------------------------------------------------------------- -- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[].CLK = PIXEL_CLK; -- check if this is better (mfro) - HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels - # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 640 pixels - # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 320 pixels - # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz, RGB + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz, VGA + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, RGB + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00" # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01" # 16 + (0, VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync pulse length in pixeln = frequenz / = 500ns @@ -580,12 +582,12 @@ BEGIN # 32 & ST_VIDEO & !VCNTRL2; - HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN + HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN # 640 & !VCNTRL2; -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; - DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS + DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS INTER_ZEI.CLK = PIXEL_CLK; INTER_ZEI = DOP_ZEI & VVCNT0 != VDIS_START0 & VVCNT[] != 0 & VHCNT[] < (HDIS_END[] - 1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC @@ -650,14 +652,16 @@ BEGIN VHCNT[].CLK = PIXEL_CLK; VHCNT[] = (VHCNT[] + 1) & !LAST; + VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; VVCNT[] = (VVCNT[] + 1) & (VVCNT[] != V_TOTAL[] - 1); -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; - DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[] RAND_OBEN[] - 1) & (VVCNT[] < RAND_UNTEN[] - 1); -- 1 ZEILE DAVOR ON OFF DPO_ZL.ENA = LAST; -- AM ZEILENENDE ÃœBERNEHMEN + DPO_ON.CLK = PIXEL_CLK; DPO_ON = VHCNT[] == RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING @@ -670,7 +674,7 @@ BEGIN -- DATENTRANSFER ON OFF VCO_ON.CLK = PIXEL_CLK; - VCO_ON = VHCNT[] == (HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING + VCO_ON = VHCNT[] == (HDIS_START[] - 1); -- BESSER EINZELN WEGEN TIMING VCO_OFF.CLK = PIXEL_CLK; VCO_OFF = VHCNT[] == HDIS_END[]; @@ -718,14 +722,18 @@ BEGIN # ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE nBLANK.CLK = PIXEL_CLK; - nBLANK = VERZ[0][8]; + -- nBLANK = VERZ[0][8]; + nBLANK = DISP_ON; HSYNC.CLK = PIXEL_CLK; - HSYNC = VERZ[1][9]; - + -- HSYNC = VERZ[1][9]; + HSYNC = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0 + # ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE + VSYNC.CLK = PIXEL_CLK; - VSYNC = VERZ[2][9]; - + -- VSYNC = VERZ[2][9]; + VSYNC = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0 + # ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE nSYNC = GND; -- RANDFARBE MACHEN ------------------------------------ @@ -737,7 +745,8 @@ BEGIN RAND[4] = RAND[3]; RAND[5] = RAND[4]; RAND[6] = RAND[5]; - RAND_ON = RAND[6]; + -- RAND_ON = RAND[6]; + RAND_ON = DISP_ON & !VDTRON & ACP_VCTR25; ---------------------------------------------------------- CLR_FIFO.CLK = PIXEL_CLK; diff --git a/FPGA_Quartus_13.1/Video/Video.bdf b/FPGA_Quartus_13.1/Video/Video.bdf index eafbf0e..83f2f08 100644 --- a/FPGA_Quartus_13.1/Video/Video.bdf +++ b/FPGA_Quartus_13.1/Video/Video.bdf @@ -6758,254 +6758,6 @@ applicable agreement for further details. (line (pt 22 96)(pt 16 102)) ) ) -(block - (rect 1664 1664 2016 2600) - (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 183 18)(font "Arial" (font_size 8))) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 160 933)(font "Arial" )) (block_io "nRSTO" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_OE" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "CLK33M" (input)) - (block_io "CLK25M" (input)) - (block_io "BLITTER_RUN" (input)) - (block_io "CLK_VIDEO" (input)) - (block_io "VR_D[8..0]" (input)) - (block_io "VR_BUSY" (input)) - (block_io "COLOR8" (output)) - (block_io "ACP_CLUT_RD" (output)) - (block_io "COLOR1" (output)) - (block_io "FALCON_CLUT_RDH" (output)) - (block_io "FALCON_CLUT_RDL" (output)) - (block_io "FALCON_CLUT_WR[3..0]" (output)) - (block_io "ST_CLUT_RD" (output)) - (block_io "ST_CLUT_WR[1..0]" (output)) - (block_io "CLUT_MUX_ADR[3..0]" (output)) - (block_io "HSYNC" (output)) - (block_io "VSYNC" (output)) - (block_io "nBLANK" (output)) - (block_io "nSYNC" (output)) - (block_io "nPD_VGA" (output)) - (block_io "FIFO_RDE" (output)) - (block_io "COLOR2" (output)) - (block_io "COLOR4" (output)) - (block_io "PIXEL_CLK" (output)) - (block_io "CLUT_OFF[3..0]" (output)) - (block_io "BLITTER_ON" (output)) - (block_io "VIDEO_RAM_CTR[15..0]" (output)) - (block_io "VIDEO_MOD_TA" (output)) - (block_io "CCR[23..0]" (output)) - (block_io "CCSEL[2..0]" (output)) - (block_io "ACP_CLUT_WR[3..0]" (output)) - (block_io "INTER_ZEI" (output)) - (block_io "DOP_FIFO_CLR" (output)) - (block_io "VIDEO_RECONFIG" (output)) - (block_io "VR_WR" (output)) - (block_io "VR_RD" (output)) - (block_io "CLR_FIFO" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (mapper - (pt 352 72) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 520) - (bidir) - ) - (mapper - (pt 0 544) - (bidir) - ) - (mapper - (pt 0 880) - (bidir) - ) - (mapper - (pt 352 600) - (bidir) - ) - (mapper - (pt 352 624) - (bidir) - ) - (mapper - (pt 352 648) - (bidir) - ) - (mapper - (pt 352 672) - (bidir) - ) - (mapper - (pt 352 696) - (bidir) - ) - (mapper - (pt 352 720) - (bidir) - ) - (mapper - (pt 352 840) - (bidir) - ) - (mapper - (pt 352 472) - (bidir) - ) - (mapper - (pt 352 448) - (bidir) - ) - (mapper - (pt 352 528) - (bidir) - ) - (mapper - (pt 352 320) - (bidir) - ) - (mapper - (pt 352 576) - (bidir) - ) - (mapper - (pt 352 400) - (bidir) - ) - (mapper - (pt 352 376) - (bidir) - ) - (mapper - (pt 352 352) - (bidir) - ) - (mapper - (pt 352 504) - (bidir) - ) - (mapper - (pt 352 296) - (bidir) - ) - (mapper - (pt 352 424) - (bidir) - ) - (mapper - (pt 352 552) - (bidir) - ) - (mapper - (pt 352 752) - (bidir) - ) - (mapper - (pt 352 776) - (bidir) - ) - (mapper - (pt 352 872) - (bidir) - ) - (mapper - (pt 0 496) - (bidir) - ) - (mapper - (pt 352 88) - (bidir) - ) - (mapper - (pt 352 264) - (bidir) - ) - (mapper - (pt 352 248) - (bidir) - ) - (mapper - (pt 352 232) - (bidir) - ) - (mapper - (pt 352 216) - (bidir) - ) - (mapper - (pt 352 136) - (bidir) - ) - (mapper - (pt 352 40) - (bidir) - ) - (mapper - (pt 352 152) - (bidir) - ) - (mapper - (pt 0 472) - (bidir) - ) - (mapper - (pt 0 456) - (bidir) - ) - (mapper - (pt 352 104) - (bidir) - ) -) (block (rect 296 1872 560 2536) (text "DDR_CTR" (rect 5 5 66 18)(font "Arial" (font_size 8))) (text "DDR_CTR" (rect 5 650 59 661)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) @@ -7327,6 +7079,254 @@ applicable agreement for further details. (bidir) ) ) +(block + (rect 1664 1664 2016 2600) + (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 5 183 18)(font "Arial" (font_size 8))) (text "VIDEO_MOD_MUX_CLUTCTR" (rect 5 922 160 933)(font "Arial" )) (block_io "nRSTO" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nFB_CS3" (input)) + (block_io "nFB_WR" (input)) + (block_io "nFB_OE" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nFB_BURST" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "CLK33M" (input)) + (block_io "CLK25M" (input)) + (block_io "BLITTER_RUN" (input)) + (block_io "CLK_VIDEO" (input)) + (block_io "VR_D[8..0]" (input)) + (block_io "VR_BUSY" (input)) + (block_io "COLOR8" (output)) + (block_io "ACP_CLUT_RD" (output)) + (block_io "COLOR1" (output)) + (block_io "FALCON_CLUT_RDH" (output)) + (block_io "FALCON_CLUT_RDL" (output)) + (block_io "FALCON_CLUT_WR[3..0]" (output)) + (block_io "ST_CLUT_RD" (output)) + (block_io "ST_CLUT_WR[1..0]" (output)) + (block_io "CLUT_MUX_ADR[3..0]" (output)) + (block_io "HSYNC" (output)) + (block_io "VSYNC" (output)) + (block_io "nBLANK" (output)) + (block_io "nSYNC" (output)) + (block_io "nPD_VGA" (output)) + (block_io "FIFO_RDE" (output)) + (block_io "COLOR2" (output)) + (block_io "COLOR4" (output)) + (block_io "PIXEL_CLK" (output)) + (block_io "CLUT_OFF[3..0]" (output)) + (block_io "BLITTER_ON" (output)) + (block_io "VIDEO_RAM_CTR[15..0]" (output)) + (block_io "VIDEO_MOD_TA" (output)) + (block_io "BORDER_COLOR[23..0]" (output)) + (block_io "CCSEL[2..0]" (output)) + (block_io "ACP_CLUT_WR[3..0]" (output)) + (block_io "INTER_ZEI" (output)) + (block_io "DOP_FIFO_CLR" (output)) + (block_io "VIDEO_RECONFIG" (output)) + (block_io "VR_WR" (output)) + (block_io "VR_RD" (output)) + (block_io "CLR_FIFO" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (mapper + (pt 352 72) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 520) + (bidir) + ) + (mapper + (pt 0 544) + (bidir) + ) + (mapper + (pt 0 880) + (bidir) + ) + (mapper + (pt 352 600) + (bidir) + ) + (mapper + (pt 352 624) + (bidir) + ) + (mapper + (pt 352 648) + (bidir) + ) + (mapper + (pt 352 672) + (bidir) + ) + (mapper + (pt 352 696) + (bidir) + ) + (mapper + (pt 352 720) + (bidir) + ) + (mapper + (pt 352 840) + (bidir) + ) + (mapper + (pt 352 472) + (bidir) + ) + (mapper + (pt 352 448) + (bidir) + ) + (mapper + (pt 352 528) + (bidir) + ) + (mapper + (pt 352 320) + (bidir) + ) + (mapper + (pt 352 576) + (bidir) + ) + (mapper + (pt 352 400) + (bidir) + ) + (mapper + (pt 352 376) + (bidir) + ) + (mapper + (pt 352 352) + (bidir) + ) + (mapper + (pt 352 504) + (bidir) + ) + (mapper + (pt 352 296) + (bidir) + ) + (mapper + (pt 352 424) + (bidir) + ) + (mapper + (pt 352 552) + (bidir) + ) + (mapper + (pt 352 752) + (bidir) + ) + (mapper + (pt 352 776) + (bidir) + ) + (mapper + (pt 352 872) + (bidir) + ) + (mapper + (pt 0 496) + (bidir) + ) + (mapper + (pt 352 88) + (bidir) + ) + (mapper + (pt 352 264) + (bidir) + ) + (mapper + (pt 352 248) + (bidir) + ) + (mapper + (pt 352 232) + (bidir) + ) + (mapper + (pt 352 216) + (bidir) + ) + (mapper + (pt 352 136) + (bidir) + ) + (mapper + (pt 352 40) + (bidir) + ) + (mapper + (pt 352 152) + (bidir) + ) + (mapper + (pt 0 472) + (bidir) + ) + (mapper + (pt 0 456) + (bidir) + ) + (mapper + (pt 352 104) + (bidir) + ) +) (connector (text "CLUT_ADR0" (rect 2786 1272 2852 1283)(font "Arial" )) (pt 2776 1288) @@ -8025,122 +8025,6 @@ applicable agreement for further details. (pt 2904 2896) (bus) ) -(connector - (text "FB_AD[31..0]" (rect 570 1904 636 1915)(font "Arial" )) - (pt 680 1920) - (pt 560 1920) - (bus) -) -(connector - (text "nFB_CS1" (rect 202 2040 250 2051)(font "Arial" )) - (pt 192 2056) - (pt 296 2056) -) -(connector - (text "nFB_CS2" (rect 202 2064 251 2075)(font "Arial" )) - (pt 192 2080) - (pt 296 2080) -) -(connector - (text "nFB_CS3" (rect 202 2088 251 2099)(font "Arial" )) - (pt 192 2104) - (pt 296 2104) -) -(connector - (text "nFB_WR" (rect 202 2112 248 2123)(font "Arial" )) - (pt 192 2128) - (pt 296 2128) -) -(connector - (text "FB_SIZE0" (rect 202 2136 253 2147)(font "Arial" )) - (pt 192 2152) - (pt 296 2152) -) -(connector - (text "FB_SIZE1" (rect 202 2160 252 2171)(font "Arial" )) - (pt 192 2176) - (pt 296 2176) -) -(connector - (text "nFB_OE" (rect 202 2184 245 2195)(font "Arial" )) - (pt 192 2200) - (pt 296 2200) -) -(connector - (text "VA[12..0]" (rect 570 2168 616 2179)(font "Arial" )) - (pt 632 2184) - (pt 560 2184) - (bus) -) -(connector - (text "nVWE" (rect 570 2192 603 2203)(font "Arial" )) - (pt 632 2208) - (pt 560 2208) -) -(connector - (text "nVCAS" (rect 570 2216 607 2227)(font "Arial" )) - (pt 632 2232) - (pt 560 2232) -) -(connector - (text "nVRAS" (rect 570 2240 607 2251)(font "Arial" )) - (pt 632 2256) - (pt 560 2256) -) -(connector - (text "nVCS" (rect 570 2264 600 2275)(font "Arial" )) - (pt 632 2280) - (pt 560 2280) -) -(connector - (text "VCKE" (rect 570 2288 601 2299)(font "Arial" )) - (pt 632 2304) - (pt 560 2304) -) -(connector - (text "MAIN_CLK" (rect 202 1944 259 1955)(font "Arial" )) - (pt 296 1960) - (pt 192 1960) -) -(connector - (text "FB_ALE" (rect 202 2016 244 2027)(font "Arial" )) - (pt 296 2032) - (pt 192 2032) -) -(connector - (text "FB_LE[3..0]" (rect 570 1976 629 1987)(font "Arial" )) - (pt 560 1992) - (pt 680 1992) - (bus) -) -(connector - (text "FB_VDOE[3..0]" (rect 570 2000 646 2011)(font "Arial" )) - (pt 560 2016) - (pt 680 2016) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 210 1968 299 1979)(font "Arial" )) - (pt 200 1984) - (pt 296 1984) -) -(connector - (text "FB_ADR[31..0]" (rect 202 1992 276 2003)(font "Arial" )) - (pt 192 2008) - (pt 296 2008) - (bus) -) -(connector - (text "nRSTO" (rect 202 1896 240 1907)(font "Arial" )) - (pt 192 1912) - (pt 296 1912) -) -(connector - (text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 303 2251)(font "Arial" )) - (pt 296 2256) - (pt 168 2256) - (bus) -) (connector (pt 792 1648) (pt 920 1648) @@ -8321,53 +8205,11 @@ applicable agreement for further details. (pt 1160 1672) (bus) ) -(connector - (text "BLITTER_ADR[31..0]" (rect 194 2288 300 2299)(font "Arial" )) - (pt 184 2304) - (pt 296 2304) - (bus) -) -(connector - (text "BLITTER_SIG" (rect 194 2312 265 2323)(font "Arial" )) - (pt 184 2328) - (pt 296 2328) -) -(connector - (text "BLITTER_WR" (rect 194 2336 265 2347)(font "Arial" )) - (pt 184 2352) - (pt 296 2352) -) -(connector - (text "SR_FIFO_WRE" (rect 570 2072 650 2083)(font "Arial" )) - (pt 648 2088) - (pt 560 2088) -) -(connector - (text "SR_DDR_FB" (rect 570 2312 637 2323)(font "Arial" )) - (pt 640 2328) - (pt 560 2328) -) (connector (text "SR_FIFO_WRE" (rect 842 2280 922 2291)(font "Arial" )) (pt 920 2296) (pt 832 2296) ) -(connector - (text "SR_DDR_WR" (rect 570 2024 641 2035)(font "Arial" )) - (pt 664 2040) - (pt 560 2040) -) -(connector - (text "SR_VDMP[7..0]" (rect 570 2336 647 2347)(font "Arial" )) - (pt 560 2352) - (pt 664 2352) - (bus) -) -(connector - (text "SR_DDRWR_D_SEL" (rect 570 2360 676 2371)(font "Arial" )) - (pt 560 2376) - (pt 664 2376) -) (connector (text "VDVZ[127..0]" (rect 810 2920 876 2931)(font "Arial" )) (pt 800 2936) @@ -8410,16 +8252,6 @@ applicable agreement for further details. (pt 1064 2296) (pt 1144 2296) ) -(connector - (text "DDRCLK0" (rect 194 1920 247 1931)(font "Arial" )) - (pt 296 1936) - (pt 184 1936) -) -(connector - (text "VIDEO_DDR_TA" (rect 570 2488 657 2499)(font "Arial" )) - (pt 560 2504) - (pt 664 2504) -) (connector (pt 432 1808) (pt 472 1808) @@ -8508,11 +8340,6 @@ applicable agreement for further details. (pt 1192 1288) (bus) ) -(connector - (text "SR_BLITTER_DACK" (rect 570 2464 676 2475)(font "Arial" )) - (pt 664 2480) - (pt 560 2480) -) (connector (text "DDRCLK0" (rect 1114 1528 1167 1539)(font "Arial" )) (pt 1104 1544) @@ -8549,11 +8376,6 @@ applicable agreement for further details. (pt 1168 2192) (bus) ) -(connector - (text "CLK33M" (rect 218 2432 262 2443)(font "Arial" )) - (pt 208 2448) - (pt 296 2448) -) (connector (text "FIFO_D[127..0]" (rect 2170 1416 2246 1427)(font "Arial" )) (pt 2168 1432) @@ -8781,12 +8603,6 @@ applicable agreement for further details. (pt 1304 2688) (bus) ) -(connector - (text "BA[1..0]" (rect 570 2120 610 2131)(font "Arial" )) - (pt 632 2136) - (pt 560 2136) - (bus) -) (connector (text "DDRWR_D_SEL0" (rect 1066 2768 1156 2779)(font "Arial" )) (pt 1056 2784) @@ -8808,11 +8624,6 @@ applicable agreement for further details. (pt 888 2784) (pt 992 2784) ) -(connector - (text "DDRWR_D_SEL1" (rect 570 2392 659 2403)(font "Arial" )) - (pt 656 2408) - (pt 560 2408) -) (connector (text "VDOUT_OE" (rect 1386 2328 1448 2339)(font "Arial" )) (pt 1376 2344) @@ -9007,72 +8818,12 @@ applicable agreement for further details. (pt 3352 2768) (bus) ) -(connector - (text "CCR[23..0]" (rect 3954 2720 4009 2731)(font "Arial" )) - (pt 4024 2736) - (pt 3944 2736) - (bus) -) (connector (text "CCS[23..0]" (rect 3362 2840 3416 2851)(font "Arial" )) (pt 3432 2856) (pt 3352 2856) (bus) ) -(connector - (text "CC16[23..0]" (rect 3954 2752 4013 2763)(font "Arial" )) - (pt 4024 2768) - (pt 3944 2768) - (bus) -) -(connector - (text "VR[7..0],VG[7..0],VB[7..0]" (rect 4522 2776 4648 2787)(font "Arial" )) - (pt 4512 2792) - (pt 4664 2792) - (bus) -) -(connector - (pt 4240 2808) - (pt 4280 2808) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 4202 2808 4263 2819)(font "Arial" )) - (pt 4192 2824) - (pt 4280 2824) -) -(connector - (pt 4240 2792) - (pt 4280 2792) - (bus) -) -(connector - (pt 4240 2800) - (pt 4176 2800) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 3946 2848 4007 2859)(font "Arial" )) - (pt 3936 2864) - (pt 4024 2864) -) -(connector - (pt 4104 2888) - (pt 4104 2920) - (bus) -) -(connector - (text "CCSEL[2..0]" (rect 4010 2904 4071 2915)(font "Arial" )) - (pt 4104 2920) - (pt 4000 2920) - (bus) -) -(connector - (text "CCA[23..0]" (rect 3954 2768 4008 2779)(font "Arial" )) - (pt 4024 2784) - (pt 3944 2784) - (bus) -) (connector (pt 2904 2896) (pt 2904 2864) @@ -9094,22 +8845,6 @@ applicable agreement for further details. (pt 2824 2840) (pt 2736 2840) ) -(connector - (text "CC24[23..0]" (rect 3954 2736 4013 2747)(font "Arial" )) - (pt 3944 2752) - (pt 4024 2752) - (bus) -) -(connector - (pt 4240 2792) - (pt 4240 2800) - (bus) -) -(connector - (pt 4240 2800) - (pt 4240 2808) - (bus) -) (connector (pt 3576 2784) (pt 3672 2784) @@ -9125,31 +8860,11 @@ applicable agreement for further details. (pt 3888 2800) (bus) ) -(connector - (pt 3888 2800) - (pt 3888 2832) - (bus) -) -(connector - (pt 3888 2832) - (pt 4024 2832) - (bus) -) -(connector - (pt 4024 2848) - (pt 3888 2848) - (bus) -) (connector (pt 3888 2888) (pt 3816 2888) (bus) ) -(connector - (pt 3888 2848) - (pt 3888 2888) - (bus) -) (connector (text "PIXEL_CLK" (rect 3034 2712 3095 2723)(font "Arial" )) (pt 3032 2728) @@ -9175,12 +8890,6 @@ applicable agreement for further details. (pt 3376 2784) (pt 3432 2784) ) -(connector - (text "CC16[23..19],CC16[15..10],CC16[7..3]" (rect 2506 2592 2694 2603)(font "Arial" )) - (pt 2688 2664) - (pt 2560 2664) - (bus) -) (connector (text "CC16[18..16],CC16[9..8],CC16[2..0]" (rect 2530 2728 2707 2739)(font "Arial" )) (pt 2696 2744) @@ -9256,12 +8965,6 @@ applicable agreement for further details. (pt 3112 2960) (pt 3192 2960) ) -(connector - (text "FIFO_MW[8..0]" (rect 194 2376 269 2387)(font "Arial" )) - (pt 296 2392) - (pt 184 2392) - (bus) -) (connector (text "MAIN_CLK" (rect 3370 2208 3427 2219)(font "Arial" )) (pt 3448 2224) @@ -10004,12 +9707,6 @@ applicable agreement for further details. (pt 2040 976) (bus) ) -(connector - (text "VDM_SEL[3..0]" (rect 570 2416 646 2427)(font "Arial" )) - (pt 560 2432) - (pt 656 2432) - (bus) -) (connector (text "VDMB[127..0]" (rect 1586 1080 1654 1091)(font "Arial" )) (pt 1576 1096) @@ -10151,11 +9848,6 @@ applicable agreement for further details. (pt 264 1832) (pt 360 1832) ) -(connector - (text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" )) - (pt 296 2232) - (pt 192 2232) -) (connector (text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" )) (pt 1712 1472) @@ -10320,6 +10012,73 @@ applicable agreement for further details. (pt 2064 1312) (pt 1992 1312) ) +(connector + (pt 1968 1424) + (pt 1968 1208) + (bus) +) +(connector + (pt 2248 1208) + (pt 2240 1208) + (bus) +) +(connector + (pt 2248 1344) + (pt 2248 1208) + (bus) +) +(connector + (pt 1608 1432) + (pt 1608 1232) +) +(connector + (pt 1944 1296) + (pt 1944 1248) +) +(connector + (pt 2064 1312) + (pt 2064 1296) +) +(connector + (pt 1872 1424) + (pt 1968 1424) + (bus) +) +(connector + (pt 1968 1424) + (pt 2000 1424) + (bus) +) +(connector + (pt 1600 1432) + (pt 1608 1432) +) +(connector + (pt 1608 1432) + (pt 1712 1432) +) +(connector + (pt 1968 1208) + (pt 2080 1208) + (bus) +) +(connector + (pt 1608 1232) + (pt 2080 1232) +) +(connector + (pt 1944 1248) + (pt 2080 1248) +) +(connector + (text "PIXEL_CLK" (rect 2010 1256 2071 1267)(font "Arial" )) + (pt 2000 1272) + (pt 2080 1272) +) +(connector + (pt 2064 1296) + (pt 2080 1296) +) (connector (text "nFB_BURST" (rect 1570 1896 1634 1907)(font "Arial" )) (pt 1560 1912) @@ -10461,12 +10220,6 @@ applicable agreement for further details. (pt 2016 2384) (bus) ) -(connector - (text "CCR[23..0]" (rect 2026 2176 2081 2187)(font "Arial" )) - (pt 2096 2192) - (pt 2016 2192) - (bus) -) (connector (text "CCSEL[2..0]" (rect 2026 2200 2087 2211)(font "Arial" )) (pt 2016 2216) @@ -10577,71 +10330,328 @@ applicable agreement for further details. (pt 2112 1768) ) (connector - (pt 1968 1424) - (pt 1968 1208) + (text "BORDER_COLOR[23..0]" (rect 2026 2176 2149 2187)(font "Arial" )) + (pt 2096 2192) + (pt 2016 2192) (bus) ) (connector - (pt 2248 1208) - (pt 2240 1208) + (text "VR[7..0],VG[7..0],VB[7..0]" (rect 4522 2776 4648 2787)(font "Arial" )) + (pt 4512 2792) + (pt 4664 2792) (bus) ) (connector - (pt 2248 1344) - (pt 2248 1208) + (pt 4240 2808) + (pt 4280 2808) (bus) ) (connector - (pt 1608 1432) - (pt 1608 1232) + (text "PIXEL_CLK" (rect 4202 2808 4263 2819)(font "Arial" )) + (pt 4192 2824) + (pt 4280 2824) ) (connector - (pt 1944 1296) - (pt 1944 1248) -) -(connector - (pt 2064 1312) - (pt 2064 1296) -) -(connector - (pt 1872 1424) - (pt 1968 1424) + (pt 4240 2792) + (pt 4280 2792) (bus) ) (connector - (pt 1968 1424) - (pt 2000 1424) + (text "FB_AD[31..0]" (rect 570 1904 636 1915)(font "Arial" )) + (pt 680 1920) + (pt 560 1920) (bus) ) (connector - (pt 1600 1432) - (pt 1608 1432) + (text "nFB_CS1" (rect 202 2040 250 2051)(font "Arial" )) + (pt 192 2056) + (pt 296 2056) ) (connector - (pt 1608 1432) - (pt 1712 1432) + (text "nFB_CS2" (rect 202 2064 251 2075)(font "Arial" )) + (pt 192 2080) + (pt 296 2080) ) (connector - (pt 1968 1208) - (pt 2080 1208) + (text "nFB_CS3" (rect 202 2088 251 2099)(font "Arial" )) + (pt 192 2104) + (pt 296 2104) +) +(connector + (text "nFB_WR" (rect 202 2112 248 2123)(font "Arial" )) + (pt 192 2128) + (pt 296 2128) +) +(connector + (text "FB_SIZE0" (rect 202 2136 253 2147)(font "Arial" )) + (pt 192 2152) + (pt 296 2152) +) +(connector + (text "FB_SIZE1" (rect 202 2160 252 2171)(font "Arial" )) + (pt 192 2176) + (pt 296 2176) +) +(connector + (text "nFB_OE" (rect 202 2184 245 2195)(font "Arial" )) + (pt 192 2200) + (pt 296 2200) +) +(connector + (text "nVWE" (rect 570 2192 603 2203)(font "Arial" )) + (pt 632 2208) + (pt 560 2208) +) +(connector + (text "nVCAS" (rect 570 2216 607 2227)(font "Arial" )) + (pt 632 2232) + (pt 560 2232) +) +(connector + (text "nVRAS" (rect 570 2240 607 2251)(font "Arial" )) + (pt 632 2256) + (pt 560 2256) +) +(connector + (text "nVCS" (rect 570 2264 600 2275)(font "Arial" )) + (pt 632 2280) + (pt 560 2280) +) +(connector + (text "VCKE" (rect 570 2288 601 2299)(font "Arial" )) + (pt 632 2304) + (pt 560 2304) +) +(connector + (text "MAIN_CLK" (rect 202 1944 259 1955)(font "Arial" )) + (pt 296 1960) + (pt 192 1960) +) +(connector + (text "FB_ALE" (rect 202 2016 244 2027)(font "Arial" )) + (pt 296 2032) + (pt 192 2032) +) +(connector + (text "FB_LE[3..0]" (rect 570 1976 629 1987)(font "Arial" )) + (pt 560 1992) + (pt 680 1992) (bus) ) (connector - (pt 1608 1232) - (pt 2080 1232) + (text "FB_VDOE[3..0]" (rect 570 2000 646 2011)(font "Arial" )) + (pt 560 2016) + (pt 680 2016) + (bus) ) (connector - (pt 1944 1248) - (pt 2080 1248) + (text "DDR_SYNC_66M" (rect 210 1968 299 1979)(font "Arial" )) + (pt 200 1984) + (pt 296 1984) ) (connector - (text "PIXEL_CLK" (rect 2010 1256 2071 1267)(font "Arial" )) - (pt 2000 1272) - (pt 2080 1272) + (text "FB_ADR[31..0]" (rect 202 1992 276 2003)(font "Arial" )) + (pt 192 2008) + (pt 296 2008) + (bus) ) (connector - (pt 2064 1296) - (pt 2080 1296) + (text "nRSTO" (rect 202 1896 240 1907)(font "Arial" )) + (pt 192 1912) + (pt 296 1912) +) +(connector + (text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 303 2251)(font "Arial" )) + (pt 296 2256) + (pt 168 2256) + (bus) +) +(connector + (text "BLITTER_ADR[31..0]" (rect 194 2288 300 2299)(font "Arial" )) + (pt 184 2304) + (pt 296 2304) + (bus) +) +(connector + (text "BLITTER_SIG" (rect 194 2312 265 2323)(font "Arial" )) + (pt 184 2328) + (pt 296 2328) +) +(connector + (text "BLITTER_WR" (rect 194 2336 265 2347)(font "Arial" )) + (pt 184 2352) + (pt 296 2352) +) +(connector + (text "SR_FIFO_WRE" (rect 570 2072 650 2083)(font "Arial" )) + (pt 648 2088) + (pt 560 2088) +) +(connector + (text "SR_DDR_FB" (rect 570 2312 637 2323)(font "Arial" )) + (pt 640 2328) + (pt 560 2328) +) +(connector + (text "SR_DDR_WR" (rect 570 2024 641 2035)(font "Arial" )) + (pt 664 2040) + (pt 560 2040) +) +(connector + (text "SR_VDMP[7..0]" (rect 570 2336 647 2347)(font "Arial" )) + (pt 560 2352) + (pt 664 2352) + (bus) +) +(connector + (text "SR_DDRWR_D_SEL" (rect 570 2360 676 2371)(font "Arial" )) + (pt 560 2376) + (pt 664 2376) +) +(connector + (text "DDRCLK0" (rect 194 1920 247 1931)(font "Arial" )) + (pt 296 1936) + (pt 184 1936) +) +(connector + (text "VIDEO_DDR_TA" (rect 570 2488 657 2499)(font "Arial" )) + (pt 560 2504) + (pt 664 2504) +) +(connector + (text "SR_BLITTER_DACK" (rect 570 2464 676 2475)(font "Arial" )) + (pt 664 2480) + (pt 560 2480) +) +(connector + (text "CLK33M" (rect 218 2432 262 2443)(font "Arial" )) + (pt 208 2448) + (pt 296 2448) +) +(connector + (text "BA[1..0]" (rect 570 2120 610 2131)(font "Arial" )) + (pt 632 2136) + (pt 560 2136) + (bus) +) +(connector + (text "DDRWR_D_SEL1" (rect 570 2392 659 2403)(font "Arial" )) + (pt 656 2408) + (pt 560 2408) +) +(connector + (text "FIFO_MW[8..0]" (rect 194 2376 269 2387)(font "Arial" )) + (pt 296 2392) + (pt 184 2392) + (bus) +) +(connector + (text "VDM_SEL[3..0]" (rect 570 2416 646 2427)(font "Arial" )) + (pt 560 2432) + (pt 656 2432) + (bus) +) +(connector + (text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" )) + (pt 296 2232) + (pt 192 2232) +) +(connector + (text "VA[12..0]" (rect 570 2168 616 2179)(font "Arial" )) + (pt 560 2184) + (pt 632 2184) + (bus) +) +(connector + (text "CC16[23..0]" (rect 3954 2752 4013 2763)(font "Arial" )) + (pt 4024 2768) + (pt 3944 2768) + (bus) +) +(connector + (pt 4240 2800) + (pt 4176 2800) + (bus) +) +(connector + (text "PIXEL_CLK" (rect 3946 2848 4007 2859)(font "Arial" )) + (pt 3936 2864) + (pt 4024 2864) +) +(connector + (pt 4104 2920) + (pt 4104 2888) + (bus) +) +(connector + (text "CCSEL[2..0]" (rect 4010 2904 4071 2915)(font "Arial" )) + (pt 4000 2920) + (pt 4104 2920) + (bus) +) +(connector + (text "CCA[23..0]" (rect 3954 2768 4008 2779)(font "Arial" )) + (pt 4024 2784) + (pt 3944 2784) + (bus) +) +(connector + (text "CC24[23..0]" (rect 3954 2736 4013 2747)(font "Arial" )) + (pt 3944 2752) + (pt 4024 2752) + (bus) +) +(connector + (pt 3888 2800) + (pt 3888 2832) + (bus) +) +(connector + (pt 3888 2832) + (pt 4024 2832) + (bus) +) +(connector + (pt 3888 2848) + (pt 4024 2848) + (bus) +) +(connector + (pt 3888 2888) + (pt 3888 2848) + (bus) +) +(connector + (text "BORDER_COLOR[23..0]" (rect 3954 2720 4077 2731)(font "Arial" )) + (pt 4024 2736) + (pt 3944 2736) + (bus) +) +(connector + (pt 4240 2792) + (pt 4240 2800) + (bus) +) +(connector + (pt 4240 2800) + (pt 4240 2808) + (bus) +) +(connector + (pt 2568 2664) + (pt 2568 2568) + (bus) +) +(connector + (pt 2560 2664) + (pt 2568 2664) + (bus) +) +(connector + (text "CC16[23..19],CC16[15..10],CC16[7..3]" (rect 2530 2552 2718 2563)(font "Arial" )) + (pt 2568 2568) + (pt 2688 2568) + (bus) ) (junction (pt 2984 1688)) (junction (pt 792 1192)) diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index 4f32a08..6addd74 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -4238,7 +4238,7 @@ applicable agreement for further details. ) ) (block - (rect 1264 -48 1672 728) + (rect 1272 -48 1680 728) (text "video" (rect 5 5 36 18)(font "Arial" (font_size 8))) (text "i_video" (rect 5 762 41 773)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) (block_io "MAIN_CLK" (input)) (block_io "nFB_CS1" (input)) @@ -4456,63 +4456,6 @@ applicable agreement for further details. (pt 1672 2400) (bus) ) -(connector - (text "FB_AD[31..0]" (rect 1682 8 1748 19)(font "Arial" )) - (pt 1832 24) - (pt 1672 24) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 328 1220 339)(font "Arial" )) - (pt 1112 344) - (pt 1264 344) - (bus) -) -(connector - (text "nFB_WR" (rect 1162 184 1208 195)(font "Arial" )) - (pt 1152 200) - (pt 1264 200) -) -(connector - (text "nFB_CS1" (rect 1154 208 1202 219)(font "Arial" )) - (pt 1152 224) - (pt 1264 224) -) -(connector - (text "FB_SIZE0" (rect 1154 256 1205 267)(font "Arial" )) - (pt 1152 272) - (pt 1264 272) -) -(connector - (text "FB_SIZE1" (rect 1154 280 1204 291)(font "Arial" )) - (pt 1152 296) - (pt 1264 296) -) -(connector - (text "nFB_CS2" (rect 1162 232 1211 243)(font "Arial" )) - (pt 1152 248) - (pt 1264 248) -) -(connector - (text "nBLANK" (rect 1682 184 1726 195)(font "Arial" )) - (pt 1672 200) - (pt 1832 200) -) -(connector - (text "nSYNC" (rect 1682 208 1720 219)(font "Arial" )) - (pt 1672 224) - (pt 1832 224) -) -(connector - (text "nFB_CS3" (rect 1186 352 1235 363)(font "Arial" )) - (pt 1264 368) - (pt 1176 368) -) -(connector - (text "nPD_VGA" (rect 1682 256 1736 267)(font "Arial" )) - (pt 1672 272) - (pt 1832 272) -) (connector (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) (pt 1152 2600) @@ -4524,11 +4467,6 @@ applicable agreement for further details. (pt 1832 2424) (bus) ) -(connector - (text "nFB_OE" (rect 1170 160 1213 171)(font "Arial" )) - (pt 1264 176) - (pt 1160 176) -) (connector (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) (pt 1152 2744) @@ -4660,87 +4598,6 @@ applicable agreement for further details. (pt 528 2416) (pt 616 2416) ) -(connector - (text "FB_ALE" (rect 1194 304 1236 315)(font "Arial" )) - (pt 1264 320) - (pt 1184 320) -) -(connector - (text "DDRCLK[3..0]" (rect 1162 136 1232 147)(font "Arial" )) - (pt 1152 152) - (pt 1264 152) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 1178 112 1267 123)(font "Arial" )) - (pt 1168 128) - (pt 1264 128) -) -(connector - (text "VD[31..0]" (rect 1682 288 1728 299)(font "Arial" )) - (pt 1672 304) - (pt 2648 304) - (bus) -) -(connector - (text "VA[12..0]" (rect 1682 312 1728 323)(font "Arial" )) - (pt 1672 328) - (pt 2528 328) - (bus) -) -(connector - (text "nVWE" (rect 1682 336 1715 347)(font "Arial" )) - (pt 1672 352) - (pt 2400 352) -) -(connector - (text "nVCAS" (rect 1690 360 1727 371)(font "Arial" )) - (pt 1672 376) - (pt 2304 376) -) -(connector - (text "nVRAS" (rect 1690 384 1727 395)(font "Arial" )) - (pt 1672 400) - (pt 2208 400) -) -(connector - (text "nVCS" (rect 1690 408 1720 419)(font "Arial" )) - (pt 1672 424) - (pt 2040 424) -) -(connector - (text "VCKE" (rect 1690 432 1721 443)(font "Arial" )) - (pt 1672 448) - (pt 1944 448) -) -(connector - (text "VSYNC" (rect 1682 136 1722 147)(font "Arial" )) - (pt 1672 152) - (pt 1832 152) -) -(connector - (text "HSYNC" (rect 1682 160 1722 171)(font "Arial" )) - (pt 1672 176) - (pt 1832 176) -) -(connector - (text "VB[7..0]" (rect 1754 112 1794 123)(font "Arial" )) - (pt 1672 128) - (pt 1912 128) - (bus) -) -(connector - (text "VG[7..0]" (rect 1842 88 1883 99)(font "Arial" )) - (pt 1672 104) - (pt 2000 104) - (bus) -) -(connector - (text "VR[7..0]" (rect 1922 64 1962 75)(font "Arial" )) - (pt 1672 80) - (pt 2080 80) - (bus) -) (connector (text "IO[17..0]" (rect 1962 3224 2004 3235)(font "Arial" )) (pt 1672 3240) @@ -4753,11 +4610,6 @@ applicable agreement for further details. (pt 1944 3264) (bus) ) -(connector - (text "CLK25M" (rect 1202 608 1246 619)(font "Arial" )) - (pt 1192 624) - (pt 1264 624) -) (connector (text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" )) (pt 440 2136) @@ -4792,11 +4644,6 @@ applicable agreement for further details. (pt 1672 3520) (pt 1792 3520) ) -(connector - (text "Video_TA" (rect 1682 696 1732 707)(font "Arial" )) - (pt 1672 712) - (pt 1880 712) -) (connector (text "INT_HANDLER_TA" (rect 1810 728 1909 739)(font "Arial" )) (pt 1880 744) @@ -4828,22 +4675,6 @@ applicable agreement for further details. (pt 2504 760) (pt 2536 760) ) -(connector - (text "MAIN_CLK" (rect 1186 88 1243 99)(font "Arial" )) - (pt 1184 104) - (pt 1264 104) -) -(connector - (text "nRSTO" (rect 1194 40 1232 51)(font "Arial" )) - (pt 1184 56) - (pt 1264 56) -) -(connector - (text "BA[1..0]" (rect 1682 456 1722 467)(font "Arial" )) - (pt 1672 472) - (pt 1832 472) - (bus) -) (connector (text "PIXEL_CLK" (rect 2394 -64 2455 -53)(font "Arial" )) (pt 2384 -48) @@ -4881,11 +4712,6 @@ applicable agreement for further details. (pt 2128 -64) (pt 2136 -64) ) -(connector - (text "PIXEL_CLK" (rect 1682 232 1743 243)(font "Arial" )) - (pt 1744 248) - (pt 1672 248) -) (connector (text "PIXEL_CLK" (rect 2394 184 2455 195)(font "Arial" )) (pt 2384 200) @@ -5157,69 +4983,23 @@ applicable agreement for further details. (pt 64 544) (pt 192 544) ) -(connector - (text "VR_D[8..0]" (rect 1170 464 1224 475)(font "Arial" )) - (pt 1144 480) - (pt 1264 480) - (bus) -) (connector (text "VDQS[3..0]" (rect 1674 504 1730 515)(font "Arial" )) (pt 2040 544) (pt 1960 544) (bus) ) -(connector - (pt 1672 544) - (pt 1888 544) - (bus) -) -(connector - (pt 1888 544) - (pt 1888 568) - (bus) -) (connector (text "VDM[3..0]" (rect 1682 528 1731 539)(font "Arial" )) (pt 1944 568) (pt 1888 568) (bus) ) -(connector - (pt 1672 520) - (pt 1960 520) - (bus) -) -(connector - (pt 1960 544) - (pt 1960 520) - (bus) -) -(connector - (text "VIDEO_RECONFIG" (rect 1674 560 1774 571)(font "Arial" )) - (pt 1672 576) - (pt 1792 576) -) -(connector - (text "VR_WR" (rect 1698 592 1739 603)(font "Arial" )) - (pt 1672 608) - (pt 1792 608) -) (connector (text "VR_BUSY" (rect 418 496 472 507)(font "Arial" )) (pt 408 512) (pt 480 512) ) -(connector - (text "VR_BUSY" (rect 1170 448 1224 459)(font "Arial" )) - (pt 1144 464) - (pt 1264 464) -) -(connector - (text "VR_RD" (rect 1698 576 1736 587)(font "Arial" )) - (pt 1792 592) - (pt 1672 592) -) (connector (text "nRSTO" (rect -86 680 -48 691)(font "Arial" )) (pt -96 696) @@ -5240,16 +5020,6 @@ applicable agreement for further details. (pt 528 568) (pt 608 568) ) -(connector - (text "CLK_VIDEO" (rect 1162 552 1225 563)(font "Arial" )) - (pt 984 568) - (pt 1264 568) -) -(connector - (text "CLK33M" (rect 1202 584 1246 595)(font "Arial" )) - (pt 1264 600) - (pt 1192 600) -) (connector (text "HSYNC" (rect 2314 -96 2354 -85)(font "Arial" )) (pt 2304 -80) @@ -5986,6 +5756,236 @@ applicable agreement for further details. (pt 472 2064) (pt 544 2064) ) +(connector + (text "FB_AD[31..0]" (rect 1690 8 1756 19)(font "Arial" )) + (pt 1840 24) + (pt 1680 24) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1154 328 1228 339)(font "Arial" )) + (pt 1120 344) + (pt 1272 344) + (bus) +) +(connector + (text "nFB_WR" (rect 1170 184 1216 195)(font "Arial" )) + (pt 1160 200) + (pt 1272 200) +) +(connector + (text "nFB_CS1" (rect 1162 208 1210 219)(font "Arial" )) + (pt 1160 224) + (pt 1272 224) +) +(connector + (text "FB_SIZE0" (rect 1162 256 1213 267)(font "Arial" )) + (pt 1160 272) + (pt 1272 272) +) +(connector + (text "FB_SIZE1" (rect 1162 280 1212 291)(font "Arial" )) + (pt 1160 296) + (pt 1272 296) +) +(connector + (text "nFB_CS2" (rect 1170 232 1219 243)(font "Arial" )) + (pt 1160 248) + (pt 1272 248) +) +(connector + (text "nBLANK" (rect 1690 184 1734 195)(font "Arial" )) + (pt 1680 200) + (pt 1840 200) +) +(connector + (text "VR[7..0]" (rect 1930 64 1970 75)(font "Arial" )) + (pt 2080 80) + (pt 1680 80) + (bus) +) +(connector + (text "VG[7..0]" (rect 1850 88 1891 99)(font "Arial" )) + (pt 2000 104) + (pt 1680 104) + (bus) +) +(connector + (text "VB[7..0]" (rect 1762 112 1802 123)(font "Arial" )) + (pt 1912 128) + (pt 1680 128) + (bus) +) +(connector + (text "nSYNC" (rect 1690 208 1728 219)(font "Arial" )) + (pt 1832 224) + (pt 1680 224) +) +(connector + (text "nPD_VGA" (rect 1690 256 1744 267)(font "Arial" )) + (pt 1832 272) + (pt 1680 272) +) +(connector + (text "VA[12..0]" (rect 1690 312 1736 323)(font "Arial" )) + (pt 2528 328) + (pt 1680 328) + (bus) +) +(connector + (text "nVWE" (rect 1690 336 1723 347)(font "Arial" )) + (pt 2400 352) + (pt 1680 352) +) +(connector + (text "nFB_CS3" (rect 1194 352 1243 363)(font "Arial" )) + (pt 1176 368) + (pt 1272 368) +) +(connector + (text "nFB_OE" (rect 1178 160 1221 171)(font "Arial" )) + (pt 1272 176) + (pt 1168 176) +) +(connector + (text "FB_ALE" (rect 1202 304 1244 315)(font "Arial" )) + (pt 1272 320) + (pt 1192 320) +) +(connector + (text "DDRCLK[3..0]" (rect 1170 136 1240 147)(font "Arial" )) + (pt 1160 152) + (pt 1272 152) + (bus) +) +(connector + (text "DDR_SYNC_66M" (rect 1186 112 1275 123)(font "Arial" )) + (pt 1176 128) + (pt 1272 128) +) +(connector + (text "VD[31..0]" (rect 1690 288 1736 299)(font "Arial" )) + (pt 2648 304) + (pt 1680 304) + (bus) +) +(connector + (text "nVCAS" (rect 1698 360 1735 371)(font "Arial" )) + (pt 2304 376) + (pt 1680 376) +) +(connector + (text "nVRAS" (rect 1698 384 1735 395)(font "Arial" )) + (pt 2208 400) + (pt 1680 400) +) +(connector + (text "nVCS" (rect 1698 408 1728 419)(font "Arial" )) + (pt 2040 424) + (pt 1680 424) +) +(connector + (text "VCKE" (rect 1698 432 1729 443)(font "Arial" )) + (pt 1944 448) + (pt 1680 448) +) +(connector + (text "VSYNC" (rect 1690 136 1730 147)(font "Arial" )) + (pt 1680 152) + (pt 1840 152) +) +(connector + (text "HSYNC" (rect 1690 160 1730 171)(font "Arial" )) + (pt 1680 176) + (pt 1840 176) +) +(connector + (text "CLK25M" (rect 1210 608 1254 619)(font "Arial" )) + (pt 1200 624) + (pt 1272 624) +) +(connector + (text "Video_TA" (rect 1690 696 1740 707)(font "Arial" )) + (pt 1880 712) + (pt 1680 712) +) +(connector + (text "MAIN_CLK" (rect 1194 88 1251 99)(font "Arial" )) + (pt 1192 104) + (pt 1272 104) +) +(connector + (text "nRSTO" (rect 1202 40 1240 51)(font "Arial" )) + (pt 1192 56) + (pt 1272 56) +) +(connector + (text "BA[1..0]" (rect 1690 456 1730 467)(font "Arial" )) + (pt 1832 472) + (pt 1680 472) + (bus) +) +(connector + (text "PIXEL_CLK" (rect 1690 232 1751 243)(font "Arial" )) + (pt 1752 248) + (pt 1680 248) +) +(connector + (text "VR_D[8..0]" (rect 1178 464 1232 475)(font "Arial" )) + (pt 1152 480) + (pt 1272 480) + (bus) +) +(connector + (pt 1888 544) + (pt 1680 544) + (bus) +) +(connector + (pt 1888 568) + (pt 1888 544) + (bus) +) +(connector + (pt 1960 520) + (pt 1680 520) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 520) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1682 560 1782 571)(font "Arial" )) + (pt 1680 576) + (pt 1800 576) +) +(connector + (text "VR_WR" (rect 1706 592 1747 603)(font "Arial" )) + (pt 1680 608) + (pt 1800 608) +) +(connector + (text "VR_BUSY" (rect 1178 448 1232 459)(font "Arial" )) + (pt 1152 464) + (pt 1272 464) +) +(connector + (text "VR_RD" (rect 1706 576 1744 587)(font "Arial" )) + (pt 1800 592) + (pt 1680 592) +) +(connector + (text "CLK_VIDEO" (rect 1170 552 1233 563)(font "Arial" )) + (pt 984 568) + (pt 1272 568) +) +(connector + (text "CLK33M" (rect 1210 584 1254 595)(font "Arial" )) + (pt 1272 600) + (pt 1200 600) +) (junction (pt 2504 760)) (junction (pt 1856 -64)) (junction (pt 2424 -80)) From f8875032552f847c14543c11c4aa94d2048f8c06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 10 Jan 2016 07:44:20 +0000 Subject: [PATCH 038/127] rename to make it usable as alternative in Quartus --- FPGA_Quartus_13.1/{firebee1.sdc.groups => firebee_groups.sdc} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename FPGA_Quartus_13.1/{firebee1.sdc.groups => firebee_groups.sdc} (100%) diff --git a/FPGA_Quartus_13.1/firebee1.sdc.groups b/FPGA_Quartus_13.1/firebee_groups.sdc similarity index 100% rename from FPGA_Quartus_13.1/firebee1.sdc.groups rename to FPGA_Quartus_13.1/firebee_groups.sdc From 7296970eb61f46f19f3e59e47f44888feabe8b6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 10 Jan 2016 10:24:30 +0000 Subject: [PATCH 039/127] rename Video.bdf to lower case --- FPGA_Quartus_13.1/Video/{Video.bdf => video.bdf} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename FPGA_Quartus_13.1/Video/{Video.bdf => video.bdf} (100%) diff --git a/FPGA_Quartus_13.1/Video/Video.bdf b/FPGA_Quartus_13.1/Video/video.bdf similarity index 100% rename from FPGA_Quartus_13.1/Video/Video.bdf rename to FPGA_Quartus_13.1/Video/video.bdf From 9cfde26eefa45cf5ef9455be6966c42c70296ac4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 10 Jan 2016 19:05:15 +0000 Subject: [PATCH 040/127] modify settings --- FPGA_Quartus_13.1/firebee1.qsf | 46 +++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 1d05824..5ccf976 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments @@ -351,8 +351,7 @@ set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name FAMILY CycloneIII set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED @@ -370,11 +369,11 @@ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to VA set_instance_assignment -name IO_STANDARD "2.5 V" -to VD @@ -648,8 +647,34 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name BDF_FILE Video/video.bdf set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp @@ -746,7 +771,6 @@ set_global_assignment -name QIP_FILE Video/lpm_compare1.qip set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd set_global_assignment -name QIP_FILE Video/lpm_ff4.qip @@ -822,10 +846,4 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From b3edfcd45714ffffae86cae60cb0bf83a35968d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 07:13:36 +0000 Subject: [PATCH 041/127] reformat --- .../Interrupt_Handler/interrupt_handler.tdf | 88 ++++++++++--------- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 68 +++++++------- FPGA_Quartus_13.1/firebee1.qsf | 2 +- FPGA_Quartus_13.1/firebee1.sdc | 8 +- 4 files changed, 92 insertions(+), 74 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf index fd3cd47..82f0b78 100644 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -94,7 +94,7 @@ BEGIN # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + -- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN INT_CTR[].CLK = MAIN_CLK; INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 INT_CTR[] = FB_AD[]; @@ -102,7 +102,8 @@ BEGIN INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; --- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + + -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA[].CLK = MAIN_CLK; INT_ENA[].CLRN = nRSTO; INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 @@ -111,16 +112,19 @@ BEGIN INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; --- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + + -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; --- INTERRUPT LATCH REGISTER READ ONLY + + -- INTERRUPT LATCH REGISTER READ ONLY INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 --- INTERRUPT + + -- INTERRUPT !nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ3 = INT_CTR0 & INT_ENA[27]; !nIRQ4 = VSYNC & INT_ENA[28]; @@ -128,26 +132,27 @@ BEGIN !nIRQ6 = !nMFP_INT & INT_ENA[30]; !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; -PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC - # FB_ADR[19..4]==H"F8E0" -- VME --- # FB_ADR[19..4]==H"F920" -- PADDLE --- # FB_ADR[19..4]==H"F921" -- PADDLE --- # FB_ADR[19..4]==H"F922" -- PADDLE - # FB_ADR[19..4]==H"FFA8" -- MFP2 - # FB_ADR[19..4]==H"FFA9" -- MFP2 - # FB_ADR[19..4]==H"FFAA" -- MFP2 - # FB_ADR[19..4]==H"FFA8" -- MFP2 - # FB_ADR[19..8]==H"F87" -- TT SCSI - # FB_ADR[19..4]==H"FFC2" -- ST UHR - # FB_ADR[19..4]==H"FFC3" -- ST UHR --- # FB_ADR[19..4]==H"F890" -- DMA SOUND --- # FB_ADR[19..4]==H"F891" -- DMA SOUND --- # FB_ADR[19..4]==H"F892" -- DMA SOUND - ); --- IF VIDEO ADR CHANGE -TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 --- INTERRUPT LATCH + PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC + # FB_ADR[19..4]==H"F8E0" -- VME +-- # FB_ADR[19..4]==H"F920" -- PADDLE +-- # FB_ADR[19..4]==H"F921" -- PADDLE +-- # FB_ADR[19..4]==H"F922" -- PADDLE + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..4]==H"FFA9" -- MFP2 + # FB_ADR[19..4]==H"FFAA" -- MFP2 + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..8]==H"F87" -- TT SCSI + # FB_ADR[19..4]==H"FFC2" -- ST UHR + # FB_ADR[19..4]==H"FFC3" -- ST UHR +-- # FB_ADR[19..4]==H"F890" -- DMA SOUND +-- # FB_ADR[19..4]==H"F891" -- DMA SOUND +-- # FB_ADR[19..4]==H"F892" -- DMA SOUND + ); + -- IF VIDEO ADR CHANGE + TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 + + -- INTERRUPT LATCH INT_L[].CLK = MAIN_CLK; INT_L[].CLRN = nRSTO; INT_L0 = PIC_INT & INT_ENA[0]; @@ -162,9 +167,11 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_L9 = HSYNC & INT_ENA[9]; INT_LA[][].CLK = MAIN_CLK; - INT_LATCH[] = H"FFFFFFFF"; + + INT_LATCH[] = H"FFFFFFFF"; INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO; - FOR I IN 0 TO 9 GENERATE + + FOR I IN 0 TO 9 GENERATE INT_LA[I][].CLRN = INT_ENA[I] & nRSTO; INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7 # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8 @@ -191,8 +198,9 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN30 = !nMFP_INT; INT_IN31 = DMA_DRQ; ---*************************************************************************************** --- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + + --*************************************************************************************** + -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE ACP_CONF[].CLK = MAIN_CLK; ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 ACP_CONF[] = FB_AD[]; @@ -200,11 +208,11 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; ---*************************************************************************************** + --*************************************************************************************** --------------------------------------------------------------- --- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR ----------------------------------------------------------- + -------------------------------------------------------------- + -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR + ---------------------------------------------------------- RTC_ADR[].CLK = MAIN_CLK; RTC_ADR[] = FB_AD[21..16]; UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 @@ -238,7 +246,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); @@ -249,36 +257,36 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- TRISTATE OUTPUT diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index e49d652..4703a54 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -93,10 +93,10 @@ VARIABLE ACP_VIDEO_ON :NODE; SYS_CTR[6..0] :DFFE; SYS_CTR_CS :NODE; - LOF[15..0] :DFFE; - LOF_CS :NODE; - LWD[15..0] :DFFE; - LWD_CS :NODE; + LOF[15..0] :DFFE; + LOF_CS :NODE; + LWD[15..0] :DFFE; + LWD_CS :NODE; -- DIV. CONTROL REGISTER CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT HSYNC :DFF; @@ -131,6 +131,7 @@ VARIABLE CCSEL[2..0] :DFF; COLOR16 :NODE; COLOR24 :NODE; + -- ATARI RESOLUTION ATARI_SYNC :NODE; ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 @@ -150,18 +151,18 @@ VARIABLE H_TOTAL[11..0] :NODE; HDIS_LEN[11..0] :NODE; MULF[5..0] :NODE; - HHT[11..0] :DFFE; - HHT_CS :NODE; - HBE[11..0] :DFFE; - HBE_CS :NODE; - HDB[11..0] :DFFE; - HDB_CS :NODE; - HDE[11..0] :DFFE; - HDE_CS :NODE; - HBB[11..0] :DFFE; - HBB_CS :NODE; - HSS[11..0] :DFFE; - HSS_CS :NODE; + HHT[11..0] :DFFE; + HHT_CS :NODE; + HBE[11..0] :DFFE; + HBE_CS :NODE; + HDB[11..0] :DFFE; + HDB_CS :NODE; + HDE[11..0] :DFFE; + HDE_CS :NODE; + HBB[11..0] :DFFE; + HBB_CS :NODE; + HSS[11..0] :DFFE; + HSS_CS :NODE; -- VERTIKAL RAND_OBEN[10..0] :NODE; VDIS_START[10..0] :NODE; @@ -175,20 +176,20 @@ VARIABLE DOP_ZEI :DFF; DOP_FIFO_CLR :DFF; - VBE[10..0] :DFFE; - VBE_CS :NODE; - VDB[10..0] :DFFE; - VDB_CS :NODE; - VDE[10..0] :DFFE; - VDE_CS :NODE; - VBB[10..0] :DFFE; - VBB_CS :NODE; - VSS[10..0] :DFFE; - VSS_CS :NODE; - VFT[10..0] :DFFE; - VFT_CS :NODE; - VCO[8..0] :DFFE; - VCO_CS :NODE; + VBE[10..0] :DFFE; + VBE_CS :NODE; + VDB[10..0] :DFFE; + VDB_CS :NODE; + VDE[10..0] :DFFE; + VDE_CS :NODE; + VBB[10..0] :DFFE; + VBB_CS :NODE; + VSS[10..0] :DFFE; + VSS_CS :NODE; + VFT[10..0] :DFFE; + VFT_CS :NODE; + VCO[8..0] :DFFE; + VCO_CS :NODE; VCNTRL[3..0] :DFFE; VCNTRL_CS :NODE; @@ -203,26 +204,32 @@ BEGIN FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + -- BYT SELECT 16 BIT FB_16B0 = FB_ADR[0] == 0; -- ADR==0 FB_16B1 = FB_ADR[0] == 1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT + -- ACP CLUT -- ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; + CLUT_TA.CLK = MAIN_CLK; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; + --FALCON CLUT -- FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; + -- ST CLUT -- ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; + -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 @@ -231,6 +238,7 @@ BEGIN COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN + -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 5ccf976..17afb0a 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -368,7 +368,7 @@ set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 3551868..026355d 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -118,15 +118,17 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] - +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_pins {VA}] #************************************************************** # Set Clock Groups From f6aa56ac7adec68de7071d3773584cbd45f359e2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 08:18:06 +0000 Subject: [PATCH 042/127] convert firebee1.bdf to vhdl --- FPGA_Quartus_13.1/firebee1.bdf | 5995 -------------------------------- FPGA_Quartus_13.1/firebee1.qsf | 2 +- FPGA_Quartus_13.1/firebee1.vhd | 886 +++++ 3 files changed, 887 insertions(+), 5996 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebee1.bdf create mode 100644 FPGA_Quartus_13.1/firebee1.vhd diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf deleted file mode 100644 index 6addd74..0000000 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ /dev/null @@ -1,5995 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2014 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -//#pragma file_not_in_maxplusii_format -(header "graphic" (version "1.4")) -(properties - (page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n1\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n") -) -(pin - (input) - (rect 208 1392 376 1408) - (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) - (text "FB_ALE" (rect 9 0 51 11)(font "Arial" )) - (pt 168 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 168 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 160 1408 208 1424)) -) -(pin - (input) - (rect 992 936 1160 952) - (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) - (text "nFB_WR" (rect 9 0 55 11)(font "Arial" )) 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1648 1797 1659)(font "Arial" )) - (pt 1672 1664) - (pt 1920 1664) -) -(connector - (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) - (pt 1040 1680) - (pt 1264 1680) -) -(connector - (text "nRP_LDS" (rect 1746 1672 1796 1683)(font "Arial" )) - (pt 1672 1688) - (pt 1920 1688) -) -(connector - (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) - (pt 1040 1704) - (pt 1264 1704) -) -(connector - (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) - (pt 1672 1720) - (pt 1856 1720) -) -(connector - (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) - (pt 1040 1728) - (pt 1264 1728) -) -(connector - (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) - (pt 1040 1752) - (pt 1264 1752) -) -(connector - (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) - (pt 1104 1784) - (pt 1264 1784) -) -(connector - (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) - (pt 1104 1808) - (pt 1264 1808) -) -(connector - (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) - (pt 1104 1832) - (pt 1264 1832) -) -(connector - (text "WR_GATE" (rect 1690 1824 1746 1835)(font "Arial" )) - (pt 1672 1840) - (pt 1800 1840) -) -(connector - (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) - (pt 1128 1856) - (pt 1264 1856) -) -(connector - (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) - (pt 1672 1864) - (pt 1856 1864) -) -(connector - (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) - (pt 1104 1880) - (pt 1264 1880) -) -(connector - (text "YM_QA" (rect 1762 1904 1803 1915)(font "Arial" )) - (pt 1672 1920) - (pt 1928 1920) -) -(connector - (text "YM_QB" (rect 1762 1928 1802 1939)(font "Arial" )) - (pt 1672 1944) - (pt 1928 1944) -) -(connector - (text "YM_QC" (rect 1762 1952 1803 1963)(font "Arial" )) - (pt 1672 1968) - (pt 1928 1968) -) -(connector - (text "SD_CD_DATA3" (rect 1682 1984 1762 1995)(font "Arial" )) - (pt 1672 2000) - (pt 1856 2000) -) -(connector - (text "SD_CDM_D1" (rect 1682 2008 1749 2019)(font "Arial" )) - (pt 1672 2024) - (pt 1856 2024) -) -(connector - (text "SD_CLK" (rect 1682 2032 1728 2043)(font "Arial" )) - (pt 1672 2048) - (pt 1856 2048) -) -(connector - (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) - (pt 1160 920) - (pt 1264 920) -) -(connector - (text "LP_D[7..0]" (rect 1810 800 1863 811)(font "Arial" )) - (pt 1672 816) - (pt 1960 816) - (bus) -) -(connector - (text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" )) - (pt 1672 896) - (pt 1904 896) - (bus) -) -(connector - (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) - (pt 1672 1072) - (pt 1936 1072) - (bus) -) -(connector - (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) - (pt 776 1496) - (pt 1264 1496) -) -(connector - (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) - (pt 1672 760) - (pt 1880 760) -) -(connector - (text "STEP_DIR" (rect 1682 1752 1737 1763)(font "Arial" )) - (pt 1672 1768) - (pt 1856 1768) -) -(connector - (text "WR_DATA" (rect 1682 1800 1738 1811)(font "Arial" )) - (pt 1672 1816) - (pt 1856 1816) -) -(connector - (text "MOT_ON" (rect 1626 1728 1673 1739)(font "Arial" )) - (pt 1672 1744) - (pt 1800 1744) -) -(connector - (text "STEP" (rect 1626 1776 1656 1787)(font "Arial" )) - (pt 1672 1792) - (pt 1800 1792) -) -(connector - (text "HD_DD" (rect 1050 1616 1090 1627)(font "Arial" )) - (pt 1040 1632) - (pt 1264 1632) -) -(connector - (pt 400 248) - (pt 440 248) -) -(connector - (pt 400 160) - (pt 400 248) -) -(connector - (text "nRSTO" (rect 1026 424 1064 435)(font "Arial" )) - (pt 1016 440) - (pt 1104 440) -) -(connector - (pt 920 432) - (pt 952 432) -) -(connector - (pt 760 448) - (pt 952 448) -) -(connector - (pt 824 440) - (pt 952 440) -) -(connector - (pt 1120 328) - (pt 920 328) -) -(connector - (pt 920 328) - (pt 920 432) -) -(connector - (pt 1888 2192) - (pt 1888 2176) -) -(connector - (pt 1848 2176) - (pt 1888 2176) -) -(connector - (pt 1848 2176) - (pt 1848 2208) -) -(connector - (pt 1848 2208) - (pt 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(pt 1160 2424) -) -(connector - (text "nRSTO" (rect 1170 2360 1208 2371)(font "Arial" )) - (pt 1264 2376) - (pt 1160 2376) -) -(connector - (pt 1912 2208) - (pt 1960 2208) -) -(connector - (text "MIDI_IN" (rect 1682 2208 1723 2219)(font "Arial" )) - (pt 1672 2224) - (pt 1864 2224) -) -(connector - (text "nDREQ0" (rect 1674 2120 1720 2131)(font "Arial" )) - (pt 1672 2136) - (pt 1800 2136) -) -(connector - (text "MIDI_OLR" (rect 1682 2272 1736 2283)(font "Arial" )) - (pt 1672 2288) - (pt 1920 2288) -) -(connector - (text "MIDI_TLR" (rect 1682 2232 1733 2243)(font "Arial" )) - (pt 1672 2248) - (pt 1832 2248) -) -(connector - (pt 824 440) - (pt 824 296) -) -(connector - (pt 824 296) - (pt 712 296) -) -(connector - (pt 1120 328) - (pt 1120 48) -) -(connector - (pt 400 -16) - (pt 464 -16) -) -(connector - (pt 400 -280) - (pt 400 -16) -) -(connector - (pt 400 -16) - (pt 400 160) -) -(connector - (pt 736 48) - (pt 1120 48) -) -(connector - (text "CLK25M" (rect 802 -32 846 -21)(font "Arial" )) - (pt 736 -16) - (pt 920 -16) -) -(connector - (text "CLK2M" (rect 810 -8 848 3)(font "Arial" )) - (pt 736 0) - (pt 808 0) -) -(connector - (text "CLK500k" (rect 834 8 881 19)(font "Arial" )) - (pt 736 16) - (pt 832 16) -) -(connector - (text "CLK2M4576" (rect 810 24 872 35)(font "Arial" )) - (pt 736 32) - (pt 808 32) -) -(connector - (text "CLK48M" (rect 722 232 766 243)(font "Arial" )) - (pt 712 248) - (pt 808 248) -) -(connector - (text "FDC_CLK" (rect 786 256 839 267)(font "Arial" )) - (pt 712 264) - (pt 784 264) -) -(connector - (text "CLK24M576" (rect 722 272 784 283)(font "Arial" )) - (pt 816 280) - (pt 712 280) -) -(connector - (text "TIMEBASE[17..0]" (rect 706 2056 792 2067)(font "Arial" )) - (pt 688 2072) - (pt 808 2072) - (bus) -) -(connector - (text "CLK500k" (rect 482 2048 529 2059)(font "Arial" )) - (pt 472 2064) - (pt 544 2064) -) -(connector - (text "FB_AD[31..0]" (rect 1690 8 1756 19)(font "Arial" )) - (pt 1840 24) - (pt 1680 24) - (bus) -) -(connector - (text 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1762 112 1802 123)(font "Arial" )) - (pt 1912 128) - (pt 1680 128) - (bus) -) -(connector - (text "nSYNC" (rect 1690 208 1728 219)(font "Arial" )) - (pt 1832 224) - (pt 1680 224) -) -(connector - (text "nPD_VGA" (rect 1690 256 1744 267)(font "Arial" )) - (pt 1832 272) - (pt 1680 272) -) -(connector - (text "VA[12..0]" (rect 1690 312 1736 323)(font "Arial" )) - (pt 2528 328) - (pt 1680 328) - (bus) -) -(connector - (text "nVWE" (rect 1690 336 1723 347)(font "Arial" )) - (pt 2400 352) - (pt 1680 352) -) -(connector - (text "nFB_CS3" (rect 1194 352 1243 363)(font "Arial" )) - (pt 1176 368) - (pt 1272 368) -) -(connector - (text "nFB_OE" (rect 1178 160 1221 171)(font "Arial" )) - (pt 1272 176) - (pt 1168 176) -) -(connector - (text "FB_ALE" (rect 1202 304 1244 315)(font "Arial" )) - (pt 1272 320) - (pt 1192 320) -) -(connector - (text "DDRCLK[3..0]" (rect 1170 136 1240 147)(font "Arial" )) - (pt 1160 152) - (pt 1272 152) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 1186 112 1275 123)(font "Arial" )) - (pt 1176 128) - (pt 1272 128) -) -(connector - (text "VD[31..0]" (rect 1690 288 1736 299)(font "Arial" )) - (pt 2648 304) - (pt 1680 304) - (bus) -) -(connector - (text "nVCAS" (rect 1698 360 1735 371)(font "Arial" )) - (pt 2304 376) - (pt 1680 376) -) -(connector - (text "nVRAS" (rect 1698 384 1735 395)(font "Arial" )) - (pt 2208 400) - (pt 1680 400) -) -(connector - (text "nVCS" (rect 1698 408 1728 419)(font "Arial" )) - (pt 2040 424) - (pt 1680 424) -) -(connector - (text "VCKE" (rect 1698 432 1729 443)(font "Arial" )) - (pt 1944 448) - (pt 1680 448) -) -(connector - (text "VSYNC" (rect 1690 136 1730 147)(font "Arial" )) - (pt 1680 152) - (pt 1840 152) -) -(connector - (text "HSYNC" (rect 1690 160 1730 171)(font "Arial" )) - (pt 1680 176) - (pt 1840 176) -) -(connector - (text "CLK25M" (rect 1210 608 1254 619)(font "Arial" )) - (pt 1200 624) - (pt 1272 624) -) -(connector - (text "Video_TA" (rect 1690 696 1740 707)(font "Arial" )) - (pt 1880 712) - (pt 1680 712) -) -(connector - (text "MAIN_CLK" (rect 1194 88 1251 99)(font "Arial" )) - (pt 1192 104) - (pt 1272 104) -) -(connector - (text "nRSTO" (rect 1202 40 1240 51)(font "Arial" )) - (pt 1192 56) - (pt 1272 56) -) -(connector - (text "BA[1..0]" (rect 1690 456 1730 467)(font "Arial" )) - (pt 1832 472) - (pt 1680 472) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 1690 232 1751 243)(font "Arial" )) - (pt 1752 248) - (pt 1680 248) -) -(connector - (text "VR_D[8..0]" (rect 1178 464 1232 475)(font "Arial" )) - (pt 1152 480) - (pt 1272 480) - (bus) -) -(connector - (pt 1888 544) - (pt 1680 544) - (bus) -) -(connector - (pt 1888 568) - (pt 1888 544) - (bus) -) -(connector - (pt 1960 520) - (pt 1680 520) - (bus) -) -(connector - (pt 1960 544) - (pt 1960 520) - (bus) -) -(connector - (text "VIDEO_RECONFIG" (rect 1682 560 1782 571)(font "Arial" )) - (pt 1680 576) - (pt 1800 576) -) -(connector - (text "VR_WR" (rect 1706 592 1747 603)(font "Arial" )) - (pt 1680 608) - (pt 1800 608) -) -(connector - (text "VR_BUSY" (rect 1178 448 1232 459)(font "Arial" )) - (pt 1152 464) - (pt 1272 464) -) -(connector - (text "VR_RD" (rect 1706 576 1744 587)(font "Arial" )) - (pt 1800 592) - (pt 1680 592) -) -(connector - (text "CLK_VIDEO" (rect 1170 552 1233 563)(font "Arial" )) - (pt 984 568) - (pt 1272 568) -) -(connector - (text "CLK33M" (rect 1210 584 1254 595)(font "Arial" )) - (pt 1272 600) - (pt 1200 600) -) -(junction (pt 2504 760)) -(junction (pt 1856 -64)) -(junction (pt 2424 -80)) -(junction (pt 400 -280)) -(junction (pt 400 160)) -(junction (pt 1848 2208)) -(junction (pt 400 -16)) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 17afb0a..94b33d9 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -670,10 +670,10 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name VHDL_FILE firebee1.vhd set_global_assignment -name SDC_FILE firebee1.sdc set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name BDF_FILE firebee1.bdf set_global_assignment -name BDF_FILE Video/video.bdf set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd new file mode 100644 index 0000000..64d0c8a --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -0,0 +1,886 @@ +LIBRARY ieee; + USE ieee.std_logic_1164.all; + +LIBRARY work; + +ENTITY firebee1 IS + PORT + ( + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CF_CARD : IN std_logic; + TRACK00 : IN std_logic; + nWP : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + nSCSI_DRQ : IN std_logic; + SD_WP : IN std_logic; + nRD_DATA : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + nSCSI_MSG : IN std_logic; + nDACK0 : IN std_logic; + PIC_INT : IN std_logic; + nFB_OE : IN std_logic; + TOUT0 : IN std_logic; + nMASTER : IN std_logic; + DVI_INT : IN std_logic; + nDACK1 : IN std_logic; + nPCI_INTD : IN std_logic; + nPCI_INTC : IN std_logic; + nPCI_INTB : IN std_logic; + nPCI_INTA : IN std_logic; + E0_INT : IN std_logic; + nINDEX : IN std_logic; + HD_DD : IN std_logic; + MAIN_CLK : IN std_logic; + nRSTO_MCF : IN std_logic; + CLK33MDIR : IN std_logic; + SCSI_PAR : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CMD_D1 : INOUT std_logic; + MIDI_IN_PIN : INOUT std_logic; + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + IO : INOUT std_logic_vector(17 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SRD : INOUT std_logic_vector(15 DOWNTO 0); + VD : INOUT std_logic_vector(31 DOWNTO 0); + VDQS : INOUT std_logic_vector(3 DOWNTO 0); + LP_STR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + MIDI_TLR : OUT std_logic; + TxD : OUT std_logic; + RTS : OUT std_logic; + DTR : OUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + nIDE_CS0 : OUT std_logic; + nIDE_CS1 : OUT std_logic; + nIDE_WR : OUT std_logic; + nIDE_RD : OUT std_logic; + nCF_CS0 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nROM3 : OUT std_logic; + nROM4 : OUT std_logic; + nRP_UDS : OUT std_logic; + nRP_LDS : OUT std_logic; + nSDSEL : OUT std_logic; + nWR_GATE : OUT std_logic; + nWR : OUT std_logic; + YM_QA : OUT std_logic; + YM_QB : OUT std_logic; + YM_QC : OUT std_logic; + SD_CLK : OUT std_logic; + DSA_D : OUT std_logic; + nVWE : OUT std_logic; + nVCAS : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + nPD_VGA : OUT std_logic; + TIN0 : OUT std_logic; + nSRCS : OUT std_logic; + nSRBLE : OUT std_logic; + nSRBHE : OUT std_logic; + nSRWE : OUT std_logic; + nDREQ1 : OUT std_logic; + LED_FPGA_OK : OUT std_logic; + nSROE : OUT std_logic; + VCKE : OUT std_logic; + nFB_TA : OUT std_logic; + nDDR_CLK : OUT std_logic; + DDR_CLK : OUT std_logic; + VSYNC_PAD : OUT std_logic; + HSYNC_PAD : OUT std_logic; + nBLANK_PAD : OUT std_logic; + PIXEL_CLK_PAD : OUT std_logic; + nSYNC : OUT std_logic; + nMOT_ON : OUT std_logic; + nSTEP_DIR : OUT std_logic; + nSTEP : OUT std_logic; + LPDIR : OUT std_logic; + MIDI_OLR : OUT std_logic; + CLK25M : OUT std_logic; + CLKUSB : OUT std_logic; + CLK24M576 : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + nIRQ : OUT std_logic_vector(7 DOWNTO 2); + VA : OUT std_logic_vector(12 DOWNTO 0); + VB : OUT std_logic_vector(7 DOWNTO 0); + VDM : OUT std_logic_vector(3 DOWNTO 0); + VG : OUT std_logic_vector(7 DOWNTO 0); + VR : OUT std_logic_vector(7 DOWNTO 0) + ); +END firebee1; + +ARCHITECTURE rtl OF firebee1 IS + +COMPONENT altpll3 + PORT + ( + inclk0 : IN std_logic; + c0 : OUT std_logic; + c1 : OUT std_logic; + c2 : OUT std_logic; + c3 : OUT std_logic; + locked : OUT std_logic + ); +END COMPONENT; + +COMPONENT altpll2 + PORT + ( + inclk0 : IN std_logic; + c0 : OUT std_logic; + c1 : OUT std_logic; + c2 : OUT std_logic; + c3 : OUT std_logic; + c4 : OUT std_logic + ); +END COMPONENT; + +COMPONENT dsp + PORT + ( + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_OE : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + nRSTO : IN std_logic; + nFB_CS3 : IN std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + IO : INOUT std_logic_vector(17 DOWNTO 0); + SRD : INOUT std_logic_vector(15 DOWNTO 0); + nSRCS : OUT std_logic; + nSRBLE : OUT std_logic; + nSRBHE : OUT std_logic; + nSRWE : OUT std_logic; + nSROE : OUT std_logic; + DSP_INT : OUT std_logic; + DSP_TA : OUT std_logic + ); +END COMPONENT; + +COMPONENT falconio_sdcard_ide_cf + PORT + ( + CLK33M : IN std_logic; + MAIN_CLK : IN std_logic; + CLK2M : IN std_logic; + CLK500k : IN std_logic; + nFB_CS1 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + nSCSI_DRQ : IN std_logic; + nSCSI_MSG : IN std_logic; + MIDI_IN : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CS_CARD : IN std_logic; + nINDEX : IN std_logic; + TRACK00 : IN std_logic; + nRD_DATA : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + SD_WP : IN std_logic; + nDACK0 : IN std_logic; + nFB_WR : IN std_logic; + WP_CF_CARD : IN std_logic; + nWP : IN std_logic; + nFB_CS2 : IN std_logic; + nRSTO : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + CLK2M4576 : IN std_logic; + nFB_OE : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DSP_INT : IN std_logic; + nBLANK : IN std_logic; + FDC_CLK : IN std_logic; + FB_ALE : IN std_logic; + HD_DD : IN std_logic; + SCSI_PAR : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CDM_D1 : INOUT std_logic; + ACP_CONF : IN std_logic_vector(31 DOWNTO 24); + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + nIDE_CS1 : OUT std_logic; + nIDE_CS0 : OUT std_logic; + LP_STR : OUT std_logic; + LP_DIR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + SD_CLK : OUT std_logic; + YM_QA : OUT std_logic; + YM_QC : OUT std_logic; + YM_QB : OUT std_logic; + nSDSEL : OUT std_logic; + STEP : OUT std_logic; + MOT_ON : OUT std_logic; + nRP_LDS : OUT std_logic; + nRP_UDS : OUT std_logic; + nROM4 : OUT std_logic; + nROM3 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nCF_CS0 : OUT std_logic; + nIDE_RD : OUT std_logic; + nIDE_WR : OUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + DTR : OUT std_logic; + RTS : OUT std_logic; + TxD : OUT std_logic; + MIDI_OLR : OUT std_logic; + nDREQ0 : OUT std_logic; + DSA_D : OUT std_logic; + nMFP_INT : OUT std_logic; + FALCON_IO_TA : OUT std_logic; + STEP_DIR : OUT std_logic; + WR_DATA : OUT std_logic; + WR_GATE : OUT std_logic; + DMA_DRQ : OUT std_logic; + MIDI_TLR : OUT std_logic + ); +END COMPONENT; + +COMPONENT interrupt_handler + PORT + ( + MAIN_CLK : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + PIC_INT : IN std_logic; + E0_INT : IN std_logic; + DVI_INT : IN std_logic; + nPCI_INTA : IN std_logic; + nPCI_INTB : IN std_logic; + nPCI_INTC : IN std_logic; + nPCI_INTD : IN std_logic; + nMFP_INT : IN std_logic; + nFB_OE : IN std_logic; + DSP_INT : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DMA_DRQ : IN std_logic; + nRSTO : IN std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + INT_HANDLER_TA : OUT std_logic; + TIN0 : OUT std_logic; + ACP_CONF : OUT std_logic_vector(31 DOWNTO 0); + nIRQ : OUT std_logic_vector(7 DOWNTO 2) + ); +END COMPONENT; + +COMPONENT altpll1 + PORT + ( + inclk0 : IN std_logic; + c0 : OUT std_logic; + c1 : OUT std_logic; + c2 : OUT std_logic; + locked : OUT std_logic + ); +END COMPONENT; + +COMPONENT altpll_reconfig1 + PORT + ( + reconfig : IN std_logic; + read_param : IN std_logic; + write_param : IN std_logic; + pll_scandataout : IN std_logic; + pll_scandone : IN std_logic; + clock : IN std_logic; + reset : IN std_logic; + pll_areset_in : IN std_logic; + counter_param : IN std_logic_vector(2 DOWNTO 0); + counter_type : IN std_logic_vector(3 DOWNTO 0); + data_in : IN std_logic_vector(8 DOWNTO 0); + busy : OUT std_logic; + pll_scandata : OUT std_logic; + pll_scanclk : OUT std_logic; + pll_scanclkena : OUT std_logic; + pll_configupdate : OUT std_logic; + pll_areset : OUT std_logic; + data_out : OUT std_logic_vector(8 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT video + PORT + ( + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + nFB_OE : IN std_logic; + FB_ALE : IN std_logic; + DDR_SYNC_66M : IN std_logic; + CLK33M : IN std_logic; + CLK25M : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_BUSY : IN std_logic; + DDRCLK : IN std_logic_vector(3 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VD : INOUT std_logic_vector(31 DOWNTO 0); + VDQS : INOUT std_logic_vector(3 DOWNTO 0); + VR_D : IN std_logic_vector(8 DOWNTO 0); + VR_RD : OUT std_logic; + nBLANK : OUT std_logic; + nVWE : OUT std_logic; + nVCAS : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + nPD_VGA : OUT std_logic; + VCKE : OUT std_logic; + VSYNC : OUT std_logic; + HSYNC : OUT std_logic; + nSYNC : OUT std_logic; + VIDEO_TA : OUT std_logic; + PIXEL_CLK : OUT std_logic; + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + VA : OUT std_logic_vector(12 DOWNTO 0); + VB : OUT std_logic_vector(7 DOWNTO 0); + VDM : OUT std_logic_vector(3 DOWNTO 0); + VG : OUT std_logic_vector(7 DOWNTO 0); + VR : OUT std_logic_vector(7 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT altpll4 + PORT(inclk0 : IN std_logic; + areset : IN std_logic; + scanclk : IN std_logic; + scandata : IN std_logic; + scanclkena : IN std_logic; + configupdate : IN std_logic; + c0 : OUT std_logic; + scandataout : OUT std_logic; + scandone : OUT std_logic; + locked : OUT std_logic + ); +END COMPONENT; + +COMPONENT lpm_ff0 + PORT(clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_counter0 + PORT(clock : IN std_logic; + q : OUT std_logic_vector(17 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT alt_iobuf + PORT(i : IN std_logic; + oe : IN std_logic; + io : INOUT std_logic; + o : OUT std_logic + ); +END COMPONENT; + +COMPONENT altddio_out3 + PORT(datain_h : IN std_logic; + datain_l : IN std_logic; + outclock : IN std_logic; + dataout : OUT std_logic + ); +END COMPONENT; + +SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0); +SIGNAL CLK25M_ALTERA_SYNTHESIZED : std_logic; +SIGNAL CLK2M : std_logic; +SIGNAL CLK2M4576 : std_logic; +SIGNAL CLK33M : std_logic; +SIGNAL CLK48M : std_logic; +SIGNAL CLK500k : std_logic; +SIGNAL CLK_VIDEO : std_logic; +SIGNAL DDR_SYNC_66M : std_logic; +SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); +SIGNAL DMA_DRQ : std_logic; +SIGNAL DSP_INT : std_logic; +SIGNAL DSP_TA : std_logic; +SIGNAL FALCON_IO_TA : std_logic; +SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0); +SIGNAL FDC_CLK : std_logic; +SIGNAL HSYNC : std_logic; +SIGNAL INT_HANDLER_TA : std_logic; +SIGNAL LP_DIR : std_logic; +SIGNAL MIDI_IN : std_logic; +SIGNAL MOT_ON : std_logic; +SIGNAL nBLANK : std_logic; +SIGNAL nDREQ0 : std_logic; +SIGNAL nMFP_INT : std_logic; +SIGNAL nRSTO : std_logic; +SIGNAL PIXEL_CLK : std_logic; +SIGNAL SD_CDM_D1 : std_logic; +SIGNAL STEP : std_logic; +SIGNAL STEP_DIR : std_logic; +SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0); +SIGNAL VIDEO_RECONFIG : std_logic; +SIGNAL Video_TA : std_logic; +SIGNAL VR_BUSY : std_logic; +SIGNAL VR_D : std_logic_vector(8 DOWNTO 0); +SIGNAL VR_RD : std_logic; +SIGNAL VR_WR : std_logic; +SIGNAL VSYNC : std_logic; +SIGNAL WR_DATA : std_logic; +SIGNAL WR_GATE : std_logic; +SIGNAL SYNTHESIZED_WIRE_0 : std_logic; +SIGNAL SYNTHESIZED_WIRE_1 : std_logic; +SIGNAL SYNTHESIZED_WIRE_2 : std_logic; +SIGNAL SYNTHESIZED_WIRE_3 : std_logic; +SIGNAL SYNTHESIZED_WIRE_4 : std_logic; +SIGNAL SYNTHESIZED_WIRE_5 : std_logic; +SIGNAL SYNTHESIZED_WIRE_6 : std_logic; +SIGNAL SYNTHESIZED_WIRE_7 : std_logic; +SIGNAL SYNTHESIZED_WIRE_8 : std_logic; +SIGNAL SYNTHESIZED_WIRE_9 : std_logic; +SIGNAL SYNTHESIZED_WIRE_10 : std_logic; +SIGNAL SYNTHESIZED_WIRE_11 : std_logic; + + +BEGIN +nDREQ1 <= nDACK1; +SYNTHESIZED_WIRE_10 <= '0'; +SYNTHESIZED_WIRE_11 <= '1'; + + + +i_atari_clk_pll : altpll3 +PORT MAP(inclk0 => MAIN_CLK, + c0 => CLK25M_ALTERA_SYNTHESIZED, + c1 => CLK2M, + c2 => CLK500k, + c3 => CLK2M4576, + locked => SYNTHESIZED_WIRE_8); + + +i_ddr_clk_pll : altpll2 +PORT MAP(inclk0 => MAIN_CLK, + c0 => DDRCLK(0), + c1 => DDRCLK(1), + c2 => DDRCLK(2), + c3 => DDRCLK(3), + c4 => DDR_SYNC_66M); + + +i_dsp : dsp +PORT MAP(CLK33M => CLK33M, + MAIN_CLK => MAIN_CLK, + nFB_OE => nFB_OE, + nFB_WR => nFB_WR, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + nRSTO => nRSTO, + nFB_CS3 => nFB_CS3, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + IO => IO, + SRD => SRD, + nSRCS => nSRCS, + nSRBLE => nSRBLE, + nSRBHE => nSRBHE, + nSRWE => nSRWE, + nSROE => nSROE, + DSP_INT => DSP_INT, + DSP_TA => DSP_TA); + + +i_falcioio_sdcard_ide_cf : falconio_sdcard_ide_cf +PORT MAP(CLK33M => CLK33M, + MAIN_CLK => MAIN_CLK, + CLK2M => CLK2M, + CLK500k => CLK500k, + nFB_CS1 => nFB_CS1, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + LP_BUSY => LP_BUSY, + nACSI_DRQ => nACSI_DRQ, + nACSI_INT => nACSI_INT, + nSCSI_DRQ => nSCSI_DRQ, + nSCSI_MSG => nSCSI_MSG, + MIDI_IN => MIDI_IN, + RxD => RxD, + CTS => CTS, + RI => RI, + DCD => DCD, + AMKB_RX => AMKB_RX, + PIC_AMKB_RX => PIC_AMKB_RX, + IDE_RDY => IDE_RDY, + IDE_INT => IDE_INT, + WP_CS_CARD => '0', + nINDEX => nINDEX, + TRACK00 => TRACK00, + nRD_DATA => nRD_DATA, + nDCHG => nDCHG, + SD_DATA0 => SD_DATA0, + SD_DATA1 => SD_DATA1, + SD_DATA2 => SD_DATA2, + SD_CARD_DEDECT => SD_CARD_DEDECT, + SD_WP => SD_WP, + nDACK0 => nDACK0, + nFB_WR => nFB_WR, + WP_CF_CARD => WP_CF_CARD, + nWP => nWP, + nFB_CS2 => nFB_CS2, + nRSTO => nRSTO, + nSCSI_C_D => nSCSI_C_D, + nSCSI_I_O => nSCSI_I_O, + CLK2M4576 => CLK2M4576, + nFB_OE => nFB_OE, + VSYNC => VSYNC, + HSYNC => HSYNC, + DSP_INT => DSP_INT, + nBLANK => nBLANK, + FDC_CLK => FDC_CLK, + FB_ALE => FB_ALE, + HD_DD => HD_DD, + SCSI_PAR => SCSI_PAR, + nSCSI_SEL => nSCSI_SEL, + nSCSI_BUSY => nSCSI_BUSY, + nSCSI_RST => nSCSI_RST, + SD_CD_DATA3 => SD_CD_DATA3, + SD_CDM_D1 => SD_CDM_D1, + ACP_CONF => ACP_CONF(31 DOWNTO 24), + ACSI_D => ACSI_D, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + LP_D => LP_D, + SCSI_D => SCSI_D, + nIDE_CS1 => nIDE_CS1, + nIDE_CS0 => nIDE_CS0, + LP_STR => LP_STR, + LP_DIR => LP_DIR, + nACSI_ACK => nACSI_ACK, + nACSI_RESET => nACSI_RESET, + nACSI_CS => nACSI_CS, + ACSI_DIR => ACSI_DIR, + ACSI_A1 => ACSI_A1, + nSCSI_ACK => nSCSI_ACK, + nSCSI_ATN => nSCSI_ATN, + SCSI_DIR => SCSI_DIR, + SD_CLK => SD_CLK, + YM_QA => YM_QA, + YM_QC => YM_QC, + YM_QB => YM_QB, + nSDSEL => nSDSEL, + STEP => STEP, + MOT_ON => MOT_ON, + nRP_LDS => nRP_LDS, + nRP_UDS => nRP_UDS, + nROM4 => nROM4, + nROM3 => nROM3, + nCF_CS1 => nCF_CS1, + nCF_CS0 => nCF_CS0, + nIDE_RD => nIDE_RD, + nIDE_WR => nIDE_WR, + AMKB_TX => AMKB_TX, + IDE_RES => IDE_RES, + DTR => DTR, + RTS => RTS, + TxD => TxD, + MIDI_OLR => MIDI_OLR, + DSA_D => DSA_D, + nMFP_INT => nMFP_INT, + FALCON_IO_TA => FALCON_IO_TA, + STEP_DIR => STEP_DIR, + WR_DATA => WR_DATA, + WR_GATE => WR_GATE, + DMA_DRQ => DMA_DRQ, + MIDI_TLR => MIDI_TLR); + + +i_interrupt_handler : interrupt_handler +PORT MAP(MAIN_CLK => MAIN_CLK, + nFB_WR => nFB_WR, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + PIC_INT => PIC_INT, + E0_INT => E0_INT, + DVI_INT => DVI_INT, + nPCI_INTA => nPCI_INTA, + nPCI_INTB => nPCI_INTB, + nPCI_INTC => nPCI_INTC, + nPCI_INTD => nPCI_INTD, + nMFP_INT => nMFP_INT, + nFB_OE => nFB_OE, + DSP_INT => DSP_INT, + VSYNC => VSYNC, + HSYNC => HSYNC, + DMA_DRQ => DMA_DRQ, + nRSTO => nRSTO, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + INT_HANDLER_TA => INT_HANDLER_TA, + TIN0 => TIN0, + ACP_CONF => ACP_CONF, + nIRQ => nIRQ); + + +i_mfp_acia_clk_pll : altpll1 +PORT MAP(inclk0 => MAIN_CLK, + c0 => CLK48M, + c1 => FDC_CLK, + c2 => CLK24M576, + locked => SYNTHESIZED_WIRE_9); + + +i_pll_reconfig : altpll_reconfig1 +PORT MAP(reconfig => VIDEO_RECONFIG, + read_param => VR_RD, + write_param => VR_WR, + pll_areset_in => '0', + pll_scandataout => SYNTHESIZED_WIRE_0, + pll_scandone => SYNTHESIZED_WIRE_1, + clock => MAIN_CLK, + reset => SYNTHESIZED_WIRE_2, + counter_param => FB_ADR(8 DOWNTO 6), + counter_type => FB_ADR(5 DOWNTO 2), + data_in => FB_AD(24 DOWNTO 16), + busy => VR_BUSY, + pll_scandata => SYNTHESIZED_WIRE_5, + pll_scanclk => SYNTHESIZED_WIRE_4, + pll_scanclkena => SYNTHESIZED_WIRE_6, + pll_configupdate => SYNTHESIZED_WIRE_7, + pll_areset => SYNTHESIZED_WIRE_3, + data_out => VR_D); + + +i_video : video +PORT MAP(MAIN_CLK => MAIN_CLK, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_WR => nFB_WR, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nRSTO => nRSTO, + nFB_OE => nFB_OE, + FB_ALE => FB_ALE, + DDR_SYNC_66M => DDR_SYNC_66M, + CLK33M => CLK33M, + CLK25M => CLK25M_ALTERA_SYNTHESIZED, + CLK_VIDEO => CLK_VIDEO, + VR_BUSY => VR_BUSY, + DDRCLK => DDRCLK, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VD => VD, + VDQS => VDQS, + VR_D => VR_D, + VR_RD => VR_RD, + nBLANK => nBLANK, + nVWE => nVWE, + nVCAS => nVCAS, + nVRAS => nVRAS, + nVCS => nVCS, + nPD_VGA => nPD_VGA, + VCKE => VCKE, + VSYNC => VSYNC, + HSYNC => HSYNC, + nSYNC => nSYNC, + VIDEO_TA => Video_TA, + PIXEL_CLK => PIXEL_CLK, + VIDEO_RECONFIG => VIDEO_RECONFIG, + VR_WR => VR_WR, + BA => BA, + VA => VA, + VB => VB, + VDM => VDM, + VG => VG, + VR => VR); + + +i_video_clk_pll : altpll4 +PORT MAP(inclk0 => CLK48M, + areset => SYNTHESIZED_WIRE_3, + scanclk => SYNTHESIZED_WIRE_4, + scandata => SYNTHESIZED_WIRE_5, + scanclkena => SYNTHESIZED_WIRE_6, + configupdate => SYNTHESIZED_WIRE_7, + c0 => CLK_VIDEO, + scandataout => SYNTHESIZED_WIRE_0, + scandone => SYNTHESIZED_WIRE_1); + + +inst1 : lpm_ff0 +PORT MAP(clock => DDR_SYNC_66M, + enable => FB_ALE, + data => FB_AD, + q => FB_ADR); + + + + +nMOT_ON <= NOT(MOT_ON); + + + +nSTEP_DIR <= NOT(STEP_DIR); + + + +nSTEP <= NOT(STEP); + + + +nWR <= NOT(WR_DATA); + + + +inst18 : lpm_counter0 +PORT MAP(clock => CLK500k, + q => TIMEBASE); + + +nWR_GATE <= NOT(WR_GATE); + + + +nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA); + +CLK33M <= MAIN_CLK; + + + +SYNTHESIZED_WIRE_2 <= NOT(nRSTO); + + + +nRSTO <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_9 AND nRSTO_MCF; + + +inst29 : alt_iobuf +PORT MAP(i => CLK2M, + oe => CLK2M, + io => MIDI_IN_PIN, + o => MIDI_IN); + +LED_FPGA_OK <= TIMEBASE(17); + + + +nDDR_CLK <= NOT(DDRCLK(0)); + + + +inst5 : altddio_out3 +PORT MAP(datain_h => VSYNC, + datain_l => VSYNC, + outclock => PIXEL_CLK, + dataout => VSYNC_PAD); + + +inst6 : altddio_out3 +PORT MAP(datain_h => HSYNC, + datain_l => HSYNC, + outclock => PIXEL_CLK, + dataout => HSYNC_PAD); + + +inst8 : altddio_out3 +PORT MAP(datain_h => nBLANK, + datain_l => nBLANK, + outclock => PIXEL_CLK, + dataout => nBLANK_PAD); + + +inst9 : altddio_out3 +PORT MAP(datain_h => SYNTHESIZED_WIRE_10, + datain_l => SYNTHESIZED_WIRE_11, + outclock => PIXEL_CLK, + dataout => PIXEL_CLK_PAD); + +SD_CMD_D1 <= SD_CDM_D1; +DDR_CLK <= DDRCLK(0); +LPDIR <= LP_DIR; +CLK25M <= CLK25M_ALTERA_SYNTHESIZED; +CLKUSB <= CLK48M; + +END rtl; \ No newline at end of file From 98a362dc908092649a80b0b427bf8b3b66f88b12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 08:43:42 +0000 Subject: [PATCH 043/127] replace video.bdf with video.vhd --- FPGA_Quartus_13.1/Video/mux41.vhd | 90 + FPGA_Quartus_13.1/Video/mux41_0.vhd | 54 + FPGA_Quartus_13.1/Video/mux41_1.vhd | 54 + FPGA_Quartus_13.1/Video/mux41_2.vhd | 55 + FPGA_Quartus_13.1/Video/mux41_3.vhd | 55 + FPGA_Quartus_13.1/Video/mux41_4.vhd | 55 + FPGA_Quartus_13.1/Video/mux41_5.vhd | 56 + FPGA_Quartus_13.1/Video/video.bdf | 10679 -------------------------- FPGA_Quartus_13.1/Video/video.vhd | 1768 +++++ FPGA_Quartus_13.1/firebee1.qsf | 9 +- 10 files changed, 2195 insertions(+), 10680 deletions(-) create mode 100644 FPGA_Quartus_13.1/Video/mux41.vhd create mode 100644 FPGA_Quartus_13.1/Video/mux41_0.vhd create mode 100644 FPGA_Quartus_13.1/Video/mux41_1.vhd create mode 100644 FPGA_Quartus_13.1/Video/mux41_2.vhd create mode 100644 FPGA_Quartus_13.1/Video/mux41_3.vhd create mode 100644 FPGA_Quartus_13.1/Video/mux41_4.vhd create mode 100644 FPGA_Quartus_13.1/Video/mux41_5.vhd delete mode 100644 FPGA_Quartus_13.1/Video/video.bdf create mode 100644 FPGA_Quartus_13.1/Video/video.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41.vhd b/FPGA_Quartus_13.1/Video/mux41.vhd new file mode 100644 index 0000000..5a51a23 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41.vhd @@ -0,0 +1,90 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:37:12 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY work; + +ENTITY mux41 IS + PORT + ( + S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D0 : IN STD_LOGIC; + D1 : IN STD_LOGIC; + D3 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + Q : OUT STD_LOGIC + ); +END mux41; + +ARCHITECTURE bdf_type OF mux41 IS + +SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC; + + +BEGIN + + + +SYNTHESIZED_WIRE_18 <= NOT(S0); + + + +SYNTHESIZED_WIRE_21 <= NOT(SYNTHESIZED_WIRE_18); + + + +SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_18 AND D0; + + +SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_21 AND D1; + + +SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_18 AND D2; + + +SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_21 AND D3; + + +Q <= SYNTHESIZED_WIRE_13 OR SYNTHESIZED_WIRE_14 OR SYNTHESIZED_WIRE_15 OR SYNTHESIZED_WIRE_16; + + +SYNTHESIZED_WIRE_19 <= NOT(INH); + + + +SYNTHESIZED_WIRE_20 <= NOT(S1); + + + +SYNTHESIZED_WIRE_22 <= NOT(SYNTHESIZED_WIRE_20); + + + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/mux41_0.vhd b/FPGA_Quartus_13.1/Video/mux41_0.vhd new file mode 100644 index 0000000..5fa086e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41_0.vhd @@ -0,0 +1,54 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera; +USE altera.maxplus2.all; + +LIBRARY work; + +ENTITY mux41_0 IS +PORT +( + S0 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC +); +END mux41_0; + +ARCHITECTURE bdf_type OF mux41_0 IS +BEGIN + +-- instantiate macrofunction + +b2v_inst40 : work.mux41 +PORT MAP(S0 => S0, + S1 => S1, + D0 => D0, + INH => INH, + D1 => D1, + D2 => '0', + D3 => '0', + Q => Q); + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/mux41_1.vhd b/FPGA_Quartus_13.1/Video/mux41_1.vhd new file mode 100644 index 0000000..0feca80 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41_1.vhd @@ -0,0 +1,54 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera; +USE altera.maxplus2.all; + +LIBRARY work; + +ENTITY mux41_1 IS +PORT +( + S0 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC +); +END mux41_1; + +ARCHITECTURE bdf_type OF mux41_1 IS +BEGIN + +-- instantiate macrofunction + +b2v_inst41 : work.mux41 +PORT MAP(S0 => S0, + S1 => S1, + D0 => D0, + INH => INH, + D1 => D1, + D2 => '0', + D3 => '0', + Q => Q); + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/mux41_2.vhd b/FPGA_Quartus_13.1/Video/mux41_2.vhd new file mode 100644 index 0000000..6e8f4ae --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41_2.vhd @@ -0,0 +1,55 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera; +USE altera.maxplus2.all; + +LIBRARY work; + +ENTITY mux41_2 IS +PORT +( + S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC +); +END mux41_2; + +ARCHITECTURE bdf_type OF mux41_2 IS +BEGIN + +-- instantiate macrofunction + +b2v_inst42 : work.mux41 +PORT MAP(S0 => S0, + D2 => D2, + S1 => S1, + D0 => D0, + D3 => '0', + INH => INH, + D1 => D1, + Q => Q); + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/mux41_3.vhd b/FPGA_Quartus_13.1/Video/mux41_3.vhd new file mode 100644 index 0000000..a8c762c --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41_3.vhd @@ -0,0 +1,55 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera; +USE altera.maxplus2.all; + +LIBRARY work; + +ENTITY mux41_3 IS +PORT +( + S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC +); +END mux41_3; + +ARCHITECTURE bdf_type OF mux41_3 IS +BEGIN + +-- instantiate macrofunction + +b2v_inst43 : work.mux41 +PORT MAP(S0 => S0, + D2 => D2, + S1 => S1, + D0 => D0, + D3 => '0', + INH => INH, + D1 => D1, + Q => Q); + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/mux41_4.vhd b/FPGA_Quartus_13.1/Video/mux41_4.vhd new file mode 100644 index 0000000..f1c9027 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41_4.vhd @@ -0,0 +1,55 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera; +USE altera.maxplus2.all; + +LIBRARY work; + +ENTITY mux41_4 IS +PORT +( + S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC +); +END mux41_4; + +ARCHITECTURE bdf_type OF mux41_4 IS +BEGIN + +-- instantiate macrofunction + +b2v_inst44 : work.mux41 +PORT MAP(S0 => S0, + D2 => D2, + S1 => S1, + D0 => D0, + D3 => '0', + INH => INH, + D1 => D1, + Q => Q); + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/mux41_5.vhd b/FPGA_Quartus_13.1/Video/mux41_5.vhd new file mode 100644 index 0000000..0fc955e --- /dev/null +++ b/FPGA_Quartus_13.1/Video/mux41_5.vhd @@ -0,0 +1,56 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera; +USE altera.maxplus2.all; + +LIBRARY work; + +ENTITY mux41_5 IS +PORT +( + S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC +); +END mux41_5; + + +ARCHITECTURE bdf_type OF mux41_5 IS +BEGIN + +-- instantiate macrofunction + +b2v_inst45 : work.mux41 +PORT MAP(S0 => S0, + D2 => D2, + S1 => S1, + D0 => D0, + D3 => '0', + INH => INH, + D1 => D1, + Q => Q); + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/video.bdf b/FPGA_Quartus_13.1/Video/video.bdf deleted file mode 100644 index 83f2f08..0000000 --- a/FPGA_Quartus_13.1/Video/video.bdf +++ /dev/null @@ -1,10679 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2014 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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(pt 192 2080) - (pt 296 2080) -) -(connector - (text "nFB_CS3" (rect 202 2088 251 2099)(font "Arial" )) - (pt 192 2104) - (pt 296 2104) -) -(connector - (text "nFB_WR" (rect 202 2112 248 2123)(font "Arial" )) - (pt 192 2128) - (pt 296 2128) -) -(connector - (text "FB_SIZE0" (rect 202 2136 253 2147)(font "Arial" )) - (pt 192 2152) - (pt 296 2152) -) -(connector - (text "FB_SIZE1" (rect 202 2160 252 2171)(font "Arial" )) - (pt 192 2176) - (pt 296 2176) -) -(connector - (text "nFB_OE" (rect 202 2184 245 2195)(font "Arial" )) - (pt 192 2200) - (pt 296 2200) -) -(connector - (text "nVWE" (rect 570 2192 603 2203)(font "Arial" )) - (pt 632 2208) - (pt 560 2208) -) -(connector - (text "nVCAS" (rect 570 2216 607 2227)(font "Arial" )) - (pt 632 2232) - (pt 560 2232) -) -(connector - (text "nVRAS" (rect 570 2240 607 2251)(font "Arial" )) - (pt 632 2256) - (pt 560 2256) -) -(connector - (text "nVCS" (rect 570 2264 600 2275)(font "Arial" )) - (pt 632 2280) - (pt 560 2280) -) -(connector - (text "VCKE" (rect 570 2288 601 2299)(font "Arial" )) - (pt 632 2304) - (pt 560 2304) -) -(connector - (text "MAIN_CLK" (rect 202 1944 259 1955)(font "Arial" )) - (pt 296 1960) - (pt 192 1960) -) -(connector - (text "FB_ALE" (rect 202 2016 244 2027)(font "Arial" )) - (pt 296 2032) - (pt 192 2032) -) -(connector - (text "FB_LE[3..0]" (rect 570 1976 629 1987)(font "Arial" )) - (pt 560 1992) - (pt 680 1992) - (bus) -) -(connector - (text "FB_VDOE[3..0]" (rect 570 2000 646 2011)(font "Arial" )) - (pt 560 2016) - (pt 680 2016) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 210 1968 299 1979)(font "Arial" )) - (pt 200 1984) - (pt 296 1984) -) -(connector - (text "FB_ADR[31..0]" (rect 202 1992 276 2003)(font "Arial" )) - (pt 192 2008) - (pt 296 2008) - (bus) -) -(connector - (text "nRSTO" (rect 202 1896 240 1907)(font "Arial" )) - (pt 192 1912) - (pt 296 1912) -) -(connector - (text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 303 2251)(font "Arial" )) - (pt 296 2256) - (pt 168 2256) - (bus) -) -(connector - (text "BLITTER_ADR[31..0]" (rect 194 2288 300 2299)(font "Arial" )) - (pt 184 2304) - (pt 296 2304) - (bus) -) -(connector - (text "BLITTER_SIG" (rect 194 2312 265 2323)(font "Arial" )) - (pt 184 2328) - (pt 296 2328) -) -(connector - (text "BLITTER_WR" (rect 194 2336 265 2347)(font "Arial" )) - (pt 184 2352) - (pt 296 2352) -) -(connector - (text "SR_FIFO_WRE" (rect 570 2072 650 2083)(font "Arial" )) - (pt 648 2088) - (pt 560 2088) -) -(connector - (text "SR_DDR_FB" (rect 570 2312 637 2323)(font "Arial" )) - (pt 640 2328) - (pt 560 2328) -) -(connector - (text "SR_DDR_WR" (rect 570 2024 641 2035)(font "Arial" )) - (pt 664 2040) - (pt 560 2040) -) -(connector - (text "SR_VDMP[7..0]" (rect 570 2336 647 2347)(font "Arial" )) - (pt 560 2352) - (pt 664 2352) - (bus) -) -(connector - (text "SR_DDRWR_D_SEL" (rect 570 2360 676 2371)(font "Arial" )) - (pt 560 2376) - (pt 664 2376) -) -(connector - (text "DDRCLK0" (rect 194 1920 247 1931)(font "Arial" )) - (pt 296 1936) - (pt 184 1936) -) -(connector - (text "VIDEO_DDR_TA" (rect 570 2488 657 2499)(font "Arial" )) - (pt 560 2504) - (pt 664 2504) -) -(connector - (text "SR_BLITTER_DACK" (rect 570 2464 676 2475)(font "Arial" )) - (pt 664 2480) - (pt 560 2480) -) -(connector - (text "CLK33M" (rect 218 2432 262 2443)(font "Arial" )) - (pt 208 2448) - (pt 296 2448) -) -(connector - (text "BA[1..0]" (rect 570 2120 610 2131)(font "Arial" )) - (pt 632 2136) - (pt 560 2136) - (bus) -) -(connector - (text "DDRWR_D_SEL1" (rect 570 2392 659 2403)(font "Arial" )) - (pt 656 2408) - (pt 560 2408) -) -(connector - (text "FIFO_MW[8..0]" (rect 194 2376 269 2387)(font "Arial" )) - (pt 296 2392) - (pt 184 2392) - (bus) -) -(connector - (text "VDM_SEL[3..0]" (rect 570 2416 646 2427)(font "Arial" )) - (pt 560 2432) - (pt 656 2432) - (bus) -) -(connector - (text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" )) - (pt 296 2232) - (pt 192 2232) -) -(connector - (text "VA[12..0]" (rect 570 2168 616 2179)(font "Arial" )) - (pt 560 2184) - (pt 632 2184) - (bus) -) -(connector - (text "CC16[23..0]" (rect 3954 2752 4013 2763)(font "Arial" )) - (pt 4024 2768) - (pt 3944 2768) - (bus) -) -(connector - (pt 4240 2800) - (pt 4176 2800) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 3946 2848 4007 2859)(font "Arial" )) - (pt 3936 2864) - (pt 4024 2864) -) -(connector - (pt 4104 2920) - (pt 4104 2888) - (bus) -) -(connector - (text "CCSEL[2..0]" (rect 4010 2904 4071 2915)(font "Arial" )) - (pt 4000 2920) - (pt 4104 2920) - (bus) -) -(connector - (text "CCA[23..0]" (rect 3954 2768 4008 2779)(font "Arial" )) - (pt 4024 2784) - (pt 3944 2784) - (bus) -) -(connector - (text "CC24[23..0]" (rect 3954 2736 4013 2747)(font "Arial" )) - (pt 3944 2752) - (pt 4024 2752) - (bus) -) -(connector - (pt 3888 2800) - (pt 3888 2832) - (bus) -) -(connector - (pt 3888 2832) - (pt 4024 2832) - (bus) -) -(connector - (pt 3888 2848) - (pt 4024 2848) - (bus) -) -(connector - (pt 3888 2888) - (pt 3888 2848) - (bus) -) -(connector - (text "BORDER_COLOR[23..0]" (rect 3954 2720 4077 2731)(font "Arial" )) - (pt 4024 2736) - (pt 3944 2736) - (bus) -) -(connector - (pt 4240 2792) - (pt 4240 2800) - (bus) -) -(connector - (pt 4240 2800) - (pt 4240 2808) - (bus) -) -(connector - (pt 2568 2664) - (pt 2568 2568) - (bus) -) -(connector - (pt 2560 2664) - (pt 2568 2664) - (bus) -) -(connector - (text "CC16[23..19],CC16[15..10],CC16[7..3]" (rect 2530 2552 2718 2563)(font "Arial" )) - (pt 2568 2568) - (pt 2688 2568) - (bus) -) -(junction (pt 2984 1688)) -(junction (pt 792 1192)) -(junction (pt 792 1312)) -(junction (pt 792 1432)) -(junction (pt 792 1792)) -(junction (pt 792 1928)) -(junction (pt 792 1552)) -(junction (pt 792 1648)) -(junction (pt 2512 1728)) -(junction (pt 2512 1888)) -(junction (pt 2512 2048)) -(junction (pt 2512 1408)) -(junction (pt 2512 1568)) -(junction (pt 2512 1552)) -(junction (pt 2512 2208)) -(junction (pt 1344 2880)) -(junction (pt 1344 2824)) -(junction (pt 1344 2928)) -(junction (pt 1328 2904)) -(junction (pt 1328 2952)) -(junction (pt 4240 2800)) -(junction (pt 3232 3024)) -(junction (pt 1968 1424)) -(junction (pt 1608 1432)) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd new file mode 100644 index 0000000..3fbd54a --- /dev/null +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -0,0 +1,1768 @@ +-- Copyright (C) 1991-2014 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" +-- CREATED "Mon Jan 11 09:20:56 2016" + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY work; + +ENTITY video IS + PORT + ( + MAIN_CLK : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + DDR_SYNC_66M : IN STD_LOGIC; + CLK33M : IN STD_LOGIC; + CLK25M : IN STD_LOGIC; + CLK_VIDEO : IN STD_LOGIC; + VR_BUSY : IN STD_LOGIC; + DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); + VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + nBLANK : OUT STD_LOGIC; + nVWE : OUT STD_LOGIC; + nVCAS : OUT STD_LOGIC; + nVRAS : OUT STD_LOGIC; + nVCS : OUT STD_LOGIC; + nPD_VGA : OUT STD_LOGIC; + VCKE : OUT STD_LOGIC; + VSYNC : OUT STD_LOGIC; + HSYNC : OUT STD_LOGIC; + nSYNC : OUT STD_LOGIC; + VIDEO_TA : OUT STD_LOGIC; + PIXEL_CLK : OUT STD_LOGIC; + VIDEO_RECONFIG : OUT STD_LOGIC; + VR_WR : OUT STD_LOGIC; + VR_RD : OUT STD_LOGIC; + BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END video; + +ARCHITECTURE bdf_type OF video IS + +ATTRIBUTE black_box : BOOLEAN; +ATTRIBUTE noopt : BOOLEAN; + +COMPONENT mux41_0 + PORT(S0 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC); +END COMPONENT; +ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; +ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; + +COMPONENT mux41_1 + PORT(S0 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC); +END COMPONENT; +ATTRIBUTE black_box OF mux41_1: COMPONENT IS true; +ATTRIBUTE noopt OF mux41_1: COMPONENT IS true; + +COMPONENT mux41_2 + PORT(S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC); +END COMPONENT; +ATTRIBUTE black_box OF mux41_2: COMPONENT IS true; +ATTRIBUTE noopt OF mux41_2: COMPONENT IS true; + +COMPONENT mux41_3 + PORT(S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC); +END COMPONENT; +ATTRIBUTE black_box OF mux41_3: COMPONENT IS true; +ATTRIBUTE noopt OF mux41_3: COMPONENT IS true; + +COMPONENT mux41_4 + PORT(S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC); +END COMPONENT; +ATTRIBUTE black_box OF mux41_4: COMPONENT IS true; +ATTRIBUTE noopt OF mux41_4: COMPONENT IS true; + +COMPONENT mux41_5 + PORT(S0 : IN STD_LOGIC; + D2 : IN STD_LOGIC; + S1 : IN STD_LOGIC; + D0 : IN STD_LOGIC; + INH : IN STD_LOGIC; + D1 : IN STD_LOGIC; + Q : OUT STD_LOGIC); +END COMPONENT; +ATTRIBUTE black_box OF mux41_5: COMPONENT IS true; +ATTRIBUTE noopt OF mux41_5: COMPONENT IS true; + +COMPONENT altdpram2 + PORT(wren_a : IN STD_LOGIC; + wren_b : IN STD_LOGIC; + clock_a : IN STD_LOGIC; + clock_b : IN STD_LOGIC; + address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT blitter + PORT(nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + BLITTER_ON : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + SR_BLITTER_DACK : IN STD_LOGIC; + BLITTER_DACK : IN STD_LOGIC_VECTOR(4 DOWNTO 0); + BLITTER_DIN : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + BLITTER_RUN : OUT STD_LOGIC; + BLITTER_SIG : OUT STD_LOGIC; + BLITTER_WR : OUT STD_LOGIC; + BLITTER_TA : OUT STD_LOGIC; + BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT ddr_ctr + PORT(nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + DDR_SYNC_66M : IN STD_LOGIC; + BLITTER_SIG : IN STD_LOGIC; + BLITTER_WR : IN STD_LOGIC; + DDRCLK0 : IN STD_LOGIC; + CLK33M : IN STD_LOGIC; + CLR_FIFO : IN STD_LOGIC; + BLITTER_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + FIFO_MW : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + nVWE : OUT STD_LOGIC; + nVRAS : OUT STD_LOGIC; + nVCS : OUT STD_LOGIC; + VCKE : OUT STD_LOGIC; + nVCAS : OUT STD_LOGIC; + SR_FIFO_WRE : OUT STD_LOGIC; + SR_DDR_FB : OUT STD_LOGIC; + SR_DDR_WR : OUT STD_LOGIC; + SR_DDRWR_D_SEL : OUT STD_LOGIC; + VIDEO_DDR_TA : OUT STD_LOGIC; + SR_BLITTER_DACK : OUT STD_LOGIC; + DDRWR_D_SEL1 : OUT STD_LOGIC; + BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + FB_LE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + FB_VDOE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + SR_VDMP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + VDM_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT altdpram1 + PORT(wren_a : IN STD_LOGIC; + wren_b : IN STD_LOGIC; + clock_a : IN STD_LOGIC; + clock_b : IN STD_LOGIC; + address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_fifo_dc0 + PORT(wrreq : IN STD_LOGIC; + wrclk : IN STD_LOGIC; + rdreq : IN STD_LOGIC; + rdclk : IN STD_LOGIC; + aclr : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + rdempty : OUT STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT altddio_bidir0 + PORT(oe : IN STD_LOGIC; + inclock : IN STD_LOGIC; + outclock : IN STD_LOGIC; + datain_h : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + padio : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + combout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dataout_h : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + dataout_l : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_ff4 + PORT(clock : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_muxvdm + PORT(data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux3 + PORT(data1 : IN STD_LOGIC; + data0 : IN STD_LOGIC; + sel : IN STD_LOGIC; + result : OUT STD_LOGIC + ); +END COMPONENT; + +COMPONENT lpm_bustri_long + PORT(enabledt : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_ff5 + PORT(clock : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_ff1 + PORT(clock : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_ff0 + PORT(clock : IN STD_LOGIC; + enable : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT altddio_out0 + PORT(outclock : IN STD_LOGIC; + datain_h : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + dataout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux0 + PORT(clock : IN STD_LOGIC; + data0x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux5 + PORT(data0x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_constant2 + PORT( result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux1 + PORT(clock : IN STD_LOGIC; + data0x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux2 + PORT(clock : IN STD_LOGIC; + data0x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_shiftreg4 + PORT(clock : IN STD_LOGIC; + shiftin : IN STD_LOGIC; + shiftout : OUT STD_LOGIC + ); +END COMPONENT; + +COMPONENT lpm_latch0 + PORT(gate : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_ff6 + PORT(clock : IN STD_LOGIC; + enable : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_ff3 + PORT(clock : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT altddio_out2 + PORT(outclock : IN STD_LOGIC; + datain_h : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + datain_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + dataout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_bustri1 + PORT(enabledt : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_bustri_byt + PORT(enabledt : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_constant0 + PORT( result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_muxdz + PORT(clock : IN STD_LOGIC; + clken : IN STD_LOGIC; + sel : IN STD_LOGIC; + data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_fifodz + PORT(wrreq : IN STD_LOGIC; + rdreq : IN STD_LOGIC; + clock : IN STD_LOGIC; + aclr : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(127 DOWNTO 0); + q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_bustri3 + PORT(enabledt : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR(5 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux6 + PORT(clock : IN STD_LOGIC; + data0x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_constant1 + PORT( result : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_mux4 + PORT(sel : IN STD_LOGIC; + data0x : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_constant3 + PORT( result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_shiftreg6 + PORT(clock : IN STD_LOGIC; + shiftin : IN STD_LOGIC; + q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT lpm_shiftreg0 + PORT(load : IN STD_LOGIC; + clock : IN STD_LOGIC; + shiftin : IN STD_LOGIC; + data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + shiftout : OUT STD_LOGIC + ); +END COMPONENT; + +COMPONENT altdpram0 + PORT(wren_a : IN STD_LOGIC; + wren_b : IN STD_LOGIC; + clock_a : IN STD_LOGIC; + clock_b : IN STD_LOGIC; + address_a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) + ); +END COMPONENT; + +COMPONENT video_mod_mux_clutctr + PORT(nRSTO : IN STD_LOGIC; + MAIN_CLK : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nFB_BURST : IN STD_LOGIC; + CLK33M : IN STD_LOGIC; + CLK25M : IN STD_LOGIC; + BLITTER_RUN : IN STD_LOGIC; + CLK_VIDEO : IN STD_LOGIC; + VR_BUSY : IN STD_LOGIC; + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + COLOR8 : OUT STD_LOGIC; + ACP_CLUT_RD : OUT STD_LOGIC; + COLOR1 : OUT STD_LOGIC; + FALCON_CLUT_RDH : OUT STD_LOGIC; + FALCON_CLUT_RDL : OUT STD_LOGIC; + ST_CLUT_RD : OUT STD_LOGIC; + HSYNC : OUT STD_LOGIC; + VSYNC : OUT STD_LOGIC; + nBLANK : OUT STD_LOGIC; + nSYNC : OUT STD_LOGIC; + nPD_VGA : OUT STD_LOGIC; + FIFO_RDE : OUT STD_LOGIC; + COLOR2 : OUT STD_LOGIC; + COLOR4 : OUT STD_LOGIC; + PIXEL_CLK : OUT STD_LOGIC; + BLITTER_ON : OUT STD_LOGIC; + VIDEO_MOD_TA : OUT STD_LOGIC; + INTER_ZEI : OUT STD_LOGIC; + DOP_FIFO_CLR : OUT STD_LOGIC; + VIDEO_RECONFIG : OUT STD_LOGIC; + VR_WR : OUT STD_LOGIC; + VR_RD : OUT STD_LOGIC; + CLR_FIFO : OUT STD_LOGIC; + ACP_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + BORDER_COLOR : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); + CCSEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + CLUT_MUX_ADR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + CLUT_OFF : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + FALCON_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + ST_CLUT_WR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + VIDEO_RAM_CTR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; + +SIGNAL ACP_CLUT_RD : STD_LOGIC; +SIGNAL ACP_CLUT_WR : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL BLITTER_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL BLITTER_DACK : STD_LOGIC_VECTOR(4 DOWNTO 0); +SIGNAL BLITTER_DIN : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL BLITTER_DOUT : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL BLITTER_ON : STD_LOGIC; +SIGNAL BLITTER_RUN : STD_LOGIC; +SIGNAL BLITTER_SIG : STD_LOGIC; +SIGNAL BLITTER_TA : STD_LOGIC; +SIGNAL BLITTER_WR : STD_LOGIC; +SIGNAL BORDER_COLOR : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL CC16 : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL CC24 : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL CCA : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL CCF : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL CCS : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL CCSEL : STD_LOGIC_VECTOR(2 DOWNTO 0); +SIGNAL CLR_FIFO : STD_LOGIC; +SIGNAL CLUT_ADR : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL CLUT_ADR1A : STD_LOGIC; +SIGNAL CLUT_ADR2A : STD_LOGIC; +SIGNAL CLUT_ADR3A : STD_LOGIC; +SIGNAL CLUT_ADR4A : STD_LOGIC; +SIGNAL CLUT_ADR5A : STD_LOGIC; +SIGNAL CLUT_ADR6A : STD_LOGIC; +SIGNAL CLUT_ADR7A : STD_LOGIC; +SIGNAL CLUT_MUX_ADR : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL CLUT_OFF : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL COLOR1 : STD_LOGIC; +SIGNAL COLOR2 : STD_LOGIC; +SIGNAL COLOR4 : STD_LOGIC; +SIGNAL COLOR8 : STD_LOGIC; +SIGNAL DDR_FB : STD_LOGIC_VECTOR(4 DOWNTO 0); +SIGNAL DDR_WR : STD_LOGIC; +SIGNAL DDRWR_D_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); +SIGNAL DOP_FIFO_CLR : STD_LOGIC; +SIGNAL FALCON_CLUT_RDH : STD_LOGIC; +SIGNAL FALCON_CLUT_RDL : STD_LOGIC; +SIGNAL FALCON_CLUT_WR : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL FB_DDR : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL FB_VDOE : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL FIFO_D : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0); +SIGNAL FIFO_RDE : STD_LOGIC; +SIGNAL FIFO_WRE : STD_LOGIC; +SIGNAL INTER_ZEI : STD_LOGIC; +SIGNAL nFB_BURST : STD_LOGIC; +SIGNAL PIXEL_CLK_ALTERA_SYNTHESIZED : STD_LOGIC; +SIGNAL SR_BLITTER_DACK : STD_LOGIC; +SIGNAL SR_DDR_FB : STD_LOGIC; +SIGNAL SR_DDR_WR : STD_LOGIC; +SIGNAL SR_DDRWR_D_SEL : STD_LOGIC; +SIGNAL SR_FIFO_WRE : STD_LOGIC; +SIGNAL SR_VDMP : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL ST_CLUT_RD : STD_LOGIC; +SIGNAL ST_CLUT_WR : STD_LOGIC_VECTOR(1 DOWNTO 0); +SIGNAL VDM_SEL : STD_LOGIC_VECTOR(3 DOWNTO 0); +SIGNAL VDMA : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL VDMB : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL VDMC : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL VDMP : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL VDOUT_OE : STD_LOGIC; +SIGNAL VDP_IN : STD_LOGIC_VECTOR(63 DOWNTO 0); +SIGNAL VDP_OUT : STD_LOGIC_VECTOR(63 DOWNTO 0); +SIGNAL VDR : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL VDVZ : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL VIDEO_DDR_TA : STD_LOGIC; +SIGNAL VIDEO_MOD_TA : STD_LOGIC; +SIGNAL VIDEO_RAM_CTR : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL ZR_C8 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL ZR_C8B : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_60 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL DFF_inst93 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_61 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_24 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_25 : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_62 : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC_VECTOR(2 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC_VECTOR(2 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC_VECTOR(2 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_63 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_38 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_40 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC_VECTOR(5 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_43 : STD_LOGIC_VECTOR(23 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC_VECTOR(5 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC_VECTOR(5 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_46 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_47 : STD_LOGIC_VECTOR(6 DOWNTO 0); +SIGNAL SYNTHESIZED_WIRE_48 : STD_LOGIC_VECTOR(31 DOWNTO 0); +SIGNAL DFF_inst91 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_64 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_50 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_51 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_52 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_53 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_54 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_55 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_56 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_57 : STD_LOGIC; +SIGNAL SYNTHESIZED_WIRE_65 : STD_LOGIC_VECTOR(23 DOWNTO 0); + +SIGNAL GDFX_TEMP_SIGNAL_16 : STD_LOGIC_VECTOR(7 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_6 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_5 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_4 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_3 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_2 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_1 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_15 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_14 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_13 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_12 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_11 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_10 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_9 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_8 : STD_LOGIC_VECTOR(127 DOWNTO 0); +SIGNAL GDFX_TEMP_SIGNAL_7 : STD_LOGIC_VECTOR(127 DOWNTO 0); + +BEGIN +VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); +VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); +VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); +SYNTHESIZED_WIRE_0 <= '0'; +SYNTHESIZED_WIRE_1 <= '0'; +SYNTHESIZED_WIRE_2 <= '0'; +SYNTHESIZED_WIRE_3 <= '0'; +SYNTHESIZED_WIRE_4 <= '0'; +SYNTHESIZED_WIRE_5 <= '0'; +SYNTHESIZED_WIRE_19 <= '0'; +SYNTHESIZED_WIRE_20 <= '0'; +SYNTHESIZED_WIRE_21 <= '0'; +SYNTHESIZED_WIRE_22 <= '0'; +SYNTHESIZED_WIRE_23 <= '0'; +SYNTHESIZED_WIRE_24 <= '0'; +SYNTHESIZED_WIRE_55 <= '0'; +SYNTHESIZED_WIRE_56 <= '0'; +SYNTHESIZED_WIRE_57 <= '0'; + +CC16(18) <= GDFX_TEMP_SIGNAL_16(7); +CC16(17) <= GDFX_TEMP_SIGNAL_16(6); +CC16(16) <= GDFX_TEMP_SIGNAL_16(5); +CC16(9) <= GDFX_TEMP_SIGNAL_16(4); +CC16(8) <= GDFX_TEMP_SIGNAL_16(3); +CC16(2) <= GDFX_TEMP_SIGNAL_16(2); +CC16(1) <= GDFX_TEMP_SIGNAL_16(1); +CC16(0) <= GDFX_TEMP_SIGNAL_16(0); + +CC16(23) <= GDFX_TEMP_SIGNAL_0(15); +CC16(22) <= GDFX_TEMP_SIGNAL_0(14); +CC16(21) <= GDFX_TEMP_SIGNAL_0(13); +CC16(20) <= GDFX_TEMP_SIGNAL_0(12); +CC16(19) <= GDFX_TEMP_SIGNAL_0(11); +CC16(15) <= GDFX_TEMP_SIGNAL_0(10); +CC16(14) <= GDFX_TEMP_SIGNAL_0(9); +CC16(13) <= GDFX_TEMP_SIGNAL_0(8); +CC16(12) <= GDFX_TEMP_SIGNAL_0(7); +CC16(11) <= GDFX_TEMP_SIGNAL_0(6); +CC16(10) <= GDFX_TEMP_SIGNAL_0(5); +CC16(7) <= GDFX_TEMP_SIGNAL_0(4); +CC16(6) <= GDFX_TEMP_SIGNAL_0(3); +CC16(5) <= GDFX_TEMP_SIGNAL_0(2); +CC16(4) <= GDFX_TEMP_SIGNAL_0(1); +CC16(3) <= GDFX_TEMP_SIGNAL_0(0); + +GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); +GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); +GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); +GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); +GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); +GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); +GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); +GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); +GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); +GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80)); +GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88)); +GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96)); +GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); +GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); +GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); + + +b2v_ACP_CLUT_RAM : altdpram2 +PORT MAP(wren_a => ACP_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_0, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(7 DOWNTO 0), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_30, + q_b => CCA(7 DOWNTO 0)); + + +b2v_ACP_CLUT_RAM54 : altdpram2 +PORT MAP(wren_a => ACP_CLUT_WR(2), + wren_b => SYNTHESIZED_WIRE_1, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(15 DOWNTO 8), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_32, + q_b => CCA(15 DOWNTO 8)); + + +b2v_ACP_CLUT_RAM55 : altdpram2 +PORT MAP(wren_a => ACP_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_2, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(23 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_33, + q_b => CCA(23 DOWNTO 16)); + + +b2v_BLITTER : blitter +PORT MAP(nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + BLITTER_ON => BLITTER_ON, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + DDRCLK0 => DDRCLK(0), + SR_BLITTER_DACK => SR_BLITTER_DACK, + BLITTER_DACK => BLITTER_DACK, + BLITTER_DIN => BLITTER_DIN, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + BLITTER_RUN => BLITTER_RUN, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + BLITTER_TA => BLITTER_TA, + BLITTER_ADR => BLITTER_ADR, + BLITTER_DOUT => BLITTER_DOUT); + + +b2v_DDR_CTR : ddr_ctr +PORT MAP(nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + DDR_SYNC_66M => DDR_SYNC_66M, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + DDRCLK0 => DDRCLK(0), + CLK33M => CLK33M, + CLR_FIFO => CLR_FIFO, + BLITTER_ADR => BLITTER_ADR, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + FIFO_MW => FIFO_MW, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + nVWE => nVWE, + nVRAS => nVRAS, + nVCS => nVCS, + VCKE => VCKE, + nVCAS => nVCAS, + SR_FIFO_WRE => SR_FIFO_WRE, + SR_DDR_FB => SR_DDR_FB, + SR_DDR_WR => SR_DDR_WR, + SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, + VIDEO_DDR_TA => VIDEO_DDR_TA, + SR_BLITTER_DACK => SR_BLITTER_DACK, + DDRWR_D_SEL1 => DDRWR_D_SEL(1), + BA => BA, + FB_LE => FB_LE, + FB_VDOE => FB_VDOE, + SR_VDMP => SR_VDMP, + VA => VA, + VDM_SEL => VDM_SEL); + + +b2v_FALCON_CLUT_BLUE : altdpram1 +PORT MAP(wren_a => FALCON_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_3, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_45, + q_b => CCF(7 DOWNTO 2)); + + +b2v_FALCON_CLUT_GREEN : altdpram1 +PORT MAP(wren_a => FALCON_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_4, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_44, + q_b => CCF(15 DOWNTO 10)); + + +b2v_FALCON_CLUT_RED : altdpram1 +PORT MAP(wren_a => FALCON_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_5, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(31 DOWNTO 26), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_41, + q_b => CCF(23 DOWNTO 18)); + + +b2v_inst : lpm_fifo_dc0 +PORT MAP(wrreq => FIFO_WRE, + wrclk => DDRCLK(0), + rdreq => SYNTHESIZED_WIRE_60, + rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => CLR_FIFO, + data => VDMC, + q => SYNTHESIZED_WIRE_63, + wrusedw => FIFO_MW); + + +b2v_inst1 : altddio_bidir0 +PORT MAP(oe => VDOUT_OE, + inclock => DDRCLK(1), + outclock => DDRCLK(3), + datain_h => VDP_OUT(63 DOWNTO 32), + datain_l => VDP_OUT(31 DOWNTO 0), + padio => VD, + combout => SYNTHESIZED_WIRE_15, + dataout_h => VDP_IN(31 DOWNTO 0), + dataout_l => VDP_IN(63 DOWNTO 32)); + + +b2v_inst10 : lpm_ff4 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_7, + q => GDFX_TEMP_SIGNAL_0); + + +b2v_inst100 : lpm_muxvdm +PORT MAP(data0x => VDMB, + data10x => GDFX_TEMP_SIGNAL_1, + data11x => GDFX_TEMP_SIGNAL_2, + data12x => GDFX_TEMP_SIGNAL_3, + data13x => GDFX_TEMP_SIGNAL_4, + data14x => GDFX_TEMP_SIGNAL_5, + data15x => GDFX_TEMP_SIGNAL_6, + data1x => GDFX_TEMP_SIGNAL_7, + data2x => GDFX_TEMP_SIGNAL_8, + data3x => GDFX_TEMP_SIGNAL_9, + data4x => GDFX_TEMP_SIGNAL_10, + data5x => GDFX_TEMP_SIGNAL_11, + data6x => GDFX_TEMP_SIGNAL_12, + data7x => GDFX_TEMP_SIGNAL_13, + data8x => GDFX_TEMP_SIGNAL_14, + data9x => GDFX_TEMP_SIGNAL_15, + sel => VDM_SEL, + result => VDMC); + + +b2v_inst102 : lpm_mux3 +PORT MAP(data1 => DFF_inst93, + data0 => ZR_C8(0), + sel => COLOR1, + result => ZR_C8B(0)); + + +CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; + + +CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; + + +SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; + + +CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; + + +SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; + + +b2v_inst108 : lpm_bustri_long +PORT MAP(enabledt => FB_VDOE(0), + data => VDR, + tridata => FB_AD); + + +b2v_inst109 : lpm_bustri_long +PORT MAP(enabledt => FB_VDOE(1), + data => SYNTHESIZED_WIRE_11, + tridata => FB_AD); + + +b2v_inst11 : lpm_ff5 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_12, + q => ZR_C8); + + +b2v_inst110 : lpm_bustri_long +PORT MAP(enabledt => FB_VDOE(2), + data => SYNTHESIZED_WIRE_13, + tridata => FB_AD); + + +b2v_inst119 : lpm_bustri_long +PORT MAP(enabledt => FB_VDOE(3), + data => SYNTHESIZED_WIRE_14, + tridata => FB_AD); + + +b2v_inst12 : lpm_ff1 +PORT MAP(clock => DDRCLK(0), + data => VDP_IN(31 DOWNTO 0), + q => VDVZ(31 DOWNTO 0)); + + +b2v_inst13 : lpm_ff0 +PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(0), + data => FB_AD, + q => FB_DDR(127 DOWNTO 96)); + + +b2v_inst14 : lpm_ff0 +PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(1), + data => FB_AD, + q => FB_DDR(95 DOWNTO 64)); + + +b2v_inst15 : lpm_ff0 +PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(2), + data => FB_AD, + q => FB_DDR(63 DOWNTO 32)); + + +b2v_inst16 : lpm_ff0 +PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(3), + data => FB_AD, + q => FB_DDR(31 DOWNTO 0)); + + +b2v_inst17 : lpm_ff0 +PORT MAP(clock => DDRCLK(0), + enable => DDR_FB(1), + data => VDP_IN(31 DOWNTO 0), + q => SYNTHESIZED_WIRE_11); + + +b2v_inst18 : lpm_ff0 +PORT MAP(clock => DDRCLK(0), + enable => DDR_FB(0), + data => VDP_IN(63 DOWNTO 32), + q => SYNTHESIZED_WIRE_13); + + +b2v_inst19 : lpm_ff0 +PORT MAP(clock => DDRCLK(0), + enable => DDR_FB(0), + data => VDP_IN(31 DOWNTO 0), + q => SYNTHESIZED_WIRE_14); + + +b2v_inst2 : altddio_out0 +PORT MAP(outclock => DDRCLK(3), + datain_h => VDMP(7 DOWNTO 4), + datain_l => VDMP(3 DOWNTO 0), + dataout => VDM); + + +b2v_inst20 : lpm_ff1 +PORT MAP(clock => DDRCLK(0), + data => VDVZ(31 DOWNTO 0), + q => VDVZ(95 DOWNTO 64)); + + +b2v_inst21 : lpm_mux0 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 96), + data1x => FIFO_D(95 DOWNTO 64), + data2x => FIFO_D(63 DOWNTO 32), + data3x => FIFO_D(31 DOWNTO 0), + sel => CLUT_MUX_ADR(1 DOWNTO 0), + result => SYNTHESIZED_WIRE_48); + + +b2v_inst22 : lpm_mux5 +PORT MAP(data0x => FB_DDR(127 DOWNTO 64), + data1x => FB_DDR(63 DOWNTO 0), + data2x => BLITTER_DOUT(127 DOWNTO 64), + data3x => BLITTER_DOUT(63 DOWNTO 0), + sel => DDRWR_D_SEL, + result => VDP_OUT); + + +b2v_inst23 : lpm_constant2 +PORT MAP( result => GDFX_TEMP_SIGNAL_16); + + +b2v_inst24 : lpm_mux1 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 112), + data1x => FIFO_D(111 DOWNTO 96), + data2x => FIFO_D(95 DOWNTO 80), + data3x => FIFO_D(79 DOWNTO 64), + data4x => FIFO_D(63 DOWNTO 48), + data5x => FIFO_D(47 DOWNTO 32), + data6x => FIFO_D(31 DOWNTO 16), + data7x => FIFO_D(15 DOWNTO 0), + sel => CLUT_MUX_ADR(2 DOWNTO 0), + result => SYNTHESIZED_WIRE_7); + + +b2v_inst25 : lpm_mux2 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 120), + data10x => FIFO_D(47 DOWNTO 40), + data11x => FIFO_D(39 DOWNTO 32), + data12x => FIFO_D(31 DOWNTO 24), + data13x => FIFO_D(23 DOWNTO 16), + data14x => FIFO_D(15 DOWNTO 8), + data15x => FIFO_D(7 DOWNTO 0), + data1x => FIFO_D(119 DOWNTO 112), + data2x => FIFO_D(111 DOWNTO 104), + data3x => FIFO_D(103 DOWNTO 96), + data4x => FIFO_D(95 DOWNTO 88), + data5x => FIFO_D(87 DOWNTO 80), + data6x => FIFO_D(79 DOWNTO 72), + data7x => FIFO_D(71 DOWNTO 64), + data8x => FIFO_D(63 DOWNTO 56), + data9x => FIFO_D(55 DOWNTO 48), + sel => CLUT_MUX_ADR, + result => SYNTHESIZED_WIRE_12); + + +b2v_inst26 : lpm_shiftreg4 +PORT MAP(clock => DDRCLK(0), + shiftin => SR_FIFO_WRE, + shiftout => FIFO_WRE); + + +b2v_inst27 : lpm_latch0 +PORT MAP(gate => DDR_SYNC_66M, + data => SYNTHESIZED_WIRE_15, + q => VDR); + + + +CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; + + +b2v_inst3 : lpm_ff1 +PORT MAP(clock => DDRCLK(0), + data => VDP_IN(63 DOWNTO 32), + q => VDVZ(63 DOWNTO 32)); + + +CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; + + +CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; + + +SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; + + +SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; + + +SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; + + +SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; + + +b2v_inst36 : lpm_ff6 +PORT MAP(clock => DDRCLK(0), + enable => BLITTER_DACK(0), + data => VDVZ, + q => BLITTER_DIN); + + +VDOUT_OE <= DDR_WR OR SR_DDR_WR; + + + +VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA; + + +b2v_inst4 : lpm_ff1 +PORT MAP(clock => DDRCLK(0), + data => VDVZ(63 DOWNTO 32), + q => VDVZ(127 DOWNTO 96)); + + +b2v_inst40 : mux41_0 +PORT MAP(S0 => COLOR2, + S1 => COLOR4, + D0 => CLUT_ADR6A, + INH => SYNTHESIZED_WIRE_19, + D1 => CLUT_ADR7A, + Q => SYNTHESIZED_WIRE_54); + + +b2v_inst41 : mux41_1 +PORT MAP(S0 => COLOR2, + S1 => COLOR4, + D0 => CLUT_ADR5A, + INH => SYNTHESIZED_WIRE_20, + D1 => CLUT_ADR6A, + Q => SYNTHESIZED_WIRE_53); + + +b2v_inst42 : mux41_2 +PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR7A, + S1 => COLOR4, + D0 => CLUT_ADR4A, + INH => SYNTHESIZED_WIRE_21, + D1 => CLUT_ADR5A, + Q => SYNTHESIZED_WIRE_52); + + +b2v_inst43 : mux41_3 +PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR6A, + S1 => COLOR4, + D0 => CLUT_ADR3A, + INH => SYNTHESIZED_WIRE_22, + D1 => CLUT_ADR4A, + Q => SYNTHESIZED_WIRE_51); + + +b2v_inst44 : mux41_4 +PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR5A, + S1 => COLOR4, + D0 => CLUT_ADR2A, + INH => SYNTHESIZED_WIRE_23, + D1 => CLUT_ADR3A, + Q => SYNTHESIZED_WIRE_50); + + +b2v_inst45 : mux41_5 +PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR4A, + S1 => COLOR4, + D0 => CLUT_ADR1A, + INH => SYNTHESIZED_WIRE_24, + D1 => CLUT_ADR2A, + Q => SYNTHESIZED_WIRE_49); + + +b2v_inst46 : lpm_ff3 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_25, + q => SYNTHESIZED_WIRE_43); + + +b2v_inst47 : lpm_ff3 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => CCF, + q => SYNTHESIZED_WIRE_25); + + + +b2v_inst49 : lpm_ff3 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_26, + q => SYNTHESIZED_WIRE_42); + + +b2v_inst5 : altddio_out2 +PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, + datain_h => SYNTHESIZED_WIRE_62, + datain_l => SYNTHESIZED_WIRE_62, + dataout => SYNTHESIZED_WIRE_65); + + + +b2v_inst51 : lpm_bustri1 +PORT MAP(enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_29, + tridata => FB_AD(26 DOWNTO 24)); + + +b2v_inst52 : lpm_ff3 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => CCS, + q => SYNTHESIZED_WIRE_26); + + +b2v_inst53 : lpm_bustri_byt +PORT MAP(enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_30, + tridata => FB_AD(7 DOWNTO 0)); + + +b2v_inst54 : lpm_constant0 +PORT MAP( result => CCS(20 DOWNTO 16)); + + + +b2v_inst56 : lpm_bustri1 +PORT MAP(enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_31, + tridata => FB_AD(22 DOWNTO 20)); + + +b2v_inst57 : lpm_bustri_byt +PORT MAP(enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_32, + tridata => FB_AD(15 DOWNTO 8)); + + +b2v_inst58 : lpm_bustri_byt +PORT MAP(enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_33, + tridata => FB_AD(23 DOWNTO 16)); + + +b2v_inst59 : lpm_constant0 +PORT MAP( result => CCS(12 DOWNTO 8)); + + + + +b2v_inst61 : lpm_bustri1 +PORT MAP(enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_34, + tridata => FB_AD(18 DOWNTO 16)); + + +b2v_inst62 : lpm_muxdz +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clken => FIFO_RDE, + sel => INTER_ZEI, + data0x => SYNTHESIZED_WIRE_63, + data1x => SYNTHESIZED_WIRE_36, + result => FIFO_D); + + +b2v_inst63 : lpm_fifodz +PORT MAP(wrreq => SYNTHESIZED_WIRE_60, + rdreq => SYNTHESIZED_WIRE_38, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => DOP_FIFO_CLR, + data => SYNTHESIZED_WIRE_63, + q => SYNTHESIZED_WIRE_36); + + +b2v_inst64 : lpm_constant0 +PORT MAP( result => CCS(4 DOWNTO 0)); + + +SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; + + +b2v_inst66 : lpm_bustri3 +PORT MAP(enabledt => FALCON_CLUT_RDH, + data => SYNTHESIZED_WIRE_41, + tridata => FB_AD(31 DOWNTO 26)); + + +SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; + + + +SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); + + + +b2v_inst7 : lpm_mux6 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => SYNTHESIZED_WIRE_42, + data1x => SYNTHESIZED_WIRE_43, + data2x => (OTHERS => '0'), + data3x => (OTHERS => '0'), + data4x => CCA, + data5x => CC16, + data6x => CC24(23 DOWNTO 0), + data7x => BORDER_COLOR, + sel => CCSEL, + result => SYNTHESIZED_WIRE_62); + + +b2v_inst70 : lpm_bustri3 +PORT MAP(enabledt => FALCON_CLUT_RDH, + data => SYNTHESIZED_WIRE_44, + tridata => FB_AD(23 DOWNTO 18)); + + +b2v_inst71 : lpm_ff6 +PORT MAP(clock => DDRCLK(0), + enable => FIFO_WRE, + data => VDVZ, + q => VDMA); + + + + +b2v_inst74 : lpm_bustri3 +PORT MAP(enabledt => FALCON_CLUT_RDL, + data => SYNTHESIZED_WIRE_45, + tridata => FB_AD(23 DOWNTO 18)); + + + + +b2v_inst77 : lpm_constant1 +PORT MAP( result => CCF(1 DOWNTO 0)); + + + +CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; + + + +b2v_inst80 : lpm_constant1 +PORT MAP( result => CCF(9 DOWNTO 8)); + + +b2v_inst81 : lpm_mux4 +PORT MAP(sel => COLOR1, + data0x => ZR_C8(7 DOWNTO 1), + data1x => SYNTHESIZED_WIRE_47, + result => ZR_C8B(7 DOWNTO 1)); + + +b2v_inst82 : lpm_constant3 +PORT MAP( result => SYNTHESIZED_WIRE_47); + + +b2v_inst83 : lpm_constant1 +PORT MAP( result => CCF(17 DOWNTO 16)); + + +PROCESS(DDRCLK(0),DDR_WR) +BEGIN +if (DDR_WR = '1') THEN + VDQS(3) <= DDRCLK(0); +ELSE + VDQS(3) <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(DDRCLK(0),DDR_WR) +BEGIN +if (DDR_WR = '1') THEN + VDQS(2) <= DDRCLK(0); +ELSE + VDQS(2) <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(DDRCLK(0),DDR_WR) +BEGIN +if (DDR_WR = '1') THEN + VDQS(1) <= DDRCLK(0); +ELSE + VDQS(1) <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(DDRCLK(0),DDR_WR) +BEGIN +if (DDR_WR = '1') THEN + VDQS(0) <= DDRCLK(0); +ELSE + VDQS(0) <= 'Z'; +END IF; +END PROCESS; + + +PROCESS(DDRCLK(3)) +BEGIN +IF (RISING_EDGE(DDRCLK(3))) THEN + DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; +END IF; +END PROCESS; + + +b2v_inst89 : lpm_shiftreg6 +PORT MAP(clock => DDRCLK(0), + shiftin => SR_BLITTER_DACK, + q => BLITTER_DACK); + + +b2v_inst9 : lpm_ff1 +PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_48, + q => CC24); + + +PROCESS(DDRCLK(3)) +BEGIN +IF (RISING_EDGE(DDRCLK(3))) THEN + DDR_WR <= SR_DDR_WR; +END IF; +END PROCESS; + + +PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) +BEGIN +IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + DFF_inst91 <= CLUT_ADR(0); +END IF; +END PROCESS; + + +b2v_inst92 : lpm_shiftreg6 +PORT MAP(clock => DDRCLK(0), + shiftin => SR_DDR_FB, + q => DDR_FB); + + +PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) +BEGIN +IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + DFF_inst93 <= DFF_inst91; +END IF; +END PROCESS; + + +b2v_inst94 : lpm_ff6 +PORT MAP(clock => DDRCLK(0), + enable => FIFO_WRE, + data => VDMA, + q => VDMB); + + +PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) +BEGIN +IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + SYNTHESIZED_WIRE_64 <= FIFO_RDE; +END IF; +END PROCESS; + + + +b2v_inst97 : lpm_ff5 +PORT MAP(clock => DDRCLK(2), + data => SR_VDMP, + q => VDMP); + + +b2v_sr0 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_49, + data => FIFO_D(127 DOWNTO 112), + shiftout => CLUT_ADR(0)); + + +b2v_sr1 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_50, + data => FIFO_D(111 DOWNTO 96), + shiftout => CLUT_ADR1A); + + +b2v_sr2 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_51, + data => FIFO_D(95 DOWNTO 80), + shiftout => CLUT_ADR2A); + + +b2v_sr3 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_52, + data => FIFO_D(79 DOWNTO 64), + shiftout => CLUT_ADR3A); + + +b2v_sr4 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_53, + data => FIFO_D(63 DOWNTO 48), + shiftout => CLUT_ADR4A); + + +b2v_sr5 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_54, + data => FIFO_D(47 DOWNTO 32), + shiftout => CLUT_ADR5A); + + +b2v_sr6 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => CLUT_ADR7A, + data => FIFO_D(31 DOWNTO 16), + shiftout => CLUT_ADR6A); + + +b2v_sr7 : lpm_shiftreg0 +PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => CLUT_ADR(0), + data => FIFO_D(15 DOWNTO 0), + shiftout => CLUT_ADR7A); + + +b2v_ST_CLUT_BLUE : altdpram0 +PORT MAP(wren_a => ST_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_55, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(18 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_34, + q_b => CCS(7 DOWNTO 5)); + + +b2v_ST_CLUT_GREEN : altdpram0 +PORT MAP(wren_a => ST_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_56, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(22 DOWNTO 20), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_31, + q_b => CCS(15 DOWNTO 13)); + + +b2v_ST_CLUT_RED : altdpram0 +PORT MAP(wren_a => ST_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_57, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(26 DOWNTO 24), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_29, + q_b => CCS(23 DOWNTO 21)); + + +b2v_VIDEO_MOD_MUX_CLUTCTR : video_mod_mux_clutctr +PORT MAP(nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + CLK33M => CLK33M, + CLK25M => CLK25M, + BLITTER_RUN => BLITTER_RUN, + CLK_VIDEO => CLK_VIDEO, + VR_BUSY => VR_BUSY, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VR_D => VR_D, + COLOR8 => COLOR8, + ACP_CLUT_RD => ACP_CLUT_RD, + COLOR1 => COLOR1, + FALCON_CLUT_RDH => FALCON_CLUT_RDH, + FALCON_CLUT_RDL => FALCON_CLUT_RDL, + ST_CLUT_RD => ST_CLUT_RD, + HSYNC => HSYNC, + VSYNC => VSYNC, + nBLANK => nBLANK, + nSYNC => nSYNC, + nPD_VGA => nPD_VGA, + FIFO_RDE => FIFO_RDE, + COLOR2 => COLOR2, + COLOR4 => COLOR4, + PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED, + BLITTER_ON => BLITTER_ON, + VIDEO_MOD_TA => VIDEO_MOD_TA, + INTER_ZEI => INTER_ZEI, + DOP_FIFO_CLR => DOP_FIFO_CLR, + VIDEO_RECONFIG => VIDEO_RECONFIG, + VR_WR => VR_WR, + VR_RD => VR_RD, + CLR_FIFO => CLR_FIFO, + ACP_CLUT_WR => ACP_CLUT_WR, + BORDER_COLOR => BORDER_COLOR, + CCSEL => CCSEL, + CLUT_MUX_ADR => CLUT_MUX_ADR, + CLUT_OFF => CLUT_OFF, + FALCON_CLUT_WR => FALCON_CLUT_WR, + ST_CLUT_WR => ST_CLUT_WR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR); + +PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; + +END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 94b33d9..41e0e96 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -670,11 +670,18 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd set_global_assignment -name VHDL_FILE firebee1.vhd set_global_assignment -name SDC_FILE firebee1.sdc set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name BDF_FILE Video/video.bdf +set_global_assignment -name VHDL_FILE Video/video.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp From 476825a3ba87aeee170305f6e35657703b4afd19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 16:11:04 +0000 Subject: [PATCH 044/127] translate interrupt_controller to vhd --- .../Interrupt_Handler/interrupt_handler.vhd | 6381 +++++++++++++++++ FPGA_Quartus_13.1/Video/video.vhd | 1 + FPGA_Quartus_13.1/firebee1.qsf | 1471 ++-- FPGA_Quartus_13.1/firebee1.sdc | 12 +- FPGA_Quartus_13.1/firebee1.vhd | 1481 ++-- FPGA_Quartus_13.1/lpm_bustri_WORD.vhd | 6 +- 6 files changed, 7740 insertions(+), 1612 deletions(-) create mode 100755 FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd new file mode 100755 index 0000000..425a621 --- /dev/null +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -0,0 +1,6381 @@ +-- Xilinx XPort Language Converter, Version 4.1 (110) +-- +-- AHDL Design Source: interrupt_handler.tdf +-- VHDL Design Output: interrupt_handler.vhd +-- Created 11-Jan-2016 01:42 PM +-- +-- Copyright (c) 2016, Xilinx, Inc. All Rights Reserved. +-- Xilinx Inc makes no warranty, expressed or implied, with respect to +-- the operation and/or functionality of the converted output files. +-- + +-- INTERRUPT HANDLER UND C1287 + + +-- Some names could not be written out to VHDL as they were +-- in the source, and have been changed: +-- +-- AHDL VHDL +-- ==== ==== +-- WERTE0_.q WERTE0_q +-- WERTE0_.ena WERTE0_ena +-- WERTE0_.prn WERTE0_prn +-- WERTE0_.clrn WERTE0_clrn +-- WERTE0_.clk WERTE0_clk +-- WERTE0_.d WERTE0_d +-- WERTE0_ WERTE0 +-- WERTE1_.q WERTE1_q +-- WERTE1_.ena WERTE1_ena +-- WERTE1_.prn WERTE1_prn +-- WERTE1_.clrn WERTE1_clrn +-- WERTE1_.clk WERTE1_clk +-- WERTE1_.d WERTE1_d +-- WERTE1_ WERTE1 +-- WERTE2_.q WERTE2_q +-- WERTE2_.ena WERTE2_ena +-- WERTE2_.prn WERTE2_prn +-- WERTE2_.clrn WERTE2_clrn +-- WERTE2_.clk WERTE2_clk +-- WERTE2_.d WERTE2_d +-- WERTE2_ WERTE2 +-- WERTE3_.q WERTE3_q +-- WERTE3_.ena WERTE3_ena +-- WERTE3_.prn WERTE3_prn +-- WERTE3_.clrn WERTE3_clrn +-- WERTE3_.clk WERTE3_clk +-- WERTE3_.d WERTE3_d +-- WERTE3_ WERTE3 +-- WERTE4_.q WERTE4_q +-- WERTE4_.ena WERTE4_ena +-- WERTE4_.prn WERTE4_prn +-- WERTE4_.clrn WERTE4_clrn +-- WERTE4_.clk WERTE4_clk +-- WERTE4_.d WERTE4_d +-- WERTE4_ WERTE4 +-- WERTE5_.q WERTE5_q +-- WERTE5_.ena WERTE5_ena +-- WERTE5_.prn WERTE5_prn +-- WERTE5_.clrn WERTE5_clrn +-- WERTE5_.clk WERTE5_clk +-- WERTE5_.d WERTE5_d +-- WERTE5_ WERTE5 +-- WERTE6_.q WERTE6_q +-- WERTE6_.ena WERTE6_ena +-- WERTE6_.prn WERTE6_prn +-- WERTE6_.clrn WERTE6_clrn +-- WERTE6_.clk WERTE6_clk +-- WERTE6_.d WERTE6_d +-- WERTE6_ WERTE6 +-- WERTE7_.q WERTE7_q +-- WERTE7_.ena WERTE7_ena +-- WERTE7_.prn WERTE7_prn +-- WERTE7_.clrn WERTE7_clrn +-- WERTE7_.clk WERTE7_clk +-- WERTE7_.d WERTE7_d +-- WERTE7_ WERTE7 +-- INT_LA0_.q INT_LA0_q +-- INT_LA0_.prn INT_LA0_prn +-- INT_LA0_.clrn INT_LA0_clrn +-- INT_LA0_.clk INT_LA0_clk +-- INT_LA0_.d INT_LA0_d +-- INT_LA0_ INT_LA0 +-- INT_LA1_.q INT_LA1_q +-- INT_LA1_.prn INT_LA1_prn +-- INT_LA1_.clrn INT_LA1_clrn +-- INT_LA1_.clk INT_LA1_clk +-- INT_LA1_.d INT_LA1_d +-- INT_LA1_ INT_LA1 +-- INT_LA2_.q INT_LA2_q +-- INT_LA2_.prn INT_LA2_prn +-- INT_LA2_.clrn INT_LA2_clrn +-- INT_LA2_.clk INT_LA2_clk +-- INT_LA2_.d INT_LA2_d +-- INT_LA2_ INT_LA2 +-- INT_LA3_.q INT_LA3_q +-- INT_LA3_.prn INT_LA3_prn +-- INT_LA3_.clrn INT_LA3_clrn +-- INT_LA3_.clk INT_LA3_clk +-- INT_LA3_.d INT_LA3_d +-- INT_LA3_ INT_LA3 +-- INT_LA4_.q INT_LA4_q +-- INT_LA4_.prn INT_LA4_prn +-- INT_LA4_.clrn INT_LA4_clrn +-- INT_LA4_.clk INT_LA4_clk +-- INT_LA4_.d INT_LA4_d +-- INT_LA4_ INT_LA4 +-- INT_LA5_.q INT_LA5_q +-- INT_LA5_.prn INT_LA5_prn +-- INT_LA5_.clrn INT_LA5_clrn +-- INT_LA5_.clk INT_LA5_clk +-- INT_LA5_.d INT_LA5_d +-- INT_LA5_ INT_LA5 +-- INT_LA6_.q INT_LA6_q +-- INT_LA6_.prn INT_LA6_prn +-- INT_LA6_.clrn INT_LA6_clrn +-- INT_LA6_.clk INT_LA6_clk +-- INT_LA6_.d INT_LA6_d +-- INT_LA6_ INT_LA6 +-- INT_LA7_.q INT_LA7_q +-- INT_LA7_.prn INT_LA7_prn +-- INT_LA7_.clrn INT_LA7_clrn +-- INT_LA7_.clk INT_LA7_clk +-- INT_LA7_.d INT_LA7_d +-- INT_LA7_ INT_LA7 +-- INT_LA8_.q INT_LA8_q +-- INT_LA8_.prn INT_LA8_prn +-- INT_LA8_.clrn INT_LA8_clrn +-- INT_LA8_.clk INT_LA8_clk +-- INT_LA8_.d INT_LA8_d +-- INT_LA8_ INT_LA8 +-- INT_LA9_.q INT_LA9_q +-- INT_LA9_.prn INT_LA9_prn +-- INT_LA9_.clrn INT_LA9_clrn +-- INT_LA9_.clk INT_LA9_clk +-- INT_LA9_.d INT_LA9_d +-- INT_LA9_ INT_LA9 + + +-- CREATED BY FREDI ASCHWANDEN +-- Parameters Statement (optional) +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! +-- Subdesign Section +LIBRARY ieee; + USE IEEE.std_logic_1164.all; + USE IEEE.std_logic_arith.all; + +LIBRARY work; + +ENTITY interrupt_handler IS + PORT + ( + MAIN_CLK : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + PIC_INT : IN std_logic; + E0_INT : IN std_logic; + DVI_INT : IN std_logic; + nPCI_INTA : IN std_logic; + nPCI_INTB : IN std_logic; + nPCI_INTC : IN std_logic; + nPCI_INTD : IN std_logic; + nMFP_INT : IN std_logic; + nFB_OE : IN std_logic; + DSP_INT : IN std_logic; + VSYNC : IN std_logic; + HSYNC : IN std_logic; + DMA_DRQ : IN std_logic; + nRSTO : IN std_logic; + nIRQ : BUFFER std_logic_vector(7 DOWNTO 2); + INT_HANDLER_TA : BUFFER std_logic; + ACP_CONF : BUFFER std_logic_vector(31 DOWNTO 0); + TIN0 : BUFFER std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + ); +END interrupt_handler; + + +ARCHITECTURE rtl OF interrupt_handler IS +-- WERTE REGISTER 0-63 + SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_CTR : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_CTR_d : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_CTR_q : std_logic_vector(31 DOWNTO 0); + + SIGNAL INT_LATCH : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_LATCH_d : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_LATCH_clrn : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_LATCH_q : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_LATCH_clk : std_logic_vector(31 DOWNTO 0); + + SIGNAL INT_CLEAR : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_CLEAR_d : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_CLEAR_q : std_logic_vector(31 DOWNTO 0); + + SIGNAL INT_IN : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_ENA : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_ENA_d : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_ENA_q : std_logic_vector(31 DOWNTO 0); + SIGNAL INT_L : std_logic_vector(9 DOWNTO 0); + SIGNAL INT_L_d : std_logic_vector(9 DOWNTO 0); + SIGNAL INT_L_q : std_logic_vector(9 DOWNTO 0); + SIGNAL INT_LA9 : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA9_d : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA9_q : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA8 : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA8_d : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA8_q : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA7 : std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA7_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA7_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA6: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA6_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA6_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA5: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA5_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA5_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA4: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA4_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA4_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA3: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA3_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA3_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA2: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA2_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA2_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA1: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA1_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA1_q: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA0: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA0_d: std_logic_vector(3 DOWNTO 0); + SIGNAL INT_LA0_q: std_logic_vector(3 DOWNTO 0); + + SIGNAL ACP_CONF_d: std_logic_vector(31 DOWNTO 0); + SIGNAL ACP_CONF_q: std_logic_vector(31 DOWNTO 0); + + SIGNAL RTC_ADR: std_logic_vector(5 DOWNTO 0); + SIGNAL RTC_ADR_d: std_logic_vector(5 DOWNTO 0); + SIGNAL RTC_ADR_q: std_logic_vector(5 DOWNTO 0); + + SIGNAL ACHTELSEKUNDEN: std_logic_vector(2 DOWNTO 0); + SIGNAL ACHTELSEKUNDEN_d: std_logic_vector(2 DOWNTO 0); + SIGNAL ACHTELSEKUNDEN_q: std_logic_vector(2 DOWNTO 0); + + SIGNAL WERTE7: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE7_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE7_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE7_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE6: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE6_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE6_clrn: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE6_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE6_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE5: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE5_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE5_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE5_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE4: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE4_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE4_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE4_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE3: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE3_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE3_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE3_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE2: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE2_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE2_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE2_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE1: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE1_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE1_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE1_q: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE0: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE0_d: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE0_ena: std_logic_vector(63 DOWNTO 0); + SIGNAL WERTE0_q: std_logic_vector(63 DOWNTO 0); + + SIGNAL PIC_INT_SYNC: std_logic_vector(2 DOWNTO 0); + SIGNAL PIC_INT_SYNC_d: std_logic_vector(2 DOWNTO 0); + SIGNAL PIC_INT_SYNC_q: std_logic_vector(2 DOWNTO 0); + + SIGNAL ANZAHL_TAGE_DES_MONATS: std_logic_vector(7 DOWNTO 0); + + SIGNAL u0_data: std_logic_vector(7 DOWNTO 0); + SIGNAL u0_tridata: std_logic_vector(7 DOWNTO 0); + + SIGNAL u1_data: std_logic_vector(7 DOWNTO 0); + SIGNAL u1_tridata: std_logic_vector(7 DOWNTO 0); + + SIGNAL u2_data: std_logic_vector(7 DOWNTO 0); + SIGNAL u2_tridata: std_logic_vector(7 DOWNTO 0); + + SIGNAL u3_data: std_logic_vector(7 DOWNTO 0); + SIGNAL u3_tridata: std_logic_vector(7 DOWNTO 0); + + SIGNAL INT_LATCH0_clk_1, INT_LATCH1_clk_1, INT_LATCH2_clk_1, + INT_LATCH3_clk_1, INT_LATCH4_clk_1, INT_LATCH5_clk_1, + INT_LATCH6_clk_1, INT_LATCH7_clk_1, INT_LATCH8_clk_1, + INT_LATCH9_clk_1, INT_CTR0_clk_ctrl, INT_CTR24_ena_ctrl, + INT_CTR16_ena_ctrl, INT_CTR8_ena_ctrl, INT_CTR0_ena_ctrl, + INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl, INT_ENA24_ena_ctrl, + INT_ENA16_ena_ctrl, INT_ENA8_ena_ctrl, INT_ENA0_ena_ctrl, + INT_CLEAR0_clk_ctrl, INT_L0_clk_ctrl, INT_L0_clrn_ctrl, + INT_LA9_0_clk_ctrl, INT_LA8_0_clk_ctrl, INT_LA7_0_clk_ctrl, + INT_LA6_0_clk_ctrl, INT_LA5_0_clk_ctrl, INT_LA4_0_clk_ctrl, + INT_LA3_0_clk_ctrl, INT_LA2_0_clk_ctrl, INT_LA1_0_clk_ctrl, + INT_LA0_0_clk_ctrl, INT_LA0_0_clrn_ctrl, INT_LA1_0_clrn_ctrl, + INT_LA2_0_clrn_ctrl, INT_LA3_0_clrn_ctrl, INT_LA4_0_clrn_ctrl, + INT_LA5_0_clrn_ctrl, INT_LA6_0_clrn_ctrl, INT_LA7_0_clrn_ctrl, + INT_LA8_0_clrn_ctrl, INT_LA9_0_clrn_ctrl, ACP_CONF0_clk_ctrl, + ACP_CONF24_ena_ctrl, ACP_CONF16_ena_ctrl, ACP_CONF8_ena_ctrl, + ACP_CONF0_ena_ctrl, RTC_ADR0_clk_ctrl, RTC_ADR0_ena_ctrl, + WERTE7_0_clk_ctrl, WERTE6_0_clk_ctrl, WERTE5_0_clk_ctrl, + WERTE4_0_clk_ctrl, WERTE3_0_clk_ctrl, WERTE2_0_clk_ctrl, + WERTE1_0_clk_ctrl, WERTE0_0_clk_ctrl, WERTE0_1_ena_ctrl, + WERTE0_3_ena_ctrl, WERTE0_5_ena_ctrl, WERTE0_10_ena_ctrl, + WERTE0_11_ena_ctrl, WERTE0_12_ena_ctrl, WERTE0_14_ena_ctrl, + WERTE0_15_ena_ctrl, WERTE0_16_ena_ctrl, WERTE0_17_ena_ctrl, + WERTE0_18_ena_ctrl, WERTE0_19_ena_ctrl, WERTE0_20_ena_ctrl, + WERTE0_21_ena_ctrl, WERTE0_22_ena_ctrl, WERTE0_23_ena_ctrl, + WERTE0_24_ena_ctrl, WERTE0_25_ena_ctrl, WERTE0_26_ena_ctrl, + WERTE0_27_ena_ctrl, WERTE0_28_ena_ctrl, WERTE0_29_ena_ctrl, + WERTE0_30_ena_ctrl, WERTE0_31_ena_ctrl, WERTE0_32_ena_ctrl, + WERTE0_33_ena_ctrl, WERTE0_34_ena_ctrl, WERTE0_35_ena_ctrl, + WERTE0_36_ena_ctrl, WERTE0_37_ena_ctrl, WERTE0_38_ena_ctrl, + WERTE0_39_ena_ctrl, WERTE0_40_ena_ctrl, WERTE0_41_ena_ctrl, + WERTE0_42_ena_ctrl, WERTE0_43_ena_ctrl, WERTE0_44_ena_ctrl, + WERTE0_45_ena_ctrl, WERTE0_46_ena_ctrl, WERTE0_47_ena_ctrl, + WERTE0_48_ena_ctrl, WERTE0_49_ena_ctrl, WERTE0_50_ena_ctrl, + WERTE0_51_ena_ctrl, WERTE0_52_ena_ctrl, WERTE0_53_ena_ctrl, + WERTE0_54_ena_ctrl, WERTE0_55_ena_ctrl, WERTE0_56_ena_ctrl, + WERTE0_57_ena_ctrl, WERTE0_58_ena_ctrl, WERTE0_59_ena_ctrl, + WERTE0_60_ena_ctrl, WERTE0_61_ena_ctrl, WERTE0_62_ena_ctrl, + WERTE0_63_ena_ctrl, PIC_INT_SYNC0_clk_ctrl, ACHTELSEKUNDEN0_clk_ctrl, + ACHTELSEKUNDEN0_ena_ctrl, WERTE7_13_d_2, WERTE7_13_d_1, WERTE7_9_d_2, + WERTE7_9_d_1, WERTE7_8_d_2, WERTE7_8_d_1, WERTE7_7_d_2, WERTE7_7_d_1, + WERTE7_6_d_2, WERTE7_6_d_1, WERTE7_4_d_2, WERTE7_4_d_1, WERTE7_2_d_2, + WERTE7_2_d_1, WERTE7_0_d_2, WERTE7_0_d_1, WERTE7_9_ena_2, + WERTE7_9_ena_1, WERTE7_8_ena_2, WERTE7_8_ena_1, WERTE7_7_ena_2, + WERTE7_7_ena_1, WERTE7_6_ena_2, WERTE7_6_ena_1, WERTE7_4_ena_2, + WERTE7_4_ena_1, WERTE7_2_ena_2, WERTE7_2_ena_1, WERTE7_0_ena_2, + WERTE7_0_ena_1, WERTE6_9_d_2, WERTE6_9_d_1, WERTE6_8_d_2, + WERTE6_8_d_1, WERTE6_7_d_2, WERTE6_7_d_1, WERTE6_6_d_2, WERTE6_6_d_1, + WERTE6_4_d_2, WERTE6_4_d_1, WERTE6_2_d_2, WERTE6_2_d_1, WERTE6_0_d_2, + WERTE6_0_d_1, WERTE6_9_ena_2, WERTE6_9_ena_1, WERTE6_8_ena_2, + WERTE6_8_ena_1, WERTE6_7_ena_2, WERTE6_7_ena_1, WERTE6_6_ena_2, + WERTE6_6_ena_1, WERTE6_4_ena_2, WERTE6_4_ena_1, WERTE6_2_ena_2, + WERTE6_2_ena_1, WERTE6_0_ena_2, WERTE6_0_ena_1, WERTE5_9_d_2, + WERTE5_9_d_1, WERTE5_8_d_2, WERTE5_8_d_1, WERTE5_7_d_2, WERTE5_7_d_1, + WERTE5_6_d_2, WERTE5_6_d_1, WERTE5_4_d_2, WERTE5_4_d_1, WERTE5_2_d_2, + WERTE5_2_d_1, WERTE5_0_d_2, WERTE5_0_d_1, WERTE5_9_ena_2, + WERTE5_9_ena_1, WERTE5_8_ena_2, WERTE5_8_ena_1, WERTE5_7_ena_2, + WERTE5_7_ena_1, WERTE5_6_ena_2, WERTE5_6_ena_1, WERTE5_4_ena_2, + WERTE5_4_ena_1, WERTE5_2_ena_2, WERTE5_2_ena_1, WERTE5_0_ena_2, + WERTE5_0_ena_1, WERTE4_9_d_2, WERTE4_9_d_1, WERTE4_8_d_2, + WERTE4_8_d_1, WERTE4_7_d_2, WERTE4_7_d_1, WERTE4_6_d_2, WERTE4_6_d_1, + WERTE4_4_d_2, WERTE4_4_d_1, WERTE4_2_d_2, WERTE4_2_d_1, WERTE4_0_d_2, + WERTE4_0_d_1, WERTE4_9_ena_2, WERTE4_9_ena_1, WERTE4_8_ena_2, + WERTE4_8_ena_1, WERTE4_7_ena_2, WERTE4_7_ena_1, WERTE4_6_ena_2, + WERTE4_6_ena_1, WERTE4_4_ena_2, WERTE4_4_ena_1, WERTE4_2_ena_2, + WERTE4_2_ena_1, WERTE4_0_ena_2, WERTE4_0_ena_1, WERTE3_9_d_2, + WERTE3_9_d_1, WERTE3_8_d_2, WERTE3_8_d_1, WERTE3_7_d_2, WERTE3_7_d_1, + WERTE3_6_d_2, WERTE3_6_d_1, WERTE3_4_d_2, WERTE3_4_d_1, WERTE3_2_d_2, + WERTE3_2_d_1, WERTE3_0_d_2, WERTE3_0_d_1, WERTE3_9_ena_2, + WERTE3_9_ena_1, WERTE3_8_ena_2, WERTE3_8_ena_1, WERTE3_7_ena_2, + WERTE3_7_ena_1, WERTE3_6_ena_2, WERTE3_6_ena_1, WERTE3_4_ena_2, + WERTE3_4_ena_1, WERTE3_2_ena_2, WERTE3_2_ena_1, WERTE3_0_ena_2, + WERTE3_0_ena_1, WERTE2_11_d_2, WERTE2_11_d_1, WERTE2_9_d_2, + WERTE2_9_d_1, WERTE2_8_d_2, WERTE2_8_d_1, WERTE2_7_d_2, WERTE2_7_d_1, + WERTE2_6_d_2, WERTE2_6_d_1, WERTE2_4_d_2, WERTE2_4_d_1, WERTE2_2_d_2, + WERTE2_2_d_1, WERTE2_0_d_2, WERTE2_0_d_1, WERTE2_9_ena_2, + WERTE2_9_ena_1, WERTE2_8_ena_2, WERTE2_8_ena_1, WERTE2_7_ena_2, + WERTE2_7_ena_1, WERTE2_6_ena_2, WERTE2_6_ena_1, WERTE2_4_ena_2, + WERTE2_4_ena_1, WERTE2_2_ena_2, WERTE2_2_ena_1, WERTE2_0_ena_2, + WERTE2_0_ena_1, WERTE1_11_d_2, WERTE1_11_d_1, WERTE1_9_d_2, + WERTE1_9_d_1, WERTE1_8_d_2, WERTE1_8_d_1, WERTE1_7_d_2, WERTE1_7_d_1, + WERTE1_6_d_2, WERTE1_6_d_1, WERTE1_4_d_2, WERTE1_4_d_1, WERTE1_2_d_2, + WERTE1_2_d_1, WERTE1_0_d_2, WERTE1_0_d_1, WERTE1_9_ena_2, + WERTE1_9_ena_1, WERTE1_8_ena_2, WERTE1_8_ena_1, WERTE1_7_ena_2, + WERTE1_7_ena_1, WERTE1_6_ena_2, WERTE1_6_ena_1, WERTE1_4_ena_2, + WERTE1_4_ena_1, WERTE1_2_ena_2, WERTE1_2_ena_1, WERTE1_0_ena_2, + WERTE1_0_ena_1, WERTE0_13_d_2, WERTE0_13_d_1, WERTE0_11_d_2, + WERTE0_11_d_1, WERTE0_9_d_2, WERTE0_9_d_1, WERTE0_8_d_2, WERTE0_8_d_1, + WERTE0_7_d_2, WERTE0_7_d_1, WERTE0_6_d_2, WERTE0_6_d_1, WERTE0_4_d_2, + WERTE0_4_d_1, WERTE0_2_d_2, WERTE0_2_d_1, WERTE0_0_d_2, WERTE0_0_d_1, + WERTE0_13_ena_2, WERTE0_13_ena_1, WERTE0_9_ena_2, WERTE0_9_ena_1, + WERTE0_8_ena_2, WERTE0_8_ena_1, WERTE0_7_ena_2, WERTE0_7_ena_1, + WERTE0_6_ena_2, WERTE0_6_ena_1, WERTE0_4_ena_2, WERTE0_4_ena_1, + WERTE0_2_ena_2, WERTE0_2_ena_1, WERTE0_0_ena_2, WERTE0_0_ena_1, + UPDATE_ON_2, UPDATE_ON_1, u3_enabledt, u2_enabledt, u1_enabledt, + u0_enabledt, vcc, gnd, UPDATE_ON, INC_JAHR, INC_MONAT, SOMMERZEIT, + WINTERZEIT, INC_TAG, INC_STD, INC_MIN, INC_SEC, UHR_DS, UHR_AS, + PSEUDO_BUS_ERROR, ACP_CONF_CS, INT_ENA_CS, INT_CLEAR_CS, INT_LATCH_CS, + INT_CTR_CS: std_logic; + + FUNCTION to_std_logic(X: IN boolean) RETURN std_logic IS + VARIABLE ret : std_logic; + BEGIN + IF x THEN + ret := '1'; + ELSE + ret := '0'; + END IF; + RETURN ret; + END to_std_logic; + + + -- sizeIt replicates a value to an array of specific length. + FUNCTION sizeIt(a: std_logic; len: integer) RETURN std_logic_vector IS + VARIABLE rep: std_logic_vector( len - 1 DOWNTO 0); + BEGIN + FOR i IN rep'RANGE LOOP + rep(i) := a; + END loop; + RETURN rep; + END sizeit; +BEGIN + +-- Sub Module Section + u0: work.lpm_bustri_BYT + PORT MAP + ( + data => u0_data, + enabledt => u0_enabledt, + tridata => u0_tridata + ); + + u1: work.lpm_bustri_BYT + PORT MAP + ( + data => u1_data, + enabledt => u1_enabledt, + tridata => u1_tridata + ); + + u2: work.lpm_bustri_BYT + PORT MAP + ( + data => u2_data, + enabledt => u2_enabledt, + tridata => u2_tridata + ); + + u3: work.lpm_bustri_BYT + PORT MAP + ( + data => u3_data, + enabledt => u3_enabledt, + tridata => u3_tridata + ); + +-- Register Section + + ACP_CONF(31 DOWNTO 24) <= ACP_CONF_q(31 DOWNTO 24); + + PROCESS (ACP_CONF0_clk_ctrl) + BEGIN + IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN + IF ACP_CONF24_ena_ctrl='1' THEN + (ACP_CONF_q(31), ACP_CONF_q(30), ACP_CONF_q(29), ACP_CONF_q(28), + ACP_CONF_q(27), ACP_CONF_q(26), ACP_CONF_q(25), + ACP_CONF_q(24)) <= ACP_CONF_d(31 DOWNTO 24); + END IF; + END IF; + END PROCESS; + + ACP_CONF(23 DOWNTO 16) <= ACP_CONF_q(23 DOWNTO 16); + + PROCESS (ACP_CONF0_clk_ctrl) + BEGIN + IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN + IF ACP_CONF16_ena_ctrl='1' THEN + (ACP_CONF_q(23), ACP_CONF_q(22), ACP_CONF_q(21), ACP_CONF_q(20), + ACP_CONF_q(19), ACP_CONF_q(18), ACP_CONF_q(17), + ACP_CONF_q(16)) <= ACP_CONF_d(23 DOWNTO 16); + END IF; + END IF; + END PROCESS; + + ACP_CONF(15 DOWNTO 8) <= ACP_CONF_q(15 DOWNTO 8); + + PROCESS (ACP_CONF0_clk_ctrl) + BEGIN + IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN + IF ACP_CONF8_ena_ctrl='1' THEN + (ACP_CONF_q(15), ACP_CONF_q(14), ACP_CONF_q(13), ACP_CONF_q(12), + ACP_CONF_q(11), ACP_CONF_q(10), ACP_CONF_q(9), ACP_CONF_q(8)) + <= ACP_CONF_d(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; + + ACP_CONF(7 DOWNTO 0) <= ACP_CONF_q(7 DOWNTO 0); + + PROCESS (ACP_CONF0_clk_ctrl) + BEGIN + IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN + IF ACP_CONF0_ena_ctrl='1' THEN + (ACP_CONF_q(7), ACP_CONF_q(6), ACP_CONF_q(5), ACP_CONF_q(4), + ACP_CONF_q(3), ACP_CONF_q(2), ACP_CONF_q(1), ACP_CONF_q(0)) + <= ACP_CONF_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_CTR0_clk_ctrl) BEGIN + IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN + IF INT_CTR24_ena_ctrl='1' THEN + (INT_CTR_q(31), INT_CTR_q(30), INT_CTR_q(29), INT_CTR_q(28), + INT_CTR_q(27), INT_CTR_q(26), INT_CTR_q(25), INT_CTR_q(24)) + <= INT_CTR_d(31 DOWNTO 24); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_CTR0_clk_ctrl) BEGIN + IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN + IF INT_CTR16_ena_ctrl='1' THEN + (INT_CTR_q(23), INT_CTR_q(22), INT_CTR_q(21), INT_CTR_q(20), + INT_CTR_q(19), INT_CTR_q(18), INT_CTR_q(17), INT_CTR_q(16)) + <= INT_CTR_d(23 DOWNTO 16); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_CTR0_clk_ctrl) BEGIN + IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN + IF INT_CTR8_ena_ctrl='1' THEN + (INT_CTR_q(15), INT_CTR_q(14), INT_CTR_q(13), INT_CTR_q(12), + INT_CTR_q(11), INT_CTR_q(10), INT_CTR_q(9), INT_CTR_q(8)) <= + INT_CTR_d(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_CTR0_clk_ctrl) BEGIN + IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN + IF INT_CTR0_ena_ctrl='1' THEN + (INT_CTR_q(7), INT_CTR_q(6), INT_CTR_q(5), INT_CTR_q(4), + INT_CTR_q(3), INT_CTR_q(2), INT_CTR_q(1), INT_CTR_q(0)) <= + INT_CTR_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(31)='0' THEN + INT_LATCH_q(31) <= '0'; + ELSIF INT_LATCH_clk(31)'event and INT_LATCH_clk(31)='1' THEN + INT_LATCH_q(31) <= INT_LATCH_d(31); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(30)='0' THEN + INT_LATCH_q(30) <= '0'; + ELSIF INT_LATCH_clk(30)'event and INT_LATCH_clk(30)='1' THEN + INT_LATCH_q(30) <= INT_LATCH_d(30); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(29)='0' THEN + INT_LATCH_q(29) <= '0'; + ELSIF INT_LATCH_clk(29)'event and INT_LATCH_clk(29)='1' THEN + INT_LATCH_q(29) <= INT_LATCH_d(29); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(28)='0' THEN + INT_LATCH_q(28) <= '0'; + ELSIF INT_LATCH_clk(28)'event and INT_LATCH_clk(28)='1' THEN + INT_LATCH_q(28) <= INT_LATCH_d(28); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(27)='0' THEN + INT_LATCH_q(27) <= '0'; + ELSIF INT_LATCH_clk(27)'event and INT_LATCH_clk(27)='1' THEN + INT_LATCH_q(27) <= INT_LATCH_d(27); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(26)='0' THEN + INT_LATCH_q(26) <= '0'; + ELSIF INT_LATCH_clk(26)'event and INT_LATCH_clk(26)='1' THEN + INT_LATCH_q(26) <= INT_LATCH_d(26); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(25)='0' THEN + INT_LATCH_q(25) <= '0'; + ELSIF INT_LATCH_clk(25)'event and INT_LATCH_clk(25)='1' THEN + INT_LATCH_q(25) <= INT_LATCH_d(25); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(24)='0' THEN + INT_LATCH_q(24) <= '0'; + ELSIF INT_LATCH_clk(24)'event and INT_LATCH_clk(24)='1' THEN + INT_LATCH_q(24) <= INT_LATCH_d(24); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(23)='0' THEN + INT_LATCH_q(23) <= '0'; + ELSIF INT_LATCH_clk(23)'event and INT_LATCH_clk(23)='1' THEN + INT_LATCH_q(23) <= INT_LATCH_d(23); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(22)='0' THEN + INT_LATCH_q(22) <= '0'; + ELSIF INT_LATCH_clk(22)'event and INT_LATCH_clk(22)='1' THEN + INT_LATCH_q(22) <= INT_LATCH_d(22); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(21)='0' THEN + INT_LATCH_q(21) <= '0'; + ELSIF INT_LATCH_clk(21)'event and INT_LATCH_clk(21)='1' THEN + INT_LATCH_q(21) <= INT_LATCH_d(21); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(20)='0' THEN + INT_LATCH_q(20) <= '0'; + ELSIF INT_LATCH_clk(20)'event and INT_LATCH_clk(20)='1' THEN + INT_LATCH_q(20) <= INT_LATCH_d(20); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(19)='0' THEN + INT_LATCH_q(19) <= '0'; + ELSIF INT_LATCH_clk(19)'event and INT_LATCH_clk(19)='1' THEN + INT_LATCH_q(19) <= INT_LATCH_d(19); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(18)='0' THEN + INT_LATCH_q(18) <= '0'; + ELSIF INT_LATCH_clk(18)'event and INT_LATCH_clk(18)='1' THEN + INT_LATCH_q(18) <= INT_LATCH_d(18); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(17)='0' THEN + INT_LATCH_q(17) <= '0'; + ELSIF INT_LATCH_clk(17)'event and INT_LATCH_clk(17)='1' THEN + INT_LATCH_q(17) <= INT_LATCH_d(17); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(16)='0' THEN + INT_LATCH_q(16) <= '0'; + ELSIF INT_LATCH_clk(16)'event and INT_LATCH_clk(16)='1' THEN + INT_LATCH_q(16) <= INT_LATCH_d(16); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(15)='0' THEN + INT_LATCH_q(15) <= '0'; + ELSIF INT_LATCH_clk(15)'event and INT_LATCH_clk(15)='1' THEN + INT_LATCH_q(15) <= INT_LATCH_d(15); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(14)='0' THEN + INT_LATCH_q(14) <= '0'; + ELSIF INT_LATCH_clk(14)'event and INT_LATCH_clk(14)='1' THEN + INT_LATCH_q(14) <= INT_LATCH_d(14); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(13)='0' THEN + INT_LATCH_q(13) <= '0'; + ELSIF INT_LATCH_clk(13)'event and INT_LATCH_clk(13)='1' THEN + INT_LATCH_q(13) <= INT_LATCH_d(13); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(12)='0' THEN + INT_LATCH_q(12) <= '0'; + ELSIF INT_LATCH_clk(12)'event and INT_LATCH_clk(12)='1' THEN + INT_LATCH_q(12) <= INT_LATCH_d(12); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(11)='0' THEN + INT_LATCH_q(11) <= '0'; + ELSIF INT_LATCH_clk(11)'event and INT_LATCH_clk(11)='1' THEN + INT_LATCH_q(11) <= INT_LATCH_d(11); + END IF; + END PROCESS; + + PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(10)='0' THEN + INT_LATCH_q(10) <= '0'; + ELSIF INT_LATCH_clk(10)'event and INT_LATCH_clk(10)='1' THEN + INT_LATCH_q(10) <= INT_LATCH_d(10); + END IF; + END PROCESS; + + PROCESS (INT_LATCH9_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(9)='0' THEN + INT_LATCH_q(9) <= '0'; + ELSIF INT_LATCH9_clk_1'event and INT_LATCH9_clk_1='1' THEN + INT_LATCH_q(9) <= INT_LATCH_d(9); + END IF; + END PROCESS; + + PROCESS (INT_LATCH8_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(8)='0' THEN + INT_LATCH_q(8) <= '0'; + ELSIF INT_LATCH8_clk_1'event and INT_LATCH8_clk_1='1' THEN + INT_LATCH_q(8) <= INT_LATCH_d(8); + END IF; + END PROCESS; + + PROCESS (INT_LATCH7_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(7)='0' THEN + INT_LATCH_q(7) <= '0'; + ELSIF INT_LATCH7_clk_1'event and INT_LATCH7_clk_1='1' THEN + INT_LATCH_q(7) <= INT_LATCH_d(7); + END IF; + END PROCESS; + + PROCESS (INT_LATCH6_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(6)='0' THEN + INT_LATCH_q(6) <= '0'; + ELSIF INT_LATCH6_clk_1'event and INT_LATCH6_clk_1='1' THEN + INT_LATCH_q(6) <= INT_LATCH_d(6); + END IF; + END PROCESS; + + PROCESS (INT_LATCH5_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(5)='0' THEN + INT_LATCH_q(5) <= '0'; + ELSIF INT_LATCH5_clk_1'event and INT_LATCH5_clk_1='1' THEN + INT_LATCH_q(5) <= INT_LATCH_d(5); + END IF; + END PROCESS; + + PROCESS (INT_LATCH4_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(4)='0' THEN + INT_LATCH_q(4) <= '0'; + ELSIF INT_LATCH4_clk_1'event and INT_LATCH4_clk_1='1' THEN + INT_LATCH_q(4) <= INT_LATCH_d(4); + END IF; + END PROCESS; + + PROCESS (INT_LATCH3_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(3)='0' THEN + INT_LATCH_q(3) <= '0'; + ELSIF INT_LATCH3_clk_1'event and INT_LATCH3_clk_1='1' THEN + INT_LATCH_q(3) <= INT_LATCH_d(3); + END IF; + END PROCESS; + + PROCESS (INT_LATCH2_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(2)='0' THEN + INT_LATCH_q(2) <= '0'; + ELSIF INT_LATCH2_clk_1'event and INT_LATCH2_clk_1='1' THEN + INT_LATCH_q(2) <= INT_LATCH_d(2); + END IF; + END PROCESS; + + PROCESS (INT_LATCH1_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(1)='0' THEN + INT_LATCH_q(1) <= '0'; + ELSIF INT_LATCH1_clk_1'event and INT_LATCH1_clk_1='1' THEN + INT_LATCH_q(1) <= INT_LATCH_d(1); + END IF; + END PROCESS; + + PROCESS (INT_LATCH0_clk_1, INT_LATCH_clrn) BEGIN + IF INT_LATCH_clrn(0)='0' THEN + INT_LATCH_q(0) <= '0'; + ELSIF INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' THEN + INT_LATCH_q(0) <= INT_LATCH_d(0); + END IF; + END PROCESS; + + PROCESS (INT_CLEAR0_clk_ctrl) BEGIN + IF INT_CLEAR0_clk_ctrl'event and INT_CLEAR0_clk_ctrl='1' THEN + INT_CLEAR_q <= INT_CLEAR_d; + END IF; + END PROCESS; + + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), + INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= + std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA24_ena_ctrl='1' THEN + (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), + INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) + <= INT_ENA_d(31 DOWNTO 24); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), + INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= + std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA16_ena_ctrl='1' THEN + (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), + INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) + <= INT_ENA_d(23 DOWNTO 16); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), + INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= + std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA8_ena_ctrl='1' THEN + (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), + INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= + INT_ENA_d(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), + INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= + std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA0_ena_ctrl='1' THEN + (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), + INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= + INT_ENA_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + PROCESS (INT_L0_clk_ctrl, INT_L0_clrn_ctrl) BEGIN + IF INT_L0_clrn_ctrl='0' THEN + INT_L_q <= std_logic_vector'("0000000000"); + ELSIF INT_L0_clk_ctrl'event and INT_L0_clk_ctrl='1' THEN + INT_L_q <= INT_L_d; + END IF; + END PROCESS; + + PROCESS (INT_LA9_0_clk_ctrl, INT_LA9_0_clrn_ctrl) BEGIN + IF INT_LA9_0_clrn_ctrl='0' THEN + INT_LA9_q <= std_logic_vector'("0000"); + ELSIF INT_LA9_0_clk_ctrl'event and INT_LA9_0_clk_ctrl='1' THEN + INT_LA9_q <= INT_LA9_d; + END IF; + END PROCESS; + + PROCESS (INT_LA8_0_clk_ctrl, INT_LA8_0_clrn_ctrl) BEGIN + IF INT_LA8_0_clrn_ctrl='0' THEN + INT_LA8_q <= std_logic_vector'("0000"); + ELSIF INT_LA8_0_clk_ctrl'event and INT_LA8_0_clk_ctrl='1' THEN + INT_LA8_q <= INT_LA8_d; + END IF; + END PROCESS; + + PROCESS (INT_LA7_0_clk_ctrl, INT_LA7_0_clrn_ctrl) BEGIN + IF INT_LA7_0_clrn_ctrl='0' THEN + INT_LA7_q <= std_logic_vector'("0000"); + ELSIF INT_LA7_0_clk_ctrl'event and INT_LA7_0_clk_ctrl='1' THEN + INT_LA7_q <= INT_LA7_d; + END IF; + END PROCESS; + + PROCESS (INT_LA6_0_clk_ctrl, INT_LA6_0_clrn_ctrl) BEGIN + IF INT_LA6_0_clrn_ctrl='0' THEN + INT_LA6_q <= std_logic_vector'("0000"); + ELSIF INT_LA6_0_clk_ctrl'event and INT_LA6_0_clk_ctrl='1' THEN + INT_LA6_q <= INT_LA6_d; + END IF; + END PROCESS; + + PROCESS (INT_LA5_0_clk_ctrl, INT_LA5_0_clrn_ctrl) BEGIN + IF INT_LA5_0_clrn_ctrl='0' THEN + INT_LA5_q <= std_logic_vector'("0000"); + ELSIF INT_LA5_0_clk_ctrl'event and INT_LA5_0_clk_ctrl='1' THEN + INT_LA5_q <= INT_LA5_d; + END IF; + END PROCESS; + + PROCESS (INT_LA4_0_clk_ctrl, INT_LA4_0_clrn_ctrl) BEGIN + IF INT_LA4_0_clrn_ctrl='0' THEN + INT_LA4_q <= std_logic_vector'("0000"); + ELSIF INT_LA4_0_clk_ctrl'event and INT_LA4_0_clk_ctrl='1' THEN + INT_LA4_q <= INT_LA4_d; + END IF; + END PROCESS; + + PROCESS (INT_LA3_0_clk_ctrl, INT_LA3_0_clrn_ctrl) BEGIN + IF INT_LA3_0_clrn_ctrl='0' THEN + INT_LA3_q <= std_logic_vector'("0000"); + ELSIF INT_LA3_0_clk_ctrl'event and INT_LA3_0_clk_ctrl='1' THEN + INT_LA3_q <= INT_LA3_d; + END IF; + END PROCESS; + + PROCESS (INT_LA2_0_clk_ctrl, INT_LA2_0_clrn_ctrl) BEGIN + IF INT_LA2_0_clrn_ctrl='0' THEN + INT_LA2_q <= std_logic_vector'("0000"); + ELSIF INT_LA2_0_clk_ctrl'event and INT_LA2_0_clk_ctrl='1' THEN + INT_LA2_q <= INT_LA2_d; + END IF; + END PROCESS; + + PROCESS (INT_LA1_0_clk_ctrl, INT_LA1_0_clrn_ctrl) BEGIN + IF INT_LA1_0_clrn_ctrl='0' THEN + INT_LA1_q <= std_logic_vector'("0000"); + ELSIF INT_LA1_0_clk_ctrl'event and INT_LA1_0_clk_ctrl='1' THEN + INT_LA1_q <= INT_LA1_d; + END IF; + END PROCESS; + + PROCESS (INT_LA0_0_clk_ctrl, INT_LA0_0_clrn_ctrl) BEGIN + IF INT_LA0_0_clrn_ctrl='0' THEN + INT_LA0_q <= std_logic_vector'("0000"); + ELSIF INT_LA0_0_clk_ctrl'event and INT_LA0_0_clk_ctrl='1' THEN + INT_LA0_q <= INT_LA0_d; + END IF; + END PROCESS; + + PROCESS (RTC_ADR0_clk_ctrl) BEGIN + IF RTC_ADR0_clk_ctrl'event and RTC_ADR0_clk_ctrl='1' THEN + IF RTC_ADR0_ena_ctrl='1' THEN + RTC_ADR_q <= RTC_ADR_d; + END IF; + END IF; + END PROCESS; + + PROCESS (ACHTELSEKUNDEN0_clk_ctrl) BEGIN + IF ACHTELSEKUNDEN0_clk_ctrl'event and ACHTELSEKUNDEN0_clk_ctrl='1' THEN + IF ACHTELSEKUNDEN0_ena_ctrl='1' THEN + ACHTELSEKUNDEN_q <= ACHTELSEKUNDEN_d; + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE7_q(63) <= WERTE7_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE7_q(62) <= WERTE7_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE7_q(61) <= WERTE7_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE7_q(60) <= WERTE7_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE7_q(59) <= WERTE7_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE7_q(58) <= WERTE7_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE7_q(57) <= WERTE7_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE7_q(56) <= WERTE7_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE7_q(55) <= WERTE7_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE7_q(54) <= WERTE7_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE7_q(53) <= WERTE7_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE7_q(52) <= WERTE7_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE7_q(51) <= WERTE7_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE7_q(50) <= WERTE7_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE7_q(49) <= WERTE7_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE7_q(48) <= WERTE7_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE7_q(47) <= WERTE7_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE7_q(46) <= WERTE7_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE7_q(45) <= WERTE7_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE7_q(44) <= WERTE7_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE7_q(43) <= WERTE7_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE7_q(42) <= WERTE7_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE7_q(41) <= WERTE7_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE7_q(40) <= WERTE7_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE7_q(39) <= WERTE7_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE7_q(38) <= WERTE7_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE7_q(37) <= WERTE7_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE7_q(36) <= WERTE7_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE7_q(35) <= WERTE7_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE7_q(34) <= WERTE7_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE7_q(33) <= WERTE7_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE7_q(32) <= WERTE7_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE7_q(31) <= WERTE7_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE7_q(30) <= WERTE7_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE7_q(29) <= WERTE7_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE7_q(28) <= WERTE7_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE7_q(27) <= WERTE7_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE7_q(26) <= WERTE7_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE7_q(25) <= WERTE7_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE7_q(24) <= WERTE7_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE7_q(23) <= WERTE7_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE7_q(22) <= WERTE7_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE7_q(21) <= WERTE7_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE7_q(20) <= WERTE7_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE7_q(19) <= WERTE7_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE7_q(18) <= WERTE7_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE7_q(17) <= WERTE7_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE7_q(16) <= WERTE7_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE7_q(15) <= WERTE7_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE7_q(14) <= WERTE7_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(13)='1' THEN + WERTE7_q(13) <= WERTE7_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE7_q(12) <= WERTE7_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE7_q(11) <= WERTE7_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE7_q(10) <= WERTE7_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(9)='1' THEN + WERTE7_q(9) <= WERTE7_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(8)='1' THEN + WERTE7_q(8) <= WERTE7_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(7)='1' THEN + WERTE7_q(7) <= WERTE7_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(6)='1' THEN + WERTE7_q(6) <= WERTE7_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE7_q(5) <= WERTE7_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(4)='1' THEN + WERTE7_q(4) <= WERTE7_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE7_q(3) <= WERTE7_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(2)='1' THEN + WERTE7_q(2) <= WERTE7_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE7_q(1) <= WERTE7_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE7_0_clk_ctrl) BEGIN + IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN + IF WERTE7_ena(0)='1' THEN + WERTE7_q(0) <= WERTE7_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE6_q(63) <= WERTE6_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE6_q(62) <= WERTE6_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE6_q(61) <= WERTE6_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE6_q(60) <= WERTE6_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE6_q(59) <= WERTE6_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE6_q(58) <= WERTE6_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE6_q(57) <= WERTE6_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE6_q(56) <= WERTE6_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE6_q(55) <= WERTE6_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE6_q(54) <= WERTE6_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE6_q(53) <= WERTE6_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE6_q(52) <= WERTE6_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE6_q(51) <= WERTE6_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE6_q(50) <= WERTE6_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE6_q(49) <= WERTE6_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE6_q(48) <= WERTE6_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE6_q(47) <= WERTE6_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE6_q(46) <= WERTE6_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE6_q(45) <= WERTE6_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE6_q(44) <= WERTE6_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE6_q(43) <= WERTE6_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE6_q(42) <= WERTE6_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE6_q(41) <= WERTE6_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE6_q(40) <= WERTE6_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE6_q(39) <= WERTE6_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE6_q(38) <= WERTE6_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE6_q(37) <= WERTE6_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE6_q(36) <= WERTE6_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE6_q(35) <= WERTE6_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE6_q(34) <= WERTE6_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE6_q(33) <= WERTE6_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE6_q(32) <= WERTE6_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE6_q(31) <= WERTE6_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE6_q(30) <= WERTE6_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE6_q(29) <= WERTE6_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE6_q(28) <= WERTE6_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE6_q(27) <= WERTE6_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE6_q(26) <= WERTE6_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE6_q(25) <= WERTE6_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE6_q(24) <= WERTE6_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE6_q(23) <= WERTE6_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE6_q(22) <= WERTE6_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE6_q(21) <= WERTE6_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE6_q(20) <= WERTE6_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE6_q(19) <= WERTE6_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE6_q(18) <= WERTE6_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE6_q(17) <= WERTE6_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE6_q(16) <= WERTE6_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE6_q(15) <= WERTE6_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE6_q(14) <= WERTE6_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(13)='1' THEN + WERTE6_q(13) <= WERTE6_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE6_q(12) <= WERTE6_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE6_q(11) <= WERTE6_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl, WERTE6_clrn) BEGIN + IF WERTE6_clrn(10)='0' THEN + WERTE6_q(10) <= '0'; + ELSIF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE6_q(10) <= WERTE6_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(9)='1' THEN + WERTE6_q(9) <= WERTE6_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(8)='1' THEN + WERTE6_q(8) <= WERTE6_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(7)='1' THEN + WERTE6_q(7) <= WERTE6_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(6)='1' THEN + WERTE6_q(6) <= WERTE6_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE6_q(5) <= WERTE6_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(4)='1' THEN + WERTE6_q(4) <= WERTE6_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE6_q(3) <= WERTE6_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(2)='1' THEN + WERTE6_q(2) <= WERTE6_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE6_q(1) <= WERTE6_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE6_0_clk_ctrl) BEGIN + IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN + IF WERTE6_ena(0)='1' THEN + WERTE6_q(0) <= WERTE6_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE5_q(63) <= WERTE5_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE5_q(62) <= WERTE5_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE5_q(61) <= WERTE5_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE5_q(60) <= WERTE5_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE5_q(59) <= WERTE5_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE5_q(58) <= WERTE5_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE5_q(57) <= WERTE5_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE5_q(56) <= WERTE5_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE5_q(55) <= WERTE5_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE5_q(54) <= WERTE5_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE5_q(53) <= WERTE5_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE5_q(52) <= WERTE5_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE5_q(51) <= WERTE5_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE5_q(50) <= WERTE5_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE5_q(49) <= WERTE5_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE5_q(48) <= WERTE5_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE5_q(47) <= WERTE5_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE5_q(46) <= WERTE5_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE5_q(45) <= WERTE5_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE5_q(44) <= WERTE5_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE5_q(43) <= WERTE5_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE5_q(42) <= WERTE5_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE5_q(41) <= WERTE5_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE5_q(40) <= WERTE5_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE5_q(39) <= WERTE5_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE5_q(38) <= WERTE5_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE5_q(37) <= WERTE5_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE5_q(36) <= WERTE5_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE5_q(35) <= WERTE5_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE5_q(34) <= WERTE5_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE5_q(33) <= WERTE5_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE5_q(32) <= WERTE5_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE5_q(31) <= WERTE5_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE5_q(30) <= WERTE5_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE5_q(29) <= WERTE5_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE5_q(28) <= WERTE5_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE5_q(27) <= WERTE5_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE5_q(26) <= WERTE5_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE5_q(25) <= WERTE5_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE5_q(24) <= WERTE5_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE5_q(23) <= WERTE5_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE5_q(22) <= WERTE5_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE5_q(21) <= WERTE5_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE5_q(20) <= WERTE5_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE5_q(19) <= WERTE5_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE5_q(18) <= WERTE5_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE5_q(17) <= WERTE5_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE5_q(16) <= WERTE5_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE5_q(15) <= WERTE5_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE5_q(14) <= WERTE5_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(13)='1' THEN + WERTE5_q(13) <= WERTE5_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE5_q(12) <= WERTE5_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE5_q(11) <= WERTE5_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE5_q(10) <= WERTE5_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(9)='1' THEN + WERTE5_q(9) <= WERTE5_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(8)='1' THEN + WERTE5_q(8) <= WERTE5_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(7)='1' THEN + WERTE5_q(7) <= WERTE5_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(6)='1' THEN + WERTE5_q(6) <= WERTE5_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE5_q(5) <= WERTE5_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(4)='1' THEN + WERTE5_q(4) <= WERTE5_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE5_q(3) <= WERTE5_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(2)='1' THEN + WERTE5_q(2) <= WERTE5_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE5_q(1) <= WERTE5_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE5_0_clk_ctrl) BEGIN + IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN + IF WERTE5_ena(0)='1' THEN + WERTE5_q(0) <= WERTE5_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE4_q(63) <= WERTE4_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE4_q(62) <= WERTE4_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE4_q(61) <= WERTE4_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE4_q(60) <= WERTE4_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE4_q(59) <= WERTE4_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE4_q(58) <= WERTE4_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE4_q(57) <= WERTE4_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE4_q(56) <= WERTE4_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE4_q(55) <= WERTE4_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE4_q(54) <= WERTE4_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE4_q(53) <= WERTE4_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE4_q(52) <= WERTE4_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE4_q(51) <= WERTE4_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE4_q(50) <= WERTE4_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE4_q(49) <= WERTE4_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE4_q(48) <= WERTE4_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE4_q(47) <= WERTE4_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE4_q(46) <= WERTE4_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE4_q(45) <= WERTE4_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE4_q(44) <= WERTE4_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE4_q(43) <= WERTE4_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE4_q(42) <= WERTE4_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE4_q(41) <= WERTE4_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE4_q(40) <= WERTE4_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE4_q(39) <= WERTE4_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE4_q(38) <= WERTE4_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE4_q(37) <= WERTE4_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE4_q(36) <= WERTE4_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE4_q(35) <= WERTE4_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE4_q(34) <= WERTE4_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE4_q(33) <= WERTE4_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE4_q(32) <= WERTE4_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE4_q(31) <= WERTE4_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE4_q(30) <= WERTE4_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE4_q(29) <= WERTE4_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE4_q(28) <= WERTE4_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE4_q(27) <= WERTE4_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE4_q(26) <= WERTE4_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE4_q(25) <= WERTE4_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE4_q(24) <= WERTE4_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE4_q(23) <= WERTE4_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE4_q(22) <= WERTE4_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE4_q(21) <= WERTE4_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE4_q(20) <= WERTE4_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE4_q(19) <= WERTE4_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE4_q(18) <= WERTE4_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE4_q(17) <= WERTE4_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE4_q(16) <= WERTE4_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE4_q(15) <= WERTE4_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE4_q(14) <= WERTE4_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(13)='1' THEN + WERTE4_q(13) <= WERTE4_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE4_q(12) <= WERTE4_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE4_q(11) <= WERTE4_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE4_q(10) <= WERTE4_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(9)='1' THEN + WERTE4_q(9) <= WERTE4_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(8)='1' THEN + WERTE4_q(8) <= WERTE4_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(7)='1' THEN + WERTE4_q(7) <= WERTE4_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(6)='1' THEN + WERTE4_q(6) <= WERTE4_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE4_q(5) <= WERTE4_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(4)='1' THEN + WERTE4_q(4) <= WERTE4_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE4_q(3) <= WERTE4_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(2)='1' THEN + WERTE4_q(2) <= WERTE4_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE4_q(1) <= WERTE4_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE4_0_clk_ctrl) BEGIN + IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN + IF WERTE4_ena(0)='1' THEN + WERTE4_q(0) <= WERTE4_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE3_q(63) <= WERTE3_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE3_q(62) <= WERTE3_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE3_q(61) <= WERTE3_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE3_q(60) <= WERTE3_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE3_q(59) <= WERTE3_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE3_q(58) <= WERTE3_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE3_q(57) <= WERTE3_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE3_q(56) <= WERTE3_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE3_q(55) <= WERTE3_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE3_q(54) <= WERTE3_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE3_q(53) <= WERTE3_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE3_q(52) <= WERTE3_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE3_q(51) <= WERTE3_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE3_q(50) <= WERTE3_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE3_q(49) <= WERTE3_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE3_q(48) <= WERTE3_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE3_q(47) <= WERTE3_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE3_q(46) <= WERTE3_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE3_q(45) <= WERTE3_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE3_q(44) <= WERTE3_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE3_q(43) <= WERTE3_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE3_q(42) <= WERTE3_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE3_q(41) <= WERTE3_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE3_q(40) <= WERTE3_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE3_q(39) <= WERTE3_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE3_q(38) <= WERTE3_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE3_q(37) <= WERTE3_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE3_q(36) <= WERTE3_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE3_q(35) <= WERTE3_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE3_q(34) <= WERTE3_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE3_q(33) <= WERTE3_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE3_q(32) <= WERTE3_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE3_q(31) <= WERTE3_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE3_q(30) <= WERTE3_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE3_q(29) <= WERTE3_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE3_q(28) <= WERTE3_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE3_q(27) <= WERTE3_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE3_q(26) <= WERTE3_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE3_q(25) <= WERTE3_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE3_q(24) <= WERTE3_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE3_q(23) <= WERTE3_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE3_q(22) <= WERTE3_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE3_q(21) <= WERTE3_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE3_q(20) <= WERTE3_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE3_q(19) <= WERTE3_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE3_q(18) <= WERTE3_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE3_q(17) <= WERTE3_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE3_q(16) <= WERTE3_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE3_q(15) <= WERTE3_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE3_q(14) <= WERTE3_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(13)='1' THEN + WERTE3_q(13) <= WERTE3_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE3_q(12) <= WERTE3_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE3_q(11) <= WERTE3_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE3_q(10) <= WERTE3_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(9)='1' THEN + WERTE3_q(9) <= WERTE3_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(8)='1' THEN + WERTE3_q(8) <= WERTE3_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(7)='1' THEN + WERTE3_q(7) <= WERTE3_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(6)='1' THEN + WERTE3_q(6) <= WERTE3_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE3_q(5) <= WERTE3_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(4)='1' THEN + WERTE3_q(4) <= WERTE3_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE3_q(3) <= WERTE3_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(2)='1' THEN + WERTE3_q(2) <= WERTE3_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE3_q(1) <= WERTE3_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE3_0_clk_ctrl) BEGIN + IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN + IF WERTE3_ena(0)='1' THEN + WERTE3_q(0) <= WERTE3_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE2_q(63) <= WERTE2_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE2_q(62) <= WERTE2_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE2_q(61) <= WERTE2_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE2_q(60) <= WERTE2_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE2_q(59) <= WERTE2_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE2_q(58) <= WERTE2_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE2_q(57) <= WERTE2_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE2_q(56) <= WERTE2_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE2_q(55) <= WERTE2_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE2_q(54) <= WERTE2_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE2_q(53) <= WERTE2_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE2_q(52) <= WERTE2_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE2_q(51) <= WERTE2_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE2_q(50) <= WERTE2_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE2_q(49) <= WERTE2_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE2_q(48) <= WERTE2_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE2_q(47) <= WERTE2_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE2_q(46) <= WERTE2_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE2_q(45) <= WERTE2_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE2_q(44) <= WERTE2_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE2_q(43) <= WERTE2_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE2_q(42) <= WERTE2_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE2_q(41) <= WERTE2_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE2_q(40) <= WERTE2_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE2_q(39) <= WERTE2_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE2_q(38) <= WERTE2_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE2_q(37) <= WERTE2_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE2_q(36) <= WERTE2_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE2_q(35) <= WERTE2_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE2_q(34) <= WERTE2_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE2_q(33) <= WERTE2_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE2_q(32) <= WERTE2_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE2_q(31) <= WERTE2_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE2_q(30) <= WERTE2_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE2_q(29) <= WERTE2_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE2_q(28) <= WERTE2_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE2_q(27) <= WERTE2_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE2_q(26) <= WERTE2_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE2_q(25) <= WERTE2_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE2_q(24) <= WERTE2_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE2_q(23) <= WERTE2_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE2_q(22) <= WERTE2_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE2_q(21) <= WERTE2_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE2_q(20) <= WERTE2_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE2_q(19) <= WERTE2_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE2_q(18) <= WERTE2_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE2_q(17) <= WERTE2_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE2_q(16) <= WERTE2_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE2_q(15) <= WERTE2_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE2_q(14) <= WERTE2_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(13)='1' THEN + WERTE2_q(13) <= WERTE2_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE2_q(12) <= WERTE2_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE2_q(11) <= WERTE2_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE2_q(10) <= WERTE2_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(9)='1' THEN + WERTE2_q(9) <= WERTE2_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(8)='1' THEN + WERTE2_q(8) <= WERTE2_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(7)='1' THEN + WERTE2_q(7) <= WERTE2_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(6)='1' THEN + WERTE2_q(6) <= WERTE2_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE2_q(5) <= WERTE2_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(4)='1' THEN + WERTE2_q(4) <= WERTE2_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE2_q(3) <= WERTE2_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(2)='1' THEN + WERTE2_q(2) <= WERTE2_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE2_q(1) <= WERTE2_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE2_0_clk_ctrl) BEGIN + IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN + IF WERTE2_ena(0)='1' THEN + WERTE2_q(0) <= WERTE2_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE1_q(63) <= WERTE1_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE1_q(62) <= WERTE1_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE1_q(61) <= WERTE1_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE1_q(60) <= WERTE1_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE1_q(59) <= WERTE1_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE1_q(58) <= WERTE1_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE1_q(57) <= WERTE1_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE1_q(56) <= WERTE1_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE1_q(55) <= WERTE1_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE1_q(54) <= WERTE1_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE1_q(53) <= WERTE1_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE1_q(52) <= WERTE1_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE1_q(51) <= WERTE1_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE1_q(50) <= WERTE1_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE1_q(49) <= WERTE1_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE1_q(48) <= WERTE1_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE1_q(47) <= WERTE1_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE1_q(46) <= WERTE1_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE1_q(45) <= WERTE1_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE1_q(44) <= WERTE1_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE1_q(43) <= WERTE1_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE1_q(42) <= WERTE1_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE1_q(41) <= WERTE1_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE1_q(40) <= WERTE1_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE1_q(39) <= WERTE1_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE1_q(38) <= WERTE1_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE1_q(37) <= WERTE1_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE1_q(36) <= WERTE1_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE1_q(35) <= WERTE1_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE1_q(34) <= WERTE1_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE1_q(33) <= WERTE1_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE1_q(32) <= WERTE1_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE1_q(31) <= WERTE1_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE1_q(30) <= WERTE1_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE1_q(29) <= WERTE1_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE1_q(28) <= WERTE1_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE1_q(27) <= WERTE1_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE1_q(26) <= WERTE1_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE1_q(25) <= WERTE1_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE1_q(24) <= WERTE1_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE1_q(23) <= WERTE1_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE1_q(22) <= WERTE1_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE1_q(21) <= WERTE1_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE1_q(20) <= WERTE1_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE1_q(19) <= WERTE1_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE1_q(18) <= WERTE1_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE1_q(17) <= WERTE1_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE1_q(16) <= WERTE1_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE1_q(15) <= WERTE1_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE1_q(14) <= WERTE1_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(13)='1' THEN + WERTE1_q(13) <= WERTE1_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE1_q(12) <= WERTE1_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE1_q(11) <= WERTE1_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE1_q(10) <= WERTE1_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(9)='1' THEN + WERTE1_q(9) <= WERTE1_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(8)='1' THEN + WERTE1_q(8) <= WERTE1_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(7)='1' THEN + WERTE1_q(7) <= WERTE1_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(6)='1' THEN + WERTE1_q(6) <= WERTE1_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE1_q(5) <= WERTE1_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(4)='1' THEN + WERTE1_q(4) <= WERTE1_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE1_q(3) <= WERTE1_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(2)='1' THEN + WERTE1_q(2) <= WERTE1_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE1_q(1) <= WERTE1_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE1_0_clk_ctrl) BEGIN + IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN + IF WERTE1_ena(0)='1' THEN + WERTE1_q(0) <= WERTE1_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_63_ena_ctrl='1' THEN + WERTE0_q(63) <= WERTE0_d(63); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_62_ena_ctrl='1' THEN + WERTE0_q(62) <= WERTE0_d(62); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_61_ena_ctrl='1' THEN + WERTE0_q(61) <= WERTE0_d(61); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_60_ena_ctrl='1' THEN + WERTE0_q(60) <= WERTE0_d(60); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_59_ena_ctrl='1' THEN + WERTE0_q(59) <= WERTE0_d(59); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_58_ena_ctrl='1' THEN + WERTE0_q(58) <= WERTE0_d(58); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_57_ena_ctrl='1' THEN + WERTE0_q(57) <= WERTE0_d(57); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_56_ena_ctrl='1' THEN + WERTE0_q(56) <= WERTE0_d(56); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_55_ena_ctrl='1' THEN + WERTE0_q(55) <= WERTE0_d(55); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_54_ena_ctrl='1' THEN + WERTE0_q(54) <= WERTE0_d(54); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_53_ena_ctrl='1' THEN + WERTE0_q(53) <= WERTE0_d(53); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_52_ena_ctrl='1' THEN + WERTE0_q(52) <= WERTE0_d(52); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_51_ena_ctrl='1' THEN + WERTE0_q(51) <= WERTE0_d(51); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_50_ena_ctrl='1' THEN + WERTE0_q(50) <= WERTE0_d(50); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_49_ena_ctrl='1' THEN + WERTE0_q(49) <= WERTE0_d(49); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_48_ena_ctrl='1' THEN + WERTE0_q(48) <= WERTE0_d(48); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_47_ena_ctrl='1' THEN + WERTE0_q(47) <= WERTE0_d(47); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_46_ena_ctrl='1' THEN + WERTE0_q(46) <= WERTE0_d(46); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_45_ena_ctrl='1' THEN + WERTE0_q(45) <= WERTE0_d(45); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_44_ena_ctrl='1' THEN + WERTE0_q(44) <= WERTE0_d(44); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_43_ena_ctrl='1' THEN + WERTE0_q(43) <= WERTE0_d(43); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_42_ena_ctrl='1' THEN + WERTE0_q(42) <= WERTE0_d(42); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_41_ena_ctrl='1' THEN + WERTE0_q(41) <= WERTE0_d(41); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_40_ena_ctrl='1' THEN + WERTE0_q(40) <= WERTE0_d(40); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_39_ena_ctrl='1' THEN + WERTE0_q(39) <= WERTE0_d(39); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_38_ena_ctrl='1' THEN + WERTE0_q(38) <= WERTE0_d(38); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_37_ena_ctrl='1' THEN + WERTE0_q(37) <= WERTE0_d(37); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_36_ena_ctrl='1' THEN + WERTE0_q(36) <= WERTE0_d(36); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_35_ena_ctrl='1' THEN + WERTE0_q(35) <= WERTE0_d(35); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_34_ena_ctrl='1' THEN + WERTE0_q(34) <= WERTE0_d(34); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_33_ena_ctrl='1' THEN + WERTE0_q(33) <= WERTE0_d(33); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_32_ena_ctrl='1' THEN + WERTE0_q(32) <= WERTE0_d(32); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_31_ena_ctrl='1' THEN + WERTE0_q(31) <= WERTE0_d(31); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_30_ena_ctrl='1' THEN + WERTE0_q(30) <= WERTE0_d(30); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_29_ena_ctrl='1' THEN + WERTE0_q(29) <= WERTE0_d(29); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_28_ena_ctrl='1' THEN + WERTE0_q(28) <= WERTE0_d(28); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_27_ena_ctrl='1' THEN + WERTE0_q(27) <= WERTE0_d(27); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_26_ena_ctrl='1' THEN + WERTE0_q(26) <= WERTE0_d(26); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_25_ena_ctrl='1' THEN + WERTE0_q(25) <= WERTE0_d(25); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_24_ena_ctrl='1' THEN + WERTE0_q(24) <= WERTE0_d(24); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_23_ena_ctrl='1' THEN + WERTE0_q(23) <= WERTE0_d(23); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_22_ena_ctrl='1' THEN + WERTE0_q(22) <= WERTE0_d(22); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_21_ena_ctrl='1' THEN + WERTE0_q(21) <= WERTE0_d(21); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_20_ena_ctrl='1' THEN + WERTE0_q(20) <= WERTE0_d(20); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_19_ena_ctrl='1' THEN + WERTE0_q(19) <= WERTE0_d(19); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_18_ena_ctrl='1' THEN + WERTE0_q(18) <= WERTE0_d(18); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_17_ena_ctrl='1' THEN + WERTE0_q(17) <= WERTE0_d(17); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_16_ena_ctrl='1' THEN + WERTE0_q(16) <= WERTE0_d(16); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_15_ena_ctrl='1' THEN + WERTE0_q(15) <= WERTE0_d(15); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_14_ena_ctrl='1' THEN + WERTE0_q(14) <= WERTE0_d(14); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(13)='1' THEN + WERTE0_q(13) <= WERTE0_d(13); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_12_ena_ctrl='1' THEN + WERTE0_q(12) <= WERTE0_d(12); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_11_ena_ctrl='1' THEN + WERTE0_q(11) <= WERTE0_d(11); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_10_ena_ctrl='1' THEN + WERTE0_q(10) <= WERTE0_d(10); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(9)='1' THEN + WERTE0_q(9) <= WERTE0_d(9); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(8)='1' THEN + WERTE0_q(8) <= WERTE0_d(8); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(7)='1' THEN + WERTE0_q(7) <= WERTE0_d(7); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(6)='1' THEN + WERTE0_q(6) <= WERTE0_d(6); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_5_ena_ctrl='1' THEN + WERTE0_q(5) <= WERTE0_d(5); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(4)='1' THEN + WERTE0_q(4) <= WERTE0_d(4); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_3_ena_ctrl='1' THEN + WERTE0_q(3) <= WERTE0_d(3); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(2)='1' THEN + WERTE0_q(2) <= WERTE0_d(2); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_1_ena_ctrl='1' THEN + WERTE0_q(1) <= WERTE0_d(1); + END IF; + END IF; + END PROCESS; + + PROCESS (WERTE0_0_clk_ctrl) BEGIN + IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN + IF WERTE0_ena(0)='1' THEN + WERTE0_q(0) <= WERTE0_d(0); + END IF; + END IF; + END PROCESS; + + PROCESS (PIC_INT_SYNC0_clk_ctrl) BEGIN + IF PIC_INT_SYNC0_clk_ctrl'event and PIC_INT_SYNC0_clk_ctrl='1' THEN + PIC_INT_SYNC_q <= PIC_INT_SYNC_d; + END IF; + END PROCESS; + +-- Start of original equations + +-- BYT SELECT +-- HWORD +-- HHBYT +-- LONG UND LINE + FB_B(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or ((not + FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and (not FB_ADR(0))) or + ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + +-- HWORD +-- HLBYT +-- LONG UND LINE + FB_B(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or ((not + FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and FB_ADR(0)) or ((not + FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + +-- LWORD +-- LHBYT +-- LONG UND LINE + FB_B(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or ((not FB_SIZE1) + and FB_SIZE0 and FB_ADR(1) and (not FB_ADR(0))) or ((not FB_SIZE1) and + (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + +-- LWORD +-- LLBYT +-- LONG UND LINE + FB_B(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or ((not FB_SIZE1) + and FB_SIZE0 and FB_ADR(1) and FB_ADR(0)) or ((not FB_SIZE1) and (not + FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + INT_CTR0_clk_ctrl <= MAIN_CLK; + +-- $10000/4 + INT_CTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + "00000000000100000000000000"); + INT_CTR_d <= FB_AD; + INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); + INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); + INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR); + INT_CTR0_ena_ctrl <= INT_CTR_CS and FB_B(3) and (not nFB_WR); + +-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + INT_ENA0_clk_ctrl <= MAIN_CLK; + INT_ENA0_clrn_ctrl <= nRSTO; + +-- $10004/4 + INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + "00000000000100000000000001"); + INT_ENA_d <= FB_AD; + INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); + INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); + INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR); + INT_ENA0_ena_ctrl <= INT_ENA_CS and FB_B(3) and (not nFB_WR); + +-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + INT_CLEAR0_clk_ctrl <= MAIN_CLK; + +-- $10008/4 + INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + "00000000000100000000000010"); + INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) + and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); + INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) + and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); + INT_CLEAR_d(15 DOWNTO 8) <= FB_AD(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8) + and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); + INT_CLEAR_d(7 DOWNTO 0) <= FB_AD(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and + sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); + +-- INTERRUPT LATCH REGISTER READ ONLY +-- $1000C/4 + INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + "00000000000100000000000011"); + +-- INTERRUPT + nIRQ(2) <= not (HSYNC and INT_ENA_q(26)); + nIRQ(3) <= not (INT_CTR_q(0) and INT_ENA_q(27)); + nIRQ(4) <= not (VSYNC and INT_ENA_q(28)); + nIRQ(5) <= not (to_std_logic(INT_LATCH_q /= + "00000000000000000000000000000000") and INT_ENA_q(29)); + nIRQ(6) <= not ((not nMFP_INT) and INT_ENA_q(30)); + nIRQ(7) <= not (PSEUDO_BUS_ERROR and INT_ENA_q(31)); + +-- SCC +-- VME +-- # FB_ADR[19..4]==H"F920" -- PADDLE +-- # FB_ADR[19..4]==H"F921" -- PADDLE +-- # FB_ADR[19..4]==H"F922" -- PADDLE +-- MFP2 +-- MFP2 +-- MFP2 +-- MFP2 +-- TT SCSI +-- ST UHR +-- ST UHR +-- # FB_ADR[19..4]==H"F890" -- DMA SOUND +-- # FB_ADR[19..4]==H"F891" -- DMA SOUND +-- # FB_ADR[19..4]==H"F892" -- DMA SOUND + PSEUDO_BUS_ERROR <= (not nFB_CS1) and (to_std_logic(FB_ADR(19 DOWNTO 4) = + "1111100011001000" or FB_ADR(19 DOWNTO 4) = "1111100011100000" or + FB_ADR(19 DOWNTO 4) = "1111111110101000" or FB_ADR(19 DOWNTO 4) = + "1111111110101001" or FB_ADR(19 DOWNTO 4) = "1111111110101010" or + FB_ADR(19 DOWNTO 4) = "1111111110101000" or FB_ADR(19 DOWNTO 8) = + "111110000111" or FB_ADR(19 DOWNTO 4) = "1111111111000010" or + FB_ADR(19 DOWNTO 4) = "1111111111000011")); + +-- IF VIDEO ADR CHANGE +-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 + TIN0 <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = + "1111100000100000000") and (not nFB_WR); + +-- INTERRUPT LATCH + INT_L0_clk_ctrl <= MAIN_CLK; + INT_L0_clrn_ctrl <= nRSTO; + INT_L_d(0) <= PIC_INT and INT_ENA_q(0); + INT_L_d(1) <= E0_INT and INT_ENA_q(1); + INT_L_d(2) <= DVI_INT and INT_ENA_q(2); + INT_L_d(3) <= (not nPCI_INTA) and INT_ENA_q(3); + INT_L_d(4) <= (not nPCI_INTB) and INT_ENA_q(4); + INT_L_d(5) <= (not nPCI_INTC) and INT_ENA_q(5); + INT_L_d(6) <= (not nPCI_INTD) and INT_ENA_q(6); + INT_L_d(7) <= DSP_INT and INT_ENA_q(7); + INT_L_d(8) <= VSYNC and INT_ENA_q(8); + INT_L_d(9) <= HSYNC and INT_ENA_q(9); + INT_LA9_0_clk_ctrl <= MAIN_CLK; + INT_LA8_0_clk_ctrl <= MAIN_CLK; + INT_LA7_0_clk_ctrl <= MAIN_CLK; + INT_LA6_0_clk_ctrl <= MAIN_CLK; + INT_LA5_0_clk_ctrl <= MAIN_CLK; + INT_LA4_0_clk_ctrl <= MAIN_CLK; + INT_LA3_0_clk_ctrl <= MAIN_CLK; + INT_LA2_0_clk_ctrl <= MAIN_CLK; + INT_LA1_0_clk_ctrl <= MAIN_CLK; + INT_LA0_0_clk_ctrl <= MAIN_CLK; + INT_LATCH_d <= "11111111111111111111111111111111"; + INT_LATCH_clrn <= (not INT_CLEAR_q) and sizeIt(nRSTO,32); + INT_LA0_0_clrn_ctrl <= INT_ENA_q(0) and nRSTO; + INT_LA0_d <= ((std_logic_vector'(unsigned(INT_LA0_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA0_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(0),4) and + sizeIt(to_std_logic((unsigned(INT_LA0_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(0),4) and + sizeIt(to_std_logic((unsigned(INT_LA0_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(0),4) and + sizeIt(to_std_logic((unsigned(INT_LA0_q) < unsigned'("1001"))),4)); + INT_LATCH0_clk_1 <= INT_LA0_q(3); + INT_LA1_0_clrn_ctrl <= INT_ENA_q(1) and nRSTO; + INT_LA1_d <= ((std_logic_vector'(unsigned(INT_LA1_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(1),4) and sizeIt(to_std_logic((unsigned(INT_LA1_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA1_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(1),4) and + sizeIt(to_std_logic((unsigned(INT_LA1_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(1),4) and + sizeIt(to_std_logic((unsigned(INT_LA1_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(1),4) and + sizeIt(to_std_logic((unsigned(INT_LA1_q) < unsigned'("1001"))),4)); + INT_LATCH1_clk_1 <= INT_LA1_q(3); + INT_LA2_0_clrn_ctrl <= INT_ENA_q(2) and nRSTO; + INT_LA2_d <= ((std_logic_vector'(unsigned(INT_LA2_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(2),4) and sizeIt(to_std_logic((unsigned(INT_LA2_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA2_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(2),4) and + sizeIt(to_std_logic((unsigned(INT_LA2_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(2),4) and + sizeIt(to_std_logic((unsigned(INT_LA2_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(2),4) and + sizeIt(to_std_logic((unsigned(INT_LA2_q) < unsigned'("1001"))),4)); + INT_LATCH2_clk_1 <= INT_LA2_q(3); + INT_LA3_0_clrn_ctrl <= INT_ENA_q(3) and nRSTO; + INT_LA3_d <= ((std_logic_vector'(unsigned(INT_LA3_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(3),4) and sizeIt(to_std_logic((unsigned(INT_LA3_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA3_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(3),4) and + sizeIt(to_std_logic((unsigned(INT_LA3_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(3),4) and + sizeIt(to_std_logic((unsigned(INT_LA3_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(3),4) and + sizeIt(to_std_logic((unsigned(INT_LA3_q) < unsigned'("1001"))),4)); + INT_LATCH3_clk_1 <= INT_LA3_q(3); + INT_LA4_0_clrn_ctrl <= INT_ENA_q(4) and nRSTO; + INT_LA4_d <= ((std_logic_vector'(unsigned(INT_LA4_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(4),4) and sizeIt(to_std_logic((unsigned(INT_LA4_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA4_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(4),4) and + sizeIt(to_std_logic((unsigned(INT_LA4_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(4),4) and + sizeIt(to_std_logic((unsigned(INT_LA4_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(4),4) and + sizeIt(to_std_logic((unsigned(INT_LA4_q) < unsigned'("1001"))),4)); + INT_LATCH4_clk_1 <= INT_LA4_q(3); + INT_LA5_0_clrn_ctrl <= INT_ENA_q(5) and nRSTO; + INT_LA5_d <= ((std_logic_vector'(unsigned(INT_LA5_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(5),4) and sizeIt(to_std_logic((unsigned(INT_LA5_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA5_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(5),4) and + sizeIt(to_std_logic((unsigned(INT_LA5_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(5),4) and + sizeIt(to_std_logic((unsigned(INT_LA5_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(5),4) and + sizeIt(to_std_logic((unsigned(INT_LA5_q) < unsigned'("1001"))),4)); + INT_LATCH5_clk_1 <= INT_LA5_q(3); + INT_LA6_0_clrn_ctrl <= INT_ENA_q(6) and nRSTO; + INT_LA6_d <= ((std_logic_vector'(unsigned(INT_LA6_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(6),4) and sizeIt(to_std_logic((unsigned(INT_LA6_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA6_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(6),4) and + sizeIt(to_std_logic((unsigned(INT_LA6_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(6),4) and + sizeIt(to_std_logic((unsigned(INT_LA6_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(6),4) and + sizeIt(to_std_logic((unsigned(INT_LA6_q) < unsigned'("1001"))),4)); + INT_LATCH6_clk_1 <= INT_LA6_q(3); + INT_LA7_0_clrn_ctrl <= INT_ENA_q(7) and nRSTO; + INT_LA7_d <= ((std_logic_vector'(unsigned(INT_LA7_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(7),4) and sizeIt(to_std_logic((unsigned(INT_LA7_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA7_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(7),4) and + sizeIt(to_std_logic((unsigned(INT_LA7_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(7),4) and + sizeIt(to_std_logic((unsigned(INT_LA7_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(7),4) and + sizeIt(to_std_logic((unsigned(INT_LA7_q) < unsigned'("1001"))),4)); + INT_LATCH7_clk_1 <= INT_LA7_q(3); + INT_LA8_0_clrn_ctrl <= INT_ENA_q(8) and nRSTO; + INT_LA8_d <= ((std_logic_vector'(unsigned(INT_LA8_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(8),4) and sizeIt(to_std_logic((unsigned(INT_LA8_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA8_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(8),4) and + sizeIt(to_std_logic((unsigned(INT_LA8_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(8),4) and + sizeIt(to_std_logic((unsigned(INT_LA8_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(8),4) and + sizeIt(to_std_logic((unsigned(INT_LA8_q) < unsigned'("1001"))),4)); + INT_LATCH8_clk_1 <= INT_LA8_q(3); + INT_LA9_0_clrn_ctrl <= INT_ENA_q(9) and nRSTO; + INT_LA9_d <= ((std_logic_vector'(unsigned(INT_LA9_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(9),4) and sizeIt(to_std_logic((unsigned(INT_LA9_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA9_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(9),4) and + sizeIt(to_std_logic((unsigned(INT_LA9_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(9),4) and + sizeIt(to_std_logic((unsigned(INT_LA9_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(9),4) and + sizeIt(to_std_logic((unsigned(INT_LA9_q) < unsigned'("1001"))),4)); + INT_LATCH9_clk_1 <= INT_LA9_q(3); + + -- INT_IN + INT_IN(0) <= PIC_INT; + INT_IN(1) <= E0_INT; + INT_IN(2) <= DVI_INT; + INT_IN(3) <= not nPCI_INTA; + INT_IN(4) <= not nPCI_INTB; + INT_IN(5) <= not nPCI_INTC; + INT_IN(6) <= not nPCI_INTD; + INT_IN(7) <= DSP_INT; + INT_IN(8) <= VSYNC; + INT_IN(9) <= HSYNC; + INT_IN(25 DOWNTO 10) <= "0000000000000000"; + INT_IN(26) <= HSYNC; + INT_IN(27) <= INT_CTR_q(0); + INT_IN(28) <= VSYNC; + INT_IN(29) <= to_std_logic(INT_LATCH_q /= "00000000000000000000000000000000"); + INT_IN(30) <= not nMFP_INT; + INT_IN(31) <= DMA_DRQ; + + -- *************************************************************************************** + -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + ACP_CONF0_clk_ctrl <= MAIN_CLK; + + -- $4'0000/4 + ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000010000000000000000"); + ACP_CONF_d <= FB_AD; + ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR); + ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR); + ACP_CONF8_ena_ctrl <= ACP_CONF_CS and FB_B(2) and (not nFB_WR); + ACP_CONF0_ena_ctrl <= ACP_CONF_CS and FB_B(3) and (not nFB_WR); + + -- *************************************************************************************** + -- ------------------------------------------------------------ + -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR + -- -------------------------------------------------------- + RTC_ADR0_clk_ctrl <= MAIN_CLK; + RTC_ADR_d <= FB_AD(21 DOWNTO 16); + + -- FFFF8961 + UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110000") and FB_B(1); + + -- FFFF8963 + UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110001") and FB_B(3); + RTC_ADR0_ena_ctrl <= UHR_AS and (not nFB_WR); + WERTE7_0_clk_ctrl <= MAIN_CLK; + WERTE6_0_clk_ctrl <= MAIN_CLK; + WERTE5_0_clk_ctrl <= MAIN_CLK; + WERTE4_0_clk_ctrl <= MAIN_CLK; + WERTE3_0_clk_ctrl <= MAIN_CLK; + WERTE2_0_clk_ctrl <= MAIN_CLK; + WERTE1_0_clk_ctrl <= MAIN_CLK; + WERTE0_0_clk_ctrl <= MAIN_CLK; + + (WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1, WERTE3_0_d_1, + WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_d(1), WERTE6_d(1), WERTE5_d(1), WERTE4_d(1), WERTE3_d(1), + WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1, WERTE3_2_d_1, + WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_d(3), WERTE6_d(3), WERTE5_d(3), WERTE4_d(3), WERTE3_d(3), + WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1, WERTE3_4_d_1, + WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_d(5), WERTE6_d(5), WERTE5_d(5), WERTE4_d(5), WERTE3_d(5), + WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1, WERTE3_6_d_1, + WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1, WERTE3_7_d_1, + WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1, WERTE3_8_d_1, + WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1, WERTE3_9_d_1, + WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= FB_AD(23 DOWNTO 16) and + sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_d(10), WERTE6_d(10), WERTE5_d(10), WERTE4_d(10), WERTE3_d(10), + WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(11), WERTE6_d(11), WERTE5_d(11), WERTE4_d(11), WERTE3_d(11), + WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(12), WERTE6_d(12), WERTE5_d(12), WERTE4_d(12), WERTE3_d(12), + WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_13_d_1, WERTE6_d(13), WERTE5_d(13), WERTE4_d(13), WERTE3_d(13), + WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(14), WERTE6_d(14), WERTE5_d(14), WERTE4_d(14), WERTE3_d(14), + WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(15), WERTE6_d(15), WERTE5_d(15), WERTE4_d(15), WERTE3_d(15), + WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(16), WERTE6_d(16), WERTE5_d(16), WERTE4_d(16), WERTE3_d(16), + WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(17), WERTE6_d(17), WERTE5_d(17), WERTE4_d(17), WERTE3_d(17), + WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(18), WERTE6_d(18), WERTE5_d(18), WERTE4_d(18), WERTE3_d(18), + WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(19), WERTE6_d(19), WERTE5_d(19), WERTE4_d(19), WERTE3_d(19), + WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(20), WERTE6_d(20), WERTE5_d(20), WERTE4_d(20), WERTE3_d(20), + WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(21), WERTE6_d(21), WERTE5_d(21), WERTE4_d(21), WERTE3_d(21), + WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(22), WERTE6_d(22), WERTE5_d(22), WERTE4_d(22), WERTE3_d(22), + WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(23), WERTE6_d(23), WERTE5_d(23), WERTE4_d(23), WERTE3_d(23), + WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(24), WERTE6_d(24), WERTE5_d(24), WERTE4_d(24), WERTE3_d(24), + WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(25), WERTE6_d(25), WERTE5_d(25), WERTE4_d(25), WERTE3_d(25), + WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(26), WERTE6_d(26), WERTE5_d(26), WERTE4_d(26), WERTE3_d(26), + WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(27), WERTE6_d(27), WERTE5_d(27), WERTE4_d(27), WERTE3_d(27), + WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(28), WERTE6_d(28), WERTE5_d(28), WERTE4_d(28), WERTE3_d(28), + WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(29), WERTE6_d(29), WERTE5_d(29), WERTE4_d(29), WERTE3_d(29), + WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(30), WERTE6_d(30), WERTE5_d(30), WERTE4_d(30), WERTE3_d(30), + WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(31), WERTE6_d(31), WERTE5_d(31), WERTE4_d(31), WERTE3_d(31), + WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(32), WERTE6_d(32), WERTE5_d(32), WERTE4_d(32), WERTE3_d(32), + WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(33), WERTE6_d(33), WERTE5_d(33), WERTE4_d(33), WERTE3_d(33), + WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(34), WERTE6_d(34), WERTE5_d(34), WERTE4_d(34), WERTE3_d(34), + WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(35), WERTE6_d(35), WERTE5_d(35), WERTE4_d(35), WERTE3_d(35), + WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(36), WERTE6_d(36), WERTE5_d(36), WERTE4_d(36), WERTE3_d(36), + WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(37), WERTE6_d(37), WERTE5_d(37), WERTE4_d(37), WERTE3_d(37), + WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(38), WERTE6_d(38), WERTE5_d(38), WERTE4_d(38), WERTE3_d(38), + WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(39), WERTE6_d(39), WERTE5_d(39), WERTE4_d(39), WERTE3_d(39), + WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(40), WERTE6_d(40), WERTE5_d(40), WERTE4_d(40), WERTE3_d(40), + WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(41), WERTE6_d(41), WERTE5_d(41), WERTE4_d(41), WERTE3_d(41), + WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(42), WERTE6_d(42), WERTE5_d(42), WERTE4_d(42), WERTE3_d(42), + WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(43), WERTE6_d(43), WERTE5_d(43), WERTE4_d(43), WERTE3_d(43), + WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(44), WERTE6_d(44), WERTE5_d(44), WERTE4_d(44), WERTE3_d(44), + WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(45), WERTE6_d(45), WERTE5_d(45), WERTE4_d(45), WERTE3_d(45), + WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(46), WERTE6_d(46), WERTE5_d(46), WERTE4_d(46), WERTE3_d(46), + WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(47), WERTE6_d(47), WERTE5_d(47), WERTE4_d(47), WERTE3_d(47), + WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(48), WERTE6_d(48), WERTE5_d(48), WERTE4_d(48), WERTE3_d(48), + WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(49), WERTE6_d(49), WERTE5_d(49), WERTE4_d(49), WERTE3_d(49), + WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(50), WERTE6_d(50), WERTE5_d(50), WERTE4_d(50), WERTE3_d(50), + WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(51), WERTE6_d(51), WERTE5_d(51), WERTE4_d(51), WERTE3_d(51), + WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(52), WERTE6_d(52), WERTE5_d(52), WERTE4_d(52), WERTE3_d(52), + WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(53), WERTE6_d(53), WERTE5_d(53), WERTE4_d(53), WERTE3_d(53), + WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(54), WERTE6_d(54), WERTE5_d(54), WERTE4_d(54), WERTE3_d(54), + WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(55), WERTE6_d(55), WERTE5_d(55), WERTE4_d(55), WERTE3_d(55), + WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(56), WERTE6_d(56), WERTE5_d(56), WERTE4_d(56), WERTE3_d(56), + WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(57), WERTE6_d(57), WERTE5_d(57), WERTE4_d(57), WERTE3_d(57), + WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(58), WERTE6_d(58), WERTE5_d(58), WERTE4_d(58), WERTE3_d(58), + WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(59), WERTE6_d(59), WERTE5_d(59), WERTE4_d(59), WERTE3_d(59), + WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(60), WERTE6_d(60), WERTE5_d(60), WERTE4_d(60), WERTE3_d(60), + WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(61), WERTE6_d(61), WERTE5_d(61), WERTE4_d(61), WERTE3_d(61), + WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(62), WERTE6_d(62), WERTE5_d(62), WERTE4_d(62), WERTE3_d(62), + WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_d(63), WERTE6_d(63), WERTE5_d(63), WERTE4_d(63), WERTE3_d(63), + WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= FB_AD(23 DOWNTO 16); + + (WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1, + WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + WERTE0_1_ena_ctrl <= to_std_logic(RTC_ADR_q = "000001") and UHR_DS and (not + nFB_WR); + + (WERTE7_2_ena_1, WERTE6_2_ena_1, WERTE5_2_ena_1, WERTE4_2_ena_1, + WERTE3_2_ena_1, WERTE2_2_ena_1, WERTE1_2_ena_1, WERTE0_2_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + WERTE0_3_ena_ctrl <= to_std_logic(RTC_ADR_q = "000011") and UHR_DS and (not + nFB_WR); + + (WERTE7_4_ena_1, WERTE6_4_ena_1, WERTE5_4_ena_1, WERTE4_4_ena_1, + WERTE3_4_ena_1, WERTE2_4_ena_1, WERTE1_4_ena_1, WERTE0_4_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + WERTE0_5_ena_ctrl <= to_std_logic(RTC_ADR_q = "000101") and UHR_DS and (not + nFB_WR); + + (WERTE7_6_ena_1, WERTE6_6_ena_1, WERTE5_6_ena_1, WERTE4_6_ena_1, + WERTE3_6_ena_1, WERTE2_6_ena_1, WERTE1_6_ena_1, WERTE0_6_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_7_ena_1, WERTE6_7_ena_1, WERTE5_7_ena_1, WERTE4_7_ena_1, + WERTE3_7_ena_1, WERTE2_7_ena_1, WERTE1_7_ena_1, WERTE0_7_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_8_ena_1, WERTE6_8_ena_1, WERTE5_8_ena_1, WERTE4_8_ena_1, + WERTE3_8_ena_1, WERTE2_8_ena_1, WERTE1_8_ena_1, WERTE0_8_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + (WERTE7_9_ena_1, WERTE6_9_ena_1, WERTE5_9_ena_1, WERTE4_9_ena_1, + WERTE3_9_ena_1, WERTE2_9_ena_1, WERTE1_9_ena_1, WERTE0_9_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + WERTE0_10_ena_ctrl <= to_std_logic(RTC_ADR_q = "001010") and UHR_DS and (not + nFB_WR); + + WERTE0_11_ena_ctrl <= to_std_logic(RTC_ADR_q = "001011") and UHR_DS and (not + nFB_WR); + + WERTE0_12_ena_ctrl <= to_std_logic(RTC_ADR_q = "001100") and UHR_DS and (not + nFB_WR); + + (WERTE7_ena(13), WERTE6_ena(13), WERTE5_ena(13), WERTE4_ena(13), + WERTE3_ena(13), WERTE2_ena(13), WERTE1_ena(13), WERTE0_13_ena_1) <= + sizeIt(to_std_logic(RTC_ADR_q = "001101"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8); + + WERTE0_14_ena_ctrl <= to_std_logic(RTC_ADR_q = "001110") and UHR_DS and (not + nFB_WR); + + WERTE0_15_ena_ctrl <= to_std_logic(RTC_ADR_q = "001111") and UHR_DS and (not + nFB_WR); + + WERTE0_16_ena_ctrl <= to_std_logic(RTC_ADR_q = "010000") and UHR_DS and (not + nFB_WR); + + WERTE0_17_ena_ctrl <= to_std_logic(RTC_ADR_q = "010001") and UHR_DS and (not + nFB_WR); + + WERTE0_18_ena_ctrl <= to_std_logic(RTC_ADR_q = "010010") and UHR_DS and (not + nFB_WR); + + WERTE0_19_ena_ctrl <= to_std_logic(RTC_ADR_q = "010011") and UHR_DS and (not + nFB_WR); + + WERTE0_20_ena_ctrl <= to_std_logic(RTC_ADR_q = "010100") and UHR_DS and (not + nFB_WR); + + WERTE0_21_ena_ctrl <= to_std_logic(RTC_ADR_q = "010101") and UHR_DS and (not + nFB_WR); + WERTE0_22_ena_ctrl <= to_std_logic(RTC_ADR_q = "010110") and UHR_DS and (not + nFB_WR); + WERTE0_23_ena_ctrl <= to_std_logic(RTC_ADR_q = "010111") and UHR_DS and (not + nFB_WR); + WERTE0_24_ena_ctrl <= to_std_logic(RTC_ADR_q = "011000") and UHR_DS and (not + nFB_WR); + WERTE0_25_ena_ctrl <= to_std_logic(RTC_ADR_q = "011001") and UHR_DS and (not + nFB_WR); + WERTE0_26_ena_ctrl <= to_std_logic(RTC_ADR_q = "011010") and UHR_DS and (not + nFB_WR); + WERTE0_27_ena_ctrl <= to_std_logic(RTC_ADR_q = "011011") and UHR_DS and (not + nFB_WR); + WERTE0_28_ena_ctrl <= to_std_logic(RTC_ADR_q = "011100") and UHR_DS and (not + nFB_WR); + WERTE0_29_ena_ctrl <= to_std_logic(RTC_ADR_q = "011101") and UHR_DS and (not + nFB_WR); + WERTE0_30_ena_ctrl <= to_std_logic(RTC_ADR_q = "011110") and UHR_DS and (not + nFB_WR); + WERTE0_31_ena_ctrl <= to_std_logic(RTC_ADR_q = "011111") and UHR_DS and (not + nFB_WR); + WERTE0_32_ena_ctrl <= to_std_logic(RTC_ADR_q = "100000") and UHR_DS and (not + nFB_WR); + WERTE0_33_ena_ctrl <= to_std_logic(RTC_ADR_q = "100001") and UHR_DS and (not + nFB_WR); + WERTE0_34_ena_ctrl <= to_std_logic(RTC_ADR_q = "100010") and UHR_DS and (not + nFB_WR); + WERTE0_35_ena_ctrl <= to_std_logic(RTC_ADR_q = "100011") and UHR_DS and (not + nFB_WR); + WERTE0_36_ena_ctrl <= to_std_logic(RTC_ADR_q = "100100") and UHR_DS and (not + nFB_WR); + WERTE0_37_ena_ctrl <= to_std_logic(RTC_ADR_q = "100101") and UHR_DS and (not + nFB_WR); + WERTE0_38_ena_ctrl <= to_std_logic(RTC_ADR_q = "100110") and UHR_DS and (not + nFB_WR); + WERTE0_39_ena_ctrl <= to_std_logic(RTC_ADR_q = "100111") and UHR_DS and (not + nFB_WR); + WERTE0_40_ena_ctrl <= to_std_logic(RTC_ADR_q = "101000") and UHR_DS and (not + nFB_WR); + WERTE0_41_ena_ctrl <= to_std_logic(RTC_ADR_q = "101001") and UHR_DS and (not + nFB_WR); + WERTE0_42_ena_ctrl <= to_std_logic(RTC_ADR_q = "101010") and UHR_DS and (not + nFB_WR); + WERTE0_43_ena_ctrl <= to_std_logic(RTC_ADR_q = "101011") and UHR_DS and (not + nFB_WR); + WERTE0_44_ena_ctrl <= to_std_logic(RTC_ADR_q = "101100") and UHR_DS and (not + nFB_WR); + WERTE0_45_ena_ctrl <= to_std_logic(RTC_ADR_q = "101101") and UHR_DS and (not + nFB_WR); + WERTE0_46_ena_ctrl <= to_std_logic(RTC_ADR_q = "101110") and UHR_DS and (not + nFB_WR); + WERTE0_47_ena_ctrl <= to_std_logic(RTC_ADR_q = "101111") and UHR_DS and (not + nFB_WR); + WERTE0_48_ena_ctrl <= to_std_logic(RTC_ADR_q = "110000") and UHR_DS and (not + nFB_WR); + WERTE0_49_ena_ctrl <= to_std_logic(RTC_ADR_q = "110001") and UHR_DS and (not + nFB_WR); + WERTE0_50_ena_ctrl <= to_std_logic(RTC_ADR_q = "110010") and UHR_DS and (not + nFB_WR); + WERTE0_51_ena_ctrl <= to_std_logic(RTC_ADR_q = "110011") and UHR_DS and (not + nFB_WR); + WERTE0_52_ena_ctrl <= to_std_logic(RTC_ADR_q = "110100") and UHR_DS and (not + nFB_WR); + WERTE0_53_ena_ctrl <= to_std_logic(RTC_ADR_q = "110101") and UHR_DS and (not + nFB_WR); + WERTE0_54_ena_ctrl <= to_std_logic(RTC_ADR_q = "110110") and UHR_DS and (not + nFB_WR); + WERTE0_55_ena_ctrl <= to_std_logic(RTC_ADR_q = "110111") and UHR_DS and (not + nFB_WR); + WERTE0_56_ena_ctrl <= to_std_logic(RTC_ADR_q = "111000") and UHR_DS and (not + nFB_WR); + WERTE0_57_ena_ctrl <= to_std_logic(RTC_ADR_q = "111001") and UHR_DS and (not + nFB_WR); + WERTE0_58_ena_ctrl <= to_std_logic(RTC_ADR_q = "111010") and UHR_DS and (not + nFB_WR); + WERTE0_59_ena_ctrl <= to_std_logic(RTC_ADR_q = "111011") and UHR_DS and (not + nFB_WR); + WERTE0_60_ena_ctrl <= to_std_logic(RTC_ADR_q = "111100") and UHR_DS and (not + nFB_WR); + WERTE0_61_ena_ctrl <= to_std_logic(RTC_ADR_q = "111101") and UHR_DS and (not + nFB_WR); + WERTE0_62_ena_ctrl <= to_std_logic(RTC_ADR_q = "111110") and UHR_DS and (not + nFB_WR); + WERTE0_63_ena_ctrl <= to_std_logic(RTC_ADR_q = "111111") and UHR_DS and (not + nFB_WR); + + PIC_INT_SYNC0_clk_ctrl <= MAIN_CLK; + PIC_INT_SYNC_d(0) <= PIC_INT; + PIC_INT_SYNC_d(1) <= PIC_INT_SYNC_q(0); + PIC_INT_SYNC_d(2) <= (not PIC_INT_SYNC_q(1)) and PIC_INT_SYNC_q(0); + UPDATE_ON_1 <= not WERTE7_q(11); + + -- KEIN UIP + WERTE6_clrn(10) <= gnd; + + + -- UPDATE ON OFF + UPDATE_ON_2 <= not WERTE7_q(11); + + -- IMMER BINARY + WERTE2_11_d_2 <= vcc; + + -- IMMER 24H FORMAT + WERTE1_11_d_2 <= vcc; + + -- IMMER SOMMERZEITKORREKTUR + WERTE0_11_d_2 <= vcc; + + -- IMMER RICHTIG + WERTE7_13_d_2 <= vcc; + + -- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) + -- LETZTER SONNTAG IM APRIL + SOMMERZEIT <= to_std_logic(std_logic_vector'(WERTE7_q(6) & WERTE6_q(6) & + WERTE5_q(6) & WERTE4_q(6) & WERTE3_q(6) & WERTE2_q(6) & WERTE1_q(6) & + WERTE0_q(6)) = "00000001" and std_logic_vector'(WERTE7_q(4) & + WERTE6_q(4) & WERTE5_q(4) & WERTE4_q(4) & WERTE3_q(4) & WERTE2_q(4) & + WERTE1_q(4) & WERTE0_q(4)) = "00000001" and + std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & WERTE5_q(8) & + WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & WERTE0_q(8)) = + "00000100" and (unsigned(std_logic_vector'(WERTE7_q(7) & WERTE6_q(7) & + WERTE5_q(7) & WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & WERTE1_q(7) & + WERTE0_q(7))) > unsigned'("00010111"))); + WERTE0_13_d_2 <= SOMMERZEIT; + WERTE0_13_ena_2 <= INC_STD and (SOMMERZEIT or WINTERZEIT); + +-- LETZTER SONNTAG IM OKTOBER + WINTERZEIT <= to_std_logic(std_logic_vector'(WERTE7_q(6) & WERTE6_q(6) & + WERTE5_q(6) & WERTE4_q(6) & WERTE3_q(6) & WERTE2_q(6) & WERTE1_q(6) & + WERTE0_q(6)) = "00000001" and std_logic_vector'(WERTE7_q(4) & + WERTE6_q(4) & WERTE5_q(4) & WERTE4_q(4) & WERTE3_q(4) & WERTE2_q(4) & + WERTE1_q(4) & WERTE0_q(4)) = "00000001" and + std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & WERTE5_q(8) & + WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & WERTE0_q(8)) = + "00001010" and (unsigned(std_logic_vector'(WERTE7_q(7) & WERTE6_q(7) & + WERTE5_q(7) & WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & WERTE1_q(7) & + WERTE0_q(7))) > unsigned'("00011000"))) and WERTE0_q(13); + +-- ACHTELSEKUNDEN + ACHTELSEKUNDEN0_clk_ctrl <= MAIN_CLK; + ACHTELSEKUNDEN_d <= std_logic_vector'(unsigned(ACHTELSEKUNDEN_q) + + unsigned'("001")); + ACHTELSEKUNDEN0_ena_ctrl <= PIC_INT_SYNC_q(2) and UPDATE_ON; + +-- SEKUNDEN + INC_SEC <= to_std_logic(ACHTELSEKUNDEN_q = "111") and PIC_INT_SYNC_q(2) and + UPDATE_ON; + +-- SEKUNDEN Z�HLEN BIS 59 + (WERTE7_0_d_2, WERTE6_0_d_2, WERTE5_0_d_2, WERTE4_0_d_2, WERTE3_0_d_2, + WERTE2_0_d_2, WERTE1_0_d_2, WERTE0_0_d_2) <= + (std_logic_vector'(unsigned(std_logic_vector'(WERTE7_q(0) & + WERTE6_q(0) & WERTE5_q(0) & WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & + WERTE1_q(0) & WERTE0_q(0))) + unsigned'("00000001"))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(0) & WERTE6_q(0) & + WERTE5_q(0) & WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & WERTE1_q(0) & + WERTE0_q(0)) /= "00111011"),8) and (not (sizeIt(to_std_logic(RTC_ADR_q + = "000000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + (WERTE7_0_ena_2, WERTE6_0_ena_2, WERTE5_0_ena_2, WERTE4_0_ena_2, + WERTE3_0_ena_2, WERTE2_0_ena_2, WERTE1_0_ena_2, WERTE0_0_ena_2) <= + sizeIt(INC_SEC,8) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "000000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- MINUTEN + INC_MIN <= to_std_logic(INC_SEC='1' and std_logic_vector'(WERTE7_q(0) & + WERTE6_q(0) & WERTE5_q(0) & WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & + WERTE1_q(0) & WERTE0_q(0)) = "00111011"); + +-- MINUTEN Z�HLEN BIS 59 + (WERTE7_2_d_2, WERTE6_2_d_2, WERTE5_2_d_2, WERTE4_2_d_2, WERTE3_2_d_2, + WERTE2_2_d_2, WERTE1_2_d_2, WERTE0_2_d_2) <= + (std_logic_vector'(unsigned(std_logic_vector'(WERTE7_q(2) & + WERTE6_q(2) & WERTE5_q(2) & WERTE4_q(2) & WERTE3_q(2) & WERTE2_q(2) & + WERTE1_q(2) & WERTE0_q(2))) + unsigned'("00000001"))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(2) & WERTE6_q(2) & + WERTE5_q(2) & WERTE4_q(2) & WERTE3_q(2) & WERTE2_q(2) & WERTE1_q(2) & + WERTE0_q(2)) /= "00111011"),8) and (not (sizeIt(to_std_logic(RTC_ADR_q + = "000010"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + (WERTE7_2_ena_2, WERTE6_2_ena_2, WERTE5_2_ena_2, WERTE4_2_ena_2, + WERTE3_2_ena_2, WERTE2_2_ena_2, WERTE1_2_ena_2, WERTE0_2_ena_2) <= + sizeIt(INC_MIN,8) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "000010"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- STUNDEN + INC_STD <= to_std_logic(INC_MIN='1' and std_logic_vector'(WERTE7_q(2) & + WERTE6_q(2) & WERTE5_q(2) & WERTE4_q(2) & WERTE3_q(2) & WERTE2_q(2) & + WERTE1_q(2) & WERTE0_q(2)) = "00111011"); + +-- STUNDEN Z�HLEN BIS 23 + (WERTE7_4_d_2, WERTE6_4_d_2, WERTE5_4_d_2, WERTE4_4_d_2, WERTE3_4_d_2, + WERTE2_4_d_2, WERTE1_4_d_2, WERTE0_4_d_2) <= + (std_logic_vector'((unsigned(std_logic_vector'(WERTE7_q(4) & + WERTE6_q(4) & WERTE5_q(4) & WERTE4_q(4) & WERTE3_q(4) & WERTE2_q(4) & + WERTE1_q(4) & WERTE0_q(4))) + unsigned'("00000001")) + + unsigned("00000001" and sizeIt(SOMMERZEIT,8)))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(4) & WERTE6_q(4) & + WERTE5_q(4) & WERTE4_q(4) & WERTE3_q(4) & WERTE2_q(4) & WERTE1_q(4) & + WERTE0_q(4)) /= "00010111"),8) and (not (sizeIt(to_std_logic(RTC_ADR_q + = "000100"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT + (WERTE7_4_ena_2, WERTE6_4_ena_2, WERTE5_4_ena_2, WERTE4_4_ena_2, + WERTE3_4_ena_2, WERTE2_4_ena_2, WERTE1_4_ena_2, WERTE0_4_ena_2) <= + sizeIt(INC_STD,8) and (not (sizeIt(WINTERZEIT,8) and + sizeIt(WERTE0_q(12),8))) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "000100"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- WOCHENTAG UND TAG + INC_TAG <= to_std_logic(INC_STD='1' and std_logic_vector'(WERTE7_q(2) & + WERTE6_q(2) & WERTE5_q(2) & WERTE4_q(2) & WERTE3_q(2) & WERTE2_q(2) & + WERTE1_q(2) & WERTE0_q(2)) = "00010111"); + +-- WOCHENTAG Z�HLEN BIS 7 +-- DANN BEI 1 WEITER + (WERTE7_6_d_2, WERTE6_6_d_2, WERTE5_6_d_2, WERTE4_6_d_2, WERTE3_6_d_2, + WERTE2_6_d_2, WERTE1_6_d_2, WERTE0_6_d_2) <= + ((std_logic_vector'(unsigned(std_logic_vector'(WERTE7_q(6) & + WERTE6_q(6) & WERTE5_q(6) & WERTE4_q(6) & WERTE3_q(6) & WERTE2_q(6) & + WERTE1_q(6) & WERTE0_q(6))) + unsigned'("00000001"))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(6) & WERTE6_q(6) & + WERTE5_q(6) & WERTE4_q(6) & WERTE3_q(6) & WERTE2_q(6) & WERTE1_q(6) & + WERTE0_q(6)) /= "00000111"),8) and (not (sizeIt(to_std_logic(RTC_ADR_q + = "000110"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8)))) or + ("00000001" and sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(6) & + WERTE6_q(6) & WERTE5_q(6) & WERTE4_q(6) & WERTE3_q(6) & WERTE2_q(6) & + WERTE1_q(6) & WERTE0_q(6)) = "00000111"),8) and (not + (sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8)))); + (WERTE7_6_ena_2, WERTE6_6_ena_2, WERTE5_6_ena_2, WERTE4_6_ena_2, + WERTE3_6_ena_2, WERTE2_6_ena_2, WERTE1_6_ena_2, WERTE0_6_ena_2) <= + sizeIt(INC_TAG,8) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "000110"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + ANZAHL_TAGE_DES_MONATS <= ("00011111" and + (sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000001"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000011"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000101"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000111"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00001000"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00001010"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00001100"),8))) or ("00011110" and + (sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000100"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000110"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00001001"),8) or + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00001011"),8))) or ("00011101" and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000010"),8) and + sizeIt(to_std_logic(std_logic_vector'(WERTE1_q(9) & WERTE0_q(9)) = + "00"),8)) or ("00011100" and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) = "00000010"),8) and + sizeIt(to_std_logic(std_logic_vector'(WERTE1_q(9) & WERTE0_q(9)) /= + "00"),8)); + +-- TAG Z�HLEN BIS MONATSENDE +-- DANN BEI 1 WEITER + (WERTE7_7_d_2, WERTE6_7_d_2, WERTE5_7_d_2, WERTE4_7_d_2, WERTE3_7_d_2, + WERTE2_7_d_2, WERTE1_7_d_2, WERTE0_7_d_2) <= + ((std_logic_vector'(unsigned(std_logic_vector'(WERTE7_q(7) & + WERTE6_q(7) & WERTE5_q(7) & WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & + WERTE1_q(7) & WERTE0_q(7))) + unsigned'("00000001"))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(7) & WERTE6_q(7) & + WERTE5_q(7) & WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & WERTE1_q(7) & + WERTE0_q(7)) /= ANZAHL_TAGE_DES_MONATS),8) and (not + (sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8)))) or ("00000001" and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(7) & WERTE6_q(7) & + WERTE5_q(7) & WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & WERTE1_q(7) & + WERTE0_q(7)) = ANZAHL_TAGE_DES_MONATS),8) and (not + (sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8)))); + (WERTE7_7_ena_2, WERTE6_7_ena_2, WERTE5_7_ena_2, WERTE4_7_ena_2, + WERTE3_7_ena_2, WERTE2_7_ena_2, WERTE1_7_ena_2, WERTE0_7_ena_2) <= + sizeIt(INC_TAG,8) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "000111"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- MONATE + INC_MONAT <= to_std_logic(INC_TAG='1' and std_logic_vector'(WERTE7_q(7) & + WERTE6_q(7) & WERTE5_q(7) & WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & + WERTE1_q(7) & WERTE0_q(7)) = ANZAHL_TAGE_DES_MONATS); + +-- MONATE Z�HLEN BIS 12 +-- DANN BEI 1 WEITER + (WERTE7_8_d_2, WERTE6_8_d_2, WERTE5_8_d_2, WERTE4_8_d_2, WERTE3_8_d_2, + WERTE2_8_d_2, WERTE1_8_d_2, WERTE0_8_d_2) <= + ((std_logic_vector'(unsigned(std_logic_vector'(WERTE7_q(8) & + WERTE6_q(8) & WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & + WERTE1_q(8) & WERTE0_q(8))) + unsigned'("00000001"))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & + WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & + WERTE0_q(8)) /= "00001100"),8) and (not (sizeIt(to_std_logic(RTC_ADR_q + = "001000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8)))) or + ("00000001" and sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(8) & + WERTE6_q(8) & WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & + WERTE1_q(8) & WERTE0_q(8)) = "00001100"),8) and (not + (sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and + sizeIt(not nFB_WR,8)))); + (WERTE7_8_ena_2, WERTE6_8_ena_2, WERTE5_8_ena_2, WERTE4_8_ena_2, + WERTE3_8_ena_2, WERTE2_8_ena_2, WERTE1_8_ena_2, WERTE0_8_ena_2) <= + sizeIt(INC_MONAT,8) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "001000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- JAHR + INC_JAHR <= to_std_logic(INC_MONAT='1' and std_logic_vector'(WERTE7_q(8) & + WERTE6_q(8) & WERTE5_q(8) & WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & + WERTE1_q(8) & WERTE0_q(8)) = "00001100"); + +-- JAHRE Z�HLEN BIS 99 + (WERTE7_9_d_2, WERTE6_9_d_2, WERTE5_9_d_2, WERTE4_9_d_2, WERTE3_9_d_2, + WERTE2_9_d_2, WERTE1_9_d_2, WERTE0_9_d_2) <= + (std_logic_vector'(unsigned(std_logic_vector'(WERTE7_q(9) & + WERTE6_q(9) & WERTE5_q(9) & WERTE4_q(9) & WERTE3_q(9) & WERTE2_q(9) & + WERTE1_q(9) & WERTE0_q(9))) + unsigned'("00000001"))) and + sizeIt(to_std_logic(std_logic_vector'(WERTE7_q(9) & WERTE6_q(9) & + WERTE5_q(9) & WERTE4_q(9) & WERTE3_q(9) & WERTE2_q(9) & WERTE1_q(9) & + WERTE0_q(9)) /= "01100011"),8) and (not (sizeIt(to_std_logic(RTC_ADR_q + = "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + (WERTE7_9_ena_2, WERTE6_9_ena_2, WERTE5_9_ena_2, WERTE4_9_ena_2, + WERTE3_9_ena_2, WERTE2_9_ena_2, WERTE1_9_ena_2, WERTE0_9_ena_2) <= + sizeIt(INC_JAHR,8) and (not (sizeIt(to_std_logic(RTC_ADR_q = + "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); + +-- TRISTATE OUTPUT + u0_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(31 DOWNTO 24)) or + (sizeIt(INT_ENA_CS,8) and INT_ENA_q(31 DOWNTO 24)) or + (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(31 DOWNTO 24)) or + (sizeIt(INT_CLEAR_CS,8) and INT_IN(31 DOWNTO 24)) or + (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(31 DOWNTO 24)); + u0_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or + ACP_CONF_CS) and (not nFB_OE); + FB_AD(31 DOWNTO 24) <= u0_tridata; + u1_data <= (std_logic_vector'(WERTE7_q(0) & WERTE6_q(0) & WERTE5_q(0) & + WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & WERTE1_q(0) & WERTE0_q(0)) + and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(1) & WERTE6_q(1) & WERTE5_q(1) & + WERTE4_q(1) & WERTE3_q(1) & WERTE2_q(1) & WERTE1_q(1) & WERTE0_q(1)) + and sizeIt(to_std_logic(RTC_ADR_q = "000001"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(2) & WERTE6_q(2) & WERTE5_q(2) & + WERTE4_q(2) & WERTE3_q(2) & WERTE2_q(2) & WERTE1_q(2) & WERTE0_q(2)) + and sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(3) & WERTE6_q(3) & WERTE5_q(3) & + WERTE4_q(3) & WERTE3_q(3) & WERTE2_q(3) & WERTE1_q(3) & WERTE0_q(3)) + and sizeIt(to_std_logic(RTC_ADR_q = "000011"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(4) & WERTE6_q(4) & WERTE5_q(4) & + WERTE4_q(4) & WERTE3_q(4) & WERTE2_q(4) & WERTE1_q(4) & WERTE0_q(4)) + and sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(5) & WERTE6_q(5) & WERTE5_q(5) & + WERTE4_q(5) & WERTE3_q(5) & WERTE2_q(5) & WERTE1_q(5) & WERTE0_q(5)) + and sizeIt(to_std_logic(RTC_ADR_q = "000101"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(6) & WERTE6_q(6) & WERTE5_q(6) & + WERTE4_q(6) & WERTE3_q(6) & WERTE2_q(6) & WERTE1_q(6) & WERTE0_q(6)) + and sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(7) & WERTE6_q(7) & WERTE5_q(7) & + WERTE4_q(7) & WERTE3_q(7) & WERTE2_q(7) & WERTE1_q(7) & WERTE0_q(7)) + and sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(8) & WERTE6_q(8) & WERTE5_q(8) & + WERTE4_q(8) & WERTE3_q(8) & WERTE2_q(8) & WERTE1_q(8) & WERTE0_q(8)) + and sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(9) & WERTE6_q(9) & WERTE5_q(9) & + WERTE4_q(9) & WERTE3_q(9) & WERTE2_q(9) & WERTE1_q(9) & WERTE0_q(9)) + and sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8)) + or (std_logic_vector'(WERTE7_q(10) & WERTE6_q(10) & WERTE5_q(10) & + WERTE4_q(10) & WERTE3_q(10) & WERTE2_q(10) & WERTE1_q(10) & + WERTE0_q(10)) and sizeIt(to_std_logic(RTC_ADR_q = "001010"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(11) & WERTE6_q(11) & + WERTE5_q(11) & WERTE4_q(11) & WERTE3_q(11) & WERTE2_q(11) & + WERTE1_q(11) & WERTE0_q(11)) and sizeIt(to_std_logic(RTC_ADR_q = + "001011"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(12) + & WERTE6_q(12) & WERTE5_q(12) & WERTE4_q(12) & WERTE3_q(12) & + WERTE2_q(12) & WERTE1_q(12) & WERTE0_q(12)) and + sizeIt(to_std_logic(RTC_ADR_q = "001100"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(13) & WERTE6_q(13) & WERTE5_q(13) & + WERTE4_q(13) & WERTE3_q(13) & WERTE2_q(13) & WERTE1_q(13) & + WERTE0_q(13)) and sizeIt(to_std_logic(RTC_ADR_q = "001101"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(14) & WERTE6_q(14) & + WERTE5_q(14) & WERTE4_q(14) & WERTE3_q(14) & WERTE2_q(14) & + WERTE1_q(14) & WERTE0_q(14)) and sizeIt(to_std_logic(RTC_ADR_q = + "001110"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(15) + & WERTE6_q(15) & WERTE5_q(15) & WERTE4_q(15) & WERTE3_q(15) & + WERTE2_q(15) & WERTE1_q(15) & WERTE0_q(15)) and + sizeIt(to_std_logic(RTC_ADR_q = "001111"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(16) & WERTE6_q(16) & WERTE5_q(16) & + WERTE4_q(16) & WERTE3_q(16) & WERTE2_q(16) & WERTE1_q(16) & + WERTE0_q(16)) and sizeIt(to_std_logic(RTC_ADR_q = "010000"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(17) & WERTE6_q(17) & + WERTE5_q(17) & WERTE4_q(17) & WERTE3_q(17) & WERTE2_q(17) & + WERTE1_q(17) & WERTE0_q(17)) and sizeIt(to_std_logic(RTC_ADR_q = + "010001"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(18) + & WERTE6_q(18) & WERTE5_q(18) & WERTE4_q(18) & WERTE3_q(18) & + WERTE2_q(18) & WERTE1_q(18) & WERTE0_q(18)) and + sizeIt(to_std_logic(RTC_ADR_q = "010010"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(19) & WERTE6_q(19) & WERTE5_q(19) & + WERTE4_q(19) & WERTE3_q(19) & WERTE2_q(19) & WERTE1_q(19) & + WERTE0_q(19)) and sizeIt(to_std_logic(RTC_ADR_q = "010011"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(20) & WERTE6_q(20) & + WERTE5_q(20) & WERTE4_q(20) & WERTE3_q(20) & WERTE2_q(20) & + WERTE1_q(20) & WERTE0_q(20)) and sizeIt(to_std_logic(RTC_ADR_q = + "010100"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(21) + & WERTE6_q(21) & WERTE5_q(21) & WERTE4_q(21) & WERTE3_q(21) & + WERTE2_q(21) & WERTE1_q(21) & WERTE0_q(21)) and + sizeIt(to_std_logic(RTC_ADR_q = "010101"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(22) & WERTE6_q(22) & WERTE5_q(22) & + WERTE4_q(22) & WERTE3_q(22) & WERTE2_q(22) & WERTE1_q(22) & + WERTE0_q(22)) and sizeIt(to_std_logic(RTC_ADR_q = "010110"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(23) & WERTE6_q(23) & + WERTE5_q(23) & WERTE4_q(23) & WERTE3_q(23) & WERTE2_q(23) & + WERTE1_q(23) & WERTE0_q(23)) and sizeIt(to_std_logic(RTC_ADR_q = + "010111"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(24) + & WERTE6_q(24) & WERTE5_q(24) & WERTE4_q(24) & WERTE3_q(24) & + WERTE2_q(24) & WERTE1_q(24) & WERTE0_q(24)) and + sizeIt(to_std_logic(RTC_ADR_q = "011000"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(25) & WERTE6_q(25) & WERTE5_q(25) & + WERTE4_q(25) & WERTE3_q(25) & WERTE2_q(25) & WERTE1_q(25) & + WERTE0_q(25)) and sizeIt(to_std_logic(RTC_ADR_q = "011001"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(26) & WERTE6_q(26) & + WERTE5_q(26) & WERTE4_q(26) & WERTE3_q(26) & WERTE2_q(26) & + WERTE1_q(26) & WERTE0_q(26)) and sizeIt(to_std_logic(RTC_ADR_q = + "011010"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(27) + & WERTE6_q(27) & WERTE5_q(27) & WERTE4_q(27) & WERTE3_q(27) & + WERTE2_q(27) & WERTE1_q(27) & WERTE0_q(27)) and + sizeIt(to_std_logic(RTC_ADR_q = "011011"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(28) & WERTE6_q(28) & WERTE5_q(28) & + WERTE4_q(28) & WERTE3_q(28) & WERTE2_q(28) & WERTE1_q(28) & + WERTE0_q(28)) and sizeIt(to_std_logic(RTC_ADR_q = "011100"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(29) & WERTE6_q(29) & + WERTE5_q(29) & WERTE4_q(29) & WERTE3_q(29) & WERTE2_q(29) & + WERTE1_q(29) & WERTE0_q(29)) and sizeIt(to_std_logic(RTC_ADR_q = + "011101"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(30) + & WERTE6_q(30) & WERTE5_q(30) & WERTE4_q(30) & WERTE3_q(30) & + WERTE2_q(30) & WERTE1_q(30) & WERTE0_q(30)) and + sizeIt(to_std_logic(RTC_ADR_q = "011110"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(31) & WERTE6_q(31) & WERTE5_q(31) & + WERTE4_q(31) & WERTE3_q(31) & WERTE2_q(31) & WERTE1_q(31) & + WERTE0_q(31)) and sizeIt(to_std_logic(RTC_ADR_q = "011111"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(32) & WERTE6_q(32) & + WERTE5_q(32) & WERTE4_q(32) & WERTE3_q(32) & WERTE2_q(32) & + WERTE1_q(32) & WERTE0_q(32)) and sizeIt(to_std_logic(RTC_ADR_q = + "100000"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(33) + & WERTE6_q(33) & WERTE5_q(33) & WERTE4_q(33) & WERTE3_q(33) & + WERTE2_q(33) & WERTE1_q(33) & WERTE0_q(33)) and + sizeIt(to_std_logic(RTC_ADR_q = "100001"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(34) & WERTE6_q(34) & WERTE5_q(34) & + WERTE4_q(34) & WERTE3_q(34) & WERTE2_q(34) & WERTE1_q(34) & + WERTE0_q(34)) and sizeIt(to_std_logic(RTC_ADR_q = "100010"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(35) & WERTE6_q(35) & + WERTE5_q(35) & WERTE4_q(35) & WERTE3_q(35) & WERTE2_q(35) & + WERTE1_q(35) & WERTE0_q(35)) and sizeIt(to_std_logic(RTC_ADR_q = + "100011"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(36) + & WERTE6_q(36) & WERTE5_q(36) & WERTE4_q(36) & WERTE3_q(36) & + WERTE2_q(36) & WERTE1_q(36) & WERTE0_q(36)) and + sizeIt(to_std_logic(RTC_ADR_q = "100100"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(37) & WERTE6_q(37) & WERTE5_q(37) & + WERTE4_q(37) & WERTE3_q(37) & WERTE2_q(37) & WERTE1_q(37) & + WERTE0_q(37)) and sizeIt(to_std_logic(RTC_ADR_q = "100101"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(38) & WERTE6_q(38) & + WERTE5_q(38) & WERTE4_q(38) & WERTE3_q(38) & WERTE2_q(38) & + WERTE1_q(38) & WERTE0_q(38)) and sizeIt(to_std_logic(RTC_ADR_q = + "100110"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(39) + & WERTE6_q(39) & WERTE5_q(39) & WERTE4_q(39) & WERTE3_q(39) & + WERTE2_q(39) & WERTE1_q(39) & WERTE0_q(39)) and + sizeIt(to_std_logic(RTC_ADR_q = "100111"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(40) & WERTE6_q(40) & WERTE5_q(40) & + WERTE4_q(40) & WERTE3_q(40) & WERTE2_q(40) & WERTE1_q(40) & + WERTE0_q(40)) and sizeIt(to_std_logic(RTC_ADR_q = "101000"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(41) & WERTE6_q(41) & + WERTE5_q(41) & WERTE4_q(41) & WERTE3_q(41) & WERTE2_q(41) & + WERTE1_q(41) & WERTE0_q(41)) and sizeIt(to_std_logic(RTC_ADR_q = + "101001"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(42) + & WERTE6_q(42) & WERTE5_q(42) & WERTE4_q(42) & WERTE3_q(42) & + WERTE2_q(42) & WERTE1_q(42) & WERTE0_q(42)) and + sizeIt(to_std_logic(RTC_ADR_q = "101010"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(43) & WERTE6_q(43) & WERTE5_q(43) & + WERTE4_q(43) & WERTE3_q(43) & WERTE2_q(43) & WERTE1_q(43) & + WERTE0_q(43)) and sizeIt(to_std_logic(RTC_ADR_q = "101011"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(44) & WERTE6_q(44) & + WERTE5_q(44) & WERTE4_q(44) & WERTE3_q(44) & WERTE2_q(44) & + WERTE1_q(44) & WERTE0_q(44)) and sizeIt(to_std_logic(RTC_ADR_q = + "101100"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(45) + & WERTE6_q(45) & WERTE5_q(45) & WERTE4_q(45) & WERTE3_q(45) & + WERTE2_q(45) & WERTE1_q(45) & WERTE0_q(45)) and + sizeIt(to_std_logic(RTC_ADR_q = "101101"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(46) & WERTE6_q(46) & WERTE5_q(46) & + WERTE4_q(46) & WERTE3_q(46) & WERTE2_q(46) & WERTE1_q(46) & + WERTE0_q(46)) and sizeIt(to_std_logic(RTC_ADR_q = "101110"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(47) & WERTE6_q(47) & + WERTE5_q(47) & WERTE4_q(47) & WERTE3_q(47) & WERTE2_q(47) & + WERTE1_q(47) & WERTE0_q(47)) and sizeIt(to_std_logic(RTC_ADR_q = + "101111"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(48) + & WERTE6_q(48) & WERTE5_q(48) & WERTE4_q(48) & WERTE3_q(48) & + WERTE2_q(48) & WERTE1_q(48) & WERTE0_q(48)) and + sizeIt(to_std_logic(RTC_ADR_q = "110000"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(49) & WERTE6_q(49) & WERTE5_q(49) & + WERTE4_q(49) & WERTE3_q(49) & WERTE2_q(49) & WERTE1_q(49) & + WERTE0_q(49)) and sizeIt(to_std_logic(RTC_ADR_q = "110001"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(50) & WERTE6_q(50) & + WERTE5_q(50) & WERTE4_q(50) & WERTE3_q(50) & WERTE2_q(50) & + WERTE1_q(50) & WERTE0_q(50)) and sizeIt(to_std_logic(RTC_ADR_q = + "110010"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(51) + & WERTE6_q(51) & WERTE5_q(51) & WERTE4_q(51) & WERTE3_q(51) & + WERTE2_q(51) & WERTE1_q(51) & WERTE0_q(51)) and + sizeIt(to_std_logic(RTC_ADR_q = "110011"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(52) & WERTE6_q(52) & WERTE5_q(52) & + WERTE4_q(52) & WERTE3_q(52) & WERTE2_q(52) & WERTE1_q(52) & + WERTE0_q(52)) and sizeIt(to_std_logic(RTC_ADR_q = "110100"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(53) & WERTE6_q(53) & + WERTE5_q(53) & WERTE4_q(53) & WERTE3_q(53) & WERTE2_q(53) & + WERTE1_q(53) & WERTE0_q(53)) and sizeIt(to_std_logic(RTC_ADR_q = + "110101"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(54) + & WERTE6_q(54) & WERTE5_q(54) & WERTE4_q(54) & WERTE3_q(54) & + WERTE2_q(54) & WERTE1_q(54) & WERTE0_q(54)) and + sizeIt(to_std_logic(RTC_ADR_q = "110110"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(55) & WERTE6_q(55) & WERTE5_q(55) & + WERTE4_q(55) & WERTE3_q(55) & WERTE2_q(55) & WERTE1_q(55) & + WERTE0_q(55)) and sizeIt(to_std_logic(RTC_ADR_q = "110111"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(56) & WERTE6_q(56) & + WERTE5_q(56) & WERTE4_q(56) & WERTE3_q(56) & WERTE2_q(56) & + WERTE1_q(56) & WERTE0_q(56)) and sizeIt(to_std_logic(RTC_ADR_q = + "111000"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(57) + & WERTE6_q(57) & WERTE5_q(57) & WERTE4_q(57) & WERTE3_q(57) & + WERTE2_q(57) & WERTE1_q(57) & WERTE0_q(57)) and + sizeIt(to_std_logic(RTC_ADR_q = "111001"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(58) & WERTE6_q(58) & WERTE5_q(58) & + WERTE4_q(58) & WERTE3_q(58) & WERTE2_q(58) & WERTE1_q(58) & + WERTE0_q(58)) and sizeIt(to_std_logic(RTC_ADR_q = "111010"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(59) & WERTE6_q(59) & + WERTE5_q(59) & WERTE4_q(59) & WERTE3_q(59) & WERTE2_q(59) & + WERTE1_q(59) & WERTE0_q(59)) and sizeIt(to_std_logic(RTC_ADR_q = + "111011"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(60) + & WERTE6_q(60) & WERTE5_q(60) & WERTE4_q(60) & WERTE3_q(60) & + WERTE2_q(60) & WERTE1_q(60) & WERTE0_q(60)) and + sizeIt(to_std_logic(RTC_ADR_q = "111100"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'(WERTE7_q(61) & WERTE6_q(61) & WERTE5_q(61) & + WERTE4_q(61) & WERTE3_q(61) & WERTE2_q(61) & WERTE1_q(61) & + WERTE0_q(61)) and sizeIt(to_std_logic(RTC_ADR_q = "111101"),8) and + sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(62) & WERTE6_q(62) & + WERTE5_q(62) & WERTE4_q(62) & WERTE3_q(62) & WERTE2_q(62) & + WERTE1_q(62) & WERTE0_q(62)) and sizeIt(to_std_logic(RTC_ADR_q = + "111110"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'(WERTE7_q(63) + & WERTE6_q(63) & WERTE5_q(63) & WERTE4_q(63) & WERTE3_q(63) & + WERTE2_q(63) & WERTE1_q(63) & WERTE0_q(63)) and + sizeIt(to_std_logic(RTC_ADR_q = "111111"),8) and sizeIt(UHR_DS,8)) or + (std_logic_vector'("00" & RTC_ADR_q) and sizeIt(UHR_AS,8)) or + (sizeIt(INT_CTR_CS,8) and INT_CTR_q(23 DOWNTO 16)) or + (sizeIt(INT_ENA_CS,8) and INT_ENA_q(23 DOWNTO 16)) or + (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(23 DOWNTO 16)) or + (sizeIt(INT_CLEAR_CS,8) and INT_IN(23 DOWNTO 16)) or + (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(23 DOWNTO 16)); + u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS + or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); + FB_AD(23 DOWNTO 16) <= u1_tridata; + u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 DOWNTO 8)) or + (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 DOWNTO 8)) or + (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 DOWNTO 8)) or + (sizeIt(INT_CLEAR_CS,8) and INT_IN(15 DOWNTO 8)) or + (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(15 DOWNTO 8)); + u2_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or + ACP_CONF_CS) and (not nFB_OE); + FB_AD(15 DOWNTO 8) <= u2_tridata; + u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 DOWNTO 0)) or + (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 DOWNTO 0)) or + (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 DOWNTO 0)) or + (sizeIt(INT_CLEAR_CS,8) and INT_IN(7 DOWNTO 0)) or + (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(7 DOWNTO 0)); + u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or + ACP_CONF_CS) and (not nFB_OE); + FB_AD(7 DOWNTO 0) <= u3_tridata; + INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS; + + +-- Assignments added to explicitly combine the +-- effects of multiple drivers in the source + UPDATE_ON <= UPDATE_ON_1 or UPDATE_ON_2; + WERTE0_ena(0) <= WERTE0_0_ena_1 or WERTE0_0_ena_2; + WERTE0_ena(2) <= WERTE0_2_ena_1 or WERTE0_2_ena_2; + WERTE0_ena(4) <= WERTE0_4_ena_1 or WERTE0_4_ena_2; + WERTE0_ena(6) <= WERTE0_6_ena_1 or WERTE0_6_ena_2; + WERTE0_ena(7) <= WERTE0_7_ena_1 or WERTE0_7_ena_2; + WERTE0_ena(8) <= WERTE0_8_ena_1 or WERTE0_8_ena_2; + WERTE0_ena(9) <= WERTE0_9_ena_1 or WERTE0_9_ena_2; + WERTE0_ena(13) <= WERTE0_13_ena_1 or WERTE0_13_ena_2; + WERTE0_d(0) <= WERTE0_0_d_1 or WERTE0_0_d_2; + WERTE0_d(2) <= WERTE0_2_d_1 or WERTE0_2_d_2; + WERTE0_d(4) <= WERTE0_4_d_1 or WERTE0_4_d_2; + WERTE0_d(6) <= WERTE0_6_d_1 or WERTE0_6_d_2; + WERTE0_d(7) <= WERTE0_7_d_1 or WERTE0_7_d_2; + WERTE0_d(8) <= WERTE0_8_d_1 or WERTE0_8_d_2; + WERTE0_d(9) <= WERTE0_9_d_1 or WERTE0_9_d_2; + WERTE0_d(11) <= WERTE0_11_d_1 or WERTE0_11_d_2; + WERTE0_d(13) <= WERTE0_13_d_1 or WERTE0_13_d_2; + WERTE1_ena(0) <= WERTE1_0_ena_1 or WERTE1_0_ena_2; + WERTE1_ena(2) <= WERTE1_2_ena_1 or WERTE1_2_ena_2; + WERTE1_ena(4) <= WERTE1_4_ena_1 or WERTE1_4_ena_2; + WERTE1_ena(6) <= WERTE1_6_ena_1 or WERTE1_6_ena_2; + WERTE1_ena(7) <= WERTE1_7_ena_1 or WERTE1_7_ena_2; + WERTE1_ena(8) <= WERTE1_8_ena_1 or WERTE1_8_ena_2; + WERTE1_ena(9) <= WERTE1_9_ena_1 or WERTE1_9_ena_2; + WERTE1_d(0) <= WERTE1_0_d_1 or WERTE1_0_d_2; + WERTE1_d(2) <= WERTE1_2_d_1 or WERTE1_2_d_2; + WERTE1_d(4) <= WERTE1_4_d_1 or WERTE1_4_d_2; + WERTE1_d(6) <= WERTE1_6_d_1 or WERTE1_6_d_2; + WERTE1_d(7) <= WERTE1_7_d_1 or WERTE1_7_d_2; + WERTE1_d(8) <= WERTE1_8_d_1 or WERTE1_8_d_2; + WERTE1_d(9) <= WERTE1_9_d_1 or WERTE1_9_d_2; + WERTE1_d(11) <= WERTE1_11_d_1 or WERTE1_11_d_2; + WERTE2_ena(0) <= WERTE2_0_ena_1 or WERTE2_0_ena_2; + WERTE2_ena(2) <= WERTE2_2_ena_1 or WERTE2_2_ena_2; + WERTE2_ena(4) <= WERTE2_4_ena_1 or WERTE2_4_ena_2; + WERTE2_ena(6) <= WERTE2_6_ena_1 or WERTE2_6_ena_2; + WERTE2_ena(7) <= WERTE2_7_ena_1 or WERTE2_7_ena_2; + WERTE2_ena(8) <= WERTE2_8_ena_1 or WERTE2_8_ena_2; + WERTE2_ena(9) <= WERTE2_9_ena_1 or WERTE2_9_ena_2; + WERTE2_d(0) <= WERTE2_0_d_1 or WERTE2_0_d_2; + WERTE2_d(2) <= WERTE2_2_d_1 or WERTE2_2_d_2; + WERTE2_d(4) <= WERTE2_4_d_1 or WERTE2_4_d_2; + WERTE2_d(6) <= WERTE2_6_d_1 or WERTE2_6_d_2; + WERTE2_d(7) <= WERTE2_7_d_1 or WERTE2_7_d_2; + WERTE2_d(8) <= WERTE2_8_d_1 or WERTE2_8_d_2; + WERTE2_d(9) <= WERTE2_9_d_1 or WERTE2_9_d_2; + WERTE2_d(11) <= WERTE2_11_d_1 or WERTE2_11_d_2; + WERTE3_ena(0) <= WERTE3_0_ena_1 or WERTE3_0_ena_2; + WERTE3_ena(2) <= WERTE3_2_ena_1 or WERTE3_2_ena_2; + WERTE3_ena(4) <= WERTE3_4_ena_1 or WERTE3_4_ena_2; + WERTE3_ena(6) <= WERTE3_6_ena_1 or WERTE3_6_ena_2; + WERTE3_ena(7) <= WERTE3_7_ena_1 or WERTE3_7_ena_2; + WERTE3_ena(8) <= WERTE3_8_ena_1 or WERTE3_8_ena_2; + WERTE3_ena(9) <= WERTE3_9_ena_1 or WERTE3_9_ena_2; + WERTE3_d(0) <= WERTE3_0_d_1 or WERTE3_0_d_2; + WERTE3_d(2) <= WERTE3_2_d_1 or WERTE3_2_d_2; + WERTE3_d(4) <= WERTE3_4_d_1 or WERTE3_4_d_2; + WERTE3_d(6) <= WERTE3_6_d_1 or WERTE3_6_d_2; + WERTE3_d(7) <= WERTE3_7_d_1 or WERTE3_7_d_2; + WERTE3_d(8) <= WERTE3_8_d_1 or WERTE3_8_d_2; + WERTE3_d(9) <= WERTE3_9_d_1 or WERTE3_9_d_2; + WERTE4_ena(0) <= WERTE4_0_ena_1 or WERTE4_0_ena_2; + WERTE4_ena(2) <= WERTE4_2_ena_1 or WERTE4_2_ena_2; + WERTE4_ena(4) <= WERTE4_4_ena_1 or WERTE4_4_ena_2; + WERTE4_ena(6) <= WERTE4_6_ena_1 or WERTE4_6_ena_2; + WERTE4_ena(7) <= WERTE4_7_ena_1 or WERTE4_7_ena_2; + WERTE4_ena(8) <= WERTE4_8_ena_1 or WERTE4_8_ena_2; + WERTE4_ena(9) <= WERTE4_9_ena_1 or WERTE4_9_ena_2; + WERTE4_d(0) <= WERTE4_0_d_1 or WERTE4_0_d_2; + WERTE4_d(2) <= WERTE4_2_d_1 or WERTE4_2_d_2; + WERTE4_d(4) <= WERTE4_4_d_1 or WERTE4_4_d_2; + WERTE4_d(6) <= WERTE4_6_d_1 or WERTE4_6_d_2; + WERTE4_d(7) <= WERTE4_7_d_1 or WERTE4_7_d_2; + WERTE4_d(8) <= WERTE4_8_d_1 or WERTE4_8_d_2; + WERTE4_d(9) <= WERTE4_9_d_1 or WERTE4_9_d_2; + WERTE5_ena(0) <= WERTE5_0_ena_1 or WERTE5_0_ena_2; + WERTE5_ena(2) <= WERTE5_2_ena_1 or WERTE5_2_ena_2; + WERTE5_ena(4) <= WERTE5_4_ena_1 or WERTE5_4_ena_2; + WERTE5_ena(6) <= WERTE5_6_ena_1 or WERTE5_6_ena_2; + WERTE5_ena(7) <= WERTE5_7_ena_1 or WERTE5_7_ena_2; + WERTE5_ena(8) <= WERTE5_8_ena_1 or WERTE5_8_ena_2; + WERTE5_ena(9) <= WERTE5_9_ena_1 or WERTE5_9_ena_2; + WERTE5_d(0) <= WERTE5_0_d_1 or WERTE5_0_d_2; + WERTE5_d(2) <= WERTE5_2_d_1 or WERTE5_2_d_2; + WERTE5_d(4) <= WERTE5_4_d_1 or WERTE5_4_d_2; + WERTE5_d(6) <= WERTE5_6_d_1 or WERTE5_6_d_2; + WERTE5_d(7) <= WERTE5_7_d_1 or WERTE5_7_d_2; + WERTE5_d(8) <= WERTE5_8_d_1 or WERTE5_8_d_2; + WERTE5_d(9) <= WERTE5_9_d_1 or WERTE5_9_d_2; + WERTE6_ena(0) <= WERTE6_0_ena_1 or WERTE6_0_ena_2; + WERTE6_ena(2) <= WERTE6_2_ena_1 or WERTE6_2_ena_2; + WERTE6_ena(4) <= WERTE6_4_ena_1 or WERTE6_4_ena_2; + WERTE6_ena(6) <= WERTE6_6_ena_1 or WERTE6_6_ena_2; + WERTE6_ena(7) <= WERTE6_7_ena_1 or WERTE6_7_ena_2; + WERTE6_ena(8) <= WERTE6_8_ena_1 or WERTE6_8_ena_2; + WERTE6_ena(9) <= WERTE6_9_ena_1 or WERTE6_9_ena_2; + WERTE6_d(0) <= WERTE6_0_d_1 or WERTE6_0_d_2; + WERTE6_d(2) <= WERTE6_2_d_1 or WERTE6_2_d_2; + WERTE6_d(4) <= WERTE6_4_d_1 or WERTE6_4_d_2; + WERTE6_d(6) <= WERTE6_6_d_1 or WERTE6_6_d_2; + WERTE6_d(7) <= WERTE6_7_d_1 or WERTE6_7_d_2; + WERTE6_d(8) <= WERTE6_8_d_1 or WERTE6_8_d_2; + WERTE6_d(9) <= WERTE6_9_d_1 or WERTE6_9_d_2; + WERTE7_ena(0) <= WERTE7_0_ena_1 or WERTE7_0_ena_2; + WERTE7_ena(2) <= WERTE7_2_ena_1 or WERTE7_2_ena_2; + WERTE7_ena(4) <= WERTE7_4_ena_1 or WERTE7_4_ena_2; + WERTE7_ena(6) <= WERTE7_6_ena_1 or WERTE7_6_ena_2; + WERTE7_ena(7) <= WERTE7_7_ena_1 or WERTE7_7_ena_2; + WERTE7_ena(8) <= WERTE7_8_ena_1 or WERTE7_8_ena_2; + WERTE7_ena(9) <= WERTE7_9_ena_1 or WERTE7_9_ena_2; + WERTE7_d(0) <= WERTE7_0_d_1 or WERTE7_0_d_2; + WERTE7_d(2) <= WERTE7_2_d_1 or WERTE7_2_d_2; + WERTE7_d(4) <= WERTE7_4_d_1 or WERTE7_4_d_2; + WERTE7_d(6) <= WERTE7_6_d_1 or WERTE7_6_d_2; + WERTE7_d(7) <= WERTE7_7_d_1 or WERTE7_7_d_2; + WERTE7_d(8) <= WERTE7_8_d_1 or WERTE7_8_d_2; + WERTE7_d(9) <= WERTE7_9_d_1 or WERTE7_9_d_2; + WERTE7_d(13) <= WERTE7_13_d_1 or WERTE7_13_d_2; + +-- Define power SIGNAL(s) + vcc <= '1'; + gnd <= '0'; +END ; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 3fbd54a..33fcbfb 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -82,6 +82,7 @@ COMPONENT mux41_0 D1 : IN STD_LOGIC; Q : OUT STD_LOGIC); END COMPONENT; + ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 41e0e96..9712f63 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,391 +39,391 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -433,7 +433,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -443,21 +443,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -467,76 +467,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -558,299 +558,298 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll_reconfig1.qip -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 026355d..f087d74 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -118,17 +118,21 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} - -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_pins {VA}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] #************************************************************** # Set Clock Groups diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 64d0c8a..58cdcf8 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -1,886 +1,629 @@ LIBRARY ieee; USE ieee.std_logic_1164.all; +LIBRARY altera; + USE altera.altera_primitives_components.all; + LIBRARY work; ENTITY firebee1 IS PORT ( - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - LP_BUSY : IN std_logic; - nACSI_DRQ : IN std_logic; - nACSI_INT : IN std_logic; - RxD : IN std_logic; - CTS : IN std_logic; - RI : IN std_logic; - DCD : IN std_logic; - AMKB_RX : IN std_logic; - PIC_AMKB_RX : IN std_logic; - IDE_RDY : IN std_logic; - IDE_INT : IN std_logic; - WP_CF_CARD : IN std_logic; - TRACK00 : IN std_logic; - nWP : IN std_logic; - nDCHG : IN std_logic; - SD_DATA0 : IN std_logic; - SD_DATA1 : IN std_logic; - SD_DATA2 : IN std_logic; - SD_CARD_DEDECT : IN std_logic; - nSCSI_DRQ : IN std_logic; - SD_WP : IN std_logic; - nRD_DATA : IN std_logic; - nSCSI_C_D : IN std_logic; - nSCSI_I_O : IN std_logic; - nSCSI_MSG : IN std_logic; - nDACK0 : IN std_logic; - PIC_INT : IN std_logic; - nFB_OE : IN std_logic; - TOUT0 : IN std_logic; - nMASTER : IN std_logic; - DVI_INT : IN std_logic; - nDACK1 : IN std_logic; - nPCI_INTD : IN std_logic; - nPCI_INTC : IN std_logic; - nPCI_INTB : IN std_logic; - nPCI_INTA : IN std_logic; - E0_INT : IN std_logic; - nINDEX : IN std_logic; - HD_DD : IN std_logic; - MAIN_CLK : IN std_logic; - nRSTO_MCF : IN std_logic; - CLK33MDIR : IN std_logic; - SCSI_PAR : INOUT std_logic; - nSCSI_RST : INOUT std_logic; - nSCSI_SEL : INOUT std_logic; - nSCSI_BUSY : INOUT std_logic; - SD_CD_DATA3 : INOUT std_logic; - SD_CMD_D1 : INOUT std_logic; - MIDI_IN_PIN : INOUT std_logic; - ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - IO : INOUT std_logic_vector(17 DOWNTO 0); - LP_D : INOUT std_logic_vector(7 DOWNTO 0); - SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); - SRD : INOUT std_logic_vector(15 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0); - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - LP_STR : OUT std_logic; - nACSI_ACK : OUT std_logic; - nACSI_RESET : OUT std_logic; - nACSI_CS : OUT std_logic; - ACSI_DIR : OUT std_logic; - ACSI_A1 : OUT std_logic; - nSCSI_ACK : OUT std_logic; - nSCSI_ATN : OUT std_logic; - SCSI_DIR : OUT std_logic; - MIDI_TLR : OUT std_logic; - TxD : OUT std_logic; - RTS : OUT std_logic; - DTR : OUT std_logic; - AMKB_TX : OUT std_logic; - IDE_RES : OUT std_logic; - nIDE_CS0 : OUT std_logic; - nIDE_CS1 : OUT std_logic; - nIDE_WR : OUT std_logic; - nIDE_RD : OUT std_logic; - nCF_CS0 : OUT std_logic; - nCF_CS1 : OUT std_logic; - nROM3 : OUT std_logic; - nROM4 : OUT std_logic; - nRP_UDS : OUT std_logic; - nRP_LDS : OUT std_logic; - nSDSEL : OUT std_logic; - nWR_GATE : OUT std_logic; - nWR : OUT std_logic; - YM_QA : OUT std_logic; - YM_QB : OUT std_logic; - YM_QC : OUT std_logic; - SD_CLK : OUT std_logic; - DSA_D : OUT std_logic; - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - nPD_VGA : OUT std_logic; - TIN0 : OUT std_logic; - nSRCS : OUT std_logic; - nSRBLE : OUT std_logic; - nSRBHE : OUT std_logic; - nSRWE : OUT std_logic; - nDREQ1 : OUT std_logic; - LED_FPGA_OK : OUT std_logic; - nSROE : OUT std_logic; - VCKE : OUT std_logic; - nFB_TA : OUT std_logic; - nDDR_CLK : OUT std_logic; - DDR_CLK : OUT std_logic; - VSYNC_PAD : OUT std_logic; - HSYNC_PAD : OUT std_logic; - nBLANK_PAD : OUT std_logic; - PIXEL_CLK_PAD : OUT std_logic; - nSYNC : OUT std_logic; - nMOT_ON : OUT std_logic; - nSTEP_DIR : OUT std_logic; - nSTEP : OUT std_logic; - LPDIR : OUT std_logic; - MIDI_OLR : OUT std_logic; - CLK25M : OUT std_logic; - CLKUSB : OUT std_logic; - CLK24M576 : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - nIRQ : OUT std_logic_vector(7 DOWNTO 2); + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + LP_BUSY : IN std_logic; + nACSI_DRQ : IN std_logic; + nACSI_INT : IN std_logic; + RxD : IN std_logic; + CTS : IN std_logic; + RI : IN std_logic; + DCD : IN std_logic; + AMKB_RX : IN std_logic; + PIC_AMKB_RX : IN std_logic; + IDE_RDY : IN std_logic; + IDE_INT : IN std_logic; + WP_CF_CARD : IN std_logic; + TRACK00 : IN std_logic; + nWP : IN std_logic; + nDCHG : IN std_logic; + SD_DATA0 : IN std_logic; + SD_DATA1 : IN std_logic; + SD_DATA2 : IN std_logic; + SD_CARD_DEDECT : IN std_logic; + nSCSI_DRQ : IN std_logic; + SD_WP : IN std_logic; + nRD_DATA : IN std_logic; + nSCSI_C_D : IN std_logic; + nSCSI_I_O : IN std_logic; + nSCSI_MSG : IN std_logic; + nDACK0 : IN std_logic; + PIC_INT : IN std_logic; + nFB_OE : IN std_logic; + TOUT0 : IN std_logic; + nMASTER : IN std_logic; + DVI_INT : IN std_logic; + nDACK1 : IN std_logic; + nPCI_INTD : IN std_logic; + nPCI_INTC : IN std_logic; + nPCI_INTB : IN std_logic; + nPCI_INTA : IN std_logic; + E0_INT : IN std_logic; + nINDEX : IN std_logic; + HD_DD : IN std_logic; + MAIN_CLK : IN std_logic; + nRSTO_MCF : IN std_logic; + CLK33MDIR : IN std_logic; + SCSI_PAR : INOUT std_logic; + nSCSI_RST : INOUT std_logic; + nSCSI_SEL : INOUT std_logic; + nSCSI_BUSY : INOUT std_logic; + SD_CD_DATA3 : INOUT std_logic; + SD_CMD_D1 : INOUT std_logic; + MIDI_IN_PIN : INOUT std_logic; + ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + IO : INOUT std_logic_vector(17 DOWNTO 0); + LP_D : INOUT std_logic_vector(7 DOWNTO 0); + SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); + SRD : INOUT std_logic_vector(15 DOWNTO 0); + VD : INOUT std_logic_vector(31 DOWNTO 0); + VDQS : INOUT std_logic_vector(3 DOWNTO 0); + LP_STR : OUT std_logic; + nACSI_ACK : OUT std_logic; + nACSI_RESET : OUT std_logic; + nACSI_CS : OUT std_logic; + ACSI_DIR : OUT std_logic; + ACSI_A1 : OUT std_logic; + nSCSI_ACK : OUT std_logic; + nSCSI_ATN : OUT std_logic; + SCSI_DIR : OUT std_logic; + MIDI_TLR : OUT std_logic; + TxD : OUT std_logic; + RTS : OUT std_logic; + DTR : OUT std_logic; + AMKB_TX : OUT std_logic; + IDE_RES : OUT std_logic; + nIDE_CS0 : OUT std_logic; + nIDE_CS1 : OUT std_logic; + nIDE_WR : OUT std_logic; + nIDE_RD : OUT std_logic; + nCF_CS0 : OUT std_logic; + nCF_CS1 : OUT std_logic; + nROM3 : OUT std_logic; + nROM4 : OUT std_logic; + nRP_UDS : OUT std_logic; + nRP_LDS : OUT std_logic; + nSDSEL : OUT std_logic; + nWR_GATE : OUT std_logic; + nWR : OUT std_logic; + YM_QA : OUT std_logic; + YM_QB : OUT std_logic; + YM_QC : OUT std_logic; + SD_CLK : OUT std_logic; + DSA_D : OUT std_logic; + nVWE : OUT std_logic; + nVCAS : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + nPD_VGA : OUT std_logic; + TIN0 : OUT std_logic; + nSRCS : OUT std_logic; + nSRBLE : OUT std_logic; + nSRBHE : OUT std_logic; + nSRWE : OUT std_logic; + nDREQ1 : OUT std_logic; + LED_FPGA_OK : OUT std_logic; + nSROE : OUT std_logic; + VCKE : OUT std_logic; + nFB_TA : OUT std_logic; + nDDR_CLK : OUT std_logic; + DDR_CLK : OUT std_logic; + VSYNC_PAD : OUT std_logic; + HSYNC_PAD : OUT std_logic; + nBLANK_PAD : OUT std_logic; + PIXEL_CLK_PAD : OUT std_logic; + nSYNC : OUT std_logic; + nMOT_ON : OUT std_logic; + nSTEP_DIR : OUT std_logic; + nSTEP : OUT std_logic; + LPDIR : OUT std_logic; + MIDI_OLR : OUT std_logic; + CLK25M : OUT std_logic; + CLKUSB : OUT std_logic; + CLK24M576 : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + nIRQ : OUT std_logic_vector(7 DOWNTO 2); VA : OUT std_logic_vector(12 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VDM : OUT std_logic_vector(3 DOWNTO 0); - VG : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0) + VB : OUT std_logic_vector(7 DOWNTO 0); + VDM : OUT std_logic_vector(3 DOWNTO 0); + VG : OUT std_logic_vector(7 DOWNTO 0); + VR : OUT std_logic_vector(7 DOWNTO 0) ); END firebee1; ARCHITECTURE rtl OF firebee1 IS + SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0); + SIGNAL clk25m_i : std_logic; + SIGNAL CLK2M : std_logic; + SIGNAL CLK2M4576 : std_logic; + SIGNAL CLK33M : std_logic; + SIGNAL CLK48M : std_logic; + SIGNAL CLK500k : std_logic; + SIGNAL CLK_VIDEO : std_logic; + SIGNAL DDR_SYNC_66M : std_logic; + SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); + SIGNAL DMA_DRQ : std_logic; + SIGNAL DSP_INT : std_logic; + SIGNAL DSP_TA : std_logic; + SIGNAL FALCON_IO_TA : std_logic; + SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0); + SIGNAL FDC_CLK : std_logic; + SIGNAL HSYNC : std_logic; + SIGNAL INT_HANDLER_TA : std_logic; + SIGNAL LP_DIR : std_logic; + SIGNAL MIDI_IN : std_logic; + SIGNAL MOT_ON : std_logic; + SIGNAL nBLANK : std_logic; + SIGNAL nDREQ0 : std_logic; + SIGNAL nMFP_INT : std_logic; + SIGNAL nRSTO : std_logic; + SIGNAL PIXEL_CLK : std_logic; + SIGNAL SD_CDM_D1 : std_logic; + SIGNAL STEP : std_logic; + SIGNAL STEP_DIR : std_logic; + SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0); + SIGNAL VIDEO_RECONFIG : std_logic; + SIGNAL Video_TA : std_logic; + SIGNAL VR_BUSY : std_logic; + SIGNAL VR_D : std_logic_vector(8 DOWNTO 0); + SIGNAL VR_RD : std_logic; + SIGNAL VR_WR : std_logic; + SIGNAL VSYNC : std_logic; + SIGNAL WR_DATA : std_logic; + SIGNAL WR_GATE : std_logic; + SIGNAL scandataout : std_logic; + SIGNAL scandone : std_logic; + SIGNAL reset : std_logic; + SIGNAL pll_reset : std_logic; + SIGNAL scanclk : std_logic; + SIGNAL scandata : std_logic; + SIGNAL scan_clkena : std_logic; + SIGNAL config_update : std_logic; + SIGNAL pll3_locked : std_logic; + SIGNAL pll1_locked : std_logic; + SIGNAL nSRCS_i : std_logic; + SIGNAL nFB_WR_i : std_logic; + SIGNAL nIDE_RD_i : std_logic; + SIGNAL nIDE_WR_i : std_logic; -COMPONENT altpll3 - PORT - ( - inclk0 : IN std_logic; - c0 : OUT std_logic; - c1 : OUT std_logic; - c2 : OUT std_logic; - c3 : OUT std_logic; - locked : OUT std_logic - ); -END COMPONENT; - -COMPONENT altpll2 - PORT - ( - inclk0 : IN std_logic; - c0 : OUT std_logic; - c1 : OUT std_logic; - c2 : OUT std_logic; - c3 : OUT std_logic; - c4 : OUT std_logic - ); -END COMPONENT; - -COMPONENT dsp - PORT - ( - CLK33M : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_OE : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - nRSTO : IN std_logic; - nFB_CS3 : IN std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - IO : INOUT std_logic_vector(17 DOWNTO 0); - SRD : INOUT std_logic_vector(15 DOWNTO 0); - nSRCS : OUT std_logic; - nSRBLE : OUT std_logic; - nSRBHE : OUT std_logic; - nSRWE : OUT std_logic; - nSROE : OUT std_logic; - DSP_INT : OUT std_logic; - DSP_TA : OUT std_logic - ); -END COMPONENT; - -COMPONENT falconio_sdcard_ide_cf - PORT - ( - CLK33M : IN std_logic; - MAIN_CLK : IN std_logic; - CLK2M : IN std_logic; - CLK500k : IN std_logic; - nFB_CS1 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - LP_BUSY : IN std_logic; - nACSI_DRQ : IN std_logic; - nACSI_INT : IN std_logic; - nSCSI_DRQ : IN std_logic; - nSCSI_MSG : IN std_logic; - MIDI_IN : IN std_logic; - RxD : IN std_logic; - CTS : IN std_logic; - RI : IN std_logic; - DCD : IN std_logic; - AMKB_RX : IN std_logic; - PIC_AMKB_RX : IN std_logic; - IDE_RDY : IN std_logic; - IDE_INT : IN std_logic; - WP_CS_CARD : IN std_logic; - nINDEX : IN std_logic; - TRACK00 : IN std_logic; - nRD_DATA : IN std_logic; - nDCHG : IN std_logic; - SD_DATA0 : IN std_logic; - SD_DATA1 : IN std_logic; - SD_DATA2 : IN std_logic; - SD_CARD_DEDECT : IN std_logic; - SD_WP : IN std_logic; - nDACK0 : IN std_logic; - nFB_WR : IN std_logic; - WP_CF_CARD : IN std_logic; - nWP : IN std_logic; - nFB_CS2 : IN std_logic; - nRSTO : IN std_logic; - nSCSI_C_D : IN std_logic; - nSCSI_I_O : IN std_logic; - CLK2M4576 : IN std_logic; - nFB_OE : IN std_logic; - VSYNC : IN std_logic; - HSYNC : IN std_logic; - DSP_INT : IN std_logic; - nBLANK : IN std_logic; - FDC_CLK : IN std_logic; - FB_ALE : IN std_logic; - HD_DD : IN std_logic; - SCSI_PAR : INOUT std_logic; - nSCSI_SEL : INOUT std_logic; - nSCSI_BUSY : INOUT std_logic; - nSCSI_RST : INOUT std_logic; - SD_CD_DATA3 : INOUT std_logic; - SD_CDM_D1 : INOUT std_logic; - ACP_CONF : IN std_logic_vector(31 DOWNTO 24); - ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - LP_D : INOUT std_logic_vector(7 DOWNTO 0); - SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); - nIDE_CS1 : OUT std_logic; - nIDE_CS0 : OUT std_logic; - LP_STR : OUT std_logic; - LP_DIR : OUT std_logic; - nACSI_ACK : OUT std_logic; - nACSI_RESET : OUT std_logic; - nACSI_CS : OUT std_logic; - ACSI_DIR : OUT std_logic; - ACSI_A1 : OUT std_logic; - nSCSI_ACK : OUT std_logic; - nSCSI_ATN : OUT std_logic; - SCSI_DIR : OUT std_logic; - SD_CLK : OUT std_logic; - YM_QA : OUT std_logic; - YM_QC : OUT std_logic; - YM_QB : OUT std_logic; - nSDSEL : OUT std_logic; - STEP : OUT std_logic; - MOT_ON : OUT std_logic; - nRP_LDS : OUT std_logic; - nRP_UDS : OUT std_logic; - nROM4 : OUT std_logic; - nROM3 : OUT std_logic; - nCF_CS1 : OUT std_logic; - nCF_CS0 : OUT std_logic; - nIDE_RD : OUT std_logic; - nIDE_WR : OUT std_logic; - AMKB_TX : OUT std_logic; - IDE_RES : OUT std_logic; - DTR : OUT std_logic; - RTS : OUT std_logic; - TxD : OUT std_logic; - MIDI_OLR : OUT std_logic; - nDREQ0 : OUT std_logic; - DSA_D : OUT std_logic; - nMFP_INT : OUT std_logic; - FALCON_IO_TA : OUT std_logic; - STEP_DIR : OUT std_logic; - WR_DATA : OUT std_logic; - WR_GATE : OUT std_logic; - DMA_DRQ : OUT std_logic; - MIDI_TLR : OUT std_logic - ); -END COMPONENT; - -COMPONENT interrupt_handler - PORT - ( - MAIN_CLK : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - PIC_INT : IN std_logic; - E0_INT : IN std_logic; - DVI_INT : IN std_logic; - nPCI_INTA : IN std_logic; - nPCI_INTB : IN std_logic; - nPCI_INTC : IN std_logic; - nPCI_INTD : IN std_logic; - nMFP_INT : IN std_logic; - nFB_OE : IN std_logic; - DSP_INT : IN std_logic; - VSYNC : IN std_logic; - HSYNC : IN std_logic; - DMA_DRQ : IN std_logic; - nRSTO : IN std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - INT_HANDLER_TA : OUT std_logic; - TIN0 : OUT std_logic; - ACP_CONF : OUT std_logic_vector(31 DOWNTO 0); - nIRQ : OUT std_logic_vector(7 DOWNTO 2) - ); -END COMPONENT; - -COMPONENT altpll1 - PORT - ( - inclk0 : IN std_logic; - c0 : OUT std_logic; - c1 : OUT std_logic; - c2 : OUT std_logic; - locked : OUT std_logic - ); -END COMPONENT; - -COMPONENT altpll_reconfig1 - PORT - ( - reconfig : IN std_logic; - read_param : IN std_logic; - write_param : IN std_logic; - pll_scandataout : IN std_logic; - pll_scandone : IN std_logic; - clock : IN std_logic; - reset : IN std_logic; - pll_areset_in : IN std_logic; - counter_param : IN std_logic_vector(2 DOWNTO 0); - counter_type : IN std_logic_vector(3 DOWNTO 0); - data_in : IN std_logic_vector(8 DOWNTO 0); - busy : OUT std_logic; - pll_scandata : OUT std_logic; - pll_scanclk : OUT std_logic; - pll_scanclkena : OUT std_logic; - pll_configupdate : OUT std_logic; - pll_areset : OUT std_logic; - data_out : OUT std_logic_vector(8 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT video - PORT - ( - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - nFB_OE : IN std_logic; - FB_ALE : IN std_logic; - DDR_SYNC_66M : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_BUSY : IN std_logic; - DDRCLK : IN std_logic_vector(3 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0); - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - VR_D : IN std_logic_vector(8 DOWNTO 0); - VR_RD : OUT std_logic; - nBLANK : OUT std_logic; - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - nPD_VGA : OUT std_logic; - VCKE : OUT std_logic; - VSYNC : OUT std_logic; - HSYNC : OUT std_logic; - nSYNC : OUT std_logic; - VIDEO_TA : OUT std_logic; - PIXEL_CLK : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - VA : OUT std_logic_vector(12 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VDM : OUT std_logic_vector(3 DOWNTO 0); - VG : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT altpll4 - PORT(inclk0 : IN std_logic; - areset : IN std_logic; - scanclk : IN std_logic; - scandata : IN std_logic; - scanclkena : IN std_logic; - configupdate : IN std_logic; - c0 : OUT std_logic; - scandataout : OUT std_logic; - scandone : OUT std_logic; - locked : OUT std_logic - ); -END COMPONENT; - -COMPONENT lpm_ff0 - PORT(clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_counter0 - PORT(clock : IN std_logic; - q : OUT std_logic_vector(17 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT alt_iobuf - PORT(i : IN std_logic; - oe : IN std_logic; - io : INOUT std_logic; - o : OUT std_logic - ); -END COMPONENT; - -COMPONENT altddio_out3 - PORT(datain_h : IN std_logic; - datain_l : IN std_logic; - outclock : IN std_logic; - dataout : OUT std_logic - ); -END COMPONENT; - -SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0); -SIGNAL CLK25M_ALTERA_SYNTHESIZED : std_logic; -SIGNAL CLK2M : std_logic; -SIGNAL CLK2M4576 : std_logic; -SIGNAL CLK33M : std_logic; -SIGNAL CLK48M : std_logic; -SIGNAL CLK500k : std_logic; -SIGNAL CLK_VIDEO : std_logic; -SIGNAL DDR_SYNC_66M : std_logic; -SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); -SIGNAL DMA_DRQ : std_logic; -SIGNAL DSP_INT : std_logic; -SIGNAL DSP_TA : std_logic; -SIGNAL FALCON_IO_TA : std_logic; -SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0); -SIGNAL FDC_CLK : std_logic; -SIGNAL HSYNC : std_logic; -SIGNAL INT_HANDLER_TA : std_logic; -SIGNAL LP_DIR : std_logic; -SIGNAL MIDI_IN : std_logic; -SIGNAL MOT_ON : std_logic; -SIGNAL nBLANK : std_logic; -SIGNAL nDREQ0 : std_logic; -SIGNAL nMFP_INT : std_logic; -SIGNAL nRSTO : std_logic; -SIGNAL PIXEL_CLK : std_logic; -SIGNAL SD_CDM_D1 : std_logic; -SIGNAL STEP : std_logic; -SIGNAL STEP_DIR : std_logic; -SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0); -SIGNAL VIDEO_RECONFIG : std_logic; -SIGNAL Video_TA : std_logic; -SIGNAL VR_BUSY : std_logic; -SIGNAL VR_D : std_logic_vector(8 DOWNTO 0); -SIGNAL VR_RD : std_logic; -SIGNAL VR_WR : std_logic; -SIGNAL VSYNC : std_logic; -SIGNAL WR_DATA : std_logic; -SIGNAL WR_GATE : std_logic; -SIGNAL SYNTHESIZED_WIRE_0 : std_logic; -SIGNAL SYNTHESIZED_WIRE_1 : std_logic; -SIGNAL SYNTHESIZED_WIRE_2 : std_logic; -SIGNAL SYNTHESIZED_WIRE_3 : std_logic; -SIGNAL SYNTHESIZED_WIRE_4 : std_logic; -SIGNAL SYNTHESIZED_WIRE_5 : std_logic; -SIGNAL SYNTHESIZED_WIRE_6 : std_logic; -SIGNAL SYNTHESIZED_WIRE_7 : std_logic; -SIGNAL SYNTHESIZED_WIRE_8 : std_logic; -SIGNAL SYNTHESIZED_WIRE_9 : std_logic; -SIGNAL SYNTHESIZED_WIRE_10 : std_logic; -SIGNAL SYNTHESIZED_WIRE_11 : std_logic; - + COMPONENT altpll_reconfig1 + PORT + ( + clock : IN STD_LOGIC ; + counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); + counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0); + data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset_in : IN STD_LOGIC := '0'; + pll_scandataout : IN STD_LOGIC ; + pll_scandone : IN STD_LOGIC ; + read_param : IN STD_LOGIC ; + reconfig : IN STD_LOGIC ; + reset : IN STD_LOGIC ; + write_param : IN STD_LOGIC ; + busy : OUT STD_LOGIC ; + data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); + pll_areset : OUT STD_LOGIC ; + pll_configupdate : OUT STD_LOGIC ; + pll_scanclk : OUT STD_LOGIC ; + pll_scanclkena : OUT STD_LOGIC ; + pll_scandata : OUT STD_LOGIC + ); + END COMPONENT altpll_reconfig1; + + COMPONENT altpll4 + PORT + ( + areset : IN STD_LOGIC := '0'; + configupdate : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + scanclk : IN STD_LOGIC := '1'; + scanclkena : IN STD_LOGIC := '0'; + scandata : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ; + scandataout : OUT STD_LOGIC ; + scandone : OUT STD_LOGIC + ); + END COMPONENT altpll4; BEGIN -nDREQ1 <= nDACK1; -SYNTHESIZED_WIRE_10 <= '0'; -SYNTHESIZED_WIRE_11 <= '1'; - - - -i_atari_clk_pll : altpll3 -PORT MAP(inclk0 => MAIN_CLK, - c0 => CLK25M_ALTERA_SYNTHESIZED, - c1 => CLK2M, - c2 => CLK500k, - c3 => CLK2M4576, - locked => SYNTHESIZED_WIRE_8); - - -i_ddr_clk_pll : altpll2 -PORT MAP(inclk0 => MAIN_CLK, - c0 => DDRCLK(0), - c1 => DDRCLK(1), - c2 => DDRCLK(2), - c3 => DDRCLK(3), - c4 => DDR_SYNC_66M); - - -i_dsp : dsp -PORT MAP(CLK33M => CLK33M, - MAIN_CLK => MAIN_CLK, - nFB_OE => nFB_OE, - nFB_WR => nFB_WR, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - nRSTO => nRSTO, - nFB_CS3 => nFB_CS3, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - IO => IO, - SRD => SRD, - nSRCS => nSRCS, - nSRBLE => nSRBLE, - nSRBHE => nSRBHE, - nSRWE => nSRWE, - nSROE => nSROE, - DSP_INT => DSP_INT, - DSP_TA => DSP_TA); - - -i_falcioio_sdcard_ide_cf : falconio_sdcard_ide_cf -PORT MAP(CLK33M => CLK33M, - MAIN_CLK => MAIN_CLK, - CLK2M => CLK2M, - CLK500k => CLK500k, - nFB_CS1 => nFB_CS1, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - LP_BUSY => LP_BUSY, - nACSI_DRQ => nACSI_DRQ, - nACSI_INT => nACSI_INT, - nSCSI_DRQ => nSCSI_DRQ, - nSCSI_MSG => nSCSI_MSG, - MIDI_IN => MIDI_IN, - RxD => RxD, - CTS => CTS, - RI => RI, - DCD => DCD, - AMKB_RX => AMKB_RX, - PIC_AMKB_RX => PIC_AMKB_RX, - IDE_RDY => IDE_RDY, - IDE_INT => IDE_INT, - WP_CS_CARD => '0', - nINDEX => nINDEX, - TRACK00 => TRACK00, - nRD_DATA => nRD_DATA, - nDCHG => nDCHG, - SD_DATA0 => SD_DATA0, - SD_DATA1 => SD_DATA1, - SD_DATA2 => SD_DATA2, - SD_CARD_DEDECT => SD_CARD_DEDECT, - SD_WP => SD_WP, - nDACK0 => nDACK0, - nFB_WR => nFB_WR, - WP_CF_CARD => WP_CF_CARD, - nWP => nWP, - nFB_CS2 => nFB_CS2, - nRSTO => nRSTO, - nSCSI_C_D => nSCSI_C_D, - nSCSI_I_O => nSCSI_I_O, - CLK2M4576 => CLK2M4576, - nFB_OE => nFB_OE, - VSYNC => VSYNC, - HSYNC => HSYNC, - DSP_INT => DSP_INT, - nBLANK => nBLANK, - FDC_CLK => FDC_CLK, - FB_ALE => FB_ALE, - HD_DD => HD_DD, - SCSI_PAR => SCSI_PAR, - nSCSI_SEL => nSCSI_SEL, - nSCSI_BUSY => nSCSI_BUSY, - nSCSI_RST => nSCSI_RST, - SD_CD_DATA3 => SD_CD_DATA3, - SD_CDM_D1 => SD_CDM_D1, - ACP_CONF => ACP_CONF(31 DOWNTO 24), - ACSI_D => ACSI_D, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - LP_D => LP_D, - SCSI_D => SCSI_D, - nIDE_CS1 => nIDE_CS1, - nIDE_CS0 => nIDE_CS0, - LP_STR => LP_STR, - LP_DIR => LP_DIR, - nACSI_ACK => nACSI_ACK, - nACSI_RESET => nACSI_RESET, - nACSI_CS => nACSI_CS, - ACSI_DIR => ACSI_DIR, - ACSI_A1 => ACSI_A1, - nSCSI_ACK => nSCSI_ACK, - nSCSI_ATN => nSCSI_ATN, - SCSI_DIR => SCSI_DIR, - SD_CLK => SD_CLK, - YM_QA => YM_QA, - YM_QC => YM_QC, - YM_QB => YM_QB, - nSDSEL => nSDSEL, - STEP => STEP, - MOT_ON => MOT_ON, - nRP_LDS => nRP_LDS, - nRP_UDS => nRP_UDS, - nROM4 => nROM4, - nROM3 => nROM3, - nCF_CS1 => nCF_CS1, - nCF_CS0 => nCF_CS0, - nIDE_RD => nIDE_RD, - nIDE_WR => nIDE_WR, - AMKB_TX => AMKB_TX, - IDE_RES => IDE_RES, - DTR => DTR, - RTS => RTS, - TxD => TxD, - MIDI_OLR => MIDI_OLR, - DSA_D => DSA_D, - nMFP_INT => nMFP_INT, - FALCON_IO_TA => FALCON_IO_TA, - STEP_DIR => STEP_DIR, - WR_DATA => WR_DATA, - WR_GATE => WR_GATE, - DMA_DRQ => DMA_DRQ, - MIDI_TLR => MIDI_TLR); - - -i_interrupt_handler : interrupt_handler -PORT MAP(MAIN_CLK => MAIN_CLK, - nFB_WR => nFB_WR, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - PIC_INT => PIC_INT, - E0_INT => E0_INT, - DVI_INT => DVI_INT, - nPCI_INTA => nPCI_INTA, - nPCI_INTB => nPCI_INTB, - nPCI_INTC => nPCI_INTC, - nPCI_INTD => nPCI_INTD, - nMFP_INT => nMFP_INT, - nFB_OE => nFB_OE, - DSP_INT => DSP_INT, - VSYNC => VSYNC, - HSYNC => HSYNC, - DMA_DRQ => DMA_DRQ, - nRSTO => nRSTO, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - INT_HANDLER_TA => INT_HANDLER_TA, - TIN0 => TIN0, - ACP_CONF => ACP_CONF, - nIRQ => nIRQ); - - -i_mfp_acia_clk_pll : altpll1 -PORT MAP(inclk0 => MAIN_CLK, - c0 => CLK48M, - c1 => FDC_CLK, - c2 => CLK24M576, - locked => SYNTHESIZED_WIRE_9); - - -i_pll_reconfig : altpll_reconfig1 -PORT MAP(reconfig => VIDEO_RECONFIG, - read_param => VR_RD, - write_param => VR_WR, - pll_areset_in => '0', - pll_scandataout => SYNTHESIZED_WIRE_0, - pll_scandone => SYNTHESIZED_WIRE_1, - clock => MAIN_CLK, - reset => SYNTHESIZED_WIRE_2, - counter_param => FB_ADR(8 DOWNTO 6), - counter_type => FB_ADR(5 DOWNTO 2), - data_in => FB_AD(24 DOWNTO 16), - busy => VR_BUSY, - pll_scandata => SYNTHESIZED_WIRE_5, - pll_scanclk => SYNTHESIZED_WIRE_4, - pll_scanclkena => SYNTHESIZED_WIRE_6, - pll_configupdate => SYNTHESIZED_WIRE_7, - pll_areset => SYNTHESIZED_WIRE_3, - data_out => VR_D); - - -i_video : video -PORT MAP(MAIN_CLK => MAIN_CLK, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_WR => nFB_WR, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nRSTO => nRSTO, - nFB_OE => nFB_OE, - FB_ALE => FB_ALE, - DDR_SYNC_66M => DDR_SYNC_66M, - CLK33M => CLK33M, - CLK25M => CLK25M_ALTERA_SYNTHESIZED, - CLK_VIDEO => CLK_VIDEO, - VR_BUSY => VR_BUSY, - DDRCLK => DDRCLK, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - VD => VD, - VDQS => VDQS, - VR_D => VR_D, - VR_RD => VR_RD, - nBLANK => nBLANK, - nVWE => nVWE, - nVCAS => nVCAS, - nVRAS => nVRAS, - nVCS => nVCS, - nPD_VGA => nPD_VGA, - VCKE => VCKE, - VSYNC => VSYNC, - HSYNC => HSYNC, - nSYNC => nSYNC, - VIDEO_TA => Video_TA, - PIXEL_CLK => PIXEL_CLK, - VIDEO_RECONFIG => VIDEO_RECONFIG, - VR_WR => VR_WR, - BA => BA, - VA => VA, - VB => VB, - VDM => VDM, - VG => VG, - VR => VR); - - -i_video_clk_pll : altpll4 -PORT MAP(inclk0 => CLK48M, - areset => SYNTHESIZED_WIRE_3, - scanclk => SYNTHESIZED_WIRE_4, - scandata => SYNTHESIZED_WIRE_5, - scanclkena => SYNTHESIZED_WIRE_6, - configupdate => SYNTHESIZED_WIRE_7, - c0 => CLK_VIDEO, - scandataout => SYNTHESIZED_WIRE_0, - scandone => SYNTHESIZED_WIRE_1); - - -inst1 : lpm_ff0 -PORT MAP(clock => DDR_SYNC_66M, - enable => FB_ALE, - data => FB_AD, - q => FB_ADR); - - - - -nMOT_ON <= NOT(MOT_ON); - - - -nSTEP_DIR <= NOT(STEP_DIR); - - - -nSTEP <= NOT(STEP); - - - -nWR <= NOT(WR_DATA); - - - -inst18 : lpm_counter0 -PORT MAP(clock => CLK500k, - q => TIMEBASE); - - -nWR_GATE <= NOT(WR_GATE); - - - -nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA); - -CLK33M <= MAIN_CLK; - - - -SYNTHESIZED_WIRE_2 <= NOT(nRSTO); - - - -nRSTO <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_9 AND nRSTO_MCF; - - -inst29 : alt_iobuf -PORT MAP(i => CLK2M, - oe => CLK2M, - io => MIDI_IN_PIN, - o => MIDI_IN); - -LED_FPGA_OK <= TIMEBASE(17); - - - -nDDR_CLK <= NOT(DDRCLK(0)); - - - -inst5 : altddio_out3 -PORT MAP(datain_h => VSYNC, - datain_l => VSYNC, - outclock => PIXEL_CLK, - dataout => VSYNC_PAD); - - -inst6 : altddio_out3 -PORT MAP(datain_h => HSYNC, - datain_l => HSYNC, - outclock => PIXEL_CLK, - dataout => HSYNC_PAD); - - -inst8 : altddio_out3 -PORT MAP(datain_h => nBLANK, - datain_l => nBLANK, - outclock => PIXEL_CLK, - dataout => nBLANK_PAD); - - -inst9 : altddio_out3 -PORT MAP(datain_h => SYNTHESIZED_WIRE_10, - datain_l => SYNTHESIZED_WIRE_11, - outclock => PIXEL_CLK, - dataout => PIXEL_CLK_PAD); - -SD_CMD_D1 <= SD_CDM_D1; -DDR_CLK <= DDRCLK(0); -LPDIR <= LP_DIR; -CLK25M <= CLK25M_ALTERA_SYNTHESIZED; -CLKUSB <= CLK48M; - + nDREQ1 <= nDACK1; + + i_atari_clk_pll : work.altpll3 + PORT MAP + ( + inclk0 => MAIN_CLK, + c0 => clk25m_i, + c1 => CLK2M, + c2 => CLK500k, + c3 => CLK2M4576, + locked => pll3_locked + ); + + + i_ddr_clk_pll : work.altpll2 + PORT MAP + ( + inclk0 => MAIN_CLK, + c0 => DDRCLK(0), + c1 => DDRCLK(1), + c2 => DDRCLK(2), + c3 => DDRCLK(3), + c4 => DDR_SYNC_66M + ); + + + i_dsp : work.dsp + PORT MAP + ( + CLK33M => CLK33M, + MAIN_CLK => MAIN_CLK, + nFB_OE => nFB_OE, + nFB_WR => nFB_WR, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + nRSTO => nRSTO, + nFB_CS3 => nFB_CS3, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + IO => IO, + SRD => SRD, + nSRCS => nSRCS_i, + nSRBLE => nSRBLE, + nSRBHE => nSRBHE, + nSRWE => nSRWE, + nSROE => nSROE, + DSP_INT => DSP_INT, + DSP_TA => DSP_TA + ); + + + i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf + PORT MAP + ( + CLK33M => CLK33M, + MAIN_CLK => MAIN_CLK, + CLK2M => CLK2M, + CLK500k => CLK500k, + nFB_CS1 => nFB_CS1, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + LP_BUSY => LP_BUSY, + nACSI_DRQ => nACSI_DRQ, + nACSI_INT => nACSI_INT, + nSCSI_DRQ => nSCSI_DRQ, + nSCSI_MSG => nSCSI_MSG, + MIDI_IN => MIDI_IN, + RxD => RxD, + CTS => CTS, + RI => RI, + DCD => DCD, + AMKB_RX => AMKB_RX, + PIC_AMKB_RX => PIC_AMKB_RX, + IDE_RDY => IDE_RDY, + IDE_INT => IDE_INT, + WP_CS_CARD => '0', + nINDEX => nINDEX, + TRACK00 => TRACK00, + nRD_DATA => nRD_DATA, + nDCHG => nDCHG, + SD_DATA0 => SD_DATA0, + SD_DATA1 => SD_DATA1, + SD_DATA2 => SD_DATA2, + SD_CARD_DEDECT => SD_CARD_DEDECT, + SD_WP => SD_WP, + nDACK0 => nDACK0, + nFB_WR => nFB_WR_i, + WP_CF_CARD => WP_CF_CARD, + nWP => nWP, + nFB_CS2 => nFB_CS2, + nRSTO => nRSTO, + nSCSI_C_D => nSCSI_C_D, + nSCSI_I_O => nSCSI_I_O, + CLK2M4576 => CLK2M4576, + nFB_OE => nFB_OE, + VSYNC => VSYNC, + HSYNC => HSYNC, + DSP_INT => DSP_INT, + nBLANK => nBLANK, + FDC_CLK => FDC_CLK, + FB_ALE => FB_ALE, + HD_DD => HD_DD, + SCSI_PAR => SCSI_PAR, + nSCSI_SEL => nSCSI_SEL, + nSCSI_BUSY => nSCSI_BUSY, + nSCSI_RST => nSCSI_RST, + SD_CD_DATA3 => SD_CD_DATA3, + SD_CDM_D1 => SD_CDM_D1, + ACP_CONF => ACP_CONF(31 DOWNTO 24), + ACSI_D => ACSI_D, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + LP_D => LP_D, + SCSI_D => SCSI_D, + nIDE_CS1 => nIDE_CS1, + nIDE_CS0 => nIDE_CS0, + LP_STR => LP_STR, + LP_DIR => LP_DIR, + nACSI_ACK => nACSI_ACK, + nACSI_RESET => nACSI_RESET, + nACSI_CS => nACSI_CS, + ACSI_DIR => ACSI_DIR, + ACSI_A1 => ACSI_A1, + nSCSI_ACK => nSCSI_ACK, + nSCSI_ATN => nSCSI_ATN, + SCSI_DIR => SCSI_DIR, + SD_CLK => SD_CLK, + YM_QA => YM_QA, + YM_QC => YM_QC, + YM_QB => YM_QB, + nSDSEL => nSDSEL, + STEP => STEP, + MOT_ON => MOT_ON, + nRP_LDS => nRP_LDS, + nRP_UDS => nRP_UDS, + nROM4 => nROM4, + nROM3 => nROM3, + nCF_CS1 => nCF_CS1, + nCF_CS0 => nCF_CS0, + nIDE_RD => nIDE_RD_i, + nIDE_WR => nIDE_WR_i, + AMKB_TX => AMKB_TX, + IDE_RES => IDE_RES, + DTR => DTR, + RTS => RTS, + TxD => TxD, + MIDI_OLR => MIDI_OLR, + DSA_D => DSA_D, + nMFP_INT => nMFP_INT, + FALCON_IO_TA => FALCON_IO_TA, + STEP_DIR => STEP_DIR, + WR_DATA => WR_DATA, + WR_GATE => WR_GATE, + DMA_DRQ => DMA_DRQ, + MIDI_TLR => MIDI_TLR + ); + + + i_interrupt_handler : work.interrupt_handler + PORT MAP + ( + MAIN_CLK => MAIN_CLK, + nFB_WR => nFB_WR, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + PIC_INT => PIC_INT, + E0_INT => E0_INT, + DVI_INT => DVI_INT, + nPCI_INTA => nPCI_INTA, + nPCI_INTB => nPCI_INTB, + nPCI_INTC => nPCI_INTC, + nPCI_INTD => nPCI_INTD, + nMFP_INT => nMFP_INT, + nFB_OE => nFB_OE, + DSP_INT => DSP_INT, + VSYNC => VSYNC, + HSYNC => HSYNC, + DMA_DRQ => DMA_DRQ, + nRSTO => nRSTO, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + INT_HANDLER_TA => INT_HANDLER_TA, + TIN0 => TIN0, + ACP_CONF => ACP_CONF, + nIRQ => nIRQ + ); + + + i_mfp_acia_clk_pll : work.altpll1 + PORT MAP + ( + inclk0 => MAIN_CLK, + c0 => CLK48M, + c1 => FDC_CLK, + c2 => CLK24M576, + locked => pll1_locked + ); + + + i_pll_reconfig : altpll_reconfig1 + PORT MAP + ( + reconfig => VIDEO_RECONFIG, + read_param => VR_RD, + write_param => VR_WR, + pll_areset_in => '0', + pll_scandataout => scandataout, + pll_scandone => scandone, + clock => MAIN_CLK, + reset => reset, + counter_param => FB_ADR(8 DOWNTO 6), + counter_type => FB_ADR(5 DOWNTO 2), + data_in => FB_AD(24 DOWNTO 16), + busy => VR_BUSY, + pll_scandata => scandata, + pll_scanclk => scanclk, + pll_scanclkena => scan_clkena, + pll_configupdate => config_update, + pll_areset => pll_reset, + data_out => VR_D + ); + + + i_video : work.video + PORT MAP + ( + MAIN_CLK => MAIN_CLK, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_WR => nFB_WR, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nRSTO => nRSTO, + nFB_OE => nFB_OE, + FB_ALE => FB_ALE, + DDR_SYNC_66M => DDR_SYNC_66M, + CLK33M => CLK33M, + CLK25M => clk25m_i, + CLK_VIDEO => CLK_VIDEO, + VR_BUSY => VR_BUSY, + DDRCLK => DDRCLK, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VD => VD, + VDQS => VDQS, + VR_D => VR_D, + VR_RD => VR_RD, + nBLANK => nBLANK, + nVWE => nVWE, + nVCAS => nVCAS, + nVRAS => nVRAS, + nVCS => nVCS, + nPD_VGA => nPD_VGA, + VCKE => VCKE, + VSYNC => VSYNC, + HSYNC => HSYNC, + nSYNC => nSYNC, + VIDEO_TA => Video_TA, + PIXEL_CLK => PIXEL_CLK, + VIDEO_RECONFIG => VIDEO_RECONFIG, + VR_WR => VR_WR, + BA => BA, + VA => VA, + VB => VB, + VDM => VDM, + VG => VG, + VR => VR + ); + + + i_video_clk_pll : altpll4 + PORT MAP + ( + inclk0 => CLK48M, + areset => pll_reset, + scanclk => scanclk, + scandata => scandata, + scanclkena => scan_clkena, + configupdate => config_update, + c0 => CLK_VIDEO, + scandataout => scandataout, + scandone => scandone + ); + + + inst1 : work.lpm_ff0 + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_ALE, + data => FB_AD, + q => FB_ADR + ); + + nMOT_ON <= NOT(MOT_ON); + nSTEP_DIR <= NOT(STEP_DIR); + nSTEP <= NOT(STEP); + nWR <= NOT(WR_DATA); + + inst18 : work.lpm_counter0 + PORT MAP + ( + clock => CLK500k, + q => TIMEBASE + ); + + + nWR_GATE <= NOT(WR_GATE); + + nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA); + + CLK33M <= MAIN_CLK; + + reset <= NOT(nRSTO); + nRSTO <= pll3_locked AND pll1_locked AND nRSTO_MCF; + + inst29 : alt_iobuf + PORT MAP + ( + i => CLK2M, + oe => CLK2M, + io => MIDI_IN_PIN, + o => MIDI_IN + ); + + LED_FPGA_OK <= TIMEBASE(17); + + nDDR_CLK <= NOT(DDRCLK(0)); + + inst5 : work.altddio_out3 + PORT MAP + ( + datain_h => VSYNC, + datain_l => VSYNC, + outclock => PIXEL_CLK, + dataout => VSYNC_PAD + ); + + + inst6 : work.altddio_out3 + PORT MAP + ( + datain_h => HSYNC, + datain_l => HSYNC, + outclock => PIXEL_CLK, + dataout => HSYNC_PAD + ); + + + inst8 : work.altddio_out3 + PORT MAP + ( + datain_h => nBLANK, + datain_l => nBLANK, + outclock => PIXEL_CLK, + dataout => nBLANK_PAD + ); + + inst9 : work.altddio_out3 + PORT MAP + ( + datain_h => '0', + datain_l => '1', + outclock => PIXEL_CLK, + dataout => PIXEL_CLK_PAD + ); + + SD_CMD_D1 <= SD_CDM_D1; + DDR_CLK <= DDRCLK(0); + LPDIR <= LP_DIR; + CLK25M <= clk25m_i; + CLKUSB <= CLK48M; + nSRCS <= nSRCS_i; + + nIDE_RD <= nIDE_RD_i; + nIDE_WR <= nIDE_WR_i; END rtl; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd b/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd index 85cbdd1..7f269cd 100644 --- a/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd +++ b/FPGA_Quartus_13.1/lpm_bustri_WORD.vhd @@ -43,7 +43,7 @@ ENTITY lpm_bustri_WORD IS PORT ( data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - enabledt : IN STD_LOGIC ; + enabledt : IN STD_LOGIC ; tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END lpm_bustri_WORD; @@ -61,8 +61,8 @@ ARCHITECTURE SYN OF lpm_bustri_word IS ); PORT ( enabledt : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + tridata : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END COMPONENT; From b35e12b32990eb235852f2f8777b8d7b0de156ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 17:05:39 +0000 Subject: [PATCH 045/127] add more DDR clk signals to sdc --- FPGA_Quartus_13.1/Video/video.vhd | 3472 ++++++++++++++--------------- FPGA_Quartus_13.1/firebee1.sdc | 11 + 2 files changed, 1746 insertions(+), 1737 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 33fcbfb..0b60561 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -24,1746 +24,1744 @@ LIBRARY work; ENTITY video IS PORT ( - MAIN_CLK : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - DDR_SYNC_66M : IN STD_LOGIC; - CLK33M : IN STD_LOGIC; - CLK25M : IN STD_LOGIC; - CLK_VIDEO : IN STD_LOGIC; - VR_BUSY : IN STD_LOGIC; - DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); - nBLANK : OUT STD_LOGIC; - nVWE : OUT STD_LOGIC; - nVCAS : OUT STD_LOGIC; - nVRAS : OUT STD_LOGIC; - nVCS : OUT STD_LOGIC; - nPD_VGA : OUT STD_LOGIC; - VCKE : OUT STD_LOGIC; - VSYNC : OUT STD_LOGIC; - HSYNC : OUT STD_LOGIC; - nSYNC : OUT STD_LOGIC; - VIDEO_TA : OUT STD_LOGIC; - PIXEL_CLK : OUT STD_LOGIC; - VIDEO_RECONFIG : OUT STD_LOGIC; - VR_WR : OUT STD_LOGIC; - VR_RD : OUT STD_LOGIC; - BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + nFB_OE : IN std_logic; + FB_ALE : IN std_logic; + DDR_SYNC_66M : IN std_logic; + CLK33M : IN std_logic; + CLK25M : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_BUSY : IN std_logic; + DDRCLK : IN std_logic_vector(3 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VD : INOUT std_logic_vector(31 DOWNTO 0); + VDQS : INOUT std_logic_vector(3 DOWNTO 0); + VR_D : IN std_logic_vector(8 DOWNTO 0); + nBLANK : OUT std_logic; + nVWE : OUT std_logic; + nVCAS : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + nPD_VGA : OUT std_logic; + VCKE : OUT std_logic; + VSYNC : OUT std_logic; + HSYNC : OUT std_logic; + nSYNC : OUT std_logic; + VIDEO_TA : OUT std_logic; + PIXEL_CLK : OUT std_logic; + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + VR_RD : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + VA : OUT std_logic_vector(12 DOWNTO 0); + VB : OUT std_logic_vector(7 DOWNTO 0); + VDM : OUT std_logic_vector(3 DOWNTO 0); + VG : OUT std_logic_vector(7 DOWNTO 0); + VR : OUT std_logic_vector(7 DOWNTO 0) ); END video; ARCHITECTURE bdf_type OF video IS - -ATTRIBUTE black_box : BOOLEAN; -ATTRIBUTE noopt : BOOLEAN; - -COMPONENT mux41_0 - PORT(S0 : IN STD_LOGIC; - S1 : IN STD_LOGIC; - D0 : IN STD_LOGIC; - INH : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q : OUT STD_LOGIC); -END COMPONENT; - -ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; -ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; - -COMPONENT mux41_1 - PORT(S0 : IN STD_LOGIC; - S1 : IN STD_LOGIC; - D0 : IN STD_LOGIC; - INH : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q : OUT STD_LOGIC); -END COMPONENT; -ATTRIBUTE black_box OF mux41_1: COMPONENT IS true; -ATTRIBUTE noopt OF mux41_1: COMPONENT IS true; - -COMPONENT mux41_2 - PORT(S0 : IN STD_LOGIC; - D2 : IN STD_LOGIC; - S1 : IN STD_LOGIC; - D0 : IN STD_LOGIC; - INH : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q : OUT STD_LOGIC); -END COMPONENT; -ATTRIBUTE black_box OF mux41_2: COMPONENT IS true; -ATTRIBUTE noopt OF mux41_2: COMPONENT IS true; - -COMPONENT mux41_3 - PORT(S0 : IN STD_LOGIC; - D2 : IN STD_LOGIC; - S1 : IN STD_LOGIC; - D0 : IN STD_LOGIC; - INH : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q : OUT STD_LOGIC); -END COMPONENT; -ATTRIBUTE black_box OF mux41_3: COMPONENT IS true; -ATTRIBUTE noopt OF mux41_3: COMPONENT IS true; - -COMPONENT mux41_4 - PORT(S0 : IN STD_LOGIC; - D2 : IN STD_LOGIC; - S1 : IN STD_LOGIC; - D0 : IN STD_LOGIC; - INH : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q : OUT STD_LOGIC); -END COMPONENT; -ATTRIBUTE black_box OF mux41_4: COMPONENT IS true; -ATTRIBUTE noopt OF mux41_4: COMPONENT IS true; - -COMPONENT mux41_5 - PORT(S0 : IN STD_LOGIC; - D2 : IN STD_LOGIC; - S1 : IN STD_LOGIC; - D0 : IN STD_LOGIC; - INH : IN STD_LOGIC; - D1 : IN STD_LOGIC; - Q : OUT STD_LOGIC); -END COMPONENT; -ATTRIBUTE black_box OF mux41_5: COMPONENT IS true; -ATTRIBUTE noopt OF mux41_5: COMPONENT IS true; - -COMPONENT altdpram2 - PORT(wren_a : IN STD_LOGIC; - wren_b : IN STD_LOGIC; - clock_a : IN STD_LOGIC; - clock_b : IN STD_LOGIC; - address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT blitter - PORT(nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - BLITTER_ON : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - SR_BLITTER_DACK : IN STD_LOGIC; - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 DOWNTO 0); - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT ddr_ctr - PORT(nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - DDR_SYNC_66M : IN STD_LOGIC; - BLITTER_SIG : IN STD_LOGIC; - BLITTER_WR : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - CLK33M : IN STD_LOGIC; - CLR_FIFO : IN STD_LOGIC; - BLITTER_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - FIFO_MW : IN STD_LOGIC_VECTOR(8 DOWNTO 0); - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - nVWE : OUT STD_LOGIC; - nVRAS : OUT STD_LOGIC; - nVCS : OUT STD_LOGIC; - VCKE : OUT STD_LOGIC; - nVCAS : OUT STD_LOGIC; - SR_FIFO_WRE : OUT STD_LOGIC; - SR_DDR_FB : OUT STD_LOGIC; - SR_DDR_WR : OUT STD_LOGIC; - SR_DDRWR_D_SEL : OUT STD_LOGIC; - VIDEO_DDR_TA : OUT STD_LOGIC; - SR_BLITTER_DACK : OUT STD_LOGIC; - DDRWR_D_SEL1 : OUT STD_LOGIC; - BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - FB_LE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - FB_VDOE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - SR_VDMP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - VDM_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT altdpram1 - PORT(wren_a : IN STD_LOGIC; - wren_b : IN STD_LOGIC; - clock_a : IN STD_LOGIC; - clock_b : IN STD_LOGIC; - address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR(5 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR(5 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_fifo_dc0 - PORT(wrreq : IN STD_LOGIC; - wrclk : IN STD_LOGIC; - rdreq : IN STD_LOGIC; - rdclk : IN STD_LOGIC; - aclr : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - rdempty : OUT STD_LOGIC; - q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT altddio_bidir0 - PORT(oe : IN STD_LOGIC; - inclock : IN STD_LOGIC; - outclock : IN STD_LOGIC; - datain_h : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - padio : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - combout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dataout_h : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - dataout_l : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_ff4 - PORT(clock : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_muxvdm - PORT(data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data10x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data11x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data12x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data13x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data14x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data15x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data8x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data9x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux3 - PORT(data1 : IN STD_LOGIC; - data0 : IN STD_LOGIC; - sel : IN STD_LOGIC; - result : OUT STD_LOGIC - ); -END COMPONENT; - -COMPONENT lpm_bustri_long - PORT(enabledt : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - tridata : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_ff5 - PORT(clock : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_ff1 - PORT(clock : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_ff0 - PORT(clock : IN STD_LOGIC; - enable : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT altddio_out0 - PORT(outclock : IN STD_LOGIC; - datain_h : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - dataout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux0 - PORT(clock : IN STD_LOGIC; - data0x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux5 - PORT(data0x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_constant2 - PORT( result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux1 - PORT(clock : IN STD_LOGIC; - data0x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux2 - PORT(clock : IN STD_LOGIC; - data0x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data10x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data11x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data12x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data13x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data14x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data15x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data8x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - data9x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_shiftreg4 - PORT(clock : IN STD_LOGIC; - shiftin : IN STD_LOGIC; - shiftout : OUT STD_LOGIC - ); -END COMPONENT; - -COMPONENT lpm_latch0 - PORT(gate : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_ff6 - PORT(clock : IN STD_LOGIC; - enable : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_ff3 - PORT(clock : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT altddio_out2 - PORT(outclock : IN STD_LOGIC; - datain_h : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - datain_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - dataout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_bustri1 - PORT(enabledt : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - tridata : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_bustri_byt - PORT(enabledt : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - tridata : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_constant0 - PORT( result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_muxdz - PORT(clock : IN STD_LOGIC; - clken : IN STD_LOGIC; - sel : IN STD_LOGIC; - data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_fifodz - PORT(wrreq : IN STD_LOGIC; - rdreq : IN STD_LOGIC; - clock : IN STD_LOGIC; - aclr : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(127 DOWNTO 0); - q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_bustri3 - PORT(enabledt : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(5 DOWNTO 0); - tridata : INOUT STD_LOGIC_VECTOR(5 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux6 - PORT(clock : IN STD_LOGIC; - data0x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data2x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data3x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data4x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data5x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data6x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - data7x : IN STD_LOGIC_VECTOR(23 DOWNTO 0); - sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_constant1 - PORT( result : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_mux4 - PORT(sel : IN STD_LOGIC; - data0x : IN STD_LOGIC_VECTOR(6 DOWNTO 0); - data1x : IN STD_LOGIC_VECTOR(6 DOWNTO 0); - result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_constant3 - PORT( result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_shiftreg6 - PORT(clock : IN STD_LOGIC; - shiftin : IN STD_LOGIC; - q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT lpm_shiftreg0 - PORT(load : IN STD_LOGIC; - clock : IN STD_LOGIC; - shiftin : IN STD_LOGIC; - data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); - shiftout : OUT STD_LOGIC - ); -END COMPONENT; - -COMPONENT altdpram0 - PORT(wren_a : IN STD_LOGIC; - wren_b : IN STD_LOGIC; - clock_a : IN STD_LOGIC; - clock_b : IN STD_LOGIC; - address_a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - address_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - data_a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - data_b : IN STD_LOGIC_VECTOR(2 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - q_b : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) - ); -END COMPONENT; - -COMPONENT video_mod_mux_clutctr - PORT(nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - CLK33M : IN STD_LOGIC; - CLK25M : IN STD_LOGIC; - BLITTER_RUN : IN STD_LOGIC; - CLK_VIDEO : IN STD_LOGIC; - VR_BUSY : IN STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); - COLOR8 : OUT STD_LOGIC; - ACP_CLUT_RD : OUT STD_LOGIC; - COLOR1 : OUT STD_LOGIC; - FALCON_CLUT_RDH : OUT STD_LOGIC; - FALCON_CLUT_RDL : OUT STD_LOGIC; - ST_CLUT_RD : OUT STD_LOGIC; - HSYNC : OUT STD_LOGIC; - VSYNC : OUT STD_LOGIC; - nBLANK : OUT STD_LOGIC; - nSYNC : OUT STD_LOGIC; - nPD_VGA : OUT STD_LOGIC; - FIFO_RDE : OUT STD_LOGIC; - COLOR2 : OUT STD_LOGIC; - COLOR4 : OUT STD_LOGIC; - PIXEL_CLK : OUT STD_LOGIC; - BLITTER_ON : OUT STD_LOGIC; - VIDEO_MOD_TA : OUT STD_LOGIC; - INTER_ZEI : OUT STD_LOGIC; - DOP_FIFO_CLR : OUT STD_LOGIC; - VIDEO_RECONFIG : OUT STD_LOGIC; - VR_WR : OUT STD_LOGIC; - VR_RD : OUT STD_LOGIC; - CLR_FIFO : OUT STD_LOGIC; - ACP_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - BORDER_COLOR : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); - CCSEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - CLUT_MUX_ADR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - CLUT_OFF : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - FALCON_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - ST_CLUT_WR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - VIDEO_RAM_CTR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) - ); -END COMPONENT; - -SIGNAL ACP_CLUT_RD : STD_LOGIC; -SIGNAL ACP_CLUT_WR : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL BLITTER_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL BLITTER_DACK : STD_LOGIC_VECTOR(4 DOWNTO 0); -SIGNAL BLITTER_DIN : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL BLITTER_DOUT : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL BLITTER_ON : STD_LOGIC; -SIGNAL BLITTER_RUN : STD_LOGIC; -SIGNAL BLITTER_SIG : STD_LOGIC; -SIGNAL BLITTER_TA : STD_LOGIC; -SIGNAL BLITTER_WR : STD_LOGIC; -SIGNAL BORDER_COLOR : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL CC16 : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL CC24 : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL CCA : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL CCF : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL CCS : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL CCSEL : STD_LOGIC_VECTOR(2 DOWNTO 0); -SIGNAL CLR_FIFO : STD_LOGIC; -SIGNAL CLUT_ADR : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL CLUT_ADR1A : STD_LOGIC; -SIGNAL CLUT_ADR2A : STD_LOGIC; -SIGNAL CLUT_ADR3A : STD_LOGIC; -SIGNAL CLUT_ADR4A : STD_LOGIC; -SIGNAL CLUT_ADR5A : STD_LOGIC; -SIGNAL CLUT_ADR6A : STD_LOGIC; -SIGNAL CLUT_ADR7A : STD_LOGIC; -SIGNAL CLUT_MUX_ADR : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL CLUT_OFF : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL COLOR1 : STD_LOGIC; -SIGNAL COLOR2 : STD_LOGIC; -SIGNAL COLOR4 : STD_LOGIC; -SIGNAL COLOR8 : STD_LOGIC; -SIGNAL DDR_FB : STD_LOGIC_VECTOR(4 DOWNTO 0); -SIGNAL DDR_WR : STD_LOGIC; -SIGNAL DDRWR_D_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); -SIGNAL DOP_FIFO_CLR : STD_LOGIC; -SIGNAL FALCON_CLUT_RDH : STD_LOGIC; -SIGNAL FALCON_CLUT_RDL : STD_LOGIC; -SIGNAL FALCON_CLUT_WR : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL FB_DDR : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL FB_VDOE : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL FIFO_D : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0); -SIGNAL FIFO_RDE : STD_LOGIC; -SIGNAL FIFO_WRE : STD_LOGIC; -SIGNAL INTER_ZEI : STD_LOGIC; -SIGNAL nFB_BURST : STD_LOGIC; -SIGNAL PIXEL_CLK_ALTERA_SYNTHESIZED : STD_LOGIC; -SIGNAL SR_BLITTER_DACK : STD_LOGIC; -SIGNAL SR_DDR_FB : STD_LOGIC; -SIGNAL SR_DDR_WR : STD_LOGIC; -SIGNAL SR_DDRWR_D_SEL : STD_LOGIC; -SIGNAL SR_FIFO_WRE : STD_LOGIC; -SIGNAL SR_VDMP : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL ST_CLUT_RD : STD_LOGIC; -SIGNAL ST_CLUT_WR : STD_LOGIC_VECTOR(1 DOWNTO 0); -SIGNAL VDM_SEL : STD_LOGIC_VECTOR(3 DOWNTO 0); -SIGNAL VDMA : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL VDMB : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL VDMC : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL VDMP : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL VDOUT_OE : STD_LOGIC; -SIGNAL VDP_IN : STD_LOGIC_VECTOR(63 DOWNTO 0); -SIGNAL VDP_OUT : STD_LOGIC_VECTOR(63 DOWNTO 0); -SIGNAL VDR : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL VDVZ : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL VIDEO_DDR_TA : STD_LOGIC; -SIGNAL VIDEO_MOD_TA : STD_LOGIC; -SIGNAL VIDEO_RAM_CTR : STD_LOGIC_VECTOR(15 DOWNTO 0); -SIGNAL ZR_C8 : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL ZR_C8B : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_60 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_7 : STD_LOGIC_VECTOR(15 DOWNTO 0); -SIGNAL DFF_inst93 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_9 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_61 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_11 : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_23 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_24 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_25 : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_26 : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_62 : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_29 : STD_LOGIC_VECTOR(2 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_30 : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_31 : STD_LOGIC_VECTOR(2 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_32 : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_33 : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_34 : STD_LOGIC_VECTOR(2 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_63 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_36 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_38 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_40 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_41 : STD_LOGIC_VECTOR(5 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_42 : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_43 : STD_LOGIC_VECTOR(23 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_44 : STD_LOGIC_VECTOR(5 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_45 : STD_LOGIC_VECTOR(5 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_46 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_47 : STD_LOGIC_VECTOR(6 DOWNTO 0); -SIGNAL SYNTHESIZED_WIRE_48 : STD_LOGIC_VECTOR(31 DOWNTO 0); -SIGNAL DFF_inst91 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_64 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_49 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_50 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_51 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_52 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_53 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_54 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_55 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_56 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_57 : STD_LOGIC; -SIGNAL SYNTHESIZED_WIRE_65 : STD_LOGIC_VECTOR(23 DOWNTO 0); - -SIGNAL GDFX_TEMP_SIGNAL_16 : STD_LOGIC_VECTOR(7 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_6 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_5 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_4 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_3 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_2 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_1 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_15 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_14 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_13 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_12 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_11 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_10 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_9 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_8 : STD_LOGIC_VECTOR(127 DOWNTO 0); -SIGNAL GDFX_TEMP_SIGNAL_7 : STD_LOGIC_VECTOR(127 DOWNTO 0); - + ATTRIBUTE black_box : BOOLEAN; + ATTRIBUTE noopt : BOOLEAN; + + COMPONENT mux41_0 + PORT(S0 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic); + END COMPONENT; + + ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; + ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; + + COMPONENT mux41_1 + PORT(S0 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic); + END COMPONENT; + ATTRIBUTE black_box OF mux41_1: COMPONENT IS true; + ATTRIBUTE noopt OF mux41_1: COMPONENT IS true; + + COMPONENT mux41_2 + PORT(S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic); + END COMPONENT; + ATTRIBUTE black_box OF mux41_2: COMPONENT IS true; + ATTRIBUTE noopt OF mux41_2: COMPONENT IS true; + + COMPONENT mux41_3 + PORT(S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic); + END COMPONENT; + ATTRIBUTE black_box OF mux41_3: COMPONENT IS true; + ATTRIBUTE noopt OF mux41_3: COMPONENT IS true; + + COMPONENT mux41_4 + PORT(S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic); + END COMPONENT; + ATTRIBUTE black_box OF mux41_4: COMPONENT IS true; + ATTRIBUTE noopt OF mux41_4: COMPONENT IS true; + + COMPONENT mux41_5 + PORT(S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic); + END COMPONENT; + ATTRIBUTE black_box OF mux41_5: COMPONENT IS true; + ATTRIBUTE noopt OF mux41_5: COMPONENT IS true; + + COMPONENT altdpram2 + PORT(wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(7 DOWNTO 0); + address_b : IN std_logic_vector(7 DOWNTO 0); + data_a : IN std_logic_vector(7 DOWNTO 0); + data_b : IN std_logic_vector(7 DOWNTO 0); + q_a : OUT std_logic_vector(7 DOWNTO 0); + q_b : OUT std_logic_vector(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT blitter + PORT(nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + BLITTER_ON : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + DDRCLK0 : IN std_logic; + SR_BLITTER_DACK : IN std_logic; + BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); + BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + BLITTER_RUN : OUT std_logic; + BLITTER_SIG : OUT std_logic; + BLITTER_WR : OUT std_logic; + BLITTER_TA : OUT std_logic; + BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); + BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT ddr_ctr + PORT(nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + DDR_SYNC_66M : IN std_logic; + BLITTER_SIG : IN std_logic; + BLITTER_WR : IN std_logic; + DDRCLK0 : IN std_logic; + CLK33M : IN std_logic; + CLR_FIFO : IN std_logic; + BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + FIFO_MW : IN std_logic_vector(8 DOWNTO 0); + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + nVWE : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + VCKE : OUT std_logic; + nVCAS : OUT std_logic; + SR_FIFO_WRE : OUT std_logic; + SR_DDR_FB : OUT std_logic; + SR_DDR_WR : OUT std_logic; + SR_DDRWR_D_SEL : OUT std_logic; + VIDEO_DDR_TA : OUT std_logic; + SR_BLITTER_DACK : OUT std_logic; + DDRWR_D_SEL1 : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + FB_LE : OUT std_logic_vector(3 DOWNTO 0); + FB_VDOE : OUT std_logic_vector(3 DOWNTO 0); + SR_VDMP : OUT std_logic_vector(7 DOWNTO 0); + VA : OUT std_logic_vector(12 DOWNTO 0); + VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT altdpram1 + PORT(wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(7 DOWNTO 0); + address_b : IN std_logic_vector(7 DOWNTO 0); + data_a : IN std_logic_vector(5 DOWNTO 0); + data_b : IN std_logic_vector(5 DOWNTO 0); + q_a : OUT std_logic_vector(5 DOWNTO 0); + q_b : OUT std_logic_vector(5 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_fifo_dc0 + PORT(wrreq : IN std_logic; + wrclk : IN std_logic; + rdreq : IN std_logic; + rdclk : IN std_logic; + aclr : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + rdempty : OUT std_logic; + q : OUT std_logic_vector(127 DOWNTO 0); + wrusedw : OUT std_logic_vector(8 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT altddio_bidir0 + PORT(oe : IN std_logic; + inclock : IN std_logic; + outclock : IN std_logic; + datain_h : IN std_logic_vector(31 DOWNTO 0); + datain_l : IN std_logic_vector(31 DOWNTO 0); + padio : INOUT std_logic_vector(31 DOWNTO 0); + combout : OUT std_logic_vector(31 DOWNTO 0); + dataout_h : OUT std_logic_vector(31 DOWNTO 0); + dataout_l : OUT std_logic_vector(31 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_ff4 + PORT(clock : IN std_logic; + data : IN std_logic_vector(15 DOWNTO 0); + q : OUT std_logic_vector(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_muxvdm + PORT(data0x : IN std_logic_vector(127 DOWNTO 0); + data10x : IN std_logic_vector(127 DOWNTO 0); + data11x : IN std_logic_vector(127 DOWNTO 0); + data12x : IN std_logic_vector(127 DOWNTO 0); + data13x : IN std_logic_vector(127 DOWNTO 0); + data14x : IN std_logic_vector(127 DOWNTO 0); + data15x : IN std_logic_vector(127 DOWNTO 0); + data1x : IN std_logic_vector(127 DOWNTO 0); + data2x : IN std_logic_vector(127 DOWNTO 0); + data3x : IN std_logic_vector(127 DOWNTO 0); + data4x : IN std_logic_vector(127 DOWNTO 0); + data5x : IN std_logic_vector(127 DOWNTO 0); + data6x : IN std_logic_vector(127 DOWNTO 0); + data7x : IN std_logic_vector(127 DOWNTO 0); + data8x : IN std_logic_vector(127 DOWNTO 0); + data9x : IN std_logic_vector(127 DOWNTO 0); + sel : IN std_logic_vector(3 DOWNTO 0); + result : OUT std_logic_vector(127 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux3 + PORT(data1 : IN std_logic; + data0 : IN std_logic; + sel : IN std_logic; + result : OUT std_logic + ); + END COMPONENT; + + COMPONENT lpm_bustri_long + PORT(enabledt : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + tridata : INOUT std_logic_vector(31 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_ff5 + PORT(clock : IN std_logic; + data : IN std_logic_vector(7 DOWNTO 0); + q : OUT std_logic_vector(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_ff1 + PORT(clock : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_ff0 + PORT(clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT altddio_out0 + PORT(outclock : IN std_logic; + datain_h : IN std_logic_vector(3 DOWNTO 0); + datain_l : IN std_logic_vector(3 DOWNTO 0); + dataout : OUT std_logic_vector(3 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux0 + PORT(clock : IN std_logic; + data0x : IN std_logic_vector(31 DOWNTO 0); + data1x : IN std_logic_vector(31 DOWNTO 0); + data2x : IN std_logic_vector(31 DOWNTO 0); + data3x : IN std_logic_vector(31 DOWNTO 0); + sel : IN std_logic_vector(1 DOWNTO 0); + result : OUT std_logic_vector(31 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux5 + PORT(data0x : IN std_logic_vector(63 DOWNTO 0); + data1x : IN std_logic_vector(63 DOWNTO 0); + data2x : IN std_logic_vector(63 DOWNTO 0); + data3x : IN std_logic_vector(63 DOWNTO 0); + sel : IN std_logic_vector(1 DOWNTO 0); + result : OUT std_logic_vector(63 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_constant2 + PORT( result : OUT std_logic_vector(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux1 + PORT(clock : IN std_logic; + data0x : IN std_logic_vector(15 DOWNTO 0); + data1x : IN std_logic_vector(15 DOWNTO 0); + data2x : IN std_logic_vector(15 DOWNTO 0); + data3x : IN std_logic_vector(15 DOWNTO 0); + data4x : IN std_logic_vector(15 DOWNTO 0); + data5x : IN std_logic_vector(15 DOWNTO 0); + data6x : IN std_logic_vector(15 DOWNTO 0); + data7x : IN std_logic_vector(15 DOWNTO 0); + sel : IN std_logic_vector(2 DOWNTO 0); + result : OUT std_logic_vector(15 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux2 + PORT(clock : IN std_logic; + data0x : IN std_logic_vector(7 DOWNTO 0); + data10x : IN std_logic_vector(7 DOWNTO 0); + data11x : IN std_logic_vector(7 DOWNTO 0); + data12x : IN std_logic_vector(7 DOWNTO 0); + data13x : IN std_logic_vector(7 DOWNTO 0); + data14x : IN std_logic_vector(7 DOWNTO 0); + data15x : IN std_logic_vector(7 DOWNTO 0); + data1x : IN std_logic_vector(7 DOWNTO 0); + data2x : IN std_logic_vector(7 DOWNTO 0); + data3x : IN std_logic_vector(7 DOWNTO 0); + data4x : IN std_logic_vector(7 DOWNTO 0); + data5x : IN std_logic_vector(7 DOWNTO 0); + data6x : IN std_logic_vector(7 DOWNTO 0); + data7x : IN std_logic_vector(7 DOWNTO 0); + data8x : IN std_logic_vector(7 DOWNTO 0); + data9x : IN std_logic_vector(7 DOWNTO 0); + sel : IN std_logic_vector(3 DOWNTO 0); + result : OUT std_logic_vector(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_shiftreg4 + PORT(clock : IN std_logic; + shiftin : IN std_logic; + shiftout : OUT std_logic + ); + END COMPONENT; + + COMPONENT lpm_latch0 + PORT(gate : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_ff6 + PORT(clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + q : OUT std_logic_vector(127 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_ff3 + PORT(clock : IN std_logic; + data : IN std_logic_vector(23 DOWNTO 0); + q : OUT std_logic_vector(23 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT altddio_out2 + PORT(outclock : IN std_logic; + datain_h : IN std_logic_vector(23 DOWNTO 0); + datain_l : IN std_logic_vector(23 DOWNTO 0); + dataout : OUT std_logic_vector(23 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_bustri1 + PORT(enabledt : IN std_logic; + data : IN std_logic_vector(2 DOWNTO 0); + tridata : INOUT std_logic_vector(2 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_bustri_byt + PORT(enabledt : IN std_logic; + data : IN std_logic_vector(7 DOWNTO 0); + tridata : INOUT std_logic_vector(7 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_constant0 + PORT( result : OUT std_logic_vector(4 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_muxdz + PORT(clock : IN std_logic; + clken : IN std_logic; + sel : IN std_logic; + data0x : IN std_logic_vector(127 DOWNTO 0); + data1x : IN std_logic_vector(127 DOWNTO 0); + result : OUT std_logic_vector(127 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_fifodz + PORT(wrreq : IN std_logic; + rdreq : IN std_logic; + clock : IN std_logic; + aclr : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + q : OUT std_logic_vector(127 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_bustri3 + PORT(enabledt : IN std_logic; + data : IN std_logic_vector(5 DOWNTO 0); + tridata : INOUT std_logic_vector(5 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux6 + PORT(clock : IN std_logic; + data0x : IN std_logic_vector(23 DOWNTO 0); + data1x : IN std_logic_vector(23 DOWNTO 0); + data2x : IN std_logic_vector(23 DOWNTO 0); + data3x : IN std_logic_vector(23 DOWNTO 0); + data4x : IN std_logic_vector(23 DOWNTO 0); + data5x : IN std_logic_vector(23 DOWNTO 0); + data6x : IN std_logic_vector(23 DOWNTO 0); + data7x : IN std_logic_vector(23 DOWNTO 0); + sel : IN std_logic_vector(2 DOWNTO 0); + result : OUT std_logic_vector(23 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_constant1 + PORT( result : OUT std_logic_vector(1 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_mux4 + PORT(sel : IN std_logic; + data0x : IN std_logic_vector(6 DOWNTO 0); + data1x : IN std_logic_vector(6 DOWNTO 0); + result : OUT std_logic_vector(6 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_constant3 + PORT( result : OUT std_logic_vector(6 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_shiftreg6 + PORT(clock : IN std_logic; + shiftin : IN std_logic; + q : OUT std_logic_vector(4 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT lpm_shiftreg0 + PORT(load : IN std_logic; + clock : IN std_logic; + shiftin : IN std_logic; + data : IN std_logic_vector(15 DOWNTO 0); + shiftout : OUT std_logic + ); + END COMPONENT; + + COMPONENT altdpram0 + PORT(wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(3 DOWNTO 0); + address_b : IN std_logic_vector(3 DOWNTO 0); + data_a : IN std_logic_vector(2 DOWNTO 0); + data_b : IN std_logic_vector(2 DOWNTO 0); + q_a : OUT std_logic_vector(2 DOWNTO 0); + q_b : OUT std_logic_vector(2 DOWNTO 0) + ); + END COMPONENT; + + COMPONENT video_mod_mux_clutctr + PORT(nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + CLK33M : IN std_logic; + CLK25M : IN std_logic; + BLITTER_RUN : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_BUSY : IN std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VR_D : IN std_logic_vector(8 DOWNTO 0); + COLOR8 : OUT std_logic; + ACP_CLUT_RD : OUT std_logic; + COLOR1 : OUT std_logic; + FALCON_CLUT_RDH : OUT std_logic; + FALCON_CLUT_RDL : OUT std_logic; + ST_CLUT_RD : OUT std_logic; + HSYNC : OUT std_logic; + VSYNC : OUT std_logic; + nBLANK : OUT std_logic; + nSYNC : OUT std_logic; + nPD_VGA : OUT std_logic; + FIFO_RDE : OUT std_logic; + COLOR2 : OUT std_logic; + COLOR4 : OUT std_logic; + PIXEL_CLK : OUT std_logic; + BLITTER_ON : OUT std_logic; + VIDEO_MOD_TA : OUT std_logic; + INTER_ZEI : OUT std_logic; + DOP_FIFO_CLR : OUT std_logic; + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + VR_RD : OUT std_logic; + CLR_FIFO : OUT std_logic; + ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); + CCSEL : OUT std_logic_vector(2 DOWNTO 0); + CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); + CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); + FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); + VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0) + ); + END COMPONENT; + + SIGNAL ACP_CLUT_RD : std_logic; + SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); + SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); + SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_ON : std_logic; + SIGNAL BLITTER_RUN : std_logic; + SIGNAL BLITTER_SIG : std_logic; + SIGNAL BLITTER_TA : std_logic; + SIGNAL BLITTER_WR : std_logic; + SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); + SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); + SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); + SIGNAL CCA : std_logic_vector(23 DOWNTO 0); + SIGNAL CCF : std_logic_vector(23 DOWNTO 0); + SIGNAL CCS : std_logic_vector(23 DOWNTO 0); + SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); + SIGNAL CLUT_ADR1A : std_logic; + SIGNAL CLUT_ADR2A : std_logic; + SIGNAL CLUT_ADR3A : std_logic; + SIGNAL CLUT_ADR4A : std_logic; + SIGNAL CLUT_ADR5A : std_logic; + SIGNAL CLUT_ADR6A : std_logic; + SIGNAL CLUT_ADR7A : std_logic; + SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); + SIGNAL COLOR1 : std_logic; + SIGNAL COLOR2 : std_logic; + SIGNAL COLOR4 : std_logic; + SIGNAL COLOR8 : std_logic; + SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); + SIGNAL DDR_WR : std_logic; + SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); + SIGNAL DOP_FIFO_CLR : std_logic; + SIGNAL FALCON_CLUT_RDH : std_logic; + SIGNAL FALCON_CLUT_RDL : std_logic; + SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); + SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); + SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); + SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); + SIGNAL FIFO_RDE : std_logic; + SIGNAL FIFO_WRE : std_logic; + SIGNAL INTER_ZEI : std_logic; + SIGNAL nFB_BURST : std_logic; + SIGNAL PIXEL_CLK_ALTERA_SYNTHESIZED : std_logic; + SIGNAL SR_BLITTER_DACK : std_logic; + SIGNAL SR_DDR_FB : std_logic; + SIGNAL SR_DDR_WR : std_logic; + SIGNAL SR_DDRWR_D_SEL : std_logic; + SIGNAL SR_FIFO_WRE : std_logic; + SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL ST_CLUT_RD : std_logic; + SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); + SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); + SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL VDOUT_OE : std_logic; + SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); + SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); + SIGNAL VDR : std_logic_vector(31 DOWNTO 0); + SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); + SIGNAL VIDEO_DDR_TA : std_logic; + SIGNAL VIDEO_MOD_TA : std_logic; + SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); + SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); + SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_0 : std_logic; + SIGNAL SYNTHESIZED_WIRE_1 : std_logic; + SIGNAL SYNTHESIZED_WIRE_2 : std_logic; + SIGNAL SYNTHESIZED_WIRE_3 : std_logic; + SIGNAL SYNTHESIZED_WIRE_4 : std_logic; + SIGNAL SYNTHESIZED_WIRE_5 : std_logic; + SIGNAL SYNTHESIZED_WIRE_60 : std_logic; + SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); + SIGNAL DFF_inst93 : std_logic; + SIGNAL SYNTHESIZED_WIRE_8 : std_logic; + SIGNAL SYNTHESIZED_WIRE_9 : std_logic; + SIGNAL SYNTHESIZED_WIRE_61 : std_logic; + SIGNAL SYNTHESIZED_WIRE_11 : std_logic_vector(31 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_12 : std_logic_vector(7 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_13 : std_logic_vector(31 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_14 : std_logic_vector(31 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_15 : std_logic_vector(31 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_16 : std_logic; + SIGNAL SYNTHESIZED_WIRE_18 : std_logic; + SIGNAL SYNTHESIZED_WIRE_19 : std_logic; + SIGNAL SYNTHESIZED_WIRE_20 : std_logic; + SIGNAL SYNTHESIZED_WIRE_21 : std_logic; + SIGNAL SYNTHESIZED_WIRE_22 : std_logic; + SIGNAL SYNTHESIZED_WIRE_23 : std_logic; + SIGNAL SYNTHESIZED_WIRE_24 : std_logic; + SIGNAL SYNTHESIZED_WIRE_25 : std_logic_vector(23 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_26 : std_logic_vector(23 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_62 : std_logic_vector(23 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_29 : std_logic_vector(2 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_30 : std_logic_vector(7 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_31 : std_logic_vector(2 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_32 : std_logic_vector(7 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_33 : std_logic_vector(7 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_34 : std_logic_vector(2 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_63 : std_logic_vector(127 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_36 : std_logic_vector(127 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_38 : std_logic; + SIGNAL SYNTHESIZED_WIRE_40 : std_logic; + SIGNAL SYNTHESIZED_WIRE_41 : std_logic_vector(5 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_42 : std_logic_vector(23 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_43 : std_logic_vector(23 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_44 : std_logic_vector(5 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_45 : std_logic_vector(5 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_46 : std_logic; + SIGNAL SYNTHESIZED_WIRE_47 : std_logic_vector(6 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_48 : std_logic_vector(31 DOWNTO 0); + SIGNAL DFF_inst91 : std_logic; + SIGNAL SYNTHESIZED_WIRE_64 : std_logic; + SIGNAL SYNTHESIZED_WIRE_49 : std_logic; + SIGNAL SYNTHESIZED_WIRE_50 : std_logic; + SIGNAL SYNTHESIZED_WIRE_51 : std_logic; + SIGNAL SYNTHESIZED_WIRE_52 : std_logic; + SIGNAL SYNTHESIZED_WIRE_53 : std_logic; + SIGNAL SYNTHESIZED_WIRE_54 : std_logic; + SIGNAL SYNTHESIZED_WIRE_55 : std_logic; + SIGNAL SYNTHESIZED_WIRE_56 : std_logic; + SIGNAL SYNTHESIZED_WIRE_57 : std_logic; + SIGNAL SYNTHESIZED_WIRE_65 : std_logic_vector(23 DOWNTO 0); + + SIGNAL GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); + BEGIN -VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); -VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); -VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); -SYNTHESIZED_WIRE_0 <= '0'; -SYNTHESIZED_WIRE_1 <= '0'; -SYNTHESIZED_WIRE_2 <= '0'; -SYNTHESIZED_WIRE_3 <= '0'; -SYNTHESIZED_WIRE_4 <= '0'; -SYNTHESIZED_WIRE_5 <= '0'; -SYNTHESIZED_WIRE_19 <= '0'; -SYNTHESIZED_WIRE_20 <= '0'; -SYNTHESIZED_WIRE_21 <= '0'; -SYNTHESIZED_WIRE_22 <= '0'; -SYNTHESIZED_WIRE_23 <= '0'; -SYNTHESIZED_WIRE_24 <= '0'; -SYNTHESIZED_WIRE_55 <= '0'; -SYNTHESIZED_WIRE_56 <= '0'; -SYNTHESIZED_WIRE_57 <= '0'; - -CC16(18) <= GDFX_TEMP_SIGNAL_16(7); -CC16(17) <= GDFX_TEMP_SIGNAL_16(6); -CC16(16) <= GDFX_TEMP_SIGNAL_16(5); -CC16(9) <= GDFX_TEMP_SIGNAL_16(4); -CC16(8) <= GDFX_TEMP_SIGNAL_16(3); -CC16(2) <= GDFX_TEMP_SIGNAL_16(2); -CC16(1) <= GDFX_TEMP_SIGNAL_16(1); -CC16(0) <= GDFX_TEMP_SIGNAL_16(0); - -CC16(23) <= GDFX_TEMP_SIGNAL_0(15); -CC16(22) <= GDFX_TEMP_SIGNAL_0(14); -CC16(21) <= GDFX_TEMP_SIGNAL_0(13); -CC16(20) <= GDFX_TEMP_SIGNAL_0(12); -CC16(19) <= GDFX_TEMP_SIGNAL_0(11); -CC16(15) <= GDFX_TEMP_SIGNAL_0(10); -CC16(14) <= GDFX_TEMP_SIGNAL_0(9); -CC16(13) <= GDFX_TEMP_SIGNAL_0(8); -CC16(12) <= GDFX_TEMP_SIGNAL_0(7); -CC16(11) <= GDFX_TEMP_SIGNAL_0(6); -CC16(10) <= GDFX_TEMP_SIGNAL_0(5); -CC16(7) <= GDFX_TEMP_SIGNAL_0(4); -CC16(6) <= GDFX_TEMP_SIGNAL_0(3); -CC16(5) <= GDFX_TEMP_SIGNAL_0(2); -CC16(4) <= GDFX_TEMP_SIGNAL_0(1); -CC16(3) <= GDFX_TEMP_SIGNAL_0(0); - -GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); -GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); -GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); -GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); -GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); -GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); -GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); -GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); -GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); -GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80)); -GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88)); -GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96)); -GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); -GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); -GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); - - -b2v_ACP_CLUT_RAM : altdpram2 -PORT MAP(wren_a => ACP_CLUT_WR(3), - wren_b => SYNTHESIZED_WIRE_0, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(7 DOWNTO 0), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_30, - q_b => CCA(7 DOWNTO 0)); - - -b2v_ACP_CLUT_RAM54 : altdpram2 -PORT MAP(wren_a => ACP_CLUT_WR(2), - wren_b => SYNTHESIZED_WIRE_1, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(15 DOWNTO 8), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_32, - q_b => CCA(15 DOWNTO 8)); - - -b2v_ACP_CLUT_RAM55 : altdpram2 -PORT MAP(wren_a => ACP_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_2, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(23 DOWNTO 16), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_33, - q_b => CCA(23 DOWNTO 16)); - - -b2v_BLITTER : blitter -PORT MAP(nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - FB_ALE => FB_ALE, - nFB_WR => nFB_WR, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - BLITTER_ON => BLITTER_ON, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - DDRCLK0 => DDRCLK(0), - SR_BLITTER_DACK => SR_BLITTER_DACK, - BLITTER_DACK => BLITTER_DACK, - BLITTER_DIN => BLITTER_DIN, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - BLITTER_RUN => BLITTER_RUN, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - BLITTER_TA => BLITTER_TA, - BLITTER_ADR => BLITTER_ADR, - BLITTER_DOUT => BLITTER_DOUT); - - -b2v_DDR_CTR : ddr_ctr -PORT MAP(nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - FB_ALE => FB_ALE, - nFB_WR => nFB_WR, - DDR_SYNC_66M => DDR_SYNC_66M, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - DDRCLK0 => DDRCLK(0), - CLK33M => CLK33M, - CLR_FIFO => CLR_FIFO, - BLITTER_ADR => BLITTER_ADR, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - FIFO_MW => FIFO_MW, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - nVWE => nVWE, - nVRAS => nVRAS, - nVCS => nVCS, - VCKE => VCKE, - nVCAS => nVCAS, - SR_FIFO_WRE => SR_FIFO_WRE, - SR_DDR_FB => SR_DDR_FB, - SR_DDR_WR => SR_DDR_WR, - SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, - VIDEO_DDR_TA => VIDEO_DDR_TA, - SR_BLITTER_DACK => SR_BLITTER_DACK, - DDRWR_D_SEL1 => DDRWR_D_SEL(1), - BA => BA, - FB_LE => FB_LE, - FB_VDOE => FB_VDOE, - SR_VDMP => SR_VDMP, - VA => VA, - VDM_SEL => VDM_SEL); - - -b2v_FALCON_CLUT_BLUE : altdpram1 -PORT MAP(wren_a => FALCON_CLUT_WR(3), - wren_b => SYNTHESIZED_WIRE_3, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_45, - q_b => CCF(7 DOWNTO 2)); - - -b2v_FALCON_CLUT_GREEN : altdpram1 -PORT MAP(wren_a => FALCON_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_4, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_44, - q_b => CCF(15 DOWNTO 10)); - - -b2v_FALCON_CLUT_RED : altdpram1 -PORT MAP(wren_a => FALCON_CLUT_WR(0), - wren_b => SYNTHESIZED_WIRE_5, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(31 DOWNTO 26), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_41, - q_b => CCF(23 DOWNTO 18)); - - -b2v_inst : lpm_fifo_dc0 -PORT MAP(wrreq => FIFO_WRE, - wrclk => DDRCLK(0), - rdreq => SYNTHESIZED_WIRE_60, - rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, - aclr => CLR_FIFO, - data => VDMC, - q => SYNTHESIZED_WIRE_63, - wrusedw => FIFO_MW); - - -b2v_inst1 : altddio_bidir0 -PORT MAP(oe => VDOUT_OE, - inclock => DDRCLK(1), - outclock => DDRCLK(3), - datain_h => VDP_OUT(63 DOWNTO 32), - datain_l => VDP_OUT(31 DOWNTO 0), - padio => VD, - combout => SYNTHESIZED_WIRE_15, - dataout_h => VDP_IN(31 DOWNTO 0), - dataout_l => VDP_IN(63 DOWNTO 32)); - - -b2v_inst10 : lpm_ff4 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_7, - q => GDFX_TEMP_SIGNAL_0); - - -b2v_inst100 : lpm_muxvdm -PORT MAP(data0x => VDMB, - data10x => GDFX_TEMP_SIGNAL_1, - data11x => GDFX_TEMP_SIGNAL_2, - data12x => GDFX_TEMP_SIGNAL_3, - data13x => GDFX_TEMP_SIGNAL_4, - data14x => GDFX_TEMP_SIGNAL_5, - data15x => GDFX_TEMP_SIGNAL_6, - data1x => GDFX_TEMP_SIGNAL_7, - data2x => GDFX_TEMP_SIGNAL_8, - data3x => GDFX_TEMP_SIGNAL_9, - data4x => GDFX_TEMP_SIGNAL_10, - data5x => GDFX_TEMP_SIGNAL_11, - data6x => GDFX_TEMP_SIGNAL_12, - data7x => GDFX_TEMP_SIGNAL_13, - data8x => GDFX_TEMP_SIGNAL_14, - data9x => GDFX_TEMP_SIGNAL_15, - sel => VDM_SEL, - result => VDMC); - - -b2v_inst102 : lpm_mux3 -PORT MAP(data1 => DFF_inst93, - data0 => ZR_C8(0), - sel => COLOR1, - result => ZR_C8B(0)); - - -CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; - - -CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; - - -SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; - - -CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; - - -SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; - - -b2v_inst108 : lpm_bustri_long -PORT MAP(enabledt => FB_VDOE(0), - data => VDR, - tridata => FB_AD); - - -b2v_inst109 : lpm_bustri_long -PORT MAP(enabledt => FB_VDOE(1), - data => SYNTHESIZED_WIRE_11, - tridata => FB_AD); - - -b2v_inst11 : lpm_ff5 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_12, - q => ZR_C8); - - -b2v_inst110 : lpm_bustri_long -PORT MAP(enabledt => FB_VDOE(2), - data => SYNTHESIZED_WIRE_13, - tridata => FB_AD); - - -b2v_inst119 : lpm_bustri_long -PORT MAP(enabledt => FB_VDOE(3), - data => SYNTHESIZED_WIRE_14, - tridata => FB_AD); - - -b2v_inst12 : lpm_ff1 -PORT MAP(clock => DDRCLK(0), - data => VDP_IN(31 DOWNTO 0), - q => VDVZ(31 DOWNTO 0)); - - -b2v_inst13 : lpm_ff0 -PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(0), - data => FB_AD, - q => FB_DDR(127 DOWNTO 96)); - - -b2v_inst14 : lpm_ff0 -PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(1), - data => FB_AD, - q => FB_DDR(95 DOWNTO 64)); - - -b2v_inst15 : lpm_ff0 -PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(2), - data => FB_AD, - q => FB_DDR(63 DOWNTO 32)); - - -b2v_inst16 : lpm_ff0 -PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(3), - data => FB_AD, - q => FB_DDR(31 DOWNTO 0)); - - -b2v_inst17 : lpm_ff0 -PORT MAP(clock => DDRCLK(0), - enable => DDR_FB(1), - data => VDP_IN(31 DOWNTO 0), - q => SYNTHESIZED_WIRE_11); - - -b2v_inst18 : lpm_ff0 -PORT MAP(clock => DDRCLK(0), - enable => DDR_FB(0), - data => VDP_IN(63 DOWNTO 32), - q => SYNTHESIZED_WIRE_13); - - -b2v_inst19 : lpm_ff0 -PORT MAP(clock => DDRCLK(0), - enable => DDR_FB(0), - data => VDP_IN(31 DOWNTO 0), - q => SYNTHESIZED_WIRE_14); - - -b2v_inst2 : altddio_out0 -PORT MAP(outclock => DDRCLK(3), - datain_h => VDMP(7 DOWNTO 4), - datain_l => VDMP(3 DOWNTO 0), - dataout => VDM); - - -b2v_inst20 : lpm_ff1 -PORT MAP(clock => DDRCLK(0), - data => VDVZ(31 DOWNTO 0), - q => VDVZ(95 DOWNTO 64)); - - -b2v_inst21 : lpm_mux0 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => FIFO_D(127 DOWNTO 96), - data1x => FIFO_D(95 DOWNTO 64), - data2x => FIFO_D(63 DOWNTO 32), - data3x => FIFO_D(31 DOWNTO 0), - sel => CLUT_MUX_ADR(1 DOWNTO 0), - result => SYNTHESIZED_WIRE_48); - - -b2v_inst22 : lpm_mux5 -PORT MAP(data0x => FB_DDR(127 DOWNTO 64), - data1x => FB_DDR(63 DOWNTO 0), - data2x => BLITTER_DOUT(127 DOWNTO 64), - data3x => BLITTER_DOUT(63 DOWNTO 0), - sel => DDRWR_D_SEL, - result => VDP_OUT); - - -b2v_inst23 : lpm_constant2 -PORT MAP( result => GDFX_TEMP_SIGNAL_16); - - -b2v_inst24 : lpm_mux1 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => FIFO_D(127 DOWNTO 112), - data1x => FIFO_D(111 DOWNTO 96), - data2x => FIFO_D(95 DOWNTO 80), - data3x => FIFO_D(79 DOWNTO 64), - data4x => FIFO_D(63 DOWNTO 48), - data5x => FIFO_D(47 DOWNTO 32), - data6x => FIFO_D(31 DOWNTO 16), - data7x => FIFO_D(15 DOWNTO 0), - sel => CLUT_MUX_ADR(2 DOWNTO 0), - result => SYNTHESIZED_WIRE_7); - - -b2v_inst25 : lpm_mux2 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => FIFO_D(127 DOWNTO 120), - data10x => FIFO_D(47 DOWNTO 40), - data11x => FIFO_D(39 DOWNTO 32), - data12x => FIFO_D(31 DOWNTO 24), - data13x => FIFO_D(23 DOWNTO 16), - data14x => FIFO_D(15 DOWNTO 8), - data15x => FIFO_D(7 DOWNTO 0), - data1x => FIFO_D(119 DOWNTO 112), - data2x => FIFO_D(111 DOWNTO 104), - data3x => FIFO_D(103 DOWNTO 96), - data4x => FIFO_D(95 DOWNTO 88), - data5x => FIFO_D(87 DOWNTO 80), - data6x => FIFO_D(79 DOWNTO 72), - data7x => FIFO_D(71 DOWNTO 64), - data8x => FIFO_D(63 DOWNTO 56), - data9x => FIFO_D(55 DOWNTO 48), - sel => CLUT_MUX_ADR, - result => SYNTHESIZED_WIRE_12); - - -b2v_inst26 : lpm_shiftreg4 -PORT MAP(clock => DDRCLK(0), - shiftin => SR_FIFO_WRE, - shiftout => FIFO_WRE); - - -b2v_inst27 : lpm_latch0 -PORT MAP(gate => DDR_SYNC_66M, - data => SYNTHESIZED_WIRE_15, - q => VDR); - - - -CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; - - -b2v_inst3 : lpm_ff1 -PORT MAP(clock => DDRCLK(0), - data => VDP_IN(63 DOWNTO 32), - q => VDVZ(63 DOWNTO 32)); - - -CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; - - -CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; - - -SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; - - -SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; - - -SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; - - -SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; - - -b2v_inst36 : lpm_ff6 -PORT MAP(clock => DDRCLK(0), - enable => BLITTER_DACK(0), - data => VDVZ, - q => BLITTER_DIN); - - -VDOUT_OE <= DDR_WR OR SR_DDR_WR; - - - -VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA; - - -b2v_inst4 : lpm_ff1 -PORT MAP(clock => DDRCLK(0), - data => VDVZ(63 DOWNTO 32), - q => VDVZ(127 DOWNTO 96)); - - -b2v_inst40 : mux41_0 -PORT MAP(S0 => COLOR2, - S1 => COLOR4, - D0 => CLUT_ADR6A, - INH => SYNTHESIZED_WIRE_19, - D1 => CLUT_ADR7A, - Q => SYNTHESIZED_WIRE_54); - - -b2v_inst41 : mux41_1 -PORT MAP(S0 => COLOR2, - S1 => COLOR4, - D0 => CLUT_ADR5A, - INH => SYNTHESIZED_WIRE_20, - D1 => CLUT_ADR6A, - Q => SYNTHESIZED_WIRE_53); - - -b2v_inst42 : mux41_2 -PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR7A, - S1 => COLOR4, - D0 => CLUT_ADR4A, - INH => SYNTHESIZED_WIRE_21, - D1 => CLUT_ADR5A, - Q => SYNTHESIZED_WIRE_52); - - -b2v_inst43 : mux41_3 -PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR6A, - S1 => COLOR4, - D0 => CLUT_ADR3A, - INH => SYNTHESIZED_WIRE_22, - D1 => CLUT_ADR4A, - Q => SYNTHESIZED_WIRE_51); - - -b2v_inst44 : mux41_4 -PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR5A, - S1 => COLOR4, - D0 => CLUT_ADR2A, - INH => SYNTHESIZED_WIRE_23, - D1 => CLUT_ADR3A, - Q => SYNTHESIZED_WIRE_50); - - -b2v_inst45 : mux41_5 -PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR4A, - S1 => COLOR4, - D0 => CLUT_ADR1A, - INH => SYNTHESIZED_WIRE_24, - D1 => CLUT_ADR2A, - Q => SYNTHESIZED_WIRE_49); - - -b2v_inst46 : lpm_ff3 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_25, - q => SYNTHESIZED_WIRE_43); - - -b2v_inst47 : lpm_ff3 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => CCF, - q => SYNTHESIZED_WIRE_25); - - - -b2v_inst49 : lpm_ff3 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_26, - q => SYNTHESIZED_WIRE_42); - - -b2v_inst5 : altddio_out2 -PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, - datain_h => SYNTHESIZED_WIRE_62, - datain_l => SYNTHESIZED_WIRE_62, - dataout => SYNTHESIZED_WIRE_65); - - - -b2v_inst51 : lpm_bustri1 -PORT MAP(enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_29, - tridata => FB_AD(26 DOWNTO 24)); - - -b2v_inst52 : lpm_ff3 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => CCS, - q => SYNTHESIZED_WIRE_26); - - -b2v_inst53 : lpm_bustri_byt -PORT MAP(enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_30, - tridata => FB_AD(7 DOWNTO 0)); - - -b2v_inst54 : lpm_constant0 -PORT MAP( result => CCS(20 DOWNTO 16)); - - - -b2v_inst56 : lpm_bustri1 -PORT MAP(enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_31, - tridata => FB_AD(22 DOWNTO 20)); - - -b2v_inst57 : lpm_bustri_byt -PORT MAP(enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_32, - tridata => FB_AD(15 DOWNTO 8)); - - -b2v_inst58 : lpm_bustri_byt -PORT MAP(enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_33, - tridata => FB_AD(23 DOWNTO 16)); - - -b2v_inst59 : lpm_constant0 -PORT MAP( result => CCS(12 DOWNTO 8)); - - - - -b2v_inst61 : lpm_bustri1 -PORT MAP(enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_34, - tridata => FB_AD(18 DOWNTO 16)); - - -b2v_inst62 : lpm_muxdz -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - clken => FIFO_RDE, - sel => INTER_ZEI, - data0x => SYNTHESIZED_WIRE_63, - data1x => SYNTHESIZED_WIRE_36, - result => FIFO_D); - - -b2v_inst63 : lpm_fifodz -PORT MAP(wrreq => SYNTHESIZED_WIRE_60, - rdreq => SYNTHESIZED_WIRE_38, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - aclr => DOP_FIFO_CLR, - data => SYNTHESIZED_WIRE_63, - q => SYNTHESIZED_WIRE_36); - - -b2v_inst64 : lpm_constant0 -PORT MAP( result => CCS(4 DOWNTO 0)); - - -SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; - - -b2v_inst66 : lpm_bustri3 -PORT MAP(enabledt => FALCON_CLUT_RDH, - data => SYNTHESIZED_WIRE_41, - tridata => FB_AD(31 DOWNTO 26)); - - -SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; - - - -SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); - - - -b2v_inst7 : lpm_mux6 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => SYNTHESIZED_WIRE_42, - data1x => SYNTHESIZED_WIRE_43, - data2x => (OTHERS => '0'), - data3x => (OTHERS => '0'), - data4x => CCA, - data5x => CC16, - data6x => CC24(23 DOWNTO 0), - data7x => BORDER_COLOR, - sel => CCSEL, - result => SYNTHESIZED_WIRE_62); - - -b2v_inst70 : lpm_bustri3 -PORT MAP(enabledt => FALCON_CLUT_RDH, - data => SYNTHESIZED_WIRE_44, - tridata => FB_AD(23 DOWNTO 18)); - - -b2v_inst71 : lpm_ff6 -PORT MAP(clock => DDRCLK(0), - enable => FIFO_WRE, - data => VDVZ, - q => VDMA); - - - - -b2v_inst74 : lpm_bustri3 -PORT MAP(enabledt => FALCON_CLUT_RDL, - data => SYNTHESIZED_WIRE_45, - tridata => FB_AD(23 DOWNTO 18)); - - - - -b2v_inst77 : lpm_constant1 -PORT MAP( result => CCF(1 DOWNTO 0)); - - - -CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; - - - -b2v_inst80 : lpm_constant1 -PORT MAP( result => CCF(9 DOWNTO 8)); - - -b2v_inst81 : lpm_mux4 -PORT MAP(sel => COLOR1, - data0x => ZR_C8(7 DOWNTO 1), - data1x => SYNTHESIZED_WIRE_47, - result => ZR_C8B(7 DOWNTO 1)); - - -b2v_inst82 : lpm_constant3 -PORT MAP( result => SYNTHESIZED_WIRE_47); - - -b2v_inst83 : lpm_constant1 -PORT MAP( result => CCF(17 DOWNTO 16)); - - -PROCESS(DDRCLK(0),DDR_WR) -BEGIN -if (DDR_WR = '1') THEN - VDQS(3) <= DDRCLK(0); -ELSE - VDQS(3) <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(DDRCLK(0),DDR_WR) -BEGIN -if (DDR_WR = '1') THEN - VDQS(2) <= DDRCLK(0); -ELSE - VDQS(2) <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(DDRCLK(0),DDR_WR) -BEGIN -if (DDR_WR = '1') THEN - VDQS(1) <= DDRCLK(0); -ELSE - VDQS(1) <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(DDRCLK(0),DDR_WR) -BEGIN -if (DDR_WR = '1') THEN - VDQS(0) <= DDRCLK(0); -ELSE - VDQS(0) <= 'Z'; -END IF; -END PROCESS; - - -PROCESS(DDRCLK(3)) -BEGIN -IF (RISING_EDGE(DDRCLK(3))) THEN - DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; -END IF; -END PROCESS; - - -b2v_inst89 : lpm_shiftreg6 -PORT MAP(clock => DDRCLK(0), - shiftin => SR_BLITTER_DACK, - q => BLITTER_DACK); - - -b2v_inst9 : lpm_ff1 -PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_48, - q => CC24); - - -PROCESS(DDRCLK(3)) -BEGIN -IF (RISING_EDGE(DDRCLK(3))) THEN - DDR_WR <= SR_DDR_WR; -END IF; -END PROCESS; - - -PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) -BEGIN -IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN - DFF_inst91 <= CLUT_ADR(0); -END IF; -END PROCESS; - - -b2v_inst92 : lpm_shiftreg6 -PORT MAP(clock => DDRCLK(0), - shiftin => SR_DDR_FB, - q => DDR_FB); - - -PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) -BEGIN -IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN - DFF_inst93 <= DFF_inst91; -END IF; -END PROCESS; - - -b2v_inst94 : lpm_ff6 -PORT MAP(clock => DDRCLK(0), - enable => FIFO_WRE, - data => VDMA, - q => VDMB); - - -PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) -BEGIN -IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN - SYNTHESIZED_WIRE_64 <= FIFO_RDE; -END IF; -END PROCESS; - - - -b2v_inst97 : lpm_ff5 -PORT MAP(clock => DDRCLK(2), - data => SR_VDMP, - q => VDMP); - - -b2v_sr0 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_49, - data => FIFO_D(127 DOWNTO 112), - shiftout => CLUT_ADR(0)); - - -b2v_sr1 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_50, - data => FIFO_D(111 DOWNTO 96), - shiftout => CLUT_ADR1A); - - -b2v_sr2 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_51, - data => FIFO_D(95 DOWNTO 80), - shiftout => CLUT_ADR2A); - - -b2v_sr3 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_52, - data => FIFO_D(79 DOWNTO 64), - shiftout => CLUT_ADR3A); - - -b2v_sr4 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_53, - data => FIFO_D(63 DOWNTO 48), - shiftout => CLUT_ADR4A); - - -b2v_sr5 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_54, - data => FIFO_D(47 DOWNTO 32), - shiftout => CLUT_ADR5A); - - -b2v_sr6 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => CLUT_ADR7A, - data => FIFO_D(31 DOWNTO 16), - shiftout => CLUT_ADR6A); - - -b2v_sr7 : lpm_shiftreg0 -PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => CLUT_ADR(0), - data => FIFO_D(15 DOWNTO 0), - shiftout => CLUT_ADR7A); - - -b2v_ST_CLUT_BLUE : altdpram0 -PORT MAP(wren_a => ST_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_55, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(18 DOWNTO 16), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_34, - q_b => CCS(7 DOWNTO 5)); - - -b2v_ST_CLUT_GREEN : altdpram0 -PORT MAP(wren_a => ST_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_56, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(22 DOWNTO 20), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_31, - q_b => CCS(15 DOWNTO 13)); - - -b2v_ST_CLUT_RED : altdpram0 -PORT MAP(wren_a => ST_CLUT_WR(0), - wren_b => SYNTHESIZED_WIRE_57, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(26 DOWNTO 24), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_29, - q_b => CCS(23 DOWNTO 21)); - - -b2v_VIDEO_MOD_MUX_CLUTCTR : video_mod_mux_clutctr -PORT MAP(nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_WR => nFB_WR, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - CLK33M => CLK33M, - CLK25M => CLK25M, - BLITTER_RUN => BLITTER_RUN, - CLK_VIDEO => CLK_VIDEO, - VR_BUSY => VR_BUSY, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - VR_D => VR_D, - COLOR8 => COLOR8, - ACP_CLUT_RD => ACP_CLUT_RD, - COLOR1 => COLOR1, - FALCON_CLUT_RDH => FALCON_CLUT_RDH, - FALCON_CLUT_RDL => FALCON_CLUT_RDL, - ST_CLUT_RD => ST_CLUT_RD, - HSYNC => HSYNC, - VSYNC => VSYNC, - nBLANK => nBLANK, - nSYNC => nSYNC, - nPD_VGA => nPD_VGA, - FIFO_RDE => FIFO_RDE, - COLOR2 => COLOR2, - COLOR4 => COLOR4, - PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED, - BLITTER_ON => BLITTER_ON, - VIDEO_MOD_TA => VIDEO_MOD_TA, - INTER_ZEI => INTER_ZEI, - DOP_FIFO_CLR => DOP_FIFO_CLR, - VIDEO_RECONFIG => VIDEO_RECONFIG, - VR_WR => VR_WR, - VR_RD => VR_RD, - CLR_FIFO => CLR_FIFO, - ACP_CLUT_WR => ACP_CLUT_WR, - BORDER_COLOR => BORDER_COLOR, - CCSEL => CCSEL, - CLUT_MUX_ADR => CLUT_MUX_ADR, - CLUT_OFF => CLUT_OFF, - FALCON_CLUT_WR => FALCON_CLUT_WR, - ST_CLUT_WR => ST_CLUT_WR, - VIDEO_RAM_CTR => VIDEO_RAM_CTR); - -PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; - + VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); + VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); + VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); + SYNTHESIZED_WIRE_0 <= '0'; + SYNTHESIZED_WIRE_1 <= '0'; + SYNTHESIZED_WIRE_2 <= '0'; + SYNTHESIZED_WIRE_3 <= '0'; + SYNTHESIZED_WIRE_4 <= '0'; + SYNTHESIZED_WIRE_5 <= '0'; + SYNTHESIZED_WIRE_19 <= '0'; + SYNTHESIZED_WIRE_20 <= '0'; + SYNTHESIZED_WIRE_21 <= '0'; + SYNTHESIZED_WIRE_22 <= '0'; + SYNTHESIZED_WIRE_23 <= '0'; + SYNTHESIZED_WIRE_24 <= '0'; + SYNTHESIZED_WIRE_55 <= '0'; + SYNTHESIZED_WIRE_56 <= '0'; + SYNTHESIZED_WIRE_57 <= '0'; + + CC16(18) <= GDFX_TEMP_SIGNAL_16(7); + CC16(17) <= GDFX_TEMP_SIGNAL_16(6); + CC16(16) <= GDFX_TEMP_SIGNAL_16(5); + CC16(9) <= GDFX_TEMP_SIGNAL_16(4); + CC16(8) <= GDFX_TEMP_SIGNAL_16(3); + CC16(2) <= GDFX_TEMP_SIGNAL_16(2); + CC16(1) <= GDFX_TEMP_SIGNAL_16(1); + CC16(0) <= GDFX_TEMP_SIGNAL_16(0); + + CC16(23) <= GDFX_TEMP_SIGNAL_0(15); + CC16(22) <= GDFX_TEMP_SIGNAL_0(14); + CC16(21) <= GDFX_TEMP_SIGNAL_0(13); + CC16(20) <= GDFX_TEMP_SIGNAL_0(12); + CC16(19) <= GDFX_TEMP_SIGNAL_0(11); + CC16(15) <= GDFX_TEMP_SIGNAL_0(10); + CC16(14) <= GDFX_TEMP_SIGNAL_0(9); + CC16(13) <= GDFX_TEMP_SIGNAL_0(8); + CC16(12) <= GDFX_TEMP_SIGNAL_0(7); + CC16(11) <= GDFX_TEMP_SIGNAL_0(6); + CC16(10) <= GDFX_TEMP_SIGNAL_0(5); + CC16(7) <= GDFX_TEMP_SIGNAL_0(4); + CC16(6) <= GDFX_TEMP_SIGNAL_0(3); + CC16(5) <= GDFX_TEMP_SIGNAL_0(2); + CC16(4) <= GDFX_TEMP_SIGNAL_0(1); + CC16(3) <= GDFX_TEMP_SIGNAL_0(0); + + GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); + GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); + GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); + GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); + GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); + GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); + GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); + GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); + GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); + GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80)); + GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88)); + GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96)); + GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); + GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); + GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); + + + ACP_CLUT_RAM : altdpram2 + PORT MAP(wren_a => ACP_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_0, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(7 DOWNTO 0), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_30, + q_b => CCA(7 DOWNTO 0)); + + + ACP_CLUT_RAM54 : altdpram2 + PORT MAP(wren_a => ACP_CLUT_WR(2), + wren_b => SYNTHESIZED_WIRE_1, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(15 DOWNTO 8), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_32, + q_b => CCA(15 DOWNTO 8)); + + + ACP_CLUT_RAM55 : altdpram2 + PORT MAP(wren_a => ACP_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_2, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(23 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_33, + q_b => CCA(23 DOWNTO 16)); + + + i_blitter : blitter + PORT MAP(nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + BLITTER_ON => BLITTER_ON, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + DDRCLK0 => DDRCLK(0), + SR_BLITTER_DACK => SR_BLITTER_DACK, + BLITTER_DACK => BLITTER_DACK, + BLITTER_DIN => BLITTER_DIN, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + BLITTER_RUN => BLITTER_RUN, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + BLITTER_TA => BLITTER_TA, + BLITTER_ADR => BLITTER_ADR, + BLITTER_DOUT => BLITTER_DOUT); + + + i_ddr_ctr : ddr_ctr + PORT MAP(nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + DDR_SYNC_66M => DDR_SYNC_66M, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + DDRCLK0 => DDRCLK(0), + CLK33M => CLK33M, + CLR_FIFO => CLR_FIFO, + BLITTER_ADR => BLITTER_ADR, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + FIFO_MW => FIFO_MW, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + nVWE => nVWE, + nVRAS => nVRAS, + nVCS => nVCS, + VCKE => VCKE, + nVCAS => nVCAS, + SR_FIFO_WRE => SR_FIFO_WRE, + SR_DDR_FB => SR_DDR_FB, + SR_DDR_WR => SR_DDR_WR, + SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, + VIDEO_DDR_TA => VIDEO_DDR_TA, + SR_BLITTER_DACK => SR_BLITTER_DACK, + DDRWR_D_SEL1 => DDRWR_D_SEL(1), + BA => BA, + FB_LE => FB_LE, + FB_VDOE => FB_VDOE, + SR_VDMP => SR_VDMP, + VA => VA, + VDM_SEL => VDM_SEL); + + + FALCON_CLUT_BLUE : altdpram1 + PORT MAP(wren_a => FALCON_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_3, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_45, + q_b => CCF(7 DOWNTO 2)); + + + FALCON_CLUT_GREEN : altdpram1 + PORT MAP(wren_a => FALCON_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_4, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_44, + q_b => CCF(15 DOWNTO 10)); + + + FALCON_CLUT_RED : altdpram1 + PORT MAP(wren_a => FALCON_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_5, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(31 DOWNTO 26), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_41, + q_b => CCF(23 DOWNTO 18)); + + + inst : lpm_fifo_dc0 + PORT MAP(wrreq => FIFO_WRE, + wrclk => DDRCLK(0), + rdreq => SYNTHESIZED_WIRE_60, + rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => CLR_FIFO, + data => VDMC, + q => SYNTHESIZED_WIRE_63, + wrusedw => FIFO_MW); + + + inst1 : altddio_bidir0 + PORT MAP(oe => VDOUT_OE, + inclock => DDRCLK(1), + outclock => DDRCLK(3), + datain_h => VDP_OUT(63 DOWNTO 32), + datain_l => VDP_OUT(31 DOWNTO 0), + padio => VD, + combout => SYNTHESIZED_WIRE_15, + dataout_h => VDP_IN(31 DOWNTO 0), + dataout_l => VDP_IN(63 DOWNTO 32)); + + + inst10 : lpm_ff4 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_7, + q => GDFX_TEMP_SIGNAL_0); + + + inst100 : lpm_muxvdm + PORT MAP(data0x => VDMB, + data10x => GDFX_TEMP_SIGNAL_1, + data11x => GDFX_TEMP_SIGNAL_2, + data12x => GDFX_TEMP_SIGNAL_3, + data13x => GDFX_TEMP_SIGNAL_4, + data14x => GDFX_TEMP_SIGNAL_5, + data15x => GDFX_TEMP_SIGNAL_6, + data1x => GDFX_TEMP_SIGNAL_7, + data2x => GDFX_TEMP_SIGNAL_8, + data3x => GDFX_TEMP_SIGNAL_9, + data4x => GDFX_TEMP_SIGNAL_10, + data5x => GDFX_TEMP_SIGNAL_11, + data6x => GDFX_TEMP_SIGNAL_12, + data7x => GDFX_TEMP_SIGNAL_13, + data8x => GDFX_TEMP_SIGNAL_14, + data9x => GDFX_TEMP_SIGNAL_15, + sel => VDM_SEL, + result => VDMC); + + + inst102 : lpm_mux3 + PORT MAP(data1 => DFF_inst93, + data0 => ZR_C8(0), + sel => COLOR1, + result => ZR_C8B(0)); + + + CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; + + + CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; + + + SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; + + + CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; + + + SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; + + + inst108 : lpm_bustri_long + PORT MAP(enabledt => FB_VDOE(0), + data => VDR, + tridata => FB_AD); + + + inst109 : lpm_bustri_long + PORT MAP(enabledt => FB_VDOE(1), + data => SYNTHESIZED_WIRE_11, + tridata => FB_AD); + + + inst11 : lpm_ff5 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_12, + q => ZR_C8); + + + inst110 : lpm_bustri_long + PORT MAP(enabledt => FB_VDOE(2), + data => SYNTHESIZED_WIRE_13, + tridata => FB_AD); + + + inst119 : lpm_bustri_long + PORT MAP(enabledt => FB_VDOE(3), + data => SYNTHESIZED_WIRE_14, + tridata => FB_AD); + + + inst12 : lpm_ff1 + PORT MAP(clock => DDRCLK(0), + data => VDP_IN(31 DOWNTO 0), + q => VDVZ(31 DOWNTO 0)); + + + inst13 : lpm_ff0 + PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(0), + data => FB_AD, + q => FB_DDR(127 DOWNTO 96)); + + + inst14 : lpm_ff0 + PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(1), + data => FB_AD, + q => FB_DDR(95 DOWNTO 64)); + + + inst15 : lpm_ff0 + PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(2), + data => FB_AD, + q => FB_DDR(63 DOWNTO 32)); + + + inst16 : lpm_ff0 + PORT MAP(clock => DDR_SYNC_66M, + enable => FB_LE(3), + data => FB_AD, + q => FB_DDR(31 DOWNTO 0)); + + + inst17 : lpm_ff0 + PORT MAP(clock => DDRCLK(0), + enable => DDR_FB(1), + data => VDP_IN(31 DOWNTO 0), + q => SYNTHESIZED_WIRE_11); + + + inst18 : lpm_ff0 + PORT MAP(clock => DDRCLK(0), + enable => DDR_FB(0), + data => VDP_IN(63 DOWNTO 32), + q => SYNTHESIZED_WIRE_13); + + + inst19 : lpm_ff0 + PORT MAP(clock => DDRCLK(0), + enable => DDR_FB(0), + data => VDP_IN(31 DOWNTO 0), + q => SYNTHESIZED_WIRE_14); + + + inst2 : altddio_out0 + PORT MAP(outclock => DDRCLK(3), + datain_h => VDMP(7 DOWNTO 4), + datain_l => VDMP(3 DOWNTO 0), + dataout => VDM); + + + inst20 : lpm_ff1 + PORT MAP(clock => DDRCLK(0), + data => VDVZ(31 DOWNTO 0), + q => VDVZ(95 DOWNTO 64)); + + + inst21 : lpm_mux0 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 96), + data1x => FIFO_D(95 DOWNTO 64), + data2x => FIFO_D(63 DOWNTO 32), + data3x => FIFO_D(31 DOWNTO 0), + sel => CLUT_MUX_ADR(1 DOWNTO 0), + result => SYNTHESIZED_WIRE_48); + + + inst22 : lpm_mux5 + PORT MAP(data0x => FB_DDR(127 DOWNTO 64), + data1x => FB_DDR(63 DOWNTO 0), + data2x => BLITTER_DOUT(127 DOWNTO 64), + data3x => BLITTER_DOUT(63 DOWNTO 0), + sel => DDRWR_D_SEL, + result => VDP_OUT); + + + inst23 : lpm_constant2 + PORT MAP( result => GDFX_TEMP_SIGNAL_16); + + + inst24 : lpm_mux1 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 112), + data1x => FIFO_D(111 DOWNTO 96), + data2x => FIFO_D(95 DOWNTO 80), + data3x => FIFO_D(79 DOWNTO 64), + data4x => FIFO_D(63 DOWNTO 48), + data5x => FIFO_D(47 DOWNTO 32), + data6x => FIFO_D(31 DOWNTO 16), + data7x => FIFO_D(15 DOWNTO 0), + sel => CLUT_MUX_ADR(2 DOWNTO 0), + result => SYNTHESIZED_WIRE_7); + + + inst25 : lpm_mux2 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 120), + data10x => FIFO_D(47 DOWNTO 40), + data11x => FIFO_D(39 DOWNTO 32), + data12x => FIFO_D(31 DOWNTO 24), + data13x => FIFO_D(23 DOWNTO 16), + data14x => FIFO_D(15 DOWNTO 8), + data15x => FIFO_D(7 DOWNTO 0), + data1x => FIFO_D(119 DOWNTO 112), + data2x => FIFO_D(111 DOWNTO 104), + data3x => FIFO_D(103 DOWNTO 96), + data4x => FIFO_D(95 DOWNTO 88), + data5x => FIFO_D(87 DOWNTO 80), + data6x => FIFO_D(79 DOWNTO 72), + data7x => FIFO_D(71 DOWNTO 64), + data8x => FIFO_D(63 DOWNTO 56), + data9x => FIFO_D(55 DOWNTO 48), + sel => CLUT_MUX_ADR, + result => SYNTHESIZED_WIRE_12); + + + inst26 : lpm_shiftreg4 + PORT MAP(clock => DDRCLK(0), + shiftin => SR_FIFO_WRE, + shiftout => FIFO_WRE); + + + inst27 : lpm_latch0 + PORT MAP(gate => DDR_SYNC_66M, + data => SYNTHESIZED_WIRE_15, + q => VDR); + + + + CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; + + + inst3 : lpm_ff1 + PORT MAP(clock => DDRCLK(0), + data => VDP_IN(63 DOWNTO 32), + q => VDVZ(63 DOWNTO 32)); + + + CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; + + + CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; + + + SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; + + + SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; + + + SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; + + + SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; + + + inst36 : lpm_ff6 + PORT MAP(clock => DDRCLK(0), + enable => BLITTER_DACK(0), + data => VDVZ, + q => BLITTER_DIN); + + + VDOUT_OE <= DDR_WR OR SR_DDR_WR; + + + + VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA; + + + inst4 : lpm_ff1 + PORT MAP(clock => DDRCLK(0), + data => VDVZ(63 DOWNTO 32), + q => VDVZ(127 DOWNTO 96)); + + + inst40 : mux41_0 + PORT MAP(S0 => COLOR2, + S1 => COLOR4, + D0 => CLUT_ADR6A, + INH => SYNTHESIZED_WIRE_19, + D1 => CLUT_ADR7A, + Q => SYNTHESIZED_WIRE_54); + + + inst41 : mux41_1 + PORT MAP(S0 => COLOR2, + S1 => COLOR4, + D0 => CLUT_ADR5A, + INH => SYNTHESIZED_WIRE_20, + D1 => CLUT_ADR6A, + Q => SYNTHESIZED_WIRE_53); + + + inst42 : mux41_2 + PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR7A, + S1 => COLOR4, + D0 => CLUT_ADR4A, + INH => SYNTHESIZED_WIRE_21, + D1 => CLUT_ADR5A, + Q => SYNTHESIZED_WIRE_52); + + + inst43 : mux41_3 + PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR6A, + S1 => COLOR4, + D0 => CLUT_ADR3A, + INH => SYNTHESIZED_WIRE_22, + D1 => CLUT_ADR4A, + Q => SYNTHESIZED_WIRE_51); + + + inst44 : mux41_4 + PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR5A, + S1 => COLOR4, + D0 => CLUT_ADR2A, + INH => SYNTHESIZED_WIRE_23, + D1 => CLUT_ADR3A, + Q => SYNTHESIZED_WIRE_50); + + + inst45 : mux41_5 + PORT MAP(S0 => COLOR2, + D2 => CLUT_ADR4A, + S1 => COLOR4, + D0 => CLUT_ADR1A, + INH => SYNTHESIZED_WIRE_24, + D1 => CLUT_ADR2A, + Q => SYNTHESIZED_WIRE_49); + + + inst46 : lpm_ff3 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_25, + q => SYNTHESIZED_WIRE_43); + + + inst47 : lpm_ff3 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => CCF, + q => SYNTHESIZED_WIRE_25); + + + + inst49 : lpm_ff3 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_26, + q => SYNTHESIZED_WIRE_42); + + + inst5 : altddio_out2 + PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, + datain_h => SYNTHESIZED_WIRE_62, + datain_l => SYNTHESIZED_WIRE_62, + dataout => SYNTHESIZED_WIRE_65); + + + + inst51 : lpm_bustri1 + PORT MAP(enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_29, + tridata => FB_AD(26 DOWNTO 24)); + + + inst52 : lpm_ff3 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => CCS, + q => SYNTHESIZED_WIRE_26); + + + inst53 : lpm_bustri_byt + PORT MAP(enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_30, + tridata => FB_AD(7 DOWNTO 0)); + + + inst54 : lpm_constant0 + PORT MAP( result => CCS(20 DOWNTO 16)); + + + + inst56 : lpm_bustri1 + PORT MAP(enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_31, + tridata => FB_AD(22 DOWNTO 20)); + + + inst57 : lpm_bustri_byt + PORT MAP(enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_32, + tridata => FB_AD(15 DOWNTO 8)); + + + inst58 : lpm_bustri_byt + PORT MAP(enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_33, + tridata => FB_AD(23 DOWNTO 16)); + + + inst59 : lpm_constant0 + PORT MAP( result => CCS(12 DOWNTO 8)); + + + + + inst61 : lpm_bustri1 + PORT MAP(enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_34, + tridata => FB_AD(18 DOWNTO 16)); + + + inst62 : lpm_muxdz + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clken => FIFO_RDE, + sel => INTER_ZEI, + data0x => SYNTHESIZED_WIRE_63, + data1x => SYNTHESIZED_WIRE_36, + result => FIFO_D); + + + inst63 : lpm_fifodz + PORT MAP(wrreq => SYNTHESIZED_WIRE_60, + rdreq => SYNTHESIZED_WIRE_38, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => DOP_FIFO_CLR, + data => SYNTHESIZED_WIRE_63, + q => SYNTHESIZED_WIRE_36); + + + inst64 : lpm_constant0 + PORT MAP( result => CCS(4 DOWNTO 0)); + + + SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; + + + inst66 : lpm_bustri3 + PORT MAP(enabledt => FALCON_CLUT_RDH, + data => SYNTHESIZED_WIRE_41, + tridata => FB_AD(31 DOWNTO 26)); + + + SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; + + + + SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); + + + + inst7 : lpm_mux6 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => SYNTHESIZED_WIRE_42, + data1x => SYNTHESIZED_WIRE_43, + data2x => (OTHERS => '0'), + data3x => (OTHERS => '0'), + data4x => CCA, + data5x => CC16, + data6x => CC24(23 DOWNTO 0), + data7x => BORDER_COLOR, + sel => CCSEL, + result => SYNTHESIZED_WIRE_62); + + + inst70 : lpm_bustri3 + PORT MAP(enabledt => FALCON_CLUT_RDH, + data => SYNTHESIZED_WIRE_44, + tridata => FB_AD(23 DOWNTO 18)); + + + inst71 : lpm_ff6 + PORT MAP(clock => DDRCLK(0), + enable => FIFO_WRE, + data => VDVZ, + q => VDMA); + + + + + inst74 : lpm_bustri3 + PORT MAP(enabledt => FALCON_CLUT_RDL, + data => SYNTHESIZED_WIRE_45, + tridata => FB_AD(23 DOWNTO 18)); + + + + + inst77 : lpm_constant1 + PORT MAP( result => CCF(1 DOWNTO 0)); + + + + CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; + + + + inst80 : lpm_constant1 + PORT MAP( result => CCF(9 DOWNTO 8)); + + + inst81 : lpm_mux4 + PORT MAP(sel => COLOR1, + data0x => ZR_C8(7 DOWNTO 1), + data1x => SYNTHESIZED_WIRE_47, + result => ZR_C8B(7 DOWNTO 1)); + + + inst82 : lpm_constant3 + PORT MAP( result => SYNTHESIZED_WIRE_47); + + + inst83 : lpm_constant1 + PORT MAP( result => CCF(17 DOWNTO 16)); + + + PROCESS(DDRCLK(0),DDR_WR) + BEGIN + if (DDR_WR = '1') THEN + VDQS(3) <= DDRCLK(0); + ELSE + VDQS(3) <= 'Z'; + END IF; + END PROCESS; + + + PROCESS(DDRCLK(0),DDR_WR) + BEGIN + if (DDR_WR = '1') THEN + VDQS(2) <= DDRCLK(0); + ELSE + VDQS(2) <= 'Z'; + END IF; + END PROCESS; + + + PROCESS(DDRCLK(0),DDR_WR) + BEGIN + if (DDR_WR = '1') THEN + VDQS(1) <= DDRCLK(0); + ELSE + VDQS(1) <= 'Z'; + END IF; + END PROCESS; + + + PROCESS(DDRCLK(0),DDR_WR) + BEGIN + if (DDR_WR = '1') THEN + VDQS(0) <= DDRCLK(0); + ELSE + VDQS(0) <= 'Z'; + END IF; + END PROCESS; + + + PROCESS(DDRCLK(3)) + BEGIN + IF (rising_edge(DDRCLK(3))) THEN + DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; + END IF; + END PROCESS; + + + inst89 : lpm_shiftreg6 + PORT MAP(clock => DDRCLK(0), + shiftin => SR_BLITTER_DACK, + q => BLITTER_DACK); + + + inst9 : lpm_ff1 + PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_48, + q => CC24); + + + PROCESS(DDRCLK(3)) + BEGIN + IF (rising_edge(DDRCLK(3))) THEN + DDR_WR <= SR_DDR_WR; + END IF; + END PROCESS; + + + PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) + BEGIN + IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + DFF_inst91 <= CLUT_ADR(0); + END IF; + END PROCESS; + + + inst92 : lpm_shiftreg6 + PORT MAP(clock => DDRCLK(0), + shiftin => SR_DDR_FB, + q => DDR_FB); + + + PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) + BEGIN + IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + DFF_inst93 <= DFF_inst91; + END IF; + END PROCESS; + + + inst94 : lpm_ff6 + PORT MAP(clock => DDRCLK(0), + enable => FIFO_WRE, + data => VDMA, + q => VDMB); + + + PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) + BEGIN + IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + SYNTHESIZED_WIRE_64 <= FIFO_RDE; + END IF; + END PROCESS; + + + + inst97 : lpm_ff5 + PORT MAP(clock => DDRCLK(2), + data => SR_VDMP, + q => VDMP); + + + sr0 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_49, + data => FIFO_D(127 DOWNTO 112), + shiftout => CLUT_ADR(0)); + + + sr1 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_50, + data => FIFO_D(111 DOWNTO 96), + shiftout => CLUT_ADR1A); + + + sr2 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_51, + data => FIFO_D(95 DOWNTO 80), + shiftout => CLUT_ADR2A); + + + sr3 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_52, + data => FIFO_D(79 DOWNTO 64), + shiftout => CLUT_ADR3A); + + + sr4 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_53, + data => FIFO_D(63 DOWNTO 48), + shiftout => CLUT_ADR4A); + + + sr5 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_54, + data => FIFO_D(47 DOWNTO 32), + shiftout => CLUT_ADR5A); + + + sr6 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => CLUT_ADR7A, + data => FIFO_D(31 DOWNTO 16), + shiftout => CLUT_ADR6A); + + + sr7 : lpm_shiftreg0 + PORT MAP(load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => CLUT_ADR(0), + data => FIFO_D(15 DOWNTO 0), + shiftout => CLUT_ADR7A); + + + ST_CLUT_BLUE : altdpram0 + PORT MAP(wren_a => ST_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_55, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(18 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_34, + q_b => CCS(7 DOWNTO 5)); + + + ST_CLUT_GREEN : altdpram0 + PORT MAP(wren_a => ST_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_56, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(22 DOWNTO 20), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_31, + q_b => CCS(15 DOWNTO 13)); + + + ST_CLUT_RED : altdpram0 + PORT MAP(wren_a => ST_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_57, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(26 DOWNTO 24), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_29, + q_b => CCS(23 DOWNTO 21)); + + + i_video_mod_mux_clutctr : video_mod_mux_clutctr + PORT MAP(nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + CLK33M => CLK33M, + CLK25M => CLK25M, + BLITTER_RUN => BLITTER_RUN, + CLK_VIDEO => CLK_VIDEO, + VR_BUSY => VR_BUSY, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VR_D => VR_D, + COLOR8 => COLOR8, + ACP_CLUT_RD => ACP_CLUT_RD, + COLOR1 => COLOR1, + FALCON_CLUT_RDH => FALCON_CLUT_RDH, + FALCON_CLUT_RDL => FALCON_CLUT_RDL, + ST_CLUT_RD => ST_CLUT_RD, + HSYNC => HSYNC, + VSYNC => VSYNC, + nBLANK => nBLANK, + nSYNC => nSYNC, + nPD_VGA => nPD_VGA, + FIFO_RDE => FIFO_RDE, + COLOR2 => COLOR2, + COLOR4 => COLOR4, + PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED, + BLITTER_ON => BLITTER_ON, + VIDEO_MOD_TA => VIDEO_MOD_TA, + INTER_ZEI => INTER_ZEI, + DOP_FIFO_CLR => DOP_FIFO_CLR, + VIDEO_RECONFIG => VIDEO_RECONFIG, + VR_WR => VR_WR, + VR_RD => VR_RD, + CLR_FIFO => CLR_FIFO, + ACP_CLUT_WR => ACP_CLUT_WR, + BORDER_COLOR => BORDER_COLOR, + CCSEL => CCSEL, + CLUT_MUX_ADR => CLUT_MUX_ADR, + CLUT_OFF => CLUT_OFF, + FALCON_CLUT_WR => FALCON_CLUT_WR, + ST_CLUT_WR => ST_CLUT_WR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR); + + PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; END bdf_type; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index f087d74..9e7ee65 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -131,8 +131,19 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_port set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} + +# the video RAM access set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VD[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDQS[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} + #************************************************************** # Set Clock Groups From 35d70dc637aacad835aa687e81dfd4aa1f554e41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 17:07:35 +0000 Subject: [PATCH 046/127] fix min instead of max --- FPGA_Quartus_13.1/firebee1.sdc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 9e7ee65..5e526e2 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -132,7 +132,7 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} -# the video RAM access +# video RAM access set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}] @@ -141,7 +141,7 @@ set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|a set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} From 3ec978dff59defa1062ae96b35bca61b4830707c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 11 Jan 2016 17:55:18 +0000 Subject: [PATCH 047/127] translate DDR_CTR to vhd --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 10 +- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 1203 +++++++++++++++++++++++++++ FPGA_Quartus_13.1/Video/video.vhd | 358 ++++---- 3 files changed, 1375 insertions(+), 196 deletions(-) create mode 100755 FPGA_Quartus_13.1/Video/DDR_CTR.vhd diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index 7c549b2..f8ae6ec 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -657,10 +657,10 @@ BEGIN VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 - FB_AD[31..24] = lpm_bustri_BYT( - VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) - # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) - ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + % FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) + # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), + (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); % FB_AD[23..16] = lpm_bustri_BYT( VIDEO_BASE_L & VIDEO_BASE_L_D[] @@ -669,6 +669,6 @@ BEGIN # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] - ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); + , (VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); END; diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd new file mode 100755 index 0000000..be0cf87 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -0,0 +1,1203 @@ +-- Xilinx XPort Language Converter, Version 4.1 (110) +-- +-- AHDL Design Source: DDR_CTR.tdf +-- VHDL Design Output: DDR_CTR.vhd +-- Created 11-Jan-2016 06:52 PM +-- +-- Copyright (c) 2016, Xilinx, Inc. All Rights Reserved. +-- Xilinx Inc makes no warranty, expressed or implied, with respect to +-- the operation and/or functionality of the converted output files. +-- + +-- ddr_ctr + + +-- CREATED BY FREDI ASCHWANDEN +-- FIFO WATER MARK +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! +Library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; +entity DDR_CTR is + +-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! + Port ( + FB_ADR: in std_logic_vector(31 downto 0); + nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1, nRSTO, MAIN_CLK, + FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO: in std_logic; + VIDEO_RAM_CTR: in std_logic_vector(15 downto 0); + BLITTER_ADR: in std_logic_vector(31 downto 0); + BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M: in std_logic; + FIFO_MW: in std_logic_vector(8 downto 0); + VA: buffer std_logic_vector(12 downto 0); + nVWE, nVRAS, nVCS, VCKE, nVCAS: buffer std_logic; + FB_LE: buffer std_logic_vector(3 downto 0); + FB_VDOE: buffer std_logic_vector(3 downto 0); + SR_FIFO_WRE, SR_DDR_FB, SR_DDR_WR, SR_DDRWR_D_SEL: buffer std_logic; + SR_VDMP: buffer std_logic_vector(7 downto 0); + VIDEO_DDR_TA, SR_BLITTER_DACK: buffer std_logic; + BA: buffer std_logic_vector(1 downto 0); + DDRWR_D_SEL1: buffer std_logic; + VDM_SEL: buffer std_logic_vector(3 downto 0); + FB_AD: inout std_logic_vector(31 downto 0) + ); +end DDR_CTR; + + +architecture DDR_CTR_behav of DDR_CTR is + +-- START (NORMAL 8 CYCLES TOTAL = 60ns) +-- CONFIG +-- READ CPU UND BLITTER, +-- WRITE CPU UND BLITTER +-- READ FIFO +-- CLOSE FIFO BANK +-- REFRESH 10X7.5NS=75NS + signal FB_REGDDR_3: std_logic_vector(2 downto 0); + signal FB_REGDDR_d: std_logic_vector(2 downto 0); + signal FB_REGDDR_q: std_logic_vector(2 downto 0); + signal DDR_SM_6: std_logic_vector(5 downto 0); + signal DDR_SM_d: std_logic_vector(5 downto 0); + signal DDR_SM_q: std_logic_vector(5 downto 0); + signal FB_B: std_logic_vector(3 downto 0); + signal VA_P: std_logic_vector(12 downto 0); + signal VA_P_d: std_logic_vector(12 downto 0); + signal VA_P_q: std_logic_vector(12 downto 0); + signal BA_P: std_logic_vector(1 downto 0); + signal BA_P_d: std_logic_vector(1 downto 0); + signal BA_P_q: std_logic_vector(1 downto 0); + signal VA_S: std_logic_vector(12 downto 0); + signal VA_S_d: std_logic_vector(12 downto 0); + signal VA_S_q: std_logic_vector(12 downto 0); + signal BA_S: std_logic_vector(1 downto 0); + signal BA_S_d: std_logic_vector(1 downto 0); + signal BA_S_q: std_logic_vector(1 downto 0); + signal MCS: std_logic_vector(1 downto 0); + signal MCS_d: std_logic_vector(1 downto 0); + signal MCS_q: std_logic_vector(1 downto 0); + signal SR_VDMP_d: std_logic_vector(7 downto 0); + signal SR_VDMP_q: std_logic_vector(7 downto 0); + signal CPU_ROW_ADR: std_logic_vector(12 downto 0); + signal CPU_BA: std_logic_vector(1 downto 0); + signal CPU_COL_ADR: std_logic_vector(9 downto 0); + signal BLITTER_ROW_ADR: std_logic_vector(12 downto 0); + signal BLITTER_BA: std_logic_vector(1 downto 0); + signal BLITTER_COL_ADR: std_logic_vector(9 downto 0); + signal FIFO_ROW_ADR: std_logic_vector(12 downto 0); + signal FIFO_BA: std_logic_vector(1 downto 0); + signal FIFO_COL_ADR: std_logic_vector(9 downto 0); + signal DDR_REFRESH_CNT: std_logic_vector(10 downto 0); + signal DDR_REFRESH_CNT_d: std_logic_vector(10 downto 0); + signal DDR_REFRESH_CNT_q: std_logic_vector(10 downto 0); + signal DDR_REFRESH_SIG: std_logic_vector(3 downto 0); + signal DDR_REFRESH_SIG_d: std_logic_vector(3 downto 0); + signal DDR_REFRESH_SIG_q: std_logic_vector(3 downto 0); + signal VIDEO_BASE_L_D: std_logic_vector(7 downto 0); + signal VIDEO_BASE_L_D_d: std_logic_vector(7 downto 0); + signal VIDEO_BASE_L_D_q: std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D: std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D_d: std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D_q: std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D: std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D_d: std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D_q: std_logic_vector(7 downto 0); + signal VIDEO_BASE_X_D: std_logic_vector(2 downto 0); + signal VIDEO_BASE_X_D_d: std_logic_vector(2 downto 0); + signal VIDEO_BASE_X_D_q: std_logic_vector(2 downto 0); + signal VIDEO_ADR_CNT: std_logic_vector(22 downto 0); + signal VIDEO_ADR_CNT_d: std_logic_vector(22 downto 0); + signal VIDEO_ADR_CNT_q: std_logic_vector(22 downto 0); + signal VIDEO_BASE_ADR: std_logic_vector(22 downto 0); + signal VIDEO_ACT_ADR: std_logic_vector(26 downto 0); + signal u0_data: std_logic_vector(7 downto 0); + signal u0_tridata: std_logic_vector(7 downto 0); + signal FB_REGDDR_0_clk_ctrl, SR_VDMP0_clk_ctrl, MCS0_clk_ctrl, + VA_S0_clk_ctrl, BA_S0_clk_ctrl, VA_P0_clk_ctrl, BA_P0_clk_ctrl, + DDR_SM_0_clk_ctrl, VIDEO_ADR_CNT0_clk_ctrl, VIDEO_ADR_CNT0_ena_ctrl, + DDR_REFRESH_CNT0_clk_ctrl, DDR_REFRESH_SIG0_clk_ctrl, + DDR_REFRESH_SIG0_ena_ctrl, VIDEO_BASE_L_D0_clk_ctrl, + VIDEO_BASE_L_D0_ena_ctrl, VIDEO_BASE_M_D0_clk_ctrl, + VIDEO_BASE_M_D0_ena_ctrl, VIDEO_BASE_H_D0_clk_ctrl, + VIDEO_BASE_H_D0_ena_ctrl, VIDEO_BASE_X_D0_clk_ctrl, + VIDEO_BASE_X_D0_ena_ctrl, VA12_2, VA12_1, VA11_2, VA11_1, VA10_2, + VA10_1, VA9_2, VA9_1, VA8_2, VA8_1, VA7_2, VA7_1, VA6_2, VA6_1, VA5_2, + VA5_1, VA4_2, VA4_1, VA3_2, VA3_1, VA2_2, VA2_1, VA1_2, VA1_1, VA0_2, + VA0_1, BA1_2, BA1_1, BA0_2, BA0_1, BUS_CYC_d_2, BUS_CYC_d_1, + FIFO_BANK_OK_d_2, FIFO_BANK_OK_d_1, u0_enabledt, gnd, vcc, + VIDEO_CNT_H, VIDEO_CNT_M, VIDEO_CNT_L, VIDEO_BASE_H, VIDEO_BASE_M, + VIDEO_BASE_L, REFRESH_TIME_q, REFRESH_TIME_clk, REFRESH_TIME_d, + REFRESH_TIME, DDR_REFRESH_REQ_q, DDR_REFRESH_REQ_clk, + DDR_REFRESH_REQ_d, DDR_REFRESH_REQ, DDR_REFRESH_ON, FIFO_BANK_NOT_OK, + FIFO_BANK_OK_q, FIFO_BANK_OK_clk, FIFO_BANK_OK_d, FIFO_BANK_OK, + SR_FIFO_WRE_q, SR_FIFO_WRE_clk, SR_FIFO_WRE_d, STOP_q, STOP_clk, + STOP_d, STOP, CLEAR_FIFO_CNT_q, CLEAR_FIFO_CNT_clk, CLEAR_FIFO_CNT_d, + CLEAR_FIFO_CNT, CLR_FIFO_SYNC_q, CLR_FIFO_SYNC_clk, CLR_FIFO_SYNC_d, + CLR_FIFO_SYNC, FIFO_ACTIVE, FIFO_AC_q, FIFO_AC_clk, FIFO_AC_d, + FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, + BLITTER_AC_clk, BLITTER_AC_d, BLITTER_AC, BLITTER_REQ_q, + BLITTER_REQ_clk, BLITTER_REQ_d, BLITTER_REQ, BUS_CYC_END, BUS_CYC_q, + BUS_CYC_clk, BUS_CYC_d, BUS_CYC, CPU_AC_q, CPU_AC_clk, CPU_AC_d, + CPU_AC, CPU_REQ_q, CPU_REQ_clk, CPU_REQ_d, CPU_REQ, CPU_SIG, + SR_DDRWR_D_SEL_q, SR_DDRWR_D_SEL_clk, SR_DDRWR_D_SEL_d, SR_DDR_WR_q, + SR_DDR_WR_clk, SR_DDR_WR_d, DDR_CONFIG, DDR_CS_q, DDR_CS_ena, + DDR_CS_clk, DDR_CS_d, DDR_CS, DDR_SEL, CPU_DDR_SYNC_q, + CPU_DDR_SYNC_clk, CPU_DDR_SYNC_d, CPU_DDR_SYNC, VWE, VRAS, VCAS, LINE: + std_logic; + +-- Sub Module Interface Section + + + component lpm_bustri_BYT + Port ( + data: in std_logic_vector(7 downto 0); + enabledt: in std_logic; + tridata: buffer std_logic_vector(7 downto 0) + ); + end component; + + Function to_std_logic(X: in Boolean) return Std_Logic is + variable ret : std_logic; + begin + if x then ret := '1'; else ret := '0'; end if; + return ret; + end to_std_logic; + + + -- sizeIt replicates a value to an array of specific length. + Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is + variable rep: std_logic_vector( len-1 downto 0); + begin for i in rep'range loop rep(i) := a; end loop; return rep; + end sizeIt; +begin + +-- Sub Module Section + u0: lpm_bustri_BYT port map (data=>u0_data, enabledt=>u0_enabledt, + tridata=>u0_tridata); + +-- Register Section + + SR_FIFO_WRE <= SR_FIFO_WRE_q; + process (SR_FIFO_WRE_clk) begin + if SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' then + SR_FIFO_WRE_q <= SR_FIFO_WRE_d; + end if; + end process; + + SR_DDR_WR <= SR_DDR_WR_q; + process (SR_DDR_WR_clk) begin + if SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' then + SR_DDR_WR_q <= SR_DDR_WR_d; + end if; + end process; + + SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; + process (SR_DDRWR_D_SEL_clk) begin + if SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' then + SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; + end if; + end process; + + SR_VDMP <= SR_VDMP_q; + process (SR_VDMP0_clk_ctrl) begin + if SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' then + SR_VDMP_q <= SR_VDMP_d; + end if; + end process; + + process (FB_REGDDR_0_clk_ctrl) begin + if FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' then + FB_REGDDR_q <= FB_REGDDR_d; + end if; + end process; + + process (DDR_SM_0_clk_ctrl) begin + if DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' then + DDR_SM_q <= DDR_SM_d; + end if; + end process; + + process (VA_P0_clk_ctrl) begin + if VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' then + VA_P_q <= VA_P_d; + end if; + end process; + + process (BA_P0_clk_ctrl) begin + if BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' then + BA_P_q <= BA_P_d; + end if; + end process; + + process (VA_S0_clk_ctrl) begin + if VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' then + VA_S_q <= VA_S_d; + end if; + end process; + + process (BA_S0_clk_ctrl) begin + if BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' then + BA_S_q <= BA_S_d; + end if; + end process; + + process (MCS0_clk_ctrl) begin + if MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' then + MCS_q <= MCS_d; + end if; + end process; + + process (CPU_DDR_SYNC_clk) begin + if CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' then + CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; + end if; + end process; + + process (DDR_CS_clk) begin + if DDR_CS_clk'event and DDR_CS_clk='1' then + if DDR_CS_ena='1' then + DDR_CS_q <= DDR_CS_d; + end if; + end if; + end process; + + process (CPU_REQ_clk) begin + if CPU_REQ_clk'event and CPU_REQ_clk='1' then + CPU_REQ_q <= CPU_REQ_d; + end if; + end process; + + process (CPU_AC_clk) begin + if CPU_AC_clk'event and CPU_AC_clk='1' then + CPU_AC_q <= CPU_AC_d; + end if; + end process; + + process (BUS_CYC_clk) begin + if BUS_CYC_clk'event and BUS_CYC_clk='1' then + BUS_CYC_q <= BUS_CYC_d; + end if; + end process; + + process (BLITTER_REQ_clk) begin + if BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' then + BLITTER_REQ_q <= BLITTER_REQ_d; + end if; + end process; + + process (BLITTER_AC_clk) begin + if BLITTER_AC_clk'event and BLITTER_AC_clk='1' then + BLITTER_AC_q <= BLITTER_AC_d; + end if; + end process; + + process (FIFO_REQ_clk) begin + if FIFO_REQ_clk'event and FIFO_REQ_clk='1' then + FIFO_REQ_q <= FIFO_REQ_d; + end if; + end process; + + process (FIFO_AC_clk) begin + if FIFO_AC_clk'event and FIFO_AC_clk='1' then + FIFO_AC_q <= FIFO_AC_d; + end if; + end process; + + process (CLR_FIFO_SYNC_clk) begin + if CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' then + CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; + end if; + end process; + + process (CLEAR_FIFO_CNT_clk) begin + if CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' then + CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; + end if; + end process; + + process (STOP_clk) begin + if STOP_clk'event and STOP_clk='1' then + STOP_q <= STOP_d; + end if; + end process; + + process (FIFO_BANK_OK_clk) begin + if FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' then + FIFO_BANK_OK_q <= FIFO_BANK_OK_d; + end if; + end process; + + process (DDR_REFRESH_CNT0_clk_ctrl) begin + if DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' then + DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; + end if; + end process; + + process (DDR_REFRESH_REQ_clk) begin + if DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' then + DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; + end if; + end process; + + process (DDR_REFRESH_SIG0_clk_ctrl) begin + if DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' then + if DDR_REFRESH_SIG0_ena_ctrl='1' then + DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; + end if; + end if; + end process; + + process (REFRESH_TIME_clk) begin + if REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' then + REFRESH_TIME_q <= REFRESH_TIME_d; + end if; + end process; + + process (VIDEO_BASE_L_D0_clk_ctrl) begin + if VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' then + if VIDEO_BASE_L_D0_ena_ctrl='1' then + VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; + end if; + end if; + end process; + + process (VIDEO_BASE_M_D0_clk_ctrl) begin + if VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' then + if VIDEO_BASE_M_D0_ena_ctrl='1' then + VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; + end if; + end if; + end process; + + process (VIDEO_BASE_H_D0_clk_ctrl) begin + if VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' then + if VIDEO_BASE_H_D0_ena_ctrl='1' then + VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; + end if; + end if; + end process; + + process (VIDEO_BASE_X_D0_clk_ctrl) begin + if VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' then + if VIDEO_BASE_X_D0_ena_ctrl='1' then + VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; + end if; + end if; + end process; + + process (VIDEO_ADR_CNT0_clk_ctrl) begin + if VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' then + if VIDEO_ADR_CNT0_ena_ctrl='1' then + VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; + end if; + end if; + end process; + +-- Start of original equations + LINE <= FB_SIZE0 and FB_SIZE1; + +-- BYT SELECT +-- ADR==0 +-- LONG UND LINE + FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and + FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + +-- ADR==1 +-- HIGH WORD +-- LONG UND LINE + FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not + FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not + FB_SIZE1) and (not FB_SIZE0)); + +-- ADR==2 +-- LONG UND LINE + FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and + FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + +-- ADR==3 +-- LOW WORD +-- LONG UND LINE + FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not + FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) + and (not FB_SIZE0)); + +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR_0_clk_ctrl <= MAIN_CLK; + + + process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, + DDR_CONFIG, nFB_WR, vcc) + variable stdVec3: std_logic_vector(2 downto 0); + begin + FB_REGDDR_d <= FB_REGDDR_q; + (FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); + (FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), + VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); + stdVec3 := FB_REGDDR_q; + case stdVec3 is + when "000" => + FB_LE(0) <= not nFB_WR; + +-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' then + FB_REGDDR_d <= "001"; + else + FB_REGDDR_d <= "000"; + end if; + when "001" => + if (DDR_CS_q)='1' then + FB_LE(0) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + if (LINE)='1' then + FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); + FB_REGDDR_d <= "010"; + else + BUS_CYC_END <= vcc; + FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not + DDR_CONFIG); + FB_REGDDR_d <= "000"; + end if; + else + FB_REGDDR_d <= "000"; + end if; + when "010" => + if (DDR_CS_q)='1' then + FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); + FB_LE(1) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + FB_REGDDR_d <= "011"; + else + FB_REGDDR_d <= "000"; + end if; + when "011" => + if (DDR_CS_q)='1' then + FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); + FB_LE(2) <= not nFB_WR; + +-- BEI LINE WRITE EVT. WARTEN + if ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' then + FB_REGDDR_d <= "011"; + else + VIDEO_DDR_TA <= vcc; + FB_REGDDR_d <= "100"; + end if; + else + FB_REGDDR_d <= "000"; + end if; + when "100" => + if (DDR_CS_q)='1' then + FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); + FB_LE(3) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + BUS_CYC_END <= vcc; + FB_REGDDR_d <= "000"; + else + FB_REGDDR_d <= "000"; + end if; + when others => + end case; + stdVec3 := (others=>'0'); -- no storage needed + end process; + +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE <= VIDEO_RAM_CTR(0); + nVCS <= not VIDEO_RAM_CTR(1); + DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); + DDR_CONFIG <= VIDEO_RAM_CTR(3); + FIFO_ACTIVE <= VIDEO_RAM_CTR(8); + +-- ------------------------------ + CPU_ROW_ADR <= FB_ADR(26 downto 14); + CPU_BA <= FB_ADR(13 downto 12); + CPU_COL_ADR <= FB_ADR(11 downto 2); + nVRAS <= not VRAS; + nVCAS <= not VCAS; + nVWE <= not VWE; + SR_DDR_WR_clk <= DDRCLK0; + SR_DDRWR_D_SEL_clk <= DDRCLK0; + SR_VDMP0_clk_ctrl <= DDRCLK0; + SR_FIFO_WRE_clk <= DDRCLK0; + CPU_AC_clk <= DDRCLK0; + FIFO_AC_clk <= DDRCLK0; + BLITTER_AC_clk <= DDRCLK0; + DDRWR_D_SEL1 <= BLITTER_AC_q; + +-- SELECT LOGIC + DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); + DDR_CS_clk <= MAIN_CLK; + DDR_CS_ena <= FB_ALE; + DDR_CS_d <= DDR_SEL; + +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER +-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG +-- CONFIG SOFORT LOS +-- LINE WRITE SPÄTER + CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or + (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and + (not nFB_WR)); + CPU_REQ_clk <= DDR_SYNC_66M; + +-- HALTEN BUS CYC BEGONNEN ODER FERTIG + CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" + and FB_REGDDR_q /= "100") and (not BUS_CYC_END) and (not BUS_CYC_q)); + BUS_CYC_clk <= DDRCLK0; + BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); + +-- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS0_clk_ctrl <= DDRCLK0; + MCS_d(0) <= MAIN_CLK; + MCS_d(1) <= MCS_q(0); + CPU_DDR_SYNC_clk <= DDRCLK0; + +-- NUR 1 WENN EIN + CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); + +-- ------------------------------------------------- + VA_S0_clk_ctrl <= DDRCLK0; + BA_S0_clk_ctrl <= DDRCLK0; + (VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1, VA3_1, + VA2_1, VA1_1, VA0_1) <= VA_S_q; + (BA1_1, BA0_1) <= BA_S_q; + VA_P0_clk_ctrl <= DDRCLK0; + BA_P0_clk_ctrl <= DDRCLK0; + +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM_0_clk_ctrl <= DDRCLK0; + + + process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, + CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, + FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, + FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, + VIDEO_ADR_CNT_q, FIFO_COL_ADR, gnd, DDR_SEL, LINE, FIFO_BA, VA_P_q, + BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, + DDR_REFRESH_SIG_q, vcc) + variable stdVec6: std_logic_vector(5 downto 0); + begin + DDR_SM_d <= DDR_SM_q; + BA_S_d <= "00"; + VA_S_d <= "0000000000000"; + BA_P_d <= "00"; + (VA_P_d(9), VA_P_d(8), VA_P_d(7), VA_P_d(6), VA_P_d(5), VA_P_d(4), + VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= + std_logic_vector'("00000000000"); + SR_VDMP_d <= "00000000"; + VA_P_d(12 downto 11) <= "00"; + (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, + SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, + VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, + BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2, + FIFO_BANK_NOT_OK, VCAS, VRAS) <= + std_logic_vector'("00000000000000000000000000000"); + stdVec6 := DDR_SM_q; + case stdVec6 is + when "000000" => + if (DDR_REFRESH_REQ_q)='1' then + DDR_SM_d <= "011111"; + +-- SYNCHRON UND EIN? + elsif (CPU_DDR_SYNC_q)='1' then + +-- JA + if (DDR_CONFIG)='1' then + DDR_SM_d <= "001000"; + +-- BEI WAIT UND LINE WRITE + elsif (CPU_REQ_q)='1' then + VA_S_d <= CPU_ROW_ADR; + BA_S_d <= CPU_BA; + CPU_AC_d <= vcc; + BUS_CYC_d_2 <= vcc; + DDR_SM_d <= "000010"; + else + +-- FIFO IST DEFAULT + if (FIFO_REQ_q or (not BLITTER_REQ_q))='1' then + VA_P_d <= FIFO_ROW_ADR; + BA_P_d <= FIFO_BA; + +-- VORBESETZEN + FIFO_AC_d <= vcc; + else + VA_P_d <= BLITTER_ROW_ADR; + BA_P_d <= BLITTER_BA; + +-- VORBESETZEN + BLITTER_AC_d <= vcc; + end if; + DDR_SM_d <= "000001"; + end if; + else + +-- NEIN ->SYNCHRONISIEREN + DDR_SM_d <= "000000"; + end if; + when "000001" => + +-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + if (DDR_SEL and (nFB_WR or (not LINE)))='1' then + VRAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, + VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); + (BA1_2, BA0_2) <= FB_AD(13 downto 12); + +-- AUTO PRECHARGE DA NICHT FIFO PAGE + VA_S_d(10) <= vcc; + CPU_AC_d <= vcc; + +-- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + else + VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and + BLITTER_REQ_q); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, + VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; + (BA1_2, BA0_2) <= BA_P_q; + VA_S_d(10) <= not (FIFO_AC_q and FIFO_REQ_q); + FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; + FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; + BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; + end if; + DDR_SM_d <= "000011"; + when "000010" => + VRAS <= vcc; + FIFO_BANK_NOT_OK <= vcc; + CPU_AC_d <= vcc; + +-- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + DDR_SM_d <= "000011"; + when "000011" => + CPU_AC_d <= CPU_AC_q; + FIFO_AC_d <= FIFO_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + +-- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + if (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' + then + DDR_SM_d <= "010000"; + +-- CPU? + elsif (CPU_AC_q)='1' then + VA_S_d(9 downto 0) <= CPU_COL_ADR; + BA_S_d <= CPU_BA; + DDR_SM_d <= "001110"; + +-- FIFO? + elsif (FIFO_AC_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "010110"; + elsif (BLITTER_AC_q)='1' then + VA_S_d(9 downto 0) <= BLITTER_COL_ADR; + BA_S_d <= BLITTER_BA; + DDR_SM_d <= "001110"; + else + +-- READ + DDR_SM_d <= "000111"; + end if; + when "001110" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VCAS <= vcc; + +-- READ DATEN FÜR CPU + SR_DDR_FB <= CPU_AC_q; + +-- BLITTER DACK AND BLITTER LATCH DATEN + SR_BLITTER_DACK <= BLITTER_AC_q; + DDR_SM_d <= "001111"; + when "001111" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + +-- FIFO READ EINSCHIEBEN WENN BANK OK + if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; + +-- MANUELL PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + else + +-- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + +-- WRITE + DDR_SM_d <= "011101"; + end if; + when "010000" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + +-- BLITTER ACK AND BLITTER LATCH DATEN + SR_BLITTER_DACK <= BLITTER_AC_q; + +-- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + DDR_SM_d <= "010001"; + when "010001" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VA_S_d(9 downto 0) <= (sizeIt(CPU_AC_q,10) and CPU_COL_ADR) or + (sizeIt(BLITTER_AC_q,10) and BLITTER_COL_ADR); + +-- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or + (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); + +-- BYTE ENABLE WRITE + SR_VDMP_d(7 downto 4) <= FB_B; + +-- LINE ENABLE WRITE + SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; + DDR_SM_d <= "010010"; + when "010010" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VCAS <= vcc; + VWE <= vcc; + +-- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDR_WR_d <= vcc; + +-- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL_d <= vcc; + +-- WENN LINE DANN ACTIV + SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; + DDR_SM_d <= "010011"; + when "010011" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + +-- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDR_WR_d <= vcc; + +-- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL_d <= vcc; + DDR_SM_d <= "010100"; + when "010100" => + DDR_SM_d <= "010101"; + when "010101" => + if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; + +-- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + else + +-- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + +-- FIFO READ + DDR_SM_d <= "011101"; + end if; + when "010110" => + VCAS <= vcc; + +-- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + DDR_SM_d <= "010111"; + when "010111" => + if (FIFO_REQ_q)='1' then + +-- NEUE PAGE? + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then + +-- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + +-- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + else + VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + + unsigned'("0000000100")); + +-- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + end if; + else + +-- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + +-- NOCH OFFEN LASSEN + DDR_SM_d <= "011101"; + end if; + when "011000" => + VCAS <= vcc; + +-- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + DDR_SM_d <= "011001"; + when "011001" => + if CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) then + +-- ALLE PAGES SCHLIESEN + VA_S_d(10) <= vcc; + +-- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + elsif (FIFO_REQ_q)='1' then + +-- NEUE PAGE? + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then + +-- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + +-- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + else + VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + + unsigned'("0000000100")); + +-- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011010"; + end if; + else + +-- ALLE PAGES SCHLIESEN + VA_S_d(10) <= vcc; + +-- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + end if; + when "011010" => + VCAS <= vcc; + +-- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + +-- NOTFALL? + if (unsigned(FIFO_MW) < unsigned'("000000000")) then + +-- JA-> + DDR_SM_d <= "010111"; + else + DDR_SM_d <= "011011"; + end if; + when "011011" => + if (FIFO_REQ_q)='1' then + +-- NEUE PAGE? + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then + +-- ALLE BANKS SCHLIESEN + VA_S_d(10) <= vcc; + +-- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + else + VA_P_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + + unsigned'("0000000100")); + +-- NON AUTO PRECHARGE + VA_P_d(10) <= gnd; + BA_P_d <= FIFO_BA; + DDR_SM_d <= "011100"; + end if; + else + +-- ALLE BANKS SCHLIESEN + VA_S_d(10) <= vcc; + +-- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + end if; + when "011100" => + if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= + FIFO_BA then + VRAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, + VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); + (BA1_2, BA0_2) <= FB_AD(13 downto 12); + CPU_AC_d <= vcc; + +-- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + +-- AUTO PRECHARGE DA NICHT FIFO BANK + VA_S_d(10) <= vcc; + DDR_SM_d <= "000011"; + else + VCAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, + VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; + (BA1_2, BA0_2) <= BA_P_q; + +-- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + +-- CONFIG CYCLUS + DDR_SM_d <= "011001"; + end if; + when "001000" => + DDR_SM_d <= "001001"; + when "001001" => + BUS_CYC_d_2 <= CPU_REQ_q; + DDR_SM_d <= "001010"; + when "001010" => + if (CPU_REQ_q)='1' then + DDR_SM_d <= "001011"; + else + DDR_SM_d <= "000000"; + end if; + when "001011" => + DDR_SM_d <= "001100"; + when "001100" => + VA_S_d <= FB_AD(12 downto 0); + BA_S_d <= FB_AD(14 downto 13); + DDR_SM_d <= "001101"; + when "001101" => + +-- NUR BEI LONG WRITE + VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not + FB_SIZE1); + +-- NUR BEI LONG WRITE + VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not + FB_SIZE1); + +-- NUR BEI LONG WRITE + VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not + FB_SIZE1); + +-- CLOSE FIFO BANK + DDR_SM_d <= "000111"; + when "011101" => + +-- AUF NOT OK + FIFO_BANK_NOT_OK <= vcc; + +-- BÄNKE SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + DDR_SM_d <= "000110"; + when "011110" => + +-- AUF NOT OK + FIFO_BANK_NOT_OK <= vcc; + +-- BÄNKE SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + +-- REFRESH 70NS = 10 ZYCLEN + DDR_SM_d <= "000000"; + when "011111" => + +-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + if DDR_REFRESH_SIG_q = "1001" then + +-- ALLE BANKS SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + VA10_2 <= vcc; + FIFO_BANK_NOT_OK <= vcc; + DDR_SM_d <= "100001"; + else + VCAS <= vcc; + VRAS <= vcc; + DDR_SM_d <= "100000"; + end if; + when "100000" => + DDR_SM_d <= "100001"; + when "100001" => + DDR_SM_d <= "100010"; + when "100010" => + DDR_SM_d <= "100011"; + when "100011" => + +-- LEERSCHLAUFE + DDR_SM_d <= "000100"; + when "000100" => + DDR_SM_d <= "000101"; + when "000101" => + DDR_SM_d <= "000110"; + when "000110" => + DDR_SM_d <= "000111"; + when "000111" => + DDR_SM_d <= "000000"; + when others => + end case; + stdVec6 := (others=>'0'); -- no storage needed + end process; + +-- ------------------------------------------------------------- +-- BLITTER ---------------------- +-- --------------------------------------- + BLITTER_REQ_clk <= DDRCLK0; + BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); + BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); + BLITTER_BA(1) <= BLITTER_ADR(13); + BLITTER_BA(0) <= BLITTER_ADR(12); + BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); + +-- ---------------------------------------------------------------------------- +-- FIFO --------------------------------- +-- ------------------------------------------------------ + FIFO_REQ_clk <= DDRCLK0; + FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or + (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and + FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not + STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); + FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); + FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); + FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); + FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & + VIDEO_ADR_CNT_q(5) & VIDEO_ADR_CNT_q(4) & VIDEO_ADR_CNT_q(3) & + VIDEO_ADR_CNT_q(2) & VIDEO_ADR_CNT_q(1) & VIDEO_ADR_CNT_q(0) & "00"); + FIFO_BANK_OK_clk <= DDRCLK0; + FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); + +-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + CLR_FIFO_SYNC_clk <= DDRCLK0; + +-- SYNCHRONISIEREN + CLR_FIFO_SYNC_d <= CLR_FIFO; + CLEAR_FIFO_CNT_clk <= DDRCLK0; + CLEAR_FIFO_CNT_d <= CLR_FIFO_SYNC_q or (not FIFO_ACTIVE); + STOP_clk <= DDRCLK0; + STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; + +-- ZÄHLEN ----------------------------------------------- + VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; + VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; + VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or + (sizeIt(not CLEAR_FIFO_CNT_q,23) and + (std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) + + unsigned'("00000000000000000000001")))); + VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D_q; + VIDEO_BASE_ADR(19 downto 12) <= VIDEO_BASE_H_D_q; + VIDEO_BASE_ADR(11 downto 4) <= VIDEO_BASE_M_D_q; + VIDEO_BASE_ADR(3 downto 0) <= VIDEO_BASE_L_D_q(7 downto 4); + VDM_SEL <= VIDEO_BASE_L_D_q(3 downto 0); + +-- AKTUELLE VIDEO ADRESSE + VIDEO_ACT_ADR(26 downto 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - + unsigned(std_logic_vector'("00000000000000" & FIFO_MW))); + VIDEO_ACT_ADR(3 downto 0) <= VDM_SEL; + +-- --------------------------------------------------------------------------------------- +-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS +-- --------------------------------------------------------------------------------------- + DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; + +-- ZÄHLEN 0-2047 + DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + + unsigned'("00000000001")); + REFRESH_TIME_clk <= DDRCLK0; + +-- SYNC + REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not + MAIN_CLK); + DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; + DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = + "100011"); + +-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) +-- MINUS 1 WENN GEMACHT + DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and + sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)) or (sizeIt(not + REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) - + unsigned'("0001"))) and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not + DDR_CONFIG,4)); + DDR_REFRESH_REQ_clk <= DDRCLK0; + DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and + DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); + +-- --------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +-- ------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; + +-- 820D/2 + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000110"); + +-- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); + VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); + VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; + +-- 8203/2 + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000001"); + VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); + VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); + VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; + +-- 8200-1/2 + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000000"); + VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); + VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); + VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); + VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); + +-- 8209/2 + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000100"); + +-- 8207/2 + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000011"); + +-- 8204,5/2 + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000010"); + +-- FB_AD[31..24] = lpm_bustri_BYT( +-- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) +-- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), +-- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or + (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or + (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or + (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or + (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or + (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); + u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L + or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); + FB_AD(23 downto 16) <= u0_tridata; + + +-- Assignments added to explicitly combine the +-- effects of multiple drivers in the source + FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; + BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; + BA(0) <= BA0_1 or BA0_2; + BA(1) <= BA1_1 or BA1_2; + VA(0) <= VA0_1 or VA0_2; + VA(1) <= VA1_1 or VA1_2; + VA(2) <= VA2_1 or VA2_2; + VA(3) <= VA3_1 or VA3_2; + VA(4) <= VA4_1 or VA4_2; + VA(5) <= VA5_1 or VA5_2; + VA(6) <= VA6_1 or VA6_2; + VA(7) <= VA7_1 or VA7_2; + VA(8) <= VA8_1 or VA8_2; + VA(9) <= VA9_1 or VA9_2; + VA(10) <= VA10_1 or VA10_2; + VA(11) <= VA11_1 or VA11_2; + VA(12) <= VA12_1 or VA12_2; + +-- Define power signal(s) + vcc <= '1'; + gnd <= '0'; +end DDR_CTR_behav; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 0b60561..49c66f4 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -69,165 +69,194 @@ ENTITY video IS ); END video; -ARCHITECTURE bdf_type OF video IS - ATTRIBUTE black_box : BOOLEAN; - ATTRIBUTE noopt : BOOLEAN; +ARCHITECTURE rtl OF video IS + ATTRIBUTE black_box : BOOLEAN; + ATTRIBUTE noopt : BOOLEAN; COMPONENT mux41_0 - PORT(S0 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic); - END COMPONENT; + PORT + ( + S0 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic + ); + END COMPONENT mux41_0; ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; COMPONENT mux41_1 - PORT(S0 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic); - END COMPONENT; + PORT + ( + S0 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic + ); + END COMPONENT mux41_1; + ATTRIBUTE black_box OF mux41_1: COMPONENT IS true; ATTRIBUTE noopt OF mux41_1: COMPONENT IS true; COMPONENT mux41_2 - PORT(S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic); - END COMPONENT; + PORT + ( + S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic + ); + END COMPONENT mux41_2; + ATTRIBUTE black_box OF mux41_2: COMPONENT IS true; ATTRIBUTE noopt OF mux41_2: COMPONENT IS true; COMPONENT mux41_3 - PORT(S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic); - END COMPONENT; + PORT + ( + S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic + ); + END COMPONENT mux41_3; + ATTRIBUTE black_box OF mux41_3: COMPONENT IS true; ATTRIBUTE noopt OF mux41_3: COMPONENT IS true; COMPONENT mux41_4 - PORT(S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic); + PORT + ( + S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic + ); END COMPONENT; + ATTRIBUTE black_box OF mux41_4: COMPONENT IS true; ATTRIBUTE noopt OF mux41_4: COMPONENT IS true; COMPONENT mux41_5 - PORT(S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic); + PORT + ( + S0 : IN std_logic; + D2 : IN std_logic; + S1 : IN std_logic; + D0 : IN std_logic; + INH : IN std_logic; + D1 : IN std_logic; + Q : OUT std_logic + ); END COMPONENT; + ATTRIBUTE black_box OF mux41_5: COMPONENT IS true; ATTRIBUTE noopt OF mux41_5: COMPONENT IS true; COMPONENT altdpram2 - PORT(wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(7 DOWNTO 0); - address_b : IN std_logic_vector(7 DOWNTO 0); - data_a : IN std_logic_vector(7 DOWNTO 0); - data_b : IN std_logic_vector(7 DOWNTO 0); - q_a : OUT std_logic_vector(7 DOWNTO 0); - q_b : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(7 DOWNTO 0); + address_b : IN std_logic_vector(7 DOWNTO 0); + data_a : IN std_logic_vector(7 DOWNTO 0); + data_b : IN std_logic_vector(7 DOWNTO 0); + q_a : OUT std_logic_vector(7 DOWNTO 0); + q_b : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT blitter - PORT(nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - BLITTER_ON : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - DDRCLK0 : IN std_logic; - SR_BLITTER_DACK : IN std_logic; - BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); - BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_RUN : OUT std_logic; - BLITTER_SIG : OUT std_logic; - BLITTER_WR : OUT std_logic; - BLITTER_TA : OUT std_logic; - BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); - BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + BLITTER_ON : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + DDRCLK0 : IN std_logic; + SR_BLITTER_DACK : IN std_logic; + BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); + BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + BLITTER_RUN : OUT std_logic; + BLITTER_SIG : OUT std_logic; + BLITTER_WR : OUT std_logic; + BLITTER_TA : OUT std_logic; + BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); + BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT ddr_ctr - PORT(nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - DDR_SYNC_66M : IN std_logic; - BLITTER_SIG : IN std_logic; - BLITTER_WR : IN std_logic; - DDRCLK0 : IN std_logic; - CLK33M : IN std_logic; - CLR_FIFO : IN std_logic; - BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - FIFO_MW : IN std_logic_vector(8 DOWNTO 0); - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - nVWE : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - VCKE : OUT std_logic; - nVCAS : OUT std_logic; - SR_FIFO_WRE : OUT std_logic; - SR_DDR_FB : OUT std_logic; - SR_DDR_WR : OUT std_logic; - SR_DDRWR_D_SEL : OUT std_logic; - VIDEO_DDR_TA : OUT std_logic; - SR_BLITTER_DACK : OUT std_logic; - DDRWR_D_SEL1 : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - FB_LE : OUT std_logic_vector(3 DOWNTO 0); - FB_VDOE : OUT std_logic_vector(3 DOWNTO 0); - SR_VDMP : OUT std_logic_vector(7 DOWNTO 0); - VA : OUT std_logic_vector(12 DOWNTO 0); - VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) + PORT + ( + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + DDR_SYNC_66M : IN std_logic; + BLITTER_SIG : IN std_logic; + BLITTER_WR : IN std_logic; + DDRCLK0 : IN std_logic; + CLK33M : IN std_logic; + CLR_FIFO : IN std_logic; + BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + FIFO_MW : IN std_logic_vector(8 DOWNTO 0); + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + nVWE : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + VCKE : OUT std_logic; + nVCAS : OUT std_logic; + SR_FIFO_WRE : OUT std_logic; + SR_DDR_FB : OUT std_logic; + SR_DDR_WR : OUT std_logic; + SR_DDRWR_D_SEL : OUT std_logic; + VIDEO_DDR_TA : OUT std_logic; + SR_BLITTER_DACK : OUT std_logic; + DDRWR_D_SEL1 : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + FB_LE : OUT std_logic_vector(3 DOWNTO 0); + FB_VDOE : OUT std_logic_vector(3 DOWNTO 0); + SR_VDMP : OUT std_logic_vector(7 DOWNTO 0); + VA : OUT std_logic_vector(12 DOWNTO 0); + VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) ); - END COMPONENT; + END COMPONENT ddr_ctr; COMPONENT altdpram1 PORT(wren_a : IN std_logic; @@ -760,6 +789,7 @@ BEGIN VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); + SYNTHESIZED_WIRE_0 <= '0'; SYNTHESIZED_WIRE_1 <= '0'; SYNTHESIZED_WIRE_2 <= '0'; @@ -1023,18 +1053,12 @@ BEGIN result => ZR_C8B(0)); + + CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; - - CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; - - + SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; - - - CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; - - SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; @@ -1216,22 +1240,11 @@ BEGIN data => VDP_IN(63 DOWNTO 32), q => VDVZ(63 DOWNTO 32)); - CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; - - CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; - - SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; - - SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; - - SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; - - SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; @@ -1497,51 +1510,22 @@ BEGIN PORT MAP( result => CCF(17 DOWNTO 16)); - PROCESS(DDRCLK(0),DDR_WR) + PROCESS(DDRCLK(0), DDR_WR) BEGIN - if (DDR_WR = '1') THEN - VDQS(3) <= DDRCLK(0); - ELSE - VDQS(3) <= 'Z'; - END IF; + IF (DDR_WR = '1') THEN + VDQS <= (OTHERS => DDRCLK(0)); + ELSE + VDQS <= (OTHERS => 'Z'); + END IF; END PROCESS; - - - PROCESS(DDRCLK(0),DDR_WR) - BEGIN - if (DDR_WR = '1') THEN - VDQS(2) <= DDRCLK(0); - ELSE - VDQS(2) <= 'Z'; - END IF; - END PROCESS; - - - PROCESS(DDRCLK(0),DDR_WR) - BEGIN - if (DDR_WR = '1') THEN - VDQS(1) <= DDRCLK(0); - ELSE - VDQS(1) <= 'Z'; - END IF; - END PROCESS; - - - PROCESS(DDRCLK(0),DDR_WR) - BEGIN - if (DDR_WR = '1') THEN - VDQS(0) <= DDRCLK(0); - ELSE - VDQS(0) <= 'Z'; - END IF; - END PROCESS; - + PROCESS(DDRCLK(3)) BEGIN - IF (rising_edge(DDRCLK(3))) THEN - DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; - END IF; + IF (rising_edge(DDRCLK(3))) THEN + DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; + DDR_WR <= SR_DDR_WR; + END IF; END PROCESS; @@ -1556,15 +1540,7 @@ BEGIN data => SYNTHESIZED_WIRE_48, q => CC24); - - PROCESS(DDRCLK(3)) - BEGIN - IF (rising_edge(DDRCLK(3))) THEN - DDR_WR <= SR_DDR_WR; - END IF; - END PROCESS; - - + PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) BEGIN IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN @@ -1764,4 +1740,4 @@ BEGIN VIDEO_RAM_CTR => VIDEO_RAM_CTR); PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; -END bdf_type; \ No newline at end of file +END rtl; \ No newline at end of file From 7d2430a62c468f75de29a1f76d24a3c9197be593 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 12 Jan 2016 07:14:33 +0000 Subject: [PATCH 048/127] reformat converted VHDL --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 84 +- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 2065 ++++++++++++++------------- FPGA_Quartus_13.1/Video/video.vhd | 1261 ++++++++-------- FPGA_Quartus_13.1/firebee1.qsf | 364 ++--- FPGA_Quartus_13.1/firebee1.sdc | 24 +- 5 files changed, 1998 insertions(+), 1800 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf index f8ae6ec..bc65c0b 100644 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf @@ -15,45 +15,47 @@ CONSTANT FIFO_HWM = 500; SUBDESIGN ddr_ctr ( -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - CLR_FIFO : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - BLITTER_ADR[31..0] : INPUT; - BLITTER_SIG : INPUT; - BLITTER_WR : INPUT; - DDRCLK0 : INPUT; - CLK33M : INPUT; - FIFO_MW[8..0] : INPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - SR_FIFO_WRE : OUTPUT; - SR_DDR_FB : OUTPUT; - SR_DDR_WR : OUTPUT; - SR_DDRWR_D_SEL : OUTPUT; - SR_VDMP[7..0] : OUTPUT; - VIDEO_DDR_TA : OUTPUT; - SR_BLITTER_DACK : OUTPUT; - BA[1..0] : OUTPUT; - DDRWR_D_SEL1 : OUTPUT; - VDM_SEL[3..0] : OUTPUT; - FB_AD[31..0] : BIDIR; + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + CLK33M : INPUT; + FIFO_MW[8..0] : INPUT; + + DDRCLK0 : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + BA[1..0] : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + FB_AD[31..0] : BIDIR; -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! ) @@ -657,10 +659,10 @@ BEGIN VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 - % FB_AD[31..24] = lpm_bustri_BYT( + FB_AD[31..24] = lpm_bustri_BYT( VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), - (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); % + (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); FB_AD[23..16] = lpm_bustri_BYT( VIDEO_BASE_L & VIDEO_BASE_L_D[] diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index be0cf87..966b0be 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -16,126 +16,219 @@ -- FIFO WATER MARK -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -Library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.std_logic_arith.all; -entity DDR_CTR is - --- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - Port ( - FB_ADR: in std_logic_vector(31 downto 0); - nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1, nRSTO, MAIN_CLK, - FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO: in std_logic; - VIDEO_RAM_CTR: in std_logic_vector(15 downto 0); - BLITTER_ADR: in std_logic_vector(31 downto 0); - BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M: in std_logic; - FIFO_MW: in std_logic_vector(8 downto 0); - VA: buffer std_logic_vector(12 downto 0); - nVWE, nVRAS, nVCS, VCKE, nVCAS: buffer std_logic; - FB_LE: buffer std_logic_vector(3 downto 0); - FB_VDOE: buffer std_logic_vector(3 downto 0); - SR_FIFO_WRE, SR_DDR_FB, SR_DDR_WR, SR_DDRWR_D_SEL: buffer std_logic; - SR_VDMP: buffer std_logic_vector(7 downto 0); - VIDEO_DDR_TA, SR_BLITTER_DACK: buffer std_logic; - BA: buffer std_logic_vector(1 downto 0); - DDRWR_D_SEL1: buffer std_logic; - VDM_SEL: buffer std_logic_vector(3 downto 0); - FB_AD: inout std_logic_vector(31 downto 0) +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.std_logic_arith.all; +ENTITY ddr_ctr IS + PORT + ( + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + DDR_SYNC_66M : IN std_logic; + CLR_FIFO : IN std_logic; + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); + BLITTER_SIG : IN std_logic; + BLITTER_WR : IN std_logic; + DDRCLK0 : IN std_logic; + CLK33M : IN std_logic; + FIFO_MW : IN std_logic_vector(8 DOWNTO 0); + VA : BUFFER std_logic_vector(12 DOWNTO 0); + nVWE : BUFFER std_logic; + nVRAS : BUFFER std_logic; + nVCS : BUFFER std_logic; + VCKE : BUFFER std_logic; + nVCAS : BUFFER std_logic; + FB_LE : BUFFER std_logic_vector(3 DOWNTO 0); + FB_VDOE : BUFFER std_logic_vector(3 DOWNTO 0); + SR_FIFO_WRE : BUFFER std_logic; + SR_DDR_FB : BUFFER std_logic; + SR_DDR_WR : BUFFER std_logic; + SR_DDRWR_D_SEL : BUFFER std_logic; + SR_VDMP : BUFFER std_logic_vector(7 DOWNTO 0); + VIDEO_DDR_TA : BUFFER std_logic; + SR_BLITTER_DACK : BUFFER std_logic; + BA : BUFFER std_logic_vector(1 DOWNTO 0); + DDRWR_D_SEL1 : BUFFER std_logic; + VDM_SEL : BUFFER std_logic_vector(3 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0) ); -end DDR_CTR; +END ddr_ctr; -architecture DDR_CTR_behav of DDR_CTR is - --- START (NORMAL 8 CYCLES TOTAL = 60ns) --- CONFIG --- READ CPU UND BLITTER, --- WRITE CPU UND BLITTER --- READ FIFO --- CLOSE FIFO BANK --- REFRESH 10X7.5NS=75NS - signal FB_REGDDR_3: std_logic_vector(2 downto 0); - signal FB_REGDDR_d: std_logic_vector(2 downto 0); - signal FB_REGDDR_q: std_logic_vector(2 downto 0); - signal DDR_SM_6: std_logic_vector(5 downto 0); - signal DDR_SM_d: std_logic_vector(5 downto 0); - signal DDR_SM_q: std_logic_vector(5 downto 0); - signal FB_B: std_logic_vector(3 downto 0); - signal VA_P: std_logic_vector(12 downto 0); - signal VA_P_d: std_logic_vector(12 downto 0); - signal VA_P_q: std_logic_vector(12 downto 0); - signal BA_P: std_logic_vector(1 downto 0); - signal BA_P_d: std_logic_vector(1 downto 0); - signal BA_P_q: std_logic_vector(1 downto 0); - signal VA_S: std_logic_vector(12 downto 0); - signal VA_S_d: std_logic_vector(12 downto 0); - signal VA_S_q: std_logic_vector(12 downto 0); - signal BA_S: std_logic_vector(1 downto 0); - signal BA_S_d: std_logic_vector(1 downto 0); - signal BA_S_q: std_logic_vector(1 downto 0); - signal MCS: std_logic_vector(1 downto 0); - signal MCS_d: std_logic_vector(1 downto 0); - signal MCS_q: std_logic_vector(1 downto 0); - signal SR_VDMP_d: std_logic_vector(7 downto 0); - signal SR_VDMP_q: std_logic_vector(7 downto 0); - signal CPU_ROW_ADR: std_logic_vector(12 downto 0); - signal CPU_BA: std_logic_vector(1 downto 0); - signal CPU_COL_ADR: std_logic_vector(9 downto 0); - signal BLITTER_ROW_ADR: std_logic_vector(12 downto 0); - signal BLITTER_BA: std_logic_vector(1 downto 0); - signal BLITTER_COL_ADR: std_logic_vector(9 downto 0); - signal FIFO_ROW_ADR: std_logic_vector(12 downto 0); - signal FIFO_BA: std_logic_vector(1 downto 0); - signal FIFO_COL_ADR: std_logic_vector(9 downto 0); - signal DDR_REFRESH_CNT: std_logic_vector(10 downto 0); - signal DDR_REFRESH_CNT_d: std_logic_vector(10 downto 0); - signal DDR_REFRESH_CNT_q: std_logic_vector(10 downto 0); - signal DDR_REFRESH_SIG: std_logic_vector(3 downto 0); - signal DDR_REFRESH_SIG_d: std_logic_vector(3 downto 0); - signal DDR_REFRESH_SIG_q: std_logic_vector(3 downto 0); - signal VIDEO_BASE_L_D: std_logic_vector(7 downto 0); - signal VIDEO_BASE_L_D_d: std_logic_vector(7 downto 0); - signal VIDEO_BASE_L_D_q: std_logic_vector(7 downto 0); - signal VIDEO_BASE_M_D: std_logic_vector(7 downto 0); - signal VIDEO_BASE_M_D_d: std_logic_vector(7 downto 0); - signal VIDEO_BASE_M_D_q: std_logic_vector(7 downto 0); - signal VIDEO_BASE_H_D: std_logic_vector(7 downto 0); - signal VIDEO_BASE_H_D_d: std_logic_vector(7 downto 0); - signal VIDEO_BASE_H_D_q: std_logic_vector(7 downto 0); - signal VIDEO_BASE_X_D: std_logic_vector(2 downto 0); - signal VIDEO_BASE_X_D_d: std_logic_vector(2 downto 0); - signal VIDEO_BASE_X_D_q: std_logic_vector(2 downto 0); - signal VIDEO_ADR_CNT: std_logic_vector(22 downto 0); - signal VIDEO_ADR_CNT_d: std_logic_vector(22 downto 0); - signal VIDEO_ADR_CNT_q: std_logic_vector(22 downto 0); - signal VIDEO_BASE_ADR: std_logic_vector(22 downto 0); - signal VIDEO_ACT_ADR: std_logic_vector(26 downto 0); - signal u0_data: std_logic_vector(7 downto 0); - signal u0_tridata: std_logic_vector(7 downto 0); - signal FB_REGDDR_0_clk_ctrl, SR_VDMP0_clk_ctrl, MCS0_clk_ctrl, - VA_S0_clk_ctrl, BA_S0_clk_ctrl, VA_P0_clk_ctrl, BA_P0_clk_ctrl, - DDR_SM_0_clk_ctrl, VIDEO_ADR_CNT0_clk_ctrl, VIDEO_ADR_CNT0_ena_ctrl, - DDR_REFRESH_CNT0_clk_ctrl, DDR_REFRESH_SIG0_clk_ctrl, - DDR_REFRESH_SIG0_ena_ctrl, VIDEO_BASE_L_D0_clk_ctrl, - VIDEO_BASE_L_D0_ena_ctrl, VIDEO_BASE_M_D0_clk_ctrl, - VIDEO_BASE_M_D0_ena_ctrl, VIDEO_BASE_H_D0_clk_ctrl, - VIDEO_BASE_H_D0_ena_ctrl, VIDEO_BASE_X_D0_clk_ctrl, - VIDEO_BASE_X_D0_ena_ctrl, VA12_2, VA12_1, VA11_2, VA11_1, VA10_2, - VA10_1, VA9_2, VA9_1, VA8_2, VA8_1, VA7_2, VA7_1, VA6_2, VA6_1, VA5_2, - VA5_1, VA4_2, VA4_1, VA3_2, VA3_1, VA2_2, VA2_1, VA1_2, VA1_1, VA0_2, - VA0_1, BA1_2, BA1_1, BA0_2, BA0_1, BUS_CYC_d_2, BUS_CYC_d_1, - FIFO_BANK_OK_d_2, FIFO_BANK_OK_d_1, u0_enabledt, gnd, vcc, - VIDEO_CNT_H, VIDEO_CNT_M, VIDEO_CNT_L, VIDEO_BASE_H, VIDEO_BASE_M, - VIDEO_BASE_L, REFRESH_TIME_q, REFRESH_TIME_clk, REFRESH_TIME_d, - REFRESH_TIME, DDR_REFRESH_REQ_q, DDR_REFRESH_REQ_clk, - DDR_REFRESH_REQ_d, DDR_REFRESH_REQ, DDR_REFRESH_ON, FIFO_BANK_NOT_OK, - FIFO_BANK_OK_q, FIFO_BANK_OK_clk, FIFO_BANK_OK_d, FIFO_BANK_OK, - SR_FIFO_WRE_q, SR_FIFO_WRE_clk, SR_FIFO_WRE_d, STOP_q, STOP_clk, - STOP_d, STOP, CLEAR_FIFO_CNT_q, CLEAR_FIFO_CNT_clk, CLEAR_FIFO_CNT_d, - CLEAR_FIFO_CNT, CLR_FIFO_SYNC_q, CLR_FIFO_SYNC_clk, CLR_FIFO_SYNC_d, - CLR_FIFO_SYNC, FIFO_ACTIVE, FIFO_AC_q, FIFO_AC_clk, FIFO_AC_d, - FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, +ARCHITECTURE rtl OF ddr_ctr IS + -- START (NORMAL 8 CYCLES TOTAL = 60ns) + -- CONFIG + -- READ CPU UND BLITTER, + -- WRITE CPU UND BLITTER + -- READ FIFO + -- CLOSE FIFO BANK + -- REFRESH 10X7.5NfS=75NS + SIGNAL FB_REGDDR_3 : std_logic_vector(2 DOWNTO 0); + SIGNAL FB_REGDDR_d : std_logic_vector(2 DOWNTO 0); + SIGNAL FB_REGDDR_q : std_logic_vector(2 DOWNTO 0); + SIGNAL DDR_SM_6 : std_logic_vector(5 DOWNTO 0); + SIGNAL DDR_SM_d : std_logic_vector(5 DOWNTO 0); + SIGNAL DDR_SM_q : std_logic_vector(5 DOWNTO 0); + SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); + SIGNAL VA_P : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_P_d : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_P_q : std_logic_vector(12 DOWNTO 0); + SIGNAL BA_P : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_P_d : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_P_q : std_logic_vector(1 DOWNTO 0); + SIGNAL VA_S : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_S_d : std_logic_vector(12 DOWNTO 0); + SIGNAL VA_S_q : std_logic_vector(12 DOWNTO 0); + SIGNAL BA_S : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_S_d : std_logic_vector(1 DOWNTO 0); + SIGNAL BA_S_q : std_logic_vector(1 DOWNTO 0); + SIGNAL MCS : std_logic_vector(1 DOWNTO 0); + SIGNAL MCS_d : std_logic_vector(1 DOWNTO 0); + SIGNAL MCS_q : std_logic_vector(1 DOWNTO 0); + SIGNAL SR_VDMP_d : std_logic_vector(7 DOWNTO 0); + SIGNAL SR_VDMP_q : std_logic_vector(7 DOWNTO 0); + SIGNAL CPU_ROW_ADR : std_logic_vector(12 DOWNTO 0); + SIGNAL CPU_BA : std_logic_vector(1 DOWNTO 0); + SIGNAL CPU_COL_ADR : std_logic_vector(9 DOWNTO 0); + SIGNAL BLITTER_ROW_ADR : std_logic_vector(12 DOWNTO 0); + SIGNAL BLITTER_BA : std_logic_vector(1 DOWNTO 0); + SIGNAL BLITTER_COL_ADR : std_logic_vector(9 DOWNTO 0); + SIGNAL FIFO_ROW_ADR : std_logic_vector(12 DOWNTO 0); + SIGNAL FIFO_BA : std_logic_vector(1 DOWNTO 0); + SIGNAL FIFO_COL_ADR : std_logic_vector(9 DOWNTO 0); + SIGNAL DDR_REFRESH_CNT : std_logic_vector(10 DOWNTO 0); + SIGNAL DDR_REFRESH_CNT_d : std_logic_vector(10 DOWNTO 0); + SIGNAL DDR_REFRESH_CNT_q : std_logic_vector(10 DOWNTO 0); + SIGNAL DDR_REFRESH_SIG : std_logic_vector(3 DOWNTO 0); + SIGNAL DDR_REFRESH_SIG_d : std_logic_vector(3 DOWNTO 0); + SIGNAL DDR_REFRESH_SIG_q : std_logic_vector(3 DOWNTO 0); + SIGNAL VIDEO_BASE_L_D : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_L_D_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_L_D_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_M_D : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_M_D_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_M_D_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_H_D : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_H_D_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_H_D_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VIDEO_BASE_X_D : std_logic_vector(2 DOWNTO 0); + SIGNAL VIDEO_BASE_X_D_d : std_logic_vector(2 DOWNTO 0); + SIGNAL VIDEO_BASE_X_D_q : std_logic_vector(2 DOWNTO 0); + SIGNAL VIDEO_ADR_CNT : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_ADR_CNT_d : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_ADR_CNT_q : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_BASE_ADR : std_logic_vector(22 DOWNTO 0); + SIGNAL VIDEO_ACT_ADR : std_logic_vector(26 DOWNTO 0); + SIGNAL u0_data : std_logic_vector(7 DOWNTO 0); + SIGNAL u0_tridata : std_logic_vector(7 DOWNTO 0); + SIGNAL FB_REGDDR_0_clk_ctrl : std_logic; + SIGNAL SR_VDMP0_clk_ctrl : std_logic; + SIGNAL MCS0_clk_ctrl : std_logic; + SIGNAL VA_S0_clk_ctrl : std_logic; + SIGNAL BA_S0_clk_ctrl : std_logic; + SIGNAL VA_P0_clk_ctrl : std_logic; + SIGNAL BA_P0_clk_ctrl : std_logic; + SIGNAL DDR_SM_0_clk_ctrl : std_logic; + SIGNAL VIDEO_ADR_CNT0_clk_ctrl : std_logic; + SIGNAL VIDEO_ADR_CNT0_ena_ctrl : std_logic; + SIGNAL DDR_REFRESH_CNT0_clk_ctrl : std_logic; + SIGNAL DDR_REFRESH_SIG0_clk_ctrl : std_logic; + SIGNAL DDR_REFRESH_SIG0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_L_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_L_D0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_M_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_M_D0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_H_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_H_D0_ena_ctrl : std_logic; + SIGNAL VIDEO_BASE_X_D0_clk_ctrl : std_logic; + SIGNAL VIDEO_BASE_X_D0_ena_ctrl : std_logic; + SIGNAL VA12_2 : std_logic; + SIGNAL VA12_1 : std_logic; + SIGNAL VA11_2 : std_logic; + SIGNAL VA11_1 : std_logic; + SIGNAL VA10_2 : std_logic; + SIGNAL VA10_1 : std_logic; + SIGNAL VA9_2 : std_logic; + SIGNAL VA9_1 : std_logic; + SIGNAL VA8_2 : std_logic; + SIGNAL VA8_1 : std_logic; + SIGNAL VA7_2 : std_logic; + SIGNAL VA7_1 : std_logic; + SIGNAL VA6_2 : std_logic; + SIGNAL VA6_1 : std_logic; + SIGNAL VA5_2 : std_logic; + SIGNAL VA5_1 : std_logic; + SIGNAL VA4_2 : std_logic; + SIGNAL VA4_1 : std_logic; + SIGNAL VA3_2 : std_logic; + SIGNAL VA3_1 : std_logic; + SIGNAL VA2_2 : std_logic; + SIGNAL VA2_1 : std_logic; + SIGNAL VA1_2 : std_logic; + SIGNAL VA1_1 : std_logic; + SIGNAL VA0_2 : std_logic; + SIGNAL VA0_1 : std_logic; + SIGNAL BA1_2 : std_logic; + SIGNAL BA1_1 : std_logic; + SIGNAL BA0_2 : std_logic; + SIGNAL BA0_1 : std_logic; + SIGNAL BUS_CYC_d_2 : std_logic; + SIGNAL BUS_CYC_d_1 : std_logic; + SIGNAL FIFO_BANK_OK_d_2 : std_logic; + SIGNAL FIFO_BANK_OK_d_1 : std_logic; + SIGNAL u0_enabledt : std_logic; + SiGNAL gnd : std_logic; + SIGNAL vcc : std_logic; + SIGNAL VIDEO_CNT_H : std_logic; + SIGNAL VIDEO_CNT_M : std_logic; + SIGNAL VIDEO_CNT_L : std_logic; + SIGNAL VIDEO_BASE_H : std_logic; + SIGNAL VIDEO_BASE_M : std_logic; + SIGNAL VIDEO_BASE_L : std_logic; + SIGNAL REFRESH_TIME_q : std_logic; + SIGNAL REFRESH_TIME_clk : std_logic; + SIGNAL REFRESH_TIME_d : std_logic; + SIGNAL REFRESH_TIME : std_logic; + SIGNAL DDR_REFRESH_REQ_q : std_logic; + SIGNAL DDR_REFRESH_REQ_clk : std_logic; + SIGNAL DDR_REFRESH_REQ_d : std_logic; + SIGNAL DDR_REFRESH_REQ : std_logic; + SIGNAL DDR_REFRESH_ON : std_logic; + SIGNAL FIFO_BANK_NOT_OK : std_logic; + SIGNAL FIFO_BANK_OK_q : std_logic; + SIGNAL FIFO_BANK_OK_clk : std_logic; + SIGNAL FIFO_BANK_OK_d : std_logic; + SIGNAL FIFO_BANK_OK : std_logic; + SiGNAL SR_FIFO_WRE_q : std_logic; + SIGNAL SR_FIFO_WRE_clk : std_logic; + SIGNAL SR_FIFO_WRE_d : std_logic; + SIGNAL STOP_q : std_logic; + SIGNAL STOP_clk : std_logic; + SIGNAL STOP_d : std_logic; + SIGNAL STOP : std_logic; + SIGNAL CLEAR_FIFO_CNT_q : std_logic; + SIGNAL CLEAR_FIFO_CNT_clk : std_logic; + SIGNAL CLEAR_FIFO_CNT_d : std_logic; + SIGNAL CLEAR_FIFO_CNT : std_logic; + SIGNAL CLR_FIFO_SYNC_q : std_logic; + SIGNAL CLR_FIFO_SYNC_clk : std_logic; + SIGNAL CLR_FIFO_SYNC_d : std_logic; + SIGNAL CLR_FIFO_SYNC : std_logic; + SIGNAL FIFO_ACTIVE : std_logic; + SIGNAL FIFO_AC_q : std_logic; + SIGNAL FIFO_AC_clk : std_logic; + SIGNAL FIFO_AC_d : std_logic; + SIGNAL FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, BLITTER_AC_clk, BLITTER_AC_d, BLITTER_AC, BLITTER_REQ_q, BLITTER_REQ_clk, BLITTER_REQ_d, BLITTER_REQ, BUS_CYC_END, BUS_CYC_q, BUS_CYC_clk, BUS_CYC_d, BUS_CYC, CPU_AC_q, CPU_AC_clk, CPU_AC_d, @@ -151,26 +244,26 @@ architecture DDR_CTR_behav of DDR_CTR is component lpm_bustri_BYT Port ( - data: in std_logic_vector(7 downto 0); + data: in std_logic_vector(7 DOWNTO 0); enabledt: in std_logic; - tridata: buffer std_logic_vector(7 downto 0) + tridata: buffer std_logic_vector(7 DOWNTO 0) ); - end component; + END component; - Function to_std_logic(X: in Boolean) return Std_Logic is - variable ret : std_logic; - begin - if x then ret := '1'; else ret := '0'; end if; + Function to_std_logic(X: in Boolean) return Std_Logic IS + VARIABLE ret : std_logic; + BEGIN + IF x THEN ret := '1'; ELSE ret := '0'; END IF; return ret; - end to_std_logic; + END to_std_logic; -- sizeIt replicates a value to an array of specific length. - Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is - variable rep: std_logic_vector( len-1 downto 0); - begin for i in rep'range loop rep(i) := a; end loop; return rep; - end sizeIt; -begin + Function sizeIt(a: std_Logic; len: integer) return std_logic_vector IS + VARIABLE rep: std_logic_vector( len-1 DOWNTO 0); + BEGIN for i in rep'range loop rep(i) := a; END loop; return rep; + END sizeIt; +BEGIN -- Sub Module Section u0: lpm_bustri_BYT port map (data=>u0_data, enabledt=>u0_enabledt, @@ -179,220 +272,220 @@ begin -- Register Section SR_FIFO_WRE <= SR_FIFO_WRE_q; - process (SR_FIFO_WRE_clk) begin - if SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' then + PROCESS (SR_FIFO_WRE_clk) BEGIN + IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN SR_FIFO_WRE_q <= SR_FIFO_WRE_d; - end if; - end process; + END IF; + END PROCESS; SR_DDR_WR <= SR_DDR_WR_q; - process (SR_DDR_WR_clk) begin - if SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' then + PROCESS (SR_DDR_WR_clk) BEGIN + IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN SR_DDR_WR_q <= SR_DDR_WR_d; - end if; - end process; + END IF; + END PROCESS; SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; - process (SR_DDRWR_D_SEL_clk) begin - if SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' then + PROCESS (SR_DDRWR_D_SEL_clk) BEGIN + IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; - end if; - end process; + END IF; + END PROCESS; SR_VDMP <= SR_VDMP_q; - process (SR_VDMP0_clk_ctrl) begin - if SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' then + PROCESS (SR_VDMP0_clk_ctrl) BEGIN + IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN SR_VDMP_q <= SR_VDMP_d; - end if; - end process; + END IF; + END PROCESS; - process (FB_REGDDR_0_clk_ctrl) begin - if FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' then + PROCESS (FB_REGDDR_0_clk_ctrl) BEGIN + IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN FB_REGDDR_q <= FB_REGDDR_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_SM_0_clk_ctrl) begin - if DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' then + PROCESS (DDR_SM_0_clk_ctrl) BEGIN + IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN DDR_SM_q <= DDR_SM_d; - end if; - end process; + END IF; + END PROCESS; - process (VA_P0_clk_ctrl) begin - if VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' then + PROCESS (VA_P0_clk_ctrl) BEGIN + IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN VA_P_q <= VA_P_d; - end if; - end process; + END IF; + END PROCESS; - process (BA_P0_clk_ctrl) begin - if BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' then + PROCESS (BA_P0_clk_ctrl) BEGIN + IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN BA_P_q <= BA_P_d; - end if; - end process; + END IF; + END PROCESS; - process (VA_S0_clk_ctrl) begin - if VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' then + PROCESS (VA_S0_clk_ctrl) BEGIN + IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN VA_S_q <= VA_S_d; - end if; - end process; + END IF; + END PROCESS; - process (BA_S0_clk_ctrl) begin - if BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' then + PROCESS (BA_S0_clk_ctrl) BEGIN + IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN BA_S_q <= BA_S_d; - end if; - end process; + END IF; + END PROCESS; - process (MCS0_clk_ctrl) begin - if MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' then + PROCESS (MCS0_clk_ctrl) BEGIN + IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN MCS_q <= MCS_d; - end if; - end process; + END IF; + END PROCESS; - process (CPU_DDR_SYNC_clk) begin - if CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' then + PROCESS (CPU_DDR_SYNC_clk) BEGIN + IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_CS_clk) begin - if DDR_CS_clk'event and DDR_CS_clk='1' then - if DDR_CS_ena='1' then + PROCESS (DDR_CS_clk) BEGIN + IF DDR_CS_clk'event and DDR_CS_clk='1' THEN + IF DDR_CS_ena='1' THEN DDR_CS_q <= DDR_CS_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (CPU_REQ_clk) begin - if CPU_REQ_clk'event and CPU_REQ_clk='1' then + PROCESS (CPU_REQ_clk) BEGIN + IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN CPU_REQ_q <= CPU_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (CPU_AC_clk) begin - if CPU_AC_clk'event and CPU_AC_clk='1' then + PROCESS (CPU_AC_clk) BEGIN + IF CPU_AC_clk'event and CPU_AC_clk='1' THEN CPU_AC_q <= CPU_AC_d; - end if; - end process; + END IF; + END PROCESS; - process (BUS_CYC_clk) begin - if BUS_CYC_clk'event and BUS_CYC_clk='1' then + PROCESS (BUS_CYC_clk) BEGIN + IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN BUS_CYC_q <= BUS_CYC_d; - end if; - end process; + END IF; + END PROCESS; - process (BLITTER_REQ_clk) begin - if BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' then + PROCESS (BLITTER_REQ_clk) BEGIN + IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN BLITTER_REQ_q <= BLITTER_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (BLITTER_AC_clk) begin - if BLITTER_AC_clk'event and BLITTER_AC_clk='1' then + PROCESS (BLITTER_AC_clk) BEGIN + IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN BLITTER_AC_q <= BLITTER_AC_d; - end if; - end process; + END IF; + END PROCESS; - process (FIFO_REQ_clk) begin - if FIFO_REQ_clk'event and FIFO_REQ_clk='1' then + PROCESS (FIFO_REQ_clk) BEGIN + IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN FIFO_REQ_q <= FIFO_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (FIFO_AC_clk) begin - if FIFO_AC_clk'event and FIFO_AC_clk='1' then + PROCESS (FIFO_AC_clk) BEGIN + IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN FIFO_AC_q <= FIFO_AC_d; - end if; - end process; + END IF; + END PROCESS; - process (CLR_FIFO_SYNC_clk) begin - if CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' then + PROCESS (CLR_FIFO_SYNC_clk) BEGIN + IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; - end if; - end process; + END IF; + END PROCESS; - process (CLEAR_FIFO_CNT_clk) begin - if CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' then + PROCESS (CLEAR_FIFO_CNT_clk) BEGIN + IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; - end if; - end process; + END IF; + END PROCESS; - process (STOP_clk) begin - if STOP_clk'event and STOP_clk='1' then + PROCESS (STOP_clk) BEGIN + IF STOP_clk'event and STOP_clk='1' THEN STOP_q <= STOP_d; - end if; - end process; + END IF; + END PROCESS; - process (FIFO_BANK_OK_clk) begin - if FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' then + PROCESS (FIFO_BANK_OK_clk) BEGIN + IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN FIFO_BANK_OK_q <= FIFO_BANK_OK_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_REFRESH_CNT0_clk_ctrl) begin - if DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' then + PROCESS (DDR_REFRESH_CNT0_clk_ctrl) BEGIN + IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_REFRESH_REQ_clk) begin - if DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' then + PROCESS (DDR_REFRESH_REQ_clk) BEGIN + IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; - end if; - end process; + END IF; + END PROCESS; - process (DDR_REFRESH_SIG0_clk_ctrl) begin - if DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' then - if DDR_REFRESH_SIG0_ena_ctrl='1' then + PROCESS (DDR_REFRESH_SIG0_clk_ctrl) BEGIN + IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN + IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (REFRESH_TIME_clk) begin - if REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' then + PROCESS (REFRESH_TIME_clk) BEGIN + IF REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' THEN REFRESH_TIME_q <= REFRESH_TIME_d; - end if; - end process; + END IF; + END PROCESS; - process (VIDEO_BASE_L_D0_clk_ctrl) begin - if VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' then - if VIDEO_BASE_L_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_L_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_BASE_M_D0_clk_ctrl) begin - if VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' then - if VIDEO_BASE_M_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_M_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_BASE_H_D0_clk_ctrl) begin - if VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' then - if VIDEO_BASE_H_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_H_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_BASE_X_D0_clk_ctrl) begin - if VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' then - if VIDEO_BASE_X_D0_ena_ctrl='1' then + PROCESS (VIDEO_BASE_X_D0_clk_ctrl) BEGIN + IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VIDEO_ADR_CNT0_clk_ctrl) begin - if VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' then - if VIDEO_ADR_CNT0_ena_ctrl='1' then + PROCESS (VIDEO_ADR_CNT0_clk_ctrl) BEGIN + IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN + IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; -- Start of original equations LINE <= FB_SIZE0 and FB_SIZE1; @@ -400,25 +493,25 @@ begin -- BYT SELECT -- ADR==0 -- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and + FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not + FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and + FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not + FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); @@ -426,741 +519,737 @@ begin FB_REGDDR_0_clk_ctrl <= MAIN_CLK; - process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, - DDR_CONFIG, nFB_WR, vcc) - variable stdVec3: std_logic_vector(2 downto 0); - begin - FB_REGDDR_d <= FB_REGDDR_q; - (FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); - (FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), - VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); - stdVec3 := FB_REGDDR_q; - case stdVec3 is - when "000" => - FB_LE(0) <= not nFB_WR; + PROCESS (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) + VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0); + BEGIN + FB_REGDDR_d <= FB_REGDDR_q; + (FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); + (FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), + VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); + stdVec3 := FB_REGDDR_q; + CASE stdVec3 IS + WHEN "000" => + FB_LE(0) <= not nFB_WR; + -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' THEN + FB_REGDDR_d <= "001"; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "001" => + IF (DDR_CS_q)='1' THEN + FB_LE(0) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + IF (LINE)='1' THEN + FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); + FB_REGDDR_d <= "010"; + ELSE + BUS_CYC_END <= vcc; + FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); + FB_REGDDR_d <= "000"; + END IF; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "010" => + IF (DDR_CS_q)='1' THEN + FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); + FB_LE(1) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + FB_REGDDR_d <= "011"; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "011" => + IF (DDR_CS_q)='1' THEN + FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); + FB_LE(2) <= not nFB_WR; --- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' then - FB_REGDDR_d <= "001"; - else - FB_REGDDR_d <= "000"; - end if; - when "001" => - if (DDR_CS_q)='1' then - FB_LE(0) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - if (LINE)='1' then - FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); - FB_REGDDR_d <= "010"; - else - BUS_CYC_END <= vcc; - FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not - DDR_CONFIG); - FB_REGDDR_d <= "000"; - end if; - else - FB_REGDDR_d <= "000"; - end if; - when "010" => - if (DDR_CS_q)='1' then - FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(1) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - FB_REGDDR_d <= "011"; - else - FB_REGDDR_d <= "000"; - end if; - when "011" => - if (DDR_CS_q)='1' then - FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(2) <= not nFB_WR; + -- BEI LINE WRITE EVT. WARTEN + IF ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' THEN + FB_REGDDR_d <= "011"; + ELSE + VIDEO_DDR_TA <= vcc; + FB_REGDDR_d <= "100"; + END IF; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN "100" => + IF (DDR_CS_q)='1' THEN + FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); + FB_LE(3) <= not nFB_WR; + VIDEO_DDR_TA <= vcc; + BUS_CYC_END <= vcc; + FB_REGDDR_d <= "000"; + ELSE + FB_REGDDR_d <= "000"; + END IF; + + WHEN others => + END CASE; + stdVec3 := (others=>'0'); -- no storage needed + END PROCESS; --- BEI LINE WRITE EVT. WARTEN - if ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' then - FB_REGDDR_d <= "011"; - else - VIDEO_DDR_TA <= vcc; - FB_REGDDR_d <= "100"; - end if; - else - FB_REGDDR_d <= "000"; - end if; - when "100" => - if (DDR_CS_q)='1' then - FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); - FB_LE(3) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - BUS_CYC_END <= vcc; - FB_REGDDR_d <= "000"; - else - FB_REGDDR_d <= "000"; - end if; - when others => - end case; - stdVec3 := (others=>'0'); -- no storage needed - end process; + -- DDR STEUERUNG ----------------------------------------------------- + -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE <= VIDEO_RAM_CTR(0); + nVCS <= not VIDEO_RAM_CTR(1); + DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); + DDR_CONFIG <= VIDEO_RAM_CTR(3); + FIFO_ACTIVE <= VIDEO_RAM_CTR(8); --- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE <= VIDEO_RAM_CTR(0); - nVCS <= not VIDEO_RAM_CTR(1); - DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); - DDR_CONFIG <= VIDEO_RAM_CTR(3); - FIFO_ACTIVE <= VIDEO_RAM_CTR(8); + -- ------------------------------ + CPU_ROW_ADR <= FB_ADR(26 DOWNTO 14); + CPU_BA <= FB_ADR(13 DOWNTO 12); + CPU_COL_ADR <= FB_ADR(11 DOWNTO 2); + nVRAS <= not VRAS; + nVCAS <= not VCAS; + nVWE <= not VWE; + SR_DDR_WR_clk <= DDRCLK0; + SR_DDRWR_D_SEL_clk <= DDRCLK0; + SR_VDMP0_clk_ctrl <= DDRCLK0; + SR_FIFO_WRE_clk <= DDRCLK0; + CPU_AC_clk <= DDRCLK0; + FIFO_AC_clk <= DDRCLK0; + BLITTER_AC_clk <= DDRCLK0; + DDRWR_D_SEL1 <= BLITTER_AC_q; --- ------------------------------ - CPU_ROW_ADR <= FB_ADR(26 downto 14); - CPU_BA <= FB_ADR(13 downto 12); - CPU_COL_ADR <= FB_ADR(11 downto 2); - nVRAS <= not VRAS; - nVCAS <= not VCAS; - nVWE <= not VWE; - SR_DDR_WR_clk <= DDRCLK0; - SR_DDRWR_D_SEL_clk <= DDRCLK0; - SR_VDMP0_clk_ctrl <= DDRCLK0; - SR_FIFO_WRE_clk <= DDRCLK0; - CPU_AC_clk <= DDRCLK0; - FIFO_AC_clk <= DDRCLK0; - BLITTER_AC_clk <= DDRCLK0; - DDRWR_D_SEL1 <= BLITTER_AC_q; + -- SELECT LOGIC + DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 DOWNTO 30) = "01"); + DDR_CS_clk <= MAIN_CLK; + DDR_CS_ena <= FB_ALE; + DDR_CS_d <= DDR_SEL; --- SELECT LOGIC - DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); - DDR_CS_clk <= MAIN_CLK; - DDR_CS_ena <= FB_ALE; - DDR_CS_d <= DDR_SEL; + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + -- CONFIG SOFORT LOS + -- LINE WRITE SPÄTER + CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or + (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and (not nFB_WR)); + CPU_REQ_clk <= DDR_SYNC_66M; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER --- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG --- CONFIG SOFORT LOS --- LINE WRITE SPÄTER - CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or - (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and - (not nFB_WR)); - CPU_REQ_clk <= DDR_SYNC_66M; - --- HALTEN BUS CYC BEGONNEN ODER FERTIG - CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" + -- HALTEN BUS CYC BEGONNEN ODER FERTIG + CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" and FB_REGDDR_q /= "100") and (not BUS_CYC_END) and (not BUS_CYC_q)); - BUS_CYC_clk <= DDRCLK0; - BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); + BUS_CYC_clk <= DDRCLK0; + BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); --- STATE MACHINE SYNCHRONISIEREN ----------------- - MCS0_clk_ctrl <= DDRCLK0; - MCS_d(0) <= MAIN_CLK; - MCS_d(1) <= MCS_q(0); - CPU_DDR_SYNC_clk <= DDRCLK0; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS0_clk_ctrl <= DDRCLK0; + MCS_d(0) <= MAIN_CLK; + MCS_d(1) <= MCS_q(0); + CPU_DDR_SYNC_clk <= DDRCLK0; --- NUR 1 WENN EIN - CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); + -- NUR 1 WENN EIN + CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); --- ------------------------------------------------- - VA_S0_clk_ctrl <= DDRCLK0; - BA_S0_clk_ctrl <= DDRCLK0; - (VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1, VA3_1, + -- ------------------------------------------------- + VA_S0_clk_ctrl <= DDRCLK0; + BA_S0_clk_ctrl <= DDRCLK0; + (VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1, VA3_1, VA2_1, VA1_1, VA0_1) <= VA_S_q; - (BA1_1, BA0_1) <= BA_S_q; - VA_P0_clk_ctrl <= DDRCLK0; - BA_P0_clk_ctrl <= DDRCLK0; + (BA1_1, BA0_1) <= BA_S_q; + VA_P0_clk_ctrl <= DDRCLK0; + BA_P0_clk_ctrl <= DDRCLK0; --- DDR STATE MACHINE ----------------------------------------------- - DDR_SM_0_clk_ctrl <= DDRCLK0; + -- DDR STATE MACHINE ----------------------------------------------- + DDR_SM_0_clk_ctrl <= DDRCLK0; - process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, + PROCESS (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, VIDEO_ADR_CNT_q, FIFO_COL_ADR, gnd, DDR_SEL, LINE, FIFO_BA, VA_P_q, BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, DDR_REFRESH_SIG_q, vcc) - variable stdVec6: std_logic_vector(5 downto 0); - begin - DDR_SM_d <= DDR_SM_q; - BA_S_d <= "00"; - VA_S_d <= "0000000000000"; - BA_P_d <= "00"; - (VA_P_d(9), VA_P_d(8), VA_P_d(7), VA_P_d(6), VA_P_d(5), VA_P_d(4), - VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= - std_logic_vector'("00000000000"); - SR_VDMP_d <= "00000000"; - VA_P_d(12 downto 11) <= "00"; - (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, + VARIABLE stdVec6: std_logic_vector(5 DOWNTO 0); + BEGIN + DDR_SM_d <= DDR_SM_q; + BA_S_d <= "00"; + VA_S_d <= "0000000000000"; + BA_P_d <= "00"; + (VA_P_d(9), VA_P_d(8), VA_P_d(7), VA_P_d(6), VA_P_d(5), VA_P_d(4), + VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= + std_logic_vector'("00000000000"); + SR_VDMP_d <= "00000000"; + VA_P_d(12 DOWNTO 11) <= "00"; + (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2, FIFO_BANK_NOT_OK, VCAS, VRAS) <= std_logic_vector'("00000000000000000000000000000"); - stdVec6 := DDR_SM_q; - case stdVec6 is - when "000000" => - if (DDR_REFRESH_REQ_q)='1' then - DDR_SM_d <= "011111"; - --- SYNCHRON UND EIN? - elsif (CPU_DDR_SYNC_q)='1' then - --- JA - if (DDR_CONFIG)='1' then - DDR_SM_d <= "001000"; - --- BEI WAIT UND LINE WRITE - elsif (CPU_REQ_q)='1' then - VA_S_d <= CPU_ROW_ADR; - BA_S_d <= CPU_BA; - CPU_AC_d <= vcc; - BUS_CYC_d_2 <= vcc; - DDR_SM_d <= "000010"; - else - --- FIFO IST DEFAULT - if (FIFO_REQ_q or (not BLITTER_REQ_q))='1' then - VA_P_d <= FIFO_ROW_ADR; - BA_P_d <= FIFO_BA; - --- VORBESETZEN - FIFO_AC_d <= vcc; - else - VA_P_d <= BLITTER_ROW_ADR; - BA_P_d <= BLITTER_BA; - --- VORBESETZEN - BLITTER_AC_d <= vcc; - end if; - DDR_SM_d <= "000001"; - end if; - else - --- NEIN ->SYNCHRONISIEREN - DDR_SM_d <= "000000"; - end if; - when "000001" => - --- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - if (DDR_SEL and (nFB_WR or (not LINE)))='1' then - VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); - (BA1_2, BA0_2) <= FB_AD(13 downto 12); - --- AUTO PRECHARGE DA NICHT FIFO PAGE - VA_S_d(10) <= vcc; - CPU_AC_d <= vcc; - --- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; - else - VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and - BLITTER_REQ_q); - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; - (BA1_2, BA0_2) <= BA_P_q; - VA_S_d(10) <= not (FIFO_AC_q and FIFO_REQ_q); - FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; - FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; - BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; - end if; - DDR_SM_d <= "000011"; - when "000010" => - VRAS <= vcc; - FIFO_BANK_NOT_OK <= vcc; - CPU_AC_d <= vcc; - --- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; - DDR_SM_d <= "000011"; - when "000011" => - CPU_AC_d <= CPU_AC_q; - FIFO_AC_d <= FIFO_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- AUTO PRECHARGE WENN NICHT FIFO PAGE - VA_S_d(10) <= VA_S_q(10); - if (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' - then - DDR_SM_d <= "010000"; - --- CPU? - elsif (CPU_AC_q)='1' then - VA_S_d(9 downto 0) <= CPU_COL_ADR; - BA_S_d <= CPU_BA; - DDR_SM_d <= "001110"; - --- FIFO? - elsif (FIFO_AC_q)='1' then - VA_S_d(9 downto 0) <= FIFO_COL_ADR; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "010110"; - elsif (BLITTER_AC_q)='1' then - VA_S_d(9 downto 0) <= BLITTER_COL_ADR; - BA_S_d <= BLITTER_BA; - DDR_SM_d <= "001110"; - else - --- READ - DDR_SM_d <= "000111"; - end if; - when "001110" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - VCAS <= vcc; - --- READ DATEN FÜR CPU - SR_DDR_FB <= CPU_AC_q; - --- BLITTER DACK AND BLITTER LATCH DATEN - SR_BLITTER_DACK <= BLITTER_AC_q; - DDR_SM_d <= "001111"; - when "001111" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- FIFO READ EINSCHIEBEN WENN BANK OK - if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then - VA_S_d(9 downto 0) <= FIFO_COL_ADR; - --- MANUELL PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011000"; - else - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- WRITE - DDR_SM_d <= "011101"; - end if; - when "010000" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- BLITTER ACK AND BLITTER LATCH DATEN - SR_BLITTER_DACK <= BLITTER_AC_q; - --- AUTO PRECHARGE WENN NICHT FIFO PAGE - VA_S_d(10) <= VA_S_q(10); - DDR_SM_d <= "010001"; - when "010001" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - VA_S_d(9 downto 0) <= (sizeIt(CPU_AC_q,10) and CPU_COL_ADR) or - (sizeIt(BLITTER_AC_q,10) and BLITTER_COL_ADR); - --- AUTO PRECHARGE WENN NICHT FIFO PAGE - VA_S_d(10) <= VA_S_q(10); - BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or - (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); - --- BYTE ENABLE WRITE - SR_VDMP_d(7 downto 4) <= FB_B; - --- LINE ENABLE WRITE - SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; - DDR_SM_d <= "010010"; - when "010010" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - VCAS <= vcc; - VWE <= vcc; - --- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDR_WR_d <= vcc; - --- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_DDRWR_D_SEL_d <= vcc; - --- WENN LINE DANN ACTIV - SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; - DDR_SM_d <= "010011"; - when "010011" => - CPU_AC_d <= CPU_AC_q; - BLITTER_AC_d <= BLITTER_AC_q; - --- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDR_WR_d <= vcc; - --- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_DDRWR_D_SEL_d <= vcc; - DDR_SM_d <= "010100"; - when "010100" => - DDR_SM_d <= "010101"; - when "010101" => - if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then - VA_S_d(9 downto 0) <= FIFO_COL_ADR; - --- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011000"; - else - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- FIFO READ - DDR_SM_d <= "011101"; - end if; - when "010110" => - VCAS <= vcc; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - DDR_SM_d <= "010111"; - when "010111" => - if (FIFO_REQ_q)='1' then - --- NEUE PAGE? - if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011101"; - else - VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + - unsigned'("0000000100")); - --- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011000"; - end if; - else - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- NOCH OFFEN LASSEN - DDR_SM_d <= "011101"; - end if; - when "011000" => - VCAS <= vcc; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - DDR_SM_d <= "011001"; - when "011001" => - if CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) then - --- ALLE PAGES SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011110"; - elsif (FIFO_REQ_q)='1' then - --- NEUE PAGE? - if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then - --- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011110"; - else - VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + - unsigned'("0000000100")); - --- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; - BA_S_d <= FIFO_BA; - DDR_SM_d <= "011010"; - end if; - else - --- ALLE PAGES SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011110"; - end if; - when "011010" => - VCAS <= vcc; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - --- NOTFALL? - if (unsigned(FIFO_MW) < unsigned'("000000000")) then - --- JA-> - DDR_SM_d <= "010111"; - else - DDR_SM_d <= "011011"; - end if; - when "011011" => - if (FIFO_REQ_q)='1' then - --- NEUE PAGE? - if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then - --- ALLE BANKS SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011101"; - else - VA_P_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + - unsigned'("0000000100")); - --- NON AUTO PRECHARGE - VA_P_d(10) <= gnd; - BA_P_d <= FIFO_BA; - DDR_SM_d <= "011100"; - end if; - else - --- ALLE BANKS SCHLIESEN - VA_S_d(10) <= vcc; - --- BANK SCHLIESSEN - DDR_SM_d <= "011101"; - end if; - when "011100" => - if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= - FIFO_BA then - VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); - (BA1_2, BA0_2) <= FB_AD(13 downto 12); - CPU_AC_d <= vcc; - --- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; - --- AUTO PRECHARGE DA NICHT FIFO BANK - VA_S_d(10) <= vcc; - DDR_SM_d <= "000011"; - else - VCAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, - VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; - (BA1_2, BA0_2) <= BA_P_q; - --- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; - --- CONFIG CYCLUS - DDR_SM_d <= "011001"; - end if; - when "001000" => - DDR_SM_d <= "001001"; - when "001001" => - BUS_CYC_d_2 <= CPU_REQ_q; - DDR_SM_d <= "001010"; - when "001010" => - if (CPU_REQ_q)='1' then - DDR_SM_d <= "001011"; - else - DDR_SM_d <= "000000"; - end if; - when "001011" => - DDR_SM_d <= "001100"; - when "001100" => - VA_S_d <= FB_AD(12 downto 0); - BA_S_d <= FB_AD(14 downto 13); - DDR_SM_d <= "001101"; - when "001101" => - --- NUR BEI LONG WRITE - VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not - FB_SIZE1); - --- NUR BEI LONG WRITE - VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not - FB_SIZE1); - --- NUR BEI LONG WRITE - VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not - FB_SIZE1); - --- CLOSE FIFO BANK - DDR_SM_d <= "000111"; - when "011101" => - --- AUF NOT OK - FIFO_BANK_NOT_OK <= vcc; - --- BÄNKE SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - DDR_SM_d <= "000110"; - when "011110" => - --- AUF NOT OK - FIFO_BANK_NOT_OK <= vcc; - --- BÄNKE SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - --- REFRESH 70NS = 10 ZYCLEN - DDR_SM_d <= "000000"; - when "011111" => - --- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - if DDR_REFRESH_SIG_q = "1001" then - --- ALLE BANKS SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - VA10_2 <= vcc; - FIFO_BANK_NOT_OK <= vcc; - DDR_SM_d <= "100001"; - else - VCAS <= vcc; - VRAS <= vcc; - DDR_SM_d <= "100000"; - end if; - when "100000" => - DDR_SM_d <= "100001"; - when "100001" => - DDR_SM_d <= "100010"; - when "100010" => - DDR_SM_d <= "100011"; - when "100011" => - --- LEERSCHLAUFE - DDR_SM_d <= "000100"; - when "000100" => - DDR_SM_d <= "000101"; - when "000101" => - DDR_SM_d <= "000110"; - when "000110" => - DDR_SM_d <= "000111"; - when "000111" => - DDR_SM_d <= "000000"; - when others => - end case; - stdVec6 := (others=>'0'); -- no storage needed - end process; - --- ------------------------------------------------------------- --- BLITTER ---------------------- --- --------------------------------------- - BLITTER_REQ_clk <= DDRCLK0; - BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); - BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); - BLITTER_BA(1) <= BLITTER_ADR(13); - BLITTER_BA(0) <= BLITTER_ADR(12); - BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); - --- ---------------------------------------------------------------------------- --- FIFO --------------------------------- --- ------------------------------------------------------ - FIFO_REQ_clk <= DDRCLK0; - FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or + stdVec6 := DDR_SM_q; + + CASE stdVec6 IS + WHEN "000000" => + IF (DDR_REFRESH_REQ_q)='1' THEN + DDR_SM_d <= "011111"; + -- SYNCHRON UND EIN? + ELSIF (CPU_DDR_SYNC_q)='1' THEN + -- JA + IF (DDR_CONFIG)='1' THEN + DDR_SM_d <= "001000"; + -- BEI WAIT UND LINE WRITE + ELSIF (CPU_REQ_q)='1' THEN + VA_S_d <= CPU_ROW_ADR; + BA_S_d <= CPU_BA; + CPU_AC_d <= vcc; + BUS_CYC_d_2 <= vcc; + DDR_SM_d <= "000010"; + ELSE + -- FIFO IST DEFAULT + IF (FIFO_REQ_q or (not BLITTER_REQ_q))='1' THEN + VA_P_d <= FIFO_ROW_ADR; + BA_P_d <= FIFO_BA; + -- VORBESETZEN + FIFO_AC_d <= vcc; + ELSE + VA_P_d <= BLITTER_ROW_ADR; + BA_P_d <= BLITTER_BA; + -- VORBESETZEN + BLITTER_AC_d <= vcc; + END IF; + DDR_SM_d <= "000001"; + END IF; + ELSE + -- NEIN ->SYNCHRONISIEREN + DDR_SM_d <= "000000"; + END IF; + + WHEN "000001" => + -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF (DDR_SEL and (nFB_WR or (not LINE)))='1' THEN + VRAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); + (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + -- AUTO PRECHARGE DA NICHT FIFO PAGE + VA_S_d(10) <= vcc; + CPU_AC_d <= vcc; + -- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + ELSE + VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; + (BA1_2, BA0_2) <= BA_P_q; + VA_S_d(10) <= not (FIFO_AC_q and FIFO_REQ_q); + FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; + FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; + BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; + END IF; + DDR_SM_d <= "000011"; + + WHEN "000010" => + VRAS <= vcc; + FIFO_BANK_NOT_OK <= vcc; + CPU_AC_d <= vcc; + + -- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + DDR_SM_d <= "000011"; + + WHEN "000011" => + CPU_AC_d <= CPU_AC_q; + FIFO_AC_d <= FIFO_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + IF (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' THEN + DDR_SM_d <= "010000"; + -- CPU? + ELSIF (CPU_AC_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= CPU_COL_ADR; + BA_S_d <= CPU_BA; + DDR_SM_d <= "001110"; + + -- FIFO? + ELSIF (FIFO_AC_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "010110"; + ELSIF (BLITTER_AC_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= BLITTER_COL_ADR; + BA_S_d <= BLITTER_BA; + DDR_SM_d <= "001110"; + ELSE + -- READ + DDR_SM_d <= "000111"; + END IF; + + WHEN "001110" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VCAS <= vcc; + + -- READ DATEN FÜR CPU + SR_DDR_FB <= CPU_AC_q; + + -- BLITTER DACK AND BLITTER LATCH DATEN + SR_BLITTER_DACK <= BLITTER_AC_q; + DDR_SM_d <= "001111"; + + WHEN "001111" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- FIFO READ EINSCHIEBEN WENN BANK OK + IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + + -- MANUELL PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + ELSE + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + -- WRITE + DDR_SM_d <= "011101"; + END IF; + + WHEN "010000" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- BLITTER ACK AND BLITTER LATCH DATEN + SR_BLITTER_DACK <= BLITTER_AC_q; + + -- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + DDR_SM_d <= "010001"; + + WHEN "010001" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VA_S_d(9 DOWNTO 0) <= (sizeIt(CPU_AC_q,10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q,10) and BLITTER_COL_ADR); + + -- AUTO PRECHARGE WENN NICHT FIFO PAGE + VA_S_d(10) <= VA_S_q(10); + BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); + + -- BYTE ENABLE WRITE + SR_VDMP_d(7 DOWNTO 4) <= FB_B; + + -- LINE ENABLE WRITE + SR_VDMP_d(3 DOWNTO 0) <= sizeIt(LINE,4) and "1111"; + DDR_SM_d <= "010010"; + + WHEN "010010" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + VCAS <= vcc; + VWE <= vcc; + + -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDR_WR_d <= vcc; + + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL_d <= vcc; + + -- WENN LINE DANN ACTIV + SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; + DDR_SM_d <= "010011"; + + WHEN "010011" => + CPU_AC_d <= CPU_AC_q; + BLITTER_AC_d <= BLITTER_AC_q; + + -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDR_WR_d <= vcc; + + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_DDRWR_D_SEL_d <= vcc; + DDR_SM_d <= "010100"; + + WHEN "010100" => + DDR_SM_d <= "010101"; + + WHEN "010101" => + IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN + VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + + -- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + ELSE + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + -- FIFO READ + DDR_SM_d <= "011101"; + END IF; + + WHEN "010110" => + VCAS <= vcc; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + DDR_SM_d <= "010111"; + + WHEN "010111" => + IF (FIFO_REQ_q)='1' THEN + + -- NEUE PAGE? + IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + ELSE + VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + + -- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011000"; + END IF; + ELSE + + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + + -- NOCH OFFEN LASSEN + DDR_SM_d <= "011101"; + END IF; + + WHEN "011000" => + VCAS <= vcc; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + DDR_SM_d <= "011001"; + + WHEN "011001" => + IF CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) THEN + + -- ALLE PAGES SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + ELSIF (FIFO_REQ_q)='1' THEN + + -- NEUE PAGE? + IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + + -- ALLE PAGES SCHLIESSEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + ELSE + VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + + -- NON AUTO PRECHARGE + VA_S_d(10) <= gnd; + BA_S_d <= FIFO_BA; + DDR_SM_d <= "011010"; + END IF; + ELSE + + -- ALLE PAGES SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011110"; + END IF; + + WHEN "011010" => + VCAS <= vcc; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + + -- NOTFALL? + IF (unsigned(FIFO_MW) < unsigned'("000000000")) THEN + + -- JA-> + DDR_SM_d <= "010111"; + ELSE + DDR_SM_d <= "011011"; + END IF; + + WHEN "011011" => + IF (FIFO_REQ_q)='1' THEN + + -- NEUE PAGE? + IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + + -- ALLE BANKS SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + ELSE + VA_P_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + + -- NON AUTO PRECHARGE + VA_P_d(10) <= gnd; + BA_P_d <= FIFO_BA; + DDR_SM_d <= "011100"; + END IF; + ELSE + + -- ALLE BANKS SCHLIESEN + VA_S_d(10) <= vcc; + + -- BANK SCHLIESSEN + DDR_SM_d <= "011101"; + END IF; + + WHEN "011100" => + IF (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 DOWNTO 12) /= FIFO_BA THEN + VRAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); + (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + CPU_AC_d <= vcc; + + -- BUS CYCLUS LOSTRETEN + BUS_CYC_d_2 <= vcc; + + -- AUTO PRECHARGE DA NICHT FIFO BANK + VA_S_d(10) <= vcc; + DDR_SM_d <= "000011"; + ELSE + VCAS <= vcc; + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; + (BA1_2, BA0_2) <= BA_P_q; + + -- DATEN WRITE FIFO + SR_FIFO_WRE_d <= vcc; + + -- CONFIG CYCLUS + DDR_SM_d <= "011001"; + END IF; + + WHEN "001000" => + DDR_SM_d <= "001001"; + + WHEN "001001" => + BUS_CYC_d_2 <= CPU_REQ_q; + DDR_SM_d <= "001010"; + + WHEN "001010" => + IF (CPU_REQ_q)='1' THEN + DDR_SM_d <= "001011"; + ELSE + DDR_SM_d <= "000000"; + END IF; + + WHEN "001011" => + DDR_SM_d <= "001100"; + + WHEN "001100" => + VA_S_d <= FB_AD(12 DOWNTO 0); + BA_S_d <= FB_AD(14 DOWNTO 13); + DDR_SM_d <= "001101"; + + WHEN "001101" => + + -- NUR BEI LONG WRITE + VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + + -- NUR BEI LONG WRITE + VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + + -- NUR BEI LONG WRITE + VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + + -- CLOSE FIFO BANK + DDR_SM_d <= "000111"; + + WHEN "011101" => + + -- AUF NOT OK + FIFO_BANK_NOT_OK <= vcc; + + -- BÄNKE SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + DDR_SM_d <= "000110"; + + WHEN "011110" => + -- AUF NOT OK + FIFO_BANK_NOT_OK <= vcc; + + -- BÄNKE SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + + -- REFRESH 70NS = 10 ZYCLEN + DDR_SM_d <= "000000"; + + WHEN "011111" => + + -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + IF DDR_REFRESH_SIG_q = "1001" THEN + + -- ALLE BANKS SCHLIESSEN + VRAS <= vcc; + VWE <= vcc; + VA10_2 <= vcc; + FIFO_BANK_NOT_OK <= vcc; + DDR_SM_d <= "100001"; + ELSE + VCAS <= vcc; + VRAS <= vcc; + DDR_SM_d <= "100000"; + END IF; + + WHEN "100000" => + DDR_SM_d <= "100001"; + + WHEN "100001" => + DDR_SM_d <= "100010"; + + WHEN "100010" => + DDR_SM_d <= "100011"; + + WHEN "100011" => + -- LEERSCHLAUFE + DDR_SM_d <= "000100"; + + WHEN "000100" => + DDR_SM_d <= "000101"; + + WHEN "000101" => + DDR_SM_d <= "000110"; + + WHEN "000110" => + DDR_SM_d <= "000111"; + + WHEN "000111" => + DDR_SM_d <= "000000"; + + WHEN OTHERS => + END CASE; + stdVec6 := (OTHERS => '0'); -- no storage needed + END PROCESS; + + -- ------------------------------------------------------------- + -- BLITTER ---------------------- + -- --------------------------------------- + BLITTER_REQ_clk <= DDRCLK0; + BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); + BLITTER_ROW_ADR <= BLITTER_ADR(26 DOWNTO 14); + BLITTER_BA(1) <= BLITTER_ADR(13); + BLITTER_BA(0) <= BLITTER_ADR(12); + BLITTER_COL_ADR <= BLITTER_ADR(11 DOWNTO 2); + + -- ---------------------------------------------------------------------------- + -- FIFO --------------------------------- + -- ------------------------------------------------------ + FIFO_REQ_clk <= DDRCLK0; + FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); - FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); - FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); - FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); - FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & + FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 DOWNTO 10); + FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); + FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); + FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & VIDEO_ADR_CNT_q(5) & VIDEO_ADR_CNT_q(4) & VIDEO_ADR_CNT_q(3) & VIDEO_ADR_CNT_q(2) & VIDEO_ADR_CNT_q(1) & VIDEO_ADR_CNT_q(0) & "00"); - FIFO_BANK_OK_clk <= DDRCLK0; - FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); + FIFO_BANK_OK_clk <= DDRCLK0; + FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); --- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- - CLR_FIFO_SYNC_clk <= DDRCLK0; + -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + CLR_FIFO_SYNC_clk <= DDRCLK0; --- SYNCHRONISIEREN - CLR_FIFO_SYNC_d <= CLR_FIFO; - CLEAR_FIFO_CNT_clk <= DDRCLK0; - CLEAR_FIFO_CNT_d <= CLR_FIFO_SYNC_q or (not FIFO_ACTIVE); - STOP_clk <= DDRCLK0; - STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; + -- SYNCHRONISIEREN + CLR_FIFO_SYNC_d <= CLR_FIFO; + CLEAR_FIFO_CNT_clk <= DDRCLK0; + CLEAR_FIFO_CNT_d <= CLR_FIFO_SYNC_q or (not FIFO_ACTIVE); + STOP_clk <= DDRCLK0; + STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; --- ZÄHLEN ----------------------------------------------- - VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; - VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; - VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or + -- ZÄHLEN ----------------------------------------------- + VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; + VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; + VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or (sizeIt(not CLEAR_FIFO_CNT_q,23) and (std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) + unsigned'("00000000000000000000001")))); - VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D_q; - VIDEO_BASE_ADR(19 downto 12) <= VIDEO_BASE_H_D_q; - VIDEO_BASE_ADR(11 downto 4) <= VIDEO_BASE_M_D_q; - VIDEO_BASE_ADR(3 downto 0) <= VIDEO_BASE_L_D_q(7 downto 4); - VDM_SEL <= VIDEO_BASE_L_D_q(3 downto 0); + + VIDEO_BASE_ADR(22 DOWNTO 20) <= VIDEO_BASE_X_D_q; + VIDEO_BASE_ADR(19 DOWNTO 12) <= VIDEO_BASE_H_D_q; + VIDEO_BASE_ADR(11 DOWNTO 4) <= VIDEO_BASE_M_D_q; + VIDEO_BASE_ADR(3 DOWNTO 0) <= VIDEO_BASE_L_D_q(7 DOWNTO 4); + VDM_SEL <= VIDEO_BASE_L_D_q(3 DOWNTO 0); --- AKTUELLE VIDEO ADRESSE - VIDEO_ACT_ADR(26 downto 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - + -- AKTUELLE VIDEO ADRESSE + VIDEO_ACT_ADR(26 DOWNTO 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - unsigned(std_logic_vector'("00000000000000" & FIFO_MW))); - VIDEO_ACT_ADR(3 downto 0) <= VDM_SEL; + VIDEO_ACT_ADR(3 DOWNTO 0) <= VDM_SEL; --- --------------------------------------------------------------------------------------- --- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS --- --------------------------------------------------------------------------------------- - DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; + -- --------------------------------------------------------------------------------------- + -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS + -- --------------------------------------------------------------------------------------- + DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; --- ZÄHLEN 0-2047 - DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + - unsigned'("00000000001")); - REFRESH_TIME_clk <= DDRCLK0; + -- ZÄHLEN 0-2047 + DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + unsigned'("00000000001")); + REFRESH_TIME_clk <= DDRCLK0; --- SYNC - REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not - MAIN_CLK); - DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; - DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = - "100011"); + -- SYNC + REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not MAIN_CLK); + DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; + DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = "100011"); --- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) --- MINUS 1 WENN GEMACHT - DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and + -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + -- MINUS 1 WENN GEMACHT + DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)) or (sizeIt(not REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) - unsigned'("0001"))) and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)); - DDR_REFRESH_REQ_clk <= DDRCLK0; - DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and - DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); + DDR_REFRESH_REQ_clk <= DDRCLK0; + DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); --- --------------------------------------------------------- --- VIDEO REGISTER ----------------------- --- ------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; + -- --------------------------------------------------------- + -- VIDEO REGISTER ----------------------- + -- ------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; --- 820D/2 - VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000110"); + -- 820D/2 + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000110"); --- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); - VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; + -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); + VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; --- 8203/2 - VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000001"); - VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); - VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; + -- 8203/2 + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000001"); + VIDEO_BASE_M_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); + VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; --- 8200-1/2 - VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000000"); - VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); - VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; - VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); - VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); + -- 8200-1/2 + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000000"); + VIDEO_BASE_H_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); + VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_X_D_d <= FB_AD(26 DOWNTO 24); + VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); --- 8209/2 - VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000100"); + -- 8209/2 + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000100"); --- 8207/2 - VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000011"); + -- 8207/2 + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000011"); --- 8204,5/2 - VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000010"); + -- 8204,5/2 + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000010"); -- FB_AD[31..24] = lpm_bustri_BYT( -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) @@ -1169,35 +1258,35 @@ begin u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or - (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or - (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or - (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); + (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 DOWNTO 0)) or + (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 DOWNTO 8)) or + (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 DOWNTO 16)); u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - FB_AD(23 downto 16) <= u0_tridata; + FB_AD(23 DOWNTO 16) <= u0_tridata; --- Assignments added to explicitly combine the --- effects of multiple drivers in the source - FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; - BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; - BA(0) <= BA0_1 or BA0_2; - BA(1) <= BA1_1 or BA1_2; - VA(0) <= VA0_1 or VA0_2; - VA(1) <= VA1_1 or VA1_2; - VA(2) <= VA2_1 or VA2_2; - VA(3) <= VA3_1 or VA3_2; - VA(4) <= VA4_1 or VA4_2; - VA(5) <= VA5_1 or VA5_2; - VA(6) <= VA6_1 or VA6_2; - VA(7) <= VA7_1 or VA7_2; - VA(8) <= VA8_1 or VA8_2; - VA(9) <= VA9_1 or VA9_2; - VA(10) <= VA10_1 or VA10_2; - VA(11) <= VA11_1 or VA11_2; - VA(12) <= VA12_1 or VA12_2; + -- Assignments added to explicitly combine the + -- effects of multiple drivers in the source + FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; + BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; + BA(0) <= BA0_1 or BA0_2; + BA(1) <= BA1_1 or BA1_2; + VA(0) <= VA0_1 or VA0_2; + VA(1) <= VA1_1 or VA1_2; + VA(2) <= VA2_1 or VA2_2; + VA(3) <= VA3_1 or VA3_2; + VA(4) <= VA4_1 or VA4_2; + VA(5) <= VA5_1 or VA5_2; + VA(6) <= VA6_1 or VA6_2; + VA(7) <= VA7_1 or VA7_2; + VA(8) <= VA8_1 or VA8_2; + VA(9) <= VA9_1 or VA9_2; + VA(10) <= VA10_1 or VA10_2; + VA(11) <= VA11_1 or VA11_2; + VA(12) <= VA12_1 or VA12_2; --- Define power signal(s) - vcc <= '1'; - gnd <= '0'; -end DDR_CTR_behav; +-- Define power SIGNAL(s) + vcc <= '1'; + gnd <= '0'; +END ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 49c66f4..b377532 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -183,70 +183,40 @@ ARCHITECTURE rtl OF video IS ); END COMPONENT; - COMPONENT blitter + COMPONENT ddr_ctr PORT ( + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; nRSTO : IN std_logic; MAIN_CLK : IN std_logic; FB_ALE : IN std_logic; nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - BLITTER_ON : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; + DDR_SYNC_66M : IN std_logic; + BLITTER_SIG : IN std_logic; + BLITTER_WR : IN std_logic; DDRCLK0 : IN std_logic; - SR_BLITTER_DACK : IN std_logic; - BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); - BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); + CLK33M : IN std_logic; + CLR_FIFO : IN std_logic; + BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); FB_AD : INOUT std_logic_vector(31 DOWNTO 0); FB_ADR : IN std_logic_vector(31 DOWNTO 0); + FIFO_MW : IN std_logic_vector(8 DOWNTO 0); VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_RUN : OUT std_logic; - BLITTER_SIG : OUT std_logic; - BLITTER_WR : OUT std_logic; - BLITTER_TA : OUT std_logic; - BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); - BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT ddr_ctr - PORT - ( - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - DDR_SYNC_66M : IN std_logic; - BLITTER_SIG : IN std_logic; - BLITTER_WR : IN std_logic; - DDRCLK0 : IN std_logic; - CLK33M : IN std_logic; - CLR_FIFO : IN std_logic; - BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - FIFO_MW : IN std_logic_vector(8 DOWNTO 0); - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - nVWE : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - VCKE : OUT std_logic; - nVCAS : OUT std_logic; - SR_FIFO_WRE : OUT std_logic; - SR_DDR_FB : OUT std_logic; - SR_DDR_WR : OUT std_logic; - SR_DDRWR_D_SEL : OUT std_logic; - VIDEO_DDR_TA : OUT std_logic; + nVWE : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + VCKE : OUT std_logic; + nVCAS : OUT std_logic; + SR_FIFO_WRE : OUT std_logic; + SR_DDR_FB : OUT std_logic; + SR_DDR_WR : OUT std_logic; + SR_DDRWR_D_SEL : OUT std_logic; + VIDEO_DDR_TA : OUT std_logic; SR_BLITTER_DACK : OUT std_logic; DDRWR_D_SEL1 : OUT std_logic; BA : OUT std_logic_vector(1 DOWNTO 0); @@ -259,455 +229,525 @@ ARCHITECTURE rtl OF video IS END COMPONENT ddr_ctr; COMPONENT altdpram1 - PORT(wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(7 DOWNTO 0); - address_b : IN std_logic_vector(7 DOWNTO 0); - data_a : IN std_logic_vector(5 DOWNTO 0); - data_b : IN std_logic_vector(5 DOWNTO 0); - q_a : OUT std_logic_vector(5 DOWNTO 0); - q_b : OUT std_logic_vector(5 DOWNTO 0) + PORT + ( + wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(7 DOWNTO 0); + address_b : IN std_logic_vector(7 DOWNTO 0); + data_a : IN std_logic_vector(5 DOWNTO 0); + data_b : IN std_logic_vector(5 DOWNTO 0); + q_a : OUT std_logic_vector(5 DOWNTO 0); + q_b : OUT std_logic_vector(5 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_fifo_dc0 - PORT(wrreq : IN std_logic; - wrclk : IN std_logic; - rdreq : IN std_logic; - rdclk : IN std_logic; - aclr : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - rdempty : OUT std_logic; - q : OUT std_logic_vector(127 DOWNTO 0); - wrusedw : OUT std_logic_vector(8 DOWNTO 0) + PORT + ( + wrreq : IN std_logic; + wrclk : IN std_logic; + rdreq : IN std_logic; + rdclk : IN std_logic; + aclr : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + rdempty : OUT std_logic; + q : OUT std_logic_vector(127 DOWNTO 0); + wrusedw : OUT std_logic_vector(8 DOWNTO 0) ); END COMPONENT; COMPONENT altddio_bidir0 - PORT(oe : IN std_logic; - inclock : IN std_logic; - outclock : IN std_logic; - datain_h : IN std_logic_vector(31 DOWNTO 0); - datain_l : IN std_logic_vector(31 DOWNTO 0); - padio : INOUT std_logic_vector(31 DOWNTO 0); - combout : OUT std_logic_vector(31 DOWNTO 0); - dataout_h : OUT std_logic_vector(31 DOWNTO 0); - dataout_l : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + oe : IN std_logic; + inclock : IN std_logic; + outclock : IN std_logic; + datain_h : IN std_logic_vector(31 DOWNTO 0); + datain_l : IN std_logic_vector(31 DOWNTO 0); + padio : INOUT std_logic_vector(31 DOWNTO 0); + combout : OUT std_logic_vector(31 DOWNTO 0); + dataout_h : OUT std_logic_vector(31 DOWNTO 0); + dataout_l : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff4 - PORT(clock : IN std_logic; - data : IN std_logic_vector(15 DOWNTO 0); - q : OUT std_logic_vector(15 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(15 DOWNTO 0); + q : OUT std_logic_vector(15 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_muxvdm - PORT(data0x : IN std_logic_vector(127 DOWNTO 0); - data10x : IN std_logic_vector(127 DOWNTO 0); - data11x : IN std_logic_vector(127 DOWNTO 0); - data12x : IN std_logic_vector(127 DOWNTO 0); - data13x : IN std_logic_vector(127 DOWNTO 0); - data14x : IN std_logic_vector(127 DOWNTO 0); - data15x : IN std_logic_vector(127 DOWNTO 0); - data1x : IN std_logic_vector(127 DOWNTO 0); - data2x : IN std_logic_vector(127 DOWNTO 0); - data3x : IN std_logic_vector(127 DOWNTO 0); - data4x : IN std_logic_vector(127 DOWNTO 0); - data5x : IN std_logic_vector(127 DOWNTO 0); - data6x : IN std_logic_vector(127 DOWNTO 0); - data7x : IN std_logic_vector(127 DOWNTO 0); - data8x : IN std_logic_vector(127 DOWNTO 0); - data9x : IN std_logic_vector(127 DOWNTO 0); - sel : IN std_logic_vector(3 DOWNTO 0); - result : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + data0x : IN std_logic_vector(127 DOWNTO 0); + data10x : IN std_logic_vector(127 DOWNTO 0); + data11x : IN std_logic_vector(127 DOWNTO 0); + data12x : IN std_logic_vector(127 DOWNTO 0); + data13x : IN std_logic_vector(127 DOWNTO 0); + data14x : IN std_logic_vector(127 DOWNTO 0); + data15x : IN std_logic_vector(127 DOWNTO 0); + data1x : IN std_logic_vector(127 DOWNTO 0); + data2x : IN std_logic_vector(127 DOWNTO 0); + data3x : IN std_logic_vector(127 DOWNTO 0); + data4x : IN std_logic_vector(127 DOWNTO 0); + data5x : IN std_logic_vector(127 DOWNTO 0); + data6x : IN std_logic_vector(127 DOWNTO 0); + data7x : IN std_logic_vector(127 DOWNTO 0); + data8x : IN std_logic_vector(127 DOWNTO 0); + data9x : IN std_logic_vector(127 DOWNTO 0); + sel : IN std_logic_vector(3 DOWNTO 0); + result : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux3 - PORT(data1 : IN std_logic; - data0 : IN std_logic; - sel : IN std_logic; - result : OUT std_logic + PORT + ( + data1 : IN std_logic; + data0 : IN std_logic; + sel : IN std_logic; + result : OUT std_logic ); END COMPONENT; COMPONENT lpm_bustri_long - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - tridata : INOUT std_logic_vector(31 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + tridata : INOUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff5 - PORT(clock : IN std_logic; - data : IN std_logic_vector(7 DOWNTO 0); - q : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(7 DOWNTO 0); + q : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff1 - PORT(clock : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff0 - PORT(clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT altddio_out0 - PORT(outclock : IN std_logic; - datain_h : IN std_logic_vector(3 DOWNTO 0); - datain_l : IN std_logic_vector(3 DOWNTO 0); - dataout : OUT std_logic_vector(3 DOWNTO 0) + PORT + ( + outclock : IN std_logic; + datain_h : IN std_logic_vector(3 DOWNTO 0); + datain_l : IN std_logic_vector(3 DOWNTO 0); + dataout : OUT std_logic_vector(3 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux0 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(31 DOWNTO 0); - data1x : IN std_logic_vector(31 DOWNTO 0); - data2x : IN std_logic_vector(31 DOWNTO 0); - data3x : IN std_logic_vector(31 DOWNTO 0); - sel : IN std_logic_vector(1 DOWNTO 0); - result : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(31 DOWNTO 0); + data1x : IN std_logic_vector(31 DOWNTO 0); + data2x : IN std_logic_vector(31 DOWNTO 0); + data3x : IN std_logic_vector(31 DOWNTO 0); + sel : IN std_logic_vector(1 DOWNTO 0); + result : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux5 - PORT(data0x : IN std_logic_vector(63 DOWNTO 0); - data1x : IN std_logic_vector(63 DOWNTO 0); - data2x : IN std_logic_vector(63 DOWNTO 0); - data3x : IN std_logic_vector(63 DOWNTO 0); - sel : IN std_logic_vector(1 DOWNTO 0); - result : OUT std_logic_vector(63 DOWNTO 0) + PORT + ( + data0x : IN std_logic_vector(63 DOWNTO 0); + data1x : IN std_logic_vector(63 DOWNTO 0); + data2x : IN std_logic_vector(63 DOWNTO 0); + data3x : IN std_logic_vector(63 DOWNTO 0); + sel : IN std_logic_vector(1 DOWNTO 0); + result : OUT std_logic_vector(63 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant2 - PORT( result : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux1 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(15 DOWNTO 0); - data1x : IN std_logic_vector(15 DOWNTO 0); - data2x : IN std_logic_vector(15 DOWNTO 0); - data3x : IN std_logic_vector(15 DOWNTO 0); - data4x : IN std_logic_vector(15 DOWNTO 0); - data5x : IN std_logic_vector(15 DOWNTO 0); - data6x : IN std_logic_vector(15 DOWNTO 0); - data7x : IN std_logic_vector(15 DOWNTO 0); - sel : IN std_logic_vector(2 DOWNTO 0); - result : OUT std_logic_vector(15 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(15 DOWNTO 0); + data1x : IN std_logic_vector(15 DOWNTO 0); + data2x : IN std_logic_vector(15 DOWNTO 0); + data3x : IN std_logic_vector(15 DOWNTO 0); + data4x : IN std_logic_vector(15 DOWNTO 0); + data5x : IN std_logic_vector(15 DOWNTO 0); + data6x : IN std_logic_vector(15 DOWNTO 0); + data7x : IN std_logic_vector(15 DOWNTO 0); + sel : IN std_logic_vector(2 DOWNTO 0); + result : OUT std_logic_vector(15 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux2 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(7 DOWNTO 0); - data10x : IN std_logic_vector(7 DOWNTO 0); - data11x : IN std_logic_vector(7 DOWNTO 0); - data12x : IN std_logic_vector(7 DOWNTO 0); - data13x : IN std_logic_vector(7 DOWNTO 0); - data14x : IN std_logic_vector(7 DOWNTO 0); - data15x : IN std_logic_vector(7 DOWNTO 0); - data1x : IN std_logic_vector(7 DOWNTO 0); - data2x : IN std_logic_vector(7 DOWNTO 0); - data3x : IN std_logic_vector(7 DOWNTO 0); - data4x : IN std_logic_vector(7 DOWNTO 0); - data5x : IN std_logic_vector(7 DOWNTO 0); - data6x : IN std_logic_vector(7 DOWNTO 0); - data7x : IN std_logic_vector(7 DOWNTO 0); - data8x : IN std_logic_vector(7 DOWNTO 0); - data9x : IN std_logic_vector(7 DOWNTO 0); - sel : IN std_logic_vector(3 DOWNTO 0); - result : OUT std_logic_vector(7 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(7 DOWNTO 0); + data10x : IN std_logic_vector(7 DOWNTO 0); + data11x : IN std_logic_vector(7 DOWNTO 0); + data12x : IN std_logic_vector(7 DOWNTO 0); + data13x : IN std_logic_vector(7 DOWNTO 0); + data14x : IN std_logic_vector(7 DOWNTO 0); + data15x : IN std_logic_vector(7 DOWNTO 0); + data1x : IN std_logic_vector(7 DOWNTO 0); + data2x : IN std_logic_vector(7 DOWNTO 0); + data3x : IN std_logic_vector(7 DOWNTO 0); + data4x : IN std_logic_vector(7 DOWNTO 0); + data5x : IN std_logic_vector(7 DOWNTO 0); + data6x : IN std_logic_vector(7 DOWNTO 0); + data7x : IN std_logic_vector(7 DOWNTO 0); + data8x : IN std_logic_vector(7 DOWNTO 0); + data9x : IN std_logic_vector(7 DOWNTO 0); + sel : IN std_logic_vector(3 DOWNTO 0); + result : OUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_shiftreg4 - PORT(clock : IN std_logic; - shiftin : IN std_logic; - shiftout : OUT std_logic + PORT + ( + clock : IN std_logic; + shiftin : IN std_logic; + shiftout : OUT std_logic ); END COMPONENT; COMPONENT lpm_latch0 - PORT(gate : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) + PORT + ( + gate : IN std_logic; + data : IN std_logic_vector(31 DOWNTO 0); + q : OUT std_logic_vector(31 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff6 - PORT(clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - q : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + clock : IN std_logic; + enable : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + q : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_ff3 - PORT(clock : IN std_logic; - data : IN std_logic_vector(23 DOWNTO 0); - q : OUT std_logic_vector(23 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data : IN std_logic_vector(23 DOWNTO 0); + q : OUT std_logic_vector(23 DOWNTO 0) ); END COMPONENT; COMPONENT altddio_out2 - PORT(outclock : IN std_logic; - datain_h : IN std_logic_vector(23 DOWNTO 0); - datain_l : IN std_logic_vector(23 DOWNTO 0); - dataout : OUT std_logic_vector(23 DOWNTO 0) + PORT + ( + outclock : IN std_logic; + datain_h : IN std_logic_vector(23 DOWNTO 0); + datain_l : IN std_logic_vector(23 DOWNTO 0); + dataout : OUT std_logic_vector(23 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_bustri1 - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(2 DOWNTO 0); - tridata : INOUT std_logic_vector(2 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(2 DOWNTO 0); + tridata : INOUT std_logic_vector(2 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_bustri_byt - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(7 DOWNTO 0); - tridata : INOUT std_logic_vector(7 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(7 DOWNTO 0); + tridata : INOUT std_logic_vector(7 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant0 - PORT( result : OUT std_logic_vector(4 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(4 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_muxdz - PORT(clock : IN std_logic; - clken : IN std_logic; - sel : IN std_logic; - data0x : IN std_logic_vector(127 DOWNTO 0); - data1x : IN std_logic_vector(127 DOWNTO 0); - result : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + clock : IN std_logic; + clken : IN std_logic; + sel : IN std_logic; + data0x : IN std_logic_vector(127 DOWNTO 0); + data1x : IN std_logic_vector(127 DOWNTO 0); + result : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_fifodz - PORT(wrreq : IN std_logic; - rdreq : IN std_logic; - clock : IN std_logic; - aclr : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - q : OUT std_logic_vector(127 DOWNTO 0) + PORT + ( + wrreq : IN std_logic; + rdreq : IN std_logic; + clock : IN std_logic; + aclr : IN std_logic; + data : IN std_logic_vector(127 DOWNTO 0); + q : OUT std_logic_vector(127 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_bustri3 - PORT(enabledt : IN std_logic; - data : IN std_logic_vector(5 DOWNTO 0); - tridata : INOUT std_logic_vector(5 DOWNTO 0) + PORT + ( + enabledt : IN std_logic; + data : IN std_logic_vector(5 DOWNTO 0); + tridata : INOUT std_logic_vector(5 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux6 - PORT(clock : IN std_logic; - data0x : IN std_logic_vector(23 DOWNTO 0); - data1x : IN std_logic_vector(23 DOWNTO 0); - data2x : IN std_logic_vector(23 DOWNTO 0); - data3x : IN std_logic_vector(23 DOWNTO 0); - data4x : IN std_logic_vector(23 DOWNTO 0); - data5x : IN std_logic_vector(23 DOWNTO 0); - data6x : IN std_logic_vector(23 DOWNTO 0); - data7x : IN std_logic_vector(23 DOWNTO 0); - sel : IN std_logic_vector(2 DOWNTO 0); - result : OUT std_logic_vector(23 DOWNTO 0) + PORT + ( + clock : IN std_logic; + data0x : IN std_logic_vector(23 DOWNTO 0); + data1x : IN std_logic_vector(23 DOWNTO 0); + data2x : IN std_logic_vector(23 DOWNTO 0); + data3x : IN std_logic_vector(23 DOWNTO 0); + data4x : IN std_logic_vector(23 DOWNTO 0); + data5x : IN std_logic_vector(23 DOWNTO 0); + data6x : IN std_logic_vector(23 DOWNTO 0); + data7x : IN std_logic_vector(23 DOWNTO 0); + sel : IN std_logic_vector(2 DOWNTO 0); + result : OUT std_logic_vector(23 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant1 - PORT( result : OUT std_logic_vector(1 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(1 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_mux4 - PORT(sel : IN std_logic; - data0x : IN std_logic_vector(6 DOWNTO 0); - data1x : IN std_logic_vector(6 DOWNTO 0); - result : OUT std_logic_vector(6 DOWNTO 0) + PORT + ( + sel : IN std_logic; + data0x : IN std_logic_vector(6 DOWNTO 0); + data1x : IN std_logic_vector(6 DOWNTO 0); + result : OUT std_logic_vector(6 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_constant3 - PORT( result : OUT std_logic_vector(6 DOWNTO 0) + PORT + ( + result : OUT std_logic_vector(6 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_shiftreg6 - PORT(clock : IN std_logic; - shiftin : IN std_logic; - q : OUT std_logic_vector(4 DOWNTO 0) + PORT + ( + clock : IN std_logic; + shiftin : IN std_logic; + q : OUT std_logic_vector(4 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_shiftreg0 - PORT(load : IN std_logic; - clock : IN std_logic; - shiftin : IN std_logic; - data : IN std_logic_vector(15 DOWNTO 0); - shiftout : OUT std_logic + PORT + ( + load : IN std_logic; + clock : IN std_logic; + shiftin : IN std_logic; + data : IN std_logic_vector(15 DOWNTO 0); + shiftout : OUT std_logic ); END COMPONENT; COMPONENT altdpram0 - PORT(wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(3 DOWNTO 0); - address_b : IN std_logic_vector(3 DOWNTO 0); - data_a : IN std_logic_vector(2 DOWNTO 0); - data_b : IN std_logic_vector(2 DOWNTO 0); - q_a : OUT std_logic_vector(2 DOWNTO 0); - q_b : OUT std_logic_vector(2 DOWNTO 0) + PORT + ( + wren_a : IN std_logic; + wren_b : IN std_logic; + clock_a : IN std_logic; + clock_b : IN std_logic; + address_a : IN std_logic_vector(3 DOWNTO 0); + address_b : IN std_logic_vector(3 DOWNTO 0); + data_a : IN std_logic_vector(2 DOWNTO 0); + data_b : IN std_logic_vector(2 DOWNTO 0); + q_a : OUT std_logic_vector(2 DOWNTO 0); + q_b : OUT std_logic_vector(2 DOWNTO 0) ); END COMPONENT; COMPONENT video_mod_mux_clutctr - PORT(nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - BLITTER_RUN : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_BUSY : IN std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VR_D : IN std_logic_vector(8 DOWNTO 0); - COLOR8 : OUT std_logic; - ACP_CLUT_RD : OUT std_logic; - COLOR1 : OUT std_logic; - FALCON_CLUT_RDH : OUT std_logic; - FALCON_CLUT_RDL : OUT std_logic; - ST_CLUT_RD : OUT std_logic; - HSYNC : OUT std_logic; - VSYNC : OUT std_logic; - nBLANK : OUT std_logic; - nSYNC : OUT std_logic; - nPD_VGA : OUT std_logic; - FIFO_RDE : OUT std_logic; - COLOR2 : OUT std_logic; - COLOR4 : OUT std_logic; - PIXEL_CLK : OUT std_logic; - BLITTER_ON : OUT std_logic; - VIDEO_MOD_TA : OUT std_logic; - INTER_ZEI : OUT std_logic; - DOP_FIFO_CLR : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - CLR_FIFO : OUT std_logic; - ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); - BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); - CCSEL : OUT std_logic_vector(2 DOWNTO 0); - CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); - CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); - FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); - ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); - VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0) + PORT + ( + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + CLK33M : IN std_logic; + CLK25M : IN std_logic; + BLITTER_RUN : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_BUSY : IN std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + VR_D : IN std_logic_vector(8 DOWNTO 0); + COLOR8 : OUT std_logic; + ACP_CLUT_RD : OUT std_logic; + COLOR1 : OUT std_logic; + FALCON_CLUT_RDH : OUT std_logic; + FALCON_CLUT_RDL : OUT std_logic; + ST_CLUT_RD : OUT std_logic; + HSYNC : OUT std_logic; + VSYNC : OUT std_logic; + nBLANK : OUT std_logic; + nSYNC : OUT std_logic; + nPD_VGA : OUT std_logic; + FIFO_RDE : OUT std_logic; + COLOR2 : OUT std_logic; + COLOR4 : OUT std_logic; + PIXEL_CLK : OUT std_logic; + BLITTER_ON : OUT std_logic; + VIDEO_MOD_TA : OUT std_logic; + INTER_ZEI : OUT std_logic; + DOP_FIFO_CLR : OUT std_logic; + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + VR_RD : OUT std_logic; + CLR_FIFO : OUT std_logic; + ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); + CCSEL : OUT std_logic_vector(2 DOWNTO 0); + CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); + CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); + FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); + VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0) ); END COMPONENT; - SIGNAL ACP_CLUT_RD : std_logic; - SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); - SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_ON : std_logic; - SIGNAL BLITTER_RUN : std_logic; - SIGNAL BLITTER_SIG : std_logic; - SIGNAL BLITTER_TA : std_logic; - SIGNAL BLITTER_WR : std_logic; - SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); - SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); - SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); - SIGNAL CCA : std_logic_vector(23 DOWNTO 0); - SIGNAL CCF : std_logic_vector(23 DOWNTO 0); - SIGNAL CCS : std_logic_vector(23 DOWNTO 0); - SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); - SIGNAL CLR_FIFO : std_logic; - SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); - SIGNAL CLUT_ADR1A : std_logic; - SIGNAL CLUT_ADR2A : std_logic; - SIGNAL CLUT_ADR3A : std_logic; - SIGNAL CLUT_ADR4A : std_logic; - SIGNAL CLUT_ADR5A : std_logic; - SIGNAL CLUT_ADR6A : std_logic; - SIGNAL CLUT_ADR7A : std_logic; - SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); - SIGNAL COLOR1 : std_logic; - SIGNAL COLOR2 : std_logic; - SIGNAL COLOR4 : std_logic; - SIGNAL COLOR8 : std_logic; - SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); - SIGNAL DDR_WR : std_logic; - SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); - SIGNAL DOP_FIFO_CLR : std_logic; + SIGNAL ACP_CLUT_RD : std_logic; + SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); + SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); + SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_ON : std_logic; + SIGNAL BLITTER_RUN : std_logic; + SIGNAL BLITTER_SIG : std_logic; + SIGNAL BLITTER_TA : std_logic; + SIGNAL BLITTER_WR : std_logic; + SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); + SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); + SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); + SIGNAL CCA : std_logic_vector(23 DOWNTO 0); + SIGNAL CCF : std_logic_vector(23 DOWNTO 0); + SIGNAL CCS : std_logic_vector(23 DOWNTO 0); + SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); + SIGNAL CLUT_ADR1A : std_logic; + SIGNAL CLUT_ADR2A : std_logic; + SIGNAL CLUT_ADR3A : std_logic; + SIGNAL CLUT_ADR4A : std_logic; + SIGNAL CLUT_ADR5A : std_logic; + SIGNAL CLUT_ADR6A : std_logic; + SIGNAL CLUT_ADR7A : std_logic; + SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); + SIGNAL COLOR1 : std_logic; + SIGNAL COLOR2 : std_logic; + SIGNAL COLOR4 : std_logic; + SIGNAL COLOR8 : std_logic; + SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); + SIGNAL DDR_WR : std_logic; + SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); + SIGNAL DOP_FIFO_CLR : std_logic; SIGNAL FALCON_CLUT_RDH : std_logic; SIGNAL FALCON_CLUT_RDL : std_logic; - SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); - SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); - SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); - SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); - SIGNAL FIFO_RDE : std_logic; - SIGNAL FIFO_WRE : std_logic; - SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic; + SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); + SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); + SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); + SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); + SIGNAL FIFO_RDE : std_logic; + SIGNAL FIFO_WRE : std_logic; + SIGNAL INTER_ZEI : std_logic; + SIGNAL nFB_BURST : std_logic; SIGNAL PIXEL_CLK_ALTERA_SYNTHESIZED : std_logic; SIGNAL SR_BLITTER_DACK : std_logic; - SIGNAL SR_DDR_FB : std_logic; - SIGNAL SR_DDR_WR : std_logic; - SIGNAL SR_DDRWR_D_SEL : std_logic; - SIGNAL SR_FIFO_WRE : std_logic; - SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL ST_CLUT_RD : std_logic; - SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); - SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); - SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL VDOUT_OE : std_logic; - SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); - SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); - SIGNAL VDR : std_logic_vector(31 DOWNTO 0); - SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); - SIGNAL VIDEO_DDR_TA : std_logic; - SIGNAL VIDEO_MOD_TA : std_logic; - SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); - SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); - SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); + SIGNAL SR_DDR_FB : std_logic; + SIGNAL SR_DDR_WR : std_logic; + SIGNAL SR_DDRWR_D_SEL : std_logic; + SIGNAL SR_FIFO_WRE : std_logic; + SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL ST_CLUT_RD : std_logic; + SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); + SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); + SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL VDOUT_OE : std_logic; + SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); + SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); + SIGNAL VDR : std_logic_vector(31 DOWNTO 0); + SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); + SIGNAL VIDEO_DDR_TA : std_logic; + SIGNAL VIDEO_MOD_TA : std_logic; + SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); + SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); + SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); SIGNAL SYNTHESIZED_WIRE_0 : std_logic; SIGNAL SYNTHESIZED_WIRE_1 : std_logic; SIGNAL SYNTHESIZED_WIRE_2 : std_logic; @@ -716,7 +756,7 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_5 : std_logic; SIGNAL SYNTHESIZED_WIRE_60 : std_logic; SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); - SIGNAL DFF_inst93 : std_logic; + SIGNAL DFF_inst93 : std_logic; SIGNAL SYNTHESIZED_WIRE_8 : std_logic; SIGNAL SYNTHESIZED_WIRE_9 : std_logic; SIGNAL SYNTHESIZED_WIRE_61 : std_logic; @@ -754,7 +794,7 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_46 : std_logic; SIGNAL SYNTHESIZED_WIRE_47 : std_logic_vector(6 DOWNTO 0); SIGNAL SYNTHESIZED_WIRE_48 : std_logic_vector(31 DOWNTO 0); - SIGNAL DFF_inst91 : std_logic; + SIGNAL DFF_inst91 : std_logic; SIGNAL SYNTHESIZED_WIRE_64 : std_logic; SIGNAL SYNTHESIZED_WIRE_49 : std_logic; SIGNAL SYNTHESIZED_WIRE_50 : std_logic; @@ -768,22 +808,22 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_65 : std_logic_vector(23 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); + SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); BEGIN VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); @@ -806,38 +846,32 @@ BEGIN SYNTHESIZED_WIRE_56 <= '0'; SYNTHESIZED_WIRE_57 <= '0'; - CC16(18) <= GDFX_TEMP_SIGNAL_16(7); - CC16(17) <= GDFX_TEMP_SIGNAL_16(6); - CC16(16) <= GDFX_TEMP_SIGNAL_16(5); - CC16(9) <= GDFX_TEMP_SIGNAL_16(4); - CC16(8) <= GDFX_TEMP_SIGNAL_16(3); - CC16(2) <= GDFX_TEMP_SIGNAL_16(2); - CC16(1) <= GDFX_TEMP_SIGNAL_16(1); - CC16(0) <= GDFX_TEMP_SIGNAL_16(0); - CC16(23) <= GDFX_TEMP_SIGNAL_0(15); CC16(22) <= GDFX_TEMP_SIGNAL_0(14); CC16(21) <= GDFX_TEMP_SIGNAL_0(13); CC16(20) <= GDFX_TEMP_SIGNAL_0(12); CC16(19) <= GDFX_TEMP_SIGNAL_0(11); + CC16(18) <= GDFX_TEMP_SIGNAL_16(7); + CC16(17) <= GDFX_TEMP_SIGNAL_16(6); + CC16(16) <= GDFX_TEMP_SIGNAL_16(5); CC16(15) <= GDFX_TEMP_SIGNAL_0(10); CC16(14) <= GDFX_TEMP_SIGNAL_0(9); CC16(13) <= GDFX_TEMP_SIGNAL_0(8); CC16(12) <= GDFX_TEMP_SIGNAL_0(7); CC16(11) <= GDFX_TEMP_SIGNAL_0(6); CC16(10) <= GDFX_TEMP_SIGNAL_0(5); + CC16(9) <= GDFX_TEMP_SIGNAL_16(4); + CC16(8) <= GDFX_TEMP_SIGNAL_16(3); CC16(7) <= GDFX_TEMP_SIGNAL_0(4); CC16(6) <= GDFX_TEMP_SIGNAL_0(3); CC16(5) <= GDFX_TEMP_SIGNAL_0(2); CC16(4) <= GDFX_TEMP_SIGNAL_0(1); CC16(3) <= GDFX_TEMP_SIGNAL_0(0); + CC16(2) <= GDFX_TEMP_SIGNAL_16(2); + CC16(1) <= GDFX_TEMP_SIGNAL_16(1); + CC16(0) <= GDFX_TEMP_SIGNAL_16(0); + - GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); - GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); - GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); - GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); - GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); - GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); @@ -847,210 +881,255 @@ BEGIN GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); + GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); + GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); + GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); + GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); + GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); + GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); ACP_CLUT_RAM : altdpram2 - PORT MAP(wren_a => ACP_CLUT_WR(3), - wren_b => SYNTHESIZED_WIRE_0, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(7 DOWNTO 0), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_30, - q_b => CCA(7 DOWNTO 0)); + PORT MAP + ( + wren_a => ACP_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_0, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(7 DOWNTO 0), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_30, + q_b => CCA(7 DOWNTO 0) + ); ACP_CLUT_RAM54 : altdpram2 - PORT MAP(wren_a => ACP_CLUT_WR(2), - wren_b => SYNTHESIZED_WIRE_1, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(15 DOWNTO 8), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_32, - q_b => CCA(15 DOWNTO 8)); + PORT MAP + ( + wren_a => ACP_CLUT_WR(2), + wren_b => SYNTHESIZED_WIRE_1, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(15 DOWNTO 8), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_32, + q_b => CCA(15 DOWNTO 8) + ); ACP_CLUT_RAM55 : altdpram2 - PORT MAP(wren_a => ACP_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_2, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => ZR_C8B, - data_a => FB_AD(23 DOWNTO 16), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_33, - q_b => CCA(23 DOWNTO 16)); + PORT MAP + ( + wren_a => ACP_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_2, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => ZR_C8B, + data_a => FB_AD(23 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_33, + q_b => CCA(23 DOWNTO 16) + ); - i_blitter : blitter - PORT MAP(nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - FB_ALE => FB_ALE, - nFB_WR => nFB_WR, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - BLITTER_ON => BLITTER_ON, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - DDRCLK0 => DDRCLK(0), - SR_BLITTER_DACK => SR_BLITTER_DACK, - BLITTER_DACK => BLITTER_DACK, - BLITTER_DIN => BLITTER_DIN, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - BLITTER_RUN => BLITTER_RUN, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - BLITTER_TA => BLITTER_TA, - BLITTER_ADR => BLITTER_ADR, - BLITTER_DOUT => BLITTER_DOUT); + i_blitter : work.blitter + PORT MAP + ( + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + BLITTER_ON => BLITTER_ON, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + DDRCLK0 => DDRCLK(0), + SR_BLITTER_DACK => SR_BLITTER_DACK, + BLITTER_DACK => BLITTER_DACK, + BLITTER_DIN => BLITTER_DIN, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + BLITTER_RUN => BLITTER_RUN, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + BLITTER_TA => BLITTER_TA, + BLITTER_ADR => BLITTER_ADR, + BLITTER_DOUT => BLITTER_DOUT + ); i_ddr_ctr : ddr_ctr - PORT MAP(nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - FB_ALE => FB_ALE, - nFB_WR => nFB_WR, - DDR_SYNC_66M => DDR_SYNC_66M, - BLITTER_SIG => BLITTER_SIG, - BLITTER_WR => BLITTER_WR, - DDRCLK0 => DDRCLK(0), - CLK33M => CLK33M, - CLR_FIFO => CLR_FIFO, - BLITTER_ADR => BLITTER_ADR, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - FIFO_MW => FIFO_MW, - VIDEO_RAM_CTR => VIDEO_RAM_CTR, - nVWE => nVWE, - nVRAS => nVRAS, - nVCS => nVCS, - VCKE => VCKE, - nVCAS => nVCAS, - SR_FIFO_WRE => SR_FIFO_WRE, - SR_DDR_FB => SR_DDR_FB, - SR_DDR_WR => SR_DDR_WR, - SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, - VIDEO_DDR_TA => VIDEO_DDR_TA, - SR_BLITTER_DACK => SR_BLITTER_DACK, - DDRWR_D_SEL1 => DDRWR_D_SEL(1), - BA => BA, - FB_LE => FB_LE, - FB_VDOE => FB_VDOE, - SR_VDMP => SR_VDMP, - VA => VA, - VDM_SEL => VDM_SEL); + PORT MAP + ( + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + FB_ALE => FB_ALE, + nFB_WR => nFB_WR, + DDR_SYNC_66M => DDR_SYNC_66M, + BLITTER_SIG => BLITTER_SIG, + BLITTER_WR => BLITTER_WR, + DDRCLK0 => DDRCLK(0), + CLK33M => CLK33M, + CLR_FIFO => CLR_FIFO, + BLITTER_ADR => BLITTER_ADR, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + FIFO_MW => FIFO_MW, + VIDEO_RAM_CTR => VIDEO_RAM_CTR, + nVWE => nVWE, + nVRAS => nVRAS, + nVCS => nVCS, + VCKE => VCKE, + nVCAS => nVCAS, + SR_FIFO_WRE => SR_FIFO_WRE, + SR_DDR_FB => SR_DDR_FB, + SR_DDR_WR => SR_DDR_WR, + SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, + VIDEO_DDR_TA => VIDEO_DDR_TA, + SR_BLITTER_DACK => SR_BLITTER_DACK, + DDRWR_D_SEL1 => DDRWR_D_SEL(1), + BA => BA, + FB_LE => FB_LE, + FB_VDOE => FB_VDOE, + SR_VDMP => SR_VDMP, + VA => VA, + VDM_SEL => VDM_SEL + ); FALCON_CLUT_BLUE : altdpram1 - PORT MAP(wren_a => FALCON_CLUT_WR(3), - wren_b => SYNTHESIZED_WIRE_3, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_45, - q_b => CCF(7 DOWNTO 2)); + PORT MAP + ( + wren_a => FALCON_CLUT_WR(3), + wren_b => SYNTHESIZED_WIRE_3, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_45, + q_b => CCF(7 DOWNTO 2) + ); FALCON_CLUT_GREEN : altdpram1 - PORT MAP(wren_a => FALCON_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_4, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_44, - q_b => CCF(15 DOWNTO 10)); + PORT MAP + ( + wren_a => FALCON_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_4, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(23 DOWNTO 18), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_44, + q_b => CCF(15 DOWNTO 10) + ); FALCON_CLUT_RED : altdpram1 - PORT MAP(wren_a => FALCON_CLUT_WR(0), - wren_b => SYNTHESIZED_WIRE_5, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => FB_AD(31 DOWNTO 26), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_41, - q_b => CCF(23 DOWNTO 18)); + PORT MAP + ( + wren_a => FALCON_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_5, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(9 DOWNTO 2), + address_b => CLUT_ADR, + data_a => FB_AD(31 DOWNTO 26), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_41, + q_b => CCF(23 DOWNTO 18) + ); inst : lpm_fifo_dc0 - PORT MAP(wrreq => FIFO_WRE, - wrclk => DDRCLK(0), - rdreq => SYNTHESIZED_WIRE_60, - rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, - aclr => CLR_FIFO, - data => VDMC, - q => SYNTHESIZED_WIRE_63, - wrusedw => FIFO_MW); + PORT MAP + ( + wrreq => FIFO_WRE, + wrclk => DDRCLK(0), + rdreq => SYNTHESIZED_WIRE_60, + rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => CLR_FIFO, + data => VDMC, + q => SYNTHESIZED_WIRE_63, + wrusedw => FIFO_MW + ); inst1 : altddio_bidir0 - PORT MAP(oe => VDOUT_OE, - inclock => DDRCLK(1), - outclock => DDRCLK(3), - datain_h => VDP_OUT(63 DOWNTO 32), - datain_l => VDP_OUT(31 DOWNTO 0), - padio => VD, - combout => SYNTHESIZED_WIRE_15, - dataout_h => VDP_IN(31 DOWNTO 0), - dataout_l => VDP_IN(63 DOWNTO 32)); + PORT MAP + ( + oe => VDOUT_OE, + inclock => DDRCLK(1), + outclock => DDRCLK(3), + datain_h => VDP_OUT(63 DOWNTO 32), + datain_l => VDP_OUT(31 DOWNTO 0), + padio => VD, + combout => SYNTHESIZED_WIRE_15, + dataout_h => VDP_IN(31 DOWNTO 0), + dataout_l => VDP_IN(63 DOWNTO 32) + ); inst10 : lpm_ff4 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_7, - q => GDFX_TEMP_SIGNAL_0); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_7, + q => GDFX_TEMP_SIGNAL_0 + ); inst100 : lpm_muxvdm - PORT MAP(data0x => VDMB, - data10x => GDFX_TEMP_SIGNAL_1, - data11x => GDFX_TEMP_SIGNAL_2, - data12x => GDFX_TEMP_SIGNAL_3, - data13x => GDFX_TEMP_SIGNAL_4, - data14x => GDFX_TEMP_SIGNAL_5, - data15x => GDFX_TEMP_SIGNAL_6, - data1x => GDFX_TEMP_SIGNAL_7, - data2x => GDFX_TEMP_SIGNAL_8, - data3x => GDFX_TEMP_SIGNAL_9, - data4x => GDFX_TEMP_SIGNAL_10, - data5x => GDFX_TEMP_SIGNAL_11, - data6x => GDFX_TEMP_SIGNAL_12, - data7x => GDFX_TEMP_SIGNAL_13, - data8x => GDFX_TEMP_SIGNAL_14, - data9x => GDFX_TEMP_SIGNAL_15, - sel => VDM_SEL, - result => VDMC); + PORT MAP + ( + data0x => VDMB, + data10x => GDFX_TEMP_SIGNAL_1, + data11x => GDFX_TEMP_SIGNAL_2, + data12x => GDFX_TEMP_SIGNAL_3, + data13x => GDFX_TEMP_SIGNAL_4, + data14x => GDFX_TEMP_SIGNAL_5, + data15x => GDFX_TEMP_SIGNAL_6, + data1x => GDFX_TEMP_SIGNAL_7, + data2x => GDFX_TEMP_SIGNAL_8, + data3x => GDFX_TEMP_SIGNAL_9, + data4x => GDFX_TEMP_SIGNAL_10, + data5x => GDFX_TEMP_SIGNAL_11, + data6x => GDFX_TEMP_SIGNAL_12, + data7x => GDFX_TEMP_SIGNAL_13, + data8x => GDFX_TEMP_SIGNAL_14, + data9x => GDFX_TEMP_SIGNAL_15, + sel => VDM_SEL, + result => VDMC + ); inst102 : lpm_mux3 - PORT MAP(data1 => DFF_inst93, - data0 => ZR_C8(0), - sel => COLOR1, - result => ZR_C8B(0)); + PORT MAP + ( + data1 => DFF_inst93, + data0 => ZR_C8(0), + sel => COLOR1, + result => ZR_C8B(0) + ); @@ -1063,53 +1142,77 @@ BEGIN inst108 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(0), - data => VDR, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(0), + data => VDR, + tridata => FB_AD + ); inst109 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(1), - data => SYNTHESIZED_WIRE_11, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(1), + data => SYNTHESIZED_WIRE_11, + tridata => FB_AD + ); inst11 : lpm_ff5 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_12, - q => ZR_C8); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_12, + q => ZR_C8 + ); inst110 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(2), - data => SYNTHESIZED_WIRE_13, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(2), + data => SYNTHESIZED_WIRE_13, + tridata => FB_AD + ); inst119 : lpm_bustri_long - PORT MAP(enabledt => FB_VDOE(3), - data => SYNTHESIZED_WIRE_14, - tridata => FB_AD); + PORT MAP + ( + enabledt => FB_VDOE(3), + data => SYNTHESIZED_WIRE_14, + tridata => FB_AD + ); inst12 : lpm_ff1 - PORT MAP(clock => DDRCLK(0), - data => VDP_IN(31 DOWNTO 0), - q => VDVZ(31 DOWNTO 0)); + PORT MAP + ( + clock => DDRCLK(0), + data => VDP_IN(31 DOWNTO 0), + q => VDVZ(31 DOWNTO 0) + ); inst13 : lpm_ff0 - PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(0), - data => FB_AD, - q => FB_DDR(127 DOWNTO 96)); + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_LE(0), + data => FB_AD, + q => FB_DDR(127 DOWNTO 96) + ); inst14 : lpm_ff0 - PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(1), - data => FB_AD, - q => FB_DDR(95 DOWNTO 64)); + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_LE(1), + data => FB_AD, + q => FB_DDR(95 DOWNTO 64) + ); inst15 : lpm_ff0 diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 9712f63..8d9b983 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -670,186 +670,186 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 5e526e2..62ec98e 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -133,16 +133,20 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_port set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} # video RAM access -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] + +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} #************************************************************** From 703d95ee756937c62b4901dcf7bf44fb76e85203 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 12 Jan 2016 07:58:07 +0000 Subject: [PATCH 049/127] fix wire loop still works (kind of) - pixel errors in MiNT, does not boot (no picture) with "pure" EmuTOS? --- .../FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd | 2 +- FPGA_Quartus_13.1/firebee1.vhd | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index a5dbf21..2529551 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -71,7 +71,7 @@ ENTITY falconio_sdcard_ide_cf IS SD_CARD_DEDECT : IN std_logic; SD_WP : IN std_logic; nDACK0 : IN std_logic; - nFB_WR : INOUT std_logic; + nFB_WR : IN std_logic; WP_CF_CARD : IN std_logic; nWP : IN std_logic; nFB_CS2 : IN std_logic; diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 58cdcf8..d9dc215 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -333,7 +333,7 @@ BEGIN SD_CARD_DEDECT => SD_CARD_DEDECT, SD_WP => SD_WP, nDACK0 => nDACK0, - nFB_WR => nFB_WR_i, + nFB_WR => nFB_WR, WP_CF_CARD => WP_CF_CARD, nWP => nWP, nFB_CS2 => nFB_CS2, From 87100a7d62d0969215feafe8f71a8f8eb9ac6cc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 12 Jan 2016 08:00:20 +0000 Subject: [PATCH 050/127] fix formatting --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 46 +++++++++++++++++----------- FPGA_Quartus_13.1/firebee1.qws | Bin 6339 -> 5478 bytes 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 966b0be..858d553 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -242,27 +242,37 @@ ARCHITECTURE rtl OF ddr_ctr IS -- Sub Module Interface Section - component lpm_bustri_BYT - Port ( - data: in std_logic_vector(7 DOWNTO 0); - enabledt: in std_logic; - tridata: buffer std_logic_vector(7 DOWNTO 0) - ); - END component; + COMPONENT lpm_bustri_BYT + PORT + ( + data : IN std_logic_vector(7 DOWNTO 0); + enabledt : IN std_logic; + tridata : BUFFER std_logic_vector(7 DOWNTO 0) + ); + END COMPONENT lpm_bustri_BYT; - Function to_std_logic(X: in Boolean) return Std_Logic IS - VARIABLE ret : std_logic; - BEGIN - IF x THEN ret := '1'; ELSE ret := '0'; END IF; - return ret; - END to_std_logic; + FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS + VARIABLE ret : std_logic; + BEGIN + IF x THEN + ret := '1'; + ELSE + ret := '0'; + END IF; + RETURN ret; + END to_std_logic; - -- sizeIt replicates a value to an array of specific length. - Function sizeIt(a: std_Logic; len: integer) return std_logic_vector IS - VARIABLE rep: std_logic_vector( len-1 DOWNTO 0); - BEGIN for i in rep'range loop rep(i) := a; END loop; return rep; - END sizeIt; + -- sizeIt replicates a value to an array of specific length. + FUNCTION sizeit(a: std_logic; len: integer) RETURN std_logic_vector IS + VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0); + BEGIN + FOR i IN rep'RANGE LOOP + rep(i) := a; + END LOOP; + RETURN rep; + END sizeIt; + BEGIN -- Sub Module Section diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index 45ccb00133c94c66c2f6abd890f9ae092b620d40..2de15470570a5aec89d087b29e9c63673535dafc 100644 GIT binary patch literal 5478 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zX3?^T^y+Y$lN3D#@V`VW%j1(%%*cR;46O`Lj$GlqHYoFy`sQ{_PK;R+#}RQ>;Ao#L z-?b1)%!;^kG^WC=B1rCq1eLht^GK!6o_aDXSFl$-o|bGv-Jx!A4yx?Bqf=#{q;;51 zV)E3W>CsUGyFP3ZoQdXnxrG(Hi#A61k}j-^oHM4{F!u*mnRkfQ1YNqo1zv20d))Z< zWfq)IyB}>KnL5RCNP2o1Nk2!(GkoDJ^hM~$j0H&{SCd6#<15>1YO-mhADE)8MU=)p3EGT^K4&=M}{uNagn(`v*UtJ zb0G|!@7eJfqf=2cGCI#-2-T^@YGVffg3n}s0%CQ`kz3&C!RtO#sA5D=o`N?@2cveI zt6|LpT#t=-W;}}+%RJO!@D|Lp9=y#xyU%k5-dOsa2IPsE#l~nrr6~fx|7vCvUt#F8 z$cY*#{lLW^p^f3d?;Jm*Mxu}jQU}~+Q+%9|Y7Bu?bqExxL+NovY9ub5AT`cNH5&>% z)u!t0AEiU=27#5v<3$Uv7I9=XZdXr0TL)wL60;7+@`Ja3O#W0%uo-7;nkR}CRnJtd zXp|nnrVlE;5Sbdpr$B1(*C~ok{UbFDn;!i|+3w#W&Vg`7aYAxl!^F;>{U7-TJx9=4 z!C7h&kj>)WHz==C2miCR?1pc;J4~;tH^p{#brtCG2-|gsBL_xDAI`vyC36zr_9+Da JL$lJZ`~;u%Dii Date: Tue, 12 Jan 2016 17:10:19 +0000 Subject: [PATCH 051/127] fix ports --- FPGA_Quartus_13.1/firebee1.sdc | 28 ++-------------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 62ec98e..4753c0c 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -145,9 +145,8 @@ set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|a set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]} - +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} +set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} #************************************************************** # Set Clock Groups @@ -224,33 +223,10 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip # Set Maximum Delay #************************************************************** -# from here to the end of the file statements are just an experiment - -#set_max_delay 25 -from [get_ports {*}] - #************************************************************** # Set Minimum Delay #************************************************************** -#set_min_delay 0.5 -from [get_ports {*}] - #************************************************************** # Set Input Transition #************************************************************** -#set_input_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 -#set_input_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 -#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25 -#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5 - -# restrict timing of video controller - -#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}] -#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}] - -#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}] -#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}] - -#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}] -#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}] -#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}] -#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}] From 29df5559451eb6c2f495bd9b4f29a1c26f2622fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 12 Jan 2016 17:11:07 +0000 Subject: [PATCH 052/127] reformat --- FPGA_Quartus_13.1/Video/video.vhd | 923 ++++++++++++++++++------------ 1 file changed, 554 insertions(+), 369 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index b377532..a5a35e2 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -223,8 +223,8 @@ ARCHITECTURE rtl OF video IS FB_LE : OUT std_logic_vector(3 DOWNTO 0); FB_VDOE : OUT std_logic_vector(3 DOWNTO 0); SR_VDMP : OUT std_logic_vector(7 DOWNTO 0); - VA : OUT std_logic_vector(12 DOWNTO 0); - VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) + VA : OUT std_logic_vector(12 DOWNTO 0); + VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) ); END COMPONENT ddr_ctr; @@ -1216,132 +1216,175 @@ BEGIN inst15 : lpm_ff0 - PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(2), - data => FB_AD, - q => FB_DDR(63 DOWNTO 32)); + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_LE(2), + data => FB_AD, + q => FB_DDR(63 DOWNTO 32) + ); inst16 : lpm_ff0 - PORT MAP(clock => DDR_SYNC_66M, - enable => FB_LE(3), - data => FB_AD, - q => FB_DDR(31 DOWNTO 0)); + PORT MAP + ( + clock => DDR_SYNC_66M, + enable => FB_LE(3), + data => FB_AD, + q => FB_DDR(31 DOWNTO 0) + ); inst17 : lpm_ff0 - PORT MAP(clock => DDRCLK(0), - enable => DDR_FB(1), - data => VDP_IN(31 DOWNTO 0), - q => SYNTHESIZED_WIRE_11); + PORT MAP + ( + clock => DDRCLK(0), + enable => DDR_FB(1), + data => VDP_IN(31 DOWNTO 0), + q => SYNTHESIZED_WIRE_11 + ); inst18 : lpm_ff0 - PORT MAP(clock => DDRCLK(0), - enable => DDR_FB(0), - data => VDP_IN(63 DOWNTO 32), - q => SYNTHESIZED_WIRE_13); + PORT MAP + ( + clock => DDRCLK(0), + enable => DDR_FB(0), + data => VDP_IN(63 DOWNTO 32), + q => SYNTHESIZED_WIRE_13 + ); inst19 : lpm_ff0 - PORT MAP(clock => DDRCLK(0), - enable => DDR_FB(0), - data => VDP_IN(31 DOWNTO 0), - q => SYNTHESIZED_WIRE_14); + PORT MAP + ( + clock => DDRCLK(0), + enable => DDR_FB(0), + data => VDP_IN(31 DOWNTO 0), + q => SYNTHESIZED_WIRE_14 + ); inst2 : altddio_out0 - PORT MAP(outclock => DDRCLK(3), - datain_h => VDMP(7 DOWNTO 4), - datain_l => VDMP(3 DOWNTO 0), - dataout => VDM); + PORT MAP + ( + outclock => DDRCLK(3), + datain_h => VDMP(7 DOWNTO 4), + datain_l => VDMP(3 DOWNTO 0), + dataout => VDM + ); inst20 : lpm_ff1 - PORT MAP(clock => DDRCLK(0), - data => VDVZ(31 DOWNTO 0), - q => VDVZ(95 DOWNTO 64)); + PORT MAP + ( + clock => DDRCLK(0), + data => VDVZ(31 DOWNTO 0), + q => VDVZ(95 DOWNTO 64) + ); inst21 : lpm_mux0 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => FIFO_D(127 DOWNTO 96), - data1x => FIFO_D(95 DOWNTO 64), - data2x => FIFO_D(63 DOWNTO 32), - data3x => FIFO_D(31 DOWNTO 0), - sel => CLUT_MUX_ADR(1 DOWNTO 0), - result => SYNTHESIZED_WIRE_48); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 96), + data1x => FIFO_D(95 DOWNTO 64), + data2x => FIFO_D(63 DOWNTO 32), + data3x => FIFO_D(31 DOWNTO 0), + sel => CLUT_MUX_ADR(1 DOWNTO 0), + result => SYNTHESIZED_WIRE_48 + ); inst22 : lpm_mux5 - PORT MAP(data0x => FB_DDR(127 DOWNTO 64), - data1x => FB_DDR(63 DOWNTO 0), - data2x => BLITTER_DOUT(127 DOWNTO 64), - data3x => BLITTER_DOUT(63 DOWNTO 0), - sel => DDRWR_D_SEL, - result => VDP_OUT); + PORT MAP + ( + data0x => FB_DDR(127 DOWNTO 64), + data1x => FB_DDR(63 DOWNTO 0), + data2x => BLITTER_DOUT(127 DOWNTO 64), + data3x => BLITTER_DOUT(63 DOWNTO 0), + sel => DDRWR_D_SEL, + result => VDP_OUT + ); inst23 : lpm_constant2 - PORT MAP( result => GDFX_TEMP_SIGNAL_16); + PORT MAP + ( + result => GDFX_TEMP_SIGNAL_16 + ); inst24 : lpm_mux1 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => FIFO_D(127 DOWNTO 112), - data1x => FIFO_D(111 DOWNTO 96), - data2x => FIFO_D(95 DOWNTO 80), - data3x => FIFO_D(79 DOWNTO 64), - data4x => FIFO_D(63 DOWNTO 48), - data5x => FIFO_D(47 DOWNTO 32), - data6x => FIFO_D(31 DOWNTO 16), - data7x => FIFO_D(15 DOWNTO 0), - sel => CLUT_MUX_ADR(2 DOWNTO 0), - result => SYNTHESIZED_WIRE_7); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 112), + data1x => FIFO_D(111 DOWNTO 96), + data2x => FIFO_D(95 DOWNTO 80), + data3x => FIFO_D(79 DOWNTO 64), + data4x => FIFO_D(63 DOWNTO 48), + data5x => FIFO_D(47 DOWNTO 32), + data6x => FIFO_D(31 DOWNTO 16), + data7x => FIFO_D(15 DOWNTO 0), + sel => CLUT_MUX_ADR(2 DOWNTO 0), + result => SYNTHESIZED_WIRE_7 + ); inst25 : lpm_mux2 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => FIFO_D(127 DOWNTO 120), - data10x => FIFO_D(47 DOWNTO 40), - data11x => FIFO_D(39 DOWNTO 32), - data12x => FIFO_D(31 DOWNTO 24), - data13x => FIFO_D(23 DOWNTO 16), - data14x => FIFO_D(15 DOWNTO 8), - data15x => FIFO_D(7 DOWNTO 0), - data1x => FIFO_D(119 DOWNTO 112), - data2x => FIFO_D(111 DOWNTO 104), - data3x => FIFO_D(103 DOWNTO 96), - data4x => FIFO_D(95 DOWNTO 88), - data5x => FIFO_D(87 DOWNTO 80), - data6x => FIFO_D(79 DOWNTO 72), - data7x => FIFO_D(71 DOWNTO 64), - data8x => FIFO_D(63 DOWNTO 56), - data9x => FIFO_D(55 DOWNTO 48), - sel => CLUT_MUX_ADR, - result => SYNTHESIZED_WIRE_12); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => FIFO_D(127 DOWNTO 120), + data10x => FIFO_D(47 DOWNTO 40), + data11x => FIFO_D(39 DOWNTO 32), + data12x => FIFO_D(31 DOWNTO 24), + data13x => FIFO_D(23 DOWNTO 16), + data14x => FIFO_D(15 DOWNTO 8), + data15x => FIFO_D(7 DOWNTO 0), + data1x => FIFO_D(119 DOWNTO 112), + data2x => FIFO_D(111 DOWNTO 104), + data3x => FIFO_D(103 DOWNTO 96), + data4x => FIFO_D(95 DOWNTO 88), + data5x => FIFO_D(87 DOWNTO 80), + data6x => FIFO_D(79 DOWNTO 72), + data7x => FIFO_D(71 DOWNTO 64), + data8x => FIFO_D(63 DOWNTO 56), + data9x => FIFO_D(55 DOWNTO 48), + sel => CLUT_MUX_ADR, + result => SYNTHESIZED_WIRE_12 + ); inst26 : lpm_shiftreg4 - PORT MAP(clock => DDRCLK(0), - shiftin => SR_FIFO_WRE, - shiftout => FIFO_WRE); + PORT MAP + ( + clock => DDRCLK(0), + shiftin => SR_FIFO_WRE, + shiftout => FIFO_WRE + ); inst27 : lpm_latch0 - PORT MAP(gate => DDR_SYNC_66M, - data => SYNTHESIZED_WIRE_15, - q => VDR); - - - + PORT MAP + ( + gate => DDR_SYNC_66M, + data => SYNTHESIZED_WIRE_15, + q => VDR + ); + CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; inst3 : lpm_ff1 - PORT MAP(clock => DDRCLK(0), - data => VDP_IN(63 DOWNTO 32), - q => VDVZ(63 DOWNTO 32)); + PORT MAP + ( + clock => DDRCLK(0), + data => VDP_IN(63 DOWNTO 32), + q => VDVZ(63 DOWNTO 32) + ); CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; @@ -1349,244 +1392,323 @@ BEGIN SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; - - + inst36 : lpm_ff6 - PORT MAP(clock => DDRCLK(0), - enable => BLITTER_DACK(0), - data => VDVZ, - q => BLITTER_DIN); - + PORT MAP + ( + clock => DDRCLK(0), + enable => BLITTER_DACK(0), + data => VDVZ, + q => BLITTER_DIN + ); VDOUT_OE <= DDR_WR OR SR_DDR_WR; - - - VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA; - inst4 : lpm_ff1 - PORT MAP(clock => DDRCLK(0), - data => VDVZ(63 DOWNTO 32), - q => VDVZ(127 DOWNTO 96)); + PORT MAP + ( + clock => DDRCLK(0), + data => VDVZ(63 DOWNTO 32), + q => VDVZ(127 DOWNTO 96) + ); inst40 : mux41_0 - PORT MAP(S0 => COLOR2, - S1 => COLOR4, - D0 => CLUT_ADR6A, - INH => SYNTHESIZED_WIRE_19, - D1 => CLUT_ADR7A, - Q => SYNTHESIZED_WIRE_54); + PORT MAP + ( + S0 => COLOR2, + S1 => COLOR4, + D0 => CLUT_ADR6A, + INH => SYNTHESIZED_WIRE_19, + D1 => CLUT_ADR7A, + Q => SYNTHESIZED_WIRE_54 + ); inst41 : mux41_1 - PORT MAP(S0 => COLOR2, - S1 => COLOR4, - D0 => CLUT_ADR5A, - INH => SYNTHESIZED_WIRE_20, - D1 => CLUT_ADR6A, - Q => SYNTHESIZED_WIRE_53); + PORT MAP + ( + S0 => COLOR2, + S1 => COLOR4, + D0 => CLUT_ADR5A, + INH => SYNTHESIZED_WIRE_20, + D1 => CLUT_ADR6A, + Q => SYNTHESIZED_WIRE_53 + ); inst42 : mux41_2 - PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR7A, - S1 => COLOR4, - D0 => CLUT_ADR4A, - INH => SYNTHESIZED_WIRE_21, - D1 => CLUT_ADR5A, - Q => SYNTHESIZED_WIRE_52); + PORT MAP + ( + S0 => COLOR2, + D2 => CLUT_ADR7A, + S1 => COLOR4, + D0 => CLUT_ADR4A, + INH => SYNTHESIZED_WIRE_21, + D1 => CLUT_ADR5A, + Q => SYNTHESIZED_WIRE_52 + ); inst43 : mux41_3 - PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR6A, - S1 => COLOR4, - D0 => CLUT_ADR3A, - INH => SYNTHESIZED_WIRE_22, - D1 => CLUT_ADR4A, - Q => SYNTHESIZED_WIRE_51); + PORT MAP + ( + S0 => COLOR2, + D2 => CLUT_ADR6A, + S1 => COLOR4, + D0 => CLUT_ADR3A, + INH => SYNTHESIZED_WIRE_22, + D1 => CLUT_ADR4A, + Q => SYNTHESIZED_WIRE_51 + ); inst44 : mux41_4 - PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR5A, - S1 => COLOR4, - D0 => CLUT_ADR2A, - INH => SYNTHESIZED_WIRE_23, - D1 => CLUT_ADR3A, - Q => SYNTHESIZED_WIRE_50); + PORT MAP + ( + S0 => COLOR2, + D2 => CLUT_ADR5A, + S1 => COLOR4, + D0 => CLUT_ADR2A, + INH => SYNTHESIZED_WIRE_23, + D1 => CLUT_ADR3A, + Q => SYNTHESIZED_WIRE_50 + ); inst45 : mux41_5 - PORT MAP(S0 => COLOR2, - D2 => CLUT_ADR4A, - S1 => COLOR4, - D0 => CLUT_ADR1A, - INH => SYNTHESIZED_WIRE_24, - D1 => CLUT_ADR2A, - Q => SYNTHESIZED_WIRE_49); + PORT MAP + ( + S0 => COLOR2, + D2 => CLUT_ADR4A, + S1 => COLOR4, + D0 => CLUT_ADR1A, + INH => SYNTHESIZED_WIRE_24, + D1 => CLUT_ADR2A, + Q => SYNTHESIZED_WIRE_49 + ); inst46 : lpm_ff3 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_25, - q => SYNTHESIZED_WIRE_43); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_25, + q => SYNTHESIZED_WIRE_43 + ); inst47 : lpm_ff3 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => CCF, - q => SYNTHESIZED_WIRE_25); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => CCF, + q => SYNTHESIZED_WIRE_25 + ); inst49 : lpm_ff3 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_26, - q => SYNTHESIZED_WIRE_42); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_26, + q => SYNTHESIZED_WIRE_42 + ); inst5 : altddio_out2 - PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, - datain_h => SYNTHESIZED_WIRE_62, - datain_l => SYNTHESIZED_WIRE_62, - dataout => SYNTHESIZED_WIRE_65); + PORT MAP + ( + outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, + datain_h => SYNTHESIZED_WIRE_62, + datain_l => SYNTHESIZED_WIRE_62, + dataout => SYNTHESIZED_WIRE_65 + ); inst51 : lpm_bustri1 - PORT MAP(enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_29, - tridata => FB_AD(26 DOWNTO 24)); + PORT MAP + ( + enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_29, + tridata => FB_AD(26 DOWNTO 24) + ); inst52 : lpm_ff3 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => CCS, - q => SYNTHESIZED_WIRE_26); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => CCS, + q => SYNTHESIZED_WIRE_26 + ); inst53 : lpm_bustri_byt - PORT MAP(enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_30, - tridata => FB_AD(7 DOWNTO 0)); + PORT MAP + ( + enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_30, + tridata => FB_AD(7 DOWNTO 0) + ); inst54 : lpm_constant0 - PORT MAP( result => CCS(20 DOWNTO 16)); + PORT MAP + ( + result => CCS(20 DOWNTO 16) + ); inst56 : lpm_bustri1 - PORT MAP(enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_31, - tridata => FB_AD(22 DOWNTO 20)); + PORT MAP + ( + enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_31, + tridata => FB_AD(22 DOWNTO 20) + ); inst57 : lpm_bustri_byt - PORT MAP(enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_32, - tridata => FB_AD(15 DOWNTO 8)); + PORT MAP + ( + enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_32, + tridata => FB_AD(15 DOWNTO 8) + ); inst58 : lpm_bustri_byt - PORT MAP(enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_33, - tridata => FB_AD(23 DOWNTO 16)); + PORT MAP + ( + enabledt => ACP_CLUT_RD, + data => SYNTHESIZED_WIRE_33, + tridata => FB_AD(23 DOWNTO 16) + ); inst59 : lpm_constant0 - PORT MAP( result => CCS(12 DOWNTO 8)); + PORT MAP + ( + result => CCS(12 DOWNTO 8) + ); inst61 : lpm_bustri1 - PORT MAP(enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_34, - tridata => FB_AD(18 DOWNTO 16)); + PORT MAP + ( + enabledt => ST_CLUT_RD, + data => SYNTHESIZED_WIRE_34, + tridata => FB_AD(18 DOWNTO 16) + ); inst62 : lpm_muxdz - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - clken => FIFO_RDE, - sel => INTER_ZEI, - data0x => SYNTHESIZED_WIRE_63, - data1x => SYNTHESIZED_WIRE_36, - result => FIFO_D); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clken => FIFO_RDE, + sel => INTER_ZEI, + data0x => SYNTHESIZED_WIRE_63, + data1x => SYNTHESIZED_WIRE_36, + result => FIFO_D + ); inst63 : lpm_fifodz - PORT MAP(wrreq => SYNTHESIZED_WIRE_60, - rdreq => SYNTHESIZED_WIRE_38, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - aclr => DOP_FIFO_CLR, - data => SYNTHESIZED_WIRE_63, - q => SYNTHESIZED_WIRE_36); + PORT MAP + ( + wrreq => SYNTHESIZED_WIRE_60, + rdreq => SYNTHESIZED_WIRE_38, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + aclr => DOP_FIFO_CLR, + data => SYNTHESIZED_WIRE_63, + q => SYNTHESIZED_WIRE_36 + ); inst64 : lpm_constant0 - PORT MAP( result => CCS(4 DOWNTO 0)); + PORT MAP + ( + result => CCS(4 DOWNTO 0) + ); SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; inst66 : lpm_bustri3 - PORT MAP(enabledt => FALCON_CLUT_RDH, - data => SYNTHESIZED_WIRE_41, - tridata => FB_AD(31 DOWNTO 26)); + PORT MAP + ( + enabledt => FALCON_CLUT_RDH, + data => SYNTHESIZED_WIRE_41, + tridata => FB_AD(31 DOWNTO 26) + ); SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; - - - SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); - - inst7 : lpm_mux6 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data0x => SYNTHESIZED_WIRE_42, - data1x => SYNTHESIZED_WIRE_43, - data2x => (OTHERS => '0'), - data3x => (OTHERS => '0'), - data4x => CCA, - data5x => CC16, - data6x => CC24(23 DOWNTO 0), - data7x => BORDER_COLOR, - sel => CCSEL, - result => SYNTHESIZED_WIRE_62); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data0x => SYNTHESIZED_WIRE_42, + data1x => SYNTHESIZED_WIRE_43, + data2x => (OTHERS => '0'), + data3x => (OTHERS => '0'), + data4x => CCA, + data5x => CC16, + data6x => CC24(23 DOWNTO 0), + data7x => BORDER_COLOR, + sel => CCSEL, + result => SYNTHESIZED_WIRE_62 + ); inst70 : lpm_bustri3 - PORT MAP(enabledt => FALCON_CLUT_RDH, - data => SYNTHESIZED_WIRE_44, - tridata => FB_AD(23 DOWNTO 18)); + PORT MAP + ( + enabledt => FALCON_CLUT_RDH, + data => SYNTHESIZED_WIRE_44, + tridata => FB_AD(23 DOWNTO 18) + ); inst71 : lpm_ff6 - PORT MAP(clock => DDRCLK(0), - enable => FIFO_WRE, - data => VDVZ, - q => VDMA); + PORT MAP + ( + clock => DDRCLK(0), + enable => FIFO_WRE, + data => VDVZ, + q => VDMA + ); inst74 : lpm_bustri3 - PORT MAP(enabledt => FALCON_CLUT_RDL, - data => SYNTHESIZED_WIRE_45, - tridata => FB_AD(23 DOWNTO 18)); + PORT MAP + ( + enabledt => FALCON_CLUT_RDL, + data => SYNTHESIZED_WIRE_45, + tridata => FB_AD(23 DOWNTO 18) + ); inst77 : lpm_constant1 - PORT MAP( result => CCF(1 DOWNTO 0)); + PORT MAP + ( + result => CCF(1 DOWNTO 0) + ); @@ -1595,22 +1717,34 @@ BEGIN inst80 : lpm_constant1 - PORT MAP( result => CCF(9 DOWNTO 8)); + PORT MAP + ( + result => CCF(9 DOWNTO 8) + ); inst81 : lpm_mux4 - PORT MAP(sel => COLOR1, - data0x => ZR_C8(7 DOWNTO 1), - data1x => SYNTHESIZED_WIRE_47, - result => ZR_C8B(7 DOWNTO 1)); + PORT MAP + ( + sel => COLOR1, + data0x => ZR_C8(7 DOWNTO 1), + data1x => SYNTHESIZED_WIRE_47, + result => ZR_C8B(7 DOWNTO 1) + ); inst82 : lpm_constant3 - PORT MAP( result => SYNTHESIZED_WIRE_47); + PORT MAP + ( + result => SYNTHESIZED_WIRE_47 + ); inst83 : lpm_constant1 - PORT MAP( result => CCF(17 DOWNTO 16)); + PORT MAP + ( + result => CCF(17 DOWNTO 16) + ); PROCESS(DDRCLK(0), DDR_WR) @@ -1633,214 +1767,265 @@ BEGIN inst89 : lpm_shiftreg6 - PORT MAP(clock => DDRCLK(0), - shiftin => SR_BLITTER_DACK, - q => BLITTER_DACK); + PORT MAP + ( + clock => DDRCLK(0), + shiftin => SR_BLITTER_DACK, + q => BLITTER_DACK + ); inst9 : lpm_ff1 - PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - data => SYNTHESIZED_WIRE_48, - q => CC24); + PORT MAP + ( + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + data => SYNTHESIZED_WIRE_48, + q => CC24 + ); PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) BEGIN - IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN - DFF_inst91 <= CLUT_ADR(0); - END IF; + IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + DFF_inst91 <= CLUT_ADR(0); + END IF; END PROCESS; inst92 : lpm_shiftreg6 - PORT MAP(clock => DDRCLK(0), - shiftin => SR_DDR_FB, - q => DDR_FB); + PORT MAP + ( + clock => DDRCLK(0), + shiftin => SR_DDR_FB, + q => DDR_FB + ); PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) BEGIN - IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN - DFF_inst93 <= DFF_inst91; - END IF; + IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + DFF_inst93 <= DFF_inst91; + END IF; END PROCESS; inst94 : lpm_ff6 - PORT MAP(clock => DDRCLK(0), - enable => FIFO_WRE, - data => VDMA, - q => VDMB); + PORT MAP + ( + clock => DDRCLK(0), + enable => FIFO_WRE, + data => VDMA, + q => VDMB + ); PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) BEGIN - IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN - SYNTHESIZED_WIRE_64 <= FIFO_RDE; - END IF; + IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + SYNTHESIZED_WIRE_64 <= FIFO_RDE; + END IF; END PROCESS; inst97 : lpm_ff5 - PORT MAP(clock => DDRCLK(2), - data => SR_VDMP, - q => VDMP); + PORT MAP + ( + clock => DDRCLK(2), + data => SR_VDMP, + q => VDMP + ); sr0 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_49, - data => FIFO_D(127 DOWNTO 112), - shiftout => CLUT_ADR(0)); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_49, + data => FIFO_D(127 DOWNTO 112), + shiftout => CLUT_ADR(0) + ); sr1 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_50, - data => FIFO_D(111 DOWNTO 96), - shiftout => CLUT_ADR1A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_50, + data => FIFO_D(111 DOWNTO 96), + shiftout => CLUT_ADR1A + ); sr2 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_51, - data => FIFO_D(95 DOWNTO 80), - shiftout => CLUT_ADR2A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_51, + data => FIFO_D(95 DOWNTO 80), + shiftout => CLUT_ADR2A + ); sr3 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_52, - data => FIFO_D(79 DOWNTO 64), - shiftout => CLUT_ADR3A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_52, + data => FIFO_D(79 DOWNTO 64), + shiftout => CLUT_ADR3A + ); sr4 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_53, - data => FIFO_D(63 DOWNTO 48), - shiftout => CLUT_ADR4A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_53, + data => FIFO_D(63 DOWNTO 48), + shiftout => CLUT_ADR4A + ); sr5 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => SYNTHESIZED_WIRE_54, - data => FIFO_D(47 DOWNTO 32), - shiftout => CLUT_ADR5A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => SYNTHESIZED_WIRE_54, + data => FIFO_D(47 DOWNTO 32), + shiftout => CLUT_ADR5A + ); sr6 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => CLUT_ADR7A, - data => FIFO_D(31 DOWNTO 16), - shiftout => CLUT_ADR6A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => CLUT_ADR7A, + data => FIFO_D(31 DOWNTO 16), + shiftout => CLUT_ADR6A + ); sr7 : lpm_shiftreg0 - PORT MAP(load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, - shiftin => CLUT_ADR(0), - data => FIFO_D(15 DOWNTO 0), - shiftout => CLUT_ADR7A); + PORT MAP + ( + load => SYNTHESIZED_WIRE_64, + clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + shiftin => CLUT_ADR(0), + data => FIFO_D(15 DOWNTO 0), + shiftout => CLUT_ADR7A + ); ST_CLUT_BLUE : altdpram0 - PORT MAP(wren_a => ST_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_55, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(18 DOWNTO 16), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_34, - q_b => CCS(7 DOWNTO 5)); + PORT MAP + ( + wren_a => ST_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_55, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(18 DOWNTO 16), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_34, + q_b => CCS(7 DOWNTO 5) + ); ST_CLUT_GREEN : altdpram0 - PORT MAP(wren_a => ST_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_56, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(22 DOWNTO 20), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_31, - q_b => CCS(15 DOWNTO 13)); + PORT MAP + ( + wren_a => ST_CLUT_WR(1), + wren_b => SYNTHESIZED_WIRE_56, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(22 DOWNTO 20), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_31, + q_b => CCS(15 DOWNTO 13) + ); ST_CLUT_RED : altdpram0 - PORT MAP(wren_a => ST_CLUT_WR(0), - wren_b => SYNTHESIZED_WIRE_57, - clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(26 DOWNTO 24), - data_b => (OTHERS => '0'), - q_a => SYNTHESIZED_WIRE_29, - q_b => CCS(23 DOWNTO 21)); + PORT MAP + ( + wren_a => ST_CLUT_WR(0), + wren_b => SYNTHESIZED_WIRE_57, + clock_a => MAIN_CLK, + clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + address_a => FB_ADR(4 DOWNTO 1), + address_b => CLUT_ADR(3 DOWNTO 0), + data_a => FB_AD(26 DOWNTO 24), + data_b => (OTHERS => '0'), + q_a => SYNTHESIZED_WIRE_29, + q_b => CCS(23 DOWNTO 21) + ); i_video_mod_mux_clutctr : video_mod_mux_clutctr - PORT MAP(nRSTO => nRSTO, - MAIN_CLK => MAIN_CLK, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_WR => nFB_WR, - nFB_OE => nFB_OE, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - CLK33M => CLK33M, - CLK25M => CLK25M, - BLITTER_RUN => BLITTER_RUN, - CLK_VIDEO => CLK_VIDEO, - VR_BUSY => VR_BUSY, - FB_AD => FB_AD, - FB_ADR => FB_ADR, - VR_D => VR_D, - COLOR8 => COLOR8, - ACP_CLUT_RD => ACP_CLUT_RD, - COLOR1 => COLOR1, - FALCON_CLUT_RDH => FALCON_CLUT_RDH, - FALCON_CLUT_RDL => FALCON_CLUT_RDL, - ST_CLUT_RD => ST_CLUT_RD, - HSYNC => HSYNC, - VSYNC => VSYNC, - nBLANK => nBLANK, - nSYNC => nSYNC, - nPD_VGA => nPD_VGA, - FIFO_RDE => FIFO_RDE, - COLOR2 => COLOR2, - COLOR4 => COLOR4, - PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED, - BLITTER_ON => BLITTER_ON, - VIDEO_MOD_TA => VIDEO_MOD_TA, - INTER_ZEI => INTER_ZEI, - DOP_FIFO_CLR => DOP_FIFO_CLR, - VIDEO_RECONFIG => VIDEO_RECONFIG, - VR_WR => VR_WR, - VR_RD => VR_RD, - CLR_FIFO => CLR_FIFO, - ACP_CLUT_WR => ACP_CLUT_WR, - BORDER_COLOR => BORDER_COLOR, - CCSEL => CCSEL, - CLUT_MUX_ADR => CLUT_MUX_ADR, - CLUT_OFF => CLUT_OFF, - FALCON_CLUT_WR => FALCON_CLUT_WR, - ST_CLUT_WR => ST_CLUT_WR, - VIDEO_RAM_CTR => VIDEO_RAM_CTR); + PORT MAP + ( + nRSTO => nRSTO, + MAIN_CLK => MAIN_CLK, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_WR => nFB_WR, + nFB_OE => nFB_OE, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + CLK33M => CLK33M, + CLK25M => CLK25M, + BLITTER_RUN => BLITTER_RUN, + CLK_VIDEO => CLK_VIDEO, + VR_BUSY => VR_BUSY, + FB_AD => FB_AD, + FB_ADR => FB_ADR, + VR_D => VR_D, + COLOR8 => COLOR8, + ACP_CLUT_RD => ACP_CLUT_RD, + COLOR1 => COLOR1, + FALCON_CLUT_RDH => FALCON_CLUT_RDH, + FALCON_CLUT_RDL => FALCON_CLUT_RDL, + ST_CLUT_RD => ST_CLUT_RD, + HSYNC => HSYNC, + VSYNC => VSYNC, + nBLANK => nBLANK, + nSYNC => nSYNC, + nPD_VGA => nPD_VGA, + FIFO_RDE => FIFO_RDE, + COLOR2 => COLOR2, + COLOR4 => COLOR4, + PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED, + BLITTER_ON => BLITTER_ON, + VIDEO_MOD_TA => VIDEO_MOD_TA, + INTER_ZEI => INTER_ZEI, + DOP_FIFO_CLR => DOP_FIFO_CLR, + VIDEO_RECONFIG => VIDEO_RECONFIG, + VR_WR => VR_WR, + VR_RD => VR_RD, + CLR_FIFO => CLR_FIFO, + ACP_CLUT_WR => ACP_CLUT_WR, + BORDER_COLOR => BORDER_COLOR, + CCSEL => CCSEL, + CLUT_MUX_ADR => CLUT_MUX_ADR, + CLUT_OFF => CLUT_OFF, + FALCON_CLUT_WR => FALCON_CLUT_WR, + ST_CLUT_WR => ST_CLUT_WR, + VIDEO_RAM_CTR => VIDEO_RAM_CTR + ); PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; END rtl; \ No newline at end of file From c8b693d755e3b516155ab1ec685dbd630ce6b112 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 12 Jan 2016 17:11:58 +0000 Subject: [PATCH 053/127] add file --- FPGA_Quartus_13.1/firebee1.qsf | 369 +++++++++++++++++---------------- 1 file changed, 185 insertions(+), 184 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 8d9b983..f90ad68 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -42,7 +42,6 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== @@ -558,7 +557,6 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT @@ -670,186 +668,189 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From 621e2267a7508dfec1039127856efb0cf363f806 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 07:16:24 +0000 Subject: [PATCH 054/127] renamed pixel_clk_i --- FPGA_Quartus_13.1/Video/video.vhd | 82 +- FPGA_Quartus_13.1/firebee1.qsf | 1470 ++++++++++++++--------------- 2 files changed, 776 insertions(+), 776 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index a5a35e2..65b5ec3 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -724,7 +724,7 @@ ARCHITECTURE rtl OF video IS SIGNAL FIFO_WRE : std_logic; SIGNAL INTER_ZEI : std_logic; SIGNAL nFB_BURST : std_logic; - SIGNAL PIXEL_CLK_ALTERA_SYNTHESIZED : std_logic; + SIGNAL pixel_clk_i : std_logic; SIGNAL SR_BLITTER_DACK : std_logic; SIGNAL SR_DDR_FB : std_logic; SIGNAL SR_DDR_WR : std_logic; @@ -895,7 +895,7 @@ BEGIN wren_a => ACP_CLUT_WR(3), wren_b => SYNTHESIZED_WIRE_0, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => ZR_C8B, data_a => FB_AD(7 DOWNTO 0), @@ -911,7 +911,7 @@ BEGIN wren_a => ACP_CLUT_WR(2), wren_b => SYNTHESIZED_WIRE_1, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => ZR_C8B, data_a => FB_AD(15 DOWNTO 8), @@ -927,7 +927,7 @@ BEGIN wren_a => ACP_CLUT_WR(1), wren_b => SYNTHESIZED_WIRE_2, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => ZR_C8B, data_a => FB_AD(23 DOWNTO 16), @@ -1018,7 +1018,7 @@ BEGIN wren_a => FALCON_CLUT_WR(3), wren_b => SYNTHESIZED_WIRE_3, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => CLUT_ADR, data_a => FB_AD(23 DOWNTO 18), @@ -1034,7 +1034,7 @@ BEGIN wren_a => FALCON_CLUT_WR(1), wren_b => SYNTHESIZED_WIRE_4, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => CLUT_ADR, data_a => FB_AD(23 DOWNTO 18), @@ -1050,7 +1050,7 @@ BEGIN wren_a => FALCON_CLUT_WR(0), wren_b => SYNTHESIZED_WIRE_5, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => CLUT_ADR, data_a => FB_AD(31 DOWNTO 26), @@ -1066,7 +1066,7 @@ BEGIN wrreq => FIFO_WRE, wrclk => DDRCLK(0), rdreq => SYNTHESIZED_WIRE_60, - rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED, + rdclk => pixel_clk_i, aclr => CLR_FIFO, data => VDMC, q => SYNTHESIZED_WIRE_63, @@ -1092,7 +1092,7 @@ BEGIN inst10 : lpm_ff4 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => SYNTHESIZED_WIRE_7, q => GDFX_TEMP_SIGNAL_0 ); @@ -1162,7 +1162,7 @@ BEGIN inst11 : lpm_ff5 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => SYNTHESIZED_WIRE_12, q => ZR_C8 ); @@ -1287,7 +1287,7 @@ BEGIN inst21 : lpm_mux0 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data0x => FIFO_D(127 DOWNTO 96), data1x => FIFO_D(95 DOWNTO 64), data2x => FIFO_D(63 DOWNTO 32), @@ -1319,7 +1319,7 @@ BEGIN inst24 : lpm_mux1 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data0x => FIFO_D(127 DOWNTO 112), data1x => FIFO_D(111 DOWNTO 96), data2x => FIFO_D(95 DOWNTO 80), @@ -1336,7 +1336,7 @@ BEGIN inst25 : lpm_mux2 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data0x => FIFO_D(127 DOWNTO 120), data10x => FIFO_D(47 DOWNTO 40), data11x => FIFO_D(39 DOWNTO 32), @@ -1493,7 +1493,7 @@ BEGIN inst46 : lpm_ff3 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => SYNTHESIZED_WIRE_25, q => SYNTHESIZED_WIRE_43 ); @@ -1502,7 +1502,7 @@ BEGIN inst47 : lpm_ff3 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => CCF, q => SYNTHESIZED_WIRE_25 ); @@ -1512,7 +1512,7 @@ BEGIN inst49 : lpm_ff3 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => SYNTHESIZED_WIRE_26, q => SYNTHESIZED_WIRE_42 ); @@ -1521,7 +1521,7 @@ BEGIN inst5 : altddio_out2 PORT MAP ( - outclock => PIXEL_CLK_ALTERA_SYNTHESIZED, + outclock => pixel_clk_i, datain_h => SYNTHESIZED_WIRE_62, datain_l => SYNTHESIZED_WIRE_62, dataout => SYNTHESIZED_WIRE_65 @@ -1541,7 +1541,7 @@ BEGIN inst52 : lpm_ff3 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => CCS, q => SYNTHESIZED_WIRE_26 ); @@ -1612,7 +1612,7 @@ BEGIN inst62 : lpm_muxdz PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, clken => FIFO_RDE, sel => INTER_ZEI, data0x => SYNTHESIZED_WIRE_63, @@ -1626,7 +1626,7 @@ BEGIN ( wrreq => SYNTHESIZED_WIRE_60, rdreq => SYNTHESIZED_WIRE_38, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, aclr => DOP_FIFO_CLR, data => SYNTHESIZED_WIRE_63, q => SYNTHESIZED_WIRE_36 @@ -1658,7 +1658,7 @@ BEGIN inst7 : lpm_mux6 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data0x => SYNTHESIZED_WIRE_42, data1x => SYNTHESIZED_WIRE_43, data2x => (OTHERS => '0'), @@ -1778,15 +1778,15 @@ BEGIN inst9 : lpm_ff1 PORT MAP ( - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, data => SYNTHESIZED_WIRE_48, q => CC24 ); - PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) + PROCESS(pixel_clk_i) BEGIN - IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + IF (rising_edge(pixel_clk_i)) THEN DFF_inst91 <= CLUT_ADR(0); END IF; END PROCESS; @@ -1801,9 +1801,9 @@ BEGIN ); - PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) + PROCESS(pixel_clk_i) BEGIN - IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + IF (rising_edge(pixel_clk_i)) THEN DFF_inst93 <= DFF_inst91; END IF; END PROCESS; @@ -1819,9 +1819,9 @@ BEGIN ); - PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED) + PROCESS(pixel_clk_i) BEGIN - IF (rising_edge(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN + IF (rising_edge(pixel_clk_i)) THEN SYNTHESIZED_WIRE_64 <= FIFO_RDE; END IF; END PROCESS; @@ -1841,7 +1841,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_49, data => FIFO_D(127 DOWNTO 112), shiftout => CLUT_ADR(0) @@ -1852,7 +1852,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_50, data => FIFO_D(111 DOWNTO 96), shiftout => CLUT_ADR1A @@ -1863,7 +1863,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_51, data => FIFO_D(95 DOWNTO 80), shiftout => CLUT_ADR2A @@ -1874,7 +1874,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_52, data => FIFO_D(79 DOWNTO 64), shiftout => CLUT_ADR3A @@ -1885,7 +1885,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_53, data => FIFO_D(63 DOWNTO 48), shiftout => CLUT_ADR4A @@ -1896,7 +1896,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_54, data => FIFO_D(47 DOWNTO 32), shiftout => CLUT_ADR5A @@ -1907,7 +1907,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => CLUT_ADR7A, data => FIFO_D(31 DOWNTO 16), shiftout => CLUT_ADR6A @@ -1918,7 +1918,7 @@ BEGIN PORT MAP ( load => SYNTHESIZED_WIRE_64, - clock => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock => pixel_clk_i, shiftin => CLUT_ADR(0), data => FIFO_D(15 DOWNTO 0), shiftout => CLUT_ADR7A @@ -1931,7 +1931,7 @@ BEGIN wren_a => ST_CLUT_WR(1), wren_b => SYNTHESIZED_WIRE_55, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), address_b => CLUT_ADR(3 DOWNTO 0), data_a => FB_AD(18 DOWNTO 16), @@ -1947,7 +1947,7 @@ BEGIN wren_a => ST_CLUT_WR(1), wren_b => SYNTHESIZED_WIRE_56, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), address_b => CLUT_ADR(3 DOWNTO 0), data_a => FB_AD(22 DOWNTO 20), @@ -1963,7 +1963,7 @@ BEGIN wren_a => ST_CLUT_WR(0), wren_b => SYNTHESIZED_WIRE_57, clock_a => MAIN_CLK, - clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED, + clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), address_b => CLUT_ADR(3 DOWNTO 0), data_a => FB_AD(26 DOWNTO 24), @@ -2008,7 +2008,7 @@ BEGIN FIFO_RDE => FIFO_RDE, COLOR2 => COLOR2, COLOR4 => COLOR4, - PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED, + PIXEL_CLK => pixel_clk_i, BLITTER_ON => BLITTER_ON, VIDEO_MOD_TA => VIDEO_MOD_TA, INTER_ZEI => INTER_ZEI, @@ -2027,5 +2027,5 @@ BEGIN VIDEO_RAM_CTR => VIDEO_RAM_CTR ); - PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED; + PIXEL_CLK <= pixel_clk_i; END rtl; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index f90ad68..fa4da84 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,390 +39,390 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -432,7 +432,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -442,21 +442,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -466,76 +466,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -557,300 +557,300 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From 79a14e2a700ffb7bbe4a72b5b09aaa9e6c946c5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 07:27:57 +0000 Subject: [PATCH 055/127] reformat internal signals --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 58 ++++++++++++++++++++++++----- 1 file changed, 48 insertions(+), 10 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 858d553..5ab3810 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -228,16 +228,54 @@ ARCHITECTURE rtl OF ddr_ctr IS SIGNAL FIFO_AC_q : std_logic; SIGNAL FIFO_AC_clk : std_logic; SIGNAL FIFO_AC_d : std_logic; - SIGNAL FIFO_AC, FIFO_REQ_q, FIFO_REQ_clk, FIFO_REQ_d, FIFO_REQ, BLITTER_AC_q, - BLITTER_AC_clk, BLITTER_AC_d, BLITTER_AC, BLITTER_REQ_q, - BLITTER_REQ_clk, BLITTER_REQ_d, BLITTER_REQ, BUS_CYC_END, BUS_CYC_q, - BUS_CYC_clk, BUS_CYC_d, BUS_CYC, CPU_AC_q, CPU_AC_clk, CPU_AC_d, - CPU_AC, CPU_REQ_q, CPU_REQ_clk, CPU_REQ_d, CPU_REQ, CPU_SIG, - SR_DDRWR_D_SEL_q, SR_DDRWR_D_SEL_clk, SR_DDRWR_D_SEL_d, SR_DDR_WR_q, - SR_DDR_WR_clk, SR_DDR_WR_d, DDR_CONFIG, DDR_CS_q, DDR_CS_ena, - DDR_CS_clk, DDR_CS_d, DDR_CS, DDR_SEL, CPU_DDR_SYNC_q, - CPU_DDR_SYNC_clk, CPU_DDR_SYNC_d, CPU_DDR_SYNC, VWE, VRAS, VCAS, LINE: - std_logic; + SIGNAL FIFO_AC : std_logic; + SIGNAL FIFO_REQ_q : std_logic; + SIGNAL FIFO_REQ_clk : std_logic; + SIGNAL FIFO_REQ_d : std_logic; + SIGNAL FIFO_REQ : std_logic; + SIGNAL BLITTER_AC_q : std_logic; + SIGNAL BLITTER_AC_clk : std_logic; + SIGNAL BLITTER_AC_d : std_logic; + SIGNAL BLITTER_AC : std_logic; + SIGNAL BLITTER_REQ_q : std_logic; + SIGNAL BLITTER_REQ_clk : std_logic; + SIGNAL BLITTER_REQ_d : std_logic; + SIGNAL BLITTER_REQ : std_logic; + SIGNAL BUS_CYC_END : std_logic; + SIGNAL BUS_CYC_q : std_logic; + SIGNAL BUS_CYC_clk : std_logic; + SIGNAL BUS_CYC_d : std_logic; + SIGNAL BUS_CYC : std_logic; + SIGNAL CPU_AC_q : std_logic; + SIGNAL CPU_AC_clk : std_logic; + SIGNAL CPU_AC_d : std_logic; + SIGNAL CPU_AC : std_logic; + SIGNAL CPU_REQ_q : std_logic; + SIGNAL CPU_REQ_clk : std_logic; + SIGNAL CPU_REQ_d : std_logic; + SIGNAL CPU_REQ : std_logic; + SIGNAL CPU_SIG : std_logic; + SIGNAL SR_DDRWR_D_SEL_q : std_logic; + SIGNAL SR_DDRWR_D_SEL_clk : std_logic; + SIGNAL SR_DDRWR_D_SEL_d : std_logic; + SIGNAL SR_DDR_WR_q : std_logic; + SIGNAL SR_DDR_WR_clk : std_logic; + SIGNAL SR_DDR_WR_d : std_logic; + SIGNAL DDR_CONFIG : std_logic; + SIGNAL DDR_CS_q : std_logic; + SIGNAL DDR_CS_ena : std_logic; + SIGNAL DDR_CS_clk : std_logic; + SIGNAL DDR_CS_d : std_logic; + SIGNAL DDR_CS : std_logic; + SIGNAL DDR_SEL : std_logic; + SIGNAL CPU_DDR_SYNC_q : std_logic; + SIGNAL CPU_DDR_SYNC_clk : std_logic; + SIGNAL CPU_DDR_SYNC_d : std_logic; + SIGNAL CPU_DDR_SYNC : std_logic; + SIGNAL VWE : std_logic; + SIGNAL VRAS : std_logic; + SIGNAL VCAS : std_logic; + SIGNAL LINE : std_logic; -- Sub Module Interface Section From 5183d08d601689938b8e139320ab64d5b7980a93 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 12:53:03 +0000 Subject: [PATCH 056/127] finish conversion to vhdl --- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 12 +- .../Video/video_mod_mux_clutctr.vhd | 2017 +++++++++++++++++ FPGA_Quartus_13.1/firebee1.qsf | 1471 ++++++------ 3 files changed, 2759 insertions(+), 741 deletions(-) create mode 100755 FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 4703a54..c2a30de 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -604,11 +604,11 @@ BEGIN DOP_FIFO_CLR.CLK = PIXEL_CLK; DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - RAND_LINKS[] = HBE[] & ACP_VIDEO_ON +% RAND_LINKS[] = HBE[] & ACP_VIDEO_ON # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - +% HDIS_START[] = HDB[] & ACP_VIDEO_ON # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- @@ -618,16 +618,16 @@ BEGIN RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON # HDIS_END[] + 1 & !ACP_VIDEO_ON; -- - HS_START[] = HSS[] & ACP_VIDEO_ON +% HS_START[] = HSS[] & ACP_VIDEO_ON # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - - H_TOTAL[] = HHT[] & ACP_VIDEO_ON + % +% H_TOTAL[] = HHT[] & ACP_VIDEO_ON # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - +% RAND_OBEN[] = VBE[] & ACP_VIDEO_ON # 31 & !ACP_VIDEO_ON & ATARI_SYNC # (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd new file mode 100755 index 0000000..cb9b77d --- /dev/null +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -0,0 +1,2017 @@ +-- Xilinx XPort Language Converter, Version 4.1 (110) +-- +-- AHDL Design Source: VIDEO_MOD_MUX_CLUTCTR.tdf +-- VHDL Design Output: VIDEO_MOD_MUX_CLUTCTR.vhd +-- Created 13-Jan-2016 10:03 AM +-- +-- Copyright (c) 2016, Xilinx, Inc. All Rights Reserved. +-- Xilinx Inc makes no warranty, expressed or implied, with respect to +-- the operation and/or functionality of the converted output files. +-- + +-- VIDEO MODUSE UND CLUT CONTROL + + +-- Some names could not be written out to VHDL as they were +-- in the source, and have been changed: +-- +-- AHDL VHDL +-- ==== ==== +-- VERZ0_.q VERZ0_q +-- VERZ0_.prn VERZ0_prn +-- VERZ0_.clrn VERZ0_clrn +-- VERZ0_.clk VERZ0_clk +-- VERZ0_.d VERZ0_d +-- VERZ0_ VERZ0 +-- VERZ1_.q VERZ1_q +-- VERZ1_.prn VERZ1_prn +-- VERZ1_.clrn VERZ1_clrn +-- VERZ1_.clk VERZ1_clk +-- VERZ1_.d VERZ1_d +-- VERZ1_ VERZ1 +-- VERZ2_.q VERZ2_q +-- VERZ2_.prn VERZ2_prn +-- VERZ2_.clrn VERZ2_clrn +-- VERZ2_.clk VERZ2_clk +-- VERZ2_.d VERZ2_d +-- VERZ2_ VERZ2 +-- CLUT_MUX_AV0_.q CLUT_MUX_AV0_q +-- CLUT_MUX_AV0_.prn CLUT_MUX_AV0_prn +-- CLUT_MUX_AV0_.clrn CLUT_MUX_AV0_clrn +-- CLUT_MUX_AV0_.clk CLUT_MUX_AV0_clk +-- CLUT_MUX_AV0_.d CLUT_MUX_AV0_d +-- CLUT_MUX_AV0_ CLUT_MUX_AV0 +-- CLUT_MUX_AV1_.q CLUT_MUX_AV1_q +-- CLUT_MUX_AV1_.prn CLUT_MUX_AV1_prn +-- CLUT_MUX_AV1_.clrn CLUT_MUX_AV1_clrn +-- CLUT_MUX_AV1_.clk CLUT_MUX_AV1_clk +-- CLUT_MUX_AV1_.d CLUT_MUX_AV1_d +-- CLUT_MUX_AV1_ CLUT_MUX_AV1 + + +-- CREATED BY FREDI ASCHWANDEN +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY video_mod_mux_clutctr IS + PORT + ( + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nFB_BURST : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + CLK33M, CLK25M, BLITTER_RUN, CLK_VIDEO: in std_logic; + VR_D: in std_logic_vector(8 downto 0); + VR_BUSY: in std_logic; + COLOR8, ACP_CLUT_RD, COLOR1, FALCON_CLUT_RDH, FALCON_CLUT_RDL: buffer + std_logic; + FALCON_CLUT_WR: buffer std_logic_vector(3 downto 0); + ST_CLUT_RD: buffer std_logic; + ST_CLUT_WR: buffer std_logic_vector(1 downto 0); + CLUT_MUX_ADR: buffer std_logic_vector(3 downto 0); + HSYNC, VSYNC, nBLANK, nSYNC, nPD_VGA, FIFO_RDE, COLOR2, COLOR4, + PIXEL_CLK: buffer std_logic; + CLUT_OFF: buffer std_logic_vector(3 downto 0); + BLITTER_ON: buffer std_logic; + VIDEO_RAM_CTR: buffer std_logic_vector(15 downto 0); + VIDEO_MOD_TA: buffer std_logic; + BORDER_COLOR: buffer std_logic_vector(23 downto 0); + CCSEL: buffer std_logic_vector(2 downto 0); + ACP_CLUT_WR: buffer std_logic_vector(3 downto 0); + INTER_ZEI, DOP_FIFO_CLR, VIDEO_RECONFIG, VR_WR, VR_RD, CLR_FIFO: buffer + std_logic; + FB_AD: inout std_logic_vector(31 downto 0) + ); +end VIDEO_MOD_MUX_CLUTCTR; + + +architecture VIDEO_MOD_MUX_CLUTCTR_behav of VIDEO_MOD_MUX_CLUTCTR is + +-- DIV. CONTROL REGISTER +-- BRAUCHT EIN WAITSTAT +-- LÄNGE HSYNC PULS IN PIXEL_CLK +-- LETZTES PIXEL EINER ZEILE ERREICHT +-- ATARI RESOLUTION +-- HORIZONTAL TIMING 640x480 +-- VERTIKAL TIMING 640x480 +-- HORIZONTAL TIMING 320x240 +-- VERTIKAL TIMING 320x240 +-- HORIZONTAL +-- VERTIKAL + signal VR_DOUT: std_logic_vector(8 downto 0); + signal VR_DOUT_d: std_logic_vector(8 downto 0); + signal VR_DOUT_q: std_logic_vector(8 downto 0); + signal VR_FRQ: std_logic_vector(7 downto 0); + signal VR_FRQ_d: std_logic_vector(7 downto 0); + signal VR_FRQ_q: std_logic_vector(7 downto 0); + signal FB_B: std_logic_vector(3 downto 0); + signal FB_16B: std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE: std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE_d: std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE_q: std_logic_vector(1 downto 0); + signal FALCON_SHIFT_MODE: std_logic_vector(10 downto 0); + signal FALCON_SHIFT_MODE_d: std_logic_vector(10 downto 0); + signal FALCON_SHIFT_MODE_q: std_logic_vector(10 downto 0); + signal CLUT_MUX_ADR_d: std_logic_vector(3 downto 0); + signal CLUT_MUX_ADR_q: std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1: std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1_d: std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1_q: std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0: std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0_d: std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0_q: std_logic_vector(3 downto 0); + signal ACP_VCTR: std_logic_vector(31 downto 0); + signal ACP_VCTR_d: std_logic_vector(31 downto 0); + signal ACP_VCTR_q: std_logic_vector(31 downto 0); + signal BORDER_COLOR_d: std_logic_vector(23 downto 0); + signal BORDER_COLOR_q: std_logic_vector(23 downto 0); + signal SYS_CTR: std_logic_vector(6 downto 0); + signal SYS_CTR_d: std_logic_vector(6 downto 0); + signal SYS_CTR_q: std_logic_vector(6 downto 0); + signal LOF: std_logic_vector(15 downto 0); + signal LOF_d: std_logic_vector(15 downto 0); + signal LOF_q: std_logic_vector(15 downto 0); + signal LWD: std_logic_vector(15 downto 0); + signal LWD_d: std_logic_vector(15 downto 0); + signal LWD_q: std_logic_vector(15 downto 0); + signal HSYNC_I: std_logic_vector(7 downto 0); + signal HSYNC_I_d: std_logic_vector(7 downto 0); + signal HSYNC_I_q: std_logic_vector(7 downto 0); + signal HSY_LEN: std_logic_vector(7 downto 0); + signal HSY_LEN_d: std_logic_vector(7 downto 0); + signal HSY_LEN_q: std_logic_vector(7 downto 0); + signal VSYNC_I: std_logic_vector(2 downto 0); + signal VSYNC_I_d: std_logic_vector(2 downto 0); + signal VSYNC_I_q: std_logic_vector(2 downto 0); + signal VHCNT: std_logic_vector(11 downto 0); + signal VHCNT_d: std_logic_vector(11 downto 0); + signal VHCNT_q: std_logic_vector(11 downto 0); + signal SUB_PIXEL_CNT: std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_d: std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_q: std_logic_vector(6 downto 0); + signal VVCNT: std_logic_vector(10 downto 0); + signal VVCNT_d: std_logic_vector(10 downto 0); + signal VVCNT_q: std_logic_vector(10 downto 0); + signal VERZ2: std_logic_vector(9 downto 0); + signal VERZ2_d: std_logic_vector(9 downto 0); + signal VERZ2_q: std_logic_vector(9 downto 0); + signal VERZ1: std_logic_vector(9 downto 0); + signal VERZ1_d: std_logic_vector(9 downto 0); + signal VERZ1_q: std_logic_vector(9 downto 0); + signal VERZ0: std_logic_vector(9 downto 0); + signal VERZ0_d: std_logic_vector(9 downto 0); + signal VERZ0_q: std_logic_vector(9 downto 0); + signal RAND: std_logic_vector(6 downto 0); + signal RAND_d: std_logic_vector(6 downto 0); + signal RAND_q: std_logic_vector(6 downto 0); + signal CCSEL_d: std_logic_vector(2 downto 0); + signal CCSEL_q: std_logic_vector(2 downto 0); + signal ATARI_HH: std_logic_vector(31 downto 0); + signal ATARI_HH_d: std_logic_vector(31 downto 0); + signal ATARI_HH_q: std_logic_vector(31 downto 0); + signal ATARI_VH: std_logic_vector(31 downto 0); + signal ATARI_VH_d: std_logic_vector(31 downto 0); + signal ATARI_VH_q: std_logic_vector(31 downto 0); + signal ATARI_HL: std_logic_vector(31 downto 0); + signal ATARI_HL_d: std_logic_vector(31 downto 0); + signal ATARI_HL_q: std_logic_vector(31 downto 0); + signal ATARI_VL: std_logic_vector(31 downto 0); + signal ATARI_VL_d: std_logic_vector(31 downto 0); + signal ATARI_VL_q: std_logic_vector(31 downto 0); + signal RAND_LINKS: std_logic_vector(11 downto 0); + signal HDIS_START: std_logic_vector(11 downto 0); + signal HDIS_END: std_logic_vector(11 downto 0); + signal RAND_RECHTS: std_logic_vector(11 downto 0); + signal HS_START: std_logic_vector(11 downto 0); + signal H_TOTAL: std_logic_vector(11 downto 0); + signal HDIS_LEN: std_logic_vector(11 downto 0); + signal MULF: std_logic_vector(5 downto 0); + signal HHT: std_logic_vector(11 downto 0); + signal HHT_d: std_logic_vector(11 downto 0); + signal HHT_q: std_logic_vector(11 downto 0); + signal HBE: std_logic_vector(11 downto 0); + signal HBE_d: std_logic_vector(11 downto 0); + signal HBE_q: std_logic_vector(11 downto 0); + signal HDB: std_logic_vector(11 downto 0); + signal HDB_d: std_logic_vector(11 downto 0); + signal HDB_q: std_logic_vector(11 downto 0); + signal HDE: std_logic_vector(11 downto 0); + signal HDE_d: std_logic_vector(11 downto 0); + signal HDE_q: std_logic_vector(11 downto 0); + signal HBB: std_logic_vector(11 downto 0); + signal HBB_d: std_logic_vector(11 downto 0); + signal HBB_q: std_logic_vector(11 downto 0); + signal HSS: std_logic_vector(11 downto 0); + signal HSS_d: std_logic_vector(11 downto 0); + signal HSS_q: std_logic_vector(11 downto 0); + signal RAND_OBEN: std_logic_vector(10 downto 0); + signal VDIS_START: std_logic_vector(10 downto 0); + signal VDIS_END: std_logic_vector(10 downto 0); + signal RAND_UNTEN: std_logic_vector(10 downto 0); + signal VS_START: std_logic_vector(10 downto 0); + signal V_TOTAL: std_logic_vector(10 downto 0); + signal VBE: std_logic_vector(10 downto 0); + signal VBE_d: std_logic_vector(10 downto 0); + signal VBE_q: std_logic_vector(10 downto 0); + signal VDB: std_logic_vector(10 downto 0); + signal VDB_d: std_logic_vector(10 downto 0); + signal VDB_q: std_logic_vector(10 downto 0); + signal VDE: std_logic_vector(10 downto 0); + signal VDE_d: std_logic_vector(10 downto 0); + signal VDE_q: std_logic_vector(10 downto 0); + signal VBB: std_logic_vector(10 downto 0); + signal VBB_d: std_logic_vector(10 downto 0); + signal VBB_q: std_logic_vector(10 downto 0); + signal VSS: std_logic_vector(10 downto 0); + signal VSS_d: std_logic_vector(10 downto 0); + signal VSS_q: std_logic_vector(10 downto 0); + signal VFT: std_logic_vector(10 downto 0); + signal VFT_d: std_logic_vector(10 downto 0); + signal VFT_q: std_logic_vector(10 downto 0); + signal VCO: std_logic_vector(8 downto 0); + signal VCO_d: std_logic_vector(8 downto 0); + signal VCO_ena: std_logic_vector(8 downto 0); + signal VCO_q: std_logic_vector(8 downto 0); + signal VCNTRL: std_logic_vector(3 downto 0); + signal VCNTRL_d: std_logic_vector(3 downto 0); + signal VCNTRL_q: std_logic_vector(3 downto 0); + signal u0_data: std_logic_vector(15 downto 0); + signal u0_tridata: std_logic_vector(15 downto 0); + signal u1_data: std_logic_vector(15 downto 0); + signal u1_tridata: std_logic_vector(15 downto 0); + signal ST_SHIFT_MODE0_clk_ctrl, ST_SHIFT_MODE0_ena_ctrl, + FALCON_SHIFT_MODE0_clk_ctrl, FALCON_SHIFT_MODE8_ena_ctrl, + FALCON_SHIFT_MODE0_ena_ctrl, ACP_VCTR0_clk_ctrl, ACP_VCTR24_ena_ctrl, + ACP_VCTR16_ena_ctrl, ACP_VCTR8_ena_ctrl, ACP_VCTR0_ena_ctrl, + ATARI_HH0_clk_ctrl, ATARI_HH24_ena_ctrl, ATARI_HH16_ena_ctrl, + ATARI_HH8_ena_ctrl, ATARI_HH0_ena_ctrl, ATARI_VH0_clk_ctrl, + ATARI_VH24_ena_ctrl, ATARI_VH16_ena_ctrl, ATARI_VH8_ena_ctrl, + ATARI_VH0_ena_ctrl, ATARI_HL0_clk_ctrl, ATARI_HL24_ena_ctrl, + ATARI_HL16_ena_ctrl, ATARI_HL8_ena_ctrl, ATARI_HL0_ena_ctrl, + ATARI_VL0_clk_ctrl, ATARI_VL24_ena_ctrl, ATARI_VL16_ena_ctrl, + ATARI_VL8_ena_ctrl, ATARI_VL0_ena_ctrl, VR_DOUT0_clk_ctrl, + VR_DOUT0_ena_ctrl, VR_FRQ0_clk_ctrl, VR_FRQ0_ena_ctrl, + ACP_VCTR6_ena_ctrl, CCSEL0_clk_ctrl, BORDER_COLOR0_clk_ctrl, + BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl, + BORDER_COLOR0_ena_ctrl, SYS_CTR0_clk_ctrl, SYS_CTR0_ena_ctrl, + LOF0_clk_ctrl, LOF8_ena_ctrl, LOF0_ena_ctrl, LWD0_clk_ctrl, + LWD8_ena_ctrl, LWD0_ena_ctrl, HHT0_clk_ctrl, HHT8_ena_ctrl, + HHT0_ena_ctrl, HBE0_clk_ctrl, HBE8_ena_ctrl, HBE0_ena_ctrl, + HDB0_clk_ctrl, HDB8_ena_ctrl, HDB0_ena_ctrl, HDE0_clk_ctrl, + HDE8_ena_ctrl, HDE0_ena_ctrl, HBB0_clk_ctrl, HBB8_ena_ctrl, + HBB0_ena_ctrl, HSS0_clk_ctrl, HSS8_ena_ctrl, HSS0_ena_ctrl, + VBE0_clk_ctrl, VBE8_ena_ctrl, VBE0_ena_ctrl, VDB0_clk_ctrl, + VDB8_ena_ctrl, VDB0_ena_ctrl, VDE0_clk_ctrl, VDE8_ena_ctrl, + VDE0_ena_ctrl, VBB0_clk_ctrl, VBB8_ena_ctrl, VBB0_ena_ctrl, + VSS0_clk_ctrl, VSS8_ena_ctrl, VSS0_ena_ctrl, VFT0_clk_ctrl, + VFT8_ena_ctrl, VFT0_ena_ctrl, VCO0_clk_ctrl, VCO0_ena_ctrl, + VCNTRL0_clk_ctrl, VCNTRL0_ena_ctrl, HSY_LEN0_clk_ctrl, + VHCNT0_clk_ctrl, VVCNT0_clk_ctrl, VVCNT0_ena_ctrl, HSYNC_I0_clk_ctrl, + VSYNC_I0_clk_ctrl, VSYNC_I0_ena_ctrl, VERZ2_0_clk_ctrl, + VERZ1_0_clk_ctrl, VERZ0_0_clk_ctrl, RAND0_clk_ctrl, + SUB_PIXEL_CNT0_clk_ctrl, SUB_PIXEL_CNT0_ena_ctrl, + CLUT_MUX_ADR0_clk_ctrl, CLUT_MUX_AV1_0_clk_ctrl, + CLUT_MUX_AV0_0_clk_ctrl, COLOR8_2, COLOR8_1, COLOR1_3, COLOR1_2, + COLOR1_1, COLOR4_2, COLOR4_1, COLOR16_2, COLOR16_1, gnd, u1_enabledt, + u0_enabledt, VCNTRL_CS, VCO_CS, VFT_CS, VSS_CS, VBB_CS, VDE_CS, + VDB_CS, VBE_CS, DOP_FIFO_CLR_q, DOP_FIFO_CLR_clk, DOP_FIFO_CLR_d, + DOP_ZEI_q, DOP_ZEI_clk, DOP_ZEI_d, DOP_ZEI, INTER_ZEI_q, + INTER_ZEI_clk, INTER_ZEI_d, ST_VIDEO, FALCON_VIDEO, HSS_CS, HBB_CS, + HDE_CS, HDB_CS, HBE_CS, HHT_CS, ATARI_VL_CS, ATARI_HL_CS, ATARI_VH_CS, + ATARI_HH_CS, ATARI_SYNC, COLOR24, COLOR16, SYNC_PIX2_q, SYNC_PIX2_clk, + SYNC_PIX2_d, SYNC_PIX2, SYNC_PIX1_q, SYNC_PIX1_clk, SYNC_PIX1_d, + SYNC_PIX1, SYNC_PIX_q, SYNC_PIX_clk, SYNC_PIX_d, SYNC_PIX, + START_ZEILE_q, START_ZEILE_ena, START_ZEILE_clk, START_ZEILE_d, + START_ZEILE, CLR_FIFO_q, CLR_FIFO_ena, CLR_FIFO_clk, CLR_FIFO_d, + FIFO_RDE_q, FIFO_RDE_clk, FIFO_RDE_d, RAND_ON, VCO_OFF_q, VCO_OFF_clk, + VCO_OFF_d, VCO_OFF, VCO_ON_q, VCO_ON_clk, VCO_ON_d, VCO_ON, VCO_ZL_q, + VCO_ZL_ena, VCO_ZL_clk, VCO_ZL_d, VCO_ZL, VDTRON_q, VDTRON_clk, + VDTRON_d, VDTRON, DPO_OFF_q, DPO_OFF_clk, DPO_OFF_d, DPO_OFF, + DPO_ON_q, DPO_ON_clk, DPO_ON_d, DPO_ON, DPO_ZL_q, DPO_ZL_ena, + DPO_ZL_clk, DPO_ZL_d, DPO_ZL, DISP_ON_q, DISP_ON_clk, DISP_ON_d, + DISP_ON, nBLANK_q, nBLANK_clk, nBLANK_d, VSYNC_START_q, + VSYNC_START_ena, VSYNC_START_clk, VSYNC_START_d, VSYNC_START, VSYNC_q, + VSYNC_clk, VSYNC_d, LAST_q, LAST_clk, LAST_d, LAST, HSYNC_START_q, + HSYNC_START_clk, HSYNC_START_d, HSYNC_START, HSYNC_q, HSYNC_clk, + HSYNC_d, CLUT_TA_q, CLUT_TA_clk, CLUT_TA_d, CLUT_TA, LWD_CS, LOF_CS, + SYS_CTR_CS, ACP_VIDEO_ON, BORDER_COLOR_CS, ACP_VCTR_CS, + FALCON_SHIFT_MODE_CS, ST_SHIFT_MODE_CS, ST_CLUT, ST_CLUT_CS, + FALCON_CLUT, FALCON_CLUT_CS, VIDEO_RECONFIG_q, VIDEO_RECONFIG_clk, + VIDEO_RECONFIG_d, VIDEO_PLL_RECONFIG_CS, VR_WR_q, VR_WR_clk, VR_WR_d, + VIDEO_PLL_CONFIG_CS, ACP_CLUT, ACP_CLUT_CS, CLK13M_q, CLK13M_clk, + CLK13M_d, CLK13M, CLK17M_q, CLK17M_clk, CLK17M_d, CLK17M: std_logic; + +-- Sub Module Interface Section + + + component lpm_bustri_WORD + Port ( + data: in std_logic_vector(15 downto 0); + enabledt: in std_logic; + tridata: buffer std_logic_vector(15 downto 0) + ); + end component; + + Function to_std_logic(X: in Boolean) return Std_Logic is + variable ret : std_logic; + begin + if x then ret := '1'; else ret := '0'; end if; + return ret; + end to_std_logic; + + + -- sizeIt replicates a value to an array of specific length. + Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is + variable rep: std_logic_vector( len-1 downto 0); + begin for i in rep'range loop rep(i) := a; end loop; return rep; + end sizeIt; +begin + +-- Sub Module Section + u0: lpm_bustri_WORD port map (data=>u0_data, enabledt=>u0_enabledt, + tridata=>u0_tridata); + u1: lpm_bustri_WORD port map (data=>u1_data, enabledt=>u1_enabledt, + tridata=>u1_tridata); + +-- Register Section + + CLUT_MUX_ADR <= CLUT_MUX_ADR_q; + process (CLUT_MUX_ADR0_clk_ctrl) begin + if CLUT_MUX_ADR0_clk_ctrl'event and CLUT_MUX_ADR0_clk_ctrl='1' then + CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; + end if; + end process; + + HSYNC <= HSYNC_q; + process (HSYNC_clk) begin + if HSYNC_clk'event and HSYNC_clk='1' then + HSYNC_q <= HSYNC_d; + end if; + end process; + + VSYNC <= VSYNC_q; + process (VSYNC_clk) begin + if VSYNC_clk'event and VSYNC_clk='1' then + VSYNC_q <= VSYNC_d; + end if; + end process; + + nBLANK <= nBLANK_q; + process (nBLANK_clk) begin + if nBLANK_clk'event and nBLANK_clk='1' then + nBLANK_q <= nBLANK_d; + end if; + end process; + + FIFO_RDE <= FIFO_RDE_q; + process (FIFO_RDE_clk) begin + if FIFO_RDE_clk'event and FIFO_RDE_clk='1' then + FIFO_RDE_q <= FIFO_RDE_d; + end if; + end process; + + BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); + process (BORDER_COLOR0_clk_ctrl) begin + if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then + if BORDER_COLOR16_ena_ctrl='1' then + (BORDER_COLOR_q(23), BORDER_COLOR_q(22), BORDER_COLOR_q(21), + BORDER_COLOR_q(20), BORDER_COLOR_q(19), BORDER_COLOR_q(18), + BORDER_COLOR_q(17), BORDER_COLOR_q(16)) <= BORDER_COLOR_d(23 + downto 16); + end if; + end if; + end process; + + BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); + process (BORDER_COLOR0_clk_ctrl) begin + if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then + if BORDER_COLOR8_ena_ctrl='1' then + (BORDER_COLOR_q(15), BORDER_COLOR_q(14), BORDER_COLOR_q(13), + BORDER_COLOR_q(12), BORDER_COLOR_q(11), BORDER_COLOR_q(10), + BORDER_COLOR_q(9), BORDER_COLOR_q(8)) <= BORDER_COLOR_d(15 + downto 8); + end if; + end if; + end process; + + BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); + process (BORDER_COLOR0_clk_ctrl) begin + if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then + if BORDER_COLOR0_ena_ctrl='1' then + (BORDER_COLOR_q(7), BORDER_COLOR_q(6), BORDER_COLOR_q(5), + BORDER_COLOR_q(4), BORDER_COLOR_q(3), BORDER_COLOR_q(2), + BORDER_COLOR_q(1), BORDER_COLOR_q(0)) <= BORDER_COLOR_d(7 + downto 0); + end if; + end if; + end process; + + CCSEL <= CCSEL_q; + process (CCSEL0_clk_ctrl) begin + if CCSEL0_clk_ctrl'event and CCSEL0_clk_ctrl='1' then + CCSEL_q <= CCSEL_d; + end if; + end process; + + INTER_ZEI <= INTER_ZEI_q; + process (INTER_ZEI_clk) begin + if INTER_ZEI_clk'event and INTER_ZEI_clk='1' then + INTER_ZEI_q <= INTER_ZEI_d; + end if; + end process; + + DOP_FIFO_CLR <= DOP_FIFO_CLR_q; + process (DOP_FIFO_CLR_clk) begin + if DOP_FIFO_CLR_clk'event and DOP_FIFO_CLR_clk='1' then + DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d; + end if; + end process; + + VIDEO_RECONFIG <= VIDEO_RECONFIG_q; + process (VIDEO_RECONFIG_clk) begin + if VIDEO_RECONFIG_clk'event and VIDEO_RECONFIG_clk='1' then + VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; + end if; + end process; + + VR_WR <= VR_WR_q; + process (VR_WR_clk) begin + if VR_WR_clk'event and VR_WR_clk='1' then + VR_WR_q <= VR_WR_d; + end if; + end process; + + CLR_FIFO <= CLR_FIFO_q; + process (CLR_FIFO_clk) begin + if CLR_FIFO_clk'event and CLR_FIFO_clk='1' then + if CLR_FIFO_ena='1' then + CLR_FIFO_q <= CLR_FIFO_d; + end if; + end if; + end process; + + process (CLK17M_clk) begin + if CLK17M_clk'event and CLK17M_clk='1' then + CLK17M_q <= CLK17M_d; + end if; + end process; + + process (CLK13M_clk) begin + if CLK13M_clk'event and CLK13M_clk='1' then + CLK13M_q <= CLK13M_d; + end if; + end process; + + process (VR_DOUT0_clk_ctrl) begin + if VR_DOUT0_clk_ctrl'event and VR_DOUT0_clk_ctrl='1' then + if VR_DOUT0_ena_ctrl='1' then + VR_DOUT_q <= VR_DOUT_d; + end if; + end if; + end process; + + process (VR_FRQ0_clk_ctrl) begin + if VR_FRQ0_clk_ctrl'event and VR_FRQ0_clk_ctrl='1' then + if VR_FRQ0_ena_ctrl='1' then + VR_FRQ_q <= VR_FRQ_d; + end if; + end if; + end process; + + process (ST_SHIFT_MODE0_clk_ctrl) begin + if ST_SHIFT_MODE0_clk_ctrl'event and ST_SHIFT_MODE0_clk_ctrl='1' then + if ST_SHIFT_MODE0_ena_ctrl='1' then + ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; + end if; + end if; + end process; + + process (FALCON_SHIFT_MODE0_clk_ctrl) begin + if FALCON_SHIFT_MODE0_clk_ctrl'event and FALCON_SHIFT_MODE0_clk_ctrl='1' + then + if FALCON_SHIFT_MODE8_ena_ctrl='1' then + (FALCON_SHIFT_MODE_q(10), FALCON_SHIFT_MODE_q(9), + FALCON_SHIFT_MODE_q(8)) <= FALCON_SHIFT_MODE_d(10 downto 8); + end if; + end if; + end process; + + process (FALCON_SHIFT_MODE0_clk_ctrl) begin + if FALCON_SHIFT_MODE0_clk_ctrl'event and FALCON_SHIFT_MODE0_clk_ctrl='1' + then + if FALCON_SHIFT_MODE0_ena_ctrl='1' then + (FALCON_SHIFT_MODE_q(7), FALCON_SHIFT_MODE_q(6), + FALCON_SHIFT_MODE_q(5), FALCON_SHIFT_MODE_q(4), + FALCON_SHIFT_MODE_q(3), FALCON_SHIFT_MODE_q(2), + FALCON_SHIFT_MODE_q(1), FALCON_SHIFT_MODE_q(0)) <= + FALCON_SHIFT_MODE_d(7 downto 0); + end if; + end if; + end process; + + process (CLUT_MUX_AV1_0_clk_ctrl) begin + if CLUT_MUX_AV1_0_clk_ctrl'event and CLUT_MUX_AV1_0_clk_ctrl='1' then + CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; + end if; + end process; + + process (CLUT_MUX_AV0_0_clk_ctrl) begin + if CLUT_MUX_AV0_0_clk_ctrl'event and CLUT_MUX_AV0_0_clk_ctrl='1' then + CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; + end if; + end process; + + process (ACP_VCTR0_clk_ctrl) begin + if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then + if ACP_VCTR24_ena_ctrl='1' then + (ACP_VCTR_q(31), ACP_VCTR_q(30), ACP_VCTR_q(29), ACP_VCTR_q(28), + ACP_VCTR_q(27), ACP_VCTR_q(26), ACP_VCTR_q(25), + ACP_VCTR_q(24)) <= ACP_VCTR_d(31 downto 24); + end if; + end if; + end process; + + process (ACP_VCTR0_clk_ctrl) begin + if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then + if ACP_VCTR16_ena_ctrl='1' then + (ACP_VCTR_q(23), ACP_VCTR_q(22), ACP_VCTR_q(21), ACP_VCTR_q(20), + ACP_VCTR_q(19), ACP_VCTR_q(18), ACP_VCTR_q(17), + ACP_VCTR_q(16)) <= ACP_VCTR_d(23 downto 16); + end if; + end if; + end process; + + process (ACP_VCTR0_clk_ctrl) begin + if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then + if ACP_VCTR8_ena_ctrl='1' then + (ACP_VCTR_q(15), ACP_VCTR_q(14), ACP_VCTR_q(13), ACP_VCTR_q(12), + ACP_VCTR_q(11), ACP_VCTR_q(10), ACP_VCTR_q(9), ACP_VCTR_q(8)) + <= ACP_VCTR_d(15 downto 8); + end if; + end if; + end process; + + process (ACP_VCTR0_clk_ctrl) begin + if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then + if ACP_VCTR6_ena_ctrl='1' then + (ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 downto 6); + end if; + end if; + end process; + + process (ACP_VCTR0_clk_ctrl) begin + if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then + if ACP_VCTR0_ena_ctrl='1' then + (ACP_VCTR_q(5), ACP_VCTR_q(4), ACP_VCTR_q(3), ACP_VCTR_q(2), + ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 downto 0); + end if; + end if; + end process; + + process (SYS_CTR0_clk_ctrl) begin + if SYS_CTR0_clk_ctrl'event and SYS_CTR0_clk_ctrl='1' then + if SYS_CTR0_ena_ctrl='1' then + SYS_CTR_q <= SYS_CTR_d; + end if; + end if; + end process; + + process (LOF0_clk_ctrl) begin + if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then + if LOF8_ena_ctrl='1' then + (LOF_q(15), LOF_q(14), LOF_q(13), LOF_q(12), LOF_q(11), LOF_q(10), + LOF_q(9), LOF_q(8)) <= LOF_d(15 downto 8); + end if; + end if; + end process; + + process (LOF0_clk_ctrl) begin + if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then + if LOF0_ena_ctrl='1' then + (LOF_q(7), LOF_q(6), LOF_q(5), LOF_q(4), LOF_q(3), LOF_q(2), + LOF_q(1), LOF_q(0)) <= LOF_d(7 downto 0); + end if; + end if; + end process; + + process (LWD0_clk_ctrl) begin + if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then + if LWD8_ena_ctrl='1' then + (LWD_q(15), LWD_q(14), LWD_q(13), LWD_q(12), LWD_q(11), LWD_q(10), + LWD_q(9), LWD_q(8)) <= LWD_d(15 downto 8); + end if; + end if; + end process; + + process (LWD0_clk_ctrl) begin + if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then + if LWD0_ena_ctrl='1' then + (LWD_q(7), LWD_q(6), LWD_q(5), LWD_q(4), LWD_q(3), LWD_q(2), + LWD_q(1), LWD_q(0)) <= LWD_d(7 downto 0); + end if; + end if; + end process; + + process (CLUT_TA_clk) begin + if CLUT_TA_clk'event and CLUT_TA_clk='1' then + CLUT_TA_q <= CLUT_TA_d; + end if; + end process; + + process (HSYNC_I0_clk_ctrl) begin + if HSYNC_I0_clk_ctrl'event and HSYNC_I0_clk_ctrl='1' then + HSYNC_I_q <= HSYNC_I_d; + end if; + end process; + + process (HSY_LEN0_clk_ctrl) begin + if HSY_LEN0_clk_ctrl'event and HSY_LEN0_clk_ctrl='1' then + HSY_LEN_q <= HSY_LEN_d; + end if; + end process; + + process (HSYNC_START_clk) begin + if HSYNC_START_clk'event and HSYNC_START_clk='1' then + HSYNC_START_q <= HSYNC_START_d; + end if; + end process; + + process (LAST_clk) begin + if LAST_clk'event and LAST_clk='1' then + LAST_q <= LAST_d; + end if; + end process; + + process (VSYNC_START_clk) begin + if VSYNC_START_clk'event and VSYNC_START_clk='1' then + if VSYNC_START_ena='1' then + VSYNC_START_q <= VSYNC_START_d; + end if; + end if; + end process; + + process (VSYNC_I0_clk_ctrl) begin + if VSYNC_I0_clk_ctrl'event and VSYNC_I0_clk_ctrl='1' then + if VSYNC_I0_ena_ctrl='1' then + VSYNC_I_q <= VSYNC_I_d; + end if; + end if; + end process; + + process (DISP_ON_clk) begin + if DISP_ON_clk'event and DISP_ON_clk='1' then + DISP_ON_q <= DISP_ON_d; + end if; + end process; + + process (DPO_ZL_clk) begin + if DPO_ZL_clk'event and DPO_ZL_clk='1' then + if DPO_ZL_ena='1' then + DPO_ZL_q <= DPO_ZL_d; + end if; + end if; + end process; + + process (DPO_ON_clk) begin + if DPO_ON_clk'event and DPO_ON_clk='1' then + DPO_ON_q <= DPO_ON_d; + end if; + end process; + + process (DPO_OFF_clk) begin + if DPO_OFF_clk'event and DPO_OFF_clk='1' then + DPO_OFF_q <= DPO_OFF_d; + end if; + end process; + + process (VDTRON_clk) begin + if VDTRON_clk'event and VDTRON_clk='1' then + VDTRON_q <= VDTRON_d; + end if; + end process; + + process (VCO_ZL_clk) begin + if VCO_ZL_clk'event and VCO_ZL_clk='1' then + if VCO_ZL_ena='1' then + VCO_ZL_q <= VCO_ZL_d; + end if; + end if; + end process; + + process (VCO_ON_clk) begin + if VCO_ON_clk'event and VCO_ON_clk='1' then + VCO_ON_q <= VCO_ON_d; + end if; + end process; + + process (VCO_OFF_clk) begin + if VCO_OFF_clk'event and VCO_OFF_clk='1' then + VCO_OFF_q <= VCO_OFF_d; + end if; + end process; + + process (VHCNT0_clk_ctrl) begin + if VHCNT0_clk_ctrl'event and VHCNT0_clk_ctrl='1' then + VHCNT_q <= VHCNT_d; + end if; + end process; + + process (SUB_PIXEL_CNT0_clk_ctrl) begin + if SUB_PIXEL_CNT0_clk_ctrl'event and SUB_PIXEL_CNT0_clk_ctrl='1' then + if SUB_PIXEL_CNT0_ena_ctrl='1' then + SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d; + end if; + end if; + end process; + + process (VVCNT0_clk_ctrl) begin + if VVCNT0_clk_ctrl'event and VVCNT0_clk_ctrl='1' then + if VVCNT0_ena_ctrl='1' then + VVCNT_q <= VVCNT_d; + end if; + end if; + end process; + + process (VERZ2_0_clk_ctrl) begin + if VERZ2_0_clk_ctrl'event and VERZ2_0_clk_ctrl='1' then + VERZ2_q <= VERZ2_d; + end if; + end process; + + process (VERZ1_0_clk_ctrl) begin + if VERZ1_0_clk_ctrl'event and VERZ1_0_clk_ctrl='1' then + VERZ1_q <= VERZ1_d; + end if; + end process; + + process (VERZ0_0_clk_ctrl) begin + if VERZ0_0_clk_ctrl'event and VERZ0_0_clk_ctrl='1' then + VERZ0_q <= VERZ0_d; + end if; + end process; + + process (RAND0_clk_ctrl) begin + if RAND0_clk_ctrl'event and RAND0_clk_ctrl='1' then + RAND_q <= RAND_d; + end if; + end process; + + process (START_ZEILE_clk) begin + if START_ZEILE_clk'event and START_ZEILE_clk='1' then + if START_ZEILE_ena='1' then + START_ZEILE_q <= START_ZEILE_d; + end if; + end if; + end process; + + process (SYNC_PIX_clk) begin + if SYNC_PIX_clk'event and SYNC_PIX_clk='1' then + SYNC_PIX_q <= SYNC_PIX_d; + end if; + end process; + + process (SYNC_PIX1_clk) begin + if SYNC_PIX1_clk'event and SYNC_PIX1_clk='1' then + SYNC_PIX1_q <= SYNC_PIX1_d; + end if; + end process; + + process (SYNC_PIX2_clk) begin + if SYNC_PIX2_clk'event and SYNC_PIX2_clk='1' then + SYNC_PIX2_q <= SYNC_PIX2_d; + end if; + end process; + + process (ATARI_HH0_clk_ctrl) begin + if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then + if ATARI_HH24_ena_ctrl='1' then + (ATARI_HH_q(31), ATARI_HH_q(30), ATARI_HH_q(29), ATARI_HH_q(28), + ATARI_HH_q(27), ATARI_HH_q(26), ATARI_HH_q(25), + ATARI_HH_q(24)) <= ATARI_HH_d(31 downto 24); + end if; + end if; + end process; + + process (ATARI_HH0_clk_ctrl) begin + if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then + if ATARI_HH16_ena_ctrl='1' then + (ATARI_HH_q(23), ATARI_HH_q(22), ATARI_HH_q(21), ATARI_HH_q(20), + ATARI_HH_q(19), ATARI_HH_q(18), ATARI_HH_q(17), + ATARI_HH_q(16)) <= ATARI_HH_d(23 downto 16); + end if; + end if; + end process; + + process (ATARI_HH0_clk_ctrl) begin + if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then + if ATARI_HH8_ena_ctrl='1' then + (ATARI_HH_q(15), ATARI_HH_q(14), ATARI_HH_q(13), ATARI_HH_q(12), + ATARI_HH_q(11), ATARI_HH_q(10), ATARI_HH_q(9), ATARI_HH_q(8)) + <= ATARI_HH_d(15 downto 8); + end if; + end if; + end process; + + process (ATARI_HH0_clk_ctrl) begin + if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then + if ATARI_HH0_ena_ctrl='1' then + (ATARI_HH_q(7), ATARI_HH_q(6), ATARI_HH_q(5), ATARI_HH_q(4), + ATARI_HH_q(3), ATARI_HH_q(2), ATARI_HH_q(1), ATARI_HH_q(0)) + <= ATARI_HH_d(7 downto 0); + end if; + end if; + end process; + + process (ATARI_VH0_clk_ctrl) begin + if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then + if ATARI_VH24_ena_ctrl='1' then + (ATARI_VH_q(31), ATARI_VH_q(30), ATARI_VH_q(29), ATARI_VH_q(28), + ATARI_VH_q(27), ATARI_VH_q(26), ATARI_VH_q(25), + ATARI_VH_q(24)) <= ATARI_VH_d(31 downto 24); + end if; + end if; + end process; + + process (ATARI_VH0_clk_ctrl) begin + if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then + if ATARI_VH16_ena_ctrl='1' then + (ATARI_VH_q(23), ATARI_VH_q(22), ATARI_VH_q(21), ATARI_VH_q(20), + ATARI_VH_q(19), ATARI_VH_q(18), ATARI_VH_q(17), + ATARI_VH_q(16)) <= ATARI_VH_d(23 downto 16); + end if; + end if; + end process; + + process (ATARI_VH0_clk_ctrl) begin + if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then + if ATARI_VH8_ena_ctrl='1' then + (ATARI_VH_q(15), ATARI_VH_q(14), ATARI_VH_q(13), ATARI_VH_q(12), + ATARI_VH_q(11), ATARI_VH_q(10), ATARI_VH_q(9), ATARI_VH_q(8)) + <= ATARI_VH_d(15 downto 8); + end if; + end if; + end process; + + process (ATARI_VH0_clk_ctrl) begin + if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then + if ATARI_VH0_ena_ctrl='1' then + (ATARI_VH_q(7), ATARI_VH_q(6), ATARI_VH_q(5), ATARI_VH_q(4), + ATARI_VH_q(3), ATARI_VH_q(2), ATARI_VH_q(1), ATARI_VH_q(0)) + <= ATARI_VH_d(7 downto 0); + end if; + end if; + end process; + + process (ATARI_HL0_clk_ctrl) begin + if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then + if ATARI_HL24_ena_ctrl='1' then + (ATARI_HL_q(31), ATARI_HL_q(30), ATARI_HL_q(29), ATARI_HL_q(28), + ATARI_HL_q(27), ATARI_HL_q(26), ATARI_HL_q(25), + ATARI_HL_q(24)) <= ATARI_HL_d(31 downto 24); + end if; + end if; + end process; + + process (ATARI_HL0_clk_ctrl) begin + if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then + if ATARI_HL16_ena_ctrl='1' then + (ATARI_HL_q(23), ATARI_HL_q(22), ATARI_HL_q(21), ATARI_HL_q(20), + ATARI_HL_q(19), ATARI_HL_q(18), ATARI_HL_q(17), + ATARI_HL_q(16)) <= ATARI_HL_d(23 downto 16); + end if; + end if; + end process; + + process (ATARI_HL0_clk_ctrl) begin + if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then + if ATARI_HL8_ena_ctrl='1' then + (ATARI_HL_q(15), ATARI_HL_q(14), ATARI_HL_q(13), ATARI_HL_q(12), + ATARI_HL_q(11), ATARI_HL_q(10), ATARI_HL_q(9), ATARI_HL_q(8)) + <= ATARI_HL_d(15 downto 8); + end if; + end if; + end process; + + process (ATARI_HL0_clk_ctrl) begin + if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then + if ATARI_HL0_ena_ctrl='1' then + (ATARI_HL_q(7), ATARI_HL_q(6), ATARI_HL_q(5), ATARI_HL_q(4), + ATARI_HL_q(3), ATARI_HL_q(2), ATARI_HL_q(1), ATARI_HL_q(0)) + <= ATARI_HL_d(7 downto 0); + end if; + end if; + end process; + + process (ATARI_VL0_clk_ctrl) begin + if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then + if ATARI_VL24_ena_ctrl='1' then + (ATARI_VL_q(31), ATARI_VL_q(30), ATARI_VL_q(29), ATARI_VL_q(28), + ATARI_VL_q(27), ATARI_VL_q(26), ATARI_VL_q(25), + ATARI_VL_q(24)) <= ATARI_VL_d(31 downto 24); + end if; + end if; + end process; + + process (ATARI_VL0_clk_ctrl) begin + if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then + if ATARI_VL16_ena_ctrl='1' then + (ATARI_VL_q(23), ATARI_VL_q(22), ATARI_VL_q(21), ATARI_VL_q(20), + ATARI_VL_q(19), ATARI_VL_q(18), ATARI_VL_q(17), + ATARI_VL_q(16)) <= ATARI_VL_d(23 downto 16); + end if; + end if; + end process; + + process (ATARI_VL0_clk_ctrl) begin + if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then + if ATARI_VL8_ena_ctrl='1' then + (ATARI_VL_q(15), ATARI_VL_q(14), ATARI_VL_q(13), ATARI_VL_q(12), + ATARI_VL_q(11), ATARI_VL_q(10), ATARI_VL_q(9), ATARI_VL_q(8)) + <= ATARI_VL_d(15 downto 8); + end if; + end if; + end process; + + process (ATARI_VL0_clk_ctrl) begin + if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then + if ATARI_VL0_ena_ctrl='1' then + (ATARI_VL_q(7), ATARI_VL_q(6), ATARI_VL_q(5), ATARI_VL_q(4), + ATARI_VL_q(3), ATARI_VL_q(2), ATARI_VL_q(1), ATARI_VL_q(0)) + <= ATARI_VL_d(7 downto 0); + end if; + end if; + end process; + + process (HHT0_clk_ctrl) begin + if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then + if HHT8_ena_ctrl='1' then + (HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 downto 8); + end if; + end if; + end process; + + process (HHT0_clk_ctrl) begin + if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then + if HHT0_ena_ctrl='1' then + (HHT_q(7), HHT_q(6), HHT_q(5), HHT_q(4), HHT_q(3), HHT_q(2), + HHT_q(1), HHT_q(0)) <= HHT_d(7 downto 0); + end if; + end if; + end process; + + process (HBE0_clk_ctrl) begin + if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then + if HBE8_ena_ctrl='1' then + (HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 downto 8); + end if; + end if; + end process; + + process (HBE0_clk_ctrl) begin + if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then + if HBE0_ena_ctrl='1' then + (HBE_q(7), HBE_q(6), HBE_q(5), HBE_q(4), HBE_q(3), HBE_q(2), + HBE_q(1), HBE_q(0)) <= HBE_d(7 downto 0); + end if; + end if; + end process; + + process (HDB0_clk_ctrl) begin + if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then + if HDB8_ena_ctrl='1' then + (HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 downto 8); + end if; + end if; + end process; + + process (HDB0_clk_ctrl) begin + if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then + if HDB0_ena_ctrl='1' then + (HDB_q(7), HDB_q(6), HDB_q(5), HDB_q(4), HDB_q(3), HDB_q(2), + HDB_q(1), HDB_q(0)) <= HDB_d(7 downto 0); + end if; + end if; + end process; + + process (HDE0_clk_ctrl) begin + if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then + if HDE8_ena_ctrl='1' then + (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 downto 8); + end if; + end if; + end process; + + process (HDE0_clk_ctrl) begin + if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then + if HDE0_ena_ctrl='1' then + (HDE_q(7), HDE_q(6), HDE_q(5), HDE_q(4), HDE_q(3), HDE_q(2), + HDE_q(1), HDE_q(0)) <= HDE_d(7 downto 0); + end if; + end if; + end process; + + process (HBB0_clk_ctrl) begin + if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then + if HBB8_ena_ctrl='1' then + (HBB_q(11), HBB_q(10), HBB_q(9), HBB_q(8)) <= HBB_d(11 downto 8); + end if; + end if; + end process; + + process (HBB0_clk_ctrl) begin + if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then + if HBB0_ena_ctrl='1' then + (HBB_q(7), HBB_q(6), HBB_q(5), HBB_q(4), HBB_q(3), HBB_q(2), + HBB_q(1), HBB_q(0)) <= HBB_d(7 downto 0); + end if; + end if; + end process; + + process (HSS0_clk_ctrl) begin + if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then + if HSS8_ena_ctrl='1' then + (HSS_q(11), HSS_q(10), HSS_q(9), HSS_q(8)) <= HSS_d(11 downto 8); + end if; + end if; + end process; + + process (HSS0_clk_ctrl) begin + if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then + if HSS0_ena_ctrl='1' then + (HSS_q(7), HSS_q(6), HSS_q(5), HSS_q(4), HSS_q(3), HSS_q(2), + HSS_q(1), HSS_q(0)) <= HSS_d(7 downto 0); + end if; + end if; + end process; + + process (DOP_ZEI_clk) begin + if DOP_ZEI_clk'event and DOP_ZEI_clk='1' then + DOP_ZEI_q <= DOP_ZEI_d; + end if; + end process; + + process (VBE0_clk_ctrl) begin + if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then + if VBE8_ena_ctrl='1' then + (VBE_q(10), VBE_q(9), VBE_q(8)) <= VBE_d(10 downto 8); + end if; + end if; + end process; + + process (VBE0_clk_ctrl) begin + if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then + if VBE0_ena_ctrl='1' then + (VBE_q(7), VBE_q(6), VBE_q(5), VBE_q(4), VBE_q(3), VBE_q(2), + VBE_q(1), VBE_q(0)) <= VBE_d(7 downto 0); + end if; + end if; + end process; + + process (VDB0_clk_ctrl) begin + if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then + if VDB8_ena_ctrl='1' then + (VDB_q(10), VDB_q(9), VDB_q(8)) <= VDB_d(10 downto 8); + end if; + end if; + end process; + + process (VDB0_clk_ctrl) begin + if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then + if VDB0_ena_ctrl='1' then + (VDB_q(7), VDB_q(6), VDB_q(5), VDB_q(4), VDB_q(3), VDB_q(2), + VDB_q(1), VDB_q(0)) <= VDB_d(7 downto 0); + end if; + end if; + end process; + + process (VDE0_clk_ctrl) begin + if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then + if VDE8_ena_ctrl='1' then + (VDE_q(10), VDE_q(9), VDE_q(8)) <= VDE_d(10 downto 8); + end if; + end if; + end process; + + process (VDE0_clk_ctrl) begin + if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then + if VDE0_ena_ctrl='1' then + (VDE_q(7), VDE_q(6), VDE_q(5), VDE_q(4), VDE_q(3), VDE_q(2), + VDE_q(1), VDE_q(0)) <= VDE_d(7 downto 0); + end if; + end if; + end process; + + process (VBB0_clk_ctrl) begin + if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then + if VBB8_ena_ctrl='1' then + (VBB_q(10), VBB_q(9), VBB_q(8)) <= VBB_d(10 downto 8); + end if; + end if; + end process; + + process (VBB0_clk_ctrl) begin + if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then + if VBB0_ena_ctrl='1' then + (VBB_q(7), VBB_q(6), VBB_q(5), VBB_q(4), VBB_q(3), VBB_q(2), + VBB_q(1), VBB_q(0)) <= VBB_d(7 downto 0); + end if; + end if; + end process; + + process (VSS0_clk_ctrl) begin + if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then + if VSS8_ena_ctrl='1' then + (VSS_q(10), VSS_q(9), VSS_q(8)) <= VSS_d(10 downto 8); + end if; + end if; + end process; + + process (VSS0_clk_ctrl) begin + if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then + if VSS0_ena_ctrl='1' then + (VSS_q(7), VSS_q(6), VSS_q(5), VSS_q(4), VSS_q(3), VSS_q(2), + VSS_q(1), VSS_q(0)) <= VSS_d(7 downto 0); + end if; + end if; + end process; + + process (VFT0_clk_ctrl) begin + if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then + if VFT8_ena_ctrl='1' then + (VFT_q(10), VFT_q(9), VFT_q(8)) <= VFT_d(10 downto 8); + end if; + end if; + end process; + + process (VFT0_clk_ctrl) begin + if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then + if VFT0_ena_ctrl='1' then + (VFT_q(7), VFT_q(6), VFT_q(5), VFT_q(4), VFT_q(3), VFT_q(2), + VFT_q(1), VFT_q(0)) <= VFT_d(7 downto 0); + end if; + end if; + end process; + + process (VCO0_clk_ctrl) begin + if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then + if VCO_ena(8)='1' then + VCO_q(8) <= VCO_d(8); + end if; + end if; + end process; + + process (VCO0_clk_ctrl) begin + if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then + if VCO0_ena_ctrl='1' then + (VCO_q(7), VCO_q(6), VCO_q(5), VCO_q(4), VCO_q(3), VCO_q(2), + VCO_q(1), VCO_q(0)) <= VCO_d(7 downto 0); + end if; + end if; + end process; + + process (VCNTRL0_clk_ctrl) begin + if VCNTRL0_clk_ctrl'event and VCNTRL0_clk_ctrl='1' then + if VCNTRL0_ena_ctrl='1' then + VCNTRL_q <= VCNTRL_d; + end if; + end if; + end process; + +-- Start of original equations + +-- BYT SELECT 32 BIT +-- ADR==0 + FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00"); + +-- ADR==1 +-- HIGH WORD +-- LONG UND LINE + FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not + FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not + FB_SIZE1) and (not FB_SIZE0)); + +-- ADR==2 +-- LONG UND LINE + FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and + FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + +-- ADR==3 +-- LOW WORD +-- LONG UND LINE + FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not + FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) + and (not FB_SIZE0)); + +-- BYT SELECT 16 BIT +-- ADR==0 + FB_16B(0) <= to_std_logic(FB_ADR(0) = '0'); + +-- ADR==1 +-- NOT BYT + FB_16B(1) <= to_std_logic(FB_ADR(0) = '1') or (not ((not FB_SIZE1) and + FB_SIZE0)); + +-- ACP CLUT -- +-- 0-3FF/1024 + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 10) = + "000000000000000000"); + ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); + ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); + CLUT_TA_clk <= MAIN_CLK; + CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not + VIDEO_MOD_TA); + +-- FALCON CLUT -- +-- $F9800/$400 + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 10) + = "1111100110"); + +-- HIGH WORD + FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); + +-- LOW WORD + FALCON_CLUT_RDL <= FALCON_CLUT_CS and (not nFB_OE) and FB_ADR(1); + FALCON_CLUT_WR(1 downto 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & + (not FB_ADR(1))) and std_logic_vector'(FALCON_CLUT_CS & + FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + FALCON_CLUT_WR(3 downto 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & + FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and + std_logic_vector'((not nFB_WR) & (not nFB_WR)); + +-- ST CLUT -- +-- $F8240/$20 + ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 5) = + "111110000010010"); + ST_CLUT_RD <= ST_CLUT_CS and (not nFB_OE); + ST_CLUT_WR <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and + std_logic_vector'((not nFB_WR) & (not nFB_WR)); + +-- ST SHIFT MODE + ST_SHIFT_MODE0_clk_ctrl <= MAIN_CLK; + +-- $F8260/2 + ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) + = "1111100000100110000"); + ST_SHIFT_MODE_d <= FB_AD(25 downto 24); + ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); + +-- MONO + COLOR1_1 <= to_std_logic(ST_SHIFT_MODE_q = "10") and (not COLOR8) and + ST_VIDEO and (not ACP_VIDEO_ON); + +-- 4 FARBEN + COLOR2 <= to_std_logic(ST_SHIFT_MODE_q = "01") and (not COLOR8) and ST_VIDEO + and (not ACP_VIDEO_ON); + +-- 16 FARBEN + COLOR4_1 <= to_std_logic(ST_SHIFT_MODE_q = "00") and (not COLOR8) and + ST_VIDEO and (not ACP_VIDEO_ON); + +-- FALCON SHIFT MODE + FALCON_SHIFT_MODE0_clk_ctrl <= MAIN_CLK; + +-- $F8266/2 + FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 + downto 1) = "1111100000100110011"); + FALCON_SHIFT_MODE_d <= FB_AD(26 downto 16); + FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and + FB_B(2); + FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and + FB_B(3); + CLUT_OFF <= FALCON_SHIFT_MODE_q(3 downto 0) and sizeIt(COLOR4,4); + COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and + FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and + (not ACP_VIDEO_ON); + COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO + and (not ACP_VIDEO_ON); + +-- ACP VIDEO CONTROL +-- BIT 0 = ACP VIDEO ON +-- BIT 1 = POWER ON VIDEO DAC +-- BIT 2 = ACP 24BIT +-- BIT 3 = ACP 16BIT +-- BIT 4 = ACP 8BIT +-- BIT 5 = ACP 1BIT +-- BIT 6 = FALCON SHIFT MODE +-- BIT 7 = ST SHIFT MODE +-- BIT 9..8 = VCLK FREQUENZ +-- BIT 15 =-SYNC ALLOWED +-- BIT 31..16 = VIDEO_RAM_CTR +-- BIT 25 = RANDFARBE EINSCHALTEN +-- BIT 26 = STANDARD ATARI SYNCS + ACP_VCTR0_clk_ctrl <= MAIN_CLK; + +-- $400/4 + ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + "00000000000000000100000000"); + ACP_VCTR_d(31 downto 8) <= FB_AD(31 downto 8); + ACP_VCTR_d(5 downto 0) <= FB_AD(5 downto 0); + ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); + ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); + ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); + ACP_VCTR0_ena_ctrl <= ACP_VCTR_CS and FB_B(3) and (not nFB_WR); + ACP_VIDEO_ON <= ACP_VCTR_q(0); + nPD_VGA <= ACP_VCTR_q(1); + +-- ATARI MODUS +-- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC <= ACP_VCTR_q(26); + +-- HORIZONTAL TIMING 640x480 + ATARI_HH0_clk_ctrl <= MAIN_CLK; + +-- $410/4 + ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + "00000000000000000100000100"); + ATARI_HH_d <= FB_AD; + ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); + ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); + ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); + ATARI_HH0_ena_ctrl <= ATARI_HH_CS and FB_B(3) and (not nFB_WR); + +-- VERTIKAL TIMING 640x480 + ATARI_VH0_clk_ctrl <= MAIN_CLK; + +-- $414/4 + ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + "00000000000000000100000101"); + ATARI_VH_d <= FB_AD; + ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); + ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); + ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); + ATARI_VH0_ena_ctrl <= ATARI_VH_CS and FB_B(3) and (not nFB_WR); + +-- HORIZONTAL TIMING 320x240 + ATARI_HL0_clk_ctrl <= MAIN_CLK; + +-- $418/4 + ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + "00000000000000000100000110"); + ATARI_HL_d <= FB_AD; + ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); + ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); + ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); + ATARI_HL0_ena_ctrl <= ATARI_HL_CS and FB_B(3) and (not nFB_WR); + +-- VERTIKAL TIMING 320x240 + ATARI_VL0_clk_ctrl <= MAIN_CLK; + +-- $41C/4 + ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + "00000000000000000100000111"); + ATARI_VL_d <= FB_AD; + ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); + ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); + ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); + ATARI_VL0_ena_ctrl <= ATARI_VL_CS and FB_B(3) and (not nFB_WR); + +-- VIDEO PLL CONFIG +-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto + 9) = "0000000000000000011") and FB_B(0) and FB_B(1); + VR_WR_clk <= MAIN_CLK; + VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not + VR_WR_q); + VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); + VR_DOUT0_clk_ctrl <= MAIN_CLK; + VR_DOUT0_ena_ctrl <= not VR_BUSY; + VR_DOUT_d <= VR_D; + VR_FRQ0_clk_ctrl <= MAIN_CLK; + VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = + "000000100"); + VR_FRQ_d <= FB_AD(23 downto 16); + +-- VIDEO PLL RECONFIG +-- $(F)000'0800 + VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 + downto 0) = "0000000000000000100000000000") and FB_B(0); + VIDEO_RECONFIG_clk <= MAIN_CLK; + VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) + and (not VIDEO_RECONFIG_q); + +-- ---------------------------------------------------------------------------------------------------------------------- + VIDEO_RAM_CTR <= ACP_VCTR_q(31 downto 16); + +-- ------------ COLOR MODE IM ACP SETZEN + COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) + and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; + COLOR8_2 <= ACP_VCTR_q(4) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) + and ACP_VIDEO_ON; + COLOR16_2 <= ACP_VCTR_q(3) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; + COLOR24 <= ACP_VCTR_q(2) and ACP_VIDEO_ON; + ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); + +-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not + ACP_VIDEO_ON); + ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or + (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and + (not nFB_WR) and FB_AD(0)); + FALCON_VIDEO <= ACP_VCTR_q(7); + FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); + ST_VIDEO <= ACP_VCTR_q(6); + ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not + COLOR1); + CCSEL0_clk_ctrl <= PIXEL_CLK; + +-- ONLY FOR INFORMATION + CCSEL_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and + sizeIt(FALCON_CLUT,3)) or ("100" and sizeIt(ACP_CLUT,3)) or ("101" and + sizeIt(COLOR16,3)) or ("110" and sizeIt(COLOR24,3)) or ("111" and + sizeIt(RAND_ON,3)); + +-- DIVERSE (VIDEO)-REGISTER ---------------------------- +-- RANDFARBE + BORDER_COLOR0_clk_ctrl <= MAIN_CLK; + +-- $404/4 + BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) + = "00000000000000000100000001"); + BORDER_COLOR_d <= FB_AD(23 downto 0); + BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); + BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); + BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); + +-- System Config Register +-- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi +-- |||||||| +-- |||||||+- RAM Wait Status +-- ||||||| 0 = 1 Wait (default) +-- ||||||| 1 = 0 Wait +-- ||||||+-- Video Bus Width +-- |||||| 0 = 16 Bit +-- |||||| 1 = 32 Bit (default) +-- ||||++--- ROM Wait Status +-- |||| 00 = reserved +-- |||| 01 = 2 Wait (default) +-- |||| 10 = 1 Wait +-- |||| 11 = 0 Wait +-- ||++----- Main Memory Size +-- || 01 = 4 MB +-- || 10 = 16 MB +-- ++------- Monitor Type +-- 00 Monochrome +-- 01 RGB +-- 10 VGA +-- 11 TV +-- $8006/2 + SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000000000011"); + SYS_CTR0_clk_ctrl <= MAIN_CLK; + SYS_CTR_d <= FB_AD(22 downto 16); + SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); + BLITTER_ON <= not SYS_CTR_q(3); + +-- LOF +-- $820E/2 + LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100000111"); + LOF0_clk_ctrl <= MAIN_CLK; + LOF_d <= FB_AD(31 downto 16); + LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); + LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); + +-- LWD +-- $8210/2 + LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000100001000"); + LWD0_clk_ctrl <= MAIN_CLK; + LWD_d <= FB_AD(31 downto 16); + LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); + LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); + +-- HORIZONTAL +-- HHT +-- $8282/2 + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101000001"); + HHT0_clk_ctrl <= MAIN_CLK; + HHT_d <= FB_AD(27 downto 16); + HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); + HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); + +-- HBE +-- $8286/2 + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101000011"); + HBE0_clk_ctrl <= MAIN_CLK; + HBE_d <= FB_AD(27 downto 16); + HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); + HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); + +-- HDB +-- $8288/2 + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101000100"); + HDB0_clk_ctrl <= MAIN_CLK; + HDB_d <= FB_AD(27 downto 16); + HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); + HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); + +-- HDE +-- $828A/2 + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101000101"); + HDE0_clk_ctrl <= MAIN_CLK; + HDE_d <= FB_AD(27 downto 16); + HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); + HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); + +-- HBB +-- $8284/2 + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101000010"); + HBB0_clk_ctrl <= MAIN_CLK; + HBB_d <= FB_AD(27 downto 16); + HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); + HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); + +-- HSS +-- Videl HSYNC start register $828C / 2 + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101000110"); + HSS0_clk_ctrl <= MAIN_CLK; + HSS_d <= FB_AD(27 downto 16); + HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); + HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); + +-- VERTIKAL +-- VBE +-- $82A6/2 + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101010011"); + VBE0_clk_ctrl <= MAIN_CLK; + VBE_d <= FB_AD(26 downto 16); + VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); + VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); + +-- VDB +-- $82A8/2 + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101010100"); + VDB0_clk_ctrl <= MAIN_CLK; + VDB_d <= FB_AD(26 downto 16); + VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); + VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); + +-- VDE +-- $82AA/2 + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101010101"); + VDE0_clk_ctrl <= MAIN_CLK; + VDE_d <= FB_AD(26 downto 16); + VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); + VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); + +-- VBB +-- $82A4/2 + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101010010"); + VBB0_clk_ctrl <= MAIN_CLK; + VBB_d <= FB_AD(26 downto 16); + VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); + VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); + +-- VSS +-- $82AC/2 + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101010110"); + VSS0_clk_ctrl <= MAIN_CLK; + VSS_d <= FB_AD(26 downto 16); + VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); + VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); + +-- VFT +-- $82A2/2 + VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101010001"); + VFT0_clk_ctrl <= MAIN_CLK; + VFT_d <= FB_AD(26 downto 16); + VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); + VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); + +-- VCO +-- $82C0 / 2 Falcon clock control register VCO + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101100000"); + VCO0_clk_ctrl <= MAIN_CLK; + VCO_d <= FB_AD(24 downto 16); + VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); + VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); + +-- VCNTRL +-- $82C2 / 2 Falcon resolution control register VCNTRL + VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + "1111100000101100001"); + VCNTRL0_clk_ctrl <= MAIN_CLK; + VCNTRL_d <= FB_AD(19 downto 16); + VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); + +-- - REGISTER OUT +-- low word register access + u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & + ST_SHIFT_MODE_q & "00000000")) or (sizeIt(FALCON_SHIFT_MODE_CS,16) and + std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or + (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 + downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or + (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or + (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or + (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or + (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or + (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or + (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or + (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or + (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or + (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or + (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or + (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or + (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or + (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or + (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or + (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & + VCNTRL_q)) or (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or + (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & + BORDER_COLOR_q(23 downto 16))) or (sizeIt(VIDEO_PLL_CONFIG_CS,16) and + std_logic_vector'("0000000" & VR_DOUT_q)) or + (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & + "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); + u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or + BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS + or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS + or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or + VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or + VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); + FB_AD(31 downto 16) <= u0_tridata; + +-- high word register access + u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or + (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); + u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS + or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); + FB_AD(15 downto 0) <= u1_tridata; + VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or + ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or + HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or + ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or + VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; + +-- VIDEO AUSGABE SETZEN + CLK17M_clk <= CLK33M; + CLK17M_d <= not CLK17M_q; + CLK13M_clk <= CLK25M; + CLK13M_d <= not CLK13M_q; + +-- 320 pixels, 32 MHz, +-- 320 pixels, 25.175 MHz, +-- 640 pixels, 32 MHz, VGA monitor +-- 640 pixels, 25.175 MHz, VGA monitor + PIXEL_CLK <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) + and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or (CLK17M_q and (not + ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and + (not VCO_q(2))) or VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and + (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not + VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or + ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) + or (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto + 8) = "00")) or (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and + ACP_VCTR_q(9 downto 8) = "01")) or (CLK_VIDEO and ACP_VIDEO_ON and + ACP_VCTR_q(9)); + +-- ------------------------------------------------------------ +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +-- -------------------------------------------------------------- +-- HSY_LEN[].CLK = MAIN_CLK; +-- check if this is better (mfro) + HSY_LEN0_clk_ctrl <= PIXEL_CLK; + +-- 320 pixels, 32 MHz, RGB +-- 320 pixels, 25.175 MHz, VGA +-- 640 pixels, 32 MHz, RGB +-- 640 pixels, 25.175 MHz, VGA +-- hsync pulse length in pixeln = frequenz / = 500ns + HSY_LEN_d <= ("00001110" and sizeIt(not ACP_VIDEO_ON,8) and + (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and + ((sizeIt(VCNTRL_q(2),8) and sizeIt(VCO_q(2),8)) or + sizeIt(VCO_q(0),8))) or ("00010000" and sizeIt(not ACP_VIDEO_ON,8) and + (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and + ((sizeIt(VCNTRL_q(2),8) and sizeIt(not VCO_q(2),8)) or + sizeIt(VCO_q(0),8))) or ("00011100" and sizeIt(not ACP_VIDEO_ON,8) and + (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and sizeIt(not + VCNTRL_q(2),8) and sizeIt(VCO_q(2),8) and sizeIt(not VCO_q(0),8)) or + ("00100000" and sizeIt(not ACP_VIDEO_ON,8) and (sizeIt(FALCON_VIDEO,8) + or sizeIt(ST_VIDEO,8)) and sizeIt(not VCNTRL_q(2),8) and sizeIt(not + VCO_q(2),8) and sizeIt(not VCO_q(0),8)) or ("00011100" and + sizeIt(ACP_VIDEO_ON,8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) + = "00"),8)) or ("00100000" and sizeIt(ACP_VIDEO_ON,8) and + sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "01"),8)) or + ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON,8) and sizeIt(ACP_VCTR_q(9),8)); + +-- MULTIPLIKATIONS FAKTOR + MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or + ("000100" and sizeIt(not ST_VIDEO,6) and sizeIt(not VCNTRL_q(2),6)) or + ("010000" and sizeIt(ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or + ("100000" and sizeIt(ST_VIDEO,6) and sizeIt(not VCNTRL_q(2),6)); + +-- BREITE IN PIXELN + HDIS_LEN <= ("000101000000" and sizeIt(VCNTRL_q(2),12)) or ("001010000000" + and sizeIt(not VCNTRL_q(2),12)); + +-- DOPPELZEILENMODUS + DOP_ZEI_clk <= MAIN_CLK; + +-- ZEILENVERDOPPELUNG EIN AUS + DOP_ZEI_d <= VCNTRL_q(0) and (FALCON_VIDEO or ST_VIDEO); + INTER_ZEI_clk <= PIXEL_CLK; + +-- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC +-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + INTER_ZEI_d <= (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) /= VDIS_START(0) + and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) < unsigned(std_logic_vector(unsigned(HDIS_END) - 1))))) or (to_std_logic(DOP_ZEI_q='1' and + VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and + (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); + DOP_FIFO_CLR_clk <= PIXEL_CLK; + +-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; + +-- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON +-- # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 +-- # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 +-- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + rand_links <= HBE_q WHEN acp_video_on ELSE + 12d"12" WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE + 12d"42" WHEN not acp_video_on and atari_sync and not(vcntrl(2)) ELSE + std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; + + /* rand_links <= (HBE_q and sizeit(acp_video_on, 12)) or + (std_logic_vector(to_unsigned(21, 12)) and sizeit(not acp_video_on and atari_sync and vcntrl(2), 12)) or + (std_logic_vector(to_unsigned(42, 12)) and sizeit(not acp_video_on and atari_sync and not vcntrl(2), 12)) or + (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 DOWNTO 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ + +-- HDIS_START[] = HDB[] & ACP_VIDEO_ON +-- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- + HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); + HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON,12)) or + ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); + RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or + ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); + + hs_start <= hss WHEN acp_video_on ELSE + atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE + atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE + std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; + +-- HS_START[] = HSS[] & ACP_VIDEO_ON +-- # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 +-- # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 +-- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- +-- + h_total <= hht WHEN acp_video_on ELSE + atari_hl(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE + atari_hh(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and not vcntrl(2) ELSE + std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) WHEN not acp_video_on and not atari_sync; + +-- H_TOTAL[] = HHT[] & ACP_VIDEO_ON +-- # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 +-- # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 +-- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and + sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or + (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not + ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or + ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + + VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and + sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and + sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) + and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or + (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not + ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or + ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + + VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 downto 0) + and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and + sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 downto 0) and sizeIt(not + ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not + VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and + sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 downto 16) + and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and + sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 downto 16) and sizeIt(not + ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not + VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and + sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + +-- ZÄHLER + LAST_clk <= PIXEL_CLK; + LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); + VHCNT0_clk_ctrl <= PIXEL_CLK; + VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); + VVCNT0_clk_ctrl <= PIXEL_CLK; + VVCNT0_ena_ctrl <= LAST_q; + VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); + +-- DISPLAY ON OFF + DPO_ZL_clk <= PIXEL_CLK; + +-- 1 ZEILE DAVOR ON OFF + DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); + +-- AM ZEILENENDE ÜBERNEHMEN + DPO_ZL_ena <= LAST_q; + DPO_ON_clk <= PIXEL_CLK; + +-- BESSER EINZELN WEGEN TIMING + DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); + DPO_OFF_clk <= PIXEL_CLK; + DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); + DISP_ON_clk <= PIXEL_CLK; + DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); + +-- DATENTRANSFER ON OFF + VCO_ON_clk <= PIXEL_CLK; + +-- BESSER EINZELN WEGEN TIMING + VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); + VCO_OFF_clk <= PIXEL_CLK; + VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); + VCO_ZL_clk <= PIXEL_CLK; + +-- AM ZEILENENDE ÜBERNEHMEN + VCO_ZL_ena <= LAST_q; + +-- 1 ZEILE DAVOR ON OFF + VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); + VDTRON_clk <= PIXEL_CLK; + VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); + +-- VERZÖGERUNG UND SYNC + HSYNC_START_clk <= PIXEL_CLK; + HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); + HSYNC_I0_clk_ctrl <= PIXEL_CLK; + HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or + ((std_logic_vector(unsigned(HSYNC_I_q) - 1)) and + sizeIt(not HSYNC_START_q,8) and sizeIt(to_std_logic(HSYNC_I_q /= + "00000000"),8)); + VSYNC_START_clk <= PIXEL_CLK; + VSYNC_START_ena <= LAST_q; + +-- start am ende der Zeile vor dem vsync + VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); + VSYNC_I0_clk_ctrl <= PIXEL_CLK; + +-- start am ende der Zeile vor dem vsync + VSYNC_I0_ena_ctrl <= LAST_q; + +-- 3 zeilen vsync length +-- runterzählen bis 0 + VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or + ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); + VERZ2_0_clk_ctrl <= PIXEL_CLK; + VERZ1_0_clk_ctrl <= PIXEL_CLK; + VERZ0_0_clk_ctrl <= PIXEL_CLK; + + (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & + VERZ1_q(0) & VERZ0_q(0)); + (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & + VERZ1_q(1) & VERZ0_q(1)); + (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & + VERZ1_q(2) & VERZ0_q(2)); + (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & + VERZ1_q(3) & VERZ0_q(3)); + (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & + VERZ1_q(4) & VERZ0_q(4)); + (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & + VERZ1_q(5) & VERZ0_q(5)); + (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & + VERZ1_q(6) & VERZ0_q(6)); + (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & + VERZ1_q(7) & VERZ0_q(7)); + (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & + VERZ1_q(8) & VERZ0_q(8)); + VERZ0_d(0) <= DISP_ON_q; + +-- VERZ[1][0] = HSYNC_I[] != 0; +-- NUR MÖGLICH WENN BEIDE + VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') + and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and + VCO_q(6))='1' and HSYNC_I_q = "00000000")); + +-- NUR MÖGLICH WENN BEIDE + VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') + and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and + VCO_q(5))='1' and VSYNC_I_q = "000")); + nBLANK_clk <= PIXEL_CLK; + +-- nBLANK = VERZ[0][8]; + nBLANK_d <= DISP_ON_q; + HSYNC_clk <= PIXEL_CLK; + +-- HSYNC = VERZ[1][9]; +-- NUR MÖGLICH WENN BEIDE + HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and + HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and + VCO_q(6))='1' and HSYNC_I_q = "00000000")); + VSYNC_clk <= PIXEL_CLK; + +-- VSYNC = VERZ[2][9]; +-- NUR MÖGLICH WENN BEIDE + VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and + VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and + VCO_q(5))='1' and VSYNC_I_q = "000")); + nSYNC <= gnd; + +-- RANDFARBE MACHEN ------------------------------------ + RAND0_clk_ctrl <= PIXEL_CLK; + RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + RAND_d(1) <= RAND_q(0); + RAND_d(2) <= RAND_q(1); + RAND_d(3) <= RAND_q(2); + RAND_d(4) <= RAND_q(3); + RAND_d(5) <= RAND_q(4); + RAND_d(6) <= RAND_q(5); + +-- RAND_ON = RAND[6]; + RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + +-- -------------------------------------------------------- + CLR_FIFO_clk <= PIXEL_CLK; + CLR_FIFO_ena <= LAST_q; + +-- IN LETZTER ZEILE LÖSCHEN + CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); + START_ZEILE_clk <= PIXEL_CLK; + START_ZEILE_ena <= LAST_q; + +-- ZEILE 1 + START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); + SYNC_PIX_clk <= PIXEL_CLK; + +-- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; + SYNC_PIX1_clk <= PIXEL_CLK; + +-- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; + SYNC_PIX2_clk <= PIXEL_CLK; + +-- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; + SUB_PIXEL_CNT0_clk_ctrl <= PIXEL_CLK; + SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; + +-- count up if display on sonst clear bei sync pix + SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); + FIFO_RDE_clk <= PIXEL_CLK; + +-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or + (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or + (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and COLOR4) or + (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and COLOR8) or + (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and COLOR16) or + (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and + VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; + CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 downto 0); + CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; + CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; + + +-- Assignments added to explicitly combine the +-- effects of multiple drivers in the source + COLOR16 <= COLOR16_1 or COLOR16_2; + COLOR4 <= COLOR4_1 or COLOR4_2; + COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; + COLOR8 <= COLOR8_1 or COLOR8_2; + +-- Define power signal(s) + gnd <= '0'; +end VIDEO_MOD_MUX_CLUTCTR_behav; diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index fa4da84..b587e1e 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,390 +39,390 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -432,7 +432,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -442,21 +442,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -466,76 +466,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -557,300 +557,301 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From 90c0f7758d88646ff2e8bc576bc23d5b0cb6f0f3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 12:54:00 +0000 Subject: [PATCH 057/127] remove AHDL files --- FPGA_Quartus_13.1/Video/DDR_CTR.tdf | 676 --------------- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 794 ------------------ 2 files changed, 1470 deletions(-) delete mode 100644 FPGA_Quartus_13.1/Video/DDR_CTR.tdf delete mode 100644 FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf deleted file mode 100644 index bc65c0b..0000000 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf +++ /dev/null @@ -1,676 +0,0 @@ -TITLE "ddr_ctr"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_BYT.inc"; - --- FIFO WATER MARK -CONSTANT FIFO_LWM = 0; -CONSTANT FIFO_MWM = 200; -CONSTANT FIFO_HWM = 500; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN ddr_ctr -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - CLR_FIFO : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - BLITTER_ADR[31..0] : INPUT; - BLITTER_SIG : INPUT; - BLITTER_WR : INPUT; - CLK33M : INPUT; - FIFO_MW[8..0] : INPUT; - - DDRCLK0 : INPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - BA[1..0] : OUTPUT; - VDM_SEL[3..0] : OUTPUT; - - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - SR_FIFO_WRE : OUTPUT; - SR_DDR_FB : OUTPUT; - SR_DDR_WR : OUTPUT; - SR_DDRWR_D_SEL : OUTPUT; - SR_VDMP[7..0] : OUTPUT; - VIDEO_DDR_TA : OUTPUT; - SR_BLITTER_DACK : OUTPUT; - DDRWR_D_SEL1 : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1, DS_T2A, DS_T2B, DS_T3, DS_N5, DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) - DS_C2, DS_C3, DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG - DS_T4R,DS_T5R, -- READ CPU UND BLITTER, - DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER - DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO - DS_CB6, DS_CB8, -- CLOSE FIFO BANK - DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS - LINE :NODE; - FB_B[3..0] :NODE; - VCAS :NODE; - VRAS :NODE; - VWE :NODE; - VA_P[12..0] :DFF; - BA_P[1..0] :DFF; - VA_S[12..0] :DFF; - BA_S[1..0] :DFF; - MCS[1..0] :DFF; - CPU_DDR_SYNC :DFF; - DDR_SEL :NODE; - DDR_CS :DFFE; - DDR_CONFIG :NODE; - SR_DDR_WR :DFF; - SR_DDRWR_D_SEL :DFF; - SR_VDMP[7..0] :DFF; - CPU_ROW_ADR[12..0] :NODE; - CPU_BA[1..0] :NODE; - CPU_COL_ADR[9..0] :NODE; - CPU_SIG :NODE; - CPU_REQ :DFF; - CPU_AC :DFF; - BUS_CYC :DFF; - BUS_CYC_END :NODE; - BLITTER_REQ :DFF; - BLITTER_AC :DFF; - BLITTER_ROW_ADR[12..0] :NODE; - BLITTER_BA[1..0] :NODE; - BLITTER_COL_ADR[9..0] :NODE; - FIFO_REQ :DFF; - FIFO_AC :DFF; - FIFO_ROW_ADR[12..0] :NODE; - FIFO_BA[1..0] :NODE; - FIFO_COL_ADR[9..0] :NODE; - FIFO_ACTIVE :NODE; - CLR_FIFO_SYNC :DFF; - CLEAR_FIFO_CNT :DFF; - STOP :DFF; - SR_FIFO_WRE :DFF; - FIFO_BANK_OK :DFF; - FIFO_BANK_NOT_OK :NODE; - DDR_REFRESH_ON :NODE; - DDR_REFRESH_CNT[10..0] :DFF; - DDR_REFRESH_REQ :DFF; - DDR_REFRESH_SIG[3..0] :DFFE; - REFRESH_TIME :DFF; - VIDEO_BASE_L_D[7..0] :DFFE; - VIDEO_BASE_L :NODE; - VIDEO_BASE_M_D[7..0] :DFFE; - VIDEO_BASE_M :NODE; - VIDEO_BASE_H_D[7..0] :DFFE; - VIDEO_BASE_H :NODE; - VIDEO_BASE_X_D[2..0] :DFFE; - VIDEO_ADR_CNT[22..0] :DFFE; - VIDEO_CNT_L :NODE; - VIDEO_CNT_M :NODE; - VIDEO_CNT_H :NODE; - VIDEO_BASE_ADR[22..0] :NODE; - VIDEO_ACT_ADR[26..0] :NODE; - -BEGIN - LINE = FB_SIZE0 & FB_SIZE1; - - -- BYT SELECT - FB_B0 = FB_ADR[1..0]==0 -- ADR==0 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - - -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR.CLK = MAIN_CLK; - CASE FB_REGDDR IS - WHEN FR_WAIT => - FB_LE0 = !nFB_WR; - IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - FB_REGDDR = FR_S0; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S0 => - IF DDR_CS THEN - FB_LE0 = !nFB_WR; - VIDEO_DDR_TA = VCC; - IF LINE THEN - FB_VDOE0 = !nFB_OE & !DDR_CONFIG; - FB_REGDDR = FR_S1; - ELSE - BUS_CYC_END = VCC; - FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; - FB_REGDDR = FR_WAIT; - END IF; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S1 => - IF DDR_CS THEN - FB_VDOE1 = !nFB_OE & !DDR_CONFIG; - FB_LE1 = !nFB_WR; - VIDEO_DDR_TA = VCC; - FB_REGDDR = FR_S2; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S2 => - IF DDR_CS THEN - FB_VDOE2 = !nFB_OE & !DDR_CONFIG; - FB_LE2 = !nFB_WR; - IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN - FB_REGDDR = FR_S2; - ELSE - VIDEO_DDR_TA = VCC; - FB_REGDDR = FR_S3; - END IF; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S3 => - IF DDR_CS THEN - FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; - FB_LE3 = !nFB_WR; - VIDEO_DDR_TA = VCC; - BUS_CYC_END = VCC; - FB_REGDDR = FR_WAIT; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - END CASE; - - -- DDR STEUERUNG ----------------------------------------------------- - -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE = VIDEO_RAM_CTR0; - nVCS = !VIDEO_RAM_CTR1; - DDR_REFRESH_ON = VIDEO_RAM_CTR2; - DDR_CONFIG = VIDEO_RAM_CTR3; - FIFO_ACTIVE = VIDEO_RAM_CTR8; --------------------------------- - CPU_ROW_ADR[] = FB_ADR[26..14]; - CPU_BA[] = FB_ADR[13..12]; - CPU_COL_ADR[] = FB_ADR[11..2]; - nVRAS = !VRAS; - nVCAS = !VCAS; - nVWE = !VWE; - SR_DDR_WR.CLK = DDRCLK0; - SR_DDRWR_D_SEL.CLK = DDRCLK0; - SR_VDMP[7..0].CLK = DDRCLK0; - SR_FIFO_WRE.CLK = DDRCLK0; - CPU_AC.CLK = DDRCLK0; - FIFO_AC.CLK = DDRCLK0; - BLITTER_AC.CLK = DDRCLK0; - DDRWR_D_SEL1 = BLITTER_AC; - - -- SELECT LOGIC - DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; - DDR_CS.CLK = MAIN_CLK; - DDR_CS.ENA = FB_ALE; - DDR_CS = DDR_SEL; - - -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER - CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG - # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS - # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER - CPU_REQ.CLK = DDR_SYNC_66M; - CPU_REQ = CPU_SIG - # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG - BUS_CYC.CLK = DDRCLK0; - BUS_CYC = BUS_CYC & !BUS_CYC_END; - - -- STATE MACHINE SYNCHRONISIEREN ----------------- - MCS[].CLK = DDRCLK0; - MCS0 = MAIN_CLK; - MCS1 = MCS0; - CPU_DDR_SYNC.CLK = DDRCLK0; - CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN - - --------------------------------------------------- - VA_S[].CLK = DDRCLK0; - BA_S[].CLK = DDRCLK0; - VA[] = VA_S[]; - BA[] = BA_S[]; - VA_P[].CLK = DDRCLK0; - BA_P[].CLK = DDRCLK0; - - -- DDR STATE MACHINE ----------------------------------------------- - DDR_SM.CLK = DDRCLK0; - CASE DDR_SM IS - WHEN DS_T1 => - IF DDR_REFRESH_REQ THEN - DDR_SM = DS_R2; - ELSE - IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? - IF DDR_CONFIG THEN -- JA - DDR_SM = DS_C2; - ELSE - IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE - VA_S[] = CPU_ROW_ADR[]; - BA_S[] = CPU_BA[]; - CPU_AC = VCC; - BUS_CYC = VCC; - DDR_SM = DS_T2B; - ELSE - IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT - VA_P[] = FIFO_ROW_ADR[]; - BA_P[] = FIFO_BA[]; - FIFO_AC = VCC; -- VORBESETZEN - ELSE - VA_P[] = BLITTER_ROW_ADR[]; - BA_P[] = BLITTER_BA[]; - BLITTER_AC = VCC; -- VORBESETZEN - END IF; - DDR_SM = DS_T2A; - END IF; - END IF; - ELSE - DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN - END IF; - END IF; - - WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - IF DDR_SEL & (nFB_WR # !LINE) THEN - VRAS = VCC; - VA[] = FB_AD[26..14]; - BA[] = FB_AD[13..12]; - VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - ELSE - VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; - VA[] = VA_P[]; - BA[] = BA_P[]; - VA_S[10] = !(FIFO_AC & FIFO_REQ); - FIFO_BANK_OK = FIFO_AC & FIFO_REQ; - FIFO_AC = FIFO_AC & FIFO_REQ; - BLITTER_AC = BLITTER_AC & BLITTER_REQ; - END IF; - DDR_SM = DS_T3; - - WHEN DS_T2B => - VRAS = VCC; - FIFO_BANK_NOT_OK = VCC; - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - DDR_SM = DS_T3; - - WHEN DS_T3 => - CPU_AC = CPU_AC; - FIFO_AC = FIFO_AC; - BLITTER_AC = BLITTER_AC; - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN - DDR_SM = DS_T4W; - ELSE - IF CPU_AC THEN -- CPU? - VA_S[9..0] = CPU_COL_ADR[]; - BA_S[] = CPU_BA[]; - DDR_SM = DS_T4R; - ELSE - IF FIFO_AC THEN -- FIFO? - VA_S[9..0] = FIFO_COL_ADR[]; - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T4F; - ELSE - IF BLITTER_AC THEN - VA_S[9..0] = BLITTER_COL_ADR[]; - BA_S[] = BLITTER_BA[]; - DDR_SM = DS_T4R; - ELSE - DDR_SM = DS_N8; - END IF; - END IF; - END IF; - END IF; - - -- READ - WHEN DS_T4R => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VCAS = VCC; - SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU - SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN - DDR_SM = DS_T5R; - - WHEN DS_T5R => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK - VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- MANUELL PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; - END IF; - - -- WRITE - WHEN DS_T4W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - DDR_SM = DS_T5W; - - WHEN DS_T5W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VA_S[9..0] = CPU_AC & CPU_COL_ADR[] - # BLITTER_AC & BLITTER_COL_ADR[]; - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - BA_S[] = CPU_AC & CPU_BA[] - # BLITTER_AC & BLITTER_BA[]; - SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE - SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE - DDR_SM = DS_T6W; - - WHEN DS_T6W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VCAS = VCC; - VWE = VCC; - SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV - DDR_SM = DS_T7W; - - WHEN DS_T7W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - DDR_SM = DS_T8W; - - WHEN DS_T8W => - DDR_SM = DS_T9W; - - WHEN DS_T9W => - IF FIFO_REQ & FIFO_BANK_OK THEN - VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; - END IF; - - -- FIFO READ - WHEN DS_T4F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T5F; - - WHEN DS_T5F => - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - ELSE - VA_S[9..0] = FIFO_COL_ADR[]+4; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN - END IF; - - WHEN DS_T6F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T7F; - - WHEN DS_T7F => - IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN - VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - ELSE - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - ELSE - VA_S[9..0] = FIFO_COL_ADR[]+4; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T8F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - END IF; - END IF; - - WHEN DS_T8F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - IF FIFO_MW[] - ELSE - DDR_SM = DS_T9F; - END IF; - - WHEN DS_T9F => - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - ELSE - VA_P[9..0] = FIFO_COL_ADR[]+4; - VA_P[10] = GND; -- NON AUTO PRECHARGE - BA_P[] = FIFO_BA[]; - DDR_SM = DS_T10F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - END IF; - - WHEN DS_T10F => - IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN - VRAS = VCC; - VA[] = FB_AD[26..14]; - BA[] = FB_AD[13..12]; - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK - DDR_SM = DS_T3; - ELSE - VCAS = VCC; - VA[] = VA_P[]; - BA[] = BA_P[]; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T7F; - END IF; - - - -- CONFIG CYCLUS - WHEN DS_C2 => - DDR_SM = DS_C3; - WHEN DS_C3 => - BUS_CYC = CPU_REQ; - DDR_SM = DS_C4; - WHEN DS_C4 => - IF CPU_REQ THEN - DDR_SM = DS_C5; - ELSE - DDR_SM = DS_T1; - END IF; - WHEN DS_C5 => - DDR_SM = DS_C6; - WHEN DS_C6 => - VA_S[] = FB_AD[12..0]; - BA_S[] = FB_AD[14..13]; - DDR_SM = DS_C7; - WHEN DS_C7 => - VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - DDR_SM = DS_N8; - - -- CLOSE FIFO BANK - WHEN DS_CB6 => - FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN - VWE = VCC; - DDR_SM = DS_N7; - WHEN DS_CB8 => - FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN - VWE = VCC; - DDR_SM = DS_T1; - - -- REFRESH 70NS = 10 ZYCLEN - WHEN DS_R2 => - IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - VRAS = VCC; -- ALLE BANKS SCHLIESSEN - VWE = VCC; - VA[10] = VCC; - FIFO_BANK_NOT_OK = VCC; - DDR_SM = DS_R4; - ELSE - VCAS = VCC; - VRAS = VCC; - DDR_SM = DS_R3; - END IF; - WHEN DS_R3 => - DDR_SM = DS_R4; - WHEN DS_R4 => - DDR_SM = DS_R5; - WHEN DS_R5 => - DDR_SM = DS_R6; - WHEN DS_R6 => - DDR_SM = DS_N5; - - -- LEERSCHLAUFE - WHEN DS_N5 => - DDR_SM = DS_N6; - WHEN DS_N6 => - DDR_SM = DS_N7; - WHEN DS_N7 => - DDR_SM = DS_N8; - WHEN DS_N8 => - DDR_SM = DS_T1; - END CASE; - ---------------------------------------------------------------- --- BLITTER ---------------------- ------------------------------------------ - BLITTER_REQ.CLK = DDRCLK0; - BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; - BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; - BLITTER_BA1 = BLITTER_ADR13; - BLITTER_BA0 = BLITTER_ADR12; - BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; ------------------------------------------------------------------------------- --- FIFO --------------------------------- --------------------------------------------------------- - FIFO_REQ.CLK = DDRCLK0; - FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS ------------------------------------------------------------------------------------------ - DDR_REFRESH_CNT[].CLK = CLK33M; - DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 - REFRESH_TIME.CLK = DDRCLK0; - REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC - DDR_REFRESH_SIG[].CLK = DDRCLK0; - DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; - DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) - # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT - DDR_REFRESH_REQ.CLK = DDRCLK0; - DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; ------------------------------------------------------------ --- VIDEO REGISTER ----------------------- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D[].CLK = MAIN_CLK; - VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 - VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; - - VIDEO_BASE_M_D[].CLK = MAIN_CLK; - VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 - VIDEO_BASE_M_D[] = FB_AD[23..16]; - VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; - - VIDEO_BASE_H_D[].CLK = MAIN_CLK; - VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 - VIDEO_BASE_H_D[] = FB_AD[23..16]; - VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; - VIDEO_BASE_X_D[].CLK = MAIN_CLK; - VIDEO_BASE_X_D[] = FB_AD[26..24]; - VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; - - VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 - VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 - VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 - - FB_AD[31..24] = lpm_bustri_BYT( - VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) - # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), - (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - - FB_AD[23..16] = lpm_bustri_BYT( - VIDEO_BASE_L & VIDEO_BASE_L_D[] - # VIDEO_BASE_M & VIDEO_BASE_M_D[] - # VIDEO_BASE_H & VIDEO_BASE_H_D[] - # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] - # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] - # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] - , (VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); -END; - diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf deleted file mode 100644 index c2a30de..0000000 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ /dev/null @@ -1,794 +0,0 @@ -TITLE "VIDEO MODUSE UND CLUT CONTROL"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_WORD.inc"; -INCLUDE "lpm_bustri_BYT.inc"; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN video_mod_mux_clutctr -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nFB_BURST : INPUT; - FB_ADR[31..0] : INPUT; - CLK33M : INPUT; - CLK25M : INPUT; - BLITTER_RUN : INPUT; - CLK_VIDEO : INPUT; - VR_D[8..0] : INPUT; - VR_BUSY : INPUT; - COLOR8 : OUTPUT; - ACP_CLUT_RD : OUTPUT; - COLOR1 : OUTPUT; - FALCON_CLUT_RDH : OUTPUT; - FALCON_CLUT_RDL : OUTPUT; - FALCON_CLUT_WR[3..0] : OUTPUT; - ST_CLUT_RD : OUTPUT; - ST_CLUT_WR[1..0] : OUTPUT; - CLUT_MUX_ADR[3..0] : OUTPUT; - HSYNC : OUTPUT; - VSYNC : OUTPUT; - nBLANK : OUTPUT; - nSYNC : OUTPUT; - nPD_VGA : OUTPUT; - FIFO_RDE : OUTPUT; - COLOR2 : OUTPUT; - COLOR4 : OUTPUT; - PIXEL_CLK : OUTPUT; - CLUT_OFF[3..0] : OUTPUT; - BLITTER_ON : OUTPUT; - VIDEO_RAM_CTR[15..0] : OUTPUT; - VIDEO_MOD_TA : OUTPUT; - BORDER_COLOR[23..0] : OUTPUT; - CCSEL[2..0] : OUTPUT; - ACP_CLUT_WR[3..0] : OUTPUT; - INTER_ZEI : OUTPUT; - DOP_FIFO_CLR : OUTPUT; - VIDEO_RECONFIG : OUTPUT; - VR_WR : OUTPUT; - VR_RD : OUTPUT; - CLR_FIFO : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - CLK17M :DFF; - CLK13M :DFF; - ACP_CLUT_CS :NODE; - ACP_CLUT :NODE; - VIDEO_PLL_CONFIG_CS :NODE; - VR_WR :DFF; - VR_DOUT[8..0] :DFFE; - VR_FRQ[7..0] :DFFE; - VIDEO_PLL_RECONFIG_CS :NODE; - VIDEO_RECONFIG :DFF; - FALCON_CLUT_CS :NODE; - FALCON_CLUT :NODE; - ST_CLUT_CS :NODE; - ST_CLUT :NODE; - FB_B[3..0] :NODE; - FB_16B[1..0] :NODE; - ST_SHIFT_MODE[1..0] :DFFE; - ST_SHIFT_MODE_CS :NODE; - FALCON_SHIFT_MODE[10..0] :DFFE; - FALCON_SHIFT_MODE_CS :NODE; - CLUT_MUX_ADR[3..0] :DFF; - CLUT_MUX_AV[1..0][3..0] :DFF; - ACP_VCTR_CS :NODE; - ACP_VCTR[31..0] :DFFE; - BORDER_COLOR_CS :NODE; - BORDER_COLOR[23..0] :DFFE; - ACP_VIDEO_ON :NODE; - SYS_CTR[6..0] :DFFE; - SYS_CTR_CS :NODE; - LOF[15..0] :DFFE; - LOF_CS :NODE; - LWD[15..0] :DFFE; - LWD_CS :NODE; --- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT - HSYNC :DFF; - HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK - HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT - VSYNC :DFF; - VSYNC_START :DFFE; - VSYNC_I[2..0] :DFFE; - nBLANK :DFF; - DISP_ON :DFF; - DPO_ZL :DFFE; - DPO_ON :DFF; - DPO_OFF :DFF; - VDTRON :DFF; - VCO_ZL :DFFE; - VCO_ON :DFF; - VCO_OFF :DFF; - VHCNT[11..0] :DFF; - SUB_PIXEL_CNT[6..0] :DFFE; - VVCNT[10..0] :DFFE; - VERZ[2..0][9..0] :DFF; - RAND[6..0] :DFF; - RAND_ON :NODE; - FIFO_RDE :DFF; - CLR_FIFO :DFFE; - START_ZEILE :DFFE; - SYNC_PIX :DFF; - SYNC_PIX1 :DFF; - SYNC_PIX2 :DFF; - CCSEL[2..0] :DFF; - COLOR16 :NODE; - COLOR24 :NODE; - --- ATARI RESOLUTION - ATARI_SYNC :NODE; - ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 - ATARI_HH_CS :NODE; - ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480 - ATARI_VH_CS :NODE; - ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240 - ATARI_HL_CS :NODE; - ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240 - ATARI_VL_CS :NODE; --- HORIZONTAL - RAND_LINKS[11..0] :NODE; - HDIS_START[11..0] :NODE; - HDIS_END[11..0] :NODE; - RAND_RECHTS[11..0] :NODE; - HS_START[11..0] :NODE; - H_TOTAL[11..0] :NODE; - HDIS_LEN[11..0] :NODE; - MULF[5..0] :NODE; - HHT[11..0] :DFFE; - HHT_CS :NODE; - HBE[11..0] :DFFE; - HBE_CS :NODE; - HDB[11..0] :DFFE; - HDB_CS :NODE; - HDE[11..0] :DFFE; - HDE_CS :NODE; - HBB[11..0] :DFFE; - HBB_CS :NODE; - HSS[11..0] :DFFE; - HSS_CS :NODE; --- VERTIKAL - RAND_OBEN[10..0] :NODE; - VDIS_START[10..0] :NODE; - VDIS_END[10..0] :NODE; - RAND_UNTEN[10..0] :NODE; - VS_START[10..0] :NODE; - V_TOTAL[10..0] :NODE; - FALCON_VIDEO :NODE; - ST_VIDEO :NODE; - INTER_ZEI :DFF; - DOP_ZEI :DFF; - DOP_FIFO_CLR :DFF; - - VBE[10..0] :DFFE; - VBE_CS :NODE; - VDB[10..0] :DFFE; - VDB_CS :NODE; - VDE[10..0] :DFFE; - VDE_CS :NODE; - VBB[10..0] :DFFE; - VBB_CS :NODE; - VSS[10..0] :DFFE; - VSS_CS :NODE; - VFT[10..0] :DFFE; - VFT_CS :NODE; - VCO[8..0] :DFFE; - VCO_CS :NODE; - VCNTRL[3..0] :DFFE; - VCNTRL_CS :NODE; - -BEGIN - -- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0] == 0; -- ADR==0 - FB_B1 = FB_ADR[1..0] == 1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0] == 2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - - -- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0] == 0; -- ADR==0 - FB_16B1 = FB_ADR[0] == 1 -- ADR==1 - # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT - - -- ACP CLUT -- - ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 - ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; - ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - - CLUT_TA.CLK = MAIN_CLK; - CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; - - --FALCON CLUT -- - FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 - FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD - FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD - FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - - -- ST CLUT -- - ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 - ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; - ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; - - -- ST SHIFT MODE - ST_SHIFT_MODE[].CLK = MAIN_CLK; - ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 - ST_SHIFT_MODE[] = FB_AD[25..24]; - ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO - COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN - COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN - - -- FALCON SHIFT MODE - FALCON_SHIFT_MODE[].CLK = MAIN_CLK; - FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 - FALCON_SHIFT_MODE[] = FB_AD[26..16]; - FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; - FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; - - -- ACP VIDEO CONTROL - -- BIT 0 = ACP VIDEO ON - -- BIT 1 = POWER ON VIDEO DAC - -- BIT 2 = ACP 24BIT - -- BIT 3 = ACP 16BIT - -- BIT 4 = ACP 8BIT - -- BIT 5 = ACP 1BIT - -- BIT 6 = FALCON SHIFT MODE - -- BIT 7 = ST SHIFT MODE - -- BIT 9..8 = VCLK FREQUENZ - -- BIT 15 =-SYNC ALLOWED - -- BIT 31..16 = VIDEO_RAM_CTR - -- BIT 25 = RANDFARBE EINSCHALTEN - -- BIT 26 = STANDARD ATARI SYNCS - ACP_VCTR[].CLK = MAIN_CLK; - ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 - ACP_VCTR[31..8] = FB_AD[31..8]; - ACP_VCTR[5..0] = FB_AD[5..0]; - ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; - ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; - ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; - ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; - ACP_VIDEO_ON = ACP_VCTR0; - nPD_VGA = ACP_VCTR1; - - -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG - - -- HORIZONTAL TIMING 640x480 - ATARI_HH[].CLK = MAIN_CLK; - ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2] == H"104"; -- $410/4 - ATARI_HH[] = FB_AD[]; - ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; - ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; - ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; - ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - - -- VERTIKAL TIMING 640x480 - ATARI_VH[].CLK = MAIN_CLK; - ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2] == H"105"; -- $414/4 - ATARI_VH[] = FB_AD[]; - ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; - ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; - ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; - ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - - -- HORIZONTAL TIMING 320x240 - ATARI_HL[].CLK = MAIN_CLK; - ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2] == H"106"; -- $418/4 - ATARI_HL[] = FB_AD[]; - ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; - ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; - ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; - ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - - -- VERTIKAL TIMING 320x240 - ATARI_VL[].CLK = MAIN_CLK; - ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2] == H"107"; -- $41C/4 - ATARI_VL[] = FB_AD[]; - ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; - ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; - ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; - ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; - - -- VIDEO PLL CONFIG - VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9] == H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VR_WR.CLK = MAIN_CLK; - VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; - VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; - - VR_DOUT[].CLK = MAIN_CLK; - VR_DOUT[].ENA = !VR_BUSY; - VR_DOUT[] = VR_D[]; - VR_FRQ[].CLK = MAIN_CLK; - VR_FRQ[].ENA = VR_WR & FB_ADR[8..0] == H"04"; - VR_FRQ[] = FB_AD[23..16]; - - -- VIDEO PLL RECONFIG - VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0] == H"800" & FB_B0; -- $(F)000'0800 - VIDEO_RECONFIG.CLK = MAIN_CLK; - VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; - ------------------------------------------------------------------------------------------------------------------------ - VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; - -------------- COLOR MODE IM ACP SETZEN - COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; - ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; - - -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; - FALCON_VIDEO = ACP_VCTR7; - FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; - ST_VIDEO = ACP_VCTR6; - ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; - CCSEL[].CLK = PIXEL_CLK; - CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION - # B"001" & FALCON_CLUT - # B"100" & ACP_CLUT - # B"101" & COLOR16 - # B"110" & COLOR24 - # B"111" & RAND_ON; - - -- DIVERSE (VIDEO)-REGISTER ---------------------------- - -- RANDFARBE - BORDER_COLOR[].CLK = MAIN_CLK; - BORDER_COLOR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 - BORDER_COLOR[] = FB_AD[23..0]; - BORDER_COLOR[23..16].ENA = BORDER_COLOR_CS & FB_B1 & !nFB_WR; - BORDER_COLOR[15..8].ENA = BORDER_COLOR_CS & FB_B2 & !nFB_WR; - BORDER_COLOR[7..0].ENA = BORDER_COLOR_CS & FB_B3 & !nFB_WR; - - -- System Config Register - -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi - -- |||||||| - -- |||||||+- RAM Wait Status - -- ||||||| 0 = 1 Wait (default) - -- ||||||| 1 = 0 Wait - -- ||||||+-- Video Bus Width - -- |||||| 0 = 16 Bit - -- |||||| 1 = 32 Bit (default) - -- ||||++--- ROM Wait Status - -- |||| 00 = reserved - -- |||| 01 = 2 Wait (default) - -- |||| 10 = 1 Wait - -- |||| 11 = 0 Wait - -- ||++----- Main Memory Size - -- || 01 = 4 MB - -- || 10 = 16 MB - -- ++------- Monitor Type - -- 00 Monochrome - -- 01 RGB - -- 10 VGA - -- 11 TV - - SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C003"; -- $8006/2 - SYS_CTR[].CLK = MAIN_CLK; - SYS_CTR[6..0] = FB_AD[22..16]; - SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; - BLITTER_ON = !SYS_CTR3; - - -- LOF - LOF_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C107"; -- $820E/2 - LOF[].CLK = MAIN_CLK; - LOF[] = FB_AD[31..16]; - LOF[15..8].ENA = LOF_CS & !nFB_WR & FB_B2; - LOF[7..0].ENA = LOF_CS & !nFB_WR & FB_B3; - - -- LWD - LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 - LWD[].CLK = MAIN_CLK; - LWD[] = FB_AD[31..16]; - LWD[15..8].ENA = LWD_CS & !nFB_WR & FB_B0; - LWD[7..0].ENA = LWD_CS & !nFB_WR & FB_B1; - - -- HORIZONTAL - -- HHT - HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 - HHT[].CLK = MAIN_CLK; - HHT[] = FB_AD[27..16]; - HHT[11..8].ENA = HHT_CS & !nFB_WR & FB_B2; - HHT[7..0].ENA = HHT_CS & !nFB_WR & FB_B3; - - -- HBE - HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 - HBE[].CLK = MAIN_CLK; - HBE[] = FB_AD[27..16]; - HBE[11..8].ENA = HBE_CS & !nFB_WR & FB_B2; - HBE[7..0].ENA = HBE_CS & !nFB_WR & FB_B3; - - -- HDB - HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 - HDB[].CLK = MAIN_CLK; - HDB[] = FB_AD[27..16]; - HDB[11..8].ENA = HDB_CS & !nFB_WR & FB_B0; - HDB[7..0].ENA = HDB_CS & !nFB_WR & FB_B1; - -- HDE - HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 - HDE[].CLK = MAIN_CLK; - HDE[] = FB_AD[27..16]; - HDE[11..8].ENA = HDE_CS & !nFB_WR & FB_B2; - HDE[7..0].ENA = HDE_CS & !nFB_WR & FB_B3; - - -- HBB - HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 - HBB[].CLK = MAIN_CLK; - HBB[] = FB_AD[27..16]; - HBB[11..8].ENA = HBB_CS & !nFB_WR & FB_B0; - HBB[7..0].ENA = HBB_CS & !nFB_WR & FB_B1; - - -- HSS - HSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C146"; -- Videl HSYNC start register $828C / 2 - HSS[].CLK = MAIN_CLK; - HSS[] = FB_AD[27..16]; - HSS[11..8].ENA = HSS_CS & !nFB_WR & FB_B0; - HSS[7..0].ENA = HSS_CS & !nFB_WR & FB_B1; - - -- VERTIKAL - -- VBE - VBE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C153"; -- $82A6/2 - VBE[].CLK = MAIN_CLK; - VBE[] = FB_AD[26..16]; - VBE[10..8].ENA = VBE_CS & !nFB_WR & FB_B2; - VBE[7..0].ENA = VBE_CS & !nFB_WR & FB_B3; - - -- VDB - VDB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C154"; -- $82A8/2 - VDB[].CLK = MAIN_CLK; - VDB[] = FB_AD[26..16]; - VDB[10..8].ENA = VDB_CS & !nFB_WR & FB_B0; - VDB[7..0].ENA = VDB_CS & !nFB_WR & FB_B1; - - -- VDE - VDE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C155"; -- $82AA/2 - VDE[].CLK = MAIN_CLK; - VDE[] = FB_AD[26..16]; - VDE[10..8].ENA = VDE_CS & !nFB_WR & FB_B2; - VDE[7..0].ENA = VDE_CS & !nFB_WR & FB_B3; - -- VBB - VBB_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C152"; -- $82A4/2 - VBB[].CLK = MAIN_CLK; - VBB[] = FB_AD[26..16]; - VBB[10..8].ENA = VBB_CS & !nFB_WR & FB_B0; - VBB[7..0].ENA = VBB_CS & !nFB_WR & FB_B1; - - -- VSS - VSS_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C156"; -- $82AC/2 - VSS[].CLK = MAIN_CLK; - VSS[] = FB_AD[26..16]; - VSS[10..8].ENA = VSS_CS & !nFB_WR & FB_B0; - VSS[7..0].ENA = VSS_CS & !nFB_WR & FB_B1; - - -- VFT - VFT_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C151"; -- $82A2/2 - VFT[].CLK = MAIN_CLK; - VFT[] = FB_AD[26..16]; - VFT[10..8].ENA = VFT_CS & !nFB_WR & FB_B2; - VFT[7..0].ENA = VFT_CS & !nFB_WR & FB_B3; - - -- VCO - VCO_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C160"; -- $82C0 / 2 Falcon clock control register VCO - VCO[].CLK = MAIN_CLK; - VCO[] = FB_AD[24..16]; - VCO[8].ENA = VCO_CS & !nFB_WR & FB_B0; - VCO[7..0].ENA = VCO_CS & !nFB_WR & FB_B1; - - -- VCNTRL - VCNTRL_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C161"; -- $82C2 / 2 Falcon resolution control register VCNTRL - VCNTRL[].CLK = MAIN_CLK; - VCNTRL[] = FB_AD[19..16]; - VCNTRL[3..0].ENA = VCNTRL_CS & !nFB_WR & FB_B3; - - --- REGISTER OUT - -- low word register access - FB_AD[31..16] = lpm_bustri_WORD( - ST_SHIFT_MODE_CS & (0, ST_SHIFT_MODE[],B"00000000") - # FALCON_SHIFT_MODE_CS & (0, FALCON_SHIFT_MODE[]) - # SYS_CTR_CS & (B"100000000", SYS_CTR[6..4], !BLITTER_RUN, SYS_CTR[2..0]) - # LOF_CS & LOF[] - # LWD_CS & LWD[] - # HBE_CS & (0, HBE[]) - # HDB_CS & (0, HDB[]) - # HDE_CS & (0, HDE[]) - # HBB_CS & (0, HBB[]) - # HSS_CS & (0, HSS[]) - # HHT_CS & (0, HHT[]) - # VBE_CS & (0, VBE[]) - # VDB_CS & (0, VDB[]) - # VDE_CS & (0, VDE[]) - # VBB_CS & (0, VBB[]) - # VSS_CS & (0, VSS[]) - # VFT_CS & (0, VFT[]) - # VCO_CS & (0, VCO[]) - # VCNTRL_CS & (0, VCNTRL[]) - # ACP_VCTR_CS & ACP_VCTR[31..16] - # ATARI_HH_CS & ATARI_HH[31..16] - # ATARI_VH_CS & ATARI_VH[31..16] - # ATARI_HL_CS & ATARI_HL[31..16] - # ATARI_VL_CS & ATARI_VL[31..16] - # BORDER_COLOR_CS & (0, BORDER_COLOR[23..16]) - # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) - # VIDEO_PLL_RECONFIG_CS & (VR_BUSY, B"0000", VR_WR, VR_RD, VIDEO_RECONFIG, H"FA") - ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # BORDER_COLOR_CS # SYS_CTR_CS # LOF_CS # LWD_CS - # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS - # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS - # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS) & !nFB_OE); - - -- high word register access - FB_AD[15..0] = lpm_bustri_WORD( - ACP_VCTR_CS & ACP_VCTR[15..0] - # ATARI_HH_CS & ATARI_HH[15..0] - # ATARI_VH_CS & ATARI_VH[15..0] - # ATARI_HL_CS & ATARI_HL[15..0] - # ATARI_VL_CS & ATARI_VL[15..0] - # BORDER_COLOR_CS & BORDER_COLOR[15..0], - (ACP_VCTR_CS # BORDER_COLOR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); - - VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # LOF_CS # LWD_CS - # HBE_CS # HDB_CS # HDE_CS # HBB_CS # HSS_CS # HHT_CS - # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS - # VBE_CS # VDB_CS # VDE_CS # VBB_CS # VSS_CS # VFT_CS # VCO_CS # VCNTRL_CS; - - -- VIDEO AUSGABE SETZEN - CLK17M.CLK = CLK33M; - CLK17M = !CLK17M; - - CLK13M.CLK = CLK25M; - CLK13M = !CLK13M; - - PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz, - # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz, - # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, VGA monitor - # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA monitor - # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00" - # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01" - # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; - - -------------------------------------------------------------- - -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK - ---------------------------------------------------------------- - -- HSY_LEN[].CLK = MAIN_CLK; - HSY_LEN[].CLK = PIXEL_CLK; -- check if this is better (mfro) - HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & VCO2 # VCO0) -- 320 pixels, 32 MHz, RGB - # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & (VCNTRL2 & !VCO2 # VCO0) -- 320 pixels, 25.175 MHz, VGA - # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & VCO2 & !VCO0 -- 640 pixels, 32 MHz, RGB - # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VCNTRL2 & !VCO2 & !VCO0 -- 640 pixels, 25.175 MHz, VGA - # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"00" - # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8] == B"01" - # 16 + (0, VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync pulse length in pixeln = frequenz / = 500ns - - MULF[] = 2 & !ST_VIDEO & VCNTRL2 -- MULTIPLIKATIONS FAKTOR - # 4 & !ST_VIDEO & !VCNTRL2 - # 16 & ST_VIDEO & VCNTRL2 - # 32 & ST_VIDEO & !VCNTRL2; - - - HDIS_LEN[] = 320 & VCNTRL2 -- BREITE IN PIXELN - # 640 & !VCNTRL2; - - -- DOPPELZEILENMODUS - DOP_ZEI.CLK = MAIN_CLK; - DOP_ZEI = VCNTRL0 & (FALCON_VIDEO # ST_VIDEO); -- ZEILENVERDOPPELUNG EIN AUS - - INTER_ZEI.CLK = PIXEL_CLK; - INTER_ZEI = DOP_ZEI & VVCNT0 != VDIS_START0 & VVCNT[] != 0 & VHCNT[] < (HDIS_END[] - 1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC - # DOP_ZEI & VVCNT0 == VDIS_START0 & VVCNT[] != 0 & VHCNT[] > (HDIS_END[] - 2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC - - DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - -% RAND_LINKS[] = HBE[] & ACP_VIDEO_ON - # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 - # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 - # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- -% - HDIS_START[] = HDB[] & ACP_VIDEO_ON - # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- - - HDIS_END[] = HDE[] & ACP_VIDEO_ON - # RAND_LINKS[] + HDIS_LEN[] & !ACP_VIDEO_ON; -- - - RAND_RECHTS[] = HBB[] & ACP_VIDEO_ON - # HDIS_END[] + 1 & !ACP_VIDEO_ON; -- - -% HS_START[] = HSS[] & ACP_VIDEO_ON - # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 - # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 - # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - % -% H_TOTAL[] = HHT[] & ACP_VIDEO_ON - # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 - # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 - # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- -% - RAND_OBEN[] = VBE[] & ACP_VIDEO_ON - # 31 & !ACP_VIDEO_ON & ATARI_SYNC - # (0, VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - - VDIS_START[] = VDB[] & ACP_VIDEO_ON - # 32 & !ACP_VIDEO_ON & ATARI_SYNC - # (0, VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - - VDIS_END[] = VDE[] & ACP_VIDEO_ON - # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO - # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO - # (0, VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - - RAND_UNTEN[] = VBB[] & ACP_VIDEO_ON - # VDIS_END[] + 1 & !ACP_VIDEO_ON & ATARI_SYNC - # (0, VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - - VS_START[] = VSS[] & ACP_VIDEO_ON - # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 - # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 - # (0, VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - - V_TOTAL[] = VFT[] & ACP_VIDEO_ON - # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 - # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 - # (0, VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - -- ZÄHLER - LAST.CLK = PIXEL_CLK; - LAST = VHCNT[] == (H_TOTAL[] - 2); - - VHCNT[].CLK = PIXEL_CLK; - VHCNT[] = (VHCNT[] + 1) & !LAST; - - VVCNT[].CLK = PIXEL_CLK; - VVCNT[].ENA = LAST; - VVCNT[] = (VVCNT[] + 1) & (VVCNT[] != V_TOTAL[] - 1); - - -- DISPLAY ON OFF - DPO_ZL.CLK = PIXEL_CLK; - DPO_ZL = (VVCNT[] > RAND_OBEN[] - 1) & (VVCNT[] < RAND_UNTEN[] - 1); -- 1 ZEILE DAVOR ON OFF - DPO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN - - DPO_ON.CLK = PIXEL_CLK; - DPO_ON = VHCNT[] == RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING - - DPO_OFF.CLK = PIXEL_CLK; - DPO_OFF = VHCNT[] == (RAND_RECHTS[] - 1); - - DISP_ON.CLK = PIXEL_CLK; - DISP_ON = DISP_ON & !DPO_OFF - # DPO_ON & DPO_ZL; - - -- DATENTRANSFER ON OFF - VCO_ON.CLK = PIXEL_CLK; - VCO_ON = VHCNT[] == (HDIS_START[] - 1); -- BESSER EINZELN WEGEN TIMING - - VCO_OFF.CLK = PIXEL_CLK; - VCO_OFF = VHCNT[] == HDIS_END[]; - - VCO_ZL.CLK = PIXEL_CLK; - VCO_ZL.ENA = LAST; -- AM ZEILENENDE ÜBERNEHMEN - VCO_ZL = (VVCNT[] >= (VDIS_START[] - 1)) & (VVCNT[] < VDIS_END[]); -- 1 ZEILE DAVOR ON OFF - - VDTRON.CLK = PIXEL_CLK; - VDTRON = VDTRON & !VCO_OFF - # VCO_ON & VCO_ZL; - - -- VERZÖGERUNG UND SYNC - HSYNC_START.CLK = PIXEL_CLK; - HSYNC_START = VHCNT[] == HS_START[] - 3; - - HSYNC_I[].CLK = PIXEL_CLK; - HSYNC_I[] = HSY_LEN[] & HSYNC_START - # (HSYNC_I[] - 1) & !HSYNC_START & HSYNC_I[] != 0; - - VSYNC_START.CLK = PIXEL_CLK; - VSYNC_START.ENA = LAST; - VSYNC_START = VVCNT[] == (VS_START[] - 3); -- start am ende der Zeile vor dem vsync - - VSYNC_I[].CLK = PIXEL_CLK; - VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync - VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length - # (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[] != 0; -- runterzählen bis 0 - - VERZ[][].CLK = PIXEL_CLK; - VERZ[][1] = VERZ[][0]; - VERZ[][2] = VERZ[][1]; - VERZ[][3] = VERZ[][2]; - VERZ[][4] = VERZ[][3]; - VERZ[][5] = VERZ[][4]; - VERZ[][6] = VERZ[][5]; - VERZ[][7] = VERZ[][6]; - VERZ[][8] = VERZ[][7]; - VERZ[][9] = VERZ[][8]; - VERZ[0][0] = DISP_ON; --- VERZ[1][0] = HSYNC_I[] != 0; - VERZ[1][0] = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0 - # ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE - VERZ[2][0] = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0 - # ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE - - nBLANK.CLK = PIXEL_CLK; - -- nBLANK = VERZ[0][8]; - nBLANK = DISP_ON; - - HSYNC.CLK = PIXEL_CLK; - -- HSYNC = VERZ[1][9]; - HSYNC = (!ACP_VCTR15 # !VCO6) & HSYNC_I[] != 0 - # ACP_VCTR15 & VCO6 & HSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE - - VSYNC.CLK = PIXEL_CLK; - -- VSYNC = VERZ[2][9]; - VSYNC = (!ACP_VCTR15 # !VCO5) & VSYNC_I[] != 0 - # ACP_VCTR15 & VCO5 & VSYNC_I[] == 0; -- NUR MÖGLICH WENN BEIDE - nSYNC = GND; - - -- RANDFARBE MACHEN ------------------------------------ - RAND[].CLK = PIXEL_CLK; - RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25; - RAND[1] = RAND[0]; - RAND[2] = RAND[1]; - RAND[3] = RAND[2]; - RAND[4] = RAND[3]; - RAND[5] = RAND[4]; - RAND[6] = RAND[5]; - -- RAND_ON = RAND[6]; - RAND_ON = DISP_ON & !VDTRON & ACP_VCTR25; - ---------------------------------------------------------- - - CLR_FIFO.CLK = PIXEL_CLK; - CLR_FIFO.ENA = LAST; - CLR_FIFO = VVCNT[] == V_TOTAL[] - 2; -- IN LETZTER ZEILE LÖSCHEN - - START_ZEILE.CLK = PIXEL_CLK; - START_ZEILE.ENA = LAST; - START_ZEILE = VVCNT[] == 0; -- ZEILE 1 - - SYNC_PIX.CLK = PIXEL_CLK; - SYNC_PIX = VHCNT[] == 3 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX1.CLK = PIXEL_CLK; - SYNC_PIX1 = VHCNT[] == 5 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX2.CLK = PIXEL_CLK; - SYNC_PIX2 = VHCNT[] == 7 & START_ZEILE; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - - SUB_PIXEL_CNT[].CLK = PIXEL_CLK; - SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX; - SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix - - FIFO_RDE.CLK = PIXEL_CLK; - FIFO_RDE = (SUB_PIXEL_CNT[6..0] == 1 & COLOR1 - # SUB_PIXEL_CNT[5..0] == 1 & COLOR2 - # SUB_PIXEL_CNT[4..0] == 1 & COLOR4 - # SUB_PIXEL_CNT[3..0] == 1 & COLOR8 - # SUB_PIXEL_CNT[2..0] == 1 & COLOR16 - # SUB_PIXEL_CNT[1..0] == 1 & COLOR24) & VDTRON - # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - - CLUT_MUX_ADR[].CLK = PIXEL_CLK; - - CLUT_MUX_AV[][].CLK = PIXEL_CLK; - CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0]; - CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][]; - CLUT_MUX_ADR[] = CLUT_MUX_AV[1][]; -END; From fd5abf8b4a9058affe18c49ca5881906a5791641 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 13:23:46 +0000 Subject: [PATCH 058/127] reformat --- .../Video/video_mod_mux_clutctr.vhd | 723 +++++++++--------- 1 file changed, 372 insertions(+), 351 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index cb9b77d..e809ac6 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -1,7 +1,7 @@ -- Xilinx XPort Language Converter, Version 4.1 (110) -- --- AHDL Design Source: VIDEO_MOD_MUX_CLUTCTR.tdf --- VHDL Design Output: VIDEO_MOD_MUX_CLUTCTR.vhd +-- AHDL Design Source: .tdf +-- VHDL Design Output: .vhd -- Created 13-Jan-2016 10:03 AM -- -- Copyright (c) 2016, Xilinx, Inc. All Rights Reserved. @@ -70,187 +70,203 @@ ENTITY video_mod_mux_clutctr IS FB_SIZE1 : IN std_logic; nFB_BURST : IN std_logic; FB_ADR : IN std_logic_vector(31 DOWNTO 0); - CLK33M, CLK25M, BLITTER_RUN, CLK_VIDEO: in std_logic; - VR_D: in std_logic_vector(8 downto 0); - VR_BUSY: in std_logic; - COLOR8, ACP_CLUT_RD, COLOR1, FALCON_CLUT_RDH, FALCON_CLUT_RDL: buffer - std_logic; - FALCON_CLUT_WR: buffer std_logic_vector(3 downto 0); - ST_CLUT_RD: buffer std_logic; - ST_CLUT_WR: buffer std_logic_vector(1 downto 0); - CLUT_MUX_ADR: buffer std_logic_vector(3 downto 0); - HSYNC, VSYNC, nBLANK, nSYNC, nPD_VGA, FIFO_RDE, COLOR2, COLOR4, - PIXEL_CLK: buffer std_logic; - CLUT_OFF: buffer std_logic_vector(3 downto 0); - BLITTER_ON: buffer std_logic; - VIDEO_RAM_CTR: buffer std_logic_vector(15 downto 0); - VIDEO_MOD_TA: buffer std_logic; - BORDER_COLOR: buffer std_logic_vector(23 downto 0); - CCSEL: buffer std_logic_vector(2 downto 0); - ACP_CLUT_WR: buffer std_logic_vector(3 downto 0); - INTER_ZEI, DOP_FIFO_CLR, VIDEO_RECONFIG, VR_WR, VR_RD, CLR_FIFO: buffer - std_logic; - FB_AD: inout std_logic_vector(31 downto 0) + CLK33M : IN std_logic; + CLK25M : IN std_logic; + BLITTER_RUN : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_D : IN std_logic_vector(8 DOWNTO 0); + VR_BUSY : IN std_logic; + COLOR8 : BUFFER std_logic; + ACP_CLUT_RD : BUFFER std_logic; + COLOR1 : BUFFER std_logic; + FALCON_CLUT_RDH : BUFFER std_logic; + FALCON_CLUT_RDL : BUFFER std_logic; + FALCON_CLUT_WR : BUFFER std_logic_vector(3 DOWNTO 0); + ST_CLUT_RD : BUFFER std_logic; + ST_CLUT_WR : BUFFER std_logic_vector(1 DOWNTO 0); + CLUT_MUX_ADR : BUFFER std_logic_vector(3 DOWNTO 0); + HSYNC : BUFFER std_logic; + VSYNC : BUFFER std_logic; + nBLANK : BUFFER std_logic; + nSYNC : BUFFER std_logic; + nPD_VGA : BUFFER std_logic; + FIFO_RDE : BUFFER std_logic; + COLOR2 : BUFFER std_logic; + COLOR4 : BUFFER std_logic; + PIXEL_CLK : BUFFER std_logic; + CLUT_OFF : BUFFER std_logic_vector(3 DOWNTO 0); + BLITTER_ON : BUFFER std_logic; + VIDEO_RAM_CTR : BUFFER std_logic_vector(15 DOWNTO 0); + VIDEO_MOD_TA : BUFFER std_logic; + BORDER_COLOR : BUFFER std_logic_vector(23 DOWNTO 0); + CCSEL : BUFFER std_logic_vector(2 DOWNTO 0); + ACP_CLUT_WR : BUFFER std_logic_vector(3 DOWNTO 0); + INTER_ZEI : BUFFER std_logic; + DOP_FIFO_CLR : BUFFER std_logic; + VIDEO_RECONFIG : BUFFER std_logic; + VR_WR : BUFFER std_logic; + VR_RD : BUFFER std_logic; + CLR_FIFO : BUFFER std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0) ); -end VIDEO_MOD_MUX_CLUTCTR; +END video_mod_mux_clutctr; -architecture VIDEO_MOD_MUX_CLUTCTR_behav of VIDEO_MOD_MUX_CLUTCTR is - --- DIV. CONTROL REGISTER --- BRAUCHT EIN WAITSTAT --- LÄNGE HSYNC PULS IN PIXEL_CLK --- LETZTES PIXEL EINER ZEILE ERREICHT --- ATARI RESOLUTION --- HORIZONTAL TIMING 640x480 --- VERTIKAL TIMING 640x480 --- HORIZONTAL TIMING 320x240 --- VERTIKAL TIMING 320x240 --- HORIZONTAL --- VERTIKAL - signal VR_DOUT: std_logic_vector(8 downto 0); - signal VR_DOUT_d: std_logic_vector(8 downto 0); - signal VR_DOUT_q: std_logic_vector(8 downto 0); - signal VR_FRQ: std_logic_vector(7 downto 0); - signal VR_FRQ_d: std_logic_vector(7 downto 0); - signal VR_FRQ_q: std_logic_vector(7 downto 0); - signal FB_B: std_logic_vector(3 downto 0); - signal FB_16B: std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE: std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE_d: std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE_q: std_logic_vector(1 downto 0); - signal FALCON_SHIFT_MODE: std_logic_vector(10 downto 0); - signal FALCON_SHIFT_MODE_d: std_logic_vector(10 downto 0); - signal FALCON_SHIFT_MODE_q: std_logic_vector(10 downto 0); - signal CLUT_MUX_ADR_d: std_logic_vector(3 downto 0); - signal CLUT_MUX_ADR_q: std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1: std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1_d: std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1_q: std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0: std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0_d: std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0_q: std_logic_vector(3 downto 0); - signal ACP_VCTR: std_logic_vector(31 downto 0); - signal ACP_VCTR_d: std_logic_vector(31 downto 0); - signal ACP_VCTR_q: std_logic_vector(31 downto 0); - signal BORDER_COLOR_d: std_logic_vector(23 downto 0); - signal BORDER_COLOR_q: std_logic_vector(23 downto 0); - signal SYS_CTR: std_logic_vector(6 downto 0); - signal SYS_CTR_d: std_logic_vector(6 downto 0); - signal SYS_CTR_q: std_logic_vector(6 downto 0); - signal LOF: std_logic_vector(15 downto 0); - signal LOF_d: std_logic_vector(15 downto 0); - signal LOF_q: std_logic_vector(15 downto 0); - signal LWD: std_logic_vector(15 downto 0); - signal LWD_d: std_logic_vector(15 downto 0); - signal LWD_q: std_logic_vector(15 downto 0); - signal HSYNC_I: std_logic_vector(7 downto 0); - signal HSYNC_I_d: std_logic_vector(7 downto 0); - signal HSYNC_I_q: std_logic_vector(7 downto 0); - signal HSY_LEN: std_logic_vector(7 downto 0); - signal HSY_LEN_d: std_logic_vector(7 downto 0); - signal HSY_LEN_q: std_logic_vector(7 downto 0); - signal VSYNC_I: std_logic_vector(2 downto 0); - signal VSYNC_I_d: std_logic_vector(2 downto 0); - signal VSYNC_I_q: std_logic_vector(2 downto 0); - signal VHCNT: std_logic_vector(11 downto 0); - signal VHCNT_d: std_logic_vector(11 downto 0); - signal VHCNT_q: std_logic_vector(11 downto 0); - signal SUB_PIXEL_CNT: std_logic_vector(6 downto 0); - signal SUB_PIXEL_CNT_d: std_logic_vector(6 downto 0); - signal SUB_PIXEL_CNT_q: std_logic_vector(6 downto 0); - signal VVCNT: std_logic_vector(10 downto 0); - signal VVCNT_d: std_logic_vector(10 downto 0); - signal VVCNT_q: std_logic_vector(10 downto 0); - signal VERZ2: std_logic_vector(9 downto 0); - signal VERZ2_d: std_logic_vector(9 downto 0); - signal VERZ2_q: std_logic_vector(9 downto 0); - signal VERZ1: std_logic_vector(9 downto 0); - signal VERZ1_d: std_logic_vector(9 downto 0); - signal VERZ1_q: std_logic_vector(9 downto 0); - signal VERZ0: std_logic_vector(9 downto 0); - signal VERZ0_d: std_logic_vector(9 downto 0); - signal VERZ0_q: std_logic_vector(9 downto 0); - signal RAND: std_logic_vector(6 downto 0); - signal RAND_d: std_logic_vector(6 downto 0); - signal RAND_q: std_logic_vector(6 downto 0); - signal CCSEL_d: std_logic_vector(2 downto 0); - signal CCSEL_q: std_logic_vector(2 downto 0); - signal ATARI_HH: std_logic_vector(31 downto 0); - signal ATARI_HH_d: std_logic_vector(31 downto 0); - signal ATARI_HH_q: std_logic_vector(31 downto 0); - signal ATARI_VH: std_logic_vector(31 downto 0); - signal ATARI_VH_d: std_logic_vector(31 downto 0); - signal ATARI_VH_q: std_logic_vector(31 downto 0); - signal ATARI_HL: std_logic_vector(31 downto 0); - signal ATARI_HL_d: std_logic_vector(31 downto 0); - signal ATARI_HL_q: std_logic_vector(31 downto 0); - signal ATARI_VL: std_logic_vector(31 downto 0); - signal ATARI_VL_d: std_logic_vector(31 downto 0); - signal ATARI_VL_q: std_logic_vector(31 downto 0); - signal RAND_LINKS: std_logic_vector(11 downto 0); - signal HDIS_START: std_logic_vector(11 downto 0); - signal HDIS_END: std_logic_vector(11 downto 0); - signal RAND_RECHTS: std_logic_vector(11 downto 0); - signal HS_START: std_logic_vector(11 downto 0); - signal H_TOTAL: std_logic_vector(11 downto 0); - signal HDIS_LEN: std_logic_vector(11 downto 0); - signal MULF: std_logic_vector(5 downto 0); - signal HHT: std_logic_vector(11 downto 0); - signal HHT_d: std_logic_vector(11 downto 0); - signal HHT_q: std_logic_vector(11 downto 0); - signal HBE: std_logic_vector(11 downto 0); - signal HBE_d: std_logic_vector(11 downto 0); - signal HBE_q: std_logic_vector(11 downto 0); - signal HDB: std_logic_vector(11 downto 0); - signal HDB_d: std_logic_vector(11 downto 0); - signal HDB_q: std_logic_vector(11 downto 0); - signal HDE: std_logic_vector(11 downto 0); - signal HDE_d: std_logic_vector(11 downto 0); - signal HDE_q: std_logic_vector(11 downto 0); - signal HBB: std_logic_vector(11 downto 0); - signal HBB_d: std_logic_vector(11 downto 0); - signal HBB_q: std_logic_vector(11 downto 0); - signal HSS: std_logic_vector(11 downto 0); - signal HSS_d: std_logic_vector(11 downto 0); - signal HSS_q: std_logic_vector(11 downto 0); - signal RAND_OBEN: std_logic_vector(10 downto 0); - signal VDIS_START: std_logic_vector(10 downto 0); - signal VDIS_END: std_logic_vector(10 downto 0); - signal RAND_UNTEN: std_logic_vector(10 downto 0); - signal VS_START: std_logic_vector(10 downto 0); - signal V_TOTAL: std_logic_vector(10 downto 0); - signal VBE: std_logic_vector(10 downto 0); - signal VBE_d: std_logic_vector(10 downto 0); - signal VBE_q: std_logic_vector(10 downto 0); - signal VDB: std_logic_vector(10 downto 0); - signal VDB_d: std_logic_vector(10 downto 0); - signal VDB_q: std_logic_vector(10 downto 0); - signal VDE: std_logic_vector(10 downto 0); - signal VDE_d: std_logic_vector(10 downto 0); - signal VDE_q: std_logic_vector(10 downto 0); - signal VBB: std_logic_vector(10 downto 0); - signal VBB_d: std_logic_vector(10 downto 0); - signal VBB_q: std_logic_vector(10 downto 0); - signal VSS: std_logic_vector(10 downto 0); - signal VSS_d: std_logic_vector(10 downto 0); - signal VSS_q: std_logic_vector(10 downto 0); - signal VFT: std_logic_vector(10 downto 0); - signal VFT_d: std_logic_vector(10 downto 0); - signal VFT_q: std_logic_vector(10 downto 0); - signal VCO: std_logic_vector(8 downto 0); - signal VCO_d: std_logic_vector(8 downto 0); - signal VCO_ena: std_logic_vector(8 downto 0); - signal VCO_q: std_logic_vector(8 downto 0); - signal VCNTRL: std_logic_vector(3 downto 0); - signal VCNTRL_d: std_logic_vector(3 downto 0); - signal VCNTRL_q: std_logic_vector(3 downto 0); - signal u0_data: std_logic_vector(15 downto 0); - signal u0_tridata: std_logic_vector(15 downto 0); - signal u1_data: std_logic_vector(15 downto 0); - signal u1_tridata: std_logic_vector(15 downto 0); - signal ST_SHIFT_MODE0_clk_ctrl, ST_SHIFT_MODE0_ena_ctrl, - FALCON_SHIFT_MODE0_clk_ctrl, FALCON_SHIFT_MODE8_ena_ctrl, +ARCHITECTURE rtl OF video_mod_mux_clutctr IS + -- DIV. CONTROL REGISTER + -- BRAUCHT EIN WAITSTAT + -- LÄNGE HSYNC PULS IN PIXEL_CLK + -- LETZTES PIXEL EINER ZEILE ERREICHT + -- ATARI RESOLUTION + -- HORIZONTAL TIMING 640x480 + -- VERTIKAL TIMING 640x480 + -- HORIZONTAL TIMING 320x240 + -- VERTIKAL TIMING 320x240 + -- HORIZONTAL + -- VERTIKAL + SIGNAL VR_DOUT: std_logic_vector(8 DOWNTO 0); + SIGNAL VR_DOUT_d: std_logic_vector(8 DOWNTO 0); + SIGNAL VR_DOUT_q: std_logic_vector(8 DOWNTO 0); + SIGNAL VR_FRQ: std_logic_vector(7 DOWNTO 0); + SIGNAL VR_FRQ_d: std_logic_vector(7 DOWNTO 0); + SIGNAL VR_FRQ_q: std_logic_vector(7 DOWNTO 0); + SIGNAL FB_B: std_logic_vector(3 DOWNTO 0); + SIGNAL FB_16B: std_logic_vector(1 DOWNTO 0); + SIGNAL ST_SHIFT_MODE: std_logic_vector(1 DOWNTO 0); + SIGNAL ST_SHIFT_MODE_d: std_logic_vector(1 DOWNTO 0); + SIGNAL ST_SHIFT_MODE_q: std_logic_vector(1 DOWNTO 0); + SIGNAL FALCON_SHIFT_MODE: std_logic_vector(10 DOWNTO 0); + SIGNAL FALCON_SHIFT_MODE_d: std_logic_vector(10 DOWNTO 0); + SIGNAL FALCON_SHIFT_MODE_q: std_logic_vector(10 DOWNTO 0); + SIGNAL CLUT_MUX_ADR_d: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_ADR_q: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV1: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV1_d: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV1_q: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV0: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV0_d: std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV0_q: std_logic_vector(3 DOWNTO 0); + SIGNAL ACP_VCTR: std_logic_vector(31 DOWNTO 0); + SIGNAL ACP_VCTR_d: std_logic_vector(31 DOWNTO 0); + SIGNAL ACP_VCTR_q: std_logic_vector(31 DOWNTO 0); + SIGNAL BORDER_COLOR_d: std_logic_vector(23 DOWNTO 0); + SIGNAL BORDER_COLOR_q: std_logic_vector(23 DOWNTO 0); + SIGNAL SYS_CTR: std_logic_vector(6 DOWNTO 0); + SIGNAL SYS_CTR_d: std_logic_vector(6 DOWNTO 0); + SIGNAL SYS_CTR_q: std_logic_vector(6 DOWNTO 0); + SIGNAL LOF: std_logic_vector(15 DOWNTO 0); + SIGNAL LOF_d: std_logic_vector(15 DOWNTO 0); + SIGNAL LOF_q: std_logic_vector(15 DOWNTO 0); + SIGNAL LWD: std_logic_vector(15 DOWNTO 0); + SIGNAL LWD_d: std_logic_vector(15 DOWNTO 0); + SIGNAL LWD_q: std_logic_vector(15 DOWNTO 0); + SIGNAL HSYNC_I: std_logic_vector(7 DOWNTO 0); + SIGNAL HSYNC_I_d: std_logic_vector(7 DOWNTO 0); + SIGNAL HSYNC_I_q: std_logic_vector(7 DOWNTO 0); + SIGNAL HSY_LEN: std_logic_vector(7 DOWNTO 0); + SIGNAL HSY_LEN_d: std_logic_vector(7 DOWNTO 0); + SIGNAL HSY_LEN_q: std_logic_vector(7 DOWNTO 0); + SIGNAL VSYNC_I: std_logic_vector(2 DOWNTO 0); + SIGNAL VSYNC_I_d: std_logic_vector(2 DOWNTO 0); + SIGNAL VSYNC_I_q: std_logic_vector(2 DOWNTO 0); + SIGNAL VHCNT: std_logic_vector(11 DOWNTO 0); + SIGNAL VHCNT_d: std_logic_vector(11 DOWNTO 0); + SIGNAL VHCNT_q: std_logic_vector(11 DOWNTO 0); + SIGNAL SUB_PIXEL_CNT: std_logic_vector(6 DOWNTO 0); + SIGNAL SUB_PIXEL_CNT_d: std_logic_vector(6 DOWNTO 0); + SIGNAL SUB_PIXEL_CNT_q: std_logic_vector(6 DOWNTO 0); + SIGNAL VVCNT: std_logic_vector(10 DOWNTO 0); + SIGNAL VVCNT_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VVCNT_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VERZ2: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ2_d: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ2_q: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ1: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ1_d: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ1_q: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ0: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ0_d: std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ0_q: std_logic_vector(9 DOWNTO 0); + SIGNAL RAND: std_logic_vector(6 DOWNTO 0); + SIGNAL RAND_d: std_logic_vector(6 DOWNTO 0); + SIGNAL RAND_q: std_logic_vector(6 DOWNTO 0); + SIGNAL CCSEL_d: std_logic_vector(2 DOWNTO 0); + SIGNAL CCSEL_q: std_logic_vector(2 DOWNTO 0); + SIGNAL ATARI_HH: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HH_d: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HH_q: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VH: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VH_d: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VH_q: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL_d: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL_q: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VL: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VL_d: std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VL_q: std_logic_vector(31 DOWNTO 0); + SIGNAL RAND_LINKS: std_logic_vector(11 DOWNTO 0); + SIGNAL HDIS_START: std_logic_vector(11 DOWNTO 0); + SIGNAL HDIS_END: std_logic_vector(11 DOWNTO 0); + SIGNAL RAND_RECHTS: std_logic_vector(11 DOWNTO 0); + SIGNAL HS_START: std_logic_vector(11 DOWNTO 0); + SIGNAL H_TOTAL: std_logic_vector(11 DOWNTO 0); + SIGNAL HDIS_LEN: std_logic_vector(11 DOWNTO 0); + SIGNAL MULF: std_logic_vector(5 DOWNTO 0); + SIGNAL HHT: std_logic_vector(11 DOWNTO 0); + SIGNAL HHT_d: std_logic_vector(11 DOWNTO 0); + SIGNAL HHT_q: std_logic_vector(11 DOWNTO 0); + SIGNAL HBE: std_logic_vector(11 DOWNTO 0); + SIGNAL HBE_d: std_logic_vector(11 DOWNTO 0); + SIGNAL HBE_q: std_logic_vector(11 DOWNTO 0); + SIGNAL HDB: std_logic_vector(11 DOWNTO 0); + SIGNAL HDB_d: std_logic_vector(11 DOWNTO 0); + SIGNAL HDB_q: std_logic_vector(11 DOWNTO 0); + SIGNAL HDE: std_logic_vector(11 DOWNTO 0); + SIGNAL HDE_d: std_logic_vector(11 DOWNTO 0); + SIGNAL HDE_q: std_logic_vector(11 DOWNTO 0); + SIGNAL HBB: std_logic_vector(11 DOWNTO 0); + SIGNAL HBB_d: std_logic_vector(11 DOWNTO 0); + SIGNAL HBB_q: std_logic_vector(11 DOWNTO 0); + SIGNAL HSS: std_logic_vector(11 DOWNTO 0); + SIGNAL HSS_d: std_logic_vector(11 DOWNTO 0); + SIGNAL HSS_q: std_logic_vector(11 DOWNTO 0); + SIGNAL RAND_OBEN: std_logic_vector(10 DOWNTO 0); + SIGNAL VDIS_START: std_logic_vector(10 DOWNTO 0); + SIGNAL VDIS_END: std_logic_vector(10 DOWNTO 0); + SIGNAL RAND_UNTEN: std_logic_vector(10 DOWNTO 0); + SIGNAL VS_START: std_logic_vector(10 DOWNTO 0); + SIGNAL V_TOTAL: std_logic_vector(10 DOWNTO 0); + SIGNAL VBE: std_logic_vector(10 DOWNTO 0); + SIGNAL VBE_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VBE_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VDB: std_logic_vector(10 DOWNTO 0); + SIGNAL VDB_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VDB_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VDE: std_logic_vector(10 DOWNTO 0); + SIGNAL VDE_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VDE_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VBB: std_logic_vector(10 DOWNTO 0); + SIGNAL VBB_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VBB_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VSS: std_logic_vector(10 DOWNTO 0); + SIGNAL VSS_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VSS_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VFT: std_logic_vector(10 DOWNTO 0); + SIGNAL VFT_d: std_logic_vector(10 DOWNTO 0); + SIGNAL VFT_q: std_logic_vector(10 DOWNTO 0); + SIGNAL VCO: std_logic_vector(8 DOWNTO 0); + SIGNAL VCO_d: std_logic_vector(8 DOWNTO 0); + SIGNAL VCO_ena: std_logic_vector(8 DOWNTO 0); + SIGNAL VCO_q: std_logic_vector(8 DOWNTO 0); + SIGNAL VCNTRL: std_logic_vector(3 DOWNTO 0); + SIGNAL VCNTRL_d: std_logic_vector(3 DOWNTO 0); + SIGNAL VCNTRL_q: std_logic_vector(3 DOWNTO 0); + SIGNAL u0_data: std_logic_vector(15 DOWNTO 0); + SIGNAL u0_tridata: std_logic_vector(15 DOWNTO 0); + SIGNAL u1_data: std_logic_vector(15 DOWNTO 0); + SIGNAL u1_tridata: std_logic_vector(15 DOWNTO 0); + SIGNAL ST_SHIFT_MODE0_clk_ctrl, ST_SHIFT_MODE0_ena_ctrl, + FALCON_SHIFT_MODE0_clk_ctrl, FALCON_SHIFT_MODE8_ena_ctrl, FALCON_SHIFT_MODE0_ena_ctrl, ACP_VCTR0_clk_ctrl, ACP_VCTR24_ena_ctrl, ACP_VCTR16_ena_ctrl, ACP_VCTR8_ena_ctrl, ACP_VCTR0_ena_ctrl, ATARI_HH0_clk_ctrl, ATARI_HH24_ena_ctrl, ATARI_HH16_ena_ctrl, @@ -314,25 +330,30 @@ architecture VIDEO_MOD_MUX_CLUTCTR_behav of VIDEO_MOD_MUX_CLUTCTR is -- Sub Module Interface Section - component lpm_bustri_WORD - Port ( - data: in std_logic_vector(15 downto 0); - enabledt: in std_logic; - tridata: buffer std_logic_vector(15 downto 0) + COMPONENT lpm_bustri_WORD + PORT + ( + data : IN std_logic_vector(15 DOWNTO 0); + enabledt : IN std_logic; + tridata : BUFFER std_logic_vector(15 DOWNTO 0) ); - end component; + END COMPONENT lpm_bustri_WORD; - Function to_std_logic(X: in Boolean) return Std_Logic is - variable ret : std_logic; - begin - if x then ret := '1'; else ret := '0'; end if; - return ret; - end to_std_logic; + FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS + VARIABLE ret : std_logic; + BEGIN + IF x THEN + ret := '1'; + ELSE + ret := '0'; + END IF; + RETURN ret; + END FUNCTION to_std_logic; -- sizeIt replicates a value to an array of specific length. Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is - variable rep: std_logic_vector( len-1 downto 0); + variable rep: std_logic_vector( len-1 DOWNTO 0); begin for i in rep'range loop rep(i) := a; end loop; return rep; end sizeIt; begin @@ -380,38 +401,38 @@ begin end if; end process; - BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); + BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); process (BORDER_COLOR0_clk_ctrl) begin if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then if BORDER_COLOR16_ena_ctrl='1' then (BORDER_COLOR_q(23), BORDER_COLOR_q(22), BORDER_COLOR_q(21), BORDER_COLOR_q(20), BORDER_COLOR_q(19), BORDER_COLOR_q(18), BORDER_COLOR_q(17), BORDER_COLOR_q(16)) <= BORDER_COLOR_d(23 - downto 16); + DOWNTO 16); end if; end if; end process; - BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); + BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); process (BORDER_COLOR0_clk_ctrl) begin if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then if BORDER_COLOR8_ena_ctrl='1' then (BORDER_COLOR_q(15), BORDER_COLOR_q(14), BORDER_COLOR_q(13), BORDER_COLOR_q(12), BORDER_COLOR_q(11), BORDER_COLOR_q(10), BORDER_COLOR_q(9), BORDER_COLOR_q(8)) <= BORDER_COLOR_d(15 - downto 8); + DOWNTO 8); end if; end if; end process; - BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); + BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); process (BORDER_COLOR0_clk_ctrl) begin if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then if BORDER_COLOR0_ena_ctrl='1' then (BORDER_COLOR_q(7), BORDER_COLOR_q(6), BORDER_COLOR_q(5), BORDER_COLOR_q(4), BORDER_COLOR_q(3), BORDER_COLOR_q(2), BORDER_COLOR_q(1), BORDER_COLOR_q(0)) <= BORDER_COLOR_d(7 - downto 0); + DOWNTO 0); end if; end if; end process; @@ -501,7 +522,7 @@ begin then if FALCON_SHIFT_MODE8_ena_ctrl='1' then (FALCON_SHIFT_MODE_q(10), FALCON_SHIFT_MODE_q(9), - FALCON_SHIFT_MODE_q(8)) <= FALCON_SHIFT_MODE_d(10 downto 8); + FALCON_SHIFT_MODE_q(8)) <= FALCON_SHIFT_MODE_d(10 DOWNTO 8); end if; end if; end process; @@ -514,7 +535,7 @@ begin FALCON_SHIFT_MODE_q(5), FALCON_SHIFT_MODE_q(4), FALCON_SHIFT_MODE_q(3), FALCON_SHIFT_MODE_q(2), FALCON_SHIFT_MODE_q(1), FALCON_SHIFT_MODE_q(0)) <= - FALCON_SHIFT_MODE_d(7 downto 0); + FALCON_SHIFT_MODE_d(7 DOWNTO 0); end if; end if; end process; @@ -536,7 +557,7 @@ begin if ACP_VCTR24_ena_ctrl='1' then (ACP_VCTR_q(31), ACP_VCTR_q(30), ACP_VCTR_q(29), ACP_VCTR_q(28), ACP_VCTR_q(27), ACP_VCTR_q(26), ACP_VCTR_q(25), - ACP_VCTR_q(24)) <= ACP_VCTR_d(31 downto 24); + ACP_VCTR_q(24)) <= ACP_VCTR_d(31 DOWNTO 24); end if; end if; end process; @@ -546,7 +567,7 @@ begin if ACP_VCTR16_ena_ctrl='1' then (ACP_VCTR_q(23), ACP_VCTR_q(22), ACP_VCTR_q(21), ACP_VCTR_q(20), ACP_VCTR_q(19), ACP_VCTR_q(18), ACP_VCTR_q(17), - ACP_VCTR_q(16)) <= ACP_VCTR_d(23 downto 16); + ACP_VCTR_q(16)) <= ACP_VCTR_d(23 DOWNTO 16); end if; end if; end process; @@ -556,7 +577,7 @@ begin if ACP_VCTR8_ena_ctrl='1' then (ACP_VCTR_q(15), ACP_VCTR_q(14), ACP_VCTR_q(13), ACP_VCTR_q(12), ACP_VCTR_q(11), ACP_VCTR_q(10), ACP_VCTR_q(9), ACP_VCTR_q(8)) - <= ACP_VCTR_d(15 downto 8); + <= ACP_VCTR_d(15 DOWNTO 8); end if; end if; end process; @@ -564,7 +585,7 @@ begin process (ACP_VCTR0_clk_ctrl) begin if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then if ACP_VCTR6_ena_ctrl='1' then - (ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 downto 6); + (ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 DOWNTO 6); end if; end if; end process; @@ -573,7 +594,7 @@ begin if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then if ACP_VCTR0_ena_ctrl='1' then (ACP_VCTR_q(5), ACP_VCTR_q(4), ACP_VCTR_q(3), ACP_VCTR_q(2), - ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 downto 0); + ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 DOWNTO 0); end if; end if; end process; @@ -590,7 +611,7 @@ begin if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then if LOF8_ena_ctrl='1' then (LOF_q(15), LOF_q(14), LOF_q(13), LOF_q(12), LOF_q(11), LOF_q(10), - LOF_q(9), LOF_q(8)) <= LOF_d(15 downto 8); + LOF_q(9), LOF_q(8)) <= LOF_d(15 DOWNTO 8); end if; end if; end process; @@ -599,7 +620,7 @@ begin if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then if LOF0_ena_ctrl='1' then (LOF_q(7), LOF_q(6), LOF_q(5), LOF_q(4), LOF_q(3), LOF_q(2), - LOF_q(1), LOF_q(0)) <= LOF_d(7 downto 0); + LOF_q(1), LOF_q(0)) <= LOF_d(7 DOWNTO 0); end if; end if; end process; @@ -608,7 +629,7 @@ begin if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then if LWD8_ena_ctrl='1' then (LWD_q(15), LWD_q(14), LWD_q(13), LWD_q(12), LWD_q(11), LWD_q(10), - LWD_q(9), LWD_q(8)) <= LWD_d(15 downto 8); + LWD_q(9), LWD_q(8)) <= LWD_d(15 DOWNTO 8); end if; end if; end process; @@ -617,7 +638,7 @@ begin if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then if LWD0_ena_ctrl='1' then (LWD_q(7), LWD_q(6), LWD_q(5), LWD_q(4), LWD_q(3), LWD_q(2), - LWD_q(1), LWD_q(0)) <= LWD_d(7 downto 0); + LWD_q(1), LWD_q(0)) <= LWD_d(7 DOWNTO 0); end if; end if; end process; @@ -797,7 +818,7 @@ begin if ATARI_HH24_ena_ctrl='1' then (ATARI_HH_q(31), ATARI_HH_q(30), ATARI_HH_q(29), ATARI_HH_q(28), ATARI_HH_q(27), ATARI_HH_q(26), ATARI_HH_q(25), - ATARI_HH_q(24)) <= ATARI_HH_d(31 downto 24); + ATARI_HH_q(24)) <= ATARI_HH_d(31 DOWNTO 24); end if; end if; end process; @@ -807,7 +828,7 @@ begin if ATARI_HH16_ena_ctrl='1' then (ATARI_HH_q(23), ATARI_HH_q(22), ATARI_HH_q(21), ATARI_HH_q(20), ATARI_HH_q(19), ATARI_HH_q(18), ATARI_HH_q(17), - ATARI_HH_q(16)) <= ATARI_HH_d(23 downto 16); + ATARI_HH_q(16)) <= ATARI_HH_d(23 DOWNTO 16); end if; end if; end process; @@ -817,7 +838,7 @@ begin if ATARI_HH8_ena_ctrl='1' then (ATARI_HH_q(15), ATARI_HH_q(14), ATARI_HH_q(13), ATARI_HH_q(12), ATARI_HH_q(11), ATARI_HH_q(10), ATARI_HH_q(9), ATARI_HH_q(8)) - <= ATARI_HH_d(15 downto 8); + <= ATARI_HH_d(15 DOWNTO 8); end if; end if; end process; @@ -827,7 +848,7 @@ begin if ATARI_HH0_ena_ctrl='1' then (ATARI_HH_q(7), ATARI_HH_q(6), ATARI_HH_q(5), ATARI_HH_q(4), ATARI_HH_q(3), ATARI_HH_q(2), ATARI_HH_q(1), ATARI_HH_q(0)) - <= ATARI_HH_d(7 downto 0); + <= ATARI_HH_d(7 DOWNTO 0); end if; end if; end process; @@ -837,7 +858,7 @@ begin if ATARI_VH24_ena_ctrl='1' then (ATARI_VH_q(31), ATARI_VH_q(30), ATARI_VH_q(29), ATARI_VH_q(28), ATARI_VH_q(27), ATARI_VH_q(26), ATARI_VH_q(25), - ATARI_VH_q(24)) <= ATARI_VH_d(31 downto 24); + ATARI_VH_q(24)) <= ATARI_VH_d(31 DOWNTO 24); end if; end if; end process; @@ -847,7 +868,7 @@ begin if ATARI_VH16_ena_ctrl='1' then (ATARI_VH_q(23), ATARI_VH_q(22), ATARI_VH_q(21), ATARI_VH_q(20), ATARI_VH_q(19), ATARI_VH_q(18), ATARI_VH_q(17), - ATARI_VH_q(16)) <= ATARI_VH_d(23 downto 16); + ATARI_VH_q(16)) <= ATARI_VH_d(23 DOWNTO 16); end if; end if; end process; @@ -857,7 +878,7 @@ begin if ATARI_VH8_ena_ctrl='1' then (ATARI_VH_q(15), ATARI_VH_q(14), ATARI_VH_q(13), ATARI_VH_q(12), ATARI_VH_q(11), ATARI_VH_q(10), ATARI_VH_q(9), ATARI_VH_q(8)) - <= ATARI_VH_d(15 downto 8); + <= ATARI_VH_d(15 DOWNTO 8); end if; end if; end process; @@ -867,7 +888,7 @@ begin if ATARI_VH0_ena_ctrl='1' then (ATARI_VH_q(7), ATARI_VH_q(6), ATARI_VH_q(5), ATARI_VH_q(4), ATARI_VH_q(3), ATARI_VH_q(2), ATARI_VH_q(1), ATARI_VH_q(0)) - <= ATARI_VH_d(7 downto 0); + <= ATARI_VH_d(7 DOWNTO 0); end if; end if; end process; @@ -877,7 +898,7 @@ begin if ATARI_HL24_ena_ctrl='1' then (ATARI_HL_q(31), ATARI_HL_q(30), ATARI_HL_q(29), ATARI_HL_q(28), ATARI_HL_q(27), ATARI_HL_q(26), ATARI_HL_q(25), - ATARI_HL_q(24)) <= ATARI_HL_d(31 downto 24); + ATARI_HL_q(24)) <= ATARI_HL_d(31 DOWNTO 24); end if; end if; end process; @@ -887,7 +908,7 @@ begin if ATARI_HL16_ena_ctrl='1' then (ATARI_HL_q(23), ATARI_HL_q(22), ATARI_HL_q(21), ATARI_HL_q(20), ATARI_HL_q(19), ATARI_HL_q(18), ATARI_HL_q(17), - ATARI_HL_q(16)) <= ATARI_HL_d(23 downto 16); + ATARI_HL_q(16)) <= ATARI_HL_d(23 DOWNTO 16); end if; end if; end process; @@ -897,7 +918,7 @@ begin if ATARI_HL8_ena_ctrl='1' then (ATARI_HL_q(15), ATARI_HL_q(14), ATARI_HL_q(13), ATARI_HL_q(12), ATARI_HL_q(11), ATARI_HL_q(10), ATARI_HL_q(9), ATARI_HL_q(8)) - <= ATARI_HL_d(15 downto 8); + <= ATARI_HL_d(15 DOWNTO 8); end if; end if; end process; @@ -907,7 +928,7 @@ begin if ATARI_HL0_ena_ctrl='1' then (ATARI_HL_q(7), ATARI_HL_q(6), ATARI_HL_q(5), ATARI_HL_q(4), ATARI_HL_q(3), ATARI_HL_q(2), ATARI_HL_q(1), ATARI_HL_q(0)) - <= ATARI_HL_d(7 downto 0); + <= ATARI_HL_d(7 DOWNTO 0); end if; end if; end process; @@ -917,7 +938,7 @@ begin if ATARI_VL24_ena_ctrl='1' then (ATARI_VL_q(31), ATARI_VL_q(30), ATARI_VL_q(29), ATARI_VL_q(28), ATARI_VL_q(27), ATARI_VL_q(26), ATARI_VL_q(25), - ATARI_VL_q(24)) <= ATARI_VL_d(31 downto 24); + ATARI_VL_q(24)) <= ATARI_VL_d(31 DOWNTO 24); end if; end if; end process; @@ -927,7 +948,7 @@ begin if ATARI_VL16_ena_ctrl='1' then (ATARI_VL_q(23), ATARI_VL_q(22), ATARI_VL_q(21), ATARI_VL_q(20), ATARI_VL_q(19), ATARI_VL_q(18), ATARI_VL_q(17), - ATARI_VL_q(16)) <= ATARI_VL_d(23 downto 16); + ATARI_VL_q(16)) <= ATARI_VL_d(23 DOWNTO 16); end if; end if; end process; @@ -937,7 +958,7 @@ begin if ATARI_VL8_ena_ctrl='1' then (ATARI_VL_q(15), ATARI_VL_q(14), ATARI_VL_q(13), ATARI_VL_q(12), ATARI_VL_q(11), ATARI_VL_q(10), ATARI_VL_q(9), ATARI_VL_q(8)) - <= ATARI_VL_d(15 downto 8); + <= ATARI_VL_d(15 DOWNTO 8); end if; end if; end process; @@ -947,7 +968,7 @@ begin if ATARI_VL0_ena_ctrl='1' then (ATARI_VL_q(7), ATARI_VL_q(6), ATARI_VL_q(5), ATARI_VL_q(4), ATARI_VL_q(3), ATARI_VL_q(2), ATARI_VL_q(1), ATARI_VL_q(0)) - <= ATARI_VL_d(7 downto 0); + <= ATARI_VL_d(7 DOWNTO 0); end if; end if; end process; @@ -955,7 +976,7 @@ begin process (HHT0_clk_ctrl) begin if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then if HHT8_ena_ctrl='1' then - (HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 downto 8); + (HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 DOWNTO 8); end if; end if; end process; @@ -964,7 +985,7 @@ begin if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then if HHT0_ena_ctrl='1' then (HHT_q(7), HHT_q(6), HHT_q(5), HHT_q(4), HHT_q(3), HHT_q(2), - HHT_q(1), HHT_q(0)) <= HHT_d(7 downto 0); + HHT_q(1), HHT_q(0)) <= HHT_d(7 DOWNTO 0); end if; end if; end process; @@ -972,7 +993,7 @@ begin process (HBE0_clk_ctrl) begin if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then if HBE8_ena_ctrl='1' then - (HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 downto 8); + (HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 DOWNTO 8); end if; end if; end process; @@ -981,7 +1002,7 @@ begin if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then if HBE0_ena_ctrl='1' then (HBE_q(7), HBE_q(6), HBE_q(5), HBE_q(4), HBE_q(3), HBE_q(2), - HBE_q(1), HBE_q(0)) <= HBE_d(7 downto 0); + HBE_q(1), HBE_q(0)) <= HBE_d(7 DOWNTO 0); end if; end if; end process; @@ -989,7 +1010,7 @@ begin process (HDB0_clk_ctrl) begin if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then if HDB8_ena_ctrl='1' then - (HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 downto 8); + (HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 DOWNTO 8); end if; end if; end process; @@ -998,7 +1019,7 @@ begin if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then if HDB0_ena_ctrl='1' then (HDB_q(7), HDB_q(6), HDB_q(5), HDB_q(4), HDB_q(3), HDB_q(2), - HDB_q(1), HDB_q(0)) <= HDB_d(7 downto 0); + HDB_q(1), HDB_q(0)) <= HDB_d(7 DOWNTO 0); end if; end if; end process; @@ -1006,7 +1027,7 @@ begin process (HDE0_clk_ctrl) begin if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then if HDE8_ena_ctrl='1' then - (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 downto 8); + (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 DOWNTO 8); end if; end if; end process; @@ -1015,7 +1036,7 @@ begin if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then if HDE0_ena_ctrl='1' then (HDE_q(7), HDE_q(6), HDE_q(5), HDE_q(4), HDE_q(3), HDE_q(2), - HDE_q(1), HDE_q(0)) <= HDE_d(7 downto 0); + HDE_q(1), HDE_q(0)) <= HDE_d(7 DOWNTO 0); end if; end if; end process; @@ -1023,7 +1044,7 @@ begin process (HBB0_clk_ctrl) begin if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then if HBB8_ena_ctrl='1' then - (HBB_q(11), HBB_q(10), HBB_q(9), HBB_q(8)) <= HBB_d(11 downto 8); + (HBB_q(11), HBB_q(10), HBB_q(9), HBB_q(8)) <= HBB_d(11 DOWNTO 8); end if; end if; end process; @@ -1032,7 +1053,7 @@ begin if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then if HBB0_ena_ctrl='1' then (HBB_q(7), HBB_q(6), HBB_q(5), HBB_q(4), HBB_q(3), HBB_q(2), - HBB_q(1), HBB_q(0)) <= HBB_d(7 downto 0); + HBB_q(1), HBB_q(0)) <= HBB_d(7 DOWNTO 0); end if; end if; end process; @@ -1040,7 +1061,7 @@ begin process (HSS0_clk_ctrl) begin if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then if HSS8_ena_ctrl='1' then - (HSS_q(11), HSS_q(10), HSS_q(9), HSS_q(8)) <= HSS_d(11 downto 8); + (HSS_q(11), HSS_q(10), HSS_q(9), HSS_q(8)) <= HSS_d(11 DOWNTO 8); end if; end if; end process; @@ -1049,7 +1070,7 @@ begin if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then if HSS0_ena_ctrl='1' then (HSS_q(7), HSS_q(6), HSS_q(5), HSS_q(4), HSS_q(3), HSS_q(2), - HSS_q(1), HSS_q(0)) <= HSS_d(7 downto 0); + HSS_q(1), HSS_q(0)) <= HSS_d(7 DOWNTO 0); end if; end if; end process; @@ -1063,7 +1084,7 @@ begin process (VBE0_clk_ctrl) begin if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then if VBE8_ena_ctrl='1' then - (VBE_q(10), VBE_q(9), VBE_q(8)) <= VBE_d(10 downto 8); + (VBE_q(10), VBE_q(9), VBE_q(8)) <= VBE_d(10 DOWNTO 8); end if; end if; end process; @@ -1072,7 +1093,7 @@ begin if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then if VBE0_ena_ctrl='1' then (VBE_q(7), VBE_q(6), VBE_q(5), VBE_q(4), VBE_q(3), VBE_q(2), - VBE_q(1), VBE_q(0)) <= VBE_d(7 downto 0); + VBE_q(1), VBE_q(0)) <= VBE_d(7 DOWNTO 0); end if; end if; end process; @@ -1080,7 +1101,7 @@ begin process (VDB0_clk_ctrl) begin if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then if VDB8_ena_ctrl='1' then - (VDB_q(10), VDB_q(9), VDB_q(8)) <= VDB_d(10 downto 8); + (VDB_q(10), VDB_q(9), VDB_q(8)) <= VDB_d(10 DOWNTO 8); end if; end if; end process; @@ -1089,7 +1110,7 @@ begin if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then if VDB0_ena_ctrl='1' then (VDB_q(7), VDB_q(6), VDB_q(5), VDB_q(4), VDB_q(3), VDB_q(2), - VDB_q(1), VDB_q(0)) <= VDB_d(7 downto 0); + VDB_q(1), VDB_q(0)) <= VDB_d(7 DOWNTO 0); end if; end if; end process; @@ -1097,7 +1118,7 @@ begin process (VDE0_clk_ctrl) begin if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then if VDE8_ena_ctrl='1' then - (VDE_q(10), VDE_q(9), VDE_q(8)) <= VDE_d(10 downto 8); + (VDE_q(10), VDE_q(9), VDE_q(8)) <= VDE_d(10 DOWNTO 8); end if; end if; end process; @@ -1106,7 +1127,7 @@ begin if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then if VDE0_ena_ctrl='1' then (VDE_q(7), VDE_q(6), VDE_q(5), VDE_q(4), VDE_q(3), VDE_q(2), - VDE_q(1), VDE_q(0)) <= VDE_d(7 downto 0); + VDE_q(1), VDE_q(0)) <= VDE_d(7 DOWNTO 0); end if; end if; end process; @@ -1114,7 +1135,7 @@ begin process (VBB0_clk_ctrl) begin if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then if VBB8_ena_ctrl='1' then - (VBB_q(10), VBB_q(9), VBB_q(8)) <= VBB_d(10 downto 8); + (VBB_q(10), VBB_q(9), VBB_q(8)) <= VBB_d(10 DOWNTO 8); end if; end if; end process; @@ -1123,7 +1144,7 @@ begin if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then if VBB0_ena_ctrl='1' then (VBB_q(7), VBB_q(6), VBB_q(5), VBB_q(4), VBB_q(3), VBB_q(2), - VBB_q(1), VBB_q(0)) <= VBB_d(7 downto 0); + VBB_q(1), VBB_q(0)) <= VBB_d(7 DOWNTO 0); end if; end if; end process; @@ -1131,7 +1152,7 @@ begin process (VSS0_clk_ctrl) begin if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then if VSS8_ena_ctrl='1' then - (VSS_q(10), VSS_q(9), VSS_q(8)) <= VSS_d(10 downto 8); + (VSS_q(10), VSS_q(9), VSS_q(8)) <= VSS_d(10 DOWNTO 8); end if; end if; end process; @@ -1140,7 +1161,7 @@ begin if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then if VSS0_ena_ctrl='1' then (VSS_q(7), VSS_q(6), VSS_q(5), VSS_q(4), VSS_q(3), VSS_q(2), - VSS_q(1), VSS_q(0)) <= VSS_d(7 downto 0); + VSS_q(1), VSS_q(0)) <= VSS_d(7 DOWNTO 0); end if; end if; end process; @@ -1148,7 +1169,7 @@ begin process (VFT0_clk_ctrl) begin if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then if VFT8_ena_ctrl='1' then - (VFT_q(10), VFT_q(9), VFT_q(8)) <= VFT_d(10 downto 8); + (VFT_q(10), VFT_q(9), VFT_q(8)) <= VFT_d(10 DOWNTO 8); end if; end if; end process; @@ -1157,7 +1178,7 @@ begin if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then if VFT0_ena_ctrl='1' then (VFT_q(7), VFT_q(6), VFT_q(5), VFT_q(4), VFT_q(3), VFT_q(2), - VFT_q(1), VFT_q(0)) <= VFT_d(7 downto 0); + VFT_q(1), VFT_q(0)) <= VFT_d(7 DOWNTO 0); end if; end if; end process; @@ -1174,7 +1195,7 @@ begin if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then if VCO0_ena_ctrl='1' then (VCO_q(7), VCO_q(6), VCO_q(5), VCO_q(4), VCO_q(3), VCO_q(2), - VCO_q(1), VCO_q(0)) <= VCO_d(7 downto 0); + VCO_q(1), VCO_q(0)) <= VCO_d(7 DOWNTO 0); end if; end if; end process; @@ -1191,24 +1212,24 @@ begin -- BYT SELECT 32 BIT -- ADR==0 - FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00"); + FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00"); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not + FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and + FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not + FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); @@ -1223,7 +1244,7 @@ begin -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 10) = + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = "000000000000000000"); ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); @@ -1233,7 +1254,7 @@ begin -- FALCON CLUT -- -- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 10) + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 10) = "1111100110"); -- HIGH WORD @@ -1241,16 +1262,16 @@ begin -- LOW WORD FALCON_CLUT_RDL <= FALCON_CLUT_CS and (not nFB_OE) and FB_ADR(1); - FALCON_CLUT_WR(1 downto 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & + FALCON_CLUT_WR(1 DOWNTO 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & (not FB_ADR(1))) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - FALCON_CLUT_WR(3 downto 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & + FALCON_CLUT_WR(3 DOWNTO 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); -- ST CLUT -- -- $F8240/$20 - ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 5) = + ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 5) = "111110000010010"); ST_CLUT_RD <= ST_CLUT_CS and (not nFB_OE); ST_CLUT_WR <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and @@ -1260,9 +1281,9 @@ begin ST_SHIFT_MODE0_clk_ctrl <= MAIN_CLK; -- $F8260/2 - ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) + ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100110000"); - ST_SHIFT_MODE_d <= FB_AD(25 downto 24); + ST_SHIFT_MODE_d <= FB_AD(25 DOWNTO 24); ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); -- MONO @@ -1282,13 +1303,13 @@ begin -- $F8266/2 FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 - downto 1) = "1111100000100110011"); - FALCON_SHIFT_MODE_d <= FB_AD(26 downto 16); + DOWNTO 1) = "1111100000100110011"); + FALCON_SHIFT_MODE_d <= FB_AD(26 DOWNTO 16); FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(2); FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); - CLUT_OFF <= FALCON_SHIFT_MODE_q(3 downto 0) and sizeIt(COLOR4,4); + CLUT_OFF <= FALCON_SHIFT_MODE_q(3 DOWNTO 0) and sizeIt(COLOR4,4); COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and @@ -1314,10 +1335,10 @@ begin ACP_VCTR0_clk_ctrl <= MAIN_CLK; -- $400/4 - ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000000"); - ACP_VCTR_d(31 downto 8) <= FB_AD(31 downto 8); - ACP_VCTR_d(5 downto 0) <= FB_AD(5 downto 0); + ACP_VCTR_d(31 DOWNTO 8) <= FB_AD(31 DOWNTO 8); + ACP_VCTR_d(5 DOWNTO 0) <= FB_AD(5 DOWNTO 0); ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); @@ -1333,7 +1354,7 @@ begin ATARI_HH0_clk_ctrl <= MAIN_CLK; -- $410/4 - ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000100"); ATARI_HH_d <= FB_AD; ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); @@ -1345,7 +1366,7 @@ begin ATARI_VH0_clk_ctrl <= MAIN_CLK; -- $414/4 - ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000101"); ATARI_VH_d <= FB_AD; ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); @@ -1357,7 +1378,7 @@ begin ATARI_HL0_clk_ctrl <= MAIN_CLK; -- $418/4 - ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000110"); ATARI_HL_d <= FB_AD; ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); @@ -1369,7 +1390,7 @@ begin ATARI_VL0_clk_ctrl <= MAIN_CLK; -- $41C/4 - ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = + ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000111"); ATARI_VL_d <= FB_AD; ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); @@ -1379,7 +1400,7 @@ begin -- VIDEO PLL CONFIG -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto + VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 9) = "0000000000000000011") and FB_B(0) and FB_B(1); VR_WR_clk <= MAIN_CLK; VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not @@ -1389,20 +1410,20 @@ begin VR_DOUT0_ena_ctrl <= not VR_BUSY; VR_DOUT_d <= VR_D; VR_FRQ0_clk_ctrl <= MAIN_CLK; - VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = + VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 DOWNTO 0) = "000000100"); - VR_FRQ_d <= FB_AD(23 downto 16); + VR_FRQ_d <= FB_AD(23 DOWNTO 16); -- VIDEO PLL RECONFIG -- $(F)000'0800 VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 - downto 0) = "0000000000000000100000000000") and FB_B(0); + DOWNTO 0) = "0000000000000000100000000000") and FB_B(0); VIDEO_RECONFIG_clk <= MAIN_CLK; VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); -- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR <= ACP_VCTR_q(31 downto 16); + VIDEO_RAM_CTR <= ACP_VCTR_q(31 DOWNTO 16); -- ------------ COLOR MODE IM ACP SETZEN COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) @@ -1438,9 +1459,9 @@ begin BORDER_COLOR0_clk_ctrl <= MAIN_CLK; -- $404/4 - BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) + BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001"); - BORDER_COLOR_d <= FB_AD(23 downto 0); + BORDER_COLOR_d <= FB_AD(23 DOWNTO 0); BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); @@ -1468,156 +1489,156 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000000000011"); SYS_CTR0_clk_ctrl <= MAIN_CLK; - SYS_CTR_d <= FB_AD(22 downto 16); + SYS_CTR_d <= FB_AD(22 DOWNTO 16); SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); BLITTER_ON <= not SYS_CTR_q(3); -- LOF -- $820E/2 - LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000111"); LOF0_clk_ctrl <= MAIN_CLK; - LOF_d <= FB_AD(31 downto 16); + LOF_d <= FB_AD(31 DOWNTO 16); LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); -- LWD -- $8210/2 - LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100001000"); LWD0_clk_ctrl <= MAIN_CLK; - LWD_d <= FB_AD(31 downto 16); + LWD_d <= FB_AD(31 DOWNTO 16); LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); -- HORIZONTAL -- HHT -- $8282/2 - HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000001"); HHT0_clk_ctrl <= MAIN_CLK; - HHT_d <= FB_AD(27 downto 16); + HHT_d <= FB_AD(27 DOWNTO 16); HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); -- HBE -- $8286/2 - HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000011"); HBE0_clk_ctrl <= MAIN_CLK; - HBE_d <= FB_AD(27 downto 16); + HBE_d <= FB_AD(27 DOWNTO 16); HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); -- HDB -- $8288/2 - HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000100"); HDB0_clk_ctrl <= MAIN_CLK; - HDB_d <= FB_AD(27 downto 16); + HDB_d <= FB_AD(27 DOWNTO 16); HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); -- HDE -- $828A/2 - HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000101"); HDE0_clk_ctrl <= MAIN_CLK; - HDE_d <= FB_AD(27 downto 16); + HDE_d <= FB_AD(27 DOWNTO 16); HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); -- HBB -- $8284/2 - HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000010"); HBB0_clk_ctrl <= MAIN_CLK; - HBB_d <= FB_AD(27 downto 16); + HBB_d <= FB_AD(27 DOWNTO 16); HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); -- HSS -- Videl HSYNC start register $828C / 2 - HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000110"); HSS0_clk_ctrl <= MAIN_CLK; - HSS_d <= FB_AD(27 downto 16); + HSS_d <= FB_AD(27 DOWNTO 16); HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); -- VERTIKAL -- VBE -- $82A6/2 - VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010011"); VBE0_clk_ctrl <= MAIN_CLK; - VBE_d <= FB_AD(26 downto 16); + VBE_d <= FB_AD(26 DOWNTO 16); VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); -- VDB -- $82A8/2 - VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010100"); VDB0_clk_ctrl <= MAIN_CLK; - VDB_d <= FB_AD(26 downto 16); + VDB_d <= FB_AD(26 DOWNTO 16); VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); -- VDE -- $82AA/2 - VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010101"); VDE0_clk_ctrl <= MAIN_CLK; - VDE_d <= FB_AD(26 downto 16); + VDE_d <= FB_AD(26 DOWNTO 16); VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); -- VBB -- $82A4/2 - VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010010"); VBB0_clk_ctrl <= MAIN_CLK; - VBB_d <= FB_AD(26 downto 16); + VBB_d <= FB_AD(26 DOWNTO 16); VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); -- VSS -- $82AC/2 - VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010110"); VSS0_clk_ctrl <= MAIN_CLK; - VSS_d <= FB_AD(26 downto 16); + VSS_d <= FB_AD(26 DOWNTO 16); VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); -- VFT -- $82A2/2 - VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010001"); VFT0_clk_ctrl <= MAIN_CLK; - VFT_d <= FB_AD(26 downto 16); + VFT_d <= FB_AD(26 DOWNTO 16); VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); -- VCO -- $82C0 / 2 Falcon clock control register VCO - VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100000"); VCO0_clk_ctrl <= MAIN_CLK; - VCO_d <= FB_AD(24 downto 16); + VCO_d <= FB_AD(24 DOWNTO 16); VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL - VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = + VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100001"); VCNTRL0_clk_ctrl <= MAIN_CLK; - VCNTRL_d <= FB_AD(19 downto 16); + VCNTRL_d <= FB_AD(19 DOWNTO 16); VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); -- - REGISTER OUT @@ -1626,7 +1647,7 @@ begin ST_SHIFT_MODE_q & "00000000")) or (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 - downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or + DOWNTO 4) & (not BLITTER_RUN) & SYS_CTR_q(2 DOWNTO 0))) or (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or @@ -1642,13 +1663,13 @@ begin (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & - VCNTRL_q)) or (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or + VCNTRL_q)) or (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 DOWNTO 16)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 DOWNTO 16)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 DOWNTO 16)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 DOWNTO 16)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 DOWNTO 16)) or (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & - BORDER_COLOR_q(23 downto 16))) or (sizeIt(VIDEO_PLL_CONFIG_CS,16) and + BORDER_COLOR_q(23 DOWNTO 16))) or (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); @@ -1658,18 +1679,18 @@ begin or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); - FB_AD(31 downto 16) <= u0_tridata; + FB_AD(31 DOWNTO 16) <= u0_tridata; -- high word register access - u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or - (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); + u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 DOWNTO 0)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 DOWNTO 0)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 DOWNTO 0)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 DOWNTO 0)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 DOWNTO 0)) or + (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 DOWNTO 0)); u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); - FB_AD(15 downto 0) <= u1_tridata; + FB_AD(15 DOWNTO 0) <= u1_tridata; VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or @@ -1693,9 +1714,9 @@ begin (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) - or (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto + or (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "00")) or (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and - ACP_VCTR_q(9 downto 8) = "01")) or (CLK_VIDEO and ACP_VIDEO_ON and + ACP_VCTR_q(9 DOWNTO 8) = "01")) or (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); -- ------------------------------------------------------------ @@ -1722,10 +1743,10 @@ begin ("00100000" and sizeIt(not ACP_VIDEO_ON,8) and (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and sizeIt(not VCNTRL_q(2),8) and sizeIt(not VCO_q(2),8) and sizeIt(not VCO_q(0),8)) or ("00011100" and - sizeIt(ACP_VIDEO_ON,8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) + sizeIt(ACP_VIDEO_ON,8) and sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "00"),8)) or ("00100000" and sizeIt(ACP_VIDEO_ON,8) and - sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "01"),8)) or - ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON,8) and sizeIt(ACP_VCTR_q(9),8)); + sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "01"),8)) or + ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 DOWNTO 1))))) and sizeIt(ACP_VIDEO_ON,8) and sizeIt(ACP_VCTR_q(9),8)); -- MULTIPLIKATIONS FAKTOR MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or @@ -1798,33 +1819,33 @@ begin -- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not + (std_logic_vector'('0' & VBE_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or - (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not + (std_logic_vector'('0' & VDE_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 downto 0) + VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 DOWNTO 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 downto 0) and sizeIt(not + sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 DOWNTO 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and + VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 downto 16) + V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 DOWNTO 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 downto 16) and sizeIt(not + sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 DOWNTO 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and + VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); -- ZÄHLER @@ -1991,16 +2012,16 @@ begin -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or - (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or - (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and COLOR4) or - (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and COLOR8) or - (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and COLOR16) or - (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and + (to_std_logic(SUB_PIXEL_CNT_q(5 DOWNTO 0) = "000001") and COLOR2) or + (to_std_logic(SUB_PIXEL_CNT_q(4 DOWNTO 0) = "00001") and COLOR4) or + (to_std_logic(SUB_PIXEL_CNT_q(3 DOWNTO 0) = "0001") and COLOR8) or + (to_std_logic(SUB_PIXEL_CNT_q(2 DOWNTO 0) = "001") and COLOR16) or + (to_std_logic(SUB_PIXEL_CNT_q(1 DOWNTO 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 downto 0); + CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; @@ -2012,6 +2033,6 @@ begin COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; COLOR8 <= COLOR8_1 or COLOR8_2; --- Define power signal(s) +-- Define power SIGNAL(s) gnd <= '0'; -end VIDEO_MOD_MUX_CLUTCTR_behav; +END ARCHITECTURE rtl; From 97a48bf6368b2bea5f103370459b61b71af4782f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 15:04:24 +0000 Subject: [PATCH 059/127] reactivated delay chain --- FPGA_Quartus_13.1/Video/video.vhd | 8 +- .../Video/video_mod_mux_clutctr.vhd | 364 ++++++++++-------- FPGA_Quartus_13.1/firebee1.vhd | 2 +- 3 files changed, 200 insertions(+), 174 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 65b5ec3..59fa7b3 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -17,7 +17,7 @@ -- CREATED "Mon Jan 11 09:20:56 2016" LIBRARY ieee; -USE ieee.std_logic_1164.all; + USE ieee.std_logic_1164.all; LIBRARY work; @@ -1929,7 +1929,7 @@ BEGIN PORT MAP ( wren_a => ST_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_55, + wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), @@ -1945,7 +1945,7 @@ BEGIN PORT MAP ( wren_a => ST_CLUT_WR(1), - wren_b => SYNTHESIZED_WIRE_56, + wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), @@ -1961,7 +1961,7 @@ BEGIN PORT MAP ( wren_a => ST_CLUT_WR(0), - wren_b => SYNTHESIZED_WIRE_57, + wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index e809ac6..be83692 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -124,161 +124,185 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS -- VERTIKAL TIMING 320x240 -- HORIZONTAL -- VERTIKAL - SIGNAL VR_DOUT: std_logic_vector(8 DOWNTO 0); - SIGNAL VR_DOUT_d: std_logic_vector(8 DOWNTO 0); - SIGNAL VR_DOUT_q: std_logic_vector(8 DOWNTO 0); - SIGNAL VR_FRQ: std_logic_vector(7 DOWNTO 0); - SIGNAL VR_FRQ_d: std_logic_vector(7 DOWNTO 0); - SIGNAL VR_FRQ_q: std_logic_vector(7 DOWNTO 0); - SIGNAL FB_B: std_logic_vector(3 DOWNTO 0); - SIGNAL FB_16B: std_logic_vector(1 DOWNTO 0); - SIGNAL ST_SHIFT_MODE: std_logic_vector(1 DOWNTO 0); - SIGNAL ST_SHIFT_MODE_d: std_logic_vector(1 DOWNTO 0); - SIGNAL ST_SHIFT_MODE_q: std_logic_vector(1 DOWNTO 0); - SIGNAL FALCON_SHIFT_MODE: std_logic_vector(10 DOWNTO 0); - SIGNAL FALCON_SHIFT_MODE_d: std_logic_vector(10 DOWNTO 0); - SIGNAL FALCON_SHIFT_MODE_q: std_logic_vector(10 DOWNTO 0); - SIGNAL CLUT_MUX_ADR_d: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_ADR_q: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV1: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV1_d: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV1_q: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV0: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV0_d: std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV0_q: std_logic_vector(3 DOWNTO 0); - SIGNAL ACP_VCTR: std_logic_vector(31 DOWNTO 0); - SIGNAL ACP_VCTR_d: std_logic_vector(31 DOWNTO 0); - SIGNAL ACP_VCTR_q: std_logic_vector(31 DOWNTO 0); - SIGNAL BORDER_COLOR_d: std_logic_vector(23 DOWNTO 0); - SIGNAL BORDER_COLOR_q: std_logic_vector(23 DOWNTO 0); - SIGNAL SYS_CTR: std_logic_vector(6 DOWNTO 0); - SIGNAL SYS_CTR_d: std_logic_vector(6 DOWNTO 0); - SIGNAL SYS_CTR_q: std_logic_vector(6 DOWNTO 0); - SIGNAL LOF: std_logic_vector(15 DOWNTO 0); - SIGNAL LOF_d: std_logic_vector(15 DOWNTO 0); - SIGNAL LOF_q: std_logic_vector(15 DOWNTO 0); - SIGNAL LWD: std_logic_vector(15 DOWNTO 0); - SIGNAL LWD_d: std_logic_vector(15 DOWNTO 0); - SIGNAL LWD_q: std_logic_vector(15 DOWNTO 0); - SIGNAL HSYNC_I: std_logic_vector(7 DOWNTO 0); - SIGNAL HSYNC_I_d: std_logic_vector(7 DOWNTO 0); - SIGNAL HSYNC_I_q: std_logic_vector(7 DOWNTO 0); - SIGNAL HSY_LEN: std_logic_vector(7 DOWNTO 0); - SIGNAL HSY_LEN_d: std_logic_vector(7 DOWNTO 0); - SIGNAL HSY_LEN_q: std_logic_vector(7 DOWNTO 0); - SIGNAL VSYNC_I: std_logic_vector(2 DOWNTO 0); - SIGNAL VSYNC_I_d: std_logic_vector(2 DOWNTO 0); - SIGNAL VSYNC_I_q: std_logic_vector(2 DOWNTO 0); - SIGNAL VHCNT: std_logic_vector(11 DOWNTO 0); - SIGNAL VHCNT_d: std_logic_vector(11 DOWNTO 0); - SIGNAL VHCNT_q: std_logic_vector(11 DOWNTO 0); - SIGNAL SUB_PIXEL_CNT: std_logic_vector(6 DOWNTO 0); - SIGNAL SUB_PIXEL_CNT_d: std_logic_vector(6 DOWNTO 0); - SIGNAL SUB_PIXEL_CNT_q: std_logic_vector(6 DOWNTO 0); - SIGNAL VVCNT: std_logic_vector(10 DOWNTO 0); - SIGNAL VVCNT_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VVCNT_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VERZ2: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ2_d: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ2_q: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ1: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ1_d: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ1_q: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ0: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ0_d: std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ0_q: std_logic_vector(9 DOWNTO 0); - SIGNAL RAND: std_logic_vector(6 DOWNTO 0); - SIGNAL RAND_d: std_logic_vector(6 DOWNTO 0); - SIGNAL RAND_q: std_logic_vector(6 DOWNTO 0); - SIGNAL CCSEL_d: std_logic_vector(2 DOWNTO 0); - SIGNAL CCSEL_q: std_logic_vector(2 DOWNTO 0); - SIGNAL ATARI_HH: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HH_d: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HH_q: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VH: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VH_d: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VH_q: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL_d: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL_q: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VL: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VL_d: std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VL_q: std_logic_vector(31 DOWNTO 0); - SIGNAL RAND_LINKS: std_logic_vector(11 DOWNTO 0); - SIGNAL HDIS_START: std_logic_vector(11 DOWNTO 0); - SIGNAL HDIS_END: std_logic_vector(11 DOWNTO 0); - SIGNAL RAND_RECHTS: std_logic_vector(11 DOWNTO 0); - SIGNAL HS_START: std_logic_vector(11 DOWNTO 0); - SIGNAL H_TOTAL: std_logic_vector(11 DOWNTO 0); - SIGNAL HDIS_LEN: std_logic_vector(11 DOWNTO 0); - SIGNAL MULF: std_logic_vector(5 DOWNTO 0); - SIGNAL HHT: std_logic_vector(11 DOWNTO 0); - SIGNAL HHT_d: std_logic_vector(11 DOWNTO 0); - SIGNAL HHT_q: std_logic_vector(11 DOWNTO 0); - SIGNAL HBE: std_logic_vector(11 DOWNTO 0); - SIGNAL HBE_d: std_logic_vector(11 DOWNTO 0); - SIGNAL HBE_q: std_logic_vector(11 DOWNTO 0); - SIGNAL HDB: std_logic_vector(11 DOWNTO 0); - SIGNAL HDB_d: std_logic_vector(11 DOWNTO 0); - SIGNAL HDB_q: std_logic_vector(11 DOWNTO 0); - SIGNAL HDE: std_logic_vector(11 DOWNTO 0); - SIGNAL HDE_d: std_logic_vector(11 DOWNTO 0); - SIGNAL HDE_q: std_logic_vector(11 DOWNTO 0); - SIGNAL HBB: std_logic_vector(11 DOWNTO 0); - SIGNAL HBB_d: std_logic_vector(11 DOWNTO 0); - SIGNAL HBB_q: std_logic_vector(11 DOWNTO 0); - SIGNAL HSS: std_logic_vector(11 DOWNTO 0); - SIGNAL HSS_d: std_logic_vector(11 DOWNTO 0); - SIGNAL HSS_q: std_logic_vector(11 DOWNTO 0); - SIGNAL RAND_OBEN: std_logic_vector(10 DOWNTO 0); - SIGNAL VDIS_START: std_logic_vector(10 DOWNTO 0); - SIGNAL VDIS_END: std_logic_vector(10 DOWNTO 0); - SIGNAL RAND_UNTEN: std_logic_vector(10 DOWNTO 0); - SIGNAL VS_START: std_logic_vector(10 DOWNTO 0); - SIGNAL V_TOTAL: std_logic_vector(10 DOWNTO 0); - SIGNAL VBE: std_logic_vector(10 DOWNTO 0); - SIGNAL VBE_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VBE_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VDB: std_logic_vector(10 DOWNTO 0); - SIGNAL VDB_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VDB_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VDE: std_logic_vector(10 DOWNTO 0); - SIGNAL VDE_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VDE_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VBB: std_logic_vector(10 DOWNTO 0); - SIGNAL VBB_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VBB_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VSS: std_logic_vector(10 DOWNTO 0); - SIGNAL VSS_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VSS_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VFT: std_logic_vector(10 DOWNTO 0); - SIGNAL VFT_d: std_logic_vector(10 DOWNTO 0); - SIGNAL VFT_q: std_logic_vector(10 DOWNTO 0); - SIGNAL VCO: std_logic_vector(8 DOWNTO 0); - SIGNAL VCO_d: std_logic_vector(8 DOWNTO 0); - SIGNAL VCO_ena: std_logic_vector(8 DOWNTO 0); - SIGNAL VCO_q: std_logic_vector(8 DOWNTO 0); - SIGNAL VCNTRL: std_logic_vector(3 DOWNTO 0); - SIGNAL VCNTRL_d: std_logic_vector(3 DOWNTO 0); - SIGNAL VCNTRL_q: std_logic_vector(3 DOWNTO 0); - SIGNAL u0_data: std_logic_vector(15 DOWNTO 0); - SIGNAL u0_tridata: std_logic_vector(15 DOWNTO 0); - SIGNAL u1_data: std_logic_vector(15 DOWNTO 0); - SIGNAL u1_tridata: std_logic_vector(15 DOWNTO 0); - SIGNAL ST_SHIFT_MODE0_clk_ctrl, ST_SHIFT_MODE0_ena_ctrl, - FALCON_SHIFT_MODE0_clk_ctrl, FALCON_SHIFT_MODE8_ena_ctrl, - FALCON_SHIFT_MODE0_ena_ctrl, ACP_VCTR0_clk_ctrl, ACP_VCTR24_ena_ctrl, - ACP_VCTR16_ena_ctrl, ACP_VCTR8_ena_ctrl, ACP_VCTR0_ena_ctrl, - ATARI_HH0_clk_ctrl, ATARI_HH24_ena_ctrl, ATARI_HH16_ena_ctrl, - ATARI_HH8_ena_ctrl, ATARI_HH0_ena_ctrl, ATARI_VH0_clk_ctrl, - ATARI_VH24_ena_ctrl, ATARI_VH16_ena_ctrl, ATARI_VH8_ena_ctrl, - ATARI_VH0_ena_ctrl, ATARI_HL0_clk_ctrl, ATARI_HL24_ena_ctrl, - ATARI_HL16_ena_ctrl, ATARI_HL8_ena_ctrl, ATARI_HL0_ena_ctrl, - ATARI_VL0_clk_ctrl, ATARI_VL24_ena_ctrl, ATARI_VL16_ena_ctrl, - ATARI_VL8_ena_ctrl, ATARI_VL0_ena_ctrl, VR_DOUT0_clk_ctrl, - VR_DOUT0_ena_ctrl, VR_FRQ0_clk_ctrl, VR_FRQ0_ena_ctrl, - ACP_VCTR6_ena_ctrl, CCSEL0_clk_ctrl, BORDER_COLOR0_clk_ctrl, - BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl, + SIGNAL VR_DOUT : std_logic_vector(8 DOWNTO 0); + SIGNAL VR_DOUT_d : std_logic_vector(8 DOWNTO 0); + SIGNAL VR_DOUT_q : std_logic_vector(8 DOWNTO 0); + SIGNAL VR_FRQ : std_logic_vector(7 DOWNTO 0); + SIGNAL VR_FRQ_d : std_logic_vector(7 DOWNTO 0); + SIGNAL VR_FRQ_q : std_logic_vector(7 DOWNTO 0); + SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_16B : std_logic_vector(1 DOWNTO 0); + SIGNAL ST_SHIFT_MODE : std_logic_vector(1 DOWNTO 0); + SIGNAL ST_SHIFT_MODE_d : std_logic_vector(1 DOWNTO 0); + SIGNAL ST_SHIFT_MODE_q : std_logic_vector(1 DOWNTO 0); + SIGNAL FALCON_SHIFT_MODE : std_logic_vector(10 DOWNTO 0); + SIGNAL FALCON_SHIFT_MODE_d : std_logic_vector(10 DOWNTO 0); + SIGNAL FALCON_SHIFT_MODE_q : std_logic_vector(10 DOWNTO 0); + SIGNAL CLUT_MUX_ADR_d : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_ADR_q : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV1 : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV1_d : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV1_q : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV0 : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV0_d : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_MUX_AV0_q : std_logic_vector(3 DOWNTO 0); + SIGNAL ACP_VCTR : std_logic_vector(31 DOWNTO 0); + SIGNAL ACP_VCTR_d : std_logic_vector(31 DOWNTO 0); + SIGNAL ACP_VCTR_q : std_logic_vector(31 DOWNTO 0); + SIGNAL BORDER_COLOR_d : std_logic_vector(23 DOWNTO 0); + SIGNAL BORDER_COLOR_q : std_logic_vector(23 DOWNTO 0); + SIGNAL SYS_CTR : std_logic_vector(6 DOWNTO 0); + SIGNAL SYS_CTR_d : std_logic_vector(6 DOWNTO 0); + SIGNAL SYS_CTR_q : std_logic_vector(6 DOWNTO 0); + SIGNAL LOF : std_logic_vector(15 DOWNTO 0); + SIGNAL LOF_d : std_logic_vector(15 DOWNTO 0); + SIGNAL LOF_q : std_logic_vector(15 DOWNTO 0); + SIGNAL LWD : std_logic_vector(15 DOWNTO 0); + SIGNAL LWD_d : std_logic_vector(15 DOWNTO 0); + SIGNAL LWD_q : std_logic_vector(15 DOWNTO 0); + SIGNAL HSYNC_I : std_logic_vector(7 DOWNTO 0); + SIGNAL HSYNC_I_d : std_logic_vector(7 DOWNTO 0); + SIGNAL HSYNC_I_q : std_logic_vector(7 DOWNTO 0); + SIGNAL HSY_LEN : std_logic_vector(7 DOWNTO 0); + SIGNAL HSY_LEN_d : std_logic_vector(7 DOWNTO 0); + SIGNAL HSY_LEN_q : std_logic_vector(7 DOWNTO 0); + SIGNAL VSYNC_I : std_logic_vector(2 DOWNTO 0); + SIGNAL VSYNC_I_d : std_logic_vector(2 DOWNTO 0); + SIGNAL VSYNC_I_q : std_logic_vector(2 DOWNTO 0); + SIGNAL VHCNT : std_logic_vector(11 DOWNTO 0); + SIGNAL VHCNT_d : std_logic_vector(11 DOWNTO 0); + SIGNAL VHCNT_q : std_logic_vector(11 DOWNTO 0); + SIGNAL SUB_PIXEL_CNT : std_logic_vector(6 DOWNTO 0); + SIGNAL SUB_PIXEL_CNT_d : std_logic_vector(6 DOWNTO 0); + SIGNAL SUB_PIXEL_CNT_q : std_logic_vector(6 DOWNTO 0); + SIGNAL VVCNT : std_logic_vector(10 DOWNTO 0); + SIGNAL VVCNT_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VVCNT_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VERZ2 : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ2_d : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ2_q : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ1 : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ1_d : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ1_q : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ0 : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ0_d : std_logic_vector(9 DOWNTO 0); + SIGNAL VERZ0_q : std_logic_vector(9 DOWNTO 0); + SIGNAL RAND : std_logic_vector(6 DOWNTO 0); + SIGNAL RAND_d : std_logic_vector(6 DOWNTO 0); + SIGNAL RAND_q : std_logic_vector(6 DOWNTO 0); + SIGNAL CCSEL_d : std_logic_vector(2 DOWNTO 0); + SIGNAL CCSEL_q : std_logic_vector(2 DOWNTO 0); + SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HH_d : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HH_q : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VH : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VH_d : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VH_q : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL_d : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL_q : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VL : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VL_d : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_VL_q : std_logic_vector(31 DOWNTO 0); + SIGNAL RAND_LINKS : std_logic_vector(11 DOWNTO 0); + SIGNAL HDIS_START : std_logic_vector(11 DOWNTO 0); + SIGNAL HDIS_END : std_logic_vector(11 DOWNTO 0); + SIGNAL RAND_RECHTS : std_logic_vector(11 DOWNTO 0); + SIGNAL HS_START : std_logic_vector(11 DOWNTO 0); + SIGNAL H_TOTAL : std_logic_vector(11 DOWNTO 0); + SIGNAL HDIS_LEN : std_logic_vector(11 DOWNTO 0); + SIGNAL MULF : std_logic_vector(5 DOWNTO 0); + SIGNAL HHT : std_logic_vector(11 DOWNTO 0); + SIGNAL HHT_d : std_logic_vector(11 DOWNTO 0); + SIGNAL HHT_q : std_logic_vector(11 DOWNTO 0); + SIGNAL HBE : std_logic_vector(11 DOWNTO 0); + SIGNAL HBE_d : std_logic_vector(11 DOWNTO 0); + SIGNAL HBE_q : std_logic_vector(11 DOWNTO 0); + SIGNAL HDB : std_logic_vector(11 DOWNTO 0); + SIGNAL HDB_d : std_logic_vector(11 DOWNTO 0); + SIGNAL HDB_q : std_logic_vector(11 DOWNTO 0); + SIGNAL HDE : std_logic_vector(11 DOWNTO 0); + SIGNAL HDE_d : std_logic_vector(11 DOWNTO 0); + SIGNAL HDE_q : std_logic_vector(11 DOWNTO 0); + SIGNAL HBB : std_logic_vector(11 DOWNTO 0); + SIGNAL HBB_d : std_logic_vector(11 DOWNTO 0); + SIGNAL HBB_q : std_logic_vector(11 DOWNTO 0); + SIGNAL HSS : std_logic_vector(11 DOWNTO 0); + SIGNAL HSS_d : std_logic_vector(11 DOWNTO 0); + SIGNAL HSS_q : std_logic_vector(11 DOWNTO 0); + SIGNAL RAND_OBEN : std_logic_vector(10 DOWNTO 0); + SIGNAL VDIS_START : std_logic_vector(10 DOWNTO 0); + SIGNAL VDIS_END : std_logic_vector(10 DOWNTO 0); + SIGNAL RAND_UNTEN : std_logic_vector(10 DOWNTO 0); + SIGNAL VS_START : std_logic_vector(10 DOWNTO 0); + SIGNAL V_TOTAL : std_logic_vector(10 DOWNTO 0); + SIGNAL VBE : std_logic_vector(10 DOWNTO 0); + SIGNAL VBE_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VBE_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VDB : std_logic_vector(10 DOWNTO 0); + SIGNAL VDB_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VDB_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VDE : std_logic_vector(10 DOWNTO 0); + SIGNAL VDE_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VDE_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VBB : std_logic_vector(10 DOWNTO 0); + SIGNAL VBB_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VBB_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VSS : std_logic_vector(10 DOWNTO 0); + SIGNAL VSS_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VSS_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VFT : std_logic_vector(10 DOWNTO 0); + SIGNAL VFT_d : std_logic_vector(10 DOWNTO 0); + SIGNAL VFT_q : std_logic_vector(10 DOWNTO 0); + SIGNAL VCO : std_logic_vector(8 DOWNTO 0); + SIGNAL VCO_d : std_logic_vector(8 DOWNTO 0); + SIGNAL VCO_ena : std_logic_vector(8 DOWNTO 0); + SIGNAL VCO_q : std_logic_vector(8 DOWNTO 0); + SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0); + SIGNAL VCNTRL_d : std_logic_vector(3 DOWNTO 0); + SIGNAL VCNTRL_q : std_logic_vector(3 DOWNTO 0); + SIGNAL u0_data : std_logic_vector(15 DOWNTO 0); + SIGNAL u0_tridata : std_logic_vector(15 DOWNTO 0); + SIGNAL u1_data : std_logic_vector(15 DOWNTO 0); + SIGNAL u1_tridata : std_logic_vector(15 DOWNTO 0); + SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic; + SIGNAL ST_SHIFT_MODE0_ena_ctrl : std_logic; + SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; + SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic; + SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic; + SIGNAL ACP_VCTR0_clk_ctrl : std_logic; + SIGNAL ACP_VCTR24_ena_ctrl : std_logic; + SIGNAL ACP_VCTR16_ena_ctrl : std_logic; + SIGNAL ACP_VCTR8_ena_ctrl : std_logic; + SIGNAL ACP_VCTR0_ena_ctrl : std_logic; + SIGNAL ATARI_HH0_clk_ctrl : std_logic; + SIGNAL ATARI_HH24_ena_ctrl : std_logic; + SIGNAL ATARI_HH16_ena_ctrl : std_logic; + SIGNAL ATARI_HH8_ena_ctrl : std_logic; + SIGNAL ATARI_HH0_ena_ctrl : std_logic; + SIGNAL ATARI_VH0_clk_ctrl : std_logic; + SIGNAL ATARI_VH24_ena_ctrl : std_logic; + SIGNAL ATARI_VH16_ena_ctrl : std_logic; + SIGNAL ATARI_VH8_ena_ctrl : std_logic; + SIGNAL ATARI_VH0_ena_ctrl : std_logic; + SIGNAL ATARI_HL0_clk_ctrl : std_logic; + SIGNAL ATARI_HL24_ena_ctrl : std_logic; + SIGNAL ATARI_HL16_ena_ctrl : std_logic; + SIGNAL ATARI_HL8_ena_ctrl : std_logic; + SIGNAL ATARI_HL0_ena_ctrl : std_logic; + SIGNAL ATARI_VL0_clk_ctrl : std_logic; + SIGNAL ATARI_VL24_ena_ctrl : std_logic; + SIGNAL ATARI_VL16_ena_ctrl : std_logic; + SIGNAL ATARI_VL8_ena_ctrl : std_logic; + SIGNAL ATARI_VL0_ena_ctrl : std_logic; + SIGNAL VR_DOUT0_clk_ctrl : std_logic; + SIGNAL VR_DOUT0_ena_ctrl : std_logic; + SIGNAL VR_FRQ0_clk_ctrl : std_logic; + SIGNAL VR_FRQ0_ena_ctrl : std_logic; + SIGNAL ACP_VCTR6_ena_ctrl : std_logic; + SIGNAL CCSEL0_clk_ctrl : std_logic; + SIGNAL BORDER_COLOR0_clk_ctrl : std_logic; + SIGNAL BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl, BORDER_COLOR0_ena_ctrl, SYS_CTR0_clk_ctrl, SYS_CTR0_ena_ctrl, LOF0_clk_ctrl, LOF8_ena_ctrl, LOF0_ena_ctrl, LWD0_clk_ctrl, LWD8_ena_ctrl, LWD0_ena_ctrl, HHT0_clk_ctrl, HHT8_ena_ctrl, @@ -336,7 +360,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS data : IN std_logic_vector(15 DOWNTO 0); enabledt : IN std_logic; tridata : BUFFER std_logic_vector(15 DOWNTO 0) - ); + ); END COMPONENT lpm_bustri_WORD; FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS @@ -1950,7 +1974,8 @@ begin nBLANK_clk <= PIXEL_CLK; -- nBLANK = VERZ[0][8]; - nBLANK_d <= DISP_ON_q; + nblank_d <= verz0_q(8); +-- nBLANK_d <= DISP_ON_q; HSYNC_clk <= PIXEL_CLK; -- HSYNC = VERZ[1][9]; @@ -1962,23 +1987,24 @@ begin -- VSYNC = VERZ[2][9]; -- NUR MÖGLICH WENN BEIDE - VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and + VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); - nSYNC <= gnd; + nSYNC <= gnd; -- RANDFARBE MACHEN ------------------------------------ - RAND0_clk_ctrl <= PIXEL_CLK; - RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); - RAND_d(1) <= RAND_q(0); - RAND_d(2) <= RAND_q(1); - RAND_d(3) <= RAND_q(2); - RAND_d(4) <= RAND_q(3); - RAND_d(5) <= RAND_q(4); - RAND_d(6) <= RAND_q(5); - + RAND0_clk_ctrl <= PIXEL_CLK; + RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + RAND_d(1) <= RAND_q(0); + RAND_d(2) <= RAND_q(1); + RAND_d(3) <= RAND_q(2); + RAND_d(4) <= RAND_q(3); + RAND_d(5) <= RAND_q(4); + RAND_d(6) <= RAND_q(5); + -- RAND_ON = RAND[6]; - RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + rand_on <= rand(6); + -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); -- -------------------------------------------------------- CLR_FIFO_clk <= PIXEL_CLK; diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index d9dc215..5ebfa52 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -155,7 +155,7 @@ ARCHITECTURE rtl OF firebee1 IS SIGNAL CLK33M : std_logic; SIGNAL CLK48M : std_logic; SIGNAL CLK500k : std_logic; - SIGNAL CLK_VIDEO : std_logic; + SIGNAL CLK_VIDEO : std_logic; SIGNAL DDR_SYNC_66M : std_logic; SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); SIGNAL DMA_DRQ : std_logic; From 4ed46161561c5d7939d85551bbbbc26a2d3866b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 13 Jan 2016 16:43:54 +0000 Subject: [PATCH 060/127] remove unused generated signals --- FPGA_Quartus_13.1/Video/video.vhd | 3 --- 1 file changed, 3 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 59fa7b3..dee9d7c 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -802,9 +802,6 @@ ARCHITECTURE rtl OF video IS SIGNAL SYNTHESIZED_WIRE_52 : std_logic; SIGNAL SYNTHESIZED_WIRE_53 : std_logic; SIGNAL SYNTHESIZED_WIRE_54 : std_logic; - SIGNAL SYNTHESIZED_WIRE_55 : std_logic; - SIGNAL SYNTHESIZED_WIRE_56 : std_logic; - SIGNAL SYNTHESIZED_WIRE_57 : std_logic; SIGNAL SYNTHESIZED_WIRE_65 : std_logic_vector(23 DOWNTO 0); SIGNAL GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 DOWNTO 0); From 52e1b5319251eec86ef571ce36ad1f30bcf18c3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Jan 2016 06:44:52 +0000 Subject: [PATCH 061/127] formatting --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 5ab3810..4ccd1dd 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -876,7 +876,7 @@ BEGIN WHEN "010001" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - VA_S_d(9 DOWNTO 0) <= (sizeIt(CPU_AC_q,10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q,10) and BLITTER_COL_ADR); + VA_S_d(9 DOWNTO 0) <= (sizeIt(CPU_AC_q, 10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q, 10) and BLITTER_COL_ADR); -- AUTO PRECHARGE WENN NICHT FIFO PAGE VA_S_d(10) <= VA_S_q(10); From 69c107ef3296b4c6f65a23b8fc5fb6199a878684 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Jan 2016 06:45:15 +0000 Subject: [PATCH 062/127] remove unused connections --- FPGA_Quartus_13.1/Video/video.vhd | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index dee9d7c..f15df82 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -839,10 +839,7 @@ BEGIN SYNTHESIZED_WIRE_22 <= '0'; SYNTHESIZED_WIRE_23 <= '0'; SYNTHESIZED_WIRE_24 <= '0'; - SYNTHESIZED_WIRE_55 <= '0'; - SYNTHESIZED_WIRE_56 <= '0'; - SYNTHESIZED_WIRE_57 <= '0'; - + CC16(23) <= GDFX_TEMP_SIGNAL_0(15); CC16(22) <= GDFX_TEMP_SIGNAL_0(14); CC16(21) <= GDFX_TEMP_SIGNAL_0(13); From b7a34c8abf440f64ae2a6cb3de80543c625e03f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Jan 2016 07:17:08 +0000 Subject: [PATCH 063/127] reformat --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 326 +++--- FPGA_Quartus_13.1/firebee1.qsf | 1472 +++++++++++++-------------- 2 files changed, 915 insertions(+), 883 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 4ccd1dd..60a152e 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -313,181 +313,213 @@ ARCHITECTURE rtl OF ddr_ctr IS BEGIN --- Sub Module Section - u0: lpm_bustri_BYT port map (data=>u0_data, enabledt=>u0_enabledt, - tridata=>u0_tridata); + -- Sub Module Section + u0: lpm_bustri_BYT + port map + ( + data=>u0_data, + enabledt=>u0_enabledt, + tridata=>u0_tridata + ); --- Register Section + -- Register Section - SR_FIFO_WRE <= SR_FIFO_WRE_q; - PROCESS (SR_FIFO_WRE_clk) BEGIN - IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN - SR_FIFO_WRE_q <= SR_FIFO_WRE_d; - END IF; - END PROCESS; + SR_FIFO_WRE <= SR_FIFO_WRE_q; + PROCESS (SR_FIFO_WRE_clk) + BEGIN + IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN + SR_FIFO_WRE_q <= SR_FIFO_WRE_d; + END IF; + END PROCESS; - SR_DDR_WR <= SR_DDR_WR_q; - PROCESS (SR_DDR_WR_clk) BEGIN - IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN - SR_DDR_WR_q <= SR_DDR_WR_d; - END IF; - END PROCESS; + SR_DDR_WR <= SR_DDR_WR_q; + PROCESS (SR_DDR_WR_clk) + BEGIN + IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN + SR_DDR_WR_q <= SR_DDR_WR_d; + END IF; + END PROCESS; - SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; - PROCESS (SR_DDRWR_D_SEL_clk) BEGIN - IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN - SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; - END IF; - END PROCESS; + SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; + PROCESS (SR_DDRWR_D_SEL_clk) + BEGIN + IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN + SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; + END IF; + END PROCESS; - SR_VDMP <= SR_VDMP_q; - PROCESS (SR_VDMP0_clk_ctrl) BEGIN - IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN - SR_VDMP_q <= SR_VDMP_d; - END IF; - END PROCESS; + SR_VDMP <= SR_VDMP_q; + PROCESS (SR_VDMP0_clk_ctrl) + BEGIN + IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN + SR_VDMP_q <= SR_VDMP_d; + END IF; + END PROCESS; - PROCESS (FB_REGDDR_0_clk_ctrl) BEGIN - IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN - FB_REGDDR_q <= FB_REGDDR_d; - END IF; - END PROCESS; + PROCESS (FB_REGDDR_0_clk_ctrl) + BEGIN + IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN + FB_REGDDR_q <= FB_REGDDR_d; + END IF; + END PROCESS; - PROCESS (DDR_SM_0_clk_ctrl) BEGIN - IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN - DDR_SM_q <= DDR_SM_d; - END IF; - END PROCESS; + PROCESS (DDR_SM_0_clk_ctrl) + BEGIN + IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN + DDR_SM_q <= DDR_SM_d; + END IF; + END PROCESS; - PROCESS (VA_P0_clk_ctrl) BEGIN - IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN - VA_P_q <= VA_P_d; - END IF; - END PROCESS; + PROCESS (VA_P0_clk_ctrl) + BEGIN + IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN + VA_P_q <= VA_P_d; + END IF; + END PROCESS; - PROCESS (BA_P0_clk_ctrl) BEGIN - IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN - BA_P_q <= BA_P_d; - END IF; - END PROCESS; + PROCESS (BA_P0_clk_ctrl) + BEGIN + IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN + BA_P_q <= BA_P_d; + END IF; + END PROCESS; - PROCESS (VA_S0_clk_ctrl) BEGIN - IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN - VA_S_q <= VA_S_d; - END IF; - END PROCESS; + PROCESS (VA_S0_clk_ctrl) + BEGIN + IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN + VA_S_q <= VA_S_d; + END IF; + END PROCESS; - PROCESS (BA_S0_clk_ctrl) BEGIN - IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN - BA_S_q <= BA_S_d; - END IF; - END PROCESS; + PROCESS (BA_S0_clk_ctrl) + BEGIN + IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN + BA_S_q <= BA_S_d; + END IF; + END PROCESS; - PROCESS (MCS0_clk_ctrl) BEGIN - IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN - MCS_q <= MCS_d; - END IF; - END PROCESS; + PROCESS (MCS0_clk_ctrl) + BEGIN + IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN + MCS_q <= MCS_d; + END IF; + END PROCESS; - PROCESS (CPU_DDR_SYNC_clk) BEGIN - IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN - CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; - END IF; - END PROCESS; + PROCESS (CPU_DDR_SYNC_clk) + BEGIN + IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN + CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; + END IF; + END PROCESS; - PROCESS (DDR_CS_clk) BEGIN - IF DDR_CS_clk'event and DDR_CS_clk='1' THEN - IF DDR_CS_ena='1' THEN - DDR_CS_q <= DDR_CS_d; - END IF; - END IF; - END PROCESS; + PROCESS (DDR_CS_clk) + BEGIN + IF DDR_CS_clk'event and DDR_CS_clk='1' THEN + IF DDR_CS_ena='1' THEN + DDR_CS_q <= DDR_CS_d; + END IF; + END IF; + END PROCESS; - PROCESS (CPU_REQ_clk) BEGIN - IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN - CPU_REQ_q <= CPU_REQ_d; - END IF; - END PROCESS; + PROCESS (CPU_REQ_clk) + BEGIN + IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN + CPU_REQ_q <= CPU_REQ_d; + END IF; + END PROCESS; - PROCESS (CPU_AC_clk) BEGIN - IF CPU_AC_clk'event and CPU_AC_clk='1' THEN - CPU_AC_q <= CPU_AC_d; - END IF; - END PROCESS; + PROCESS (CPU_AC_clk) + BEGIN + IF CPU_AC_clk'event and CPU_AC_clk='1' THEN + CPU_AC_q <= CPU_AC_d; + END IF; + END PROCESS; - PROCESS (BUS_CYC_clk) BEGIN - IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN - BUS_CYC_q <= BUS_CYC_d; - END IF; - END PROCESS; + PROCESS (BUS_CYC_clk) + BEGIN + IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN + BUS_CYC_q <= BUS_CYC_d; + END IF; + END PROCESS; - PROCESS (BLITTER_REQ_clk) BEGIN - IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN - BLITTER_REQ_q <= BLITTER_REQ_d; - END IF; - END PROCESS; + PROCESS (BLITTER_REQ_clk) + BEGIN + IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN + BLITTER_REQ_q <= BLITTER_REQ_d; + END IF; + END PROCESS; - PROCESS (BLITTER_AC_clk) BEGIN - IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN - BLITTER_AC_q <= BLITTER_AC_d; - END IF; - END PROCESS; + PROCESS (BLITTER_AC_clk) + BEGIN + IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN + BLITTER_AC_q <= BLITTER_AC_d; + END IF; + END PROCESS; - PROCESS (FIFO_REQ_clk) BEGIN - IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN - FIFO_REQ_q <= FIFO_REQ_d; - END IF; - END PROCESS; + PROCESS (FIFO_REQ_clk) + BEGIN + IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN + FIFO_REQ_q <= FIFO_REQ_d; + END IF; + END PROCESS; - PROCESS (FIFO_AC_clk) BEGIN - IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN - FIFO_AC_q <= FIFO_AC_d; - END IF; - END PROCESS; + PROCESS (FIFO_AC_clk) + BEGIN + IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN + FIFO_AC_q <= FIFO_AC_d; + END IF; + END PROCESS; - PROCESS (CLR_FIFO_SYNC_clk) BEGIN - IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN - CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; - END IF; - END PROCESS; + PROCESS (CLR_FIFO_SYNC_clk) + BEGIN + IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN + CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; + END IF; + END PROCESS; - PROCESS (CLEAR_FIFO_CNT_clk) BEGIN - IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN - CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; - END IF; - END PROCESS; + PROCESS (CLEAR_FIFO_CNT_clk) + BEGIN + IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN + CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; + END IF; + END PROCESS; - PROCESS (STOP_clk) BEGIN - IF STOP_clk'event and STOP_clk='1' THEN - STOP_q <= STOP_d; - END IF; - END PROCESS; + PROCESS (STOP_clk) + BEGIN + IF STOP_clk'event and STOP_clk='1' THEN + STOP_q <= STOP_d; + END IF; + END PROCESS; - PROCESS (FIFO_BANK_OK_clk) BEGIN - IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN - FIFO_BANK_OK_q <= FIFO_BANK_OK_d; - END IF; - END PROCESS; + PROCESS (FIFO_BANK_OK_clk) + BEGIN + IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN + FIFO_BANK_OK_q <= FIFO_BANK_OK_d; + END IF; + END PROCESS; - PROCESS (DDR_REFRESH_CNT0_clk_ctrl) BEGIN - IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN - DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; - END IF; - END PROCESS; + PROCESS (DDR_REFRESH_CNT0_clk_ctrl) + BEGIN + IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN + DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; + END IF; + END PROCESS; - PROCESS (DDR_REFRESH_REQ_clk) BEGIN - IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN - DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; - END IF; - END PROCESS; + PROCESS (DDR_REFRESH_REQ_clk) + BEGIN + IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN + DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; + END IF; + END PROCESS; - PROCESS (DDR_REFRESH_SIG0_clk_ctrl) BEGIN - IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN - IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN - DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; - END IF; - END IF; - END PROCESS; + PROCESS (DDR_REFRESH_SIG0_clk_ctrl) + BEGIN + IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN + IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN + DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; + END IF; + END IF; + END PROCESS; PROCESS (REFRESH_TIME_clk) BEGIN IF REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' THEN diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index b587e1e..a73de2d 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,390 +39,390 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -432,7 +432,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -442,21 +442,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -466,76 +466,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -557,301 +557,301 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From c4d56bb65241fddc47d52204639833b3557e90bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Jan 2016 16:49:11 +0000 Subject: [PATCH 064/127] reformat --- .../Video/video_mod_mux_clutctr.vhd | 1237 +++++++------- FPGA_Quartus_13.1/firebee1.qsf | 1472 ++++++++--------- FPGA_Quartus_13.1/firebee1.qws | Bin 5478 -> 4827 bytes 3 files changed, 1356 insertions(+), 1353 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index be83692..50ec8f9 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -375,862 +375,866 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS END FUNCTION to_std_logic; - -- sizeIt replicates a value to an array of specific length. - Function sizeIt(a: std_Logic; len: integer) return std_logic_vector is - variable rep: std_logic_vector( len-1 DOWNTO 0); - begin for i in rep'range loop rep(i) := a; end loop; return rep; - end sizeIt; -begin + -- sizeIt replicates a value to an array of specific length. + FUNCTION sizeit(a : std_Logic; len : integer) RETURN std_logic_vector IS + VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0); + BEGIN + FOR i IN rep'RANGE LOOP + rep(i) := a; + END LOOP; + RETURN rep; + END FUNCTION sizeit; --- Sub Module Section - u0: lpm_bustri_WORD port map (data=>u0_data, enabledt=>u0_enabledt, - tridata=>u0_tridata); - u1: lpm_bustri_WORD port map (data=>u1_data, enabledt=>u1_enabledt, - tridata=>u1_tridata); +BEGIN --- Register Section + -- Sub Module Section + u0 : lpm_bustri_WORD + PORT MAP + ( + data => u0_data, + enabledt => u0_enabledt, + tridata => u0_tridata + ); + + u1 : lpm_bustri_WORD + PORT MAP + ( + data => u1_data, + enabledt => u1_enabledt, + tridata => u1_tridata + ); - CLUT_MUX_ADR <= CLUT_MUX_ADR_q; - process (CLUT_MUX_ADR0_clk_ctrl) begin - if CLUT_MUX_ADR0_clk_ctrl'event and CLUT_MUX_ADR0_clk_ctrl='1' then - CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; - end if; - end process; + -- Register Section - HSYNC <= HSYNC_q; - process (HSYNC_clk) begin - if HSYNC_clk'event and HSYNC_clk='1' then - HSYNC_q <= HSYNC_d; - end if; - end process; + CLUT_MUX_ADR <= CLUT_MUX_ADR_q; + + PROCESS (CLUT_MUX_ADR0_clk_ctrl) + BEGIN + IF CLUT_MUX_ADR0_clk_ctrl'EVENT and CLUT_MUX_ADR0_clk_ctrl = '1' THEN + CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; + END IF; + END PROCESS; - VSYNC <= VSYNC_q; - process (VSYNC_clk) begin - if VSYNC_clk'event and VSYNC_clk='1' then - VSYNC_q <= VSYNC_d; - end if; - end process; + HSYNC <= HSYNC_q; + PROCESS (HSYNC_clk) + BEGIN + IF HSYNC_clk'EVENT and HSYNC_clk = '1' THEN + HSYNC_q <= HSYNC_d; + END IF; + END PROCESS; - nBLANK <= nBLANK_q; - process (nBLANK_clk) begin - if nBLANK_clk'event and nBLANK_clk='1' then - nBLANK_q <= nBLANK_d; - end if; - end process; + VSYNC <= VSYNC_q; + PROCESS (VSYNC_clk) + BEGIN + IF VSYNC_clk'EVENT and VSYNC_clk = '1' THEN + VSYNC_q <= VSYNC_d; + END IF; + END PROCESS; - FIFO_RDE <= FIFO_RDE_q; - process (FIFO_RDE_clk) begin - if FIFO_RDE_clk'event and FIFO_RDE_clk='1' then - FIFO_RDE_q <= FIFO_RDE_d; - end if; - end process; + nBLANK <= nBLANK_q; + PROCESS (nBLANK_clk) + BEGIN + IF nBLANK_clk'EVENT and nBLANK_clk = '1' THEN + nBLANK_q <= nBLANK_d; + END IF; + END PROCESS; - BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); - process (BORDER_COLOR0_clk_ctrl) begin - if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then - if BORDER_COLOR16_ena_ctrl='1' then - (BORDER_COLOR_q(23), BORDER_COLOR_q(22), BORDER_COLOR_q(21), - BORDER_COLOR_q(20), BORDER_COLOR_q(19), BORDER_COLOR_q(18), - BORDER_COLOR_q(17), BORDER_COLOR_q(16)) <= BORDER_COLOR_d(23 - DOWNTO 16); - end if; - end if; - end process; + FIFO_RDE <= FIFO_RDE_q; + PROCESS (FIFO_RDE_clk) + BEGIN + IF FIFO_RDE_clk'EVENT and FIFO_RDE_clk = '1' THEN + FIFO_RDE_q <= FIFO_RDE_d; + END IF; + END PROCESS; - BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); - process (BORDER_COLOR0_clk_ctrl) begin - if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then - if BORDER_COLOR8_ena_ctrl='1' then - (BORDER_COLOR_q(15), BORDER_COLOR_q(14), BORDER_COLOR_q(13), - BORDER_COLOR_q(12), BORDER_COLOR_q(11), BORDER_COLOR_q(10), - BORDER_COLOR_q(9), BORDER_COLOR_q(8)) <= BORDER_COLOR_d(15 - DOWNTO 8); - end if; - end if; - end process; + BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); + BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); + BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); + + PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN + IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN + IF BORDER_COLOR16_ena_ctrl = '1' THEN + border_color_q(23 DOWNTO 16) <= border_color_d(23 DOWNTO 16); + END IF; + IF BORDER_COLOR8_ena_ctrl = '1' THEN + border_color_q(15 DOWNTO 8) <= border_color_d(15 DOWNTO 8); + END IF; + IF BORDER_COLOR0_ena_ctrl = '1' THEN + border_color_q(7 DOWNTO 0) <= border_color_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); - process (BORDER_COLOR0_clk_ctrl) begin - if BORDER_COLOR0_clk_ctrl'event and BORDER_COLOR0_clk_ctrl='1' then - if BORDER_COLOR0_ena_ctrl='1' then - (BORDER_COLOR_q(7), BORDER_COLOR_q(6), BORDER_COLOR_q(5), - BORDER_COLOR_q(4), BORDER_COLOR_q(3), BORDER_COLOR_q(2), - BORDER_COLOR_q(1), BORDER_COLOR_q(0)) <= BORDER_COLOR_d(7 - DOWNTO 0); - end if; - end if; - end process; + CCSEL <= CCSEL_q; + PROCESS (CCSEL0_clk_ctrl) + BEGIN + IF CCSEL0_clk_ctrl'EVENT and CCSEL0_clk_ctrl = '1' THEN + CCSEL_q <= CCSEL_d; + END IF; + END PROCESS; - CCSEL <= CCSEL_q; - process (CCSEL0_clk_ctrl) begin - if CCSEL0_clk_ctrl'event and CCSEL0_clk_ctrl='1' then - CCSEL_q <= CCSEL_d; - end if; - end process; + INTER_ZEI <= INTER_ZEI_q; + PROCESS (INTER_ZEI_clk) + BEGIN + IF INTER_ZEI_clk'EVENT and INTER_ZEI_clk = '1' THEN + INTER_ZEI_q <= INTER_ZEI_d; + END IF; + END PROCESS; - INTER_ZEI <= INTER_ZEI_q; - process (INTER_ZEI_clk) begin - if INTER_ZEI_clk'event and INTER_ZEI_clk='1' then - INTER_ZEI_q <= INTER_ZEI_d; - end if; - end process; + DOP_FIFO_CLR <= DOP_FIFO_CLR_q; + PROCESS (DOP_FIFO_CLR_clk) + BEGIN + IF DOP_FIFO_CLR_clk'EVENT and DOP_FIFO_CLR_clk = '1' THEN + DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d; + END IF; + END PROCESS; - DOP_FIFO_CLR <= DOP_FIFO_CLR_q; - process (DOP_FIFO_CLR_clk) begin - if DOP_FIFO_CLR_clk'event and DOP_FIFO_CLR_clk='1' then - DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d; - end if; - end process; + VIDEO_RECONFIG <= VIDEO_RECONFIG_q; + PROCESS (VIDEO_RECONFIG_clk) + BEGIN + IF VIDEO_RECONFIG_clk'EVENT and VIDEO_RECONFIG_clk = '1' THEN + VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; + END IF; + END PROCESS; - VIDEO_RECONFIG <= VIDEO_RECONFIG_q; - process (VIDEO_RECONFIG_clk) begin - if VIDEO_RECONFIG_clk'event and VIDEO_RECONFIG_clk='1' then - VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; - end if; - end process; + VR_WR <= VR_WR_q; + PROCESS (VR_WR_clk) + BEGIN + IF VR_WR_clk'EVENT and VR_WR_clk = '1' THEN + VR_WR_q <= VR_WR_d; + END IF; + END PROCESS; - VR_WR <= VR_WR_q; - process (VR_WR_clk) begin - if VR_WR_clk'event and VR_WR_clk='1' then - VR_WR_q <= VR_WR_d; - end if; - end process; + CLR_FIFO <= CLR_FIFO_q; + PROCESS (CLR_FIFO_clk) + BEGIN + IF CLR_FIFO_clk'EVENT and CLR_FIFO_clk = '1' THEN + IF CLR_FIFO_ena = '1' THEN + CLR_FIFO_q <= CLR_FIFO_d; + END IF; + END IF; + END PROCESS; - CLR_FIFO <= CLR_FIFO_q; - process (CLR_FIFO_clk) begin - if CLR_FIFO_clk'event and CLR_FIFO_clk='1' then - if CLR_FIFO_ena='1' then - CLR_FIFO_q <= CLR_FIFO_d; - end if; - end if; - end process; + PROCESS (CLK17M_clk) + BEGIN + IF CLK17M_clk'EVENT and CLK17M_clk = '1' THEN + CLK17M_q <= CLK17M_d; + END IF; + END PROCESS; - process (CLK17M_clk) begin - if CLK17M_clk'event and CLK17M_clk='1' then - CLK17M_q <= CLK17M_d; - end if; - end process; + PROCESS (CLK13M_clk) + BEGIN + IF CLK13M_clk'EVENT and CLK13M_clk = '1' THEN + CLK13M_q <= CLK13M_d; + END IF; + END PROCESS; - process (CLK13M_clk) begin - if CLK13M_clk'event and CLK13M_clk='1' then - CLK13M_q <= CLK13M_d; - end if; - end process; + PROCESS (VR_DOUT0_clk_ctrl) + BEGIN + IF VR_DOUT0_clk_ctrl'EVENT and VR_DOUT0_clk_ctrl = '1' THEN + IF VR_DOUT0_ena_ctrl = '1' THEN + VR_DOUT_q <= VR_DOUT_d; + END IF; + END IF; + END PROCESS; - process (VR_DOUT0_clk_ctrl) begin - if VR_DOUT0_clk_ctrl'event and VR_DOUT0_clk_ctrl='1' then - if VR_DOUT0_ena_ctrl='1' then - VR_DOUT_q <= VR_DOUT_d; - end if; - end if; - end process; + PROCESS (VR_FRQ0_clk_ctrl) + BEGIN + IF VR_FRQ0_clk_ctrl'EVENT and VR_FRQ0_clk_ctrl = '1' THEN + IF VR_FRQ0_ena_ctrl = '1' THEN + VR_FRQ_q <= VR_FRQ_d; + END IF; + END IF; + END PROCESS; - process (VR_FRQ0_clk_ctrl) begin - if VR_FRQ0_clk_ctrl'event and VR_FRQ0_clk_ctrl='1' then - if VR_FRQ0_ena_ctrl='1' then - VR_FRQ_q <= VR_FRQ_d; - end if; - end if; - end process; + PROCESS (ST_SHIFT_MODE0_clk_ctrl) + BEGIN + IF ST_SHIFT_MODE0_clk_ctrl'EVENT and ST_SHIFT_MODE0_clk_ctrl = '1' THEN + IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN + ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; + END IF; + END IF; + END PROCESS; - process (ST_SHIFT_MODE0_clk_ctrl) begin - if ST_SHIFT_MODE0_clk_ctrl'event and ST_SHIFT_MODE0_clk_ctrl='1' then - if ST_SHIFT_MODE0_ena_ctrl='1' then - ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; - end if; - end if; - end process; + PROCESS (FALCON_SHIFT_MODE0_clk_ctrl) + BEGIN + IF FALCON_SHIFT_MODE0_clk_ctrl'EVENT and FALCON_SHIFT_MODE0_clk_ctrl = '1' THEN + IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN + falcon_shift_mode_q(10 DOWNTO 8) <= falcon_shift_mode_d(10 DOWNTO 8); + END IF; + IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN + falcon_shift_mode_q(7 DOWNTO 0) <= falcon_shift_mode_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - process (FALCON_SHIFT_MODE0_clk_ctrl) begin - if FALCON_SHIFT_MODE0_clk_ctrl'event and FALCON_SHIFT_MODE0_clk_ctrl='1' - then - if FALCON_SHIFT_MODE8_ena_ctrl='1' then - (FALCON_SHIFT_MODE_q(10), FALCON_SHIFT_MODE_q(9), - FALCON_SHIFT_MODE_q(8)) <= FALCON_SHIFT_MODE_d(10 DOWNTO 8); - end if; - end if; - end process; - - process (FALCON_SHIFT_MODE0_clk_ctrl) begin - if FALCON_SHIFT_MODE0_clk_ctrl'event and FALCON_SHIFT_MODE0_clk_ctrl='1' - then - if FALCON_SHIFT_MODE0_ena_ctrl='1' then - (FALCON_SHIFT_MODE_q(7), FALCON_SHIFT_MODE_q(6), - FALCON_SHIFT_MODE_q(5), FALCON_SHIFT_MODE_q(4), - FALCON_SHIFT_MODE_q(3), FALCON_SHIFT_MODE_q(2), - FALCON_SHIFT_MODE_q(1), FALCON_SHIFT_MODE_q(0)) <= - FALCON_SHIFT_MODE_d(7 DOWNTO 0); - end if; - end if; - end process; - - process (CLUT_MUX_AV1_0_clk_ctrl) begin - if CLUT_MUX_AV1_0_clk_ctrl'event and CLUT_MUX_AV1_0_clk_ctrl='1' then + PROCESS (CLUT_MUX_AV1_0_clk_ctrl) BEGIN + if CLUT_MUX_AV1_0_clk_ctrl'EVENT and CLUT_MUX_AV1_0_clk_ctrl='1' THEN CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; - end if; - end process; + END IF; + END PROCESS; - process (CLUT_MUX_AV0_0_clk_ctrl) begin - if CLUT_MUX_AV0_0_clk_ctrl'event and CLUT_MUX_AV0_0_clk_ctrl='1' then + PROCESS (CLUT_MUX_AV0_0_clk_ctrl) BEGIN + if CLUT_MUX_AV0_0_clk_ctrl'EVENT and CLUT_MUX_AV0_0_clk_ctrl='1' THEN CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; - end if; - end process; + END IF; + END PROCESS; - process (ACP_VCTR0_clk_ctrl) begin - if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then - if ACP_VCTR24_ena_ctrl='1' then + PROCESS (ACP_VCTR0_clk_ctrl) BEGIN + if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN + if ACP_VCTR24_ena_ctrl='1' THEN (ACP_VCTR_q(31), ACP_VCTR_q(30), ACP_VCTR_q(29), ACP_VCTR_q(28), ACP_VCTR_q(27), ACP_VCTR_q(26), ACP_VCTR_q(25), ACP_VCTR_q(24)) <= ACP_VCTR_d(31 DOWNTO 24); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ACP_VCTR0_clk_ctrl) begin - if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then - if ACP_VCTR16_ena_ctrl='1' then + PROCESS (ACP_VCTR0_clk_ctrl) BEGIN + if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN + if ACP_VCTR16_ena_ctrl='1' THEN (ACP_VCTR_q(23), ACP_VCTR_q(22), ACP_VCTR_q(21), ACP_VCTR_q(20), ACP_VCTR_q(19), ACP_VCTR_q(18), ACP_VCTR_q(17), ACP_VCTR_q(16)) <= ACP_VCTR_d(23 DOWNTO 16); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ACP_VCTR0_clk_ctrl) begin - if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then - if ACP_VCTR8_ena_ctrl='1' then + PROCESS (ACP_VCTR0_clk_ctrl) BEGIN + if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN + if ACP_VCTR8_ena_ctrl='1' THEN (ACP_VCTR_q(15), ACP_VCTR_q(14), ACP_VCTR_q(13), ACP_VCTR_q(12), ACP_VCTR_q(11), ACP_VCTR_q(10), ACP_VCTR_q(9), ACP_VCTR_q(8)) <= ACP_VCTR_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ACP_VCTR0_clk_ctrl) begin - if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then - if ACP_VCTR6_ena_ctrl='1' then + PROCESS (ACP_VCTR0_clk_ctrl) BEGIN + if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN + if ACP_VCTR6_ena_ctrl='1' THEN (ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 DOWNTO 6); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ACP_VCTR0_clk_ctrl) begin - if ACP_VCTR0_clk_ctrl'event and ACP_VCTR0_clk_ctrl='1' then - if ACP_VCTR0_ena_ctrl='1' then + PROCESS (ACP_VCTR0_clk_ctrl) BEGIN + if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN + if ACP_VCTR0_ena_ctrl='1' THEN (ACP_VCTR_q(5), ACP_VCTR_q(4), ACP_VCTR_q(3), ACP_VCTR_q(2), ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (SYS_CTR0_clk_ctrl) begin - if SYS_CTR0_clk_ctrl'event and SYS_CTR0_clk_ctrl='1' then - if SYS_CTR0_ena_ctrl='1' then + PROCESS (SYS_CTR0_clk_ctrl) BEGIN + if SYS_CTR0_clk_ctrl'EVENT and SYS_CTR0_clk_ctrl='1' THEN + if SYS_CTR0_ena_ctrl='1' THEN SYS_CTR_q <= SYS_CTR_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (LOF0_clk_ctrl) begin - if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then - if LOF8_ena_ctrl='1' then + PROCESS (LOF0_clk_ctrl) BEGIN + if LOF0_clk_ctrl'EVENT and LOF0_clk_ctrl='1' THEN + if LOF8_ena_ctrl='1' THEN (LOF_q(15), LOF_q(14), LOF_q(13), LOF_q(12), LOF_q(11), LOF_q(10), LOF_q(9), LOF_q(8)) <= LOF_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (LOF0_clk_ctrl) begin - if LOF0_clk_ctrl'event and LOF0_clk_ctrl='1' then - if LOF0_ena_ctrl='1' then + PROCESS (LOF0_clk_ctrl) BEGIN + if LOF0_clk_ctrl'EVENT and LOF0_clk_ctrl='1' THEN + if LOF0_ena_ctrl='1' THEN (LOF_q(7), LOF_q(6), LOF_q(5), LOF_q(4), LOF_q(3), LOF_q(2), LOF_q(1), LOF_q(0)) <= LOF_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (LWD0_clk_ctrl) begin - if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then - if LWD8_ena_ctrl='1' then + PROCESS (LWD0_clk_ctrl) BEGIN + if LWD0_clk_ctrl'EVENT and LWD0_clk_ctrl='1' THEN + if LWD8_ena_ctrl='1' THEN (LWD_q(15), LWD_q(14), LWD_q(13), LWD_q(12), LWD_q(11), LWD_q(10), LWD_q(9), LWD_q(8)) <= LWD_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (LWD0_clk_ctrl) begin - if LWD0_clk_ctrl'event and LWD0_clk_ctrl='1' then - if LWD0_ena_ctrl='1' then + PROCESS (LWD0_clk_ctrl) BEGIN + if LWD0_clk_ctrl'EVENT and LWD0_clk_ctrl='1' THEN + if LWD0_ena_ctrl='1' THEN (LWD_q(7), LWD_q(6), LWD_q(5), LWD_q(4), LWD_q(3), LWD_q(2), LWD_q(1), LWD_q(0)) <= LWD_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (CLUT_TA_clk) begin - if CLUT_TA_clk'event and CLUT_TA_clk='1' then + PROCESS (CLUT_TA_clk) BEGIN + if CLUT_TA_clk'EVENT and CLUT_TA_clk='1' THEN CLUT_TA_q <= CLUT_TA_d; - end if; - end process; + END IF; + END PROCESS; - process (HSYNC_I0_clk_ctrl) begin - if HSYNC_I0_clk_ctrl'event and HSYNC_I0_clk_ctrl='1' then + PROCESS (HSYNC_I0_clk_ctrl) BEGIN + if HSYNC_I0_clk_ctrl'EVENT and HSYNC_I0_clk_ctrl='1' THEN HSYNC_I_q <= HSYNC_I_d; - end if; - end process; + END IF; + END PROCESS; - process (HSY_LEN0_clk_ctrl) begin - if HSY_LEN0_clk_ctrl'event and HSY_LEN0_clk_ctrl='1' then + PROCESS (HSY_LEN0_clk_ctrl) BEGIN + if HSY_LEN0_clk_ctrl'EVENT and HSY_LEN0_clk_ctrl='1' THEN HSY_LEN_q <= HSY_LEN_d; - end if; - end process; + END IF; + END PROCESS; - process (HSYNC_START_clk) begin - if HSYNC_START_clk'event and HSYNC_START_clk='1' then + PROCESS (HSYNC_START_clk) BEGIN + if HSYNC_START_clk'EVENT and HSYNC_START_clk='1' THEN HSYNC_START_q <= HSYNC_START_d; - end if; - end process; + END IF; + END PROCESS; - process (LAST_clk) begin - if LAST_clk'event and LAST_clk='1' then + PROCESS (LAST_clk) BEGIN + if LAST_clk'EVENT and LAST_clk='1' THEN LAST_q <= LAST_d; - end if; - end process; + END IF; + END PROCESS; - process (VSYNC_START_clk) begin - if VSYNC_START_clk'event and VSYNC_START_clk='1' then - if VSYNC_START_ena='1' then + PROCESS (VSYNC_START_clk) BEGIN + if VSYNC_START_clk'EVENT and VSYNC_START_clk='1' THEN + if VSYNC_START_ena='1' THEN VSYNC_START_q <= VSYNC_START_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VSYNC_I0_clk_ctrl) begin - if VSYNC_I0_clk_ctrl'event and VSYNC_I0_clk_ctrl='1' then - if VSYNC_I0_ena_ctrl='1' then + PROCESS (VSYNC_I0_clk_ctrl) BEGIN + if VSYNC_I0_clk_ctrl'EVENT and VSYNC_I0_clk_ctrl='1' THEN + if VSYNC_I0_ena_ctrl='1' THEN VSYNC_I_q <= VSYNC_I_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (DISP_ON_clk) begin - if DISP_ON_clk'event and DISP_ON_clk='1' then + PROCESS (DISP_ON_clk) BEGIN + if DISP_ON_clk'EVENT and DISP_ON_clk='1' THEN DISP_ON_q <= DISP_ON_d; - end if; - end process; + END IF; + END PROCESS; - process (DPO_ZL_clk) begin - if DPO_ZL_clk'event and DPO_ZL_clk='1' then - if DPO_ZL_ena='1' then + PROCESS (DPO_ZL_clk) BEGIN + if DPO_ZL_clk'EVENT and DPO_ZL_clk='1' THEN + if DPO_ZL_ena='1' THEN DPO_ZL_q <= DPO_ZL_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (DPO_ON_clk) begin - if DPO_ON_clk'event and DPO_ON_clk='1' then + PROCESS (DPO_ON_clk) BEGIN + if DPO_ON_clk'EVENT and DPO_ON_clk='1' THEN DPO_ON_q <= DPO_ON_d; - end if; - end process; + END IF; + END PROCESS; - process (DPO_OFF_clk) begin - if DPO_OFF_clk'event and DPO_OFF_clk='1' then + PROCESS (DPO_OFF_clk) BEGIN + if DPO_OFF_clk'EVENT and DPO_OFF_clk='1' THEN DPO_OFF_q <= DPO_OFF_d; - end if; - end process; + END IF; + END PROCESS; - process (VDTRON_clk) begin - if VDTRON_clk'event and VDTRON_clk='1' then + PROCESS (VDTRON_clk) BEGIN + if VDTRON_clk'EVENT and VDTRON_clk='1' THEN VDTRON_q <= VDTRON_d; - end if; - end process; + END IF; + END PROCESS; - process (VCO_ZL_clk) begin - if VCO_ZL_clk'event and VCO_ZL_clk='1' then - if VCO_ZL_ena='1' then + PROCESS (VCO_ZL_clk) BEGIN + if VCO_ZL_clk'EVENT and VCO_ZL_clk='1' THEN + if VCO_ZL_ena='1' THEN VCO_ZL_q <= VCO_ZL_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VCO_ON_clk) begin - if VCO_ON_clk'event and VCO_ON_clk='1' then + PROCESS (VCO_ON_clk) BEGIN + if VCO_ON_clk'EVENT and VCO_ON_clk='1' THEN VCO_ON_q <= VCO_ON_d; - end if; - end process; + END IF; + END PROCESS; - process (VCO_OFF_clk) begin - if VCO_OFF_clk'event and VCO_OFF_clk='1' then + PROCESS (VCO_OFF_clk) BEGIN + if VCO_OFF_clk'EVENT and VCO_OFF_clk='1' THEN VCO_OFF_q <= VCO_OFF_d; - end if; - end process; + END IF; + END PROCESS; - process (VHCNT0_clk_ctrl) begin - if VHCNT0_clk_ctrl'event and VHCNT0_clk_ctrl='1' then + PROCESS (VHCNT0_clk_ctrl) BEGIN + if VHCNT0_clk_ctrl'EVENT and VHCNT0_clk_ctrl='1' THEN VHCNT_q <= VHCNT_d; - end if; - end process; + END IF; + END PROCESS; - process (SUB_PIXEL_CNT0_clk_ctrl) begin - if SUB_PIXEL_CNT0_clk_ctrl'event and SUB_PIXEL_CNT0_clk_ctrl='1' then - if SUB_PIXEL_CNT0_ena_ctrl='1' then + PROCESS (SUB_PIXEL_CNT0_clk_ctrl) BEGIN + if SUB_PIXEL_CNT0_clk_ctrl'EVENT and SUB_PIXEL_CNT0_clk_ctrl='1' THEN + if SUB_PIXEL_CNT0_ena_ctrl='1' THEN SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VVCNT0_clk_ctrl) begin - if VVCNT0_clk_ctrl'event and VVCNT0_clk_ctrl='1' then - if VVCNT0_ena_ctrl='1' then + PROCESS (VVCNT0_clk_ctrl) BEGIN + if VVCNT0_clk_ctrl'EVENT and VVCNT0_clk_ctrl='1' THEN + if VVCNT0_ena_ctrl='1' THEN VVCNT_q <= VVCNT_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VERZ2_0_clk_ctrl) begin - if VERZ2_0_clk_ctrl'event and VERZ2_0_clk_ctrl='1' then + PROCESS (VERZ2_0_clk_ctrl) BEGIN + if VERZ2_0_clk_ctrl'EVENT and VERZ2_0_clk_ctrl='1' THEN VERZ2_q <= VERZ2_d; - end if; - end process; + END IF; + END PROCESS; - process (VERZ1_0_clk_ctrl) begin - if VERZ1_0_clk_ctrl'event and VERZ1_0_clk_ctrl='1' then + PROCESS (VERZ1_0_clk_ctrl) BEGIN + if VERZ1_0_clk_ctrl'EVENT and VERZ1_0_clk_ctrl='1' THEN VERZ1_q <= VERZ1_d; - end if; - end process; + END IF; + END PROCESS; - process (VERZ0_0_clk_ctrl) begin - if VERZ0_0_clk_ctrl'event and VERZ0_0_clk_ctrl='1' then + PROCESS (VERZ0_0_clk_ctrl) BEGIN + if VERZ0_0_clk_ctrl'EVENT and VERZ0_0_clk_ctrl='1' THEN VERZ0_q <= VERZ0_d; - end if; - end process; + END IF; + END PROCESS; - process (RAND0_clk_ctrl) begin - if RAND0_clk_ctrl'event and RAND0_clk_ctrl='1' then + PROCESS (RAND0_clk_ctrl) BEGIN + if RAND0_clk_ctrl'EVENT and RAND0_clk_ctrl='1' THEN RAND_q <= RAND_d; - end if; - end process; + END IF; + END PROCESS; - process (START_ZEILE_clk) begin - if START_ZEILE_clk'event and START_ZEILE_clk='1' then - if START_ZEILE_ena='1' then + PROCESS (START_ZEILE_clk) BEGIN + if START_ZEILE_clk'EVENT and START_ZEILE_clk='1' THEN + if START_ZEILE_ena='1' THEN START_ZEILE_q <= START_ZEILE_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (SYNC_PIX_clk) begin - if SYNC_PIX_clk'event and SYNC_PIX_clk='1' then + PROCESS (SYNC_PIX_clk) BEGIN + if SYNC_PIX_clk'EVENT and SYNC_PIX_clk='1' THEN SYNC_PIX_q <= SYNC_PIX_d; - end if; - end process; + END IF; + END PROCESS; - process (SYNC_PIX1_clk) begin - if SYNC_PIX1_clk'event and SYNC_PIX1_clk='1' then + PROCESS (SYNC_PIX1_clk) BEGIN + if SYNC_PIX1_clk'EVENT and SYNC_PIX1_clk='1' THEN SYNC_PIX1_q <= SYNC_PIX1_d; - end if; - end process; + END IF; + END PROCESS; - process (SYNC_PIX2_clk) begin - if SYNC_PIX2_clk'event and SYNC_PIX2_clk='1' then + PROCESS (SYNC_PIX2_clk) BEGIN + if SYNC_PIX2_clk'EVENT and SYNC_PIX2_clk='1' THEN SYNC_PIX2_q <= SYNC_PIX2_d; - end if; - end process; + END IF; + END PROCESS; - process (ATARI_HH0_clk_ctrl) begin - if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then - if ATARI_HH24_ena_ctrl='1' then + PROCESS (ATARI_HH0_clk_ctrl) BEGIN + if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN + if ATARI_HH24_ena_ctrl='1' THEN (ATARI_HH_q(31), ATARI_HH_q(30), ATARI_HH_q(29), ATARI_HH_q(28), ATARI_HH_q(27), ATARI_HH_q(26), ATARI_HH_q(25), ATARI_HH_q(24)) <= ATARI_HH_d(31 DOWNTO 24); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HH0_clk_ctrl) begin - if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then - if ATARI_HH16_ena_ctrl='1' then + PROCESS (ATARI_HH0_clk_ctrl) BEGIN + if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN + if ATARI_HH16_ena_ctrl='1' THEN (ATARI_HH_q(23), ATARI_HH_q(22), ATARI_HH_q(21), ATARI_HH_q(20), ATARI_HH_q(19), ATARI_HH_q(18), ATARI_HH_q(17), ATARI_HH_q(16)) <= ATARI_HH_d(23 DOWNTO 16); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HH0_clk_ctrl) begin - if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then - if ATARI_HH8_ena_ctrl='1' then + PROCESS (ATARI_HH0_clk_ctrl) BEGIN + if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN + if ATARI_HH8_ena_ctrl='1' THEN (ATARI_HH_q(15), ATARI_HH_q(14), ATARI_HH_q(13), ATARI_HH_q(12), ATARI_HH_q(11), ATARI_HH_q(10), ATARI_HH_q(9), ATARI_HH_q(8)) <= ATARI_HH_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HH0_clk_ctrl) begin - if ATARI_HH0_clk_ctrl'event and ATARI_HH0_clk_ctrl='1' then - if ATARI_HH0_ena_ctrl='1' then + PROCESS (ATARI_HH0_clk_ctrl) BEGIN + if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN + if ATARI_HH0_ena_ctrl='1' THEN (ATARI_HH_q(7), ATARI_HH_q(6), ATARI_HH_q(5), ATARI_HH_q(4), ATARI_HH_q(3), ATARI_HH_q(2), ATARI_HH_q(1), ATARI_HH_q(0)) <= ATARI_HH_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VH0_clk_ctrl) begin - if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then - if ATARI_VH24_ena_ctrl='1' then + PROCESS (ATARI_VH0_clk_ctrl) BEGIN + if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN + if ATARI_VH24_ena_ctrl='1' THEN (ATARI_VH_q(31), ATARI_VH_q(30), ATARI_VH_q(29), ATARI_VH_q(28), ATARI_VH_q(27), ATARI_VH_q(26), ATARI_VH_q(25), ATARI_VH_q(24)) <= ATARI_VH_d(31 DOWNTO 24); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VH0_clk_ctrl) begin - if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then - if ATARI_VH16_ena_ctrl='1' then + PROCESS (ATARI_VH0_clk_ctrl) BEGIN + if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN + if ATARI_VH16_ena_ctrl='1' THEN (ATARI_VH_q(23), ATARI_VH_q(22), ATARI_VH_q(21), ATARI_VH_q(20), ATARI_VH_q(19), ATARI_VH_q(18), ATARI_VH_q(17), ATARI_VH_q(16)) <= ATARI_VH_d(23 DOWNTO 16); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VH0_clk_ctrl) begin - if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then - if ATARI_VH8_ena_ctrl='1' then + PROCESS (ATARI_VH0_clk_ctrl) BEGIN + if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN + if ATARI_VH8_ena_ctrl='1' THEN (ATARI_VH_q(15), ATARI_VH_q(14), ATARI_VH_q(13), ATARI_VH_q(12), ATARI_VH_q(11), ATARI_VH_q(10), ATARI_VH_q(9), ATARI_VH_q(8)) <= ATARI_VH_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VH0_clk_ctrl) begin - if ATARI_VH0_clk_ctrl'event and ATARI_VH0_clk_ctrl='1' then - if ATARI_VH0_ena_ctrl='1' then + PROCESS (ATARI_VH0_clk_ctrl) BEGIN + if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN + if ATARI_VH0_ena_ctrl='1' THEN (ATARI_VH_q(7), ATARI_VH_q(6), ATARI_VH_q(5), ATARI_VH_q(4), ATARI_VH_q(3), ATARI_VH_q(2), ATARI_VH_q(1), ATARI_VH_q(0)) <= ATARI_VH_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HL0_clk_ctrl) begin - if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then - if ATARI_HL24_ena_ctrl='1' then + PROCESS (ATARI_HL0_clk_ctrl) BEGIN + if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN + if ATARI_HL24_ena_ctrl='1' THEN (ATARI_HL_q(31), ATARI_HL_q(30), ATARI_HL_q(29), ATARI_HL_q(28), ATARI_HL_q(27), ATARI_HL_q(26), ATARI_HL_q(25), ATARI_HL_q(24)) <= ATARI_HL_d(31 DOWNTO 24); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HL0_clk_ctrl) begin - if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then - if ATARI_HL16_ena_ctrl='1' then + PROCESS (ATARI_HL0_clk_ctrl) BEGIN + if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN + if ATARI_HL16_ena_ctrl='1' THEN (ATARI_HL_q(23), ATARI_HL_q(22), ATARI_HL_q(21), ATARI_HL_q(20), ATARI_HL_q(19), ATARI_HL_q(18), ATARI_HL_q(17), ATARI_HL_q(16)) <= ATARI_HL_d(23 DOWNTO 16); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HL0_clk_ctrl) begin - if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then - if ATARI_HL8_ena_ctrl='1' then + PROCESS (ATARI_HL0_clk_ctrl) BEGIN + if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN + if ATARI_HL8_ena_ctrl='1' THEN (ATARI_HL_q(15), ATARI_HL_q(14), ATARI_HL_q(13), ATARI_HL_q(12), ATARI_HL_q(11), ATARI_HL_q(10), ATARI_HL_q(9), ATARI_HL_q(8)) <= ATARI_HL_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_HL0_clk_ctrl) begin - if ATARI_HL0_clk_ctrl'event and ATARI_HL0_clk_ctrl='1' then - if ATARI_HL0_ena_ctrl='1' then + PROCESS (ATARI_HL0_clk_ctrl) BEGIN + if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN + if ATARI_HL0_ena_ctrl='1' THEN (ATARI_HL_q(7), ATARI_HL_q(6), ATARI_HL_q(5), ATARI_HL_q(4), ATARI_HL_q(3), ATARI_HL_q(2), ATARI_HL_q(1), ATARI_HL_q(0)) <= ATARI_HL_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VL0_clk_ctrl) begin - if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then - if ATARI_VL24_ena_ctrl='1' then + PROCESS (ATARI_VL0_clk_ctrl) BEGIN + if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN + if ATARI_VL24_ena_ctrl='1' THEN (ATARI_VL_q(31), ATARI_VL_q(30), ATARI_VL_q(29), ATARI_VL_q(28), ATARI_VL_q(27), ATARI_VL_q(26), ATARI_VL_q(25), ATARI_VL_q(24)) <= ATARI_VL_d(31 DOWNTO 24); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VL0_clk_ctrl) begin - if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then - if ATARI_VL16_ena_ctrl='1' then + PROCESS (ATARI_VL0_clk_ctrl) BEGIN + if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN + if ATARI_VL16_ena_ctrl='1' THEN (ATARI_VL_q(23), ATARI_VL_q(22), ATARI_VL_q(21), ATARI_VL_q(20), ATARI_VL_q(19), ATARI_VL_q(18), ATARI_VL_q(17), ATARI_VL_q(16)) <= ATARI_VL_d(23 DOWNTO 16); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VL0_clk_ctrl) begin - if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then - if ATARI_VL8_ena_ctrl='1' then + PROCESS (ATARI_VL0_clk_ctrl) BEGIN + if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN + if ATARI_VL8_ena_ctrl='1' THEN (ATARI_VL_q(15), ATARI_VL_q(14), ATARI_VL_q(13), ATARI_VL_q(12), ATARI_VL_q(11), ATARI_VL_q(10), ATARI_VL_q(9), ATARI_VL_q(8)) <= ATARI_VL_d(15 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (ATARI_VL0_clk_ctrl) begin - if ATARI_VL0_clk_ctrl'event and ATARI_VL0_clk_ctrl='1' then - if ATARI_VL0_ena_ctrl='1' then + PROCESS (ATARI_VL0_clk_ctrl) BEGIN + if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN + if ATARI_VL0_ena_ctrl='1' THEN (ATARI_VL_q(7), ATARI_VL_q(6), ATARI_VL_q(5), ATARI_VL_q(4), ATARI_VL_q(3), ATARI_VL_q(2), ATARI_VL_q(1), ATARI_VL_q(0)) <= ATARI_VL_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HHT0_clk_ctrl) begin - if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then - if HHT8_ena_ctrl='1' then + PROCESS (HHT0_clk_ctrl) BEGIN + if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN + if HHT8_ena_ctrl='1' THEN (HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HHT0_clk_ctrl) begin - if HHT0_clk_ctrl'event and HHT0_clk_ctrl='1' then - if HHT0_ena_ctrl='1' then + PROCESS (HHT0_clk_ctrl) BEGIN + if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN + if HHT0_ena_ctrl='1' THEN (HHT_q(7), HHT_q(6), HHT_q(5), HHT_q(4), HHT_q(3), HHT_q(2), HHT_q(1), HHT_q(0)) <= HHT_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HBE0_clk_ctrl) begin - if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then - if HBE8_ena_ctrl='1' then + PROCESS (HBE0_clk_ctrl) BEGIN + if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN + if HBE8_ena_ctrl='1' THEN (HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HBE0_clk_ctrl) begin - if HBE0_clk_ctrl'event and HBE0_clk_ctrl='1' then - if HBE0_ena_ctrl='1' then + PROCESS (HBE0_clk_ctrl) BEGIN + if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN + if HBE0_ena_ctrl='1' THEN (HBE_q(7), HBE_q(6), HBE_q(5), HBE_q(4), HBE_q(3), HBE_q(2), HBE_q(1), HBE_q(0)) <= HBE_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HDB0_clk_ctrl) begin - if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then - if HDB8_ena_ctrl='1' then + PROCESS (HDB0_clk_ctrl) BEGIN + if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN + if HDB8_ena_ctrl='1' THEN (HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HDB0_clk_ctrl) begin - if HDB0_clk_ctrl'event and HDB0_clk_ctrl='1' then - if HDB0_ena_ctrl='1' then + PROCESS (HDB0_clk_ctrl) BEGIN + if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN + if HDB0_ena_ctrl='1' THEN (HDB_q(7), HDB_q(6), HDB_q(5), HDB_q(4), HDB_q(3), HDB_q(2), HDB_q(1), HDB_q(0)) <= HDB_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HDE0_clk_ctrl) begin - if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then - if HDE8_ena_ctrl='1' then + PROCESS (HDE0_clk_ctrl) BEGIN + if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN + if HDE8_ena_ctrl='1' THEN (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HDE0_clk_ctrl) begin - if HDE0_clk_ctrl'event and HDE0_clk_ctrl='1' then - if HDE0_ena_ctrl='1' then + PROCESS (HDE0_clk_ctrl) BEGIN + if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN + if HDE0_ena_ctrl='1' THEN (HDE_q(7), HDE_q(6), HDE_q(5), HDE_q(4), HDE_q(3), HDE_q(2), HDE_q(1), HDE_q(0)) <= HDE_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HBB0_clk_ctrl) begin - if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then - if HBB8_ena_ctrl='1' then + PROCESS (HBB0_clk_ctrl) BEGIN + if HBB0_clk_ctrl'EVENT and HBB0_clk_ctrl='1' THEN + if HBB8_ena_ctrl='1' THEN (HBB_q(11), HBB_q(10), HBB_q(9), HBB_q(8)) <= HBB_d(11 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HBB0_clk_ctrl) begin - if HBB0_clk_ctrl'event and HBB0_clk_ctrl='1' then - if HBB0_ena_ctrl='1' then + PROCESS (HBB0_clk_ctrl) BEGIN + if HBB0_clk_ctrl'EVENT and HBB0_clk_ctrl='1' THEN + if HBB0_ena_ctrl='1' THEN (HBB_q(7), HBB_q(6), HBB_q(5), HBB_q(4), HBB_q(3), HBB_q(2), HBB_q(1), HBB_q(0)) <= HBB_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HSS0_clk_ctrl) begin - if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then - if HSS8_ena_ctrl='1' then + PROCESS (HSS0_clk_ctrl) BEGIN + if HSS0_clk_ctrl'EVENT and HSS0_clk_ctrl='1' THEN + if HSS8_ena_ctrl='1' THEN (HSS_q(11), HSS_q(10), HSS_q(9), HSS_q(8)) <= HSS_d(11 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (HSS0_clk_ctrl) begin - if HSS0_clk_ctrl'event and HSS0_clk_ctrl='1' then - if HSS0_ena_ctrl='1' then + PROCESS (HSS0_clk_ctrl) BEGIN + if HSS0_clk_ctrl'EVENT and HSS0_clk_ctrl='1' THEN + if HSS0_ena_ctrl='1' THEN (HSS_q(7), HSS_q(6), HSS_q(5), HSS_q(4), HSS_q(3), HSS_q(2), HSS_q(1), HSS_q(0)) <= HSS_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (DOP_ZEI_clk) begin - if DOP_ZEI_clk'event and DOP_ZEI_clk='1' then + PROCESS (DOP_ZEI_clk) BEGIN + if DOP_ZEI_clk'EVENT and DOP_ZEI_clk='1' THEN DOP_ZEI_q <= DOP_ZEI_d; - end if; - end process; + END IF; + END PROCESS; - process (VBE0_clk_ctrl) begin - if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then - if VBE8_ena_ctrl='1' then + PROCESS (VBE0_clk_ctrl) BEGIN + if VBE0_clk_ctrl'EVENT and VBE0_clk_ctrl='1' THEN + if VBE8_ena_ctrl='1' THEN (VBE_q(10), VBE_q(9), VBE_q(8)) <= VBE_d(10 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VBE0_clk_ctrl) begin - if VBE0_clk_ctrl'event and VBE0_clk_ctrl='1' then - if VBE0_ena_ctrl='1' then + PROCESS (VBE0_clk_ctrl) BEGIN + if VBE0_clk_ctrl'EVENT and VBE0_clk_ctrl='1' THEN + if VBE0_ena_ctrl='1' THEN (VBE_q(7), VBE_q(6), VBE_q(5), VBE_q(4), VBE_q(3), VBE_q(2), VBE_q(1), VBE_q(0)) <= VBE_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VDB0_clk_ctrl) begin - if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then - if VDB8_ena_ctrl='1' then + PROCESS (VDB0_clk_ctrl) BEGIN + if VDB0_clk_ctrl'EVENT and VDB0_clk_ctrl='1' THEN + if VDB8_ena_ctrl='1' THEN (VDB_q(10), VDB_q(9), VDB_q(8)) <= VDB_d(10 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VDB0_clk_ctrl) begin - if VDB0_clk_ctrl'event and VDB0_clk_ctrl='1' then - if VDB0_ena_ctrl='1' then + PROCESS (VDB0_clk_ctrl) BEGIN + if VDB0_clk_ctrl'EVENT and VDB0_clk_ctrl='1' THEN + if VDB0_ena_ctrl='1' THEN (VDB_q(7), VDB_q(6), VDB_q(5), VDB_q(4), VDB_q(3), VDB_q(2), VDB_q(1), VDB_q(0)) <= VDB_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VDE0_clk_ctrl) begin - if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then - if VDE8_ena_ctrl='1' then + PROCESS (VDE0_clk_ctrl) BEGIN + if VDE0_clk_ctrl'EVENT and VDE0_clk_ctrl='1' THEN + if VDE8_ena_ctrl='1' THEN (VDE_q(10), VDE_q(9), VDE_q(8)) <= VDE_d(10 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VDE0_clk_ctrl) begin - if VDE0_clk_ctrl'event and VDE0_clk_ctrl='1' then - if VDE0_ena_ctrl='1' then + PROCESS (VDE0_clk_ctrl) BEGIN + if VDE0_clk_ctrl'EVENT and VDE0_clk_ctrl='1' THEN + if VDE0_ena_ctrl='1' THEN (VDE_q(7), VDE_q(6), VDE_q(5), VDE_q(4), VDE_q(3), VDE_q(2), VDE_q(1), VDE_q(0)) <= VDE_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VBB0_clk_ctrl) begin - if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then - if VBB8_ena_ctrl='1' then + PROCESS (VBB0_clk_ctrl) BEGIN + if VBB0_clk_ctrl'EVENT and VBB0_clk_ctrl='1' THEN + if VBB8_ena_ctrl='1' THEN (VBB_q(10), VBB_q(9), VBB_q(8)) <= VBB_d(10 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VBB0_clk_ctrl) begin - if VBB0_clk_ctrl'event and VBB0_clk_ctrl='1' then - if VBB0_ena_ctrl='1' then + PROCESS (VBB0_clk_ctrl) BEGIN + if VBB0_clk_ctrl'EVENT and VBB0_clk_ctrl='1' THEN + if VBB0_ena_ctrl='1' THEN (VBB_q(7), VBB_q(6), VBB_q(5), VBB_q(4), VBB_q(3), VBB_q(2), VBB_q(1), VBB_q(0)) <= VBB_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VSS0_clk_ctrl) begin - if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then - if VSS8_ena_ctrl='1' then + PROCESS (VSS0_clk_ctrl) BEGIN + if VSS0_clk_ctrl'EVENT and VSS0_clk_ctrl='1' THEN + if VSS8_ena_ctrl='1' THEN (VSS_q(10), VSS_q(9), VSS_q(8)) <= VSS_d(10 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VSS0_clk_ctrl) begin - if VSS0_clk_ctrl'event and VSS0_clk_ctrl='1' then - if VSS0_ena_ctrl='1' then + PROCESS (VSS0_clk_ctrl) BEGIN + if VSS0_clk_ctrl'EVENT and VSS0_clk_ctrl='1' THEN + if VSS0_ena_ctrl='1' THEN (VSS_q(7), VSS_q(6), VSS_q(5), VSS_q(4), VSS_q(3), VSS_q(2), VSS_q(1), VSS_q(0)) <= VSS_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VFT0_clk_ctrl) begin - if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then - if VFT8_ena_ctrl='1' then + PROCESS (VFT0_clk_ctrl) BEGIN + if VFT0_clk_ctrl'EVENT and VFT0_clk_ctrl='1' THEN + if VFT8_ena_ctrl='1' THEN (VFT_q(10), VFT_q(9), VFT_q(8)) <= VFT_d(10 DOWNTO 8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VFT0_clk_ctrl) begin - if VFT0_clk_ctrl'event and VFT0_clk_ctrl='1' then - if VFT0_ena_ctrl='1' then + PROCESS (VFT0_clk_ctrl) BEGIN + if VFT0_clk_ctrl'EVENT and VFT0_clk_ctrl='1' THEN + if VFT0_ena_ctrl='1' THEN (VFT_q(7), VFT_q(6), VFT_q(5), VFT_q(4), VFT_q(3), VFT_q(2), VFT_q(1), VFT_q(0)) <= VFT_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VCO0_clk_ctrl) begin - if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then - if VCO_ena(8)='1' then + PROCESS (VCO0_clk_ctrl) BEGIN + if VCO0_clk_ctrl'EVENT and VCO0_clk_ctrl='1' THEN + if VCO_ena(8)='1' THEN VCO_q(8) <= VCO_d(8); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VCO0_clk_ctrl) begin - if VCO0_clk_ctrl'event and VCO0_clk_ctrl='1' then - if VCO0_ena_ctrl='1' then + PROCESS (VCO0_clk_ctrl) BEGIN + if VCO0_clk_ctrl'EVENT and VCO0_clk_ctrl='1' THEN + if VCO0_ena_ctrl='1' THEN (VCO_q(7), VCO_q(6), VCO_q(5), VCO_q(4), VCO_q(3), VCO_q(2), VCO_q(1), VCO_q(0)) <= VCO_d(7 DOWNTO 0); - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; - process (VCNTRL0_clk_ctrl) begin - if VCNTRL0_clk_ctrl'event and VCNTRL0_clk_ctrl='1' then - if VCNTRL0_ena_ctrl='1' then + PROCESS (VCNTRL0_clk_ctrl) BEGIN + if VCNTRL0_clk_ctrl'EVENT and VCNTRL0_clk_ctrl='1' THEN + if VCNTRL0_ena_ctrl='1' THEN VCNTRL_q <= VCNTRL_d; - end if; - end if; - end process; + END IF; + END IF; + END PROCESS; -- Start of original equations @@ -1268,8 +1272,7 @@ begin -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = - "000000000000000000"); + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = "000000000000000000"); ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); CLUT_TA_clk <= MAIN_CLK; diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index a73de2d..b587e1e 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,390 +39,390 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -432,7 +432,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -442,21 +442,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -466,76 +466,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -557,301 +557,301 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index 2de15470570a5aec89d087b29e9c63673535dafc..e98d7ce0a0ea514a0aa58f4ef02b0141b7afe8a5 100644 GIT binary patch literal 4827 zcmeH~%}!H66vzK9m9TW>$^|jT5R*co7inFo6b%NWG0?a$A^o`3hL2m@f+mLO(zr13 z5nQ_Q1z7k1Zrr*s@(}Js@pq;dD214mpuLjL&ADgJ+%q$0&iv<`xz|RtTh41)1vS*v zqMj;HT}wzc+Dh_KIs?7Zw61DQ3w-g>Xi%@f1EhvlG>)7@DrpVL*D9l#PLBFIw9L2K z-j^}m)IHtOb!L1*j{+k#;SFS)zv@P>Qu9@We8wMToX09h#Fhq@l(6N^Kle)>@09UK zfREPq>igdL&{K=@nq|*tbeEmH!#n5rf*!!9H3xp?;q$uBel}T01t0d-;(Z@3g3kb( zjIZe#yaaC7u(Jf!+YmU2)pL4IdqHVsG)b>XO(}`&(Q37Eo-$-@DP_@0!c&@n3aq>0 zbkpz&ZA1js?u5lKCia@w4y2#3+u1*q6_r+(0&mEAbbM{B2iaMF-^; zIt`a)ur~$zD&TKYS3p~tnnz19MCTN3_BF+-vhMNFsn9FycvR5oVy=0!kIwKQx$Tb< zI^!=}h)i&_4V|5G>+6Zf&WL5LXZ`Q4*EqmA7&8hg*^oQ+mqHJn)a%3;~uwwx6E!RrF~r9gCEW}aaZ zMuqn@-0sxj%{uHE+eH1LB^|oHwNa2yM~1c)9y>$-rL?=%O0xzUS32d^rO=YDT?*|Y z=sD12NTg|`!=SN?;$hJ2UkZDBHSYQ{Z=2Rn&QVRyF3_<<7WgbVcghaaC;wy9TMT#o jdv_#;6Sr|$9tWL{;QIgn{v>AEkRU{?CBR=sCdc&~9A+#m literal 5478 zcmeI0&rcIU6vw|U1UP!~{iIq7$pr`o98CfQ;F|t4^XY>x}E?TUki>53e zFGQ9_EL36dRc&cWcd*iZEIa4y=0Pn%El|#3SF`QkbB}_KHS`*tRh#R-xDZXQfNBps z`{!j|_ng+2DNi&ph&FEPiKan)UKyp~pCC`tlEn&B)W&%|QWB07XCy@}#hWJOIVENC z333~`AE9>LnT^Gy*eX&Slk~$fsV^bLhpF@jX^3*@C?F^lCtX7mCHB!!LO1ac4PHZG zLd%p@P+4H7HDlE=kCnl52_Ty5@El7~8?Bg-OqNElz&dAa?K~^l#5T!QC)75={Xtat z&WPGalTC1)fz@D-oBuw|XzcLwCpVG$lg#)|8hn6))1)l)7w8r0C+^;0R@5Xq@{|Ky z)2KQLJq3_FY8hGz0nDcsr_89FE2D&&bBCtE*ekNrFpKZe_=d*rfSEz< z+%UTgK1+UesOmE@C(|$zSBKE|eVUVwWy#?KFM0QND?xFLPzjo#i`Rhp0 z8Gr60vLD}J=nT_-uM5i_{xRcxruj|th!a7O4u@q6;Ag{f2JUhE>V9+ovA4|5x_)SM zrx77;kPePqX!%apFlRT9FRpNc69kDe`5dKx(YCza9C-kH!45PtOxi5a-QoRghv)Ww z?RRN?ACTu8A4M|&=8!8*h^E&b-=*1oY&w8V7FgKLu1N3{x3v%*rhSOE n-P?A^e}R_R9GK;BzGmay5#Im*j~jOrcpo6qu3$ec86DRzGNY3V From f11629ac29015ea44a337c1405127fda27e4acc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Jan 2016 22:02:44 +0000 Subject: [PATCH 065/127] fix video base address and video counter register --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 146 +-- FPGA_Quartus_13.1/firebee1.qsf | 1472 +++++++++++++-------------- 2 files changed, 811 insertions(+), 807 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 60a152e..ed0906f 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -521,82 +521,82 @@ BEGIN END IF; END PROCESS; - PROCESS (REFRESH_TIME_clk) BEGIN - IF REFRESH_TIME_clk'event and REFRESH_TIME_clk='1' THEN - REFRESH_TIME_q <= REFRESH_TIME_d; - END IF; - END PROCESS; + PROCESS (REFRESH_TIME_clk) + BEGIN + IF REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' THEN + REFRESH_TIME_q <= REFRESH_TIME_d; + END IF; + END PROCESS; - PROCESS (VIDEO_BASE_L_D0_clk_ctrl) BEGIN - IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN - VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; - END IF; - END IF; - END PROCESS; + PROCESS (VIDEO_BASE_L_D0_clk_ctrl) + BEGIN + IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN + VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; + END IF; + END IF; + END PROCESS; - PROCESS (VIDEO_BASE_M_D0_clk_ctrl) BEGIN - IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN - VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; - END IF; - END IF; - END PROCESS; + PROCESS (VIDEO_BASE_M_D0_clk_ctrl) + BEGIN + IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN + VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; + END IF; + END IF; + END PROCESS; - PROCESS (VIDEO_BASE_H_D0_clk_ctrl) BEGIN - IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN - VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; - END IF; - END IF; - END PROCESS; + PROCESS (VIDEO_BASE_H_D0_clk_ctrl) + BEGIN + IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN + VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; + END IF; + END IF; + END PROCESS; - PROCESS (VIDEO_BASE_X_D0_clk_ctrl) BEGIN - IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN - VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; - END IF; - END IF; - END PROCESS; + PROCESS (VIDEO_BASE_X_D0_clk_ctrl) + BEGIN + IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN + IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN + VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; + END IF; + END IF; + END PROCESS; - PROCESS (VIDEO_ADR_CNT0_clk_ctrl) BEGIN - IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN - IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN - VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; - END IF; - END IF; - END PROCESS; + PROCESS (VIDEO_ADR_CNT0_clk_ctrl) + BEGIN + IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN + IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN + VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; + END IF; + END IF; + END PROCESS; --- Start of original equations - LINE <= FB_SIZE0 and FB_SIZE1; + -- Start of original equations + LINE <= FB_SIZE0 and FB_SIZE1; --- BYT SELECT --- ADR==0 --- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and - FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + -- BYT SELECT + -- ADR==0 + -- LONG UND LINE + FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); --- ADR==1 --- HIGH WORD --- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not - FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not - FB_SIZE1) and (not FB_SIZE0)); + -- ADR==1 + -- HIGH WORD + -- LONG UND LINE + FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); --- ADR==2 --- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and - FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + -- ADR==2 + -- LONG UND LINE + FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); --- ADR==3 --- LOW WORD --- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not - FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) - and (not FB_SIZE0)); + -- ADR==3 + -- LOW WORD + -- LONG UND LINE + FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR_0_clk_ctrl <= MAIN_CLK; + -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR_0_clk_ctrl <= MAIN_CLK; PROCESS (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) @@ -1331,17 +1331,21 @@ BEGIN -- 8204,5/2 VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000010"); --- FB_AD[31..24] = lpm_bustri_BYT( --- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) --- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), --- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or + -- FB_AD[31..24] = lpm_bustri_BYT( + -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) + -- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), + -- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + fb_ad(31 DOWNTO 24) <= "00000" & video_base_x_d_d WHEN video_base_h and not nfb_oe ELSE + "00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h and not nfb_oe ELSE + (OTHERS => 'Z'); + + u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 DOWNTO 0)) or (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 DOWNTO 8)) or (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 DOWNTO 16)); - u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L + u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); FB_AD(23 DOWNTO 16) <= u0_tridata; diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index b587e1e..a73de2d 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,390 +39,390 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -432,7 +432,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -442,21 +442,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -466,76 +466,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -557,301 +557,301 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name SDC_FILE firebee1.sdc +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From 11bd410c153b694be5aeb5f181e95a47a8eb3d35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 15 Jan 2016 08:37:40 +0000 Subject: [PATCH 066/127] simplify processes --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 26 +++++++++++++++----------- FPGA_Quartus_13.1/firebee1.sdc | 22 ++++++++++++++-------- 2 files changed, 29 insertions(+), 19 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index ed0906f..e247a73 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -603,25 +603,27 @@ BEGIN VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0); BEGIN FB_REGDDR_d <= FB_REGDDR_q; - (FB_VDOE(0), FB_VDOE(1)) <= std_logic_vector'("00"); - (FB_LE(0), FB_LE(1), FB_VDOE(2), FB_LE(2), FB_VDOE(3), FB_LE(3), - VIDEO_DDR_TA, BUS_CYC_END) <= std_logic_vector'("00000000"); + fb_vdoe <= (OTHERS => '0'); + fb_le <= (OTHERS => '0'); + video_ddr_ta <= '0'; + bus_cyc_end <= '0'; + stdVec3 := FB_REGDDR_q; CASE stdVec3 IS WHEN "000" => FB_LE(0) <= not nFB_WR; -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR)))='1' THEN + IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' THEN FB_REGDDR_d <= "001"; ELSE FB_REGDDR_d <= "000"; END IF; WHEN "001" => - IF (DDR_CS_q)='1' THEN + IF DDR_CS_q = '1' THEN FB_LE(0) <= not nFB_WR; VIDEO_DDR_TA <= vcc; - IF (LINE)='1' THEN + IF LINE ='1' THEN FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); FB_REGDDR_d <= "010"; ELSE @@ -634,7 +636,7 @@ BEGIN END IF; WHEN "010" => - IF (DDR_CS_q)='1' THEN + IF DDR_CS_q = '1' THEN FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(1) <= not nFB_WR; VIDEO_DDR_TA <= vcc; @@ -644,12 +646,12 @@ BEGIN END IF; WHEN "011" => - IF (DDR_CS_q)='1' THEN + IF DDR_CS_q ='1' THEN FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(2) <= not nFB_WR; -- BEI LINE WRITE EVT. WARTEN - IF ((not BUS_CYC_q) and LINE and (not nFB_WR))='1' THEN + IF ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' THEN FB_REGDDR_d <= "011"; ELSE VIDEO_DDR_TA <= vcc; @@ -660,7 +662,7 @@ BEGIN END IF; WHEN "100" => - IF (DDR_CS_q)='1' THEN + IF DDR_CS_q = '1' THEN FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_LE(3) <= not nFB_WR; VIDEO_DDR_TA <= vcc; @@ -672,7 +674,7 @@ BEGIN WHEN others => END CASE; - stdVec3 := (others=>'0'); -- no storage needed + stdVec3 := (OTHERS => '0'); -- no storage needed END PROCESS; -- DDR STEUERUNG ----------------------------------------------------- @@ -690,6 +692,7 @@ BEGIN nVRAS <= not VRAS; nVCAS <= not VCAS; nVWE <= not VWE; + SR_DDR_WR_clk <= DDRCLK0; SR_DDRWR_D_SEL_clk <= DDRCLK0; SR_VDMP0_clk_ctrl <= DDRCLK0; @@ -697,6 +700,7 @@ BEGIN CPU_AC_clk <= DDRCLK0; FIFO_AC_clk <= DDRCLK0; BLITTER_AC_clk <= DDRCLK0; + DDRWR_D_SEL1 <= BLITTER_AC_q; -- SELECT LOGIC diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 4753c0c..a8f4131 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -118,19 +118,25 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs] + +#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] +#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} +#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] +#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] + +#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] +#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} +#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}] +#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} # video RAM access set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] From 0fe61bedef44acc3cbb068490696c7abb3019984 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 15 Jan 2016 17:38:29 +0000 Subject: [PATCH 067/127] fix output delay --- FPGA_Quartus_13.1/firebee1.sdc | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index a8f4131..189849d 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -130,8 +130,8 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs # Set Output Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} @@ -139,20 +139,20 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_output #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA} # video RAM access -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}] +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}] -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} -set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} +#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]} #************************************************************** # Set Clock Groups From 7bf4d912a0417cffc1a6d8378c6ad9f79e443f2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 16 Jan 2016 21:38:17 +0000 Subject: [PATCH 068/127] fix timing --- FPGA_Quartus_13.1/Video/video.vhd | 4 +- .../Video/video_mod_mux_clutctr.vhd | 274 +++++++++--------- FPGA_Quartus_13.1/firebee1.qsf | 20 +- FPGA_Quartus_13.1/firebee1.qws | Bin 4827 -> 5228 bytes FPGA_Quartus_13.1/firebee1.sdc | 12 +- FPGA_Quartus_13.1/firebee1.vhd | 49 +++- FPGA_Quartus_13.1/firebee_groups.sdc | 42 +-- 7 files changed, 232 insertions(+), 169 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index f15df82..c209bd1 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -723,8 +723,8 @@ ARCHITECTURE rtl OF video IS SIGNAL FIFO_RDE : std_logic; SIGNAL FIFO_WRE : std_logic; SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic; - SIGNAL pixel_clk_i : std_logic; + SIGNAL nFB_BURST : std_logic := '0'; + SIGNAL pixel_clk_i : std_logic; SIGNAL SR_BLITTER_DACK : std_logic; SIGNAL SR_DDR_FB : std_logic; SIGNAL SR_DDR_WR : std_logic; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 50ec8f9..0ea49e4 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -187,18 +187,18 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL VERZ0 : std_logic_vector(9 DOWNTO 0); SIGNAL VERZ0_d : std_logic_vector(9 DOWNTO 0); SIGNAL VERZ0_q : std_logic_vector(9 DOWNTO 0); - SIGNAL RAND : std_logic_vector(6 DOWNTO 0); + SIGNAL RAND : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL RAND_d : std_logic_vector(6 DOWNTO 0); SIGNAL RAND_q : std_logic_vector(6 DOWNTO 0); SIGNAL CCSEL_d : std_logic_vector(2 DOWNTO 0); SIGNAL CCSEL_q : std_logic_vector(2 DOWNTO 0); - SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL ATARI_HH_d : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_HH_q : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VH : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VH_d : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VH_q : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL ATARI_HL_d : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_HL_q : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VL : std_logic_vector(31 DOWNTO 0); @@ -212,10 +212,10 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL H_TOTAL : std_logic_vector(11 DOWNTO 0); SIGNAL HDIS_LEN : std_logic_vector(11 DOWNTO 0); SIGNAL MULF : std_logic_vector(5 DOWNTO 0); - SIGNAL HHT : std_logic_vector(11 DOWNTO 0); + SIGNAL HHT : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL HHT_d : std_logic_vector(11 DOWNTO 0); SIGNAL HHT_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HBE : std_logic_vector(11 DOWNTO 0); + SIGNAL HBE : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL HBE_d : std_logic_vector(11 DOWNTO 0); SIGNAL HBE_q : std_logic_vector(11 DOWNTO 0); SIGNAL HDB : std_logic_vector(11 DOWNTO 0); @@ -227,7 +227,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL HBB : std_logic_vector(11 DOWNTO 0); SIGNAL HBB_d : std_logic_vector(11 DOWNTO 0); SIGNAL HBB_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HSS : std_logic_vector(11 DOWNTO 0); + SIGNAL HSS : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL HSS_d : std_logic_vector(11 DOWNTO 0); SIGNAL HSS_q : std_logic_vector(11 DOWNTO 0); SIGNAL RAND_OBEN : std_logic_vector(10 DOWNTO 0); @@ -258,7 +258,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL VCO_d : std_logic_vector(8 DOWNTO 0); SIGNAL VCO_ena : std_logic_vector(8 DOWNTO 0); SIGNAL VCO_q : std_logic_vector(8 DOWNTO 0); - SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0); + SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL VCNTRL_d : std_logic_vector(3 DOWNTO 0); SIGNAL VCNTRL_q : std_logic_vector(3 DOWNTO 0); SIGNAL u0_data : std_logic_vector(15 DOWNTO 0); @@ -1825,17 +1825,17 @@ BEGIN RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); - hs_start <= hss WHEN acp_video_on ELSE - atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE - atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE - std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; + hs_start <= hss_q WHEN acp_video_on ELSE + atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE + atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE + std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; -- HS_START[] = HSS[] & ACP_VIDEO_ON -- # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- -- - h_total <= hht WHEN acp_video_on ELSE + h_total <= hht_q WHEN acp_video_on ELSE atari_hl(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE atari_hh(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and not vcntrl(2) ELSE std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) WHEN not acp_video_on and not atari_sync; @@ -1844,158 +1844,160 @@ BEGIN -- # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and + RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or (std_logic_vector'('0' & VBE_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or + + VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and + VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or (std_logic_vector'('0' & VDE_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or + RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 DOWNTO 0) + VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 DOWNTO 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 DOWNTO 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 DOWNTO 16) + V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 DOWNTO 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 DOWNTO 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); --- ZÄHLER - LAST_clk <= PIXEL_CLK; - LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); - VHCNT0_clk_ctrl <= PIXEL_CLK; - VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); - VVCNT0_clk_ctrl <= PIXEL_CLK; - VVCNT0_ena_ctrl <= LAST_q; - VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); + -- ZÄHLER + LAST_clk <= PIXEL_CLK; + LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); + VHCNT0_clk_ctrl <= PIXEL_CLK; + VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); + VVCNT0_clk_ctrl <= PIXEL_CLK; + VVCNT0_ena_ctrl <= LAST_q; + VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); --- DISPLAY ON OFF - DPO_ZL_clk <= PIXEL_CLK; + -- DISPLAY ON OFF + DPO_ZL_clk <= PIXEL_CLK; --- 1 ZEILE DAVOR ON OFF - DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); + -- 1 ZEILE DAVOR ON OFF + DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); --- AM ZEILENENDE ÜBERNEHMEN - DPO_ZL_ena <= LAST_q; - DPO_ON_clk <= PIXEL_CLK; + -- AM ZEILENENDE ÜBERNEHMEN + DPO_ZL_ena <= LAST_q; + DPO_ON_clk <= PIXEL_CLK; --- BESSER EINZELN WEGEN TIMING - DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); - DPO_OFF_clk <= PIXEL_CLK; - DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); - DISP_ON_clk <= PIXEL_CLK; - DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); + -- BESSER EINZELN WEGEN TIMING + DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); + DPO_OFF_clk <= PIXEL_CLK; + DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); + DISP_ON_clk <= PIXEL_CLK; + DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); --- DATENTRANSFER ON OFF - VCO_ON_clk <= PIXEL_CLK; + -- DATENTRANSFER ON OFF + VCO_ON_clk <= PIXEL_CLK; --- BESSER EINZELN WEGEN TIMING - VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); - VCO_OFF_clk <= PIXEL_CLK; - VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); - VCO_ZL_clk <= PIXEL_CLK; + -- BESSER EINZELN WEGEN TIMING + VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); + VCO_OFF_clk <= PIXEL_CLK; + VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); + VCO_ZL_clk <= PIXEL_CLK; --- AM ZEILENENDE ÜBERNEHMEN - VCO_ZL_ena <= LAST_q; + -- AM ZEILENENDE ÜBERNEHMEN + VCO_ZL_ena <= LAST_q; --- 1 ZEILE DAVOR ON OFF - VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); - VDTRON_clk <= PIXEL_CLK; - VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); + -- 1 ZEILE DAVOR ON OFF + VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); + VDTRON_clk <= PIXEL_CLK; + VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); --- VERZÖGERUNG UND SYNC - HSYNC_START_clk <= PIXEL_CLK; - HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); - HSYNC_I0_clk_ctrl <= PIXEL_CLK; - HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or + -- VERZÖGERUNG UND SYNC + HSYNC_START_clk <= PIXEL_CLK; + HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); + HSYNC_I0_clk_ctrl <= PIXEL_CLK; + HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or ((std_logic_vector(unsigned(HSYNC_I_q) - 1)) and sizeIt(not HSYNC_START_q,8) and sizeIt(to_std_logic(HSYNC_I_q /= "00000000"),8)); - VSYNC_START_clk <= PIXEL_CLK; - VSYNC_START_ena <= LAST_q; + VSYNC_START_clk <= PIXEL_CLK; + VSYNC_START_ena <= LAST_q; --- start am ende der Zeile vor dem vsync - VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); - VSYNC_I0_clk_ctrl <= PIXEL_CLK; + -- start am ende der Zeile vor dem vsync + VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); + VSYNC_I0_clk_ctrl <= PIXEL_CLK; --- start am ende der Zeile vor dem vsync - VSYNC_I0_ena_ctrl <= LAST_q; + -- start am ende der Zeile vor dem vsync + VSYNC_I0_ena_ctrl <= LAST_q; --- 3 zeilen vsync length --- runterzählen bis 0 - VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or + -- 3 zeilen vsync length + -- runterzählen bis 0 + VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); - VERZ2_0_clk_ctrl <= PIXEL_CLK; - VERZ1_0_clk_ctrl <= PIXEL_CLK; - VERZ0_0_clk_ctrl <= PIXEL_CLK; + VERZ2_0_clk_ctrl <= PIXEL_CLK; + VERZ1_0_clk_ctrl <= PIXEL_CLK; + VERZ0_0_clk_ctrl <= PIXEL_CLK; - (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & + (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); - (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & + (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); - (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & + (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & VERZ1_q(2) & VERZ0_q(2)); - (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & + (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & VERZ1_q(3) & VERZ0_q(3)); - (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & + (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & VERZ1_q(4) & VERZ0_q(4)); - (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & + (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & VERZ1_q(5) & VERZ0_q(5)); - (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & + (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & VERZ1_q(6) & VERZ0_q(6)); - (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & + (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & VERZ1_q(7) & VERZ0_q(7)); - (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & + (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & VERZ1_q(8) & VERZ0_q(8)); - VERZ0_d(0) <= DISP_ON_q; + VERZ0_d(0) <= DISP_ON_q; --- VERZ[1][0] = HSYNC_I[] != 0; --- NUR MÖGLICH WENN BEIDE - VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') + -- VERZ[1][0] = HSYNC_I[] != 0; + -- NUR MÖGLICH WENN BEIDE + VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); --- NUR MÖGLICH WENN BEIDE - VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') + -- NUR MÖGLICH WENN BEIDE + VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); - nBLANK_clk <= PIXEL_CLK; + nBLANK_clk <= PIXEL_CLK; --- nBLANK = VERZ[0][8]; + -- nBLANK = VERZ[0][8]; nblank_d <= verz0_q(8); --- nBLANK_d <= DISP_ON_q; - HSYNC_clk <= PIXEL_CLK; + + -- nBLANK_d <= DISP_ON_q; + HSYNC_clk <= PIXEL_CLK; --- HSYNC = VERZ[1][9]; --- NUR MÖGLICH WENN BEIDE - HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and + -- HSYNC = VERZ[1][9]; + -- NUR MÖGLICH WENN BEIDE + HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); - VSYNC_clk <= PIXEL_CLK; + VSYNC_clk <= PIXEL_CLK; --- VSYNC = VERZ[2][9]; --- NUR MÖGLICH WENN BEIDE + -- VSYNC = VERZ[2][9]; + -- NUR MÖGLICH WENN BEIDE VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); nSYNC <= gnd; --- RANDFARBE MACHEN ------------------------------------ + -- RANDFARBE MACHEN ------------------------------------ RAND0_clk_ctrl <= PIXEL_CLK; RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); RAND_d(1) <= RAND_q(0); @@ -2005,63 +2007,63 @@ BEGIN RAND_d(5) <= RAND_q(4); RAND_d(6) <= RAND_q(5); --- RAND_ON = RAND[6]; + -- RAND_ON = RAND[6]; rand_on <= rand(6); -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); --- -------------------------------------------------------- - CLR_FIFO_clk <= PIXEL_CLK; - CLR_FIFO_ena <= LAST_q; + -- -------------------------------------------------------- + CLR_FIFO_clk <= PIXEL_CLK; + CLR_FIFO_ena <= LAST_q; --- IN LETZTER ZEILE LÖSCHEN - CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); - START_ZEILE_clk <= PIXEL_CLK; - START_ZEILE_ena <= LAST_q; + -- IN LETZTER ZEILE LÖSCHEN + CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); + START_ZEILE_clk <= PIXEL_CLK; + START_ZEILE_ena <= LAST_q; --- ZEILE 1 - START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); - SYNC_PIX_clk <= PIXEL_CLK; + -- ZEILE 1 + START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); + SYNC_PIX_clk <= PIXEL_CLK; --- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; - SYNC_PIX1_clk <= PIXEL_CLK; + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; + SYNC_PIX1_clk <= PIXEL_CLK; --- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; - SYNC_PIX2_clk <= PIXEL_CLK; + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; + SYNC_PIX2_clk <= PIXEL_CLK; --- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; - SUB_PIXEL_CNT0_clk_ctrl <= PIXEL_CLK; - SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; + SUB_PIXEL_CNT0_clk_ctrl <= PIXEL_CLK; + SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; --- count up if display on sonst clear bei sync pix - SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - FIFO_RDE_clk <= PIXEL_CLK; + -- count up if display on sonst clear bei sync pix + SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); + FIFO_RDE_clk <= PIXEL_CLK; --- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or + -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or (to_std_logic(SUB_PIXEL_CNT_q(5 DOWNTO 0) = "000001") and COLOR2) or (to_std_logic(SUB_PIXEL_CNT_q(4 DOWNTO 0) = "00001") and COLOR4) or (to_std_logic(SUB_PIXEL_CNT_q(3 DOWNTO 0) = "0001") and COLOR8) or (to_std_logic(SUB_PIXEL_CNT_q(2 DOWNTO 0) = "001") and COLOR16) or (to_std_logic(SUB_PIXEL_CNT_q(1 DOWNTO 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); - CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; - CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; + CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); + CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; + CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; --- Assignments added to explicitly combine the --- effects of multiple drivers in the source - COLOR16 <= COLOR16_1 or COLOR16_2; - COLOR4 <= COLOR4_1 or COLOR4_2; - COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; - COLOR8 <= COLOR8_1 or COLOR8_2; + -- Assignments added to explicitly combine the + -- effects of multiple drivers in the source + COLOR16 <= COLOR16_1 or COLOR16_2; + COLOR4 <= COLOR4_1 or COLOR4_2; + COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; + COLOR8 <= COLOR8_1 or COLOR8_2; --- Define power SIGNAL(s) - gnd <= '0'; + -- Define power SIGNAL(s) + gnd <= '0'; END ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index a73de2d..5e7140b 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -365,12 +365,12 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK @@ -664,7 +664,7 @@ set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON @@ -672,14 +672,18 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd set_global_assignment -name VHDL_FILE Video/mux41.vhd set_global_assignment -name VHDL_FILE Video/mux41_5.vhd set_global_assignment -name VHDL_FILE Video/mux41_4.vhd @@ -854,4 +858,6 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index e98d7ce0a0ea514a0aa58f4ef02b0141b7afe8a5..80b4fbfd39e1e937c7752e40f53896c9ec813214 100644 GIT binary patch literal 5228 zcmeI0OHWf#5Xa{h6k?2Vr7l5{}x;RkS|OINPlx^N?kzyI6|!j+gvfHtJ3IgdGyIdkUx&&-`(>9vj2Wz$x$n$>OG zo>;}IHU%|D--Ja>IzoPC1NMlq8F~gN%gn0K8l{}FdGDWvgGNUw7s%6$&25eh*iE}@ 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zbkpz&ZA1js?u5lKCia@w4y2#3+u1*q6_r+(0&mEAbbM{B2iaMF-^; zIt`a)ur~$zD&TKYS3p~tnnz19MCTN3_BF+-vhMNFsn9FycvR5oVy=0!kIwKQx$Tb< zI^!=}h)i&_4V|5G>+6Zf&WL5LXZ`Q4*EqmA7&8hg*^oQ+mqHJn)a%3;~uwwx6E!RrF~r9gCEW}aaZ zMuqn@-0sxj%{uHE+eH1LB^|oHwNa2yM~1c)9y>$-rL?=%O0xzUS32d^rO=YDT?*|Y z=sD12NTg|`!=SN?;$hJ2UkZDBHSYQ{Z=2Rn&QVRyF3_<<7WgbVcghaaC;wy9TMT#o jdv_#;6Sr|$9tWL{;QIgn{v>AEkRU{?CBR=sCdc&~9A+#m diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 189849d..993879a 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -109,8 +109,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00 +#set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00 +#set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00 derive_clock_uncertainty @@ -118,8 +118,8 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs] +# set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs] +# set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs] #set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] #set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} @@ -130,8 +130,8 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] +# set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] +# set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 5ebfa52..d7c0db0 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -242,6 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS ); END COMPONENT altpll4; + COMPONENT Video + PORT + ( + FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + MAIN_CLK : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DDR_SYNC_66M : IN STD_LOGIC; + CLK33M : IN STD_LOGIC; + CLK25M : IN STD_LOGIC; + CLK_VIDEO : IN STD_LOGIC; + VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + VR_BUSY : IN STD_LOGIC; + VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + nBLANK : OUT STD_LOGIC; + VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + nVWE : OUT STD_LOGIC; + nVCAS : OUT STD_LOGIC; + nVRAS : OUT STD_LOGIC; + nVCS : OUT STD_LOGIC; + VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + nPD_VGA : OUT STD_LOGIC; + VCKE : OUT STD_LOGIC; + VSYNC : OUT STD_LOGIC; + HSYNC : OUT STD_LOGIC; + nSYNC : OUT STD_LOGIC; + VIDEO_TA : OUT STD_LOGIC; + PIXEL_CLK : OUT STD_LOGIC; + BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + VIDEO_RECONFIG : OUT STD_LOGIC; + VR_WR : OUT STD_LOGIC; + VR_RD : OUT STD_LOGIC; + VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; BEGIN nDREQ1 <= nDACK1; @@ -472,7 +519,7 @@ BEGIN ); - i_video : work.video + i_video : video PORT MAP ( MAIN_CLK => MAIN_CLK, diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 97bcc70..3924ec3 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -90,6 +90,9 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por #************************************************************** derive_pll_clocks + +create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q +create_generated_clock -divide_by 2 -source i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2] i_video|i_video_mod_mux_clutctr|CLK13M_q # PIXEL_CLK is either # CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO @@ -109,8 +112,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.0 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.0 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.5 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.5 derive_clock_uncertainty @@ -133,38 +136,43 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outpu #************************************************************** # Set Clock Groups #************************************************************** - + set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \ [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] \ -group [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ - [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ - [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ - [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ - -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ + -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ - -group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] - + -group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + -group [get_clocks {video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK17M_q}] \ + -group [get_clocks {video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q}] + + #************************************************************** # Set False Path #************************************************************** -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] -set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] -set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] - - #************************************************************** # Set Multicycle Path #************************************************************** -set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 +#set_multicycle_path -start -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK17M_q -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 +#set_multicycle_path -start -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 + +#set_multicycle_path -end -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q -to MAIN_CLK 2 + +#set_multicycle_path -start -from MAIN_CLK -to i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 +#set_multicycle_path -start -from MAIN_CLK -to i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1] 2 +#set_multicycle_path -start -from MAIN_CLK -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 + +# set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 #************************************************************** # Set Maximum Delay From 58a69ffc5f9ca722a94a2318d7eda19b2d5a581b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 16 Jan 2016 22:04:05 +0000 Subject: [PATCH 069/127] reformat --- .../Interrupt_Handler/interrupt_handler.vhd | 244 +++++++++--------- 1 file changed, 116 insertions(+), 128 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 425a621..2c56b5b 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -795,149 +795,137 @@ BEGIN END IF; END PROCESS; - PROCESS (INT_LATCH0_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(0)='0' THEN - INT_LATCH_q(0) <= '0'; - ELSIF INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' THEN - INT_LATCH_q(0) <= INT_LATCH_d(0); - END IF; - END PROCESS; + PROCESS (INT_LATCH0_clk_1, INT_LATCH_clrn) + BEGIN + IF INT_LATCH_clrn(0)='0' THEN + INT_LATCH_q(0) <= '0'; + ELSIF INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' THEN + INT_LATCH_q(0) <= INT_LATCH_d(0); + END IF; + END PROCESS; - PROCESS (INT_CLEAR0_clk_ctrl) BEGIN - IF INT_CLEAR0_clk_ctrl'event and INT_CLEAR0_clk_ctrl='1' THEN - INT_CLEAR_q <= INT_CLEAR_d; - END IF; - END PROCESS; + PROCESS (INT_CLEAR0_clk_ctrl) + BEGIN + IF INT_CLEAR0_clk_ctrl'event and INT_CLEAR0_clk_ctrl='1' THEN + INT_CLEAR_q <= INT_CLEAR_d; + END IF; + END PROCESS; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN - (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), - INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= - std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA24_ena_ctrl='1' THEN - (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), - INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) - <= INT_ENA_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) + BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), + INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA24_ena_ctrl='1' THEN + (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= INT_ENA_d(31 DOWNTO 24); + END IF; + END IF; + END PROCESS; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN - (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), - INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= - std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA16_ena_ctrl='1' THEN - (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), - INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) - <= INT_ENA_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA16_ena_ctrl='1' THEN + (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= INT_ENA_d(23 DOWNTO 16); + END IF; + END IF; + END PROCESS; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN - (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), - INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= - std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA8_ena_ctrl='1' THEN - (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), - INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= - INT_ENA_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA8_ena_ctrl='1' THEN + (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= INT_ENA_d(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN - (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), - INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= - std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA0_ena_ctrl='1' THEN - (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), - INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= - INT_ENA_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN + IF INT_ENA0_clrn_ctrl='0' THEN + (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= std_logic_vector'("00000000"); + ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN + IF INT_ENA0_ena_ctrl='1' THEN + (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= INT_ENA_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (INT_L0_clk_ctrl, INT_L0_clrn_ctrl) BEGIN - IF INT_L0_clrn_ctrl='0' THEN - INT_L_q <= std_logic_vector'("0000000000"); - ELSIF INT_L0_clk_ctrl'event and INT_L0_clk_ctrl='1' THEN - INT_L_q <= INT_L_d; - END IF; - END PROCESS; + PROCESS (INT_L0_clk_ctrl, INT_L0_clrn_ctrl) BEGIN + IF INT_L0_clrn_ctrl='0' THEN + INT_L_q <= std_logic_vector'("0000000000"); + ELSIF INT_L0_clk_ctrl'event and INT_L0_clk_ctrl='1' THEN + INT_L_q <= INT_L_d; + END IF; + END PROCESS; - PROCESS (INT_LA9_0_clk_ctrl, INT_LA9_0_clrn_ctrl) BEGIN - IF INT_LA9_0_clrn_ctrl='0' THEN - INT_LA9_q <= std_logic_vector'("0000"); - ELSIF INT_LA9_0_clk_ctrl'event and INT_LA9_0_clk_ctrl='1' THEN - INT_LA9_q <= INT_LA9_d; - END IF; - END PROCESS; + PROCESS (INT_LA9_0_clk_ctrl, INT_LA9_0_clrn_ctrl) BEGIN + IF INT_LA9_0_clrn_ctrl='0' THEN + INT_LA9_q <= std_logic_vector'("0000"); + ELSIF INT_LA9_0_clk_ctrl'event and INT_LA9_0_clk_ctrl='1' THEN + INT_LA9_q <= INT_LA9_d; + END IF; + END PROCESS; - PROCESS (INT_LA8_0_clk_ctrl, INT_LA8_0_clrn_ctrl) BEGIN - IF INT_LA8_0_clrn_ctrl='0' THEN - INT_LA8_q <= std_logic_vector'("0000"); - ELSIF INT_LA8_0_clk_ctrl'event and INT_LA8_0_clk_ctrl='1' THEN - INT_LA8_q <= INT_LA8_d; - END IF; - END PROCESS; + PROCESS (INT_LA8_0_clk_ctrl, INT_LA8_0_clrn_ctrl) BEGIN + IF INT_LA8_0_clrn_ctrl='0' THEN + INT_LA8_q <= std_logic_vector'("0000"); + ELSIF INT_LA8_0_clk_ctrl'event and INT_LA8_0_clk_ctrl='1' THEN + INT_LA8_q <= INT_LA8_d; + END IF; + END PROCESS; - PROCESS (INT_LA7_0_clk_ctrl, INT_LA7_0_clrn_ctrl) BEGIN - IF INT_LA7_0_clrn_ctrl='0' THEN - INT_LA7_q <= std_logic_vector'("0000"); - ELSIF INT_LA7_0_clk_ctrl'event and INT_LA7_0_clk_ctrl='1' THEN - INT_LA7_q <= INT_LA7_d; - END IF; - END PROCESS; + PROCESS (INT_LA7_0_clk_ctrl, INT_LA7_0_clrn_ctrl) BEGIN + IF INT_LA7_0_clrn_ctrl='0' THEN + INT_LA7_q <= std_logic_vector'("0000"); + ELSIF INT_LA7_0_clk_ctrl'event and INT_LA7_0_clk_ctrl='1' THEN + INT_LA7_q <= INT_LA7_d; + END IF; + END PROCESS; - PROCESS (INT_LA6_0_clk_ctrl, INT_LA6_0_clrn_ctrl) BEGIN - IF INT_LA6_0_clrn_ctrl='0' THEN - INT_LA6_q <= std_logic_vector'("0000"); - ELSIF INT_LA6_0_clk_ctrl'event and INT_LA6_0_clk_ctrl='1' THEN - INT_LA6_q <= INT_LA6_d; - END IF; - END PROCESS; + PROCESS (INT_LA6_0_clk_ctrl, INT_LA6_0_clrn_ctrl) BEGIN + IF INT_LA6_0_clrn_ctrl='0' THEN + INT_LA6_q <= std_logic_vector'("0000"); + ELSIF INT_LA6_0_clk_ctrl'event and INT_LA6_0_clk_ctrl='1' THEN + INT_LA6_q <= INT_LA6_d; + END IF; + END PROCESS; - PROCESS (INT_LA5_0_clk_ctrl, INT_LA5_0_clrn_ctrl) BEGIN - IF INT_LA5_0_clrn_ctrl='0' THEN - INT_LA5_q <= std_logic_vector'("0000"); - ELSIF INT_LA5_0_clk_ctrl'event and INT_LA5_0_clk_ctrl='1' THEN - INT_LA5_q <= INT_LA5_d; - END IF; - END PROCESS; + PROCESS (INT_LA5_0_clk_ctrl, INT_LA5_0_clrn_ctrl) BEGIN + IF INT_LA5_0_clrn_ctrl='0' THEN + INT_LA5_q <= std_logic_vector'("0000"); + ELSIF INT_LA5_0_clk_ctrl'event and INT_LA5_0_clk_ctrl='1' THEN + INT_LA5_q <= INT_LA5_d; + END IF; + END PROCESS; - PROCESS (INT_LA4_0_clk_ctrl, INT_LA4_0_clrn_ctrl) BEGIN - IF INT_LA4_0_clrn_ctrl='0' THEN - INT_LA4_q <= std_logic_vector'("0000"); - ELSIF INT_LA4_0_clk_ctrl'event and INT_LA4_0_clk_ctrl='1' THEN - INT_LA4_q <= INT_LA4_d; - END IF; - END PROCESS; + PROCESS (INT_LA4_0_clk_ctrl, INT_LA4_0_clrn_ctrl) BEGIN + IF INT_LA4_0_clrn_ctrl='0' THEN + INT_LA4_q <= std_logic_vector'("0000"); + ELSIF INT_LA4_0_clk_ctrl'event and INT_LA4_0_clk_ctrl='1' THEN + INT_LA4_q <= INT_LA4_d; + END IF; + END PROCESS; - PROCESS (INT_LA3_0_clk_ctrl, INT_LA3_0_clrn_ctrl) BEGIN - IF INT_LA3_0_clrn_ctrl='0' THEN - INT_LA3_q <= std_logic_vector'("0000"); - ELSIF INT_LA3_0_clk_ctrl'event and INT_LA3_0_clk_ctrl='1' THEN - INT_LA3_q <= INT_LA3_d; - END IF; - END PROCESS; + PROCESS (INT_LA3_0_clk_ctrl, INT_LA3_0_clrn_ctrl) BEGIN + IF INT_LA3_0_clrn_ctrl='0' THEN + INT_LA3_q <= std_logic_vector'("0000"); + ELSIF INT_LA3_0_clk_ctrl'event and INT_LA3_0_clk_ctrl='1' THEN + INT_LA3_q <= INT_LA3_d; + END IF; + END PROCESS; - PROCESS (INT_LA2_0_clk_ctrl, INT_LA2_0_clrn_ctrl) BEGIN - IF INT_LA2_0_clrn_ctrl='0' THEN - INT_LA2_q <= std_logic_vector'("0000"); - ELSIF INT_LA2_0_clk_ctrl'event and INT_LA2_0_clk_ctrl='1' THEN - INT_LA2_q <= INT_LA2_d; - END IF; - END PROCESS; + PROCESS (INT_LA2_0_clk_ctrl, INT_LA2_0_clrn_ctrl) BEGIN + IF INT_LA2_0_clrn_ctrl='0' THEN + INT_LA2_q <= std_logic_vector'("0000"); + ELSIF INT_LA2_0_clk_ctrl'event and INT_LA2_0_clk_ctrl='1' THEN + INT_LA2_q <= INT_LA2_d; + END IF; + END PROCESS; - PROCESS (INT_LA1_0_clk_ctrl, INT_LA1_0_clrn_ctrl) BEGIN + PROCESS (INT_LA1_0_clk_ctrl, INT_LA1_0_clrn_ctrl) BEGIN IF INT_LA1_0_clrn_ctrl='0' THEN INT_LA1_q <= std_logic_vector'("0000"); ELSIF INT_LA1_0_clk_ctrl'event and INT_LA1_0_clk_ctrl='1' THEN From 91791dfb5df2e82d54421b2f2c5cd55617fbd1e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 16 Jan 2016 22:11:51 +0000 Subject: [PATCH 070/127] do not automatically insert delay chains --- FPGA_Quartus_13.1/firebee1.qsf | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 5e7140b..78c95fb 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -385,7 +385,6 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns" set_instance_assignment -name IO_STANDARD "2.5 V" -to BA set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD @@ -674,7 +673,7 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF set_global_assignment -name SDC_FILE firebee_groups.sdc set_global_assignment -name VHDL_FILE Video/video.vhd From ddad975d6f71734141ac457b106443b062136345 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 17 Jan 2016 08:43:20 +0000 Subject: [PATCH 071/127] fix 13MHz clock sdc --- FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd | 3 +-- FPGA_Quartus_13.1/firebee_groups.sdc | 10 +++++----- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 0ea49e4..2cc1649 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -1486,8 +1486,7 @@ BEGIN BORDER_COLOR0_clk_ctrl <= MAIN_CLK; -- $404/4 - BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) - = "00000000000000000100000001"); + BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001"); BORDER_COLOR_d <= FB_AD(23 DOWNTO 0); BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 3924ec3..5b43ebc 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -92,7 +92,7 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por derive_pll_clocks create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q -create_generated_clock -divide_by 2 -source i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2] i_video|i_video_mod_mux_clutctr|CLK13M_q +create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] i_video|i_video_mod_mux_clutctr|CLK13M_q # PIXEL_CLK is either # CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO @@ -121,16 +121,16 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_inputs] +#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] +#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_inputs] #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outputs] +#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] +#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outputs] #************************************************************** From 21a4a80fb7eaee7e0a3be4d495520576f4b4be51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 17 Jan 2016 20:28:18 +0000 Subject: [PATCH 072/127] start of flexbus_register implementation to simplify that --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 22 +- .../Video/video_mod_mux_clutctr.vhd | 550 +++++++----------- FPGA_Quartus_13.1/firebee1.qsf | 6 +- FPGA_Quartus_13.1/firebee1.vhd | 144 ++--- FPGA_Quartus_13.1/firebee_groups.sdc | 4 +- FPGA_Quartus_13.1/flexbus_register.vhd | 48 ++ 6 files changed, 353 insertions(+), 421 deletions(-) create mode 100644 FPGA_Quartus_13.1/flexbus_register.vhd diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index e247a73..dd18799 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -276,7 +276,8 @@ ARCHITECTURE rtl OF ddr_ctr IS SIGNAL VRAS : std_logic; SIGNAL VCAS : std_logic; SIGNAL LINE : std_logic; - + SIGNAL v_bash : std_logic_vector(7 DOWNTO 0); + SIGNAL v_bash_cs : std_logic; -- Sub Module Interface Section @@ -573,6 +574,25 @@ BEGIN END IF; END PROCESS; + i_vbash : work.flexbus_register + GENERIC MAP + ( + reg_width => 8, + match_address => x"ffff8604", + match_mask => x"0000fffe", -- byte register + match_fbcs => 1 + ) + PORT MAP + ( + clk => clk33m, + fb_addr => fb_adr, + fb_data => fb_ad, + fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), + fb_wr_n => nfb_wr, + data => v_bash, + cs => v_bash_cs + ); + -- Start of original equations LINE <= FB_SIZE0 and FB_SIZE1; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 2cc1649..1e11f3a 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -270,12 +270,15 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic; SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic; + SIGNAL ACP_VCTR0_clk_ctrl : std_logic; SIGNAL ACP_VCTR24_ena_ctrl : std_logic; SIGNAL ACP_VCTR16_ena_ctrl : std_logic; SIGNAL ACP_VCTR8_ena_ctrl : std_logic; + SIGNAL ACP_VCTR6_ena_ctrl : std_logic; SIGNAL ACP_VCTR0_ena_ctrl : std_logic; - SIGNAL ATARI_HH0_clk_ctrl : std_logic; + + SIGNAL ATARI_HH0_clk_ctrl : std_logic; SIGNAL ATARI_HH24_ena_ctrl : std_logic; SIGNAL ATARI_HH16_ena_ctrl : std_logic; SIGNAL ATARI_HH8_ena_ctrl : std_logic; @@ -299,7 +302,6 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL VR_DOUT0_ena_ctrl : std_logic; SIGNAL VR_FRQ0_clk_ctrl : std_logic; SIGNAL VR_FRQ0_ena_ctrl : std_logic; - SIGNAL ACP_VCTR6_ena_ctrl : std_logic; SIGNAL CCSEL0_clk_ctrl : std_logic; SIGNAL BORDER_COLOR0_clk_ctrl : std_logic; SIGNAL BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl, @@ -580,52 +582,26 @@ BEGIN END IF; END PROCESS; - PROCESS (ACP_VCTR0_clk_ctrl) BEGIN - if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN - if ACP_VCTR24_ena_ctrl='1' THEN - (ACP_VCTR_q(31), ACP_VCTR_q(30), ACP_VCTR_q(29), ACP_VCTR_q(28), - ACP_VCTR_q(27), ACP_VCTR_q(26), ACP_VCTR_q(25), - ACP_VCTR_q(24)) <= ACP_VCTR_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; - - PROCESS (ACP_VCTR0_clk_ctrl) BEGIN - if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN - if ACP_VCTR16_ena_ctrl='1' THEN - (ACP_VCTR_q(23), ACP_VCTR_q(22), ACP_VCTR_q(21), ACP_VCTR_q(20), - ACP_VCTR_q(19), ACP_VCTR_q(18), ACP_VCTR_q(17), - ACP_VCTR_q(16)) <= ACP_VCTR_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; - - PROCESS (ACP_VCTR0_clk_ctrl) BEGIN - if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN - if ACP_VCTR8_ena_ctrl='1' THEN - (ACP_VCTR_q(15), ACP_VCTR_q(14), ACP_VCTR_q(13), ACP_VCTR_q(12), - ACP_VCTR_q(11), ACP_VCTR_q(10), ACP_VCTR_q(9), ACP_VCTR_q(8)) - <= ACP_VCTR_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (ACP_VCTR0_clk_ctrl) BEGIN - if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN - if ACP_VCTR6_ena_ctrl='1' THEN - (ACP_VCTR_q(7), ACP_VCTR_q(6)) <= ACP_VCTR_d(7 DOWNTO 6); - END IF; - END IF; - END PROCESS; - - PROCESS (ACP_VCTR0_clk_ctrl) BEGIN - if ACP_VCTR0_clk_ctrl'EVENT and ACP_VCTR0_clk_ctrl='1' THEN - if ACP_VCTR0_ena_ctrl='1' THEN - (ACP_VCTR_q(5), ACP_VCTR_q(4), ACP_VCTR_q(3), ACP_VCTR_q(2), - ACP_VCTR_q(1), ACP_VCTR_q(0)) <= ACP_VCTR_d(5 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (ACP_VCTR0_clk_ctrl) + BEGIN + IF rising_edge(ACP_VCTR0_clk_ctrl) THEN + IF ACP_VCTR24_ena_ctrl = '1' THEN + ACP_VCTR_q(31 DOWNTO 24) <= ACP_VCTR_d(31 DOWNTO 24); + END IF; + IF ACP_VCTR16_ena_ctrl = '1' THEN + ACP_VCTR_q(23 DOWNTO 16) <= ACP_VCTR_d(23 DOWNTO 16); + END IF; + IF ACP_VCTR8_ena_ctrl = '1' THEN + ACP_VCTR_q(15 DOWNTO 8) <= ACP_VCTR_d(15 DOWNTO 8); + END IF; + IF ACP_VCTR6_ena_ctrl = '1' THEN + ACP_VCTR_q(7 DOWNTO 6) <= ACP_VCTR_d(7 DOWNTO 6); + END IF; + IF ACP_VCTR0_ena_ctrl = '1' THEN + ACP_VCTR_q(5 DOWNTO 0) <= ACP_VCTR_d(5 DOWNTO 0); + END IF; + END IF; + END PROCESS; PROCESS (SYS_CTR0_clk_ctrl) BEGIN if SYS_CTR0_clk_ctrl'EVENT and SYS_CTR0_clk_ctrl='1' THEN @@ -841,218 +817,116 @@ BEGIN END IF; END PROCESS; - PROCESS (ATARI_HH0_clk_ctrl) BEGIN - if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN - if ATARI_HH24_ena_ctrl='1' THEN - (ATARI_HH_q(31), ATARI_HH_q(30), ATARI_HH_q(29), ATARI_HH_q(28), - ATARI_HH_q(27), ATARI_HH_q(26), ATARI_HH_q(25), - ATARI_HH_q(24)) <= ATARI_HH_d(31 DOWNTO 24); - END IF; - END IF; + PROCESS (ATARI_HH0_clk_ctrl) + BEGIN + IF rising_edge(ATARI_HH0_clk_ctrl) THEN + IF ATARI_HH24_ena_ctrl = '1' THEN + ATARI_HH_q(31 DOWNTO 24) <= ATARI_HH_d(31 DOWNTO 24); + END IF; + IF ATARI_HH16_ena_ctrl = '1' THEN + ATARI_HH_q(23 DOWNTO 16) <= ATARI_HH_d(23 DOWNTO 16); + END IF; + IF ATARI_HH8_ena_ctrl = '1' THEN + ATARI_HH_q(15 DOWNTO 8) <= ATARI_HH_d(15 DOWNTO 8); + END IF; + IF ATARI_HH0_ena_ctrl = '1' THEN + ATARI_HH_q(7 DOWNTO 0) <= ATARI_HH_d(7 DOWNTO 0); + END IF; + END IF; END PROCESS; - PROCESS (ATARI_HH0_clk_ctrl) BEGIN - if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN - if ATARI_HH16_ena_ctrl='1' THEN - (ATARI_HH_q(23), ATARI_HH_q(22), ATARI_HH_q(21), ATARI_HH_q(20), - ATARI_HH_q(19), ATARI_HH_q(18), ATARI_HH_q(17), - ATARI_HH_q(16)) <= ATARI_HH_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; + PROCESS (ATARI_VH0_clk_ctrl) + BEGIN + IF rising_edge(ATARI_VH0_clk_ctrl) THEN + IF ATARI_VH24_ena_ctrl = '1' THEN + ATARI_VH_q(31 DOWNTO 24) <= ATARI_VH_d(31 DOWNTO 24); + END IF; + IF ATARI_VH16_ena_ctrl = '1' THEN + ATARI_VH_q(23 DOWNTO 16) <= ATARI_VH_d(23 DOWNTO 16); + END IF; + IF ATARI_VH8_ena_ctrl = '1' THEN + ATARI_VH_q(15 DOWNTO 8) <= ATARI_VH_d(15 DOWNTO 8); + END IF; + IF ATARI_VH0_ena_ctrl='1' THEN + ATARI_VH_q(7 DOWNTO 0) <= ATARI_VH_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (ATARI_HH0_clk_ctrl) BEGIN - if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN - if ATARI_HH8_ena_ctrl='1' THEN - (ATARI_HH_q(15), ATARI_HH_q(14), ATARI_HH_q(13), ATARI_HH_q(12), - ATARI_HH_q(11), ATARI_HH_q(10), ATARI_HH_q(9), ATARI_HH_q(8)) - <= ATARI_HH_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (ATARI_HL0_clk_ctrl) BEGIN + IF rising_edge(ATARI_HL0_clk_ctrl) THEN + IF ATARI_HL24_ena_ctrl = '1' THEN + ATARI_HL_q(31 DOWNTO 24) <= ATARI_HL_d(31 DOWNTO 24); + END IF; + IF ATARI_HL16_ena_ctrl = '1' THEN + ATARI_HL_q(23 DOWNTO 16) <= ATARI_HL_d(23 DOWNTO 16); + END IF; + IF ATARI_HL8_ena_ctrl = '1' THEN + ATARI_HL_q(15 DOWNTO 8) <= ATARI_HL_d(15 DOWNTO 8); + END IF; + IF ATARI_HL0_ena_ctrl = '1' THEN + ATARI_HL_q(7 DOWNTO 0) <= ATARI_HL_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (ATARI_HH0_clk_ctrl) BEGIN - if ATARI_HH0_clk_ctrl'EVENT and ATARI_HH0_clk_ctrl='1' THEN - if ATARI_HH0_ena_ctrl='1' THEN - (ATARI_HH_q(7), ATARI_HH_q(6), ATARI_HH_q(5), ATARI_HH_q(4), - ATARI_HH_q(3), ATARI_HH_q(2), ATARI_HH_q(1), ATARI_HH_q(0)) - <= ATARI_HH_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (ATARI_VL0_clk_ctrl) + BEGIN + IF rising_edge(ATARI_VL0_clk_ctrl) THEN + IF ATARI_VL24_ena_ctrl = '1' THEN + ATARI_VL_q(31 DOWNTO 24) <= ATARI_VL_d(31 DOWNTO 24); + END IF; + IF ATARI_VL16_ena_ctrl = '1' THEN + ATARI_VL_q(23 DOWNTO 16) <= ATARI_VL_d(23 DOWNTO 16); + END IF; + IF ATARI_VL8_ena_ctrl = '1' THEN + ATARI_VL_q(15 DOWNTO 8) <= ATARI_VL_d(15 DOWNTO 8); + END IF; + IF ATARI_VL0_ena_ctrl = '1' THEN + ATARI_VL_q(7 DOWNTO 0) <= ATARI_VL_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (ATARI_VH0_clk_ctrl) BEGIN - if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN - if ATARI_VH24_ena_ctrl='1' THEN - (ATARI_VH_q(31), ATARI_VH_q(30), ATARI_VH_q(29), ATARI_VH_q(28), - ATARI_VH_q(27), ATARI_VH_q(26), ATARI_VH_q(25), - ATARI_VH_q(24)) <= ATARI_VH_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; - PROCESS (ATARI_VH0_clk_ctrl) BEGIN - if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN - if ATARI_VH16_ena_ctrl='1' THEN - (ATARI_VH_q(23), ATARI_VH_q(22), ATARI_VH_q(21), ATARI_VH_q(20), - ATARI_VH_q(19), ATARI_VH_q(18), ATARI_VH_q(17), - ATARI_VH_q(16)) <= ATARI_VH_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; + PROCESS (HHT0_clk_ctrl) + BEGIN + IF rising_edge(HHT0_clk_ctrl) THEN + IF HHT8_ena_ctrl = '1' THEN + HHT_q(11 DOWNTO 8) <= HHT_d(11 DOWNTO 8); + END IF; + IF HHT0_ena_ctrl = '1' THEN + HHT_q(7 DOWNTO 0) <= HHT_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (ATARI_VH0_clk_ctrl) BEGIN - if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN - if ATARI_VH8_ena_ctrl='1' THEN - (ATARI_VH_q(15), ATARI_VH_q(14), ATARI_VH_q(13), ATARI_VH_q(12), - ATARI_VH_q(11), ATARI_VH_q(10), ATARI_VH_q(9), ATARI_VH_q(8)) - <= ATARI_VH_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (HBE0_clk_ctrl) + BEGIN + IF rising_edge(HBE0_clk_ctrl) THEN + IF HBE8_ena_ctrl = '1' THEN + HBE_q(11 DOWNTO 8) <= HBE_d(11 DOWNTO 8); + END IF; + IF HBE0_ena_ctrl = '1' THEN + HBE_q(7 DOWNTO 0) <= HBE_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (ATARI_VH0_clk_ctrl) BEGIN - if ATARI_VH0_clk_ctrl'EVENT and ATARI_VH0_clk_ctrl='1' THEN - if ATARI_VH0_ena_ctrl='1' THEN - (ATARI_VH_q(7), ATARI_VH_q(6), ATARI_VH_q(5), ATARI_VH_q(4), - ATARI_VH_q(3), ATARI_VH_q(2), ATARI_VH_q(1), ATARI_VH_q(0)) - <= ATARI_VH_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (HDB0_clk_ctrl) + BEGIN + IF rising_edge(HDB0_clk_ctrl) THEN + IF HDB8_ena_ctrl = '1' THEN + HDB_q(11 DOWNTO 8) <= HDB_d(11 DOWNTO 8); + END IF; + IF HDB0_ena_ctrl = '1' THEN + HDB_q(7 DOWNTO 0) <= HDB_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (ATARI_HL0_clk_ctrl) BEGIN - if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN - if ATARI_HL24_ena_ctrl='1' THEN - (ATARI_HL_q(31), ATARI_HL_q(30), ATARI_HL_q(29), ATARI_HL_q(28), - ATARI_HL_q(27), ATARI_HL_q(26), ATARI_HL_q(25), - ATARI_HL_q(24)) <= ATARI_HL_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_HL0_clk_ctrl) BEGIN - if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN - if ATARI_HL16_ena_ctrl='1' THEN - (ATARI_HL_q(23), ATARI_HL_q(22), ATARI_HL_q(21), ATARI_HL_q(20), - ATARI_HL_q(19), ATARI_HL_q(18), ATARI_HL_q(17), - ATARI_HL_q(16)) <= ATARI_HL_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_HL0_clk_ctrl) BEGIN - if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN - if ATARI_HL8_ena_ctrl='1' THEN - (ATARI_HL_q(15), ATARI_HL_q(14), ATARI_HL_q(13), ATARI_HL_q(12), - ATARI_HL_q(11), ATARI_HL_q(10), ATARI_HL_q(9), ATARI_HL_q(8)) - <= ATARI_HL_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_HL0_clk_ctrl) BEGIN - if ATARI_HL0_clk_ctrl'EVENT and ATARI_HL0_clk_ctrl='1' THEN - if ATARI_HL0_ena_ctrl='1' THEN - (ATARI_HL_q(7), ATARI_HL_q(6), ATARI_HL_q(5), ATARI_HL_q(4), - ATARI_HL_q(3), ATARI_HL_q(2), ATARI_HL_q(1), ATARI_HL_q(0)) - <= ATARI_HL_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_VL0_clk_ctrl) BEGIN - if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN - if ATARI_VL24_ena_ctrl='1' THEN - (ATARI_VL_q(31), ATARI_VL_q(30), ATARI_VL_q(29), ATARI_VL_q(28), - ATARI_VL_q(27), ATARI_VL_q(26), ATARI_VL_q(25), - ATARI_VL_q(24)) <= ATARI_VL_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_VL0_clk_ctrl) BEGIN - if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN - if ATARI_VL16_ena_ctrl='1' THEN - (ATARI_VL_q(23), ATARI_VL_q(22), ATARI_VL_q(21), ATARI_VL_q(20), - ATARI_VL_q(19), ATARI_VL_q(18), ATARI_VL_q(17), - ATARI_VL_q(16)) <= ATARI_VL_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_VL0_clk_ctrl) BEGIN - if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN - if ATARI_VL8_ena_ctrl='1' THEN - (ATARI_VL_q(15), ATARI_VL_q(14), ATARI_VL_q(13), ATARI_VL_q(12), - ATARI_VL_q(11), ATARI_VL_q(10), ATARI_VL_q(9), ATARI_VL_q(8)) - <= ATARI_VL_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_VL0_clk_ctrl) BEGIN - if ATARI_VL0_clk_ctrl'EVENT and ATARI_VL0_clk_ctrl='1' THEN - if ATARI_VL0_ena_ctrl='1' THEN - (ATARI_VL_q(7), ATARI_VL_q(6), ATARI_VL_q(5), ATARI_VL_q(4), - ATARI_VL_q(3), ATARI_VL_q(2), ATARI_VL_q(1), ATARI_VL_q(0)) - <= ATARI_VL_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (HHT0_clk_ctrl) BEGIN - if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN - if HHT8_ena_ctrl='1' THEN - (HHT_q(11), HHT_q(10), HHT_q(9), HHT_q(8)) <= HHT_d(11 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (HHT0_clk_ctrl) BEGIN - if HHT0_clk_ctrl'EVENT and HHT0_clk_ctrl='1' THEN - if HHT0_ena_ctrl='1' THEN - (HHT_q(7), HHT_q(6), HHT_q(5), HHT_q(4), HHT_q(3), HHT_q(2), - HHT_q(1), HHT_q(0)) <= HHT_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (HBE0_clk_ctrl) BEGIN - if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN - if HBE8_ena_ctrl='1' THEN - (HBE_q(11), HBE_q(10), HBE_q(9), HBE_q(8)) <= HBE_d(11 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (HBE0_clk_ctrl) BEGIN - if HBE0_clk_ctrl'EVENT and HBE0_clk_ctrl='1' THEN - if HBE0_ena_ctrl='1' THEN - (HBE_q(7), HBE_q(6), HBE_q(5), HBE_q(4), HBE_q(3), HBE_q(2), - HBE_q(1), HBE_q(0)) <= HBE_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (HDB0_clk_ctrl) BEGIN - if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN - if HDB8_ena_ctrl='1' THEN - (HDB_q(11), HDB_q(10), HDB_q(9), HDB_q(8)) <= HDB_d(11 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (HDB0_clk_ctrl) BEGIN - if HDB0_clk_ctrl'EVENT and HDB0_clk_ctrl='1' THEN - if HDB0_ena_ctrl='1' THEN - (HDB_q(7), HDB_q(6), HDB_q(5), HDB_q(4), HDB_q(3), HDB_q(2), - HDB_q(1), HDB_q(0)) <= HDB_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (HDE0_clk_ctrl) BEGIN + PROCESS (HDE0_clk_ctrl) + BEGIN if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN if HDE8_ena_ctrl='1' THEN (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 DOWNTO 8); @@ -1362,10 +1236,11 @@ BEGIN ACP_VCTR0_clk_ctrl <= MAIN_CLK; -- $400/4 - ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000000000100000000"); + ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000000"); + ACP_VCTR_d(31 DOWNTO 8) <= FB_AD(31 DOWNTO 8); ACP_VCTR_d(5 DOWNTO 0) <= FB_AD(5 DOWNTO 0); + ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); @@ -1465,9 +1340,8 @@ BEGIN ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or - (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and - (not nFB_WR) and FB_AD(0)); + + ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); FALCON_VIDEO <= ACP_VCTR_q(7); FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); ST_VIDEO <= ACP_VCTR_q(6); @@ -1661,103 +1535,91 @@ BEGIN -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL - VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101100001"); - VCNTRL0_clk_ctrl <= MAIN_CLK; - VCNTRL_d <= FB_AD(19 DOWNTO 16); - VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); + VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100001"); + VCNTRL0_clk_ctrl <= MAIN_CLK; + VCNTRL_d <= FB_AD(19 DOWNTO 16); + VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); -- - REGISTER OUT -- low word register access - u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & - ST_SHIFT_MODE_q & "00000000")) or (sizeIt(FALCON_SHIFT_MODE_CS,16) and - std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or - (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 - DOWNTO 4) & (not BLITTER_RUN) & SYS_CTR_q(2 DOWNTO 0))) or - (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or - (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or - (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or - (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or - (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or - (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or - (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or - (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or - (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or - (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or - (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or - (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or - (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or - (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or - (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & - VCNTRL_q)) or (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 DOWNTO 16)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 DOWNTO 16)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 DOWNTO 16)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 DOWNTO 16)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 DOWNTO 16)) or - (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & - BORDER_COLOR_q(23 DOWNTO 16))) or (sizeIt(VIDEO_PLL_CONFIG_CS,16) and - std_logic_vector'("0000000" & VR_DOUT_q)) or - (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & - "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); - u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or - BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS - or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS - or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or - VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or - VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); - FB_AD(31 DOWNTO 16) <= u0_tridata; + u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or + (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or + (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 DOWNTO 4) & (not BLITTER_RUN) & SYS_CTR_q(2 DOWNTO 0))) or + (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or + (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or + (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or + (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or + (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or + (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or + (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or + (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or + (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or + (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or + (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or + (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or + (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or + (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or + (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or + (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 DOWNTO 16)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 DOWNTO 16)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 DOWNTO 16)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 DOWNTO 16)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 DOWNTO 16)) or + (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 DOWNTO 16))) or + (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or + (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); + + u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or + HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or + VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); + FB_AD(31 DOWNTO 16) <= u0_tridata; -- high word register access - u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 DOWNTO 0)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 DOWNTO 0)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 DOWNTO 0)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 DOWNTO 0)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 DOWNTO 0)) or - (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 DOWNTO 0)); - u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS - or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); - FB_AD(15 DOWNTO 0) <= u1_tridata; - VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or - ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or - HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or - ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or - VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; + u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 DOWNTO 0)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 DOWNTO 0)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 DOWNTO 0)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 DOWNTO 0)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 DOWNTO 0)) or + (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 DOWNTO 0)); + u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); + FB_AD(15 DOWNTO 0) <= u1_tridata; --- VIDEO AUSGABE SETZEN - CLK17M_clk <= CLK33M; - CLK17M_d <= not CLK17M_q; - CLK13M_clk <= CLK25M; - CLK13M_d <= not CLK13M_q; + VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or + HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or + VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; --- 320 pixels, 32 MHz, --- 320 pixels, 25.175 MHz, --- 640 pixels, 32 MHz, VGA monitor --- 640 pixels, 25.175 MHz, VGA monitor - PIXEL_CLK <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) - and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or (CLK17M_q and (not - ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and - (not VCO_q(2))) or VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and - (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not - VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or - ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) - or (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO - 8) = "00")) or (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and - ACP_VCTR_q(9 DOWNTO 8) = "01")) or (CLK_VIDEO and ACP_VIDEO_ON and - ACP_VCTR_q(9)); + -- VIDEO AUSGABE SETZEN + CLK17M_clk <= CLK33M; + CLK17M_d <= not CLK17M_q; + + CLK13M_clk <= CLK25M; + CLK13M_d <= not CLK13M_q; --- ------------------------------------------------------------ --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK --- -------------------------------------------------------------- --- HSY_LEN[].CLK = MAIN_CLK; --- check if this is better (mfro) - HSY_LEN0_clk_ctrl <= PIXEL_CLK; + -- 320 pixels, 32 MHz, + -- 320 pixels, 25.175 MHz, + -- 640 pixels, 32 MHz, VGA monitor + -- 640 pixels, 25.175 MHz, VGA monitor + PIXEL_CLK <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or + (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or + (CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or + (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or + (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "00")) or + (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "01")) or + (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); --- 320 pixels, 32 MHz, RGB --- 320 pixels, 25.175 MHz, VGA --- 640 pixels, 32 MHz, RGB --- 640 pixels, 25.175 MHz, VGA --- hsync pulse length in pixeln = frequenz / = 500ns - HSY_LEN_d <= ("00001110" and sizeIt(not ACP_VIDEO_ON,8) and + -- ------------------------------------------------------------ + -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK + -- -------------------------------------------------------------- + -- HSY_LEN[].CLK = MAIN_CLK; + -- check if this is better (mfro) + HSY_LEN0_clk_ctrl <= PIXEL_CLK; + + -- 320 pixels, 32 MHz, RGB + -- 320 pixels, 25.175 MHz, VGA + -- 640 pixels, 32 MHz, RGB + -- 640 pixels, 25.175 MHz, VGA + -- hsync pulse length in pixeln = frequenz / = 500ns + HSY_LEN_d <= ("00001110" and sizeIt(not ACP_VIDEO_ON,8) and (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and ((sizeIt(VCNTRL_q(2),8) and sizeIt(VCO_q(2),8)) or sizeIt(VCO_q(0),8))) or ("00010000" and sizeIt(not ACP_VIDEO_ON,8) and diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 78c95fb..89223ae 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -675,6 +675,9 @@ set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll4.tdf set_global_assignment -name SDC_FILE firebee_groups.sdc set_global_assignment -name VHDL_FILE Video/video.vhd set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd @@ -857,6 +860,5 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index d7c0db0..4034aa9 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -205,90 +205,90 @@ ARCHITECTURE rtl OF firebee1 IS COMPONENT altpll_reconfig1 PORT ( - clock : IN STD_LOGIC ; - counter_param : IN STD_LOGIC_VECTOR (2 DOWNTO 0); - counter_type : IN STD_LOGIC_VECTOR (3 DOWNTO 0); - data_in : IN STD_LOGIC_VECTOR (8 DOWNTO 0); - pll_areset_in : IN STD_LOGIC := '0'; - pll_scandataout : IN STD_LOGIC ; - pll_scandone : IN STD_LOGIC ; - read_param : IN STD_LOGIC ; - reconfig : IN STD_LOGIC ; - reset : IN STD_LOGIC ; - write_param : IN STD_LOGIC ; - busy : OUT STD_LOGIC ; - data_out : OUT STD_LOGIC_VECTOR (8 DOWNTO 0); - pll_areset : OUT STD_LOGIC ; - pll_configupdate : OUT STD_LOGIC ; - pll_scanclk : OUT STD_LOGIC ; - pll_scanclkena : OUT STD_LOGIC ; - pll_scandata : OUT STD_LOGIC + clock : IN std_logic ; + counter_param : IN std_logic_vector (2 DOWNTO 0); + counter_type : IN std_logic_vector (3 DOWNTO 0); + data_in : IN std_logic_vector (8 DOWNTO 0); + pll_areset_in : IN std_logic := '0'; + pll_scandataout : IN std_logic ; + pll_scandone : IN std_logic ; + read_param : IN std_logic ; + reconfig : IN std_logic ; + reset : IN std_logic ; + write_param : IN std_logic ; + busy : OUT std_logic ; + data_out : OUT std_logic_vector (8 DOWNTO 0); + pll_areset : OUT std_logic ; + pll_configupdate : OUT std_logic ; + pll_scanclk : OUT std_logic ; + pll_scanclkena : OUT std_logic ; + pll_scandata : OUT std_logic ); END COMPONENT altpll_reconfig1; COMPONENT altpll4 PORT ( - areset : IN STD_LOGIC := '0'; - configupdate : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - scanclk : IN STD_LOGIC := '1'; - scanclkena : IN STD_LOGIC := '0'; - scandata : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC ; - scandataout : OUT STD_LOGIC ; - scandone : OUT STD_LOGIC + areset : IN std_logic := '0'; + configupdate : IN std_logic := '0'; + inclk0 : IN std_logic := '0'; + scanclk : IN std_logic := '1'; + scanclkena : IN std_logic := '0'; + scandata : IN std_logic := '0'; + c0 : OUT std_logic ; + locked : OUT std_logic ; + scandataout : OUT std_logic ; + scandone : OUT std_logic ); END COMPONENT altpll4; - COMPONENT Video + COMPONENT video PORT ( - FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - MAIN_CLK : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - DDR_SYNC_66M : IN STD_LOGIC; - CLK33M : IN STD_LOGIC; - CLK25M : IN STD_LOGIC; - CLK_VIDEO : IN STD_LOGIC; - VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); - VR_BUSY : IN STD_LOGIC; - VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - nBLANK : OUT STD_LOGIC; - VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); - nVWE : OUT STD_LOGIC; - nVCAS : OUT STD_LOGIC; - nVRAS : OUT STD_LOGIC; - nVCS : OUT STD_LOGIC; - VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - nPD_VGA : OUT STD_LOGIC; - VCKE : OUT STD_LOGIC; - VSYNC : OUT STD_LOGIC; - HSYNC : OUT STD_LOGIC; - nSYNC : OUT STD_LOGIC; - VIDEO_TA : OUT STD_LOGIC; - PIXEL_CLK : OUT STD_LOGIC; - BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - VIDEO_RECONFIG : OUT STD_LOGIC; - VR_WR : OUT STD_LOGIC; - VR_RD : OUT STD_LOGIC; - VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); - FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + MAIN_CLK : IN std_logic; + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + nFB_WR : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + nRSTO : IN std_logic; + nFB_OE : IN std_logic; + FB_ALE : IN std_logic; + DDRCLK : IN std_logic_vector(3 DOWNTO 0); + DDR_SYNC_66M : IN std_logic; + CLK33M : IN std_logic; + CLK25M : IN std_logic; + CLK_VIDEO : IN std_logic; + VR_D : IN std_logic_vector(8 DOWNTO 0); + VR_BUSY : IN std_logic; + VG : OUT std_logic_vector(7 DOWNTO 0); + VB : OUT std_logic_vector(7 DOWNTO 0); + VR : OUT std_logic_vector(7 DOWNTO 0); + nBLANK : OUT std_logic; + VA : OUT std_logic_vector(12 DOWNTO 0); + nVWE : OUT std_logic; + nVCAS : OUT std_logic; + nVRAS : OUT std_logic; + nVCS : OUT std_logic; + VDM : OUT std_logic_vector(3 DOWNTO 0); + nPD_VGA : OUT std_logic; + VCKE : OUT std_logic; + VSYNC : OUT std_logic; + HSYNC : OUT std_logic; + nSYNC : OUT std_logic; + VIDEO_TA : OUT std_logic; + PIXEL_CLK : OUT std_logic; + BA : OUT std_logic_vector(1 DOWNTO 0); + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + VR_RD : OUT std_logic; + VDQS : INOUT std_logic_vector(3 DOWNTO 0); + FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + VD : INOUT std_logic_vector(31 DOWNTO 0) ); -END COMPONENT; + END COMPONENT video; BEGIN nDREQ1 <= nDACK1; diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 5b43ebc..ee5b103 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -112,8 +112,8 @@ create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|aut # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.5 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.5 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 4.5 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 4.5 derive_clock_uncertainty diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd new file mode 100644 index 0000000..6b54cbf --- /dev/null +++ b/FPGA_Quartus_13.1/flexbus_register.vhd @@ -0,0 +1,48 @@ +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + + ENTITY flexbus_register IS + GENERIC + ( + reg_width : integer := 11; + match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); + match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1'); + match_fbcs : integer := 0 + ); + PORT + ( + clk : IN std_logic; + fb_addr : IN std_logic_vector(31 DOWNTO 0); + fb_data : IN std_logic_vector(31 DOWNTO 0); + fb_cs : IN std_logic_vector(5 DOWNTO 1); + fb_wr_n : IN std_logic; + data : OUT std_logic_vector(reg_width - 1 DOWNTO 0); + cs : OUT std_logic := '0' + ); + END ENTITY flexbus_register; + +ARCHITECTURE rtl OF flexbus_register IS + SIGNAL fbcs_match : std_logic; + SIGNAL address_match : std_logic; + SIGNAL reg_value : std_logic_vector(reg_width - 1 DOWNTO 0) := (OTHERS => '0'); +BEGIN + fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0'; + address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0'; + + p_register_access : PROCESS(ALL) + BEGIN + IF rising_edge(clk) THEN + IF fbcs_match = '1' and address_match = '1' THEN + cs <= '1'; + IF fb_wr_n = '0' THEN -- write access + reg_value <= fb_data(reg_width - 1 DOWNTO 0); + ELSE -- read access + data <= reg_value; + END IF; + ELSE + cs <= '0'; + END IF; + END IF; + END PROCESS p_register_access; +END ARCHITECTURE rtl; \ No newline at end of file From b9c3ec9366ab29d236b5a87eb3e5768bca745de8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 17 Jan 2016 20:39:25 +0000 Subject: [PATCH 073/127] modify indent --- FPGA_Quartus_13.1/firebee1.qws | Bin 5228 -> 7748 bytes FPGA_Quartus_13.1/flexbus_register.vhd | 38 ++++++++++++------------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index 80b4fbfd39e1e937c7752e40f53896c9ec813214..b91970ff6c6c26f4a9ba8047ac6b48c8eff1de53 100644 GIT binary patch delta 1283 zcmbVMOGs2v82-*3?~K`)<5*GP$S?#MVd?ltLn@OBMbxAsX(8i0R2rR_@f9XhNCYC} za2D;uT0~GWZOS%*OWOvmTC|9uAX=6-egC;?x@pn5{P%x9&wuaN>Xp{TqspUm_KY1x z42c&{%anSUtBvb7rQRcx7@;tZ6b3NLcg)}kOcO_u#018P$C1`2t(;y~^J*biJCse* zWg3H2XK0uvH^e|08pg>T!z6|o3Me6TVTRH=B+!B|B7`_(1)u6r~{0Pfe6eT8Ga12tf2swWqoGd+V9W4l3Z&R zQ(0?#opMsEYTE4oNr4hok@OZqHzSR+FXy_0Hv<-c9Qw_S?lh7f%Vz;}K zwe*O$rJMXIn>(vk^b>!BU#(DR_LBInh|P*uS+~janu<6u>jPm2pMU46umf)$6ZaX% z#I=Lh>)!tV_$A~=eUFuX=Bd%%($4&kvXEucFq5QFAK8bb;c@uhT7lP!-`oPmL9+T=TIa%_yA z3=9k@li0;2^BEWz-9a3N|Ns93X=Vlnc6*?h-(&-J1tAcVVHre9Lv9$ak7FO$K)U})y@5UEUdD{K>7U)46L7k z%H{#>K;dtaY-W-K$}-hMWI=|3R73caHwZ^=J}9Qdqy*9g1Rz5g??Vki;scqJ19 '0'); - match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1'); - match_fbcs : integer := 0 - ); - PORT - ( - clk : IN std_logic; - fb_addr : IN std_logic_vector(31 DOWNTO 0); - fb_data : IN std_logic_vector(31 DOWNTO 0); - fb_cs : IN std_logic_vector(5 DOWNTO 1); - fb_wr_n : IN std_logic; - data : OUT std_logic_vector(reg_width - 1 DOWNTO 0); - cs : OUT std_logic := '0' - ); - END ENTITY flexbus_register; +ENTITY flexbus_register IS + GENERIC + ( + reg_width : integer := 11; + match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); + match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1'); + match_fbcs : integer := 0 + ); + PORT + ( + clk : IN std_logic; + fb_addr : IN std_logic_vector(31 DOWNTO 0); + fb_data : IN std_logic_vector(31 DOWNTO 0); + fb_cs : IN std_logic_vector(5 DOWNTO 1); + fb_wr_n : IN std_logic; + data : OUT std_logic_vector(reg_width - 1 DOWNTO 0); + cs : OUT std_logic := '0' + ); +END ENTITY flexbus_register; ARCHITECTURE rtl OF flexbus_register IS SIGNAL fbcs_match : std_logic; From 47f6884bbebea3cc10c7984e3f80562dddb5823c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 17 Jan 2016 21:45:53 +0000 Subject: [PATCH 074/127] add more functionality --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 4 +++- FPGA_Quartus_13.1/flexbus_register.vhd | 11 +++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index dd18799..0189d67 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -278,6 +278,7 @@ ARCHITECTURE rtl OF ddr_ctr IS SIGNAL LINE : std_logic; SIGNAL v_bash : std_logic_vector(7 DOWNTO 0); SIGNAL v_bash_cs : std_logic; + SIGNAL reg_ta : std_logic; -- Sub Module Interface Section @@ -588,8 +589,9 @@ BEGIN fb_addr => fb_adr, fb_data => fb_ad, fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), + fb_ta_n => reg_ta, fb_wr_n => nfb_wr, - data => v_bash, + reg_value => v_bash, cs => v_bash_cs ); diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd index 72d3dc0..0fdf3c8 100644 --- a/FPGA_Quartus_13.1/flexbus_register.vhd +++ b/FPGA_Quartus_13.1/flexbus_register.vhd @@ -14,10 +14,11 @@ ENTITY flexbus_register IS ( clk : IN std_logic; fb_addr : IN std_logic_vector(31 DOWNTO 0); - fb_data : IN std_logic_vector(31 DOWNTO 0); + fb_data : INOUT std_logic_vector(31 DOWNTO 0); fb_cs : IN std_logic_vector(5 DOWNTO 1); fb_wr_n : IN std_logic; - data : OUT std_logic_vector(reg_width - 1 DOWNTO 0); + fb_ta_n : OUT std_logic; + reg_value : INOUT std_logic_vector(reg_width - 1 DOWNTO 0); cs : OUT std_logic := '0' ); END ENTITY flexbus_register; @@ -25,7 +26,6 @@ END ENTITY flexbus_register; ARCHITECTURE rtl OF flexbus_register IS SIGNAL fbcs_match : std_logic; SIGNAL address_match : std_logic; - SIGNAL reg_value : std_logic_vector(reg_width - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0'; address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0'; @@ -38,9 +38,12 @@ BEGIN IF fb_wr_n = '0' THEN -- write access reg_value <= fb_data(reg_width - 1 DOWNTO 0); ELSE -- read access - data <= reg_value; + fb_data(reg_width - 1 DOWNTO 0) <= reg_value; + fb_ta_n <= '0'; END IF; ELSE + fb_data <= (OTHERS => 'Z'); + fb_ta_n <= 'Z'; cs <= '0'; END IF; END IF; From e623e668c20916959f9acdf5e489b94ba0c855ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 18 Jan 2016 07:40:08 +0000 Subject: [PATCH 075/127] more flexbus_register work --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 0189d67..3536347 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -276,8 +276,13 @@ ARCHITECTURE rtl OF ddr_ctr IS SIGNAL VRAS : std_logic; SIGNAL VCAS : std_logic; SIGNAL LINE : std_logic; + + SIGNAL v_basx : std_logic_vector(1 DOWNTO 0); + SIGNAL v_basx_cs : std_logic; + SIGNAL v_bash : std_logic_vector(7 DOWNTO 0); SIGNAL v_bash_cs : std_logic; + SIGNAL reg_ta : std_logic; -- Sub Module Interface Section @@ -575,6 +580,26 @@ BEGIN END IF; END PROCESS; + i_vbasx : work.flexbus_register + GENERIC MAP + ( + reg_width => 2, + match_address => x"ffff8603", + match_mask => x"0000ffff", -- byte register + match_fbcs => 1 + ) + PORT MAP + ( + clk => clk33m, + fb_addr => fb_adr, + fb_data => fb_ad, + fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), + fb_ta_n => reg_ta, + fb_wr_n => nfb_wr, + reg_value => v_basx, + cs => v_basx_cs + ); + i_vbash : work.flexbus_register GENERIC MAP ( From 652dd1c124187f70104d093a1331448f82d3554a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 18 Jan 2016 18:15:02 +0000 Subject: [PATCH 076/127] hold time fix test --- .../Video/video_mod_mux_clutctr.vhd | 15 +- FPGA_Quartus_13.1/firebee1.qsf | 1486 ++++++++--------- FPGA_Quartus_13.1/firebee_groups.sdc | 12 +- 3 files changed, 765 insertions(+), 748 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 1e11f3a..86932d6 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -449,9 +449,18 @@ BEGIN END IF; END PROCESS; - BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); - BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); - BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); + -- try if an aditional FF will help hold timing + PROCESS + BEGIN + WAIT UNTIL rising_edge(main_clk); + BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); + BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); + BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); + END PROCESS; + + -- BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); + -- BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); + -- BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 89223ae..ec496e5 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,309 +556,309 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index ee5b103..5358126 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -91,6 +91,7 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por derive_pll_clocks +# two (video) clocks created by logic create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] i_video|i_video_mod_mux_clutctr|CLK13M_q @@ -101,6 +102,13 @@ create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|aut # clock of i_video_clk_pll # +# virtual clocks for i/o constraints +create_clock -name virt_main_clk -period 30.303 -waveform { 0.000 15.151 } + +create_clock -name virt_ddr_clk0 -period 7.575 -waveform { 0.666 4.456 } +create_clock -name virt_ddr_clk1 -period 7.575 -waveform { 0.0 3.788 } +create_clock -name virt_ddr_clk2 -period 7.575 -waveform { 0.5 4.288 } +create_clock -name virt_ddr_clk3 -period 7.575 -waveform { 0.291 4.080 } #************************************************************** # Set Clock Latency @@ -112,8 +120,8 @@ create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|aut # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 4.5 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 4.5 +# set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 4.5 +# set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 4.5 derive_clock_uncertainty From e2ab4af0205f15043f8ed465578032ffe7c464f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 18 Jan 2016 18:32:50 +0000 Subject: [PATCH 077/127] get rid of BUFFER parameters --- FPGA_Quartus_13.1/Video/video.vhd | 57 +----------- .../Video/video_mod_mux_clutctr.vhd | 88 +++++++++---------- 2 files changed, 42 insertions(+), 103 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index c209bd1..0706292 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -620,61 +620,6 @@ ARCHITECTURE rtl OF video IS ); END COMPONENT; - COMPONENT video_mod_mux_clutctr - PORT - ( - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - BLITTER_RUN : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_BUSY : IN std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VR_D : IN std_logic_vector(8 DOWNTO 0); - COLOR8 : OUT std_logic; - ACP_CLUT_RD : OUT std_logic; - COLOR1 : OUT std_logic; - FALCON_CLUT_RDH : OUT std_logic; - FALCON_CLUT_RDL : OUT std_logic; - ST_CLUT_RD : OUT std_logic; - HSYNC : OUT std_logic; - VSYNC : OUT std_logic; - nBLANK : OUT std_logic; - nSYNC : OUT std_logic; - nPD_VGA : OUT std_logic; - FIFO_RDE : OUT std_logic; - COLOR2 : OUT std_logic; - COLOR4 : OUT std_logic; - PIXEL_CLK : OUT std_logic; - BLITTER_ON : OUT std_logic; - VIDEO_MOD_TA : OUT std_logic; - INTER_ZEI : OUT std_logic; - DOP_FIFO_CLR : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - CLR_FIFO : OUT std_logic; - ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); - BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); - CCSEL : OUT std_logic_vector(2 DOWNTO 0); - CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); - CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); - FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); - ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); - VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0) - ); - END COMPONENT; - SIGNAL ACP_CLUT_RD : std_logic; SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); @@ -1967,7 +1912,7 @@ BEGIN ); - i_video_mod_mux_clutctr : video_mod_mux_clutctr + i_video_mod_mux_clutctr : work.video_mod_mux_clutctr PORT MAP ( nRSTO => nRSTO, diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 86932d6..fc6ec34 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -76,38 +76,38 @@ ENTITY video_mod_mux_clutctr IS CLK_VIDEO : IN std_logic; VR_D : IN std_logic_vector(8 DOWNTO 0); VR_BUSY : IN std_logic; - COLOR8 : BUFFER std_logic; - ACP_CLUT_RD : BUFFER std_logic; - COLOR1 : BUFFER std_logic; - FALCON_CLUT_RDH : BUFFER std_logic; - FALCON_CLUT_RDL : BUFFER std_logic; - FALCON_CLUT_WR : BUFFER std_logic_vector(3 DOWNTO 0); - ST_CLUT_RD : BUFFER std_logic; - ST_CLUT_WR : BUFFER std_logic_vector(1 DOWNTO 0); - CLUT_MUX_ADR : BUFFER std_logic_vector(3 DOWNTO 0); - HSYNC : BUFFER std_logic; - VSYNC : BUFFER std_logic; - nBLANK : BUFFER std_logic; - nSYNC : BUFFER std_logic; - nPD_VGA : BUFFER std_logic; - FIFO_RDE : BUFFER std_logic; - COLOR2 : BUFFER std_logic; - COLOR4 : BUFFER std_logic; - PIXEL_CLK : BUFFER std_logic; - CLUT_OFF : BUFFER std_logic_vector(3 DOWNTO 0); - BLITTER_ON : BUFFER std_logic; - VIDEO_RAM_CTR : BUFFER std_logic_vector(15 DOWNTO 0); - VIDEO_MOD_TA : BUFFER std_logic; - BORDER_COLOR : BUFFER std_logic_vector(23 DOWNTO 0); - CCSEL : BUFFER std_logic_vector(2 DOWNTO 0); - ACP_CLUT_WR : BUFFER std_logic_vector(3 DOWNTO 0); - INTER_ZEI : BUFFER std_logic; - DOP_FIFO_CLR : BUFFER std_logic; - VIDEO_RECONFIG : BUFFER std_logic; - VR_WR : BUFFER std_logic; - VR_RD : BUFFER std_logic; - CLR_FIFO : BUFFER std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + COLOR8 : OUT std_logic; + ACP_CLUT_RD : OUT std_logic; + COLOR1 : OUT std_logic; + FALCON_CLUT_RDH : OUT std_logic; + FALCON_CLUT_RDL : OUT std_logic; + FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + ST_CLUT_RD : OUT std_logic; + ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); + CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); + HSYNC : OUT std_logic; + VSYNC : OUT std_logic; + nBLANK : OUT std_logic; + nSYNC : OUT std_logic; + nPD_VGA : OUT std_logic; + FIFO_RDE : OUT std_logic; + COLOR2 : OUT std_logic; + color4 : OUT std_logic; + PIXEL_CLK : OUT std_logic; + CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); + BLITTER_ON : OUT std_logic; + VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0); + VIDEO_MOD_TA : OUT std_logic; + BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); + CCSEL : OUT std_logic_vector(2 DOWNTO 0); + ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + INTER_ZEI : OUT std_logic; + DOP_FIFO_CLR : OUT std_logic; + VIDEO_RECONFIG : OUT std_logic; + VR_WR : OUT std_logic; + VR_RD : OUT std_logic; + CLR_FIFO : OUT std_logic; + FB_AD : OUT std_logic_vector(31 DOWNTO 0) ); END video_mod_mux_clutctr; @@ -353,6 +353,8 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS VIDEO_PLL_CONFIG_CS, ACP_CLUT, ACP_CLUT_CS, CLK13M_q, CLK13M_clk, CLK13M_d, CLK13M, CLK17M_q, CLK17M_clk, CLK17M_d, CLK17M: std_logic; + SIGNAL color4_i : std_logic; + -- Sub Module Interface Section @@ -448,19 +450,10 @@ BEGIN FIFO_RDE_q <= FIFO_RDE_d; END IF; END PROCESS; - - -- try if an aditional FF will help hold timing - PROCESS - BEGIN - WAIT UNTIL rising_edge(main_clk); - BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); - BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); - BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); - END PROCESS; - -- BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); - -- BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); - -- BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); + BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); + BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); + BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN @@ -1219,7 +1212,7 @@ BEGIN FB_B(2); FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); - CLUT_OFF <= FALCON_SHIFT_MODE_q(3 DOWNTO 0) and sizeIt(COLOR4,4); + CLUT_OFF <= FALCON_SHIFT_MODE_q(3 DOWNTO 0) and sizeIt(COLOR4_i, 4); COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and @@ -1914,7 +1907,7 @@ BEGIN -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or (to_std_logic(SUB_PIXEL_CNT_q(5 DOWNTO 0) = "000001") and COLOR2) or - (to_std_logic(SUB_PIXEL_CNT_q(4 DOWNTO 0) = "00001") and COLOR4) or + (to_std_logic(SUB_PIXEL_CNT_q(4 DOWNTO 0) = "00001") and color4_i) or (to_std_logic(SUB_PIXEL_CNT_q(3 DOWNTO 0) = "0001") and COLOR8) or (to_std_logic(SUB_PIXEL_CNT_q(2 DOWNTO 0) = "001") and COLOR16) or (to_std_logic(SUB_PIXEL_CNT_q(1 DOWNTO 0) = "01") and COLOR24)) and @@ -1930,7 +1923,8 @@ BEGIN -- Assignments added to explicitly combine the -- effects of multiple drivers in the source COLOR16 <= COLOR16_1 or COLOR16_2; - COLOR4 <= COLOR4_1 or COLOR4_2; + color4_i <= COLOR4_1 or COLOR4_2; + color4 <= color4_i; COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; COLOR8 <= COLOR8_1 or COLOR8_2; From 9f01c704dc8b927bc574f9851a7d87fd10e786c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 18 Jan 2016 18:45:17 +0000 Subject: [PATCH 078/127] saved --- FPGA_Quartus_13.1/firebee1.qws | Bin 7748 -> 4388 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index b91970ff6c6c26f4a9ba8047ac6b48c8eff1de53..cca85dd9557194a47310d37395700170f54caeed 100644 GIT binary patch literal 4388 zcmeH~&rcIk5XWZ$ff!@Fh%p*Nj3LB?-z{Z5i2}xigMxZ8!FG2m4TY`U7EKI+lNt}6 zJbBZLc=2EG5Aed(gUV6vnwW^F;3HmaFI+)5Bw0ECq=kGX3(ZGLyTvk zENi*SN|%htHMt^#oOq8NNi-GcBX~VOW7;!}0!cvu^LOpEB3dHpgnZ5tdAsL!-NHH_ zi$ZLit&AtQTgbfjMR`E)apxkp@}N8x&&nk0BF_$p#TyniV%4ZTlsIwdl>y=!hmz7k zACm-g9mKZ>>w6d_r5g$ub@S^rE^YF0Vx^v$Tce31;;f)~4U(TwoepT<7_O`;SNDU* z5gB7o&f;ERlbm8>6a8&LjY=Gr8=M#^DphG4^l5#a9(Xn_(0^Rj-Hz@!ijPAu81c+X zpz}17dZAiH8Xv0_Og5CMnZ9|o%+Q&+ZTKbNZUt$TOBT(7>21ZL&~&G;EN?fnOY6o` zI|jrRxIRwN7inrcAu|~Hc6^Wl;gdT#NfoQ2b7oZT&!(DjRi@%VQ*fR;hFG9?oc?-<9wpG|(A9&Kjgr3JxwBa&BuGG6iNVd6jq8EwbC7D01kD zYJsnT#)^WvXtzLvs&Z?L@bc?*4j}zfQoaHj577AhT(XnqE6r5>fW~JOV^)`YBN5R-Im3e}?I4EO#gRT0n1Y?;G6wQL~h;9|nsx~d1 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17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 19 Jan 2016 07:07:31 +0000 Subject: [PATCH 079/127] removed more "indirect" clocks --- .../Video/video_mod_mux_clutctr.vhd | 1597 ++++++++--------- 1 file changed, 723 insertions(+), 874 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index fc6ec34..2f72315 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -271,24 +271,20 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic; SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic; - SIGNAL ACP_VCTR0_clk_ctrl : std_logic; SIGNAL ACP_VCTR24_ena_ctrl : std_logic; SIGNAL ACP_VCTR16_ena_ctrl : std_logic; SIGNAL ACP_VCTR8_ena_ctrl : std_logic; SIGNAL ACP_VCTR6_ena_ctrl : std_logic; SIGNAL ACP_VCTR0_ena_ctrl : std_logic; - SIGNAL ATARI_HH0_clk_ctrl : std_logic; SIGNAL ATARI_HH24_ena_ctrl : std_logic; SIGNAL ATARI_HH16_ena_ctrl : std_logic; SIGNAL ATARI_HH8_ena_ctrl : std_logic; SIGNAL ATARI_HH0_ena_ctrl : std_logic; - SIGNAL ATARI_VH0_clk_ctrl : std_logic; SIGNAL ATARI_VH24_ena_ctrl : std_logic; SIGNAL ATARI_VH16_ena_ctrl : std_logic; SIGNAL ATARI_VH8_ena_ctrl : std_logic; SIGNAL ATARI_VH0_ena_ctrl : std_logic; - SIGNAL ATARI_HL0_clk_ctrl : std_logic; SIGNAL ATARI_HL24_ena_ctrl : std_logic; SIGNAL ATARI_HL16_ena_ctrl : std_logic; SIGNAL ATARI_HL8_ena_ctrl : std_logic; @@ -298,36 +294,69 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL ATARI_VL16_ena_ctrl : std_logic; SIGNAL ATARI_VL8_ena_ctrl : std_logic; SIGNAL ATARI_VL0_ena_ctrl : std_logic; - SIGNAL VR_DOUT0_clk_ctrl : std_logic; SIGNAL VR_DOUT0_ena_ctrl : std_logic; - SIGNAL VR_FRQ0_clk_ctrl : std_logic; SIGNAL VR_FRQ0_ena_ctrl : std_logic; - SIGNAL CCSEL0_clk_ctrl : std_logic; - SIGNAL BORDER_COLOR0_clk_ctrl : std_logic; - SIGNAL BORDER_COLOR16_ena_ctrl, BORDER_COLOR8_ena_ctrl, - BORDER_COLOR0_ena_ctrl, SYS_CTR0_clk_ctrl, SYS_CTR0_ena_ctrl, - LOF0_clk_ctrl, LOF8_ena_ctrl, LOF0_ena_ctrl, LWD0_clk_ctrl, - LWD8_ena_ctrl, LWD0_ena_ctrl, HHT0_clk_ctrl, HHT8_ena_ctrl, - HHT0_ena_ctrl, HBE0_clk_ctrl, HBE8_ena_ctrl, HBE0_ena_ctrl, - HDB0_clk_ctrl, HDB8_ena_ctrl, HDB0_ena_ctrl, HDE0_clk_ctrl, - HDE8_ena_ctrl, HDE0_ena_ctrl, HBB0_clk_ctrl, HBB8_ena_ctrl, - HBB0_ena_ctrl, HSS0_clk_ctrl, HSS8_ena_ctrl, HSS0_ena_ctrl, - VBE0_clk_ctrl, VBE8_ena_ctrl, VBE0_ena_ctrl, VDB0_clk_ctrl, - VDB8_ena_ctrl, VDB0_ena_ctrl, VDE0_clk_ctrl, VDE8_ena_ctrl, - VDE0_ena_ctrl, VBB0_clk_ctrl, VBB8_ena_ctrl, VBB0_ena_ctrl, - VSS0_clk_ctrl, VSS8_ena_ctrl, VSS0_ena_ctrl, VFT0_clk_ctrl, - VFT8_ena_ctrl, VFT0_ena_ctrl, VCO0_clk_ctrl, VCO0_ena_ctrl, - VCNTRL0_clk_ctrl, VCNTRL0_ena_ctrl, HSY_LEN0_clk_ctrl, - VHCNT0_clk_ctrl, VVCNT0_clk_ctrl, VVCNT0_ena_ctrl, HSYNC_I0_clk_ctrl, - VSYNC_I0_clk_ctrl, VSYNC_I0_ena_ctrl, VERZ2_0_clk_ctrl, - VERZ1_0_clk_ctrl, VERZ0_0_clk_ctrl, RAND0_clk_ctrl, - SUB_PIXEL_CNT0_clk_ctrl, SUB_PIXEL_CNT0_ena_ctrl, - CLUT_MUX_ADR0_clk_ctrl, CLUT_MUX_AV1_0_clk_ctrl, - CLUT_MUX_AV0_0_clk_ctrl, COLOR8_2, COLOR8_1, COLOR1_3, COLOR1_2, - COLOR1_1, COLOR4_2, COLOR4_1, COLOR16_2, COLOR16_1, gnd, u1_enabledt, - u0_enabledt, VCNTRL_CS, VCO_CS, VFT_CS, VSS_CS, VBB_CS, VDE_CS, - VDB_CS, VBE_CS, DOP_FIFO_CLR_q, DOP_FIFO_CLR_clk, DOP_FIFO_CLR_d, - DOP_ZEI_q, DOP_ZEI_clk, DOP_ZEI_d, DOP_ZEI, INTER_ZEI_q, + SIGNAL BORDER_COLOR16_ena_ctrl : std_logic; + SIGNAL BORDER_COLOR8_ena_ctrl : std_logic; + SIGNAL BORDER_COLOR0_ena_ctrl : std_logic; + SIGNAL SYS_CTR0_ena_ctrl : std_logic; + SIGNAL LOF8_ena_ctrl : std_logic; + SIGNAL LOF0_ena_ctrl : std_logic; + SIGNAL LWD8_ena_ctrl : std_logic; + SIGNAL LWD0_ena_ctrl : std_logic; + SIGNAL HHT8_ena_ctrl : std_logic; + SIGNAL HHT0_ena_ctrl : std_logic; + SIGNAL HBE8_ena_ctrl : std_logic; + SIGNAL HBE0_ena_ctrl : std_logic; + SIGNAL HDB8_ena_ctrl : std_logic; + SIGNAL HDB0_ena_ctrl : std_logic; + SIGNAL HDE8_ena_ctrl : std_logic; + SIGNAL HDE0_ena_ctrl : std_logic; + SIGNAL HBB8_ena_ctrl : std_logic; + SIGNAL HBB0_ena_ctrl : std_logic; + SIGNAL HSS0_clk_ctrl : std_logic; + SIGNAL HSS8_ena_ctrl : std_logic; + SIGNAL HSS0_ena_ctrl : std_logic; + SIGNAL VBE8_ena_ctrl : std_logic; + SIGNAL VBE0_ena_ctrl : std_logic; + SIGNAL VDB8_ena_ctrl : std_logic; + SIGNAL VDB0_ena_ctrl : std_logic; + SIGNAL VDE8_ena_ctrl : std_logic; + SIGNAL VDE0_ena_ctrl : std_logic; + SIGNAL VBB8_ena_ctrl : std_logic; + SIGNAL VBB0_ena_ctrl : std_logic; + SIGNAL VSS8_ena_ctrl : std_logic; + SIGNAL VSS0_ena_ctrl : std_logic; + SIGNAL VFT8_ena_ctrl : std_logic; + SIGNAL VFT0_ena_ctrl : std_logic; + SIGNAL VCO0_ena_ctrl : std_logic; + SIGNAL VCNTRL0_ena_ctrl : std_logic; + SIGNAL VVCNT0_ena_ctrl : std_logic; + SIGNAL VSYNC_I0_ena_ctrl : std_logic; + SIGNAL SUB_PIXEL_CNT0_ena_ctrl : std_logic; + SIGNAL COLOR8_2 : std_logic; + SIGNAL COLOR8_1 : std_logic; + SIGNAL COLOR1_3 : std_logic; + SIGNAL COLOR1_2 : std_logic; + SIGNAL COLOR1_1 : std_logic; + SIGNAL COLOR4_2 : std_logic; + SIGNAL COLOR4_1 : std_logic; + SIGNAL COLOR16_2 : std_logic; + SIGNAL COLOR16_1 : std_logic; + SIGNAL gnd : std_logic; + SIGNAL u1_enabledt : std_logic; + SIGNAL u0_enabledt : std_logic; + SIGNAL VCNTRL_CS : std_logic; + SIGNAL VCO_CS : std_logic; + SIGNAL VFT_CS : std_logic; + SIGNAL VSS_CS : std_logic; + SIGNAL VBB_CS : std_logic; + SIGNAL VDE_CS : std_logic; + SIGNAL VDB_CS : std_logic; + SIGNAL VBE_CS : std_logic; + SIGNAL DOP_FIFO_CLR_q : std_logic; + SIGNAL DOP_FIFO_CLR_d : std_logic; + SIGNAL DOP_ZEI_q, DOP_ZEI_clk, DOP_ZEI_d, DOP_ZEI, INTER_ZEI_q, INTER_ZEI_clk, INTER_ZEI_d, ST_VIDEO, FALCON_VIDEO, HSS_CS, HBB_CS, HDE_CS, HDB_CS, HBE_CS, HHT_CS, ATARI_VL_CS, ATARI_HL_CS, ATARI_VH_CS, ATARI_HH_CS, ATARI_SYNC, COLOR24, COLOR16, SYNC_PIX2_q, SYNC_PIX2_clk, @@ -354,6 +383,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS CLK13M_d, CLK13M, CLK17M_q, CLK17M_clk, CLK17M_d, CLK17M: std_logic; SIGNAL color4_i : std_logic; + SIGNAL pixel_clk_i : std_logic; -- Sub Module Interface Section @@ -412,41 +442,41 @@ BEGIN CLUT_MUX_ADR <= CLUT_MUX_ADR_q; - PROCESS (CLUT_MUX_ADR0_clk_ctrl) + PROCESS (pixel_clk_i) BEGIN - IF CLUT_MUX_ADR0_clk_ctrl'EVENT and CLUT_MUX_ADR0_clk_ctrl = '1' THEN + IF rising_edge(pixel_clk_i) THEN CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; END IF; END PROCESS; HSYNC <= HSYNC_q; - PROCESS (HSYNC_clk) + PROCESS (pixel_clk_i) BEGIN - IF HSYNC_clk'EVENT and HSYNC_clk = '1' THEN + IF rising_edge(pixel_clk_i) THEN HSYNC_q <= HSYNC_d; END IF; END PROCESS; VSYNC <= VSYNC_q; - PROCESS (VSYNC_clk) + PROCESS (pixel_clk_i) BEGIN - IF VSYNC_clk'EVENT and VSYNC_clk = '1' THEN + IF rising_edge(pixel_clk_i) THEN VSYNC_q <= VSYNC_d; END IF; END PROCESS; nBLANK <= nBLANK_q; - PROCESS (nBLANK_clk) + PROCESS (pixel_clk_i) BEGIN - IF nBLANK_clk'EVENT and nBLANK_clk = '1' THEN + IF rising_edge(pixel_clk_i) THEN nBLANK_q <= nBLANK_d; END IF; END PROCESS; FIFO_RDE <= FIFO_RDE_q; - PROCESS (FIFO_RDE_clk) + PROCESS (pixel_clk_i) BEGIN - IF FIFO_RDE_clk'EVENT and FIFO_RDE_clk = '1' THEN + IF rising_edge(pixel_clk_i) THEN FIFO_RDE_q <= FIFO_RDE_d; END IF; END PROCESS; @@ -455,8 +485,9 @@ BEGIN BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); - PROCESS (BORDER_COLOR0_clk_ctrl) BEGIN - IF BORDER_COLOR0_clk_ctrl'EVENT and BORDER_COLOR0_clk_ctrl = '1' THEN + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN IF BORDER_COLOR16_ena_ctrl = '1' THEN border_color_q(23 DOWNTO 16) <= border_color_d(23 DOWNTO 16); END IF; @@ -470,99 +501,99 @@ BEGIN END PROCESS; CCSEL <= CCSEL_q; - PROCESS (CCSEL0_clk_ctrl) + PROCESS (pixel_clk_i) BEGIN - IF CCSEL0_clk_ctrl'EVENT and CCSEL0_clk_ctrl = '1' THEN + IF rising_edge(pixel_clk_i) THEN CCSEL_q <= CCSEL_d; END IF; END PROCESS; INTER_ZEI <= INTER_ZEI_q; - PROCESS (INTER_ZEI_clk) + PROCESS (main_clk) BEGIN - IF INTER_ZEI_clk'EVENT and INTER_ZEI_clk = '1' THEN + IF rising_edge(main_clk) THEN INTER_ZEI_q <= INTER_ZEI_d; END IF; END PROCESS; DOP_FIFO_CLR <= DOP_FIFO_CLR_q; - PROCESS (DOP_FIFO_CLR_clk) + PROCESS (pixel_clk_i) BEGIN - IF DOP_FIFO_CLR_clk'EVENT and DOP_FIFO_CLR_clk = '1' THEN + IF rising_edge(pixel_clk_i) THEN DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d; END IF; END PROCESS; VIDEO_RECONFIG <= VIDEO_RECONFIG_q; - PROCESS (VIDEO_RECONFIG_clk) + PROCESS (main_clk) BEGIN - IF VIDEO_RECONFIG_clk'EVENT and VIDEO_RECONFIG_clk = '1' THEN + IF rising_edge(main_clk) THEN VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; END IF; END PROCESS; VR_WR <= VR_WR_q; - PROCESS (VR_WR_clk) + PROCESS (main_clk) BEGIN - IF VR_WR_clk'EVENT and VR_WR_clk = '1' THEN + IF rising_edge(main_clk) THEN VR_WR_q <= VR_WR_d; END IF; END PROCESS; CLR_FIFO <= CLR_FIFO_q; - PROCESS (CLR_FIFO_clk) + PROCESS (pixel_clk_i) BEGIN - IF CLR_FIFO_clk'EVENT and CLR_FIFO_clk = '1' THEN + IF rising_edge(pixel_clk_i) THEN IF CLR_FIFO_ena = '1' THEN CLR_FIFO_q <= CLR_FIFO_d; END IF; END IF; END PROCESS; - PROCESS (CLK17M_clk) + PROCESS (main_clk) BEGIN - IF CLK17M_clk'EVENT and CLK17M_clk = '1' THEN + IF rising_edge(main_clk) THEN CLK17M_q <= CLK17M_d; END IF; END PROCESS; - PROCESS (CLK13M_clk) + PROCESS (clk25m) BEGIN - IF CLK13M_clk'EVENT and CLK13M_clk = '1' THEN + IF rising_edge(clk25m) THEN CLK13M_q <= CLK13M_d; END IF; END PROCESS; - PROCESS (VR_DOUT0_clk_ctrl) + PROCESS (main_clk) BEGIN - IF VR_DOUT0_clk_ctrl'EVENT and VR_DOUT0_clk_ctrl = '1' THEN + IF rising_edge(main_clk) THEN IF VR_DOUT0_ena_ctrl = '1' THEN VR_DOUT_q <= VR_DOUT_d; END IF; END IF; END PROCESS; - PROCESS (VR_FRQ0_clk_ctrl) + PROCESS (main_clk) BEGIN - IF VR_FRQ0_clk_ctrl'EVENT and VR_FRQ0_clk_ctrl = '1' THEN + IF rising_edge(main_clk) THEN IF VR_FRQ0_ena_ctrl = '1' THEN VR_FRQ_q <= VR_FRQ_d; END IF; END IF; END PROCESS; - PROCESS (ST_SHIFT_MODE0_clk_ctrl) + PROCESS (main_clk) BEGIN - IF ST_SHIFT_MODE0_clk_ctrl'EVENT and ST_SHIFT_MODE0_clk_ctrl = '1' THEN + IF rising_edge(main_clk) THEN IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; END IF; END IF; END PROCESS; - PROCESS (FALCON_SHIFT_MODE0_clk_ctrl) + PROCESS (main_clk) BEGIN - IF FALCON_SHIFT_MODE0_clk_ctrl'EVENT and FALCON_SHIFT_MODE0_clk_ctrl = '1' THEN + IF rising_edge(main_clk) THEN IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN falcon_shift_mode_q(10 DOWNTO 8) <= falcon_shift_mode_d(10 DOWNTO 8); END IF; @@ -572,21 +603,23 @@ BEGIN END IF; END PROCESS; - PROCESS (CLUT_MUX_AV1_0_clk_ctrl) BEGIN - if CLUT_MUX_AV1_0_clk_ctrl'EVENT and CLUT_MUX_AV1_0_clk_ctrl='1' THEN - CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; - END IF; - END PROCESS; - - PROCESS (CLUT_MUX_AV0_0_clk_ctrl) BEGIN - if CLUT_MUX_AV0_0_clk_ctrl'EVENT and CLUT_MUX_AV0_0_clk_ctrl='1' THEN - CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; - END IF; - END PROCESS; - - PROCESS (ACP_VCTR0_clk_ctrl) + PROCESS (pixel_clk_i) BEGIN - IF rising_edge(ACP_VCTR0_clk_ctrl) THEN + IF rising_edge(pixel_clk_i) THEN + CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; + END IF; + END PROCESS; + + PROCESS (pixel_clk_i) + BEGIN + IF rising_edge(pixel_clk_i) THEN + CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; + END IF; + END PROCESS; + + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN IF ACP_VCTR24_ena_ctrl = '1' THEN ACP_VCTR_q(31 DOWNTO 24) <= ACP_VCTR_d(31 DOWNTO 24); END IF; @@ -605,319 +638,211 @@ BEGIN END IF; END PROCESS; - PROCESS (SYS_CTR0_clk_ctrl) BEGIN - if SYS_CTR0_clk_ctrl'EVENT and SYS_CTR0_clk_ctrl='1' THEN - if SYS_CTR0_ena_ctrl='1' THEN - SYS_CTR_q <= SYS_CTR_d; - END IF; - END IF; - END PROCESS; - - PROCESS (LOF0_clk_ctrl) BEGIN - if LOF0_clk_ctrl'EVENT and LOF0_clk_ctrl='1' THEN - if LOF8_ena_ctrl='1' THEN - (LOF_q(15), LOF_q(14), LOF_q(13), LOF_q(12), LOF_q(11), LOF_q(10), - LOF_q(9), LOF_q(8)) <= LOF_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (LOF0_clk_ctrl) BEGIN - if LOF0_clk_ctrl'EVENT and LOF0_clk_ctrl='1' THEN - if LOF0_ena_ctrl='1' THEN - (LOF_q(7), LOF_q(6), LOF_q(5), LOF_q(4), LOF_q(3), LOF_q(2), - LOF_q(1), LOF_q(0)) <= LOF_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (LWD0_clk_ctrl) BEGIN - if LWD0_clk_ctrl'EVENT and LWD0_clk_ctrl='1' THEN - if LWD8_ena_ctrl='1' THEN - (LWD_q(15), LWD_q(14), LWD_q(13), LWD_q(12), LWD_q(11), LWD_q(10), - LWD_q(9), LWD_q(8)) <= LWD_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; - - PROCESS (LWD0_clk_ctrl) BEGIN - if LWD0_clk_ctrl'EVENT and LWD0_clk_ctrl='1' THEN - if LWD0_ena_ctrl='1' THEN - (LWD_q(7), LWD_q(6), LWD_q(5), LWD_q(4), LWD_q(3), LWD_q(2), - LWD_q(1), LWD_q(0)) <= LWD_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; - - PROCESS (CLUT_TA_clk) BEGIN - if CLUT_TA_clk'EVENT and CLUT_TA_clk='1' THEN - CLUT_TA_q <= CLUT_TA_d; - END IF; - END PROCESS; - - PROCESS (HSYNC_I0_clk_ctrl) BEGIN - if HSYNC_I0_clk_ctrl'EVENT and HSYNC_I0_clk_ctrl='1' THEN - HSYNC_I_q <= HSYNC_I_d; - END IF; - END PROCESS; - - PROCESS (HSY_LEN0_clk_ctrl) BEGIN - if HSY_LEN0_clk_ctrl'EVENT and HSY_LEN0_clk_ctrl='1' THEN - HSY_LEN_q <= HSY_LEN_d; - END IF; - END PROCESS; - - PROCESS (HSYNC_START_clk) BEGIN - if HSYNC_START_clk'EVENT and HSYNC_START_clk='1' THEN - HSYNC_START_q <= HSYNC_START_d; - END IF; - END PROCESS; - - PROCESS (LAST_clk) BEGIN - if LAST_clk'EVENT and LAST_clk='1' THEN - LAST_q <= LAST_d; - END IF; - END PROCESS; - - PROCESS (VSYNC_START_clk) BEGIN - if VSYNC_START_clk'EVENT and VSYNC_START_clk='1' THEN - if VSYNC_START_ena='1' THEN - VSYNC_START_q <= VSYNC_START_d; - END IF; - END IF; - END PROCESS; - - PROCESS (VSYNC_I0_clk_ctrl) BEGIN - if VSYNC_I0_clk_ctrl'EVENT and VSYNC_I0_clk_ctrl='1' THEN - if VSYNC_I0_ena_ctrl='1' THEN - VSYNC_I_q <= VSYNC_I_d; - END IF; - END IF; - END PROCESS; - - PROCESS (DISP_ON_clk) BEGIN - if DISP_ON_clk'EVENT and DISP_ON_clk='1' THEN - DISP_ON_q <= DISP_ON_d; - END IF; - END PROCESS; - - PROCESS (DPO_ZL_clk) BEGIN - if DPO_ZL_clk'EVENT and DPO_ZL_clk='1' THEN - if DPO_ZL_ena='1' THEN - DPO_ZL_q <= DPO_ZL_d; - END IF; - END IF; - END PROCESS; - - PROCESS (DPO_ON_clk) BEGIN - if DPO_ON_clk'EVENT and DPO_ON_clk='1' THEN - DPO_ON_q <= DPO_ON_d; - END IF; - END PROCESS; - - PROCESS (DPO_OFF_clk) BEGIN - if DPO_OFF_clk'EVENT and DPO_OFF_clk='1' THEN - DPO_OFF_q <= DPO_OFF_d; - END IF; - END PROCESS; - - PROCESS (VDTRON_clk) BEGIN - if VDTRON_clk'EVENT and VDTRON_clk='1' THEN - VDTRON_q <= VDTRON_d; - END IF; - END PROCESS; - - PROCESS (VCO_ZL_clk) BEGIN - if VCO_ZL_clk'EVENT and VCO_ZL_clk='1' THEN - if VCO_ZL_ena='1' THEN - VCO_ZL_q <= VCO_ZL_d; - END IF; - END IF; - END PROCESS; - - PROCESS (VCO_ON_clk) BEGIN - if VCO_ON_clk'EVENT and VCO_ON_clk='1' THEN - VCO_ON_q <= VCO_ON_d; - END IF; - END PROCESS; - - PROCESS (VCO_OFF_clk) BEGIN - if VCO_OFF_clk'EVENT and VCO_OFF_clk='1' THEN - VCO_OFF_q <= VCO_OFF_d; - END IF; - END PROCESS; - - PROCESS (VHCNT0_clk_ctrl) BEGIN - if VHCNT0_clk_ctrl'EVENT and VHCNT0_clk_ctrl='1' THEN - VHCNT_q <= VHCNT_d; - END IF; - END PROCESS; - - PROCESS (SUB_PIXEL_CNT0_clk_ctrl) BEGIN - if SUB_PIXEL_CNT0_clk_ctrl'EVENT and SUB_PIXEL_CNT0_clk_ctrl='1' THEN - if SUB_PIXEL_CNT0_ena_ctrl='1' THEN - SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d; - END IF; - END IF; - END PROCESS; - - PROCESS (VVCNT0_clk_ctrl) BEGIN - if VVCNT0_clk_ctrl'EVENT and VVCNT0_clk_ctrl='1' THEN - if VVCNT0_ena_ctrl='1' THEN - VVCNT_q <= VVCNT_d; - END IF; - END IF; - END PROCESS; - - PROCESS (VERZ2_0_clk_ctrl) BEGIN - if VERZ2_0_clk_ctrl'EVENT and VERZ2_0_clk_ctrl='1' THEN - VERZ2_q <= VERZ2_d; - END IF; - END PROCESS; - - PROCESS (VERZ1_0_clk_ctrl) BEGIN - if VERZ1_0_clk_ctrl'EVENT and VERZ1_0_clk_ctrl='1' THEN - VERZ1_q <= VERZ1_d; - END IF; - END PROCESS; - - PROCESS (VERZ0_0_clk_ctrl) BEGIN - if VERZ0_0_clk_ctrl'EVENT and VERZ0_0_clk_ctrl='1' THEN - VERZ0_q <= VERZ0_d; - END IF; - END PROCESS; - - PROCESS (RAND0_clk_ctrl) BEGIN - if RAND0_clk_ctrl'EVENT and RAND0_clk_ctrl='1' THEN - RAND_q <= RAND_d; - END IF; - END PROCESS; - - PROCESS (START_ZEILE_clk) BEGIN - if START_ZEILE_clk'EVENT and START_ZEILE_clk='1' THEN - if START_ZEILE_ena='1' THEN - START_ZEILE_q <= START_ZEILE_d; - END IF; - END IF; - END PROCESS; - - PROCESS (SYNC_PIX_clk) BEGIN - if SYNC_PIX_clk'EVENT and SYNC_PIX_clk='1' THEN - SYNC_PIX_q <= SYNC_PIX_d; - END IF; - END PROCESS; - - PROCESS (SYNC_PIX1_clk) BEGIN - if SYNC_PIX1_clk'EVENT and SYNC_PIX1_clk='1' THEN - SYNC_PIX1_q <= SYNC_PIX1_d; - END IF; - END PROCESS; - - PROCESS (SYNC_PIX2_clk) BEGIN - if SYNC_PIX2_clk'EVENT and SYNC_PIX2_clk='1' THEN - SYNC_PIX2_q <= SYNC_PIX2_d; - END IF; - END PROCESS; - - PROCESS (ATARI_HH0_clk_ctrl) + PROCESS (main_clk) BEGIN - IF rising_edge(ATARI_HH0_clk_ctrl) THEN + IF rising_edge(main_clk) THEN + IF SYS_CTR0_ena_ctrl='1' THEN + SYS_CTR_q <= SYS_CTR_d; + END IF; + END IF; + END PROCESS; + + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF LOF8_ena_ctrl = '1' THEN + LOF_q(15 DOWNTO 8) <= LOF_d(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; + + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF LOF0_ena_ctrl = '1' THEN + LOF_q(7 DOWNTO 0) <= LOF_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF LWD8_ena_ctrl = '1' THEN + LWD_q(15 DOWNTO 8) <= LWD_d(15 DOWNTO 8); + END IF; + END IF; + END PROCESS; + + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF LWD0_ena_ctrl = '1' THEN + LWD_q(7 DOWNTO 0) <= LWD_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; + + PROCESS (pixel_clk_i) + BEGIN + IF rising_edge(pixel_clk_i) THEN + CLUT_TA_q <= CLUT_TA_d; + END IF; + END PROCESS; + + PROCESS (pixel_clk_i) + BEGIN + IF rising_edge(pixel_clk_i) THEN + HSYNC_I_q <= HSYNC_I_d; + END IF; + END PROCESS; + + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + HSY_LEN_q <= HSY_LEN_d; + END IF; + END PROCESS; + + PROCESS (pixel_clk_i) + BEGIN + IF rising_edge(pixel_clk_i) THEN + HSYNC_START_q <= HSYNC_START_d; + + LAST_q <= LAST_d; + + IF VSYNC_START_ena = '1' THEN + VSYNC_START_q <= VSYNC_START_d; + END IF; + + IF VSYNC_I0_ena_ctrl='1' THEN + VSYNC_I_q <= VSYNC_I_d; + END IF; + + DISP_ON_q <= DISP_ON_d; + + IF DPO_ZL_ena = '1' THEN + DPO_ZL_q <= DPO_ZL_d; + END IF; + + DPO_ON_q <= DPO_ON_d; + DPO_OFF_q <= DPO_OFF_d; + VDTRON_q <= VDTRON_d; + + IF VCO_ZL_ena = '1' THEN + VCO_ZL_q <= VCO_ZL_d; + END IF; + + VCO_ON_q <= VCO_ON_d; + VCO_OFF_q <= VCO_OFF_d; + VHCNT_q <= VHCNT_d; + + IF SUB_PIXEL_CNT0_ena_ctrl = '1' THEN + SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d; + END IF; + + IF VVCNT0_ena_ctrl='1' THEN + VVCNT_q <= VVCNT_d; + END IF; + + VERZ2_q <= VERZ2_d; + VERZ1_q <= VERZ1_d; + VERZ0_q <= VERZ0_d; + RAND_q <= RAND_d; + + IF START_ZEILE_ena = '1' THEN + START_ZEILE_q <= START_ZEILE_d; + END IF; + + SYNC_PIX_q <= SYNC_PIX_d; + SYNC_PIX1_q <= SYNC_PIX1_d; + SYNC_PIX2_q <= SYNC_PIX2_d; + IF ATARI_HH24_ena_ctrl = '1' THEN ATARI_HH_q(31 DOWNTO 24) <= ATARI_HH_d(31 DOWNTO 24); END IF; + IF ATARI_HH16_ena_ctrl = '1' THEN ATARI_HH_q(23 DOWNTO 16) <= ATARI_HH_d(23 DOWNTO 16); END IF; + IF ATARI_HH8_ena_ctrl = '1' THEN ATARI_HH_q(15 DOWNTO 8) <= ATARI_HH_d(15 DOWNTO 8); END IF; + IF ATARI_HH0_ena_ctrl = '1' THEN ATARI_HH_q(7 DOWNTO 0) <= ATARI_HH_d(7 DOWNTO 0); END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_VH0_clk_ctrl) - BEGIN - IF rising_edge(ATARI_VH0_clk_ctrl) THEN + IF ATARI_VH24_ena_ctrl = '1' THEN ATARI_VH_q(31 DOWNTO 24) <= ATARI_VH_d(31 DOWNTO 24); END IF; + IF ATARI_VH16_ena_ctrl = '1' THEN ATARI_VH_q(23 DOWNTO 16) <= ATARI_VH_d(23 DOWNTO 16); END IF; + IF ATARI_VH8_ena_ctrl = '1' THEN ATARI_VH_q(15 DOWNTO 8) <= ATARI_VH_d(15 DOWNTO 8); END IF; + IF ATARI_VH0_ena_ctrl='1' THEN ATARI_VH_q(7 DOWNTO 0) <= ATARI_VH_d(7 DOWNTO 0); END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_HL0_clk_ctrl) BEGIN - IF rising_edge(ATARI_HL0_clk_ctrl) THEN + IF ATARI_HL24_ena_ctrl = '1' THEN ATARI_HL_q(31 DOWNTO 24) <= ATARI_HL_d(31 DOWNTO 24); END IF; + IF ATARI_HL16_ena_ctrl = '1' THEN ATARI_HL_q(23 DOWNTO 16) <= ATARI_HL_d(23 DOWNTO 16); END IF; + IF ATARI_HL8_ena_ctrl = '1' THEN ATARI_HL_q(15 DOWNTO 8) <= ATARI_HL_d(15 DOWNTO 8); END IF; + IF ATARI_HL0_ena_ctrl = '1' THEN ATARI_HL_q(7 DOWNTO 0) <= ATARI_HL_d(7 DOWNTO 0); END IF; - END IF; - END PROCESS; - - PROCESS (ATARI_VL0_clk_ctrl) - BEGIN - IF rising_edge(ATARI_VL0_clk_ctrl) THEN + IF ATARI_VL24_ena_ctrl = '1' THEN ATARI_VL_q(31 DOWNTO 24) <= ATARI_VL_d(31 DOWNTO 24); END IF; + IF ATARI_VL16_ena_ctrl = '1' THEN ATARI_VL_q(23 DOWNTO 16) <= ATARI_VL_d(23 DOWNTO 16); END IF; + IF ATARI_VL8_ena_ctrl = '1' THEN ATARI_VL_q(15 DOWNTO 8) <= ATARI_VL_d(15 DOWNTO 8); END IF; + IF ATARI_VL0_ena_ctrl = '1' THEN ATARI_VL_q(7 DOWNTO 0) <= ATARI_VL_d(7 DOWNTO 0); END IF; - END IF; - END PROCESS; - - - PROCESS (HHT0_clk_ctrl) - BEGIN - IF rising_edge(HHT0_clk_ctrl) THEN + IF HHT8_ena_ctrl = '1' THEN HHT_q(11 DOWNTO 8) <= HHT_d(11 DOWNTO 8); END IF; + IF HHT0_ena_ctrl = '1' THEN HHT_q(7 DOWNTO 0) <= HHT_d(7 DOWNTO 0); END IF; - END IF; - END PROCESS; - - PROCESS (HBE0_clk_ctrl) - BEGIN - IF rising_edge(HBE0_clk_ctrl) THEN + IF HBE8_ena_ctrl = '1' THEN HBE_q(11 DOWNTO 8) <= HBE_d(11 DOWNTO 8); END IF; + IF HBE0_ena_ctrl = '1' THEN HBE_q(7 DOWNTO 0) <= HBE_d(7 DOWNTO 0); END IF; END IF; END PROCESS; - PROCESS (HDB0_clk_ctrl) + PROCESS (main_clk) BEGIN - IF rising_edge(HDB0_clk_ctrl) THEN + IF rising_edge(main_clk) THEN IF HDB8_ena_ctrl = '1' THEN HDB_q(11 DOWNTO 8) <= HDB_d(11 DOWNTO 8); END IF; @@ -927,618 +852,553 @@ BEGIN END IF; END PROCESS; - PROCESS (HDE0_clk_ctrl) + PROCESS (main_clk) BEGIN - if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN - if HDE8_ena_ctrl='1' THEN - (HDE_q(11), HDE_q(10), HDE_q(9), HDE_q(8)) <= HDE_d(11 DOWNTO 8); - END IF; - END IF; - END PROCESS; + IF rising_edge(main_clk) THEN + IF HDE8_ena_ctrl = '1' THEN + HDE_q(11 DOWNTO 8) <= HDE_d(11 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (HDE0_clk_ctrl) BEGIN - if HDE0_clk_ctrl'EVENT and HDE0_clk_ctrl='1' THEN - if HDE0_ena_ctrl='1' THEN - (HDE_q(7), HDE_q(6), HDE_q(5), HDE_q(4), HDE_q(3), HDE_q(2), - HDE_q(1), HDE_q(0)) <= HDE_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF HDE0_ena_ctrl = '1' THEN + HDE_q(7 DOWNTO 0) <= HDE_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (HBB0_clk_ctrl) BEGIN - if HBB0_clk_ctrl'EVENT and HBB0_clk_ctrl='1' THEN - if HBB8_ena_ctrl='1' THEN - (HBB_q(11), HBB_q(10), HBB_q(9), HBB_q(8)) <= HBB_d(11 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF HBB8_ena_ctrl = '1' THEN + HBB_q(11 DOWNTO 8) <= HBB_d(11 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (HBB0_clk_ctrl) BEGIN - if HBB0_clk_ctrl'EVENT and HBB0_clk_ctrl='1' THEN - if HBB0_ena_ctrl='1' THEN - (HBB_q(7), HBB_q(6), HBB_q(5), HBB_q(4), HBB_q(3), HBB_q(2), - HBB_q(1), HBB_q(0)) <= HBB_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF HBB0_ena_ctrl = '1' THEN + HBB_q(7 DOWNTO 0) <= HBB_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (HSS0_clk_ctrl) BEGIN - if HSS0_clk_ctrl'EVENT and HSS0_clk_ctrl='1' THEN - if HSS8_ena_ctrl='1' THEN - (HSS_q(11), HSS_q(10), HSS_q(9), HSS_q(8)) <= HSS_d(11 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF HSS8_ena_ctrl = '1' THEN + HSS_q(11 DOWNTO 8) <= HSS_d(11 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (HSS0_clk_ctrl) BEGIN - if HSS0_clk_ctrl'EVENT and HSS0_clk_ctrl='1' THEN - if HSS0_ena_ctrl='1' THEN - (HSS_q(7), HSS_q(6), HSS_q(5), HSS_q(4), HSS_q(3), HSS_q(2), - HSS_q(1), HSS_q(0)) <= HSS_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF HSS0_ena_ctrl='1' THEN + HSS_q(7 DOWNTO 0) <= HSS_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (DOP_ZEI_clk) BEGIN - if DOP_ZEI_clk'EVENT and DOP_ZEI_clk='1' THEN - DOP_ZEI_q <= DOP_ZEI_d; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + DOP_ZEI_q <= DOP_ZEI_d; + END IF; + END PROCESS; - PROCESS (VBE0_clk_ctrl) BEGIN - if VBE0_clk_ctrl'EVENT and VBE0_clk_ctrl='1' THEN - if VBE8_ena_ctrl='1' THEN - (VBE_q(10), VBE_q(9), VBE_q(8)) <= VBE_d(10 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VBE8_ena_ctrl = '1' THEN + VBE_q(10 DOWNTO 8) <= VBE_d(10 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (VBE0_clk_ctrl) BEGIN - if VBE0_clk_ctrl'EVENT and VBE0_clk_ctrl='1' THEN - if VBE0_ena_ctrl='1' THEN - (VBE_q(7), VBE_q(6), VBE_q(5), VBE_q(4), VBE_q(3), VBE_q(2), - VBE_q(1), VBE_q(0)) <= VBE_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VBE0_ena_ctrl = '1' THEN + VBE_q(7 DOWNTO 0) <= VBE_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VDB0_clk_ctrl) BEGIN - if VDB0_clk_ctrl'EVENT and VDB0_clk_ctrl='1' THEN - if VDB8_ena_ctrl='1' THEN - (VDB_q(10), VDB_q(9), VDB_q(8)) <= VDB_d(10 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VDB8_ena_ctrl = '1' THEN + VDB_q(10 DOWNTO 8) <= VDB_d(10 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (VDB0_clk_ctrl) BEGIN - if VDB0_clk_ctrl'EVENT and VDB0_clk_ctrl='1' THEN - if VDB0_ena_ctrl='1' THEN - (VDB_q(7), VDB_q(6), VDB_q(5), VDB_q(4), VDB_q(3), VDB_q(2), - VDB_q(1), VDB_q(0)) <= VDB_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VDB0_ena_ctrl = '1' THEN + VDB_q(7 DOWNTO 0) <= VDB_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VDE0_clk_ctrl) BEGIN - if VDE0_clk_ctrl'EVENT and VDE0_clk_ctrl='1' THEN - if VDE8_ena_ctrl='1' THEN - (VDE_q(10), VDE_q(9), VDE_q(8)) <= VDE_d(10 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VDE8_ena_ctrl = '1' THEN + VDE_q(10 DOWNTO 8) <= VDE_d(10 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (VDE0_clk_ctrl) BEGIN - if VDE0_clk_ctrl'EVENT and VDE0_clk_ctrl='1' THEN - if VDE0_ena_ctrl='1' THEN - (VDE_q(7), VDE_q(6), VDE_q(5), VDE_q(4), VDE_q(3), VDE_q(2), - VDE_q(1), VDE_q(0)) <= VDE_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VDE0_ena_ctrl = '1' THEN + VDE_q(7 DOWNTO 0) <= VDE_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VBB0_clk_ctrl) BEGIN - if VBB0_clk_ctrl'EVENT and VBB0_clk_ctrl='1' THEN - if VBB8_ena_ctrl='1' THEN - (VBB_q(10), VBB_q(9), VBB_q(8)) <= VBB_d(10 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VBB8_ena_ctrl = '1' THEN + VBB_q(10 DOWNTO 8) <= VBB_d(10 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (VBB0_clk_ctrl) BEGIN - if VBB0_clk_ctrl'EVENT and VBB0_clk_ctrl='1' THEN - if VBB0_ena_ctrl='1' THEN - (VBB_q(7), VBB_q(6), VBB_q(5), VBB_q(4), VBB_q(3), VBB_q(2), - VBB_q(1), VBB_q(0)) <= VBB_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VBB0_ena_ctrl = '1' THEN + VBB_q(7 DOWNTO 0) <= VBB_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VSS0_clk_ctrl) BEGIN - if VSS0_clk_ctrl'EVENT and VSS0_clk_ctrl='1' THEN - if VSS8_ena_ctrl='1' THEN - (VSS_q(10), VSS_q(9), VSS_q(8)) <= VSS_d(10 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VSS8_ena_ctrl = '1' THEN + VSS_q(10 DOWNTO 8) <= VSS_d(10 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (VSS0_clk_ctrl) BEGIN - if VSS0_clk_ctrl'EVENT and VSS0_clk_ctrl='1' THEN - if VSS0_ena_ctrl='1' THEN - (VSS_q(7), VSS_q(6), VSS_q(5), VSS_q(4), VSS_q(3), VSS_q(2), - VSS_q(1), VSS_q(0)) <= VSS_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VSS0_ena_ctrl = '1' THEN + VSS_q(7 DOWNTO 0) <= VSS_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VFT0_clk_ctrl) BEGIN - if VFT0_clk_ctrl'EVENT and VFT0_clk_ctrl='1' THEN - if VFT8_ena_ctrl='1' THEN - (VFT_q(10), VFT_q(9), VFT_q(8)) <= VFT_d(10 DOWNTO 8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VFT8_ena_ctrl = '1' THEN + VFT_q(10 DOWNTO 8) <= VFT_d(10 DOWNTO 8); + END IF; + END IF; + END PROCESS; - PROCESS (VFT0_clk_ctrl) BEGIN - if VFT0_clk_ctrl'EVENT and VFT0_clk_ctrl='1' THEN - if VFT0_ena_ctrl='1' THEN - (VFT_q(7), VFT_q(6), VFT_q(5), VFT_q(4), VFT_q(3), VFT_q(2), - VFT_q(1), VFT_q(0)) <= VFT_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VFT0_ena_ctrl = '1' THEN + VFT_q(7 DOWNTO 0) <= VFT_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VCO0_clk_ctrl) BEGIN - if VCO0_clk_ctrl'EVENT and VCO0_clk_ctrl='1' THEN - if VCO_ena(8)='1' THEN - VCO_q(8) <= VCO_d(8); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VCO_ena(8) = '1' THEN + VCO_q(8) <= VCO_d(8); + END IF; + END IF; + END PROCESS; - PROCESS (VCO0_clk_ctrl) BEGIN - if VCO0_clk_ctrl'EVENT and VCO0_clk_ctrl='1' THEN - if VCO0_ena_ctrl='1' THEN - (VCO_q(7), VCO_q(6), VCO_q(5), VCO_q(4), VCO_q(3), VCO_q(2), - VCO_q(1), VCO_q(0)) <= VCO_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VCO0_ena_ctrl = '1' THEN + VCO_q(7 DOWNTO 0) <= VCO_d(7 DOWNTO 0); + END IF; + END IF; + END PROCESS; - PROCESS (VCNTRL0_clk_ctrl) BEGIN - if VCNTRL0_clk_ctrl'EVENT and VCNTRL0_clk_ctrl='1' THEN - if VCNTRL0_ena_ctrl='1' THEN - VCNTRL_q <= VCNTRL_d; - END IF; - END IF; - END PROCESS; + PROCESS (main_clk) + BEGIN + IF rising_edge(main_clk) THEN + IF VCNTRL0_ena_ctrl = '1' THEN + VCNTRL_q <= VCNTRL_d; + END IF; + END IF; + END PROCESS; -- Start of original equations --- BYT SELECT 32 BIT --- ADR==0 - FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00"); + -- BYT SELECT 32 BIT + -- ADR==0 + FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00"); --- ADR==1 --- HIGH WORD --- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not + -- ADR==1 + -- HIGH WORD + -- LONG UND LINE + FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); --- ADR==2 --- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and - FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + -- ADR==2 + -- LONG UND LINE + FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); --- ADR==3 --- LOW WORD --- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not - FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) - and (not FB_SIZE0)); + -- ADR==3 + -- LOW WORD + -- LONG UND LINE + FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or + (FB_SIZE1 and FB_SIZE0) or + ((not FB_SIZE1) and (not FB_SIZE0)); --- BYT SELECT 16 BIT --- ADR==0 - FB_16B(0) <= to_std_logic(FB_ADR(0) = '0'); + -- BYT SELECT 16 BIT + -- ADR==0 + FB_16B(0) <= to_std_logic(FB_ADR(0) = '0'); --- ADR==1 --- NOT BYT - FB_16B(1) <= to_std_logic(FB_ADR(0) = '1') or (not ((not FB_SIZE1) and - FB_SIZE0)); + -- ADR==1 + -- NOT BYT + FB_16B(1) <= to_std_logic(FB_ADR(0) = '1') or (not ((not FB_SIZE1) and FB_SIZE0)); --- ACP CLUT -- --- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = "000000000000000000"); - ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); - ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); - CLUT_TA_clk <= MAIN_CLK; - CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not - VIDEO_MOD_TA); + -- ACP CLUT -- + -- 0-3FF/1024 + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = "000000000000000000"); + ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); + ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); + CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not VIDEO_MOD_TA); --- FALCON CLUT -- --- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 10) - = "1111100110"); + -- FALCON CLUT -- + -- $F9800/$400 + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 10) = "1111100110"); --- HIGH WORD - FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); + -- HIGH WORD + FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); --- LOW WORD - FALCON_CLUT_RDL <= FALCON_CLUT_CS and (not nFB_OE) and FB_ADR(1); - FALCON_CLUT_WR(1 DOWNTO 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & - (not FB_ADR(1))) and std_logic_vector'(FALCON_CLUT_CS & - FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - FALCON_CLUT_WR(3 DOWNTO 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & - FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and - std_logic_vector'((not nFB_WR) & (not nFB_WR)); + -- LOW WORD + FALCON_CLUT_RDL <= FALCON_CLUT_CS and (not nFB_OE) and FB_ADR(1); + FALCON_CLUT_WR(1 DOWNTO 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & + (not FB_ADR(1))) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + FALCON_CLUT_WR(3 DOWNTO 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and + std_logic_vector'((not nFB_WR) & (not nFB_WR)); --- ST CLUT -- --- $F8240/$20 - ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 5) = - "111110000010010"); - ST_CLUT_RD <= ST_CLUT_CS and (not nFB_OE); - ST_CLUT_WR <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and - std_logic_vector'((not nFB_WR) & (not nFB_WR)); + -- ST CLUT -- + -- $F8240/$20 + ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 5) = "111110000010010"); + ST_CLUT_RD <= ST_CLUT_CS and (not nFB_OE); + ST_CLUT_WR <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); --- ST SHIFT MODE - ST_SHIFT_MODE0_clk_ctrl <= MAIN_CLK; + -- ST SHIFT MODE --- $F8260/2 - ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) - = "1111100000100110000"); - ST_SHIFT_MODE_d <= FB_AD(25 DOWNTO 24); - ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); + -- $F8260/2 + ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100110000"); + ST_SHIFT_MODE_d <= FB_AD(25 DOWNTO 24); + ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); --- MONO - COLOR1_1 <= to_std_logic(ST_SHIFT_MODE_q = "10") and (not COLOR8) and - ST_VIDEO and (not ACP_VIDEO_ON); + -- MONO + COLOR1_1 <= to_std_logic(ST_SHIFT_MODE_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); --- 4 FARBEN - COLOR2 <= to_std_logic(ST_SHIFT_MODE_q = "01") and (not COLOR8) and ST_VIDEO - and (not ACP_VIDEO_ON); + -- 4 FARBEN + COLOR2 <= to_std_logic(ST_SHIFT_MODE_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); --- 16 FARBEN - COLOR4_1 <= to_std_logic(ST_SHIFT_MODE_q = "00") and (not COLOR8) and - ST_VIDEO and (not ACP_VIDEO_ON); + -- 16 FARBEN + COLOR4_1 <= to_std_logic(ST_SHIFT_MODE_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); --- FALCON SHIFT MODE - FALCON_SHIFT_MODE0_clk_ctrl <= MAIN_CLK; + -- FALCON SHIFT MODE --- $F8266/2 - FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 - DOWNTO 1) = "1111100000100110011"); - FALCON_SHIFT_MODE_d <= FB_AD(26 DOWNTO 16); - FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and - FB_B(2); - FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and - FB_B(3); - CLUT_OFF <= FALCON_SHIFT_MODE_q(3 DOWNTO 0) and sizeIt(COLOR4_i, 4); - COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and - FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and - (not ACP_VIDEO_ON); - COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO - and (not ACP_VIDEO_ON); + -- $F8266/2 + FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100110011"); + FALCON_SHIFT_MODE_d <= FB_AD(26 DOWNTO 16); + FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(2); + FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); --- ACP VIDEO CONTROL --- BIT 0 = ACP VIDEO ON --- BIT 1 = POWER ON VIDEO DAC --- BIT 2 = ACP 24BIT --- BIT 3 = ACP 16BIT --- BIT 4 = ACP 8BIT --- BIT 5 = ACP 1BIT --- BIT 6 = FALCON SHIFT MODE --- BIT 7 = ST SHIFT MODE --- BIT 9..8 = VCLK FREQUENZ --- BIT 15 =-SYNC ALLOWED --- BIT 31..16 = VIDEO_RAM_CTR --- BIT 25 = RANDFARBE EINSCHALTEN --- BIT 26 = STANDARD ATARI SYNCS - ACP_VCTR0_clk_ctrl <= MAIN_CLK; + CLUT_OFF <= FALCON_SHIFT_MODE_q(3 DOWNTO 0) and sizeIt(COLOR4_i, 4); + COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); --- $400/4 - ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000000"); + -- ACP VIDEO CONTROL + -- BIT 0 = ACP VIDEO ON + -- BIT 1 = POWER ON VIDEO DAC + -- BIT 2 = ACP 24BIT + -- BIT 3 = ACP 16BIT + -- BIT 4 = ACP 8BIT + -- BIT 5 = ACP 1BIT + -- BIT 6 = FALCON SHIFT MODE + -- BIT 7 = ST SHIFT MODE + -- BIT 9..8 = VCLK FREQUENZ + -- BIT 15 =-SYNC ALLOWED + -- BIT 31..16 = VIDEO_RAM_CTR + -- BIT 25 = RANDFARBE EINSCHALTEN + -- BIT 26 = STANDARD ATARI SYNCS + + -- $400/4 + ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000000"); - ACP_VCTR_d(31 DOWNTO 8) <= FB_AD(31 DOWNTO 8); - ACP_VCTR_d(5 DOWNTO 0) <= FB_AD(5 DOWNTO 0); + ACP_VCTR_d(31 DOWNTO 8) <= FB_AD(31 DOWNTO 8); + ACP_VCTR_d(5 DOWNTO 0) <= FB_AD(5 DOWNTO 0); - ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); - ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); - ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); - ACP_VCTR0_ena_ctrl <= ACP_VCTR_CS and FB_B(3) and (not nFB_WR); - ACP_VIDEO_ON <= ACP_VCTR_q(0); - nPD_VGA <= ACP_VCTR_q(1); + ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); + ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); + ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); + ACP_VCTR0_ena_ctrl <= ACP_VCTR_CS and FB_B(3) and (not nFB_WR); + ACP_VIDEO_ON <= ACP_VCTR_q(0); + nPD_VGA <= ACP_VCTR_q(1); --- ATARI MODUS --- WENN 1 AUTOMATISCHE AUFLÖSUNG - ATARI_SYNC <= ACP_VCTR_q(26); + -- ATARI MODUS + -- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC <= ACP_VCTR_q(26); --- HORIZONTAL TIMING 640x480 - ATARI_HH0_clk_ctrl <= MAIN_CLK; + -- HORIZONTAL TIMING 640x480 --- $410/4 - ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000000000100000100"); - ATARI_HH_d <= FB_AD; - ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); - ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); - ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); - ATARI_HH0_ena_ctrl <= ATARI_HH_CS and FB_B(3) and (not nFB_WR); + -- $410/4 + ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000100"); + ATARI_HH_d <= FB_AD; + ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); + ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); + ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); + ATARI_HH0_ena_ctrl <= ATARI_HH_CS and FB_B(3) and (not nFB_WR); --- VERTIKAL TIMING 640x480 - ATARI_VH0_clk_ctrl <= MAIN_CLK; + -- VERTIKAL TIMING 640x480 --- $414/4 - ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000000000100000101"); - ATARI_VH_d <= FB_AD; - ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); - ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); - ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); - ATARI_VH0_ena_ctrl <= ATARI_VH_CS and FB_B(3) and (not nFB_WR); + -- $414/4 + ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000101"); + ATARI_VH_d <= FB_AD; + ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); + ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); + ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); + ATARI_VH0_ena_ctrl <= ATARI_VH_CS and FB_B(3) and (not nFB_WR); --- HORIZONTAL TIMING 320x240 - ATARI_HL0_clk_ctrl <= MAIN_CLK; + -- HORIZONTAL TIMING 320x240 --- $418/4 - ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000000000100000110"); - ATARI_HL_d <= FB_AD; - ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); - ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); - ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); - ATARI_HL0_ena_ctrl <= ATARI_HL_CS and FB_B(3) and (not nFB_WR); + -- $418/4 + ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000110"); + ATARI_HL_d <= FB_AD; + ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); + ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); + ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); + ATARI_HL0_ena_ctrl <= ATARI_HL_CS and FB_B(3) and (not nFB_WR); --- VERTIKAL TIMING 320x240 - ATARI_VL0_clk_ctrl <= MAIN_CLK; + -- VERTIKAL TIMING 320x240 --- $41C/4 - ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000000000100000111"); - ATARI_VL_d <= FB_AD; - ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); - ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); - ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); - ATARI_VL0_ena_ctrl <= ATARI_VL_CS and FB_B(3) and (not nFB_WR); + -- $41C/4 + ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000111"); + ATARI_VL_d <= FB_AD; + ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); + ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); + ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); + ATARI_VL0_ena_ctrl <= ATARI_VL_CS and FB_B(3) and (not nFB_WR); --- VIDEO PLL CONFIG --- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO - 9) = "0000000000000000011") and FB_B(0) and FB_B(1); - VR_WR_clk <= MAIN_CLK; - VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not - VR_WR_q); - VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); - VR_DOUT0_clk_ctrl <= MAIN_CLK; - VR_DOUT0_ena_ctrl <= not VR_BUSY; - VR_DOUT_d <= VR_D; - VR_FRQ0_clk_ctrl <= MAIN_CLK; - VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 DOWNTO 0) = - "000000100"); - VR_FRQ_d <= FB_AD(23 DOWNTO 16); + -- VIDEO PLL CONFIG + -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 9) = "0000000000000000011") and FB_B(0) and FB_B(1); + VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q); + VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); + VR_DOUT0_ena_ctrl <= not VR_BUSY; + VR_DOUT_d <= VR_D; + VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 DOWNTO 0) = "000000100"); + VR_FRQ_d <= FB_AD(23 DOWNTO 16); --- VIDEO PLL RECONFIG --- $(F)000'0800 - VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 - DOWNTO 0) = "0000000000000000100000000000") and FB_B(0); - VIDEO_RECONFIG_clk <= MAIN_CLK; - VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) - and (not VIDEO_RECONFIG_q); + -- VIDEO PLL RECONFIG + -- $(F)000'0800 + VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 0) = "0000000000000000100000000000") and FB_B(0); + VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); --- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR <= ACP_VCTR_q(31 DOWNTO 16); + -- ---------------------------------------------------------------------------------------------------------------------- + VIDEO_RAM_CTR <= ACP_VCTR_q(31 DOWNTO 16); --- ------------ COLOR MODE IM ACP SETZEN - COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) - and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR8_2 <= ACP_VCTR_q(4) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) - and ACP_VIDEO_ON; - COLOR16_2 <= ACP_VCTR_q(3) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR24 <= ACP_VCTR_q(2) and ACP_VIDEO_ON; - ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); + -- ------------ COLOR MODE IM ACP SETZEN + COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; + COLOR8_2 <= ACP_VCTR_q(4) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; + COLOR16_2 <= ACP_VCTR_q(3) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; + COLOR24 <= ACP_VCTR_q(2) and ACP_VIDEO_ON; + ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not - ACP_VIDEO_ON); - ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); - FALCON_VIDEO <= ACP_VCTR_q(7); - FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); - ST_VIDEO <= ACP_VCTR_q(6); - ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not - COLOR1); - CCSEL0_clk_ctrl <= PIXEL_CLK; + ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); + FALCON_VIDEO <= ACP_VCTR_q(7); + FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); + ST_VIDEO <= ACP_VCTR_q(6); + ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not COLOR1); + pixel_clk_i <= pixel_clk; --- ONLY FOR INFORMATION - CCSEL_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and - sizeIt(FALCON_CLUT,3)) or ("100" and sizeIt(ACP_CLUT,3)) or ("101" and - sizeIt(COLOR16,3)) or ("110" and sizeIt(COLOR24,3)) or ("111" and - sizeIt(RAND_ON,3)); + -- ONLY FOR INFORMATION + CCSEL_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and + sizeIt(FALCON_CLUT,3)) or ("100" and sizeIt(ACP_CLUT,3)) or ("101" and + sizeIt(COLOR16,3)) or ("110" and sizeIt(COLOR24,3)) or ("111" and + sizeIt(RAND_ON,3)); --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE - BORDER_COLOR0_clk_ctrl <= MAIN_CLK; + -- DIVERSE (VIDEO)-REGISTER ---------------------------- + -- RANDFARBE --- $404/4 - BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001"); - BORDER_COLOR_d <= FB_AD(23 DOWNTO 0); - BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); - BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); - BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); + -- $404/4 + BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001"); + BORDER_COLOR_d <= FB_AD(23 DOWNTO 0); + BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); + BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); + BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); --- System Config Register --- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi --- |||||||| --- |||||||+- RAM Wait Status --- ||||||| 0 = 1 Wait (default) --- ||||||| 1 = 0 Wait --- ||||||+-- Video Bus Width --- |||||| 0 = 16 Bit --- |||||| 1 = 32 Bit (default) --- ||||++--- ROM Wait Status --- |||| 00 = reserved --- |||| 01 = 2 Wait (default) --- |||| 10 = 1 Wait --- |||| 11 = 0 Wait --- ||++----- Main Memory Size --- || 01 = 4 MB --- || 10 = 16 MB --- ++------- Monitor Type --- 00 Monochrome --- 01 RGB --- 10 VGA --- 11 TV --- $8006/2 - SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000000000011"); - SYS_CTR0_clk_ctrl <= MAIN_CLK; - SYS_CTR_d <= FB_AD(22 DOWNTO 16); - SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); - BLITTER_ON <= not SYS_CTR_q(3); + -- System Config Register + -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi + -- |||||||| + -- |||||||+- RAM Wait Status + -- ||||||| 0 = 1 Wait (default) + -- ||||||| 1 = 0 Wait + -- ||||||+-- Video Bus Width + -- |||||| 0 = 16 Bit + -- |||||| 1 = 32 Bit (default) + -- ||||++--- ROM Wait Status + -- |||| 00 = reserved + -- |||| 01 = 2 Wait (default) + -- |||| 10 = 1 Wait + -- |||| 11 = 0 Wait + -- ||++----- Main Memory Size + -- || 01 = 4 MB + -- || 10 = 16 MB + -- ++------- Monitor Type + -- 00 Monochrome + -- 01 RGB + -- 10 VGA + -- 11 TV + -- $8006/2 + SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000000000011"); + SYS_CTR_d <= FB_AD(22 DOWNTO 16); + SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); + BLITTER_ON <= not SYS_CTR_q(3); --- LOF --- $820E/2 - LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000100000111"); - LOF0_clk_ctrl <= MAIN_CLK; - LOF_d <= FB_AD(31 DOWNTO 16); - LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); - LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); + -- LOF + -- $820E/2 + LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000111"); + LOF_d <= FB_AD(31 DOWNTO 16); + LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); + LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); --- LWD --- $8210/2 - LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000100001000"); - LWD0_clk_ctrl <= MAIN_CLK; - LWD_d <= FB_AD(31 DOWNTO 16); - LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); - LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); + -- LWD + -- $8210/2 + LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100001000"); + LWD_d <= FB_AD(31 DOWNTO 16); + LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); + LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); --- HORIZONTAL --- HHT --- $8282/2 - HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101000001"); - HHT0_clk_ctrl <= MAIN_CLK; - HHT_d <= FB_AD(27 DOWNTO 16); - HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); - HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); + -- HORIZONTAL + -- HHT + -- $8282/2 + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000001"); + HHT_d <= FB_AD(27 DOWNTO 16); + HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); + HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); --- HBE --- $8286/2 - HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101000011"); - HBE0_clk_ctrl <= MAIN_CLK; - HBE_d <= FB_AD(27 DOWNTO 16); - HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); - HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); + -- HBE + -- $8286/2 + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000011"); + HBE_d <= FB_AD(27 DOWNTO 16); + HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); + HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); --- HDB --- $8288/2 - HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101000100"); - HDB0_clk_ctrl <= MAIN_CLK; - HDB_d <= FB_AD(27 DOWNTO 16); - HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); - HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); + -- HDB + -- $8288/2 + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000100"); + HDB_d <= FB_AD(27 DOWNTO 16); + HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); + HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); --- HDE --- $828A/2 - HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101000101"); - HDE0_clk_ctrl <= MAIN_CLK; - HDE_d <= FB_AD(27 DOWNTO 16); - HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); - HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); + -- HDE + -- $828A/2 + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000101"); + HDE_d <= FB_AD(27 DOWNTO 16); + HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); + HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); --- HBB --- $8284/2 - HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101000010"); - HBB0_clk_ctrl <= MAIN_CLK; - HBB_d <= FB_AD(27 DOWNTO 16); - HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); - HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); + -- HBB + -- $8284/2 + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000010"); + HBB_d <= FB_AD(27 DOWNTO 16); + HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); + HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); --- HSS --- Videl HSYNC start register $828C / 2 - HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101000110"); - HSS0_clk_ctrl <= MAIN_CLK; - HSS_d <= FB_AD(27 DOWNTO 16); - HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); - HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); + -- HSS + -- Videl HSYNC start register $828C / 2 + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000110"); + HSS_d <= FB_AD(27 DOWNTO 16); + HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); + HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); --- VERTIKAL --- VBE --- $82A6/2 - VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101010011"); - VBE0_clk_ctrl <= MAIN_CLK; - VBE_d <= FB_AD(26 DOWNTO 16); - VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); - VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); + -- VERTIKAL + -- VBE + -- $82A6/2 + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010011"); + VBE_d <= FB_AD(26 DOWNTO 16); + VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); + VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); --- VDB --- $82A8/2 - VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101010100"); - VDB0_clk_ctrl <= MAIN_CLK; - VDB_d <= FB_AD(26 DOWNTO 16); - VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); - VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); + -- VDB + -- $82A8/2 + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010100"); + VDB_d <= FB_AD(26 DOWNTO 16); + VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); + VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); --- VDE --- $82AA/2 - VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101010101"); - VDE0_clk_ctrl <= MAIN_CLK; - VDE_d <= FB_AD(26 DOWNTO 16); - VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); - VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); + -- VDE + -- $82AA/2 + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010101"); + VDE_d <= FB_AD(26 DOWNTO 16); + VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); + VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); --- VBB --- $82A4/2 - VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101010010"); - VBB0_clk_ctrl <= MAIN_CLK; - VBB_d <= FB_AD(26 DOWNTO 16); - VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); - VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); + -- VBB + -- $82A4/2 + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010010"); + VBB_d <= FB_AD(26 DOWNTO 16); + VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); + VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); --- VSS --- $82AC/2 - VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101010110"); - VSS0_clk_ctrl <= MAIN_CLK; - VSS_d <= FB_AD(26 DOWNTO 16); - VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); - VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); + -- VSS + -- $82AC/2 + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010110"); + VSS_d <= FB_AD(26 DOWNTO 16); + VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); + VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); --- VFT --- $82A2/2 - VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101010001"); - VFT0_clk_ctrl <= MAIN_CLK; - VFT_d <= FB_AD(26 DOWNTO 16); - VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); - VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); + -- VFT + -- $82A2/2 + VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010001"); + VFT_d <= FB_AD(26 DOWNTO 16); + VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); + VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); --- VCO --- $82C0 / 2 Falcon clock control register VCO - VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = - "1111100000101100000"); - VCO0_clk_ctrl <= MAIN_CLK; - VCO_d <= FB_AD(24 DOWNTO 16); - VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); - VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); + -- VCO + -- $82C0 / 2 Falcon clock control register VCO + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100000"); + VCO_d <= FB_AD(24 DOWNTO 16); + VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); + VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); --- VCNTRL --- $82C2 / 2 Falcon resolution control register VCNTRL + -- VCNTRL + -- $82C2 / 2 Falcon resolution control register VCNTRL VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100001"); - VCNTRL0_clk_ctrl <= MAIN_CLK; VCNTRL_d <= FB_AD(19 DOWNTO 16); VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); @@ -1612,9 +1472,6 @@ BEGIN -- ------------------------------------------------------------ -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -- -------------------------------------------------------------- - -- HSY_LEN[].CLK = MAIN_CLK; - -- check if this is better (mfro) - HSY_LEN0_clk_ctrl <= PIXEL_CLK; -- 320 pixels, 32 MHz, RGB -- 320 pixels, 25.175 MHz, VGA @@ -1661,7 +1518,6 @@ BEGIN and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) < unsigned(std_logic_vector(unsigned(HDIS_END) - 1))))) or (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); - DOP_FIFO_CLR_clk <= PIXEL_CLK; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; @@ -1742,9 +1598,9 @@ BEGIN -- ZÄHLER LAST_clk <= PIXEL_CLK; LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); - VHCNT0_clk_ctrl <= PIXEL_CLK; + VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); - VVCNT0_clk_ctrl <= PIXEL_CLK; + VVCNT0_ena_ctrl <= LAST_q; VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); @@ -1785,7 +1641,7 @@ BEGIN -- VERZÖGERUNG UND SYNC HSYNC_START_clk <= PIXEL_CLK; HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); - HSYNC_I0_clk_ctrl <= PIXEL_CLK; + HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or ((std_logic_vector(unsigned(HSYNC_I_q) - 1)) and sizeIt(not HSYNC_START_q,8) and sizeIt(to_std_logic(HSYNC_I_q /= @@ -1795,7 +1651,6 @@ BEGIN -- start am ende der Zeile vor dem vsync VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); - VSYNC_I0_clk_ctrl <= PIXEL_CLK; -- start am ende der Zeile vor dem vsync VSYNC_I0_ena_ctrl <= LAST_q; @@ -1804,9 +1659,6 @@ BEGIN -- runterzählen bis 0 VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); - VERZ2_0_clk_ctrl <= PIXEL_CLK; - VERZ1_0_clk_ctrl <= PIXEL_CLK; - VERZ0_0_clk_ctrl <= PIXEL_CLK; (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); @@ -1861,7 +1713,6 @@ BEGIN nSYNC <= gnd; -- RANDFARBE MACHEN ------------------------------------ - RAND0_clk_ctrl <= PIXEL_CLK; RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); RAND_d(1) <= RAND_q(0); RAND_d(2) <= RAND_q(1); @@ -1897,7 +1748,7 @@ BEGIN -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; - SUB_PIXEL_CNT0_clk_ctrl <= PIXEL_CLK; + SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; -- count up if display on sonst clear bei sync pix @@ -1912,9 +1763,7 @@ BEGIN (to_std_logic(SUB_PIXEL_CNT_q(2 DOWNTO 0) = "001") and COLOR16) or (to_std_logic(SUB_PIXEL_CNT_q(1 DOWNTO 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; From 1846f7eff25f1c103822f8118248b159f7d6ac4a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 19 Jan 2016 07:27:27 +0000 Subject: [PATCH 080/127] remove specialised clocks --- .../Video/video_mod_mux_clutctr.vhd | 53 ++++--------------- 1 file changed, 11 insertions(+), 42 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 2f72315..19d0e56 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -635,48 +635,23 @@ BEGIN IF ACP_VCTR0_ena_ctrl = '1' THEN ACP_VCTR_q(5 DOWNTO 0) <= ACP_VCTR_d(5 DOWNTO 0); END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN + IF SYS_CTR0_ena_ctrl='1' THEN SYS_CTR_q <= SYS_CTR_d; END IF; - END IF; - END PROCESS; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN IF LOF8_ena_ctrl = '1' THEN LOF_q(15 DOWNTO 8) <= LOF_d(15 DOWNTO 8); END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN + IF LOF0_ena_ctrl = '1' THEN LOF_q(7 DOWNTO 0) <= LOF_d(7 DOWNTO 0); END IF; - END IF; - END PROCESS; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN IF LWD8_ena_ctrl = '1' THEN LWD_q(15 DOWNTO 8) <= LWD_d(15 DOWNTO 8); END IF; - END IF; - END PROCESS; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN IF LWD0_ena_ctrl = '1' THEN LWD_q(7 DOWNTO 0) <= LWD_d(7 DOWNTO 0); END IF; @@ -697,9 +672,9 @@ BEGIN END IF; END PROCESS; - PROCESS (main_clk) + PROCESS (pixel_clk_i) BEGIN - IF rising_edge(main_clk) THEN + IF rising_edge(pixel_clk_i) THEN HSY_LEN_q <= HSY_LEN_d; END IF; END PROCESS; @@ -1622,32 +1597,32 @@ BEGIN DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); -- DATENTRANSFER ON OFF - VCO_ON_clk <= PIXEL_CLK; - + + -- BESSER EINZELN WEGEN TIMING VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); VCO_OFF_clk <= PIXEL_CLK; VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); - VCO_ZL_clk <= PIXEL_CLK; + -- AM ZEILENENDE ÜBERNEHMEN VCO_ZL_ena <= LAST_q; -- 1 ZEILE DAVOR ON OFF VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); - VDTRON_clk <= PIXEL_CLK; + VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); -- VERZÖGERUNG UND SYNC - HSYNC_START_clk <= PIXEL_CLK; + HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or ((std_logic_vector(unsigned(HSYNC_I_q) - 1)) and sizeIt(not HSYNC_START_q,8) and sizeIt(to_std_logic(HSYNC_I_q /= "00000000"),8)); - VSYNC_START_clk <= PIXEL_CLK; - VSYNC_START_ena <= LAST_q; + + VSYNC_START_ena <= LAST_q; -- start am ende der Zeile vor dem vsync VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); @@ -1696,7 +1671,6 @@ BEGIN nblank_d <= verz0_q(8); -- nBLANK_d <= DISP_ON_q; - HSYNC_clk <= PIXEL_CLK; -- HSYNC = VERZ[1][9]; -- NUR MÖGLICH WENN BEIDE @@ -1726,7 +1700,6 @@ BEGIN -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); -- -------------------------------------------------------- - CLR_FIFO_clk <= PIXEL_CLK; CLR_FIFO_ena <= LAST_q; -- IN LETZTER ZEILE LÖSCHEN @@ -1736,15 +1709,12 @@ BEGIN -- ZEILE 1 START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); - SYNC_PIX_clk <= PIXEL_CLK; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; - SYNC_PIX1_clk <= PIXEL_CLK; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; - SYNC_PIX2_clk <= PIXEL_CLK; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; @@ -1753,7 +1723,6 @@ BEGIN -- count up if display on sonst clear bei sync pix SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - FIFO_RDE_clk <= PIXEL_CLK; -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or From 752b4cd0ad7e33224e0908f9553bf12768e0bc20 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 19 Jan 2016 15:50:36 +0000 Subject: [PATCH 081/127] modify to use WHEN statements instead of binary logic --- .../Video/video_mod_mux_clutctr.vhd | 189 ++++++++++++------ 1 file changed, 128 insertions(+), 61 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 19d0e56..c4b2d63 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -356,36 +356,120 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL VBE_CS : std_logic; SIGNAL DOP_FIFO_CLR_q : std_logic; SIGNAL DOP_FIFO_CLR_d : std_logic; - SIGNAL DOP_ZEI_q, DOP_ZEI_clk, DOP_ZEI_d, DOP_ZEI, INTER_ZEI_q, - INTER_ZEI_clk, INTER_ZEI_d, ST_VIDEO, FALCON_VIDEO, HSS_CS, HBB_CS, - HDE_CS, HDB_CS, HBE_CS, HHT_CS, ATARI_VL_CS, ATARI_HL_CS, ATARI_VH_CS, - ATARI_HH_CS, ATARI_SYNC, COLOR24, COLOR16, SYNC_PIX2_q, SYNC_PIX2_clk, - SYNC_PIX2_d, SYNC_PIX2, SYNC_PIX1_q, SYNC_PIX1_clk, SYNC_PIX1_d, - SYNC_PIX1, SYNC_PIX_q, SYNC_PIX_clk, SYNC_PIX_d, SYNC_PIX, - START_ZEILE_q, START_ZEILE_ena, START_ZEILE_clk, START_ZEILE_d, - START_ZEILE, CLR_FIFO_q, CLR_FIFO_ena, CLR_FIFO_clk, CLR_FIFO_d, - FIFO_RDE_q, FIFO_RDE_clk, FIFO_RDE_d, RAND_ON, VCO_OFF_q, VCO_OFF_clk, - VCO_OFF_d, VCO_OFF, VCO_ON_q, VCO_ON_clk, VCO_ON_d, VCO_ON, VCO_ZL_q, - VCO_ZL_ena, VCO_ZL_clk, VCO_ZL_d, VCO_ZL, VDTRON_q, VDTRON_clk, - VDTRON_d, VDTRON, DPO_OFF_q, DPO_OFF_clk, DPO_OFF_d, DPO_OFF, - DPO_ON_q, DPO_ON_clk, DPO_ON_d, DPO_ON, DPO_ZL_q, DPO_ZL_ena, - DPO_ZL_clk, DPO_ZL_d, DPO_ZL, DISP_ON_q, DISP_ON_clk, DISP_ON_d, - DISP_ON, nBLANK_q, nBLANK_clk, nBLANK_d, VSYNC_START_q, - VSYNC_START_ena, VSYNC_START_clk, VSYNC_START_d, VSYNC_START, VSYNC_q, - VSYNC_clk, VSYNC_d, LAST_q, LAST_clk, LAST_d, LAST, HSYNC_START_q, - HSYNC_START_clk, HSYNC_START_d, HSYNC_START, HSYNC_q, HSYNC_clk, - HSYNC_d, CLUT_TA_q, CLUT_TA_clk, CLUT_TA_d, CLUT_TA, LWD_CS, LOF_CS, - SYS_CTR_CS, ACP_VIDEO_ON, BORDER_COLOR_CS, ACP_VCTR_CS, - FALCON_SHIFT_MODE_CS, ST_SHIFT_MODE_CS, ST_CLUT, ST_CLUT_CS, - FALCON_CLUT, FALCON_CLUT_CS, VIDEO_RECONFIG_q, VIDEO_RECONFIG_clk, - VIDEO_RECONFIG_d, VIDEO_PLL_RECONFIG_CS, VR_WR_q, VR_WR_clk, VR_WR_d, - VIDEO_PLL_CONFIG_CS, ACP_CLUT, ACP_CLUT_CS, CLK13M_q, CLK13M_clk, - CLK13M_d, CLK13M, CLK17M_q, CLK17M_clk, CLK17M_d, CLK17M: std_logic; - - SIGNAL color4_i : std_logic; - SIGNAL pixel_clk_i : std_logic; + SIGNAL DOP_ZEI_q : std_logic; + SIGNAL DOP_ZEI_d : std_logic; + SIGNAL DOP_ZEI : std_logic; + SIGNAL INTER_ZEI_q : std_logic; + SIGNAL INTER_ZEI_d : std_logic; + SIGNAL ST_VIDEO : std_logic; + SIGNAL FALCON_VIDEO : std_logic; + SIGNAL HSS_CS : std_logic; + SIGNAL HBB_CS : std_logic; + SIGNAL HDE_CS : std_logic; + SIGNAL HDB_CS : std_logic; + SIGNAL HBE_CS : std_logic; + SIGNAL HHT_CS : std_logic; + SIGNAL ATARI_VL_CS : std_logic; + SIGNAL ATARI_HL_CS : std_logic; + SIGNAL ATARI_VH_CS : std_logic; + SIGNAL ATARI_HH_CS : std_logic; + SIGNAL ATARI_SYNC : std_logic; + SIGNAL COLOR24 : std_logic; + SIGNAL COLOR16 : std_logic; + SIGNAL SYNC_PIX2_q : std_logic; + SIGNAL SYNC_PIX2_d : std_logic; + SIGNAL SYNC_PIX2 : std_logic; + SIGNAL SYNC_PIX1_q : std_logic; + SIGNAL SYNC_PIX1_d : std_logic; + SIGNAL SYNC_PIX1 : std_logic; + SIGNAL SYNC_PIX_q : std_logic; + SIGNAL SYNC_PIX_d : std_logic; + SIGNAL SYNC_PIX : std_logic; + SIGNAL START_ZEILE_q : std_logic; + SIGNAL START_ZEILE_ena : std_logic; + SIGNAL START_ZEILE_d : std_logic; + SIGNAL START_ZEILE : std_logic; + SIGNAL CLR_FIFO_q : std_logic; + SIGNAL CLR_FIFO_ena : std_logic; + SIGNAL CLR_FIFO_d : std_logic; + SIGNAL FIFO_RDE_q : std_logic; + SIGNAL FIFO_RDE_d : std_logic; + SIGNAL RAND_ON : std_logic; + SIGNAL VCO_OFF_q : std_logic; + SIGNAL VCO_OFF_d : std_logic; + SIGNAL VCO_OFF : std_logic; + SIGNAL VCO_ON_q : std_logic; + SIGNAL VCO_ON_d : std_logic; + SIGNAL VCO_ON : std_logic; + SIGNAL VCO_ZL_q : std_logic; + SIGNAL VCO_ZL_ena : std_logic; + SIGNAL VCO_ZL_d : std_logic; + SIGNAL VCO_ZL : std_logic; + SIGNAL VDTRON_q : std_logic; + SIGNAL VDTRON_d : std_logic; + SIGNAL VDTRON : std_logic; + SIGNAL DPO_OFF_q : std_logic; + SIGNAL DPO_OFF_d : std_logic; + SIGNAL DPO_OFF : std_logic; + SIGNAL DPO_ON_q : std_logic; + SIGNAL DPO_ON_d : std_logic; + SIGNAL DPO_ON : std_logic; + SIGNAL DPO_ZL_q : std_logic; + SIGNAL DPO_ZL_ena : std_logic; + SIGNAL DPO_ZL_d : std_logic; + SIGNAL DPO_ZL : std_logic; + SIGNAL DISP_ON_q : std_logic; + SIGNAL DISP_ON_d : std_logic; + SIGNAL DISP_ON : std_logic; + SIGNAL nBLANK_q : std_logic; + SIGNAL nBLANK_d : std_logic; + SIGNAL VSYNC_START_q : std_logic; + SIGNAL VSYNC_START_ena : std_logic; + SIGNAL VSYNC_START_d : std_logic; + SIGNAL VSYNC_START : std_logic; + SIGNAL VSYNC_q : std_logic; + SIGNAL VSYNC_d : std_logic; + SIGNAL LAST_q : std_logic; + SIGNAL LAST_d : std_logic; + SIGNAL LAST : std_logic; + SIGNAL HSYNC_START_q : std_logic; + SIGNAL HSYNC_START_d : std_logic; + SIGNAL HSYNC_START : std_logic; + SIGNAL HSYNC_q : std_logic; + SIGNAL HSYNC_d : std_logic; + SIGNAL CLUT_TA_q : std_logic; + SIGNAL CLUT_TA_d : std_logic; + SIGNAL CLUT_TA : std_logic; + SIGNAL LWD_CS : std_logic; + SIGNAL LOF_CS : std_logic; + SIGNAL SYS_CTR_CS : std_logic; + SIGNAL ACP_VIDEO_ON : std_logic; + SIGNAL BORDER_COLOR_CS : std_logic; + SIGNAL ACP_VCTR_CS : std_logic; + SIGNAL FALCON_SHIFT_MODE_CS : std_logic; + SIGNAL ST_SHIFT_MODE_CS : std_logic; + SIGNAL ST_CLUT : std_logic; + SIGNAL ST_CLUT_CS : std_logic; + SIGNAL FALCON_CLUT : std_logic; + SIGNAL FALCON_CLUT_CS : std_logic; + SIGNAL VIDEO_RECONFIG_q : std_logic; + SIGNAL VIDEO_RECONFIG_d : std_logic; + SIGNAL VIDEO_PLL_RECONFIG_CS : std_logic; + SIGNAL VR_WR_q : std_logic; + SIGNAL VR_WR_d : std_logic; + SIGNAL VIDEO_PLL_CONFIG_CS : std_logic; + SIGNAL ACP_CLUT : std_logic; + SIGNAL ACP_CLUT_CS : std_logic; + SIGNAL CLK13M_q : std_logic; + SIGNAL CLK13M_d : std_logic; + SIGNAL CLK13M : std_logic; + SIGNAL CLK17M_q : std_logic; + SIGNAL CLK17M_d : std_logic; + SIGNAL CLK17M : std_logic; + SIGNAL color4_i : std_logic; + SIGNAL pixel_clk_i : std_logic; --- Sub Module Interface Section + -- Sub Module Interface Section COMPONENT lpm_bustri_WORD @@ -1426,10 +1510,7 @@ BEGIN VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; -- VIDEO AUSGABE SETZEN - CLK17M_clk <= CLK33M; CLK17M_d <= not CLK17M_q; - - CLK13M_clk <= CLK25M; CLK13M_d <= not CLK13M_q; -- 320 pixels, 32 MHz, @@ -1453,22 +1534,21 @@ BEGIN -- 640 pixels, 32 MHz, RGB -- 640 pixels, 25.175 MHz, VGA -- hsync pulse length in pixeln = frequenz / = 500ns - HSY_LEN_d <= ("00001110" and sizeIt(not ACP_VIDEO_ON,8) and - (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and - ((sizeIt(VCNTRL_q(2),8) and sizeIt(VCO_q(2),8)) or - sizeIt(VCO_q(0),8))) or ("00010000" and sizeIt(not ACP_VIDEO_ON,8) and - (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and - ((sizeIt(VCNTRL_q(2),8) and sizeIt(not VCO_q(2),8)) or - sizeIt(VCO_q(0),8))) or ("00011100" and sizeIt(not ACP_VIDEO_ON,8) and - (sizeIt(FALCON_VIDEO,8) or sizeIt(ST_VIDEO,8)) and sizeIt(not - VCNTRL_q(2),8) and sizeIt(VCO_q(2),8) and sizeIt(not VCO_q(0),8)) or - ("00100000" and sizeIt(not ACP_VIDEO_ON,8) and (sizeIt(FALCON_VIDEO,8) - or sizeIt(ST_VIDEO,8)) and sizeIt(not VCNTRL_q(2),8) and sizeIt(not - VCO_q(2),8) and sizeIt(not VCO_q(0),8)) or ("00011100" and - sizeIt(ACP_VIDEO_ON,8) and sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) - = "00"),8)) or ("00100000" and sizeIt(ACP_VIDEO_ON,8) and - sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "01"),8)) or - ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 DOWNTO 1))))) and sizeIt(ACP_VIDEO_ON,8) and sizeIt(ACP_VCTR_q(9),8)); + HSY_LEN_d <= std_logic_vector'(d"14") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') ELSE + std_logic_vector'(d"16") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') ELSE + std_logic_vector'(d"28") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' ELSE + std_logic_vector'(d"32") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' ELSE + std_logic_vector'(d"28") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "00" ELSE + std_logic_vector'(d"32") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "01" ELSE + std_logic_vector(16 + unsigned("0" & vr_frq(7 DOWNTO 1))) WHEN acp_video_on and acp_vctr(9); + + -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or + -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or + -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "00"), 8)) or + -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "01"), 8)) or + -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 DOWNTO 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(ACP_VCTR_q(9), 8)); -- MULTIPLIKATIONS FAKTOR MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or @@ -1481,11 +1561,8 @@ BEGIN and sizeIt(not VCNTRL_q(2),12)); -- DOPPELZEILENMODUS - DOP_ZEI_clk <= MAIN_CLK; - -- ZEILENVERDOPPELUNG EIN AUS DOP_ZEI_d <= VCNTRL_q(0) and (FALCON_VIDEO or ST_VIDEO); - INTER_ZEI_clk <= PIXEL_CLK; -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC @@ -1571,7 +1648,6 @@ BEGIN sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); -- ZÄHLER - LAST_clk <= PIXEL_CLK; LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); @@ -1580,20 +1656,15 @@ BEGIN VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); -- DISPLAY ON OFF - DPO_ZL_clk <= PIXEL_CLK; - -- 1 ZEILE DAVOR ON OFF DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); -- AM ZEILENENDE ÜBERNEHMEN DPO_ZL_ena <= LAST_q; - DPO_ON_clk <= PIXEL_CLK; -- BESSER EINZELN WEGEN TIMING DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); - DPO_OFF_clk <= PIXEL_CLK; DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); - DISP_ON_clk <= PIXEL_CLK; DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); -- DATENTRANSFER ON OFF @@ -1601,7 +1672,6 @@ BEGIN -- BESSER EINZELN WEGEN TIMING VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); - VCO_OFF_clk <= PIXEL_CLK; VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); @@ -1665,7 +1735,6 @@ BEGIN VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); - nBLANK_clk <= PIXEL_CLK; -- nBLANK = VERZ[0][8]; nblank_d <= verz0_q(8); @@ -1677,7 +1746,6 @@ BEGIN HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); - VSYNC_clk <= PIXEL_CLK; -- VSYNC = VERZ[2][9]; -- NUR MÖGLICH WENN BEIDE @@ -1704,7 +1772,6 @@ BEGIN -- IN LETZTER ZEILE LÖSCHEN CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); - START_ZEILE_clk <= PIXEL_CLK; START_ZEILE_ena <= LAST_q; -- ZEILE 1 From 5f55a6738a45f367bcf665dcd68edb297ceb7c8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 19 Jan 2016 17:36:29 +0000 Subject: [PATCH 082/127] cast to std_logic_vector --- FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index c4b2d63..bd5765c 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -265,9 +265,9 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL u0_tridata : std_logic_vector(15 DOWNTO 0); SIGNAL u1_data : std_logic_vector(15 DOWNTO 0); SIGNAL u1_tridata : std_logic_vector(15 DOWNTO 0); - SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic; + -- SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic; SIGNAL ST_SHIFT_MODE0_ena_ctrl : std_logic; - SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; + -- SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic; SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic; @@ -1540,7 +1540,7 @@ BEGIN std_logic_vector'(d"32") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' ELSE std_logic_vector'(d"28") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "00" ELSE std_logic_vector'(d"32") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "01" ELSE - std_logic_vector(16 + unsigned("0" & vr_frq(7 DOWNTO 1))) WHEN acp_video_on and acp_vctr(9); + std_logic_vector'(d"16" + unsigned("0" & vr_frq(7 DOWNTO 1))) WHEN acp_video_on = '1' and acp_vctr(9) = '1' ; -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or From accc7e85f0ad7df9a7a718b2c734682a01c40f2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 10 Feb 2016 17:06:57 +0000 Subject: [PATCH 083/127] make it compile again --- FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index bd5765c..0e648d5 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -468,6 +468,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL CLK17M : std_logic; SIGNAL color4_i : std_logic; SIGNAL pixel_clk_i : std_logic; + SIGNAL calc_freq : unsigned(7 DOWNTO 0); -- Sub Module Interface Section @@ -1372,7 +1373,7 @@ BEGIN -- HBE -- $8286/2 - HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000011"); + HBE_CS <= '1' WHEN nFB_CS1 ='0' and FB_ADR(19 DOWNTO 1) = "1111100000101000011" ELSE '0'; HBE_d <= FB_AD(27 DOWNTO 16); HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); @@ -1534,13 +1535,14 @@ BEGIN -- 640 pixels, 32 MHz, RGB -- 640 pixels, 25.175 MHz, VGA -- hsync pulse length in pixeln = frequenz / = 500ns + calc_freq <= 8d"16" + unsigned("0" & vr_frq(7 DOWNTO 1)); HSY_LEN_d <= std_logic_vector'(d"14") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') ELSE std_logic_vector'(d"16") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') ELSE std_logic_vector'(d"28") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' ELSE std_logic_vector'(d"32") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' ELSE std_logic_vector'(d"28") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "00" ELSE std_logic_vector'(d"32") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "01" ELSE - std_logic_vector'(d"16" + unsigned("0" & vr_frq(7 DOWNTO 1))) WHEN acp_video_on = '1' and acp_vctr(9) = '1' ; + std_logic_vector(calc_freq) WHEN acp_video_on = '1' and acp_vctr(9) = '1' ; -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or From 8114dcadf3672ef370c4061a852db970b4578f6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Apr 2016 05:56:39 +0000 Subject: [PATCH 084/127] fix hsync len calculation for Firebee mode --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 2 +- .../Video/video_mod_mux_clutctr.vhd | 697 +++++++++--------- 2 files changed, 346 insertions(+), 353 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 3536347..d5e2740 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -621,7 +621,7 @@ BEGIN ); -- Start of original equations - LINE <= FB_SIZE0 and FB_SIZE1; + line <= fb_size0 and fb_size1; -- BYT SELECT -- ADR==0 diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 0e648d5..31ea155 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -69,22 +69,22 @@ ENTITY video_mod_mux_clutctr IS FB_SIZE0 : IN std_logic; FB_SIZE1 : IN std_logic; nFB_BURST : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); + FB_ADR : IN std_logic_vector(31 downto 0); CLK33M : IN std_logic; CLK25M : IN std_logic; BLITTER_RUN : IN std_logic; CLK_VIDEO : IN std_logic; - VR_D : IN std_logic_vector(8 DOWNTO 0); + VR_D : IN std_logic_vector(8 downto 0); VR_BUSY : IN std_logic; COLOR8 : OUT std_logic; ACP_CLUT_RD : OUT std_logic; COLOR1 : OUT std_logic; FALCON_CLUT_RDH : OUT std_logic; FALCON_CLUT_RDL : OUT std_logic; - FALCON_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + FALCON_CLUT_WR : OUT std_logic_vector(3 downto 0); ST_CLUT_RD : OUT std_logic; - ST_CLUT_WR : OUT std_logic_vector(1 DOWNTO 0); - CLUT_MUX_ADR : OUT std_logic_vector(3 DOWNTO 0); + ST_CLUT_WR : OUT std_logic_vector(1 downto 0); + CLUT_MUX_ADR : OUT std_logic_vector(3 downto 0); HSYNC : OUT std_logic; VSYNC : OUT std_logic; nBLANK : OUT std_logic; @@ -94,20 +94,20 @@ ENTITY video_mod_mux_clutctr IS COLOR2 : OUT std_logic; color4 : OUT std_logic; PIXEL_CLK : OUT std_logic; - CLUT_OFF : OUT std_logic_vector(3 DOWNTO 0); + CLUT_OFF : OUT std_logic_vector(3 downto 0); BLITTER_ON : OUT std_logic; - VIDEO_RAM_CTR : OUT std_logic_vector(15 DOWNTO 0); + VIDEO_RAM_CTR : OUT std_logic_vector(15 downto 0); VIDEO_MOD_TA : OUT std_logic; - BORDER_COLOR : OUT std_logic_vector(23 DOWNTO 0); - CCSEL : OUT std_logic_vector(2 DOWNTO 0); - ACP_CLUT_WR : OUT std_logic_vector(3 DOWNTO 0); + BORDER_COLOR : OUT std_logic_vector(23 downto 0); + CCSEL : OUT std_logic_vector(2 downto 0); + ACP_CLUT_WR : OUT std_logic_vector(3 downto 0); INTER_ZEI : OUT std_logic; DOP_FIFO_CLR : OUT std_logic; VIDEO_RECONFIG : OUT std_logic; VR_WR : OUT std_logic; VR_RD : OUT std_logic; CLR_FIFO : OUT std_logic; - FB_AD : OUT std_logic_vector(31 DOWNTO 0) + FB_AD : OUT std_logic_vector(31 downto 0) ); END video_mod_mux_clutctr; @@ -124,147 +124,147 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS -- VERTIKAL TIMING 320x240 -- HORIZONTAL -- VERTIKAL - SIGNAL VR_DOUT : std_logic_vector(8 DOWNTO 0); - SIGNAL VR_DOUT_d : std_logic_vector(8 DOWNTO 0); - SIGNAL VR_DOUT_q : std_logic_vector(8 DOWNTO 0); - SIGNAL VR_FRQ : std_logic_vector(7 DOWNTO 0); - SIGNAL VR_FRQ_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VR_FRQ_q : std_logic_vector(7 DOWNTO 0); - SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_16B : std_logic_vector(1 DOWNTO 0); - SIGNAL ST_SHIFT_MODE : std_logic_vector(1 DOWNTO 0); - SIGNAL ST_SHIFT_MODE_d : std_logic_vector(1 DOWNTO 0); - SIGNAL ST_SHIFT_MODE_q : std_logic_vector(1 DOWNTO 0); - SIGNAL FALCON_SHIFT_MODE : std_logic_vector(10 DOWNTO 0); - SIGNAL FALCON_SHIFT_MODE_d : std_logic_vector(10 DOWNTO 0); - SIGNAL FALCON_SHIFT_MODE_q : std_logic_vector(10 DOWNTO 0); - SIGNAL CLUT_MUX_ADR_d : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_ADR_q : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV1 : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV1_d : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV1_q : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV0 : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV0_d : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_MUX_AV0_q : std_logic_vector(3 DOWNTO 0); - SIGNAL ACP_VCTR : std_logic_vector(31 DOWNTO 0); - SIGNAL ACP_VCTR_d : std_logic_vector(31 DOWNTO 0); - SIGNAL ACP_VCTR_q : std_logic_vector(31 DOWNTO 0); - SIGNAL BORDER_COLOR_d : std_logic_vector(23 DOWNTO 0); - SIGNAL BORDER_COLOR_q : std_logic_vector(23 DOWNTO 0); - SIGNAL SYS_CTR : std_logic_vector(6 DOWNTO 0); - SIGNAL SYS_CTR_d : std_logic_vector(6 DOWNTO 0); - SIGNAL SYS_CTR_q : std_logic_vector(6 DOWNTO 0); - SIGNAL LOF : std_logic_vector(15 DOWNTO 0); - SIGNAL LOF_d : std_logic_vector(15 DOWNTO 0); - SIGNAL LOF_q : std_logic_vector(15 DOWNTO 0); - SIGNAL LWD : std_logic_vector(15 DOWNTO 0); - SIGNAL LWD_d : std_logic_vector(15 DOWNTO 0); - SIGNAL LWD_q : std_logic_vector(15 DOWNTO 0); - SIGNAL HSYNC_I : std_logic_vector(7 DOWNTO 0); - SIGNAL HSYNC_I_d : std_logic_vector(7 DOWNTO 0); - SIGNAL HSYNC_I_q : std_logic_vector(7 DOWNTO 0); - SIGNAL HSY_LEN : std_logic_vector(7 DOWNTO 0); - SIGNAL HSY_LEN_d : std_logic_vector(7 DOWNTO 0); - SIGNAL HSY_LEN_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VSYNC_I : std_logic_vector(2 DOWNTO 0); - SIGNAL VSYNC_I_d : std_logic_vector(2 DOWNTO 0); - SIGNAL VSYNC_I_q : std_logic_vector(2 DOWNTO 0); - SIGNAL VHCNT : std_logic_vector(11 DOWNTO 0); - SIGNAL VHCNT_d : std_logic_vector(11 DOWNTO 0); - SIGNAL VHCNT_q : std_logic_vector(11 DOWNTO 0); - SIGNAL SUB_PIXEL_CNT : std_logic_vector(6 DOWNTO 0); - SIGNAL SUB_PIXEL_CNT_d : std_logic_vector(6 DOWNTO 0); - SIGNAL SUB_PIXEL_CNT_q : std_logic_vector(6 DOWNTO 0); - SIGNAL VVCNT : std_logic_vector(10 DOWNTO 0); - SIGNAL VVCNT_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VVCNT_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VERZ2 : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ2_d : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ2_q : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ1 : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ1_d : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ1_q : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ0 : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ0_d : std_logic_vector(9 DOWNTO 0); - SIGNAL VERZ0_q : std_logic_vector(9 DOWNTO 0); - SIGNAL RAND : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); - SIGNAL RAND_d : std_logic_vector(6 DOWNTO 0); - SIGNAL RAND_q : std_logic_vector(6 DOWNTO 0); - SIGNAL CCSEL_d : std_logic_vector(2 DOWNTO 0); - SIGNAL CCSEL_q : std_logic_vector(2 DOWNTO 0); - SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); - SIGNAL ATARI_HH_d : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HH_q : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VH : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VH_d : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VH_q : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); - SIGNAL ATARI_HL_d : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL_q : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VL : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VL_d : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_VL_q : std_logic_vector(31 DOWNTO 0); - SIGNAL RAND_LINKS : std_logic_vector(11 DOWNTO 0); - SIGNAL HDIS_START : std_logic_vector(11 DOWNTO 0); - SIGNAL HDIS_END : std_logic_vector(11 DOWNTO 0); - SIGNAL RAND_RECHTS : std_logic_vector(11 DOWNTO 0); - SIGNAL HS_START : std_logic_vector(11 DOWNTO 0); - SIGNAL H_TOTAL : std_logic_vector(11 DOWNTO 0); - SIGNAL HDIS_LEN : std_logic_vector(11 DOWNTO 0); - SIGNAL MULF : std_logic_vector(5 DOWNTO 0); - SIGNAL HHT : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); - SIGNAL HHT_d : std_logic_vector(11 DOWNTO 0); - SIGNAL HHT_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HBE : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); - SIGNAL HBE_d : std_logic_vector(11 DOWNTO 0); - SIGNAL HBE_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HDB : std_logic_vector(11 DOWNTO 0); - SIGNAL HDB_d : std_logic_vector(11 DOWNTO 0); - SIGNAL HDB_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HDE : std_logic_vector(11 DOWNTO 0); - SIGNAL HDE_d : std_logic_vector(11 DOWNTO 0); - SIGNAL HDE_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HBB : std_logic_vector(11 DOWNTO 0); - SIGNAL HBB_d : std_logic_vector(11 DOWNTO 0); - SIGNAL HBB_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HSS : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); - SIGNAL HSS_d : std_logic_vector(11 DOWNTO 0); - SIGNAL HSS_q : std_logic_vector(11 DOWNTO 0); - SIGNAL RAND_OBEN : std_logic_vector(10 DOWNTO 0); - SIGNAL VDIS_START : std_logic_vector(10 DOWNTO 0); - SIGNAL VDIS_END : std_logic_vector(10 DOWNTO 0); - SIGNAL RAND_UNTEN : std_logic_vector(10 DOWNTO 0); - SIGNAL VS_START : std_logic_vector(10 DOWNTO 0); - SIGNAL V_TOTAL : std_logic_vector(10 DOWNTO 0); - SIGNAL VBE : std_logic_vector(10 DOWNTO 0); - SIGNAL VBE_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VBE_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VDB : std_logic_vector(10 DOWNTO 0); - SIGNAL VDB_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VDB_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VDE : std_logic_vector(10 DOWNTO 0); - SIGNAL VDE_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VDE_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VBB : std_logic_vector(10 DOWNTO 0); - SIGNAL VBB_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VBB_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VSS : std_logic_vector(10 DOWNTO 0); - SIGNAL VSS_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VSS_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VFT : std_logic_vector(10 DOWNTO 0); - SIGNAL VFT_d : std_logic_vector(10 DOWNTO 0); - SIGNAL VFT_q : std_logic_vector(10 DOWNTO 0); - SIGNAL VCO : std_logic_vector(8 DOWNTO 0); - SIGNAL VCO_d : std_logic_vector(8 DOWNTO 0); - SIGNAL VCO_ena : std_logic_vector(8 DOWNTO 0); - SIGNAL VCO_q : std_logic_vector(8 DOWNTO 0); - SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); - SIGNAL VCNTRL_d : std_logic_vector(3 DOWNTO 0); - SIGNAL VCNTRL_q : std_logic_vector(3 DOWNTO 0); - SIGNAL u0_data : std_logic_vector(15 DOWNTO 0); - SIGNAL u0_tridata : std_logic_vector(15 DOWNTO 0); - SIGNAL u1_data : std_logic_vector(15 DOWNTO 0); - SIGNAL u1_tridata : std_logic_vector(15 DOWNTO 0); + SIGNAL VR_DOUT : std_logic_vector(8 downto 0); + SIGNAL VR_DOUT_d : std_logic_vector(8 downto 0); + SIGNAL VR_DOUT_q : std_logic_vector(8 downto 0); + SIGNAL VR_FRQ : unsigned(7 downto 0); + SIGNAL VR_FRQ_d : std_logic_vector(7 downto 0); + SIGNAL VR_FRQ_q : std_logic_vector(7 downto 0); + SIGNAL FB_B : std_logic_vector(3 downto 0); + SIGNAL FB_16B : std_logic_vector(1 downto 0); + SIGNAL ST_SHIFT_MODE : std_logic_vector(1 downto 0); + SIGNAL ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); + SIGNAL ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); + SIGNAL FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); + SIGNAL FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); + SIGNAL FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); + SIGNAL CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_AV1 : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_AV0 : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); + SIGNAL CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); + SIGNAL ACP_VCTR : std_logic_vector(31 downto 0); + SIGNAL ACP_VCTR_d : std_logic_vector(31 downto 0); + SIGNAL ACP_VCTR_q : std_logic_vector(31 downto 0); + SIGNAL BORDER_COLOR_d : std_logic_vector(23 downto 0); + SIGNAL BORDER_COLOR_q : std_logic_vector(23 downto 0); + SIGNAL SYS_CTR : std_logic_vector(6 downto 0); + SIGNAL SYS_CTR_d : std_logic_vector(6 downto 0); + SIGNAL SYS_CTR_q : std_logic_vector(6 downto 0); + SIGNAL LOF : std_logic_vector(15 downto 0); + SIGNAL LOF_d : std_logic_vector(15 downto 0); + SIGNAL LOF_q : std_logic_vector(15 downto 0); + SIGNAL LWD : std_logic_vector(15 downto 0); + SIGNAL LWD_d : std_logic_vector(15 downto 0); + SIGNAL LWD_q : std_logic_vector(15 downto 0); + SIGNAL HSYNC_I : std_logic_vector(7 downto 0); + SIGNAL HSYNC_I_d : std_logic_vector(7 downto 0); + SIGNAL HSYNC_I_q : std_logic_vector(7 downto 0); + SIGNAL HSY_LEN : std_logic_vector(7 downto 0); + SIGNAL HSY_LEN_d : std_logic_vector(7 downto 0); + SIGNAL HSY_LEN_q : std_logic_vector(7 downto 0); + SIGNAL VSYNC_I : std_logic_vector(2 downto 0); + SIGNAL VSYNC_I_d : std_logic_vector(2 downto 0); + SIGNAL VSYNC_I_q : std_logic_vector(2 downto 0); + SIGNAL VHCNT : std_logic_vector(11 downto 0); + SIGNAL VHCNT_d : std_logic_vector(11 downto 0); + SIGNAL VHCNT_q : std_logic_vector(11 downto 0); + SIGNAL SUB_PIXEL_CNT : std_logic_vector(6 downto 0); + SIGNAL SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); + SIGNAL SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); + SIGNAL VVCNT : std_logic_vector(10 downto 0); + SIGNAL VVCNT_d : std_logic_vector(10 downto 0); + SIGNAL VVCNT_q : std_logic_vector(10 downto 0); + SIGNAL VERZ2 : std_logic_vector(9 downto 0); + SIGNAL VERZ2_d : std_logic_vector(9 downto 0); + SIGNAL VERZ2_q : std_logic_vector(9 downto 0); + SIGNAL VERZ1 : std_logic_vector(9 downto 0); + SIGNAL VERZ1_d : std_logic_vector(9 downto 0); + SIGNAL VERZ1_q : std_logic_vector(9 downto 0); + SIGNAL VERZ0 : std_logic_vector(9 downto 0); + SIGNAL VERZ0_d : std_logic_vector(9 downto 0); + SIGNAL VERZ0_q : std_logic_vector(9 downto 0); + SIGNAL RAND : std_logic_vector(6 downto 0) := (OTHERS => '0'); + SIGNAL RAND_d : std_logic_vector(6 downto 0); + SIGNAL RAND_q : std_logic_vector(6 downto 0); + SIGNAL CCSEL_d : std_logic_vector(2 downto 0); + SIGNAL CCSEL_q : std_logic_vector(2 downto 0); + SIGNAL ATARI_HH : std_logic_vector(31 downto 0) := (OTHERS => '0'); + SIGNAL ATARI_HH_d : std_logic_vector(31 downto 0); + SIGNAL ATARI_HH_q : std_logic_vector(31 downto 0); + SIGNAL ATARI_VH : std_logic_vector(31 downto 0); + SIGNAL ATARI_VH_d : std_logic_vector(31 downto 0); + SIGNAL ATARI_VH_q : std_logic_vector(31 downto 0); + SIGNAL ATARI_HL : std_logic_vector(31 downto 0) := (OTHERS => '0'); + SIGNAL ATARI_HL_d : std_logic_vector(31 downto 0); + SIGNAL ATARI_HL_q : std_logic_vector(31 downto 0); + SIGNAL ATARI_VL : std_logic_vector(31 downto 0); + SIGNAL ATARI_VL_d : std_logic_vector(31 downto 0); + SIGNAL ATARI_VL_q : std_logic_vector(31 downto 0); + SIGNAL RAND_LINKS : std_logic_vector(11 downto 0); + SIGNAL HDIS_START : std_logic_vector(11 downto 0); + SIGNAL HDIS_END : std_logic_vector(11 downto 0); + SIGNAL RAND_RECHTS : std_logic_vector(11 downto 0); + SIGNAL HS_START : std_logic_vector(11 downto 0); + SIGNAL H_TOTAL : std_logic_vector(11 downto 0); + SIGNAL HDIS_LEN : std_logic_vector(11 downto 0); + SIGNAL MULF : std_logic_vector(5 downto 0); + SIGNAL HHT : std_logic_vector(11 downto 0) := (OTHERS => '0'); + SIGNAL HHT_d : std_logic_vector(11 downto 0); + SIGNAL HHT_q : std_logic_vector(11 downto 0); + SIGNAL HBE : std_logic_vector(11 downto 0) := (OTHERS => '0'); + SIGNAL HBE_d : std_logic_vector(11 downto 0); + SIGNAL HBE_q : std_logic_vector(11 downto 0); + SIGNAL HDB : std_logic_vector(11 downto 0); + SIGNAL HDB_d : std_logic_vector(11 downto 0); + SIGNAL HDB_q : std_logic_vector(11 downto 0); + SIGNAL HDE : std_logic_vector(11 downto 0); + SIGNAL HDE_d : std_logic_vector(11 downto 0); + SIGNAL HDE_q : std_logic_vector(11 downto 0); + SIGNAL HBB : std_logic_vector(11 downto 0); + SIGNAL HBB_d : std_logic_vector(11 downto 0); + SIGNAL HBB_q : std_logic_vector(11 downto 0); + SIGNAL HSS : std_logic_vector(11 downto 0) := (OTHERS => '0'); + SIGNAL HSS_d : std_logic_vector(11 downto 0); + SIGNAL HSS_q : std_logic_vector(11 downto 0); + SIGNAL RAND_OBEN : std_logic_vector(10 downto 0); + SIGNAL VDIS_START : std_logic_vector(10 downto 0); + SIGNAL VDIS_END : std_logic_vector(10 downto 0); + SIGNAL RAND_UNTEN : std_logic_vector(10 downto 0); + SIGNAL VS_START : std_logic_vector(10 downto 0); + SIGNAL V_TOTAL : std_logic_vector(10 downto 0); + SIGNAL VBE : std_logic_vector(10 downto 0); + SIGNAL VBE_d : std_logic_vector(10 downto 0); + SIGNAL VBE_q : std_logic_vector(10 downto 0); + SIGNAL VDB : std_logic_vector(10 downto 0); + SIGNAL VDB_d : std_logic_vector(10 downto 0); + SIGNAL VDB_q : std_logic_vector(10 downto 0); + SIGNAL VDE : std_logic_vector(10 downto 0); + SIGNAL VDE_d : std_logic_vector(10 downto 0); + SIGNAL VDE_q : std_logic_vector(10 downto 0); + SIGNAL VBB : std_logic_vector(10 downto 0); + SIGNAL VBB_d : std_logic_vector(10 downto 0); + SIGNAL VBB_q : std_logic_vector(10 downto 0); + SIGNAL VSS : std_logic_vector(10 downto 0); + SIGNAL VSS_d : std_logic_vector(10 downto 0); + SIGNAL VSS_q : std_logic_vector(10 downto 0); + SIGNAL VFT : std_logic_vector(10 downto 0); + SIGNAL VFT_d : std_logic_vector(10 downto 0); + SIGNAL VFT_q : std_logic_vector(10 downto 0); + SIGNAL VCO : std_logic_vector(8 downto 0); + SIGNAL VCO_d : std_logic_vector(8 downto 0); + SIGNAL VCO_ena : std_logic_vector(8 downto 0); + SIGNAL VCO_q : std_logic_vector(8 downto 0); + SIGNAL VCNTRL : std_logic_vector(3 downto 0) := (OTHERS => '0'); + SIGNAL VCNTRL_d : std_logic_vector(3 downto 0); + SIGNAL VCNTRL_q : std_logic_vector(3 downto 0); + SIGNAL u0_data : std_logic_vector(15 downto 0); + SIGNAL u0_tridata : std_logic_vector(15 downto 0); + SIGNAL u1_data : std_logic_vector(15 downto 0); + SIGNAL u1_tridata : std_logic_vector(15 downto 0); -- SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic; SIGNAL ST_SHIFT_MODE0_ena_ctrl : std_logic; -- SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; @@ -468,7 +468,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL CLK17M : std_logic; SIGNAL color4_i : std_logic; SIGNAL pixel_clk_i : std_logic; - SIGNAL calc_freq : unsigned(7 DOWNTO 0); + signal fbee_pxl_half : unsigned(7 downto 0); -- Sub Module Interface Section @@ -476,9 +476,9 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS COMPONENT lpm_bustri_WORD PORT ( - data : IN std_logic_vector(15 DOWNTO 0); + data : IN std_logic_vector(15 downto 0); enabledt : IN std_logic; - tridata : BUFFER std_logic_vector(15 DOWNTO 0) + tridata : BUFFER std_logic_vector(15 downto 0) ); END COMPONENT lpm_bustri_WORD; @@ -487,7 +487,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS BEGIN IF x THEN ret := '1'; - ELSE + else ret := '0'; END IF; RETURN ret; @@ -496,7 +496,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS -- sizeIt replicates a value to an array of specific length. FUNCTION sizeit(a : std_Logic; len : integer) RETURN std_logic_vector IS - VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0); + VARIABLE rep: std_logic_vector(len - 1 downto 0); BEGIN FOR i IN rep'RANGE LOOP rep(i) := a; @@ -566,21 +566,21 @@ BEGIN END IF; END PROCESS; - BORDER_COLOR(23 DOWNTO 16) <= BORDER_COLOR_q(23 DOWNTO 16); - BORDER_COLOR(15 DOWNTO 8) <= BORDER_COLOR_q(15 DOWNTO 8); - BORDER_COLOR(7 DOWNTO 0) <= BORDER_COLOR_q(7 DOWNTO 0); + BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); + BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); + BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); PROCESS (main_clk) BEGIN IF rising_edge(main_clk) THEN IF BORDER_COLOR16_ena_ctrl = '1' THEN - border_color_q(23 DOWNTO 16) <= border_color_d(23 DOWNTO 16); + border_color_q(23 downto 16) <= border_color_d(23 downto 16); END IF; IF BORDER_COLOR8_ena_ctrl = '1' THEN - border_color_q(15 DOWNTO 8) <= border_color_d(15 DOWNTO 8); + border_color_q(15 downto 8) <= border_color_d(15 downto 8); END IF; IF BORDER_COLOR0_ena_ctrl = '1' THEN - border_color_q(7 DOWNTO 0) <= border_color_d(7 DOWNTO 0); + border_color_q(7 downto 0) <= border_color_d(7 downto 0); END IF; END IF; END PROCESS; @@ -680,10 +680,10 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN - falcon_shift_mode_q(10 DOWNTO 8) <= falcon_shift_mode_d(10 DOWNTO 8); + falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); END IF; IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN - falcon_shift_mode_q(7 DOWNTO 0) <= falcon_shift_mode_d(7 DOWNTO 0); + falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); END IF; END IF; END PROCESS; @@ -706,19 +706,19 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF ACP_VCTR24_ena_ctrl = '1' THEN - ACP_VCTR_q(31 DOWNTO 24) <= ACP_VCTR_d(31 DOWNTO 24); + ACP_VCTR_q(31 downto 24) <= ACP_VCTR_d(31 downto 24); END IF; IF ACP_VCTR16_ena_ctrl = '1' THEN - ACP_VCTR_q(23 DOWNTO 16) <= ACP_VCTR_d(23 DOWNTO 16); + ACP_VCTR_q(23 downto 16) <= ACP_VCTR_d(23 downto 16); END IF; IF ACP_VCTR8_ena_ctrl = '1' THEN - ACP_VCTR_q(15 DOWNTO 8) <= ACP_VCTR_d(15 DOWNTO 8); + ACP_VCTR_q(15 downto 8) <= ACP_VCTR_d(15 downto 8); END IF; IF ACP_VCTR6_ena_ctrl = '1' THEN - ACP_VCTR_q(7 DOWNTO 6) <= ACP_VCTR_d(7 DOWNTO 6); + ACP_VCTR_q(7 downto 6) <= ACP_VCTR_d(7 downto 6); END IF; IF ACP_VCTR0_ena_ctrl = '1' THEN - ACP_VCTR_q(5 DOWNTO 0) <= ACP_VCTR_d(5 DOWNTO 0); + ACP_VCTR_q(5 downto 0) <= ACP_VCTR_d(5 downto 0); END IF; IF SYS_CTR0_ena_ctrl='1' THEN @@ -726,19 +726,19 @@ BEGIN END IF; IF LOF8_ena_ctrl = '1' THEN - LOF_q(15 DOWNTO 8) <= LOF_d(15 DOWNTO 8); + LOF_q(15 downto 8) <= LOF_d(15 downto 8); END IF; IF LOF0_ena_ctrl = '1' THEN - LOF_q(7 DOWNTO 0) <= LOF_d(7 DOWNTO 0); + LOF_q(7 downto 0) <= LOF_d(7 downto 0); END IF; IF LWD8_ena_ctrl = '1' THEN - LWD_q(15 DOWNTO 8) <= LWD_d(15 DOWNTO 8); + LWD_q(15 downto 8) <= LWD_d(15 downto 8); END IF; IF LWD0_ena_ctrl = '1' THEN - LWD_q(7 DOWNTO 0) <= LWD_d(7 DOWNTO 0); + LWD_q(7 downto 0) <= LWD_d(7 downto 0); END IF; END IF; END PROCESS; @@ -819,83 +819,83 @@ BEGIN SYNC_PIX2_q <= SYNC_PIX2_d; IF ATARI_HH24_ena_ctrl = '1' THEN - ATARI_HH_q(31 DOWNTO 24) <= ATARI_HH_d(31 DOWNTO 24); + ATARI_HH_q(31 downto 24) <= ATARI_HH_d(31 downto 24); END IF; IF ATARI_HH16_ena_ctrl = '1' THEN - ATARI_HH_q(23 DOWNTO 16) <= ATARI_HH_d(23 DOWNTO 16); + ATARI_HH_q(23 downto 16) <= ATARI_HH_d(23 downto 16); END IF; IF ATARI_HH8_ena_ctrl = '1' THEN - ATARI_HH_q(15 DOWNTO 8) <= ATARI_HH_d(15 DOWNTO 8); + ATARI_HH_q(15 downto 8) <= ATARI_HH_d(15 downto 8); END IF; IF ATARI_HH0_ena_ctrl = '1' THEN - ATARI_HH_q(7 DOWNTO 0) <= ATARI_HH_d(7 DOWNTO 0); + ATARI_HH_q(7 downto 0) <= ATARI_HH_d(7 downto 0); END IF; IF ATARI_VH24_ena_ctrl = '1' THEN - ATARI_VH_q(31 DOWNTO 24) <= ATARI_VH_d(31 DOWNTO 24); + ATARI_VH_q(31 downto 24) <= ATARI_VH_d(31 downto 24); END IF; IF ATARI_VH16_ena_ctrl = '1' THEN - ATARI_VH_q(23 DOWNTO 16) <= ATARI_VH_d(23 DOWNTO 16); + ATARI_VH_q(23 downto 16) <= ATARI_VH_d(23 downto 16); END IF; IF ATARI_VH8_ena_ctrl = '1' THEN - ATARI_VH_q(15 DOWNTO 8) <= ATARI_VH_d(15 DOWNTO 8); + ATARI_VH_q(15 downto 8) <= ATARI_VH_d(15 downto 8); END IF; IF ATARI_VH0_ena_ctrl='1' THEN - ATARI_VH_q(7 DOWNTO 0) <= ATARI_VH_d(7 DOWNTO 0); + ATARI_VH_q(7 downto 0) <= ATARI_VH_d(7 downto 0); END IF; IF ATARI_HL24_ena_ctrl = '1' THEN - ATARI_HL_q(31 DOWNTO 24) <= ATARI_HL_d(31 DOWNTO 24); + ATARI_HL_q(31 downto 24) <= ATARI_HL_d(31 downto 24); END IF; IF ATARI_HL16_ena_ctrl = '1' THEN - ATARI_HL_q(23 DOWNTO 16) <= ATARI_HL_d(23 DOWNTO 16); + ATARI_HL_q(23 downto 16) <= ATARI_HL_d(23 downto 16); END IF; IF ATARI_HL8_ena_ctrl = '1' THEN - ATARI_HL_q(15 DOWNTO 8) <= ATARI_HL_d(15 DOWNTO 8); + ATARI_HL_q(15 downto 8) <= ATARI_HL_d(15 downto 8); END IF; IF ATARI_HL0_ena_ctrl = '1' THEN - ATARI_HL_q(7 DOWNTO 0) <= ATARI_HL_d(7 DOWNTO 0); + ATARI_HL_q(7 downto 0) <= ATARI_HL_d(7 downto 0); END IF; IF ATARI_VL24_ena_ctrl = '1' THEN - ATARI_VL_q(31 DOWNTO 24) <= ATARI_VL_d(31 DOWNTO 24); + ATARI_VL_q(31 downto 24) <= ATARI_VL_d(31 downto 24); END IF; IF ATARI_VL16_ena_ctrl = '1' THEN - ATARI_VL_q(23 DOWNTO 16) <= ATARI_VL_d(23 DOWNTO 16); + ATARI_VL_q(23 downto 16) <= ATARI_VL_d(23 downto 16); END IF; IF ATARI_VL8_ena_ctrl = '1' THEN - ATARI_VL_q(15 DOWNTO 8) <= ATARI_VL_d(15 DOWNTO 8); + ATARI_VL_q(15 downto 8) <= ATARI_VL_d(15 downto 8); END IF; IF ATARI_VL0_ena_ctrl = '1' THEN - ATARI_VL_q(7 DOWNTO 0) <= ATARI_VL_d(7 DOWNTO 0); + ATARI_VL_q(7 downto 0) <= ATARI_VL_d(7 downto 0); END IF; IF HHT8_ena_ctrl = '1' THEN - HHT_q(11 DOWNTO 8) <= HHT_d(11 DOWNTO 8); + HHT_q(11 downto 8) <= HHT_d(11 downto 8); END IF; IF HHT0_ena_ctrl = '1' THEN - HHT_q(7 DOWNTO 0) <= HHT_d(7 DOWNTO 0); + HHT_q(7 downto 0) <= HHT_d(7 downto 0); END IF; IF HBE8_ena_ctrl = '1' THEN - HBE_q(11 DOWNTO 8) <= HBE_d(11 DOWNTO 8); + HBE_q(11 downto 8) <= HBE_d(11 downto 8); END IF; IF HBE0_ena_ctrl = '1' THEN - HBE_q(7 DOWNTO 0) <= HBE_d(7 DOWNTO 0); + HBE_q(7 downto 0) <= HBE_d(7 downto 0); END IF; END IF; END PROCESS; @@ -904,10 +904,10 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HDB8_ena_ctrl = '1' THEN - HDB_q(11 DOWNTO 8) <= HDB_d(11 DOWNTO 8); + HDB_q(11 downto 8) <= HDB_d(11 downto 8); END IF; IF HDB0_ena_ctrl = '1' THEN - HDB_q(7 DOWNTO 0) <= HDB_d(7 DOWNTO 0); + HDB_q(7 downto 0) <= HDB_d(7 downto 0); END IF; END IF; END PROCESS; @@ -916,7 +916,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HDE8_ena_ctrl = '1' THEN - HDE_q(11 DOWNTO 8) <= HDE_d(11 DOWNTO 8); + HDE_q(11 downto 8) <= HDE_d(11 downto 8); END IF; END IF; END PROCESS; @@ -925,7 +925,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HDE0_ena_ctrl = '1' THEN - HDE_q(7 DOWNTO 0) <= HDE_d(7 DOWNTO 0); + HDE_q(7 downto 0) <= HDE_d(7 downto 0); END IF; END IF; END PROCESS; @@ -934,7 +934,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HBB8_ena_ctrl = '1' THEN - HBB_q(11 DOWNTO 8) <= HBB_d(11 DOWNTO 8); + HBB_q(11 downto 8) <= HBB_d(11 downto 8); END IF; END IF; END PROCESS; @@ -943,7 +943,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HBB0_ena_ctrl = '1' THEN - HBB_q(7 DOWNTO 0) <= HBB_d(7 DOWNTO 0); + HBB_q(7 downto 0) <= HBB_d(7 downto 0); END IF; END IF; END PROCESS; @@ -952,7 +952,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HSS8_ena_ctrl = '1' THEN - HSS_q(11 DOWNTO 8) <= HSS_d(11 DOWNTO 8); + HSS_q(11 downto 8) <= HSS_d(11 downto 8); END IF; END IF; END PROCESS; @@ -961,7 +961,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF HSS0_ena_ctrl='1' THEN - HSS_q(7 DOWNTO 0) <= HSS_d(7 DOWNTO 0); + HSS_q(7 downto 0) <= HSS_d(7 downto 0); END IF; END IF; END PROCESS; @@ -977,7 +977,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VBE8_ena_ctrl = '1' THEN - VBE_q(10 DOWNTO 8) <= VBE_d(10 DOWNTO 8); + VBE_q(10 downto 8) <= VBE_d(10 downto 8); END IF; END IF; END PROCESS; @@ -986,7 +986,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VBE0_ena_ctrl = '1' THEN - VBE_q(7 DOWNTO 0) <= VBE_d(7 DOWNTO 0); + VBE_q(7 downto 0) <= VBE_d(7 downto 0); END IF; END IF; END PROCESS; @@ -995,7 +995,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VDB8_ena_ctrl = '1' THEN - VDB_q(10 DOWNTO 8) <= VDB_d(10 DOWNTO 8); + VDB_q(10 downto 8) <= VDB_d(10 downto 8); END IF; END IF; END PROCESS; @@ -1004,7 +1004,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VDB0_ena_ctrl = '1' THEN - VDB_q(7 DOWNTO 0) <= VDB_d(7 DOWNTO 0); + VDB_q(7 downto 0) <= VDB_d(7 downto 0); END IF; END IF; END PROCESS; @@ -1013,7 +1013,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VDE8_ena_ctrl = '1' THEN - VDE_q(10 DOWNTO 8) <= VDE_d(10 DOWNTO 8); + VDE_q(10 downto 8) <= VDE_d(10 downto 8); END IF; END IF; END PROCESS; @@ -1022,7 +1022,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VDE0_ena_ctrl = '1' THEN - VDE_q(7 DOWNTO 0) <= VDE_d(7 DOWNTO 0); + VDE_q(7 downto 0) <= VDE_d(7 downto 0); END IF; END IF; END PROCESS; @@ -1031,7 +1031,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VBB8_ena_ctrl = '1' THEN - VBB_q(10 DOWNTO 8) <= VBB_d(10 DOWNTO 8); + VBB_q(10 downto 8) <= VBB_d(10 downto 8); END IF; END IF; END PROCESS; @@ -1040,7 +1040,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VBB0_ena_ctrl = '1' THEN - VBB_q(7 DOWNTO 0) <= VBB_d(7 DOWNTO 0); + VBB_q(7 downto 0) <= VBB_d(7 downto 0); END IF; END IF; END PROCESS; @@ -1049,7 +1049,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VSS8_ena_ctrl = '1' THEN - VSS_q(10 DOWNTO 8) <= VSS_d(10 DOWNTO 8); + VSS_q(10 downto 8) <= VSS_d(10 downto 8); END IF; END IF; END PROCESS; @@ -1058,7 +1058,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VSS0_ena_ctrl = '1' THEN - VSS_q(7 DOWNTO 0) <= VSS_d(7 DOWNTO 0); + VSS_q(7 downto 0) <= VSS_d(7 downto 0); END IF; END IF; END PROCESS; @@ -1067,7 +1067,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VFT8_ena_ctrl = '1' THEN - VFT_q(10 DOWNTO 8) <= VFT_d(10 DOWNTO 8); + VFT_q(10 downto 8) <= VFT_d(10 downto 8); END IF; END IF; END PROCESS; @@ -1076,7 +1076,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VFT0_ena_ctrl = '1' THEN - VFT_q(7 DOWNTO 0) <= VFT_d(7 DOWNTO 0); + VFT_q(7 downto 0) <= VFT_d(7 downto 0); END IF; END IF; END PROCESS; @@ -1094,7 +1094,7 @@ BEGIN BEGIN IF rising_edge(main_clk) THEN IF VCO0_ena_ctrl = '1' THEN - VCO_q(7 DOWNTO 0) <= VCO_d(7 DOWNTO 0); + VCO_q(7 downto 0) <= VCO_d(7 downto 0); END IF; END IF; END PROCESS; @@ -1112,23 +1112,23 @@ BEGIN -- BYT SELECT 32 BIT -- ADR==0 - FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00"); + FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00"); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not + FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or + FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); @@ -1142,36 +1142,36 @@ BEGIN -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 10) = "000000000000000000"); + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 10) = "000000000000000000"); ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not VIDEO_MOD_TA); -- FALCON CLUT -- -- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 10) = "1111100110"); + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 10) = "1111100110"); -- HIGH WORD FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); -- LOW WORD FALCON_CLUT_RDL <= FALCON_CLUT_CS and (not nFB_OE) and FB_ADR(1); - FALCON_CLUT_WR(1 DOWNTO 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & + FALCON_CLUT_WR(1 downto 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & (not FB_ADR(1))) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - FALCON_CLUT_WR(3 DOWNTO 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and + FALCON_CLUT_WR(3 downto 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); -- ST CLUT -- -- $F8240/$20 - ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 5) = "111110000010010"); + ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 5) = "111110000010010"); ST_CLUT_RD <= ST_CLUT_CS and (not nFB_OE); ST_CLUT_WR <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); -- ST SHIFT MODE -- $F8260/2 - ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100110000"); - ST_SHIFT_MODE_d <= FB_AD(25 DOWNTO 24); + ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); + ST_SHIFT_MODE_d <= FB_AD(25 downto 24); ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); -- MONO @@ -1186,12 +1186,12 @@ BEGIN -- FALCON SHIFT MODE -- $F8266/2 - FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100110011"); - FALCON_SHIFT_MODE_d <= FB_AD(26 DOWNTO 16); + FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); + FALCON_SHIFT_MODE_d <= FB_AD(26 downto 16); FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(2); FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); - CLUT_OFF <= FALCON_SHIFT_MODE_q(3 DOWNTO 0) and sizeIt(COLOR4_i, 4); + CLUT_OFF <= FALCON_SHIFT_MODE_q(3 downto 0) and sizeIt(COLOR4_i, 4); COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); @@ -1213,10 +1213,10 @@ BEGIN -- BIT 26 = STANDARD ATARI SYNCS -- $400/4 - ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000000"); + ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); - ACP_VCTR_d(31 DOWNTO 8) <= FB_AD(31 DOWNTO 8); - ACP_VCTR_d(5 DOWNTO 0) <= FB_AD(5 DOWNTO 0); + ACP_VCTR_d(31 downto 8) <= FB_AD(31 downto 8); + ACP_VCTR_d(5 downto 0) <= FB_AD(5 downto 0); ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); @@ -1232,7 +1232,7 @@ BEGIN -- HORIZONTAL TIMING 640x480 -- $410/4 - ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000100"); + ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000100"); ATARI_HH_d <= FB_AD; ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); @@ -1242,7 +1242,7 @@ BEGIN -- VERTIKAL TIMING 640x480 -- $414/4 - ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000101"); + ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000101"); ATARI_VH_d <= FB_AD; ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); @@ -1252,7 +1252,7 @@ BEGIN -- HORIZONTAL TIMING 320x240 -- $418/4 - ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000110"); + ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000110"); ATARI_HL_d <= FB_AD; ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); @@ -1262,7 +1262,7 @@ BEGIN -- VERTIKAL TIMING 320x240 -- $41C/4 - ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000111"); + ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000111"); ATARI_VL_d <= FB_AD; ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); @@ -1271,21 +1271,21 @@ BEGIN -- VIDEO PLL CONFIG -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 9) = "0000000000000000011") and FB_B(0) and FB_B(1); + VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q); VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); VR_DOUT0_ena_ctrl <= not VR_BUSY; VR_DOUT_d <= VR_D; - VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 DOWNTO 0) = "000000100"); - VR_FRQ_d <= FB_AD(23 DOWNTO 16); + VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); + VR_FRQ_d <= FB_AD(23 downto 16); -- VIDEO PLL RECONFIG -- $(F)000'0800 - VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 0) = "0000000000000000100000000000") and FB_B(0); + VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 0) = "0000000000000000100000000000") and FB_B(0); VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); -- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR <= ACP_VCTR_q(31 DOWNTO 16); + VIDEO_RAM_CTR <= ACP_VCTR_q(31 downto 16); -- ------------ COLOR MODE IM ACP SETZEN COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; @@ -1315,8 +1315,8 @@ BEGIN -- RANDFARBE -- $404/4 - BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001"); - BORDER_COLOR_d <= FB_AD(23 DOWNTO 0); + BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); + BORDER_COLOR_d <= FB_AD(23 downto 0); BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); @@ -1344,129 +1344,129 @@ BEGIN -- 10 VGA -- 11 TV -- $8006/2 - SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000000000011"); - SYS_CTR_d <= FB_AD(22 DOWNTO 16); + SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000000000011"); + SYS_CTR_d <= FB_AD(22 downto 16); SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); BLITTER_ON <= not SYS_CTR_q(3); -- LOF -- $820E/2 - LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000111"); - LOF_d <= FB_AD(31 DOWNTO 16); + LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); + LOF_d <= FB_AD(31 downto 16); LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); -- LWD -- $8210/2 - LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100001000"); - LWD_d <= FB_AD(31 DOWNTO 16); + LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); + LWD_d <= FB_AD(31 downto 16); LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); -- HORIZONTAL -- HHT -- $8282/2 - HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000001"); - HHT_d <= FB_AD(27 DOWNTO 16); + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000001"); + HHT_d <= FB_AD(27 downto 16); HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); -- HBE -- $8286/2 - HBE_CS <= '1' WHEN nFB_CS1 ='0' and FB_ADR(19 DOWNTO 1) = "1111100000101000011" ELSE '0'; - HBE_d <= FB_AD(27 DOWNTO 16); + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000011"); + HBE_d <= FB_AD(27 downto 16); HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); -- HDB -- $8288/2 - HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000100"); - HDB_d <= FB_AD(27 DOWNTO 16); + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000100"); + HDB_d <= FB_AD(27 downto 16); HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); -- HDE -- $828A/2 - HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000101"); - HDE_d <= FB_AD(27 DOWNTO 16); + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000101"); + HDE_d <= FB_AD(27 downto 16); HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); -- HBB -- $8284/2 - HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000010"); - HBB_d <= FB_AD(27 DOWNTO 16); + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000010"); + HBB_d <= FB_AD(27 downto 16); HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); -- HSS -- Videl HSYNC start register $828C / 2 - HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101000110"); - HSS_d <= FB_AD(27 DOWNTO 16); + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000110"); + HSS_d <= FB_AD(27 downto 16); HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); -- VERTIKAL -- VBE -- $82A6/2 - VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010011"); - VBE_d <= FB_AD(26 DOWNTO 16); + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010011"); + VBE_d <= FB_AD(26 downto 16); VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); -- VDB -- $82A8/2 - VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010100"); - VDB_d <= FB_AD(26 DOWNTO 16); + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010100"); + VDB_d <= FB_AD(26 downto 16); VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); -- VDE -- $82AA/2 - VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010101"); - VDE_d <= FB_AD(26 DOWNTO 16); + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010101"); + VDE_d <= FB_AD(26 downto 16); VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); -- VBB -- $82A4/2 - VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010010"); - VBB_d <= FB_AD(26 DOWNTO 16); + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010010"); + VBB_d <= FB_AD(26 downto 16); VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); -- VSS -- $82AC/2 - VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010110"); - VSS_d <= FB_AD(26 DOWNTO 16); + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010110"); + VSS_d <= FB_AD(26 downto 16); VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); -- VFT -- $82A2/2 - VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101010001"); - VFT_d <= FB_AD(26 DOWNTO 16); + VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); + VFT_d <= FB_AD(26 downto 16); VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); -- VCO -- $82C0 / 2 Falcon clock control register VCO - VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100000"); - VCO_d <= FB_AD(24 DOWNTO 16); + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101100000"); + VCO_d <= FB_AD(24 downto 16); VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL - VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000101100001"); - VCNTRL_d <= FB_AD(19 DOWNTO 16); + VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101100001"); + VCNTRL_d <= FB_AD(19 downto 16); VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); -- - REGISTER OUT -- low word register access u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or - (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 DOWNTO 4) & (not BLITTER_RUN) & SYS_CTR_q(2 DOWNTO 0))) or + (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or @@ -1482,29 +1482,29 @@ BEGIN (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or - (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 DOWNTO 16)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 DOWNTO 16)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 DOWNTO 16)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 DOWNTO 16)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 DOWNTO 16)) or - (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 DOWNTO 16))) or + (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or + (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); - FB_AD(31 DOWNTO 16) <= u0_tridata; + FB_AD(31 downto 16) <= u0_tridata; -- high word register access - u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 DOWNTO 0)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 DOWNTO 0)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 DOWNTO 0)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 DOWNTO 0)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 DOWNTO 0)) or - (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 DOWNTO 0)); + u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or + (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or + (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or + (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or + (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or + (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); - FB_AD(15 DOWNTO 0) <= u1_tridata; + FB_AD(15 downto 0) <= u1_tridata; VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or @@ -1522,8 +1522,8 @@ BEGIN (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or - (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "00")) or - (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 DOWNTO 8) = "01")) or + (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "00")) or + (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "01")) or (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); -- ------------------------------------------------------------ @@ -1535,22 +1535,24 @@ BEGIN -- 640 pixels, 32 MHz, RGB -- 640 pixels, 25.175 MHz, VGA -- hsync pulse length in pixeln = frequenz / = 500ns - calc_freq <= 8d"16" + unsigned("0" & vr_frq(7 DOWNTO 1)); - HSY_LEN_d <= std_logic_vector'(d"14") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') ELSE - std_logic_vector'(d"16") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') ELSE - std_logic_vector'(d"28") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' ELSE - std_logic_vector'(d"32") WHEN acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' ELSE - std_logic_vector'(d"28") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "00" ELSE - std_logic_vector'(d"32") WHEN acp_video_on = '1' and acp_vctr(9 DOWNTO 8) = "01" ELSE - std_logic_vector(calc_freq) WHEN acp_video_on = '1' and acp_vctr(9) = '1' ; + + fbee_pxl_half <= d"16" + ("0" & vr_frq(7 downto 1)); + HSY_LEN_d <= std_logic_vector'(d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else + std_logic_vector'(d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else + std_logic_vector'(d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else + std_logic_vector'(d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else + std_logic_vector'(d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else + std_logic_vector'(d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else + std_logic_vector(fbee_pxl_half) when acp_video_on = '1' and acp_vctr(9) = '1'; + -- std_logic_vector'(vr_frq(7 downto 1) + unsigned'(8d"16")) when acp_video_on = '1' and acp_vctr(9) = '1' ; -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "00"), 8)) or - -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 DOWNTO 8) = "01"), 8)) or - -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 DOWNTO 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(ACP_VCTR_q(9), 8)); + -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "00"), 8)) or + -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "01"), 8)) or + -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(ACP_VCTR_q(9), 8)); -- MULTIPLIKATIONS FAKTOR MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or @@ -1580,15 +1582,15 @@ BEGIN -- # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - rand_links <= HBE_q WHEN acp_video_on ELSE - 12d"12" WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE - 12d"42" WHEN not acp_video_on and atari_sync and not(vcntrl(2)) ELSE - std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; + rand_links <= HBE_q when acp_video_on else + 12d"12" when not acp_video_on and atari_sync and vcntrl(2) else + 12d"42" when not acp_video_on and atari_sync and not(vcntrl(2)) else + std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync; /* rand_links <= (HBE_q and sizeit(acp_video_on, 12)) or (std_logic_vector(to_unsigned(21, 12)) and sizeit(not acp_video_on and atari_sync and vcntrl(2), 12)) or (std_logic_vector(to_unsigned(42, 12)) and sizeit(not acp_video_on and atari_sync and not vcntrl(2), 12)) or - (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 DOWNTO 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ + (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 downto 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ -- HDIS_START[] = HDB[] & ACP_VIDEO_ON -- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- @@ -1598,20 +1600,20 @@ BEGIN RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); - hs_start <= hss_q WHEN acp_video_on ELSE - atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE - atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE - std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; + hs_start <= hss_q when acp_video_on else + atari_hl(11 downto 0) when not(acp_video_on) and atari_sync and vcntrl(2) else + atari_hh(11 downto 0) when not(acp_video_on) and atari_sync and not vcntrl(2) else + std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync; -- HS_START[] = HSS[] & ACP_VIDEO_ON -- # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- -- - h_total <= hht_q WHEN acp_video_on ELSE - atari_hl(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE - atari_hh(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and not vcntrl(2) ELSE - std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) WHEN not acp_video_on and not atari_sync; + h_total <= hht_q when acp_video_on else + atari_hl(27 downto 16) when not acp_video_on and atari_sync and vcntrl(2) else + atari_hh(27 downto 16) when not acp_video_on and atari_sync and not vcntrl(2) else + std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync; -- H_TOTAL[] = HHT[] & ACP_VIDEO_ON -- # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 @@ -1619,34 +1621,34 @@ BEGIN -- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - (std_logic_vector'('0' & VBE_q(10 DOWNTO 1)) and sizeIt(not + (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or - (std_logic_vector'('0' & VDE_q(10 DOWNTO 1)) and sizeIt(not + (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 DOWNTO 0) + VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 downto 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 DOWNTO 0) and sizeIt(not + sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 downto 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 DOWNTO 1)) and + VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 DOWNTO 16) + V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 downto 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 DOWNTO 16) and sizeIt(not + sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 downto 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 DOWNTO 1)) and + VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); -- ZÄHLER @@ -1707,24 +1709,15 @@ BEGIN VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); - (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & - VERZ1_q(0) & VERZ0_q(0)); - (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & - VERZ1_q(1) & VERZ0_q(1)); - (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & - VERZ1_q(2) & VERZ0_q(2)); - (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & - VERZ1_q(3) & VERZ0_q(3)); - (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & - VERZ1_q(4) & VERZ0_q(4)); - (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & - VERZ1_q(5) & VERZ0_q(5)); - (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & - VERZ1_q(6) & VERZ0_q(6)); - (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & - VERZ1_q(7) & VERZ0_q(7)); - (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & - VERZ1_q(8) & VERZ0_q(8)); + (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); + (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); + (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & VERZ1_q(2) & VERZ0_q(2)); + (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & VERZ1_q(3) & VERZ0_q(3)); + (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & VERZ1_q(4) & VERZ0_q(4)); + (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & VERZ1_q(5) & VERZ0_q(5)); + (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & VERZ1_q(6) & VERZ0_q(6)); + (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & VERZ1_q(7) & VERZ0_q(7)); + (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & VERZ1_q(8) & VERZ0_q(8)); VERZ0_d(0) <= DISP_ON_q; -- VERZ[1][0] = HSYNC_I[] != 0; @@ -1795,14 +1788,14 @@ BEGIN -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or - (to_std_logic(SUB_PIXEL_CNT_q(5 DOWNTO 0) = "000001") and COLOR2) or - (to_std_logic(SUB_PIXEL_CNT_q(4 DOWNTO 0) = "00001") and color4_i) or - (to_std_logic(SUB_PIXEL_CNT_q(3 DOWNTO 0) = "0001") and COLOR8) or - (to_std_logic(SUB_PIXEL_CNT_q(2 DOWNTO 0) = "001") and COLOR16) or - (to_std_logic(SUB_PIXEL_CNT_q(1 DOWNTO 0) = "01") and COLOR24)) and + (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or + (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or + (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and COLOR8) or + (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and COLOR16) or + (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); + CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 downto 0); CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; From fb71e53c7e5de18c862e90268a0d2a61ea361461 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 14 Apr 2016 18:11:14 +0000 Subject: [PATCH 085/127] fix timing violation at border color assignment --- FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 31ea155..a7a6b00 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -468,7 +468,6 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL CLK17M : std_logic; SIGNAL color4_i : std_logic; SIGNAL pixel_clk_i : std_logic; - signal fbee_pxl_half : unsigned(7 downto 0); -- Sub Module Interface Section @@ -507,7 +506,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS BEGIN -- Sub Module Section - u0 : lpm_bustri_WORD + u0 : entity work.lpm_bustri_WORD PORT MAP ( data => u0_data, @@ -570,9 +569,9 @@ BEGIN BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); - PROCESS (main_clk) + PROCESS (pixel_clk_i) BEGIN - IF rising_edge(main_clk) THEN + IF rising_edge(pixel_clk_i) THEN IF BORDER_COLOR16_ena_ctrl = '1' THEN border_color_q(23 downto 16) <= border_color_d(23 downto 16); END IF; @@ -1536,15 +1535,13 @@ BEGIN -- 640 pixels, 25.175 MHz, VGA -- hsync pulse length in pixeln = frequenz / = 500ns - fbee_pxl_half <= d"16" + ("0" & vr_frq(7 downto 1)); HSY_LEN_d <= std_logic_vector'(d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else std_logic_vector'(d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else std_logic_vector'(d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else std_logic_vector'(d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else std_logic_vector'(d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else std_logic_vector'(d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else - std_logic_vector(fbee_pxl_half) when acp_video_on = '1' and acp_vctr(9) = '1'; - -- std_logic_vector'(vr_frq(7 downto 1) + unsigned'(8d"16")) when acp_video_on = '1' and acp_vctr(9) = '1' ; + std_logic_vector(d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1'; -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or From 6a0eebf0684f2775fd7d380a22e896c6c4e5b853 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 25 Apr 2016 19:09:52 +0000 Subject: [PATCH 086/127] change formatting --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 1312 ++++++++--------- .../Video/video_mod_mux_clutctr.vhd | 940 ++++++------ 2 files changed, 1122 insertions(+), 1130 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index d5e2740..cb29254 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -16,56 +16,56 @@ -- FIFO WATER MARK -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -LIBRARY ieee; - USE ieee.std_logic_1164.all; - USE ieee.std_logic_arith.all; -ENTITY ddr_ctr IS - PORT +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; +entity ddr_ctr is + port ( - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - DDR_SYNC_66M : IN std_logic; - CLR_FIFO : IN std_logic; - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); - BLITTER_SIG : IN std_logic; - BLITTER_WR : IN std_logic; - DDRCLK0 : IN std_logic; - CLK33M : IN std_logic; - FIFO_MW : IN std_logic_vector(8 DOWNTO 0); - VA : BUFFER std_logic_vector(12 DOWNTO 0); - nVWE : BUFFER std_logic; - nVRAS : BUFFER std_logic; - nVCS : BUFFER std_logic; - VCKE : BUFFER std_logic; - nVCAS : BUFFER std_logic; - FB_LE : BUFFER std_logic_vector(3 DOWNTO 0); - FB_VDOE : BUFFER std_logic_vector(3 DOWNTO 0); - SR_FIFO_WRE : BUFFER std_logic; - SR_DDR_FB : BUFFER std_logic; - SR_DDR_WR : BUFFER std_logic; - SR_DDRWR_D_SEL : BUFFER std_logic; - SR_VDMP : BUFFER std_logic_vector(7 DOWNTO 0); - VIDEO_DDR_TA : BUFFER std_logic; - SR_BLITTER_DACK : BUFFER std_logic; - BA : BUFFER std_logic_vector(1 DOWNTO 0); - DDRWR_D_SEL1 : BUFFER std_logic; - VDM_SEL : BUFFER std_logic_vector(3 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + FB_ADR : in std_logic_vector(31 downto 0); + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_OE : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nRSTO : in std_logic; + MAIN_CLK : in std_logic; + FB_ALE : in std_logic; + nFB_WR : in std_logic; + DDR_SYNC_66M : in std_logic; + CLR_FIFO : in std_logic; + VIDEO_RAM_CTR : in std_logic_vector(15 downto 0); + BLITTER_ADR : in std_logic_vector(31 downto 0); + BLITTER_SIG : in std_logic; + BLITTER_WR : in std_logic; + DDRCLK0 : in std_logic; + CLK33M : in std_logic; + FIFO_MW : in std_logic_vector(8 downto 0); + VA : buffer std_logic_vector(12 downto 0); + nVWE : buffer std_logic; + nVRAS : buffer std_logic; + nVCS : buffer std_logic; + VCKE : buffer std_logic; + nVCAS : buffer std_logic; + FB_LE : buffer std_logic_vector(3 downto 0); + FB_VDOE : buffer std_logic_vector(3 downto 0); + SR_FIFO_WRE : buffer std_logic; + SR_DDR_FB : buffer std_logic; + SR_DDR_WR : buffer std_logic; + SR_DDRWR_D_SEL : buffer std_logic; + SR_VDMP : buffer std_logic_vector(7 downto 0); + VIDEO_DDR_TA : buffer std_logic; + SR_BLITTER_DACK : buffer std_logic; + BA : buffer std_logic_vector(1 downto 0); + DDRWR_D_SEL1 : buffer std_logic; + VDM_SEL : buffer std_logic_vector(3 downto 0); + FB_AD : inout std_logic_vector(31 downto 0) ); -END ddr_ctr; +end ddr_ctr; -ARCHITECTURE rtl OF ddr_ctr IS +architecture rtl of ddr_ctr is -- START (NORMAL 8 CYCLES TOTAL = 60ns) -- CONFIG -- READ CPU UND BLITTER, @@ -73,522 +73,522 @@ ARCHITECTURE rtl OF ddr_ctr IS -- READ FIFO -- CLOSE FIFO BANK -- REFRESH 10X7.5NfS=75NS - SIGNAL FB_REGDDR_3 : std_logic_vector(2 DOWNTO 0); - SIGNAL FB_REGDDR_d : std_logic_vector(2 DOWNTO 0); - SIGNAL FB_REGDDR_q : std_logic_vector(2 DOWNTO 0); - SIGNAL DDR_SM_6 : std_logic_vector(5 DOWNTO 0); - SIGNAL DDR_SM_d : std_logic_vector(5 DOWNTO 0); - SIGNAL DDR_SM_q : std_logic_vector(5 DOWNTO 0); - SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); - SIGNAL VA_P : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_P_d : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_P_q : std_logic_vector(12 DOWNTO 0); - SIGNAL BA_P : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_P_d : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_P_q : std_logic_vector(1 DOWNTO 0); - SIGNAL VA_S : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_S_d : std_logic_vector(12 DOWNTO 0); - SIGNAL VA_S_q : std_logic_vector(12 DOWNTO 0); - SIGNAL BA_S : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_S_d : std_logic_vector(1 DOWNTO 0); - SIGNAL BA_S_q : std_logic_vector(1 DOWNTO 0); - SIGNAL MCS : std_logic_vector(1 DOWNTO 0); - SIGNAL MCS_d : std_logic_vector(1 DOWNTO 0); - SIGNAL MCS_q : std_logic_vector(1 DOWNTO 0); - SIGNAL SR_VDMP_d : std_logic_vector(7 DOWNTO 0); - SIGNAL SR_VDMP_q : std_logic_vector(7 DOWNTO 0); - SIGNAL CPU_ROW_ADR : std_logic_vector(12 DOWNTO 0); - SIGNAL CPU_BA : std_logic_vector(1 DOWNTO 0); - SIGNAL CPU_COL_ADR : std_logic_vector(9 DOWNTO 0); - SIGNAL BLITTER_ROW_ADR : std_logic_vector(12 DOWNTO 0); - SIGNAL BLITTER_BA : std_logic_vector(1 DOWNTO 0); - SIGNAL BLITTER_COL_ADR : std_logic_vector(9 DOWNTO 0); - SIGNAL FIFO_ROW_ADR : std_logic_vector(12 DOWNTO 0); - SIGNAL FIFO_BA : std_logic_vector(1 DOWNTO 0); - SIGNAL FIFO_COL_ADR : std_logic_vector(9 DOWNTO 0); - SIGNAL DDR_REFRESH_CNT : std_logic_vector(10 DOWNTO 0); - SIGNAL DDR_REFRESH_CNT_d : std_logic_vector(10 DOWNTO 0); - SIGNAL DDR_REFRESH_CNT_q : std_logic_vector(10 DOWNTO 0); - SIGNAL DDR_REFRESH_SIG : std_logic_vector(3 DOWNTO 0); - SIGNAL DDR_REFRESH_SIG_d : std_logic_vector(3 DOWNTO 0); - SIGNAL DDR_REFRESH_SIG_q : std_logic_vector(3 DOWNTO 0); - SIGNAL VIDEO_BASE_L_D : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_L_D_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_L_D_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_M_D : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_M_D_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_M_D_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_H_D : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_H_D_d : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_H_D_q : std_logic_vector(7 DOWNTO 0); - SIGNAL VIDEO_BASE_X_D : std_logic_vector(2 DOWNTO 0); - SIGNAL VIDEO_BASE_X_D_d : std_logic_vector(2 DOWNTO 0); - SIGNAL VIDEO_BASE_X_D_q : std_logic_vector(2 DOWNTO 0); - SIGNAL VIDEO_ADR_CNT : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_ADR_CNT_d : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_ADR_CNT_q : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_BASE_ADR : std_logic_vector(22 DOWNTO 0); - SIGNAL VIDEO_ACT_ADR : std_logic_vector(26 DOWNTO 0); - SIGNAL u0_data : std_logic_vector(7 DOWNTO 0); - SIGNAL u0_tridata : std_logic_vector(7 DOWNTO 0); - SIGNAL FB_REGDDR_0_clk_ctrl : std_logic; - SIGNAL SR_VDMP0_clk_ctrl : std_logic; - SIGNAL MCS0_clk_ctrl : std_logic; - SIGNAL VA_S0_clk_ctrl : std_logic; - SIGNAL BA_S0_clk_ctrl : std_logic; - SIGNAL VA_P0_clk_ctrl : std_logic; - SIGNAL BA_P0_clk_ctrl : std_logic; - SIGNAL DDR_SM_0_clk_ctrl : std_logic; - SIGNAL VIDEO_ADR_CNT0_clk_ctrl : std_logic; - SIGNAL VIDEO_ADR_CNT0_ena_ctrl : std_logic; - SIGNAL DDR_REFRESH_CNT0_clk_ctrl : std_logic; - SIGNAL DDR_REFRESH_SIG0_clk_ctrl : std_logic; - SIGNAL DDR_REFRESH_SIG0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_L_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_L_D0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_M_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_M_D0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_H_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_H_D0_ena_ctrl : std_logic; - SIGNAL VIDEO_BASE_X_D0_clk_ctrl : std_logic; - SIGNAL VIDEO_BASE_X_D0_ena_ctrl : std_logic; - SIGNAL VA12_2 : std_logic; - SIGNAL VA12_1 : std_logic; - SIGNAL VA11_2 : std_logic; - SIGNAL VA11_1 : std_logic; - SIGNAL VA10_2 : std_logic; - SIGNAL VA10_1 : std_logic; - SIGNAL VA9_2 : std_logic; - SIGNAL VA9_1 : std_logic; - SIGNAL VA8_2 : std_logic; - SIGNAL VA8_1 : std_logic; - SIGNAL VA7_2 : std_logic; - SIGNAL VA7_1 : std_logic; - SIGNAL VA6_2 : std_logic; - SIGNAL VA6_1 : std_logic; - SIGNAL VA5_2 : std_logic; - SIGNAL VA5_1 : std_logic; - SIGNAL VA4_2 : std_logic; - SIGNAL VA4_1 : std_logic; - SIGNAL VA3_2 : std_logic; - SIGNAL VA3_1 : std_logic; - SIGNAL VA2_2 : std_logic; - SIGNAL VA2_1 : std_logic; - SIGNAL VA1_2 : std_logic; - SIGNAL VA1_1 : std_logic; - SIGNAL VA0_2 : std_logic; - SIGNAL VA0_1 : std_logic; - SIGNAL BA1_2 : std_logic; - SIGNAL BA1_1 : std_logic; - SIGNAL BA0_2 : std_logic; - SIGNAL BA0_1 : std_logic; - SIGNAL BUS_CYC_d_2 : std_logic; - SIGNAL BUS_CYC_d_1 : std_logic; - SIGNAL FIFO_BANK_OK_d_2 : std_logic; - SIGNAL FIFO_BANK_OK_d_1 : std_logic; - SIGNAL u0_enabledt : std_logic; + signal FB_REGDDR_3 : std_logic_vector(2 downto 0); + signal FB_REGDDR_d : std_logic_vector(2 downto 0); + signal FB_REGDDR_q : std_logic_vector(2 downto 0); + signal DDR_SM_6 : std_logic_vector(5 downto 0); + signal DDR_SM_d : std_logic_vector(5 downto 0); + signal DDR_SM_q : std_logic_vector(5 downto 0); + signal FB_B : std_logic_vector(3 downto 0); + signal VA_P : std_logic_vector(12 downto 0); + signal VA_P_d : std_logic_vector(12 downto 0); + signal VA_P_q : std_logic_vector(12 downto 0); + signal BA_P : std_logic_vector(1 downto 0); + signal BA_P_d : std_logic_vector(1 downto 0); + signal BA_P_q : std_logic_vector(1 downto 0); + signal VA_S : std_logic_vector(12 downto 0); + signal VA_S_d : std_logic_vector(12 downto 0); + signal VA_S_q : std_logic_vector(12 downto 0); + signal BA_S : std_logic_vector(1 downto 0); + signal BA_S_d : std_logic_vector(1 downto 0); + signal BA_S_q : std_logic_vector(1 downto 0); + signal MCS : std_logic_vector(1 downto 0); + signal MCS_d : std_logic_vector(1 downto 0); + signal MCS_q : std_logic_vector(1 downto 0); + signal SR_VDMP_d : std_logic_vector(7 downto 0); + signal SR_VDMP_q : std_logic_vector(7 downto 0); + signal CPU_ROW_ADR : std_logic_vector(12 downto 0); + signal CPU_BA : std_logic_vector(1 downto 0); + signal CPU_COL_ADR : std_logic_vector(9 downto 0); + signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0); + signal BLITTER_BA : std_logic_vector(1 downto 0); + signal BLITTER_COL_ADR : std_logic_vector(9 downto 0); + signal FIFO_ROW_ADR : std_logic_vector(12 downto 0); + signal FIFO_BA : std_logic_vector(1 downto 0); + signal FIFO_COL_ADR : std_logic_vector(9 downto 0); + signal DDR_REFRESH_CNT : std_logic_vector(10 downto 0); + signal DDR_REFRESH_CNT_d : std_logic_vector(10 downto 0); + signal DDR_REFRESH_CNT_q : std_logic_vector(10 downto 0); + signal DDR_REFRESH_SIG : std_logic_vector(3 downto 0); + signal DDR_REFRESH_SIG_d : std_logic_vector(3 downto 0); + signal DDR_REFRESH_SIG_q : std_logic_vector(3 downto 0); + signal VIDEO_BASE_L_D : std_logic_vector(7 downto 0); + signal VIDEO_BASE_L_D_d : std_logic_vector(7 downto 0); + signal VIDEO_BASE_L_D_q : std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D : std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D_d : std_logic_vector(7 downto 0); + signal VIDEO_BASE_M_D_q : std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D : std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D_d : std_logic_vector(7 downto 0); + signal VIDEO_BASE_H_D_q : std_logic_vector(7 downto 0); + signal VIDEO_BASE_X_D : std_logic_vector(2 downto 0); + signal VIDEO_BASE_X_D_d : std_logic_vector(2 downto 0); + signal VIDEO_BASE_X_D_q : std_logic_vector(2 downto 0); + signal VIDEO_ADR_CNT : std_logic_vector(22 downto 0); + signal VIDEO_ADR_CNT_d : std_logic_vector(22 downto 0); + signal VIDEO_ADR_CNT_q : std_logic_vector(22 downto 0); + signal VIDEO_BASE_ADR : std_logic_vector(22 downto 0); + signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0); + signal u0_data : std_logic_vector(7 downto 0); + signal u0_tridata : std_logic_vector(7 downto 0); + signal FB_REGDDR_0_clk_ctrl : std_logic; + signal SR_VDMP0_clk_ctrl : std_logic; + signal MCS0_clk_ctrl : std_logic; + signal VA_S0_clk_ctrl : std_logic; + signal BA_S0_clk_ctrl : std_logic; + signal VA_P0_clk_ctrl : std_logic; + signal BA_P0_clk_ctrl : std_logic; + signal DDR_SM_0_clk_ctrl : std_logic; + signal VIDEO_ADR_CNT0_clk_ctrl : std_logic; + signal VIDEO_ADR_CNT0_ena_ctrl : std_logic; + signal DDR_REFRESH_CNT0_clk_ctrl : std_logic; + signal DDR_REFRESH_SIG0_clk_ctrl : std_logic; + signal DDR_REFRESH_SIG0_ena_ctrl : std_logic; + signal VIDEO_BASE_L_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_L_D0_ena_ctrl : std_logic; + signal VIDEO_BASE_M_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_M_D0_ena_ctrl : std_logic; + signal VIDEO_BASE_H_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_H_D0_ena_ctrl : std_logic; + signal VIDEO_BASE_X_D0_clk_ctrl : std_logic; + signal VIDEO_BASE_X_D0_ena_ctrl : std_logic; + signal VA12_2 : std_logic; + signal VA12_1 : std_logic; + signal VA11_2 : std_logic; + signal VA11_1 : std_logic; + signal VA10_2 : std_logic; + signal VA10_1 : std_logic; + signal VA9_2 : std_logic; + signal VA9_1 : std_logic; + signal VA8_2 : std_logic; + signal VA8_1 : std_logic; + signal VA7_2 : std_logic; + signal VA7_1 : std_logic; + signal VA6_2 : std_logic; + signal VA6_1 : std_logic; + signal VA5_2 : std_logic; + signal VA5_1 : std_logic; + signal VA4_2 : std_logic; + signal VA4_1 : std_logic; + signal VA3_2 : std_logic; + signal VA3_1 : std_logic; + signal VA2_2 : std_logic; + signal VA2_1 : std_logic; + signal VA1_2 : std_logic; + signal VA1_1 : std_logic; + signal VA0_2 : std_logic; + signal VA0_1 : std_logic; + signal BA1_2 : std_logic; + signal BA1_1 : std_logic; + signal BA0_2 : std_logic; + signal BA0_1 : std_logic; + signal BUS_CYC_d_2 : std_logic; + signal BUS_CYC_d_1 : std_logic; + signal FIFO_BANK_OK_d_2 : std_logic; + signal FIFO_BANK_OK_d_1 : std_logic; + signal u0_enabledt : std_logic; SiGNAL gnd : std_logic; - SIGNAL vcc : std_logic; - SIGNAL VIDEO_CNT_H : std_logic; - SIGNAL VIDEO_CNT_M : std_logic; - SIGNAL VIDEO_CNT_L : std_logic; - SIGNAL VIDEO_BASE_H : std_logic; - SIGNAL VIDEO_BASE_M : std_logic; - SIGNAL VIDEO_BASE_L : std_logic; - SIGNAL REFRESH_TIME_q : std_logic; - SIGNAL REFRESH_TIME_clk : std_logic; - SIGNAL REFRESH_TIME_d : std_logic; - SIGNAL REFRESH_TIME : std_logic; - SIGNAL DDR_REFRESH_REQ_q : std_logic; - SIGNAL DDR_REFRESH_REQ_clk : std_logic; - SIGNAL DDR_REFRESH_REQ_d : std_logic; - SIGNAL DDR_REFRESH_REQ : std_logic; - SIGNAL DDR_REFRESH_ON : std_logic; - SIGNAL FIFO_BANK_NOT_OK : std_logic; - SIGNAL FIFO_BANK_OK_q : std_logic; - SIGNAL FIFO_BANK_OK_clk : std_logic; - SIGNAL FIFO_BANK_OK_d : std_logic; - SIGNAL FIFO_BANK_OK : std_logic; + signal vcc : std_logic; + signal VIDEO_CNT_H : std_logic; + signal VIDEO_CNT_M : std_logic; + signal VIDEO_CNT_L : std_logic; + signal VIDEO_BASE_H : std_logic; + signal VIDEO_BASE_M : std_logic; + signal VIDEO_BASE_L : std_logic; + signal REFRESH_TIME_q : std_logic; + signal REFRESH_TIME_clk : std_logic; + signal REFRESH_TIME_d : std_logic; + signal REFRESH_TIME : std_logic; + signal DDR_REFRESH_REQ_q : std_logic; + signal DDR_REFRESH_REQ_clk : std_logic; + signal DDR_REFRESH_REQ_d : std_logic; + signal DDR_REFRESH_REQ : std_logic; + signal DDR_REFRESH_ON : std_logic; + signal FIFO_BANK_NOT_OK : std_logic; + signal FIFO_BANK_OK_q : std_logic; + signal FIFO_BANK_OK_clk : std_logic; + signal FIFO_BANK_OK_d : std_logic; + signal FIFO_BANK_OK : std_logic; SiGNAL SR_FIFO_WRE_q : std_logic; - SIGNAL SR_FIFO_WRE_clk : std_logic; - SIGNAL SR_FIFO_WRE_d : std_logic; - SIGNAL STOP_q : std_logic; - SIGNAL STOP_clk : std_logic; - SIGNAL STOP_d : std_logic; - SIGNAL STOP : std_logic; - SIGNAL CLEAR_FIFO_CNT_q : std_logic; - SIGNAL CLEAR_FIFO_CNT_clk : std_logic; - SIGNAL CLEAR_FIFO_CNT_d : std_logic; - SIGNAL CLEAR_FIFO_CNT : std_logic; - SIGNAL CLR_FIFO_SYNC_q : std_logic; - SIGNAL CLR_FIFO_SYNC_clk : std_logic; - SIGNAL CLR_FIFO_SYNC_d : std_logic; - SIGNAL CLR_FIFO_SYNC : std_logic; - SIGNAL FIFO_ACTIVE : std_logic; - SIGNAL FIFO_AC_q : std_logic; - SIGNAL FIFO_AC_clk : std_logic; - SIGNAL FIFO_AC_d : std_logic; - SIGNAL FIFO_AC : std_logic; - SIGNAL FIFO_REQ_q : std_logic; - SIGNAL FIFO_REQ_clk : std_logic; - SIGNAL FIFO_REQ_d : std_logic; - SIGNAL FIFO_REQ : std_logic; - SIGNAL BLITTER_AC_q : std_logic; - SIGNAL BLITTER_AC_clk : std_logic; - SIGNAL BLITTER_AC_d : std_logic; - SIGNAL BLITTER_AC : std_logic; - SIGNAL BLITTER_REQ_q : std_logic; - SIGNAL BLITTER_REQ_clk : std_logic; - SIGNAL BLITTER_REQ_d : std_logic; - SIGNAL BLITTER_REQ : std_logic; - SIGNAL BUS_CYC_END : std_logic; - SIGNAL BUS_CYC_q : std_logic; - SIGNAL BUS_CYC_clk : std_logic; - SIGNAL BUS_CYC_d : std_logic; - SIGNAL BUS_CYC : std_logic; - SIGNAL CPU_AC_q : std_logic; - SIGNAL CPU_AC_clk : std_logic; - SIGNAL CPU_AC_d : std_logic; - SIGNAL CPU_AC : std_logic; - SIGNAL CPU_REQ_q : std_logic; - SIGNAL CPU_REQ_clk : std_logic; - SIGNAL CPU_REQ_d : std_logic; - SIGNAL CPU_REQ : std_logic; - SIGNAL CPU_SIG : std_logic; - SIGNAL SR_DDRWR_D_SEL_q : std_logic; - SIGNAL SR_DDRWR_D_SEL_clk : std_logic; - SIGNAL SR_DDRWR_D_SEL_d : std_logic; - SIGNAL SR_DDR_WR_q : std_logic; - SIGNAL SR_DDR_WR_clk : std_logic; - SIGNAL SR_DDR_WR_d : std_logic; - SIGNAL DDR_CONFIG : std_logic; - SIGNAL DDR_CS_q : std_logic; - SIGNAL DDR_CS_ena : std_logic; - SIGNAL DDR_CS_clk : std_logic; - SIGNAL DDR_CS_d : std_logic; - SIGNAL DDR_CS : std_logic; - SIGNAL DDR_SEL : std_logic; - SIGNAL CPU_DDR_SYNC_q : std_logic; - SIGNAL CPU_DDR_SYNC_clk : std_logic; - SIGNAL CPU_DDR_SYNC_d : std_logic; - SIGNAL CPU_DDR_SYNC : std_logic; - SIGNAL VWE : std_logic; - SIGNAL VRAS : std_logic; - SIGNAL VCAS : std_logic; - SIGNAL LINE : std_logic; + signal SR_FIFO_WRE_clk : std_logic; + signal SR_FIFO_WRE_d : std_logic; + signal STOP_q : std_logic; + signal STOP_clk : std_logic; + signal STOP_d : std_logic; + signal STOP : std_logic; + signal CLEAR_FIFO_CNT_q : std_logic; + signal CLEAR_FIFO_CNT_clk : std_logic; + signal CLEAR_FIFO_CNT_d : std_logic; + signal CLEAR_FIFO_CNT : std_logic; + signal CLR_FIFO_SYNC_q : std_logic; + signal CLR_FIFO_SYNC_clk : std_logic; + signal CLR_FIFO_SYNC_d : std_logic; + signal CLR_FIFO_SYNC : std_logic; + signal FIFO_ACTIVE : std_logic; + signal FIFO_AC_q : std_logic; + signal FIFO_AC_clk : std_logic; + signal FIFO_AC_d : std_logic; + signal FIFO_AC : std_logic; + signal FIFO_REQ_q : std_logic; + signal FIFO_REQ_clk : std_logic; + signal FIFO_REQ_d : std_logic; + signal FIFO_REQ : std_logic; + signal BLITTER_AC_q : std_logic; + signal BLITTER_AC_clk : std_logic; + signal BLITTER_AC_d : std_logic; + signal BLITTER_AC : std_logic; + signal BLITTER_REQ_q : std_logic; + signal BLITTER_REQ_clk : std_logic; + signal BLITTER_REQ_d : std_logic; + signal BLITTER_REQ : std_logic; + signal BUS_CYC_END : std_logic; + signal BUS_CYC_q : std_logic; + signal BUS_CYC_clk : std_logic; + signal BUS_CYC_d : std_logic; + signal BUS_CYC : std_logic; + signal CPU_AC_q : std_logic; + signal CPU_AC_clk : std_logic; + signal CPU_AC_d : std_logic; + signal CPU_AC : std_logic; + signal CPU_REQ_q : std_logic; + signal CPU_REQ_clk : std_logic; + signal CPU_REQ_d : std_logic; + signal CPU_REQ : std_logic; + signal CPU_SIG : std_logic; + signal SR_DDRWR_D_SEL_q : std_logic; + signal SR_DDRWR_D_SEL_clk : std_logic; + signal SR_DDRWR_D_SEL_d : std_logic; + signal SR_DDR_WR_q : std_logic; + signal SR_DDR_WR_clk : std_logic; + signal SR_DDR_WR_d : std_logic; + signal DDR_CONFIG : std_logic; + signal DDR_CS_q : std_logic; + signal DDR_CS_ena : std_logic; + signal DDR_CS_clk : std_logic; + signal DDR_CS_d : std_logic; + signal DDR_CS : std_logic; + signal DDR_SEL : std_logic; + signal CPU_DDR_SYNC_q : std_logic; + signal CPU_DDR_SYNC_clk : std_logic; + signal CPU_DDR_SYNC_d : std_logic; + signal CPU_DDR_SYNC : std_logic; + signal VWE : std_logic; + signal VRAS : std_logic; + signal VCAS : std_logic; + signal LINE : std_logic; - SIGNAL v_basx : std_logic_vector(1 DOWNTO 0); - SIGNAL v_basx_cs : std_logic; + signal v_basx : std_logic_vector(1 downto 0); + signal v_basx_cs : std_logic; - SIGNAL v_bash : std_logic_vector(7 DOWNTO 0); - SIGNAL v_bash_cs : std_logic; + signal v_bash : std_logic_vector(7 downto 0); + signal v_bash_cs : std_logic; - SIGNAL reg_ta : std_logic; + signal reg_ta : std_logic; -- Sub Module Interface Section - COMPONENT lpm_bustri_BYT - PORT + component lpm_bustri_BYT + port ( - data : IN std_logic_vector(7 DOWNTO 0); - enabledt : IN std_logic; - tridata : BUFFER std_logic_vector(7 DOWNTO 0) + data : in std_logic_vector(7 downto 0); + enabledt : in std_logic; + tridata : buffer std_logic_vector(7 downto 0) ); - END COMPONENT lpm_bustri_BYT; + end component lpm_bustri_BYT; - FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS - VARIABLE ret : std_logic; - BEGIN - IF x THEN + function to_std_logic(X : in boolean) return std_logic is + variable ret : std_logic; + begin + if x then ret := '1'; - ELSE + else ret := '0'; - END IF; - RETURN ret; - END to_std_logic; + end if; + return ret; + end to_std_logic; -- sizeIt replicates a value to an array of specific length. - FUNCTION sizeit(a: std_logic; len: integer) RETURN std_logic_vector IS - VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0); - BEGIN - FOR i IN rep'RANGE LOOP + function sizeit(a: std_logic; len: integer) return std_logic_vector is + variable rep: std_logic_vector(len - 1 downto 0); + begin + FOR i in rep'RANGE LOOP rep(i) := a; - END LOOP; - RETURN rep; - END sizeIt; + end LOOP; + return rep; + end sizeIt; -BEGIN +begin -- Sub Module Section - u0: lpm_bustri_BYT + u0 : lpm_bustri_BYT port map ( - data=>u0_data, - enabledt=>u0_enabledt, - tridata=>u0_tridata + data => u0_data, + enabledt => u0_enabledt, + tridata => u0_tridata ); -- Register Section SR_FIFO_WRE <= SR_FIFO_WRE_q; - PROCESS (SR_FIFO_WRE_clk) - BEGIN - IF SR_FIFO_WRE_clk'event and SR_FIFO_WRE_clk='1' THEN + process (SR_FIFO_WRE_clk) + begin + if rising_edge(sr_fifo_wre_clk) then SR_FIFO_WRE_q <= SR_FIFO_WRE_d; - END IF; - END PROCESS; + end if; + end process; SR_DDR_WR <= SR_DDR_WR_q; - PROCESS (SR_DDR_WR_clk) - BEGIN - IF SR_DDR_WR_clk'event and SR_DDR_WR_clk='1' THEN + process (SR_DDR_WR_clk) + begin + if rising_edge(sr_ddr_wr_clk) then SR_DDR_WR_q <= SR_DDR_WR_d; - END IF; - END PROCESS; + end if; + end process; SR_DDRWR_D_SEL <= SR_DDRWR_D_SEL_q; - PROCESS (SR_DDRWR_D_SEL_clk) - BEGIN - IF SR_DDRWR_D_SEL_clk'event and SR_DDRWR_D_SEL_clk='1' THEN + process (SR_DDRWR_D_SEL_clk) + begin + if rising_edge(sr_ddrwr_d_sel_clk) then SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d; - END IF; - END PROCESS; + end if; + end process; SR_VDMP <= SR_VDMP_q; - PROCESS (SR_VDMP0_clk_ctrl) - BEGIN - IF SR_VDMP0_clk_ctrl'event and SR_VDMP0_clk_ctrl='1' THEN + process (SR_VDMP0_clk_ctrl) + begin + if rising_edge(sr_vdmp0_clk_ctrl) then SR_VDMP_q <= SR_VDMP_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FB_REGDDR_0_clk_ctrl) - BEGIN - IF FB_REGDDR_0_clk_ctrl'event and FB_REGDDR_0_clk_ctrl='1' THEN + process (FB_REGDDR_0_clk_ctrl) + begin + if rising_edge(fb_regddr_0_clk_ctrl) then FB_REGDDR_q <= FB_REGDDR_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_SM_0_clk_ctrl) - BEGIN - IF DDR_SM_0_clk_ctrl'event and DDR_SM_0_clk_ctrl='1' THEN + process (DDR_SM_0_clk_ctrl) + begin + if rising_edge(ddr_sm_0_clk_ctrl) then DDR_SM_q <= DDR_SM_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (VA_P0_clk_ctrl) - BEGIN - IF VA_P0_clk_ctrl'event and VA_P0_clk_ctrl='1' THEN + process (VA_P0_clk_ctrl) + begin + if rising_edge(va_p0_clk_ctrl) then VA_P_q <= VA_P_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BA_P0_clk_ctrl) - BEGIN - IF BA_P0_clk_ctrl'event and BA_P0_clk_ctrl='1' THEN + process (BA_P0_clk_ctrl) + begin + if rising_edge(ba_p0_clk_ctrl) then BA_P_q <= BA_P_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (VA_S0_clk_ctrl) - BEGIN - IF VA_S0_clk_ctrl'event and VA_S0_clk_ctrl='1' THEN + process (VA_S0_clk_ctrl) + begin + if rising_edge(va_s0_clk_ctrl) then VA_S_q <= VA_S_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BA_S0_clk_ctrl) - BEGIN - IF BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' THEN + process (BA_S0_clk_ctrl) + begin + if BA_S0_clk_ctrl'event and BA_S0_clk_ctrl='1' then BA_S_q <= BA_S_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (MCS0_clk_ctrl) - BEGIN - IF MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' THEN + process (MCS0_clk_ctrl) + begin + if MCS0_clk_ctrl'event and MCS0_clk_ctrl='1' then MCS_q <= MCS_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CPU_DDR_SYNC_clk) - BEGIN - IF CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' THEN + process (CPU_DDR_SYNC_clk) + begin + if CPU_DDR_SYNC_clk'event and CPU_DDR_SYNC_clk='1' then CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_CS_clk) - BEGIN - IF DDR_CS_clk'event and DDR_CS_clk='1' THEN - IF DDR_CS_ena='1' THEN + process (DDR_CS_clk) + begin + if DDR_CS_clk'event and DDR_CS_clk='1' then + if DDR_CS_ena='1' then DDR_CS_q <= DDR_CS_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (CPU_REQ_clk) - BEGIN - IF CPU_REQ_clk'event and CPU_REQ_clk='1' THEN + process (CPU_REQ_clk) + begin + if CPU_REQ_clk'event and CPU_REQ_clk='1' then CPU_REQ_q <= CPU_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CPU_AC_clk) - BEGIN - IF CPU_AC_clk'event and CPU_AC_clk='1' THEN + process (CPU_AC_clk) + begin + if CPU_AC_clk'event and CPU_AC_clk='1' then CPU_AC_q <= CPU_AC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BUS_CYC_clk) - BEGIN - IF BUS_CYC_clk'event and BUS_CYC_clk='1' THEN + process (BUS_CYC_clk) + begin + if BUS_CYC_clk'event and BUS_CYC_clk='1' then BUS_CYC_q <= BUS_CYC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BLITTER_REQ_clk) - BEGIN - IF BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' THEN + process (BLITTER_REQ_clk) + begin + if BLITTER_REQ_clk'event and BLITTER_REQ_clk='1' then BLITTER_REQ_q <= BLITTER_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (BLITTER_AC_clk) - BEGIN - IF BLITTER_AC_clk'event and BLITTER_AC_clk='1' THEN + process (BLITTER_AC_clk) + begin + if BLITTER_AC_clk'event and BLITTER_AC_clk='1' then BLITTER_AC_q <= BLITTER_AC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FIFO_REQ_clk) - BEGIN - IF FIFO_REQ_clk'event and FIFO_REQ_clk='1' THEN + process (FIFO_REQ_clk) + begin + if FIFO_REQ_clk'event and FIFO_REQ_clk='1' then FIFO_REQ_q <= FIFO_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FIFO_AC_clk) - BEGIN - IF FIFO_AC_clk'event and FIFO_AC_clk='1' THEN + process (FIFO_AC_clk) + begin + if FIFO_AC_clk'event and FIFO_AC_clk='1' then FIFO_AC_q <= FIFO_AC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CLR_FIFO_SYNC_clk) - BEGIN - IF CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' THEN + process (CLR_FIFO_SYNC_clk) + begin + if CLR_FIFO_SYNC_clk'event and CLR_FIFO_SYNC_clk='1' then CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (CLEAR_FIFO_CNT_clk) - BEGIN - IF CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' THEN + process (CLEAR_FIFO_CNT_clk) + begin + if CLEAR_FIFO_CNT_clk'event and CLEAR_FIFO_CNT_clk='1' then CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (STOP_clk) - BEGIN - IF STOP_clk'event and STOP_clk='1' THEN + process (STOP_clk) + begin + if STOP_clk'event and STOP_clk='1' then STOP_q <= STOP_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (FIFO_BANK_OK_clk) - BEGIN - IF FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' THEN + process (FIFO_BANK_OK_clk) + begin + if FIFO_BANK_OK_clk'event and FIFO_BANK_OK_clk='1' then FIFO_BANK_OK_q <= FIFO_BANK_OK_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_REFRESH_CNT0_clk_ctrl) - BEGIN - IF DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' THEN + process (DDR_REFRESH_CNT0_clk_ctrl) + begin + if DDR_REFRESH_CNT0_clk_ctrl'event and DDR_REFRESH_CNT0_clk_ctrl='1' then DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_REFRESH_REQ_clk) - BEGIN - IF DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' THEN + process (DDR_REFRESH_REQ_clk) + begin + if DDR_REFRESH_REQ_clk'event and DDR_REFRESH_REQ_clk='1' then DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (DDR_REFRESH_SIG0_clk_ctrl) - BEGIN - IF DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' THEN - IF DDR_REFRESH_SIG0_ena_ctrl='1' THEN + process (DDR_REFRESH_SIG0_clk_ctrl) + begin + if DDR_REFRESH_SIG0_clk_ctrl'event and DDR_REFRESH_SIG0_clk_ctrl='1' then + if DDR_REFRESH_SIG0_ena_ctrl='1' then DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (REFRESH_TIME_clk) - BEGIN - IF REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' THEN + process (REFRESH_TIME_clk) + begin + if REFRESH_TIME_clk'event and REFRESH_TIME_clk = '1' then REFRESH_TIME_q <= REFRESH_TIME_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (VIDEO_BASE_L_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_L_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_L_D0_clk_ctrl) + begin + if VIDEO_BASE_L_D0_clk_ctrl'event and VIDEO_BASE_L_D0_clk_ctrl='1' then + if VIDEO_BASE_L_D0_ena_ctrl='1' then VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_BASE_M_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_M_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_M_D0_clk_ctrl) + begin + if VIDEO_BASE_M_D0_clk_ctrl'event and VIDEO_BASE_M_D0_clk_ctrl='1' then + if VIDEO_BASE_M_D0_ena_ctrl='1' then VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_BASE_H_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_H_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_H_D0_clk_ctrl) + begin + if VIDEO_BASE_H_D0_clk_ctrl'event and VIDEO_BASE_H_D0_clk_ctrl='1' then + if VIDEO_BASE_H_D0_ena_ctrl='1' then VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_BASE_X_D0_clk_ctrl) - BEGIN - IF VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' THEN - IF VIDEO_BASE_X_D0_ena_ctrl='1' THEN + process (VIDEO_BASE_X_D0_clk_ctrl) + begin + if VIDEO_BASE_X_D0_clk_ctrl'event and VIDEO_BASE_X_D0_clk_ctrl='1' then + if VIDEO_BASE_X_D0_ena_ctrl='1' then VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (VIDEO_ADR_CNT0_clk_ctrl) - BEGIN - IF VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' THEN - IF VIDEO_ADR_CNT0_ena_ctrl='1' THEN + process (VIDEO_ADR_CNT0_clk_ctrl) + begin + if VIDEO_ADR_CNT0_clk_ctrl'event and VIDEO_ADR_CNT0_clk_ctrl='1' then + if VIDEO_ADR_CNT0_ena_ctrl='1' then VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; i_vbasx : work.flexbus_register - GENERIC MAP + generic map ( reg_width => 2, match_address => x"ffff8603", match_mask => x"0000ffff", -- byte register match_fbcs => 1 ) - PORT MAP + port map ( clk => clk33m, fb_addr => fb_adr, @@ -601,14 +601,14 @@ BEGIN ); i_vbash : work.flexbus_register - GENERIC MAP + generic map ( reg_width => 8, match_address => x"ffff8604", match_mask => x"0000fffe", -- byte register match_fbcs => 1 ) - PORT MAP + port map ( clk => clk33m, fb_addr => fb_adr, @@ -626,106 +626,106 @@ BEGIN -- BYT SELECT -- ADR==0 -- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 DOWNTO 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- FB_REGDDR_0_clk_ctrl <= MAIN_CLK; - PROCESS (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) - VARIABLE stdVec3: std_logic_vector(2 DOWNTO 0); - BEGIN + process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) + variable stdVec3: std_logic_vector(2 downto 0); + begin FB_REGDDR_d <= FB_REGDDR_q; - fb_vdoe <= (OTHERS => '0'); - fb_le <= (OTHERS => '0'); + fb_vdoe <= (others => '0'); + fb_le <= (others => '0'); video_ddr_ta <= '0'; bus_cyc_end <= '0'; stdVec3 := FB_REGDDR_q; - CASE stdVec3 IS - WHEN "000" => + case stdVec3 is + when "000" => FB_LE(0) <= not nFB_WR; -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - IF (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' THEN + if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' then FB_REGDDR_d <= "001"; - ELSE + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "001" => - IF DDR_CS_q = '1' THEN + when "001" => + if DDR_CS_q = '1' then FB_LE(0) <= not nFB_WR; VIDEO_DDR_TA <= vcc; - IF LINE ='1' THEN + if LINE ='1' then FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); FB_REGDDR_d <= "010"; - ELSE + else BUS_CYC_END <= vcc; FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_REGDDR_d <= "000"; - END IF; - ELSE + end if; + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "010" => - IF DDR_CS_q = '1' THEN + when "010" => + if DDR_CS_q = '1' then FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(1) <= not nFB_WR; VIDEO_DDR_TA <= vcc; FB_REGDDR_d <= "011"; - ELSE + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "011" => - IF DDR_CS_q ='1' THEN + when "011" => + if DDR_CS_q ='1' then FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(2) <= not nFB_WR; -- BEI LINE WRITE EVT. WARTEN - IF ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' THEN + if ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' then FB_REGDDR_d <= "011"; - ELSE + else VIDEO_DDR_TA <= vcc; FB_REGDDR_d <= "100"; - END IF; - ELSE + end if; + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN "100" => - IF DDR_CS_q = '1' THEN + when "100" => + if DDR_CS_q = '1' then FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_LE(3) <= not nFB_WR; VIDEO_DDR_TA <= vcc; BUS_CYC_END <= vcc; FB_REGDDR_d <= "000"; - ELSE + else FB_REGDDR_d <= "000"; - END IF; + end if; - WHEN others => - END CASE; - stdVec3 := (OTHERS => '0'); -- no storage needed - END PROCESS; + when others => + end case; + stdVec3 := (others => '0'); -- no storage needed + end process; -- DDR STEUERUNG ----------------------------------------------------- - -- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; VCKE <= VIDEO_RAM_CTR(0); nVCS <= not VIDEO_RAM_CTR(1); DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); @@ -733,9 +733,9 @@ BEGIN FIFO_ACTIVE <= VIDEO_RAM_CTR(8); -- ------------------------------ - CPU_ROW_ADR <= FB_ADR(26 DOWNTO 14); - CPU_BA <= FB_ADR(13 DOWNTO 12); - CPU_COL_ADR <= FB_ADR(11 DOWNTO 2); + CPU_ROW_ADR <= FB_ADR(26 downto 14); + CPU_BA <= FB_ADR(13 downto 12); + CPU_COL_ADR <= FB_ADR(11 downto 2); nVRAS <= not VRAS; nVCAS <= not VCAS; nVWE <= not VWE; @@ -751,7 +751,7 @@ BEGIN DDRWR_D_SEL1 <= BLITTER_AC_q; -- SELECT LOGIC - DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 DOWNTO 30) = "01"); + DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); DDR_CS_clk <= MAIN_CLK; DDR_CS_ena <= FB_ALE; DDR_CS_d <= DDR_SEL; @@ -792,15 +792,15 @@ BEGIN DDR_SM_0_clk_ctrl <= DDRCLK0; - PROCESS (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, + process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, VIDEO_ADR_CNT_q, FIFO_COL_ADR, gnd, DDR_SEL, LINE, FIFO_BA, VA_P_q, BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, DDR_REFRESH_SIG_q, vcc) - VARIABLE stdVec6: std_logic_vector(5 DOWNTO 0); - BEGIN + variable stdVec6: std_logic_vector(5 downto 0); + begin DDR_SM_d <= DDR_SM_q; BA_S_d <= "00"; VA_S_d <= "0000000000000"; @@ -809,7 +809,7 @@ BEGIN VA_P_d(3), VA_P_d(2), VA_P_d(1), VA_P_d(0), VA_P_d(10)) <= std_logic_vector'("00000000000"); SR_VDMP_d <= "00000000"; - VA_P_d(12 DOWNTO 11) <= "00"; + VA_P_d(12 downto 11) <= "00"; (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, @@ -818,54 +818,54 @@ BEGIN std_logic_vector'("00000000000000000000000000000"); stdVec6 := DDR_SM_q; - CASE stdVec6 IS - WHEN "000000" => - IF (DDR_REFRESH_REQ_q)='1' THEN + case stdVec6 is + when "000000" => + if (DDR_REFRESH_REQ_q)='1' then DDR_SM_d <= "011111"; -- SYNCHRON UND EIN? - ELSIF (CPU_DDR_SYNC_q)='1' THEN + elsif (CPU_DDR_SYNC_q)='1' then -- JA - IF (DDR_CONFIG)='1' THEN + if (DDR_CONFIG)='1' then DDR_SM_d <= "001000"; -- BEI WAIT UND LINE WRITE - ELSIF (CPU_REQ_q)='1' THEN + elsif (CPU_REQ_q)='1' then VA_S_d <= CPU_ROW_ADR; BA_S_d <= CPU_BA; CPU_AC_d <= vcc; BUS_CYC_d_2 <= vcc; DDR_SM_d <= "000010"; - ELSE + else -- FIFO IST DEFAULT - IF (FIFO_REQ_q or (not BLITTER_REQ_q))='1' THEN + if (FIFO_REQ_q or (not BLITTER_REQ_q))='1' then VA_P_d <= FIFO_ROW_ADR; BA_P_d <= FIFO_BA; -- VORBESETZEN FIFO_AC_d <= vcc; - ELSE + else VA_P_d <= BLITTER_ROW_ADR; BA_P_d <= BLITTER_BA; -- VORBESETZEN BLITTER_AC_d <= vcc; - END IF; + end if; DDR_SM_d <= "000001"; - END IF; - ELSE + end if; + else -- NEIN ->SYNCHRONISIEREN DDR_SM_d <= "000000"; - END IF; + end if; - WHEN "000001" => + when "000001" => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - IF (DDR_SEL and (nFB_WR or (not LINE)))='1' THEN + if (DDR_SEL and (nFB_WR or (not LINE)))='1' then VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); - (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); + (BA1_2, BA0_2) <= FB_AD(13 downto 12); -- AUTO PRECHARGE DA NICHT FIFO PAGE VA_S_d(10) <= vcc; CPU_AC_d <= vcc; -- BUS CYCLUS LOSTRETEN BUS_CYC_d_2 <= vcc; - ELSE + else VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; (BA1_2, BA0_2) <= BA_P_q; @@ -873,10 +873,10 @@ BEGIN FIFO_BANK_OK_d_1 <= FIFO_AC_q and FIFO_REQ_q; FIFO_AC_d <= FIFO_AC_q and FIFO_REQ_q; BLITTER_AC_d <= BLITTER_AC_q and BLITTER_REQ_q; - END IF; + end if; DDR_SM_d <= "000011"; - WHEN "000010" => + when "000010" => VRAS <= vcc; FIFO_BANK_NOT_OK <= vcc; CPU_AC_d <= vcc; @@ -885,36 +885,36 @@ BEGIN BUS_CYC_d_2 <= vcc; DDR_SM_d <= "000011"; - WHEN "000011" => + when "000011" => CPU_AC_d <= CPU_AC_q; FIFO_AC_d <= FIFO_AC_q; BLITTER_AC_d <= BLITTER_AC_q; -- AUTO PRECHARGE WENN NICHT FIFO PAGE VA_S_d(10) <= VA_S_q(10); - IF (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' THEN + if (((not nFB_WR) and CPU_AC_q) or (BLITTER_WR and BLITTER_AC_q))='1' then DDR_SM_d <= "010000"; -- CPU? - ELSIF (CPU_AC_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= CPU_COL_ADR; + elsif (CPU_AC_q)='1' then + VA_S_d(9 downto 0) <= CPU_COL_ADR; BA_S_d <= CPU_BA; DDR_SM_d <= "001110"; -- FIFO? - ELSIF (FIFO_AC_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + elsif (FIFO_AC_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; BA_S_d <= FIFO_BA; DDR_SM_d <= "010110"; - ELSIF (BLITTER_AC_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= BLITTER_COL_ADR; + elsif (BLITTER_AC_q)='1' then + VA_S_d(9 downto 0) <= BLITTER_COL_ADR; BA_S_d <= BLITTER_BA; DDR_SM_d <= "001110"; - ELSE + else -- READ DDR_SM_d <= "000111"; - END IF; + end if; - WHEN "001110" => + when "001110" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; VCAS <= vcc; @@ -926,26 +926,26 @@ BEGIN SR_BLITTER_DACK <= BLITTER_AC_q; DDR_SM_d <= "001111"; - WHEN "001111" => + when "001111" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; -- FIFO READ EINSCHIEBEN WENN BANK OK - IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; -- MANUELL PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; - ELSE + else -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- WRITE DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "010000" => + when "010000" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; @@ -956,29 +956,29 @@ BEGIN VA_S_d(10) <= VA_S_q(10); DDR_SM_d <= "010001"; - WHEN "010001" => + when "010001" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - VA_S_d(9 DOWNTO 0) <= (sizeIt(CPU_AC_q, 10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q, 10) and BLITTER_COL_ADR); + VA_S_d(9 downto 0) <= (sizeIt(CPU_AC_q, 10) and CPU_COL_ADR) or (sizeIt(BLITTER_AC_q, 10) and BLITTER_COL_ADR); -- AUTO PRECHARGE WENN NICHT FIFO PAGE VA_S_d(10) <= VA_S_q(10); BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); -- BYTE ENABLE WRITE - SR_VDMP_d(7 DOWNTO 4) <= FB_B; + SR_VDMP_d(7 downto 4) <= FB_B; -- LINE ENABLE WRITE - SR_VDMP_d(3 DOWNTO 0) <= sizeIt(LINE,4) and "1111"; + SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; DDR_SM_d <= "010010"; - WHEN "010010" => + when "010010" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; VCAS <= vcc; VWE <= vcc; - -- WRITE COMMAND CPU UND BLITTER IF WRITER + -- WRITE COMMAND CPU UND BLITTER if WRITER SR_DDR_WR_d <= vcc; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN @@ -988,160 +988,160 @@ BEGIN SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; DDR_SM_d <= "010011"; - WHEN "010011" => + when "010011" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - -- WRITE COMMAND CPU UND BLITTER IF WRITE + -- WRITE COMMAND CPU UND BLITTER if WRITE SR_DDR_WR_d <= vcc; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL_d <= vcc; DDR_SM_d <= "010100"; - WHEN "010100" => + when "010100" => DDR_SM_d <= "010101"; - WHEN "010101" => - IF (FIFO_REQ_q and FIFO_BANK_OK_q)='1' THEN - VA_S_d(9 DOWNTO 0) <= FIFO_COL_ADR; + when "010101" => + if (FIFO_REQ_q and FIFO_BANK_OK_q)='1' then + VA_S_d(9 downto 0) <= FIFO_COL_ADR; -- NON AUTO PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; - ELSE + else -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- FIFO READ DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "010110" => + when "010110" => VCAS <= vcc; -- DATEN WRITE FIFO SR_FIFO_WRE_d <= vcc; DDR_SM_d <= "010111"; - WHEN "010111" => - IF (FIFO_REQ_q)='1' THEN + when "010111" => + if (FIFO_REQ_q)='1' then -- NEUE PAGE? - IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; - ELSE - VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + else + VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; - END IF; - ELSE + end if; + else -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- NOCH OFFEN LASSEN DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "011000" => + when "011000" => VCAS <= vcc; -- DATEN WRITE FIFO SR_FIFO_WRE_d <= vcc; DDR_SM_d <= "011001"; - WHEN "011001" => - IF CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) THEN + when "011001" => + if CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) then -- ALLE PAGES SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; - ELSIF (FIFO_REQ_q)='1' THEN + elsif (FIFO_REQ_q)='1' then -- NEUE PAGE? - IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE PAGES SCHLIESSEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; - ELSE - VA_S_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + else + VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE VA_S_d(10) <= gnd; BA_S_d <= FIFO_BA; DDR_SM_d <= "011010"; - END IF; - ELSE + end if; + else -- ALLE PAGES SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; - END IF; + end if; - WHEN "011010" => + when "011010" => VCAS <= vcc; -- DATEN WRITE FIFO SR_FIFO_WRE_d <= vcc; -- NOTFALL? - IF (unsigned(FIFO_MW) < unsigned'("000000000")) THEN + if (unsigned(FIFO_MW) < unsigned'("000000000")) then -- JA-> DDR_SM_d <= "010111"; - ELSE + else DDR_SM_d <= "011011"; - END IF; + end if; - WHEN "011011" => - IF (FIFO_REQ_q)='1' THEN + when "011011" => + if (FIFO_REQ_q)='1' then -- NEUE PAGE? - IF VIDEO_ADR_CNT_q(7 DOWNTO 0) = "11111111" THEN + if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE BANKS SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; - ELSE - VA_P_d(9 DOWNTO 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); + else + VA_P_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE VA_P_d(10) <= gnd; BA_P_d <= FIFO_BA; DDR_SM_d <= "011100"; - END IF; - ELSE + end if; + else -- ALLE BANKS SCHLIESEN VA_S_d(10) <= vcc; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; - END IF; + end if; - WHEN "011100" => - IF (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 DOWNTO 12) /= FIFO_BA THEN + when "011100" => + if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then VRAS <= vcc; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 DOWNTO 14); - (BA1_2, BA0_2) <= FB_AD(13 DOWNTO 12); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); + (BA1_2, BA0_2) <= FB_AD(13 downto 12); CPU_AC_d <= vcc; -- BUS CYCLUS LOSTRETEN @@ -1150,7 +1150,7 @@ BEGIN -- AUTO PRECHARGE DA NICHT FIFO BANK VA_S_d(10) <= vcc; DDR_SM_d <= "000011"; - ELSE + else VCAS <= vcc; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; (BA1_2, BA0_2) <= BA_P_q; @@ -1160,31 +1160,31 @@ BEGIN -- CONFIG CYCLUS DDR_SM_d <= "011001"; - END IF; + end if; - WHEN "001000" => + when "001000" => DDR_SM_d <= "001001"; - WHEN "001001" => + when "001001" => BUS_CYC_d_2 <= CPU_REQ_q; DDR_SM_d <= "001010"; - WHEN "001010" => - IF (CPU_REQ_q)='1' THEN + when "001010" => + if (CPU_REQ_q)='1' then DDR_SM_d <= "001011"; - ELSE + else DDR_SM_d <= "000000"; - END IF; + end if; - WHEN "001011" => + when "001011" => DDR_SM_d <= "001100"; - WHEN "001100" => - VA_S_d <= FB_AD(12 DOWNTO 0); - BA_S_d <= FB_AD(14 DOWNTO 13); + when "001100" => + VA_S_d <= FB_AD(12 downto 0); + BA_S_d <= FB_AD(14 downto 13); DDR_SM_d <= "001101"; - WHEN "001101" => + when "001101" => -- NUR BEI LONG WRITE VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); @@ -1198,7 +1198,7 @@ BEGIN -- CLOSE FIFO BANK DDR_SM_d <= "000111"; - WHEN "011101" => + when "011101" => -- AUF NOT OK FIFO_BANK_NOT_OK <= vcc; @@ -1208,7 +1208,7 @@ BEGIN VWE <= vcc; DDR_SM_d <= "000110"; - WHEN "011110" => + when "011110" => -- AUF NOT OK FIFO_BANK_NOT_OK <= vcc; @@ -1219,10 +1219,10 @@ BEGIN -- REFRESH 70NS = 10 ZYCLEN DDR_SM_d <= "000000"; - WHEN "011111" => + when "011111" => -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - IF DDR_REFRESH_SIG_q = "1001" THEN + if DDR_REFRESH_SIG_q = "1001" then -- ALLE BANKS SCHLIESSEN VRAS <= vcc; @@ -1230,51 +1230,51 @@ BEGIN VA10_2 <= vcc; FIFO_BANK_NOT_OK <= vcc; DDR_SM_d <= "100001"; - ELSE + else VCAS <= vcc; VRAS <= vcc; DDR_SM_d <= "100000"; - END IF; + end if; - WHEN "100000" => + when "100000" => DDR_SM_d <= "100001"; - WHEN "100001" => + when "100001" => DDR_SM_d <= "100010"; - WHEN "100010" => + when "100010" => DDR_SM_d <= "100011"; - WHEN "100011" => + when "100011" => -- LEERSCHLAUFE DDR_SM_d <= "000100"; - WHEN "000100" => + when "000100" => DDR_SM_d <= "000101"; - WHEN "000101" => + when "000101" => DDR_SM_d <= "000110"; - WHEN "000110" => + when "000110" => DDR_SM_d <= "000111"; - WHEN "000111" => + when "000111" => DDR_SM_d <= "000000"; - WHEN OTHERS => - END CASE; - stdVec6 := (OTHERS => '0'); -- no storage needed - END PROCESS; + when others => + end case; + stdVec6 := (others => '0'); -- no storage needed + end process; -- ------------------------------------------------------------- -- BLITTER ---------------------- -- --------------------------------------- BLITTER_REQ_clk <= DDRCLK0; BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); - BLITTER_ROW_ADR <= BLITTER_ADR(26 DOWNTO 14); + BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); BLITTER_BA(1) <= BLITTER_ADR(13); BLITTER_BA(0) <= BLITTER_ADR(12); - BLITTER_COL_ADR <= BLITTER_ADR(11 DOWNTO 2); + BLITTER_COL_ADR <= BLITTER_ADR(11 downto 2); -- ---------------------------------------------------------------------------- -- FIFO --------------------------------- @@ -1284,7 +1284,7 @@ BEGIN (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); - FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 DOWNTO 10); + FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); FIFO_COL_ADR <= std_logic_vector'(VIDEO_ADR_CNT_q(7) & VIDEO_ADR_CNT_q(6) & @@ -1311,16 +1311,16 @@ BEGIN (std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) + unsigned'("00000000000000000000001")))); - VIDEO_BASE_ADR(22 DOWNTO 20) <= VIDEO_BASE_X_D_q; - VIDEO_BASE_ADR(19 DOWNTO 12) <= VIDEO_BASE_H_D_q; - VIDEO_BASE_ADR(11 DOWNTO 4) <= VIDEO_BASE_M_D_q; - VIDEO_BASE_ADR(3 DOWNTO 0) <= VIDEO_BASE_L_D_q(7 DOWNTO 4); - VDM_SEL <= VIDEO_BASE_L_D_q(3 DOWNTO 0); + VIDEO_BASE_ADR(22 downto 20) <= VIDEO_BASE_X_D_q; + VIDEO_BASE_ADR(19 downto 12) <= VIDEO_BASE_H_D_q; + VIDEO_BASE_ADR(11 downto 4) <= VIDEO_BASE_M_D_q; + VIDEO_BASE_ADR(3 downto 0) <= VIDEO_BASE_L_D_q(7 downto 4); + VDM_SEL <= VIDEO_BASE_L_D_q(3 downto 0); -- AKTUELLE VIDEO ADRESSE - VIDEO_ACT_ADR(26 DOWNTO 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - + VIDEO_ACT_ADR(26 downto 4) <= std_logic_vector'(unsigned(VIDEO_ADR_CNT_q) - unsigned(std_logic_vector'("00000000000000" & FIFO_MW))); - VIDEO_ACT_ADR(3 DOWNTO 0) <= VDM_SEL; + VIDEO_ACT_ADR(3 downto 0) <= VDM_SEL; -- --------------------------------------------------------------------------------------- -- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS @@ -1352,53 +1352,53 @@ BEGIN VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; -- 820D/2 - VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000110"); + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000110"); -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; -- 8203/2 - VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000001"); - VIDEO_BASE_M_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000001"); + VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; -- 8200-1/2 - VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000000"); - VIDEO_BASE_H_D_d <= FB_AD(23 DOWNTO 16); + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000"); + VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; - VIDEO_BASE_X_D_d <= FB_AD(26 DOWNTO 24); + VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); -- 8209/2 - VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000100"); + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000100"); -- 8207/2 - VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000011"); + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000011"); -- 8204,5/2 - VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100000100000010"); + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000010"); -- FB_AD[31..24] = lpm_bustri_BYT( -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) -- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), -- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - fb_ad(31 DOWNTO 24) <= "00000" & video_base_x_d_d WHEN video_base_h and not nfb_oe ELSE - "00000" & video_act_adr(26 DOWNTO 24) WHEN video_cnt_h and not nfb_oe ELSE - (OTHERS => 'Z'); + fb_ad(31 downto 24) <= "00000" & video_base_x_d_d when video_base_h and not nfb_oe else + "00000" & video_act_adr(26 downto 24) when video_cnt_h and not nfb_oe else + (others => 'Z'); u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or - (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 DOWNTO 0)) or - (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 DOWNTO 8)) or - (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 DOWNTO 16)); + (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or + (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or + (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - FB_AD(23 DOWNTO 16) <= u0_tridata; + FB_AD(23 downto 16) <= u0_tridata; -- Assignments added to explicitly combine the @@ -1421,7 +1421,7 @@ BEGIN VA(11) <= VA11_1 or VA11_2; VA(12) <= VA12_1 or VA12_2; --- Define power SIGNAL(s) +-- Define power signal(s) vcc <= '1'; gnd <= '0'; -END ARCHITECTURE rtl; +end architecture rtl; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index a7a6b00..a98c78a 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -52,67 +52,68 @@ -- CREATED BY FREDI ASCHWANDEN -- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! -LIBRARY ieee; - USE ieee.std_logic_1164.all; - USE ieee.numeric_std.all; -ENTITY video_mod_mux_clutctr IS - PORT +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +entity video_mod_mux_clutctr is + port ( - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - FB_ADR : IN std_logic_vector(31 downto 0); - CLK33M : IN std_logic; - CLK25M : IN std_logic; - BLITTER_RUN : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_D : IN std_logic_vector(8 downto 0); - VR_BUSY : IN std_logic; - COLOR8 : OUT std_logic; - ACP_CLUT_RD : OUT std_logic; - COLOR1 : OUT std_logic; - FALCON_CLUT_RDH : OUT std_logic; - FALCON_CLUT_RDL : OUT std_logic; - FALCON_CLUT_WR : OUT std_logic_vector(3 downto 0); - ST_CLUT_RD : OUT std_logic; - ST_CLUT_WR : OUT std_logic_vector(1 downto 0); - CLUT_MUX_ADR : OUT std_logic_vector(3 downto 0); - HSYNC : OUT std_logic; - VSYNC : OUT std_logic; - nBLANK : OUT std_logic; - nSYNC : OUT std_logic; - nPD_VGA : OUT std_logic; - FIFO_RDE : OUT std_logic; - COLOR2 : OUT std_logic; - color4 : OUT std_logic; - PIXEL_CLK : OUT std_logic; - CLUT_OFF : OUT std_logic_vector(3 downto 0); - BLITTER_ON : OUT std_logic; - VIDEO_RAM_CTR : OUT std_logic_vector(15 downto 0); - VIDEO_MOD_TA : OUT std_logic; - BORDER_COLOR : OUT std_logic_vector(23 downto 0); - CCSEL : OUT std_logic_vector(2 downto 0); - ACP_CLUT_WR : OUT std_logic_vector(3 downto 0); - INTER_ZEI : OUT std_logic; - DOP_FIFO_CLR : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - CLR_FIFO : OUT std_logic; - FB_AD : OUT std_logic_vector(31 downto 0) + nRSTO : in std_logic; + MAIN_CLK : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_WR : in std_logic; + nFB_OE : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + CLK33M : in std_logic; + CLK25M : in std_logic; + BLITTER_RUN : in std_logic; + CLK_VIDEO : in std_logic; + VR_D : in std_logic_vector(8 downto 0); + VR_BUSY : in std_logic; + COLOR8 : out std_logic; + ACP_CLUT_RD : out std_logic; + COLOR1 : out std_logic; + FALCON_CLUT_RDH : out std_logic; + FALCON_CLUT_RDL : out std_logic; + FALCON_CLUT_WR : out std_logic_vector(3 downto 0); + ST_CLUT_RD : out std_logic; + ST_CLUT_WR : out std_logic_vector(1 downto 0); + CLUT_MUX_ADR : out std_logic_vector(3 downto 0); + HSYNC : out std_logic; + VSYNC : out std_logic; + nBLANK : out std_logic; + nSYNC : out std_logic; + nPD_VGA : out std_logic; + FIFO_RDE : out std_logic; + COLOR2 : out std_logic; + color4 : out std_logic; + PIXEL_CLK : out std_logic; + CLUT_OFF : out std_logic_vector(3 downto 0); + BLITTER_ON : out std_logic; + VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); + VIDEO_MOD_TA : out std_logic; + BORDER_COLOR : out std_logic_vector(23 downto 0); + CCSEL : out std_logic_vector(2 downto 0); + ACP_CLUT_WR : out std_logic_vector(3 downto 0); + INTER_ZEI : out std_logic; + DOP_FIFO_CLR : out std_logic; + VIDEO_RECONFIG : out std_logic; + VR_WR : out std_logic; + VR_RD : out std_logic; + CLR_FIFO : out std_logic; + FB_AD : out std_logic_vector(31 downto 0) ); -END video_mod_mux_clutctr; +end video_mod_mux_clutctr; -ARCHITECTURE rtl OF video_mod_mux_clutctr IS +architecture rtl of video_mod_mux_clutctr is -- DIV. CONTROL REGISTER -- BRAUCHT EIN WAITSTAT -- LÄNGE HSYNC PULS IN PIXEL_CLK @@ -124,398 +125,387 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS -- VERTIKAL TIMING 320x240 -- HORIZONTAL -- VERTIKAL - SIGNAL VR_DOUT : std_logic_vector(8 downto 0); - SIGNAL VR_DOUT_d : std_logic_vector(8 downto 0); - SIGNAL VR_DOUT_q : std_logic_vector(8 downto 0); - SIGNAL VR_FRQ : unsigned(7 downto 0); - SIGNAL VR_FRQ_d : std_logic_vector(7 downto 0); - SIGNAL VR_FRQ_q : std_logic_vector(7 downto 0); - SIGNAL FB_B : std_logic_vector(3 downto 0); - SIGNAL FB_16B : std_logic_vector(1 downto 0); - SIGNAL ST_SHIFT_MODE : std_logic_vector(1 downto 0); - SIGNAL ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); - SIGNAL ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); - SIGNAL FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); - SIGNAL FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); - SIGNAL FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); - SIGNAL CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV1 : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV0 : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); - SIGNAL CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); - SIGNAL ACP_VCTR : std_logic_vector(31 downto 0); - SIGNAL ACP_VCTR_d : std_logic_vector(31 downto 0); - SIGNAL ACP_VCTR_q : std_logic_vector(31 downto 0); - SIGNAL BORDER_COLOR_d : std_logic_vector(23 downto 0); - SIGNAL BORDER_COLOR_q : std_logic_vector(23 downto 0); - SIGNAL SYS_CTR : std_logic_vector(6 downto 0); - SIGNAL SYS_CTR_d : std_logic_vector(6 downto 0); - SIGNAL SYS_CTR_q : std_logic_vector(6 downto 0); - SIGNAL LOF : std_logic_vector(15 downto 0); - SIGNAL LOF_d : std_logic_vector(15 downto 0); - SIGNAL LOF_q : std_logic_vector(15 downto 0); - SIGNAL LWD : std_logic_vector(15 downto 0); - SIGNAL LWD_d : std_logic_vector(15 downto 0); - SIGNAL LWD_q : std_logic_vector(15 downto 0); - SIGNAL HSYNC_I : std_logic_vector(7 downto 0); - SIGNAL HSYNC_I_d : std_logic_vector(7 downto 0); - SIGNAL HSYNC_I_q : std_logic_vector(7 downto 0); - SIGNAL HSY_LEN : std_logic_vector(7 downto 0); - SIGNAL HSY_LEN_d : std_logic_vector(7 downto 0); - SIGNAL HSY_LEN_q : std_logic_vector(7 downto 0); - SIGNAL VSYNC_I : std_logic_vector(2 downto 0); - SIGNAL VSYNC_I_d : std_logic_vector(2 downto 0); - SIGNAL VSYNC_I_q : std_logic_vector(2 downto 0); - SIGNAL VHCNT : std_logic_vector(11 downto 0); - SIGNAL VHCNT_d : std_logic_vector(11 downto 0); - SIGNAL VHCNT_q : std_logic_vector(11 downto 0); - SIGNAL SUB_PIXEL_CNT : std_logic_vector(6 downto 0); - SIGNAL SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); - SIGNAL SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); - SIGNAL VVCNT : std_logic_vector(10 downto 0); - SIGNAL VVCNT_d : std_logic_vector(10 downto 0); - SIGNAL VVCNT_q : std_logic_vector(10 downto 0); - SIGNAL VERZ2 : std_logic_vector(9 downto 0); - SIGNAL VERZ2_d : std_logic_vector(9 downto 0); - SIGNAL VERZ2_q : std_logic_vector(9 downto 0); - SIGNAL VERZ1 : std_logic_vector(9 downto 0); - SIGNAL VERZ1_d : std_logic_vector(9 downto 0); - SIGNAL VERZ1_q : std_logic_vector(9 downto 0); - SIGNAL VERZ0 : std_logic_vector(9 downto 0); - SIGNAL VERZ0_d : std_logic_vector(9 downto 0); - SIGNAL VERZ0_q : std_logic_vector(9 downto 0); - SIGNAL RAND : std_logic_vector(6 downto 0) := (OTHERS => '0'); - SIGNAL RAND_d : std_logic_vector(6 downto 0); - SIGNAL RAND_q : std_logic_vector(6 downto 0); - SIGNAL CCSEL_d : std_logic_vector(2 downto 0); - SIGNAL CCSEL_q : std_logic_vector(2 downto 0); - SIGNAL ATARI_HH : std_logic_vector(31 downto 0) := (OTHERS => '0'); - SIGNAL ATARI_HH_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_HH_q : std_logic_vector(31 downto 0); - SIGNAL ATARI_VH : std_logic_vector(31 downto 0); - SIGNAL ATARI_VH_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_VH_q : std_logic_vector(31 downto 0); - SIGNAL ATARI_HL : std_logic_vector(31 downto 0) := (OTHERS => '0'); - SIGNAL ATARI_HL_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_HL_q : std_logic_vector(31 downto 0); - SIGNAL ATARI_VL : std_logic_vector(31 downto 0); - SIGNAL ATARI_VL_d : std_logic_vector(31 downto 0); - SIGNAL ATARI_VL_q : std_logic_vector(31 downto 0); - SIGNAL RAND_LINKS : std_logic_vector(11 downto 0); - SIGNAL HDIS_START : std_logic_vector(11 downto 0); - SIGNAL HDIS_END : std_logic_vector(11 downto 0); - SIGNAL RAND_RECHTS : std_logic_vector(11 downto 0); - SIGNAL HS_START : std_logic_vector(11 downto 0); - SIGNAL H_TOTAL : std_logic_vector(11 downto 0); - SIGNAL HDIS_LEN : std_logic_vector(11 downto 0); - SIGNAL MULF : std_logic_vector(5 downto 0); - SIGNAL HHT : std_logic_vector(11 downto 0) := (OTHERS => '0'); - SIGNAL HHT_d : std_logic_vector(11 downto 0); - SIGNAL HHT_q : std_logic_vector(11 downto 0); - SIGNAL HBE : std_logic_vector(11 downto 0) := (OTHERS => '0'); - SIGNAL HBE_d : std_logic_vector(11 downto 0); - SIGNAL HBE_q : std_logic_vector(11 downto 0); - SIGNAL HDB : std_logic_vector(11 downto 0); - SIGNAL HDB_d : std_logic_vector(11 downto 0); - SIGNAL HDB_q : std_logic_vector(11 downto 0); - SIGNAL HDE : std_logic_vector(11 downto 0); - SIGNAL HDE_d : std_logic_vector(11 downto 0); - SIGNAL HDE_q : std_logic_vector(11 downto 0); - SIGNAL HBB : std_logic_vector(11 downto 0); - SIGNAL HBB_d : std_logic_vector(11 downto 0); - SIGNAL HBB_q : std_logic_vector(11 downto 0); - SIGNAL HSS : std_logic_vector(11 downto 0) := (OTHERS => '0'); - SIGNAL HSS_d : std_logic_vector(11 downto 0); - SIGNAL HSS_q : std_logic_vector(11 downto 0); - SIGNAL RAND_OBEN : std_logic_vector(10 downto 0); - SIGNAL VDIS_START : std_logic_vector(10 downto 0); - SIGNAL VDIS_END : std_logic_vector(10 downto 0); - SIGNAL RAND_UNTEN : std_logic_vector(10 downto 0); - SIGNAL VS_START : std_logic_vector(10 downto 0); - SIGNAL V_TOTAL : std_logic_vector(10 downto 0); - SIGNAL VBE : std_logic_vector(10 downto 0); - SIGNAL VBE_d : std_logic_vector(10 downto 0); - SIGNAL VBE_q : std_logic_vector(10 downto 0); - SIGNAL VDB : std_logic_vector(10 downto 0); - SIGNAL VDB_d : std_logic_vector(10 downto 0); - SIGNAL VDB_q : std_logic_vector(10 downto 0); - SIGNAL VDE : std_logic_vector(10 downto 0); - SIGNAL VDE_d : std_logic_vector(10 downto 0); - SIGNAL VDE_q : std_logic_vector(10 downto 0); - SIGNAL VBB : std_logic_vector(10 downto 0); - SIGNAL VBB_d : std_logic_vector(10 downto 0); - SIGNAL VBB_q : std_logic_vector(10 downto 0); - SIGNAL VSS : std_logic_vector(10 downto 0); - SIGNAL VSS_d : std_logic_vector(10 downto 0); - SIGNAL VSS_q : std_logic_vector(10 downto 0); - SIGNAL VFT : std_logic_vector(10 downto 0); - SIGNAL VFT_d : std_logic_vector(10 downto 0); - SIGNAL VFT_q : std_logic_vector(10 downto 0); - SIGNAL VCO : std_logic_vector(8 downto 0); - SIGNAL VCO_d : std_logic_vector(8 downto 0); - SIGNAL VCO_ena : std_logic_vector(8 downto 0); - SIGNAL VCO_q : std_logic_vector(8 downto 0); - SIGNAL VCNTRL : std_logic_vector(3 downto 0) := (OTHERS => '0'); - SIGNAL VCNTRL_d : std_logic_vector(3 downto 0); - SIGNAL VCNTRL_q : std_logic_vector(3 downto 0); - SIGNAL u0_data : std_logic_vector(15 downto 0); - SIGNAL u0_tridata : std_logic_vector(15 downto 0); - SIGNAL u1_data : std_logic_vector(15 downto 0); - SIGNAL u1_tridata : std_logic_vector(15 downto 0); - -- SIGNAL ST_SHIFT_MODE0_clk_ctrl : std_logic; - SIGNAL ST_SHIFT_MODE0_ena_ctrl : std_logic; - -- SIGNAL FALCON_SHIFT_MODE0_clk_ctrl : std_logic; - SIGNAL FALCON_SHIFT_MODE8_ena_ctrl : std_logic; - SIGNAL FALCON_SHIFT_MODE0_ena_ctrl : std_logic; + signal VR_DOUT : std_logic_vector(8 downto 0); + signal VR_DOUT_d : std_logic_vector(8 downto 0); + signal VR_DOUT_q : std_logic_vector(8 downto 0); + signal VR_FRQ : unsigned(7 downto 0); + signal VR_FRQ_d : std_logic_vector(7 downto 0); + signal VR_FRQ_q : std_logic_vector(7 downto 0); + signal FB_B : std_logic_vector(3 downto 0); + signal FB_16B : std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE : std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); + signal ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); + signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); + signal FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); + signal FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); + signal CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); + signal CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1 : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0 : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); + signal CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); + signal ACP_VCTR : std_logic_vector(31 downto 0); + signal ACP_VCTR_d : std_logic_vector(31 downto 0); + signal ACP_VCTR_q : std_logic_vector(31 downto 0); + signal BORDER_COLOR_d : std_logic_vector(23 downto 0); + signal BORDER_COLOR_q : std_logic_vector(23 downto 0); + signal SYS_CTR : std_logic_vector(6 downto 0); + signal SYS_CTR_d : std_logic_vector(6 downto 0); + signal SYS_CTR_q : std_logic_vector(6 downto 0); + signal LOF : std_logic_vector(15 downto 0); + signal LOF_d : std_logic_vector(15 downto 0); + signal LOF_q : std_logic_vector(15 downto 0); + signal LWD : std_logic_vector(15 downto 0); + signal LWD_d : std_logic_vector(15 downto 0); + signal LWD_q : std_logic_vector(15 downto 0); + signal HSYNC_I : std_logic_vector(7 downto 0); + signal HSYNC_I_d : std_logic_vector(7 downto 0); + signal HSYNC_I_q : std_logic_vector(7 downto 0); + signal HSY_LEN : std_logic_vector(7 downto 0); + signal HSY_LEN_d : std_logic_vector(7 downto 0); + signal HSY_LEN_q : std_logic_vector(7 downto 0); + signal VSYNC_I : std_logic_vector(2 downto 0); + signal VSYNC_I_d : std_logic_vector(2 downto 0); + signal VSYNC_I_q : std_logic_vector(2 downto 0); + signal VHCNT : std_logic_vector(11 downto 0); + signal VHCNT_d : std_logic_vector(11 downto 0); + signal VHCNT_q : std_logic_vector(11 downto 0); + signal SUB_PIXEL_CNT : std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); + signal VVCNT : std_logic_vector(10 downto 0); + signal VVCNT_d : std_logic_vector(10 downto 0); + signal VVCNT_q : std_logic_vector(10 downto 0); + signal VERZ2 : std_logic_vector(9 downto 0); + signal VERZ2_d : std_logic_vector(9 downto 0); + signal VERZ2_q : std_logic_vector(9 downto 0); + signal VERZ1 : std_logic_vector(9 downto 0); + signal VERZ1_d : std_logic_vector(9 downto 0); + signal VERZ1_q : std_logic_vector(9 downto 0); + signal VERZ0 : std_logic_vector(9 downto 0); + signal VERZ0_d : std_logic_vector(9 downto 0); + signal VERZ0_q : std_logic_vector(9 downto 0); + signal RAND : std_logic_vector(6 downto 0) := (others => '0'); + signal RAND_d : std_logic_vector(6 downto 0); + signal RAND_q : std_logic_vector(6 downto 0); + signal CCSEL_d : std_logic_vector(2 downto 0); + signal CCSEL_q : std_logic_vector(2 downto 0); + signal ATARI_HH : std_logic_vector(31 downto 0) := (others => '0'); + signal ATARI_HH_d : std_logic_vector(31 downto 0); + signal ATARI_HH_q : std_logic_vector(31 downto 0); + signal ATARI_VH : std_logic_vector(31 downto 0); + signal ATARI_VH_d : std_logic_vector(31 downto 0); + signal ATARI_VH_q : std_logic_vector(31 downto 0); + signal ATARI_HL : std_logic_vector(31 downto 0) := (others => '0'); + signal ATARI_HL_d : std_logic_vector(31 downto 0); + signal ATARI_HL_q : std_logic_vector(31 downto 0); + signal ATARI_VL : std_logic_vector(31 downto 0); + signal ATARI_VL_d : std_logic_vector(31 downto 0); + signal ATARI_VL_q : std_logic_vector(31 downto 0); + signal RAND_LINKS : std_logic_vector(11 downto 0); + signal HDIS_START : std_logic_vector(11 downto 0); + signal HDIS_END : std_logic_vector(11 downto 0); + signal RAND_RECHTS : std_logic_vector(11 downto 0); + signal HS_START : std_logic_vector(11 downto 0); + signal H_TOTAL : std_logic_vector(11 downto 0); + signal HDIS_LEN : std_logic_vector(11 downto 0); + signal MULF : std_logic_vector(5 downto 0); + signal HHT : std_logic_vector(11 downto 0) := (others => '0'); + signal HHT_d : std_logic_vector(11 downto 0); + signal HHT_q : std_logic_vector(11 downto 0); + signal HBE : std_logic_vector(11 downto 0) := (others => '0'); + signal HBE_d : std_logic_vector(11 downto 0); + signal HBE_q : std_logic_vector(11 downto 0); + signal HDB : std_logic_vector(11 downto 0); + signal HDB_d : std_logic_vector(11 downto 0); + signal HDB_q : std_logic_vector(11 downto 0); + signal HDE : std_logic_vector(11 downto 0); + signal HDE_d : std_logic_vector(11 downto 0); + signal HDE_q : std_logic_vector(11 downto 0); + signal HBB : std_logic_vector(11 downto 0); + signal HBB_d : std_logic_vector(11 downto 0); + signal HBB_q : std_logic_vector(11 downto 0); + signal HSS : std_logic_vector(11 downto 0) := (others => '0'); + signal HSS_d : std_logic_vector(11 downto 0); + signal HSS_q : std_logic_vector(11 downto 0); + signal RAND_OBEN : std_logic_vector(10 downto 0); + signal VDIS_START : std_logic_vector(10 downto 0); + signal VDIS_END : std_logic_vector(10 downto 0); + signal RAND_UNTEN : std_logic_vector(10 downto 0); + signal VS_START : std_logic_vector(10 downto 0); + signal V_TOTAL : std_logic_vector(10 downto 0); + signal VBE : std_logic_vector(10 downto 0); + signal VBE_d : std_logic_vector(10 downto 0); + signal VBE_q : std_logic_vector(10 downto 0); + signal VDB : std_logic_vector(10 downto 0); + signal VDB_d : std_logic_vector(10 downto 0); + signal VDB_q : std_logic_vector(10 downto 0); + signal VDE : std_logic_vector(10 downto 0); + signal VDE_d : std_logic_vector(10 downto 0); + signal VDE_q : std_logic_vector(10 downto 0); + signal VBB : std_logic_vector(10 downto 0); + signal VBB_d : std_logic_vector(10 downto 0); + signal VBB_q : std_logic_vector(10 downto 0); + signal VSS : std_logic_vector(10 downto 0); + signal VSS_d : std_logic_vector(10 downto 0); + signal VSS_q : std_logic_vector(10 downto 0); + signal VFT : std_logic_vector(10 downto 0); + signal VFT_d : std_logic_vector(10 downto 0); + signal VFT_q : std_logic_vector(10 downto 0); + signal VCO : std_logic_vector(8 downto 0); + signal VCO_d : std_logic_vector(8 downto 0); + signal VCO_ena : std_logic_vector(8 downto 0); + signal VCO_q : std_logic_vector(8 downto 0); + signal VCNTRL : std_logic_vector(3 downto 0) := (others => '0'); + signal VCNTRL_d : std_logic_vector(3 downto 0); + signal VCNTRL_q : std_logic_vector(3 downto 0); + signal u0_data : std_logic_vector(15 downto 0); + signal u0_tridata : std_logic_vector(15 downto 0); + signal u1_data : std_logic_vector(15 downto 0); + signal u1_tridata : std_logic_vector(15 downto 0); + -- signal ST_SHIFT_MODE0_clk_ctrl : std_logic; + signal ST_SHIFT_MODE0_ena_ctrl : std_logic; + -- signal FALCON_SHIFT_MODE0_clk_ctrl : std_logic; + signal FALCON_SHIFT_MODE8_ena_ctrl : std_logic; + signal FALCON_SHIFT_MODE0_ena_ctrl : std_logic; - SIGNAL ACP_VCTR24_ena_ctrl : std_logic; - SIGNAL ACP_VCTR16_ena_ctrl : std_logic; - SIGNAL ACP_VCTR8_ena_ctrl : std_logic; - SIGNAL ACP_VCTR6_ena_ctrl : std_logic; - SIGNAL ACP_VCTR0_ena_ctrl : std_logic; + signal ACP_VCTR24_ena_ctrl : std_logic; + signal ACP_VCTR16_ena_ctrl : std_logic; + signal ACP_VCTR8_ena_ctrl : std_logic; + signal ACP_VCTR6_ena_ctrl : std_logic; + signal ACP_VCTR0_ena_ctrl : std_logic; - SIGNAL ATARI_HH24_ena_ctrl : std_logic; - SIGNAL ATARI_HH16_ena_ctrl : std_logic; - SIGNAL ATARI_HH8_ena_ctrl : std_logic; - SIGNAL ATARI_HH0_ena_ctrl : std_logic; - SIGNAL ATARI_VH24_ena_ctrl : std_logic; - SIGNAL ATARI_VH16_ena_ctrl : std_logic; - SIGNAL ATARI_VH8_ena_ctrl : std_logic; - SIGNAL ATARI_VH0_ena_ctrl : std_logic; - SIGNAL ATARI_HL24_ena_ctrl : std_logic; - SIGNAL ATARI_HL16_ena_ctrl : std_logic; - SIGNAL ATARI_HL8_ena_ctrl : std_logic; - SIGNAL ATARI_HL0_ena_ctrl : std_logic; - SIGNAL ATARI_VL0_clk_ctrl : std_logic; - SIGNAL ATARI_VL24_ena_ctrl : std_logic; - SIGNAL ATARI_VL16_ena_ctrl : std_logic; - SIGNAL ATARI_VL8_ena_ctrl : std_logic; - SIGNAL ATARI_VL0_ena_ctrl : std_logic; - SIGNAL VR_DOUT0_ena_ctrl : std_logic; - SIGNAL VR_FRQ0_ena_ctrl : std_logic; - SIGNAL BORDER_COLOR16_ena_ctrl : std_logic; - SIGNAL BORDER_COLOR8_ena_ctrl : std_logic; - SIGNAL BORDER_COLOR0_ena_ctrl : std_logic; - SIGNAL SYS_CTR0_ena_ctrl : std_logic; - SIGNAL LOF8_ena_ctrl : std_logic; - SIGNAL LOF0_ena_ctrl : std_logic; - SIGNAL LWD8_ena_ctrl : std_logic; - SIGNAL LWD0_ena_ctrl : std_logic; - SIGNAL HHT8_ena_ctrl : std_logic; - SIGNAL HHT0_ena_ctrl : std_logic; - SIGNAL HBE8_ena_ctrl : std_logic; - SIGNAL HBE0_ena_ctrl : std_logic; - SIGNAL HDB8_ena_ctrl : std_logic; - SIGNAL HDB0_ena_ctrl : std_logic; - SIGNAL HDE8_ena_ctrl : std_logic; - SIGNAL HDE0_ena_ctrl : std_logic; - SIGNAL HBB8_ena_ctrl : std_logic; - SIGNAL HBB0_ena_ctrl : std_logic; - SIGNAL HSS0_clk_ctrl : std_logic; - SIGNAL HSS8_ena_ctrl : std_logic; - SIGNAL HSS0_ena_ctrl : std_logic; - SIGNAL VBE8_ena_ctrl : std_logic; - SIGNAL VBE0_ena_ctrl : std_logic; - SIGNAL VDB8_ena_ctrl : std_logic; - SIGNAL VDB0_ena_ctrl : std_logic; - SIGNAL VDE8_ena_ctrl : std_logic; - SIGNAL VDE0_ena_ctrl : std_logic; - SIGNAL VBB8_ena_ctrl : std_logic; - SIGNAL VBB0_ena_ctrl : std_logic; - SIGNAL VSS8_ena_ctrl : std_logic; - SIGNAL VSS0_ena_ctrl : std_logic; - SIGNAL VFT8_ena_ctrl : std_logic; - SIGNAL VFT0_ena_ctrl : std_logic; - SIGNAL VCO0_ena_ctrl : std_logic; - SIGNAL VCNTRL0_ena_ctrl : std_logic; - SIGNAL VVCNT0_ena_ctrl : std_logic; - SIGNAL VSYNC_I0_ena_ctrl : std_logic; - SIGNAL SUB_PIXEL_CNT0_ena_ctrl : std_logic; - SIGNAL COLOR8_2 : std_logic; - SIGNAL COLOR8_1 : std_logic; - SIGNAL COLOR1_3 : std_logic; - SIGNAL COLOR1_2 : std_logic; - SIGNAL COLOR1_1 : std_logic; - SIGNAL COLOR4_2 : std_logic; - SIGNAL COLOR4_1 : std_logic; - SIGNAL COLOR16_2 : std_logic; - SIGNAL COLOR16_1 : std_logic; - SIGNAL gnd : std_logic; - SIGNAL u1_enabledt : std_logic; - SIGNAL u0_enabledt : std_logic; - SIGNAL VCNTRL_CS : std_logic; - SIGNAL VCO_CS : std_logic; - SIGNAL VFT_CS : std_logic; - SIGNAL VSS_CS : std_logic; - SIGNAL VBB_CS : std_logic; - SIGNAL VDE_CS : std_logic; - SIGNAL VDB_CS : std_logic; - SIGNAL VBE_CS : std_logic; - SIGNAL DOP_FIFO_CLR_q : std_logic; - SIGNAL DOP_FIFO_CLR_d : std_logic; - SIGNAL DOP_ZEI_q : std_logic; - SIGNAL DOP_ZEI_d : std_logic; - SIGNAL DOP_ZEI : std_logic; - SIGNAL INTER_ZEI_q : std_logic; - SIGNAL INTER_ZEI_d : std_logic; - SIGNAL ST_VIDEO : std_logic; - SIGNAL FALCON_VIDEO : std_logic; - SIGNAL HSS_CS : std_logic; - SIGNAL HBB_CS : std_logic; - SIGNAL HDE_CS : std_logic; - SIGNAL HDB_CS : std_logic; - SIGNAL HBE_CS : std_logic; - SIGNAL HHT_CS : std_logic; - SIGNAL ATARI_VL_CS : std_logic; - SIGNAL ATARI_HL_CS : std_logic; - SIGNAL ATARI_VH_CS : std_logic; - SIGNAL ATARI_HH_CS : std_logic; - SIGNAL ATARI_SYNC : std_logic; - SIGNAL COLOR24 : std_logic; - SIGNAL COLOR16 : std_logic; - SIGNAL SYNC_PIX2_q : std_logic; - SIGNAL SYNC_PIX2_d : std_logic; - SIGNAL SYNC_PIX2 : std_logic; - SIGNAL SYNC_PIX1_q : std_logic; - SIGNAL SYNC_PIX1_d : std_logic; - SIGNAL SYNC_PIX1 : std_logic; - SIGNAL SYNC_PIX_q : std_logic; - SIGNAL SYNC_PIX_d : std_logic; - SIGNAL SYNC_PIX : std_logic; - SIGNAL START_ZEILE_q : std_logic; - SIGNAL START_ZEILE_ena : std_logic; - SIGNAL START_ZEILE_d : std_logic; - SIGNAL START_ZEILE : std_logic; - SIGNAL CLR_FIFO_q : std_logic; - SIGNAL CLR_FIFO_ena : std_logic; - SIGNAL CLR_FIFO_d : std_logic; - SIGNAL FIFO_RDE_q : std_logic; - SIGNAL FIFO_RDE_d : std_logic; - SIGNAL RAND_ON : std_logic; - SIGNAL VCO_OFF_q : std_logic; - SIGNAL VCO_OFF_d : std_logic; - SIGNAL VCO_OFF : std_logic; - SIGNAL VCO_ON_q : std_logic; - SIGNAL VCO_ON_d : std_logic; - SIGNAL VCO_ON : std_logic; - SIGNAL VCO_ZL_q : std_logic; - SIGNAL VCO_ZL_ena : std_logic; - SIGNAL VCO_ZL_d : std_logic; - SIGNAL VCO_ZL : std_logic; - SIGNAL VDTRON_q : std_logic; - SIGNAL VDTRON_d : std_logic; - SIGNAL VDTRON : std_logic; - SIGNAL DPO_OFF_q : std_logic; - SIGNAL DPO_OFF_d : std_logic; - SIGNAL DPO_OFF : std_logic; - SIGNAL DPO_ON_q : std_logic; - SIGNAL DPO_ON_d : std_logic; - SIGNAL DPO_ON : std_logic; - SIGNAL DPO_ZL_q : std_logic; - SIGNAL DPO_ZL_ena : std_logic; - SIGNAL DPO_ZL_d : std_logic; - SIGNAL DPO_ZL : std_logic; - SIGNAL DISP_ON_q : std_logic; - SIGNAL DISP_ON_d : std_logic; - SIGNAL DISP_ON : std_logic; - SIGNAL nBLANK_q : std_logic; - SIGNAL nBLANK_d : std_logic; - SIGNAL VSYNC_START_q : std_logic; - SIGNAL VSYNC_START_ena : std_logic; - SIGNAL VSYNC_START_d : std_logic; - SIGNAL VSYNC_START : std_logic; - SIGNAL VSYNC_q : std_logic; - SIGNAL VSYNC_d : std_logic; - SIGNAL LAST_q : std_logic; - SIGNAL LAST_d : std_logic; - SIGNAL LAST : std_logic; - SIGNAL HSYNC_START_q : std_logic; - SIGNAL HSYNC_START_d : std_logic; - SIGNAL HSYNC_START : std_logic; - SIGNAL HSYNC_q : std_logic; - SIGNAL HSYNC_d : std_logic; - SIGNAL CLUT_TA_q : std_logic; - SIGNAL CLUT_TA_d : std_logic; - SIGNAL CLUT_TA : std_logic; - SIGNAL LWD_CS : std_logic; - SIGNAL LOF_CS : std_logic; - SIGNAL SYS_CTR_CS : std_logic; - SIGNAL ACP_VIDEO_ON : std_logic; - SIGNAL BORDER_COLOR_CS : std_logic; - SIGNAL ACP_VCTR_CS : std_logic; - SIGNAL FALCON_SHIFT_MODE_CS : std_logic; - SIGNAL ST_SHIFT_MODE_CS : std_logic; - SIGNAL ST_CLUT : std_logic; - SIGNAL ST_CLUT_CS : std_logic; - SIGNAL FALCON_CLUT : std_logic; - SIGNAL FALCON_CLUT_CS : std_logic; - SIGNAL VIDEO_RECONFIG_q : std_logic; - SIGNAL VIDEO_RECONFIG_d : std_logic; - SIGNAL VIDEO_PLL_RECONFIG_CS : std_logic; - SIGNAL VR_WR_q : std_logic; - SIGNAL VR_WR_d : std_logic; - SIGNAL VIDEO_PLL_CONFIG_CS : std_logic; - SIGNAL ACP_CLUT : std_logic; - SIGNAL ACP_CLUT_CS : std_logic; - SIGNAL CLK13M_q : std_logic; - SIGNAL CLK13M_d : std_logic; - SIGNAL CLK13M : std_logic; - SIGNAL CLK17M_q : std_logic; - SIGNAL CLK17M_d : std_logic; - SIGNAL CLK17M : std_logic; - SIGNAL color4_i : std_logic; - SIGNAL pixel_clk_i : std_logic; + signal ATARI_HH24_ena_ctrl : std_logic; + signal ATARI_HH16_ena_ctrl : std_logic; + signal ATARI_HH8_ena_ctrl : std_logic; + signal ATARI_HH0_ena_ctrl : std_logic; + signal ATARI_VH24_ena_ctrl : std_logic; + signal ATARI_VH16_ena_ctrl : std_logic; + signal ATARI_VH8_ena_ctrl : std_logic; + signal ATARI_VH0_ena_ctrl : std_logic; + signal ATARI_HL24_ena_ctrl : std_logic; + signal ATARI_HL16_ena_ctrl : std_logic; + signal ATARI_HL8_ena_ctrl : std_logic; + signal ATARI_HL0_ena_ctrl : std_logic; + signal ATARI_VL0_clk_ctrl : std_logic; + signal ATARI_VL24_ena_ctrl : std_logic; + signal ATARI_VL16_ena_ctrl : std_logic; + signal ATARI_VL8_ena_ctrl : std_logic; + signal ATARI_VL0_ena_ctrl : std_logic; + signal VR_DOUT0_ena_ctrl : std_logic; + signal VR_FRQ0_ena_ctrl : std_logic; + signal BORDER_COLOR16_ena_ctrl : std_logic; + signal BORDER_COLOR8_ena_ctrl : std_logic; + signal BORDER_COLOR0_ena_ctrl : std_logic; + signal SYS_CTR0_ena_ctrl : std_logic; + signal LOF8_ena_ctrl : std_logic; + signal LOF0_ena_ctrl : std_logic; + signal LWD8_ena_ctrl : std_logic; + signal LWD0_ena_ctrl : std_logic; + signal HHT8_ena_ctrl : std_logic; + signal HHT0_ena_ctrl : std_logic; + signal HBE8_ena_ctrl : std_logic; + signal HBE0_ena_ctrl : std_logic; + signal HDB8_ena_ctrl : std_logic; + signal HDB0_ena_ctrl : std_logic; + signal HDE8_ena_ctrl : std_logic; + signal HDE0_ena_ctrl : std_logic; + signal HBB8_ena_ctrl : std_logic; + signal HBB0_ena_ctrl : std_logic; + signal HSS0_clk_ctrl : std_logic; + signal HSS8_ena_ctrl : std_logic; + signal HSS0_ena_ctrl : std_logic; + signal VBE8_ena_ctrl : std_logic; + signal VBE0_ena_ctrl : std_logic; + signal VDB8_ena_ctrl : std_logic; + signal VDB0_ena_ctrl : std_logic; + signal VDE8_ena_ctrl : std_logic; + signal VDE0_ena_ctrl : std_logic; + signal VBB8_ena_ctrl : std_logic; + signal VBB0_ena_ctrl : std_logic; + signal VSS8_ena_ctrl : std_logic; + signal VSS0_ena_ctrl : std_logic; + signal VFT8_ena_ctrl : std_logic; + signal VFT0_ena_ctrl : std_logic; + signal VCO0_ena_ctrl : std_logic; + signal VCNTRL0_ena_ctrl : std_logic; + signal VVCNT0_ena_ctrl : std_logic; + signal VSYNC_I0_ena_ctrl : std_logic; + signal SUB_PIXEL_CNT0_ena_ctrl : std_logic; + signal COLOR8_2 : std_logic; + signal COLOR8_1 : std_logic; + signal COLOR1_3 : std_logic; + signal COLOR1_2 : std_logic; + signal COLOR1_1 : std_logic; + signal COLOR4_2 : std_logic; + signal COLOR4_1 : std_logic; + signal COLOR16_2 : std_logic; + signal COLOR16_1 : std_logic; + signal gnd : std_logic; + signal u1_enabledt : std_logic; + signal u0_enabledt : std_logic; + signal VCNTRL_CS : std_logic; + signal VCO_CS : std_logic; + signal VFT_CS : std_logic; + signal VSS_CS : std_logic; + signal VBB_CS : std_logic; + signal VDE_CS : std_logic; + signal VDB_CS : std_logic; + signal VBE_CS : std_logic; + signal DOP_FIFO_CLR_q : std_logic; + signal DOP_FIFO_CLR_d : std_logic; + signal DOP_ZEI_q : std_logic; + signal DOP_ZEI_d : std_logic; + signal DOP_ZEI : std_logic; + signal INTER_ZEI_q : std_logic; + signal INTER_ZEI_d : std_logic; + signal ST_VIDEO : std_logic; + signal FALCON_VIDEO : std_logic; + signal HSS_CS : std_logic; + signal HBB_CS : std_logic; + signal HDE_CS : std_logic; + signal HDB_CS : std_logic; + signal HBE_CS : std_logic; + signal HHT_CS : std_logic; + signal ATARI_VL_CS : std_logic; + signal ATARI_HL_CS : std_logic; + signal ATARI_VH_CS : std_logic; + signal ATARI_HH_CS : std_logic; + signal ATARI_SYNC : std_logic; + signal COLOR24 : std_logic; + signal COLOR16 : std_logic; + signal SYNC_PIX2_q : std_logic; + signal SYNC_PIX2_d : std_logic; + signal SYNC_PIX2 : std_logic; + signal SYNC_PIX1_q : std_logic; + signal SYNC_PIX1_d : std_logic; + signal SYNC_PIX1 : std_logic; + signal SYNC_PIX_q : std_logic; + signal SYNC_PIX_d : std_logic; + signal SYNC_PIX : std_logic; + signal START_ZEILE_q : std_logic; + signal START_ZEILE_ena : std_logic; + signal START_ZEILE_d : std_logic; + signal START_ZEILE : std_logic; + signal CLR_FIFO_q : std_logic; + signal CLR_FIFO_ena : std_logic; + signal CLR_FIFO_d : std_logic; + signal FIFO_RDE_q : std_logic; + signal FIFO_RDE_d : std_logic; + signal RAND_ON : std_logic; + signal VCO_OFF_q : std_logic; + signal VCO_OFF_d : std_logic; + signal VCO_OFF : std_logic; + signal VCO_ON_q : std_logic; + signal VCO_ON_d : std_logic; + signal VCO_ON : std_logic; + signal VCO_ZL_q : std_logic; + signal VCO_ZL_ena : std_logic; + signal VCO_ZL_d : std_logic; + signal VCO_ZL : std_logic; + signal VDTRON_q : std_logic; + signal VDTRON_d : std_logic; + signal VDTRON : std_logic; + signal DPO_OFF_q : std_logic; + signal DPO_OFF_d : std_logic; + signal DPO_OFF : std_logic; + signal DPO_ON_q : std_logic; + signal DPO_ON_d : std_logic; + signal DPO_ON : std_logic; + signal DPO_ZL_q : std_logic; + signal DPO_ZL_ena : std_logic; + signal DPO_ZL_d : std_logic; + signal DPO_ZL : std_logic; + signal DISP_ON_q : std_logic; + signal DISP_ON_d : std_logic; + signal DISP_ON : std_logic; + signal nBLANK_q : std_logic; + signal nBLANK_d : std_logic; + signal VSYNC_START_q : std_logic; + signal VSYNC_START_ena : std_logic; + signal VSYNC_START_d : std_logic; + signal VSYNC_START : std_logic; + signal VSYNC_q : std_logic; + signal VSYNC_d : std_logic; + signal LAST_q : std_logic; + signal LAST_d : std_logic; + signal LAST : std_logic; + signal HSYNC_START_q : std_logic; + signal HSYNC_START_d : std_logic; + signal HSYNC_START : std_logic; + signal HSYNC_q : std_logic; + signal HSYNC_d : std_logic; + signal CLUT_TA_q : std_logic; + signal CLUT_TA_d : std_logic; + signal CLUT_TA : std_logic; + signal LWD_CS : std_logic; + signal LOF_CS : std_logic; + signal SYS_CTR_CS : std_logic; + signal ACP_VIDEO_ON : std_logic; + signal BORDER_COLOR_CS : std_logic; + signal ACP_VCTR_CS : std_logic; + signal FALCON_SHIFT_MODE_CS : std_logic; + signal ST_SHIFT_MODE_CS : std_logic; + signal ST_CLUT : std_logic; + signal ST_CLUT_CS : std_logic; + signal FALCON_CLUT : std_logic; + signal FALCON_CLUT_CS : std_logic; + signal VIDEO_RECONFIG_q : std_logic; + signal VIDEO_RECONFIG_d : std_logic; + signal VIDEO_PLL_RECONFIG_CS : std_logic; + signal VR_WR_q : std_logic; + signal VR_WR_d : std_logic; + signal VIDEO_PLL_CONFIG_CS : std_logic; + signal ACP_CLUT : std_logic; + signal ACP_CLUT_CS : std_logic; + signal CLK13M_q : std_logic; + signal CLK13M_d : std_logic; + signal CLK13M : std_logic; + signal CLK17M_q : std_logic; + signal CLK17M_d : std_logic; + signal CLK17M : std_logic; + signal color4_i : std_logic; + signal pixel_clk_i : std_logic; -- Sub Module Interface Section - - COMPONENT lpm_bustri_WORD - PORT - ( - data : IN std_logic_vector(15 downto 0); - enabledt : IN std_logic; - tridata : BUFFER std_logic_vector(15 downto 0) - ); - END COMPONENT lpm_bustri_WORD; - - FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS - VARIABLE ret : std_logic; - BEGIN - IF x THEN + function to_std_logic(X : in boolean) return std_logic is + variable ret : std_logic; + begin + if x then ret := '1'; else ret := '0'; - END IF; - RETURN ret; - END FUNCTION to_std_logic; + end if; + return ret; + end function to_std_logic; -- sizeIt replicates a value to an array of specific length. - FUNCTION sizeit(a : std_Logic; len : integer) RETURN std_logic_vector IS - VARIABLE rep: std_logic_vector(len - 1 downto 0); - BEGIN - FOR i IN rep'RANGE LOOP + function sizeit(a : std_Logic; len : integer) return std_logic_vector is + variable rep : std_logic_vector(len - 1 downto 0); + begin + for i in rep'range loop rep(i) := a; - END LOOP; - RETURN rep; - END FUNCTION sizeit; - -BEGIN + end loop; + return rep; + end function sizeit; +begin -- Sub Module Section u0 : entity work.lpm_bustri_WORD - PORT MAP + port map ( data => u0_data, enabledt => u0_enabledt, tridata => u0_tridata ); - u1 : lpm_bustri_WORD - PORT MAP + u1 : entity work.lpm_bustri_WORD + port map ( data => u1_data, enabledt => u1_enabledt, @@ -526,56 +516,56 @@ BEGIN CLUT_MUX_ADR <= CLUT_MUX_ADR_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; - END IF; - END PROCESS; + end if; + end process; HSYNC <= HSYNC_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then HSYNC_q <= HSYNC_d; - END IF; - END PROCESS; + end if; + end process; VSYNC <= VSYNC_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then VSYNC_q <= VSYNC_d; - END IF; - END PROCESS; + end if; + end process; nBLANK <= nBLANK_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then nBLANK_q <= nBLANK_d; - END IF; - END PROCESS; + end if; + end process; FIFO_RDE <= FIFO_RDE_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then FIFO_RDE_q <= FIFO_RDE_d; - END IF; - END PROCESS; + end if; + end process; BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - IF BORDER_COLOR16_ena_ctrl = '1' THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then + if BORDER_COLOR16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); - END IF; - IF BORDER_COLOR8_ena_ctrl = '1' THEN + end if; + if BORDER_COLOR8_ena_ctrl = '1' THEN border_color_q(15 downto 8) <= border_color_d(15 downto 8); END IF; IF BORDER_COLOR0_ena_ctrl = '1' THEN @@ -1141,14 +1131,14 @@ BEGIN -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 10) = "000000000000000000"); + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 10) = "000000000000000000"); ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); - ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS,4) and sizeIt(not nFB_WR,4); + ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS, 4) and sizeIt(not nFB_WR, 4); CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not VIDEO_MOD_TA); -- FALCON CLUT -- -- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 10) = "1111100110"); + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 10) = "1111100110"); -- HIGH WORD FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); @@ -1541,7 +1531,8 @@ BEGIN std_logic_vector'(d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else std_logic_vector'(d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else std_logic_vector'(d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else - std_logic_vector(d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1'; + std_logic_vector(d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else + (others => '0'); -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or @@ -1580,9 +1571,10 @@ BEGIN -- # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- rand_links <= HBE_q when acp_video_on else - 12d"12" when not acp_video_on and atari_sync and vcntrl(2) else + 12d"21" when not acp_video_on and atari_sync and vcntrl(2) else 12d"42" when not acp_video_on and atari_sync and not(vcntrl(2)) else - std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync; + std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else + (others => '0'); /* rand_links <= (HBE_q and sizeit(acp_video_on, 12)) or (std_logic_vector(to_unsigned(21, 12)) and sizeit(not acp_video_on and atari_sync and vcntrl(2), 12)) or @@ -1593,7 +1585,7 @@ BEGIN -- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON,12)) or - ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); + ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); @@ -1621,16 +1613,16 @@ BEGIN (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or - ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and - sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) - and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or - (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not - ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or + ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(ST_VIDEO,11)) or + ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or + (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); @@ -1805,6 +1797,6 @@ BEGIN COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; COLOR8 <= COLOR8_1 or COLOR8_2; - -- Define power SIGNAL(s) + -- Define power signal(s) gnd <= '0'; END ARCHITECTURE rtl; From a7f6d4191eec22991d9b54c3a3a0b5409ab9a10a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 26 Apr 2016 06:14:03 +0000 Subject: [PATCH 087/127] add function f_addr_cmp() --- .../Video/video_mod_mux_clutctr.vhd | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index a98c78a..9d02bcf 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -493,6 +493,24 @@ architecture rtl of video_mod_mux_clutctr is end loop; return rep; end function sizeit; + + function f_addr_cmp(addr_const : std_logic_vector; addr : std_logic_vector; ignore : integer) return boolean is + variable c_len : integer := addr_const'high; + variable a_len : integer := addr'high; + variable len : integer; + variable result : boolean := false; + begin + if c_len < a_len then + len := c_len; + else + len := a_len; + end if; + for i in len downto len - ignore loop + result := addr_const(i) = addr(i); + exit when result = false; + end loop; + return result; + end function f_addr_cmp; begin -- Sub Module Section @@ -1333,7 +1351,10 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - SYS_CTR_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000000000011"); + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp(FB_ADR, 20x"f8006", 1); + -- FB_ADR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; + + -- SYS_CTR_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); SYS_CTR_d <= FB_AD(22 downto 16); SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); BLITTER_ON <= not SYS_CTR_q(3); From fa4a3f686c209ad4b3a8175eb9ebe04a97f6db19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 26 Apr 2016 16:39:22 +0000 Subject: [PATCH 088/127] simplify and fix errors --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 18 +- .../Video/video_mod_mux_clutctr.vhd | 484 +++++------------- FPGA_Quartus_13.1/firebee1.qsf | 2 + 3 files changed, 149 insertions(+), 355 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index cb29254..fdaf759 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -287,14 +287,14 @@ architecture rtl of ddr_ctr is -- Sub Module Interface Section - component lpm_bustri_BYT - port - ( - data : in std_logic_vector(7 downto 0); - enabledt : in std_logic; - tridata : buffer std_logic_vector(7 downto 0) - ); - end component lpm_bustri_BYT; +-- component lpm_bustri_BYT +-- port +-- ( +-- data : in std_logic_vector(7 downto 0); +-- enabledt : in std_logic; +-- tridata : buffer std_logic_vector(7 downto 0) +-- ); +-- end component lpm_bustri_BYT; function to_std_logic(X : in boolean) return std_logic is variable ret : std_logic; @@ -321,7 +321,7 @@ architecture rtl of ddr_ctr is begin -- Sub Module Section - u0 : lpm_bustri_BYT + u0 : entity work.lpm_bustri_BYT port map ( data => u0_data, diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 9d02bcf..4987f38 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -494,6 +494,8 @@ architecture rtl of video_mod_mux_clutctr is return rep; end function sizeit; + -- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller + -- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise function f_addr_cmp(addr_const : std_logic_vector; addr : std_logic_vector; ignore : integer) return boolean is variable c_len : integer := addr_const'high; variable a_len : integer := addr'high; @@ -533,53 +535,25 @@ begin -- Register Section CLUT_MUX_ADR <= CLUT_MUX_ADR_q; + HSYNC <= HSYNC_q; + VSYNC <= VSYNC_q; + nBLANK <= nBLANK_q; + FIFO_RDE <= FIFO_RDE_q; + BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); + BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); + BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); + CCSEL <= CCSEL_q; + INTER_ZEI <= INTER_ZEI_q; + DOP_FIFO_CLR <= DOP_FIFO_CLR_q; process (pixel_clk_i) begin if rising_edge(pixel_clk_i) then CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; - end if; - end process; - - HSYNC <= HSYNC_q; - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then HSYNC_q <= HSYNC_d; - end if; - end process; - - VSYNC <= VSYNC_q; - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then VSYNC_q <= VSYNC_d; - end if; - end process; - - nBLANK <= nBLANK_q; - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then nBLANK_q <= nBLANK_d; - end if; - end process; - - FIFO_RDE <= FIFO_RDE_q; - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then FIFO_RDE_q <= FIFO_RDE_d; - end if; - end process; - - BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); - BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); - BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); - - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then if BORDER_COLOR16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); end if; @@ -589,29 +563,8 @@ begin IF BORDER_COLOR0_ena_ctrl = '1' THEN border_color_q(7 downto 0) <= border_color_d(7 downto 0); END IF; - END IF; - END PROCESS; - - CCSEL <= CCSEL_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN CCSEL_q <= CCSEL_d; - END IF; - END PROCESS; - - INTER_ZEI <= INTER_ZEI_q; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN INTER_ZEI_q <= INTER_ZEI_d; - END IF; - END PROCESS; - - DOP_FIFO_CLR <= DOP_FIFO_CLR_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d; END IF; END PROCESS; @@ -642,13 +595,6 @@ begin END IF; END PROCESS; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - CLK17M_q <= CLK17M_d; - END IF; - END PROCESS; - PROCESS (clk25m) BEGIN IF rising_edge(clk25m) THEN @@ -656,74 +602,48 @@ begin END IF; END PROCESS; + VR_FRQ <= unsigned(VR_FRQ_q); + PROCESS (main_clk) BEGIN IF rising_edge(main_clk) THEN + CLK17M_q <= CLK17M_d; + IF VR_DOUT0_ena_ctrl = '1' THEN VR_DOUT_q <= VR_DOUT_d; END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN + IF VR_FRQ0_ena_ctrl = '1' THEN VR_FRQ_q <= VR_FRQ_d; END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN + IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN + IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); END IF; + IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); END IF; - END IF; - END PROCESS; - - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; - END IF; - END PROCESS; - - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF ACP_VCTR24_ena_ctrl = '1' THEN + IF ACP_VCTR24_ena_ctrl = '1' THEN ACP_VCTR_q(31 downto 24) <= ACP_VCTR_d(31 downto 24); END IF; + IF ACP_VCTR16_ena_ctrl = '1' THEN ACP_VCTR_q(23 downto 16) <= ACP_VCTR_d(23 downto 16); END IF; + IF ACP_VCTR8_ena_ctrl = '1' THEN ACP_VCTR_q(15 downto 8) <= ACP_VCTR_d(15 downto 8); END IF; + IF ACP_VCTR6_ena_ctrl = '1' THEN ACP_VCTR_q(7 downto 6) <= ACP_VCTR_d(7 downto 6); END IF; + IF ACP_VCTR0_ena_ctrl = '1' THEN ACP_VCTR_q(5 downto 0) <= ACP_VCTR_d(5 downto 0); END IF; @@ -747,35 +667,112 @@ begin IF LWD0_ena_ctrl = '1' THEN LWD_q(7 downto 0) <= LWD_d(7 downto 0); END IF; - END IF; - END PROCESS; - - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - CLUT_TA_q <= CLUT_TA_d; - END IF; - END PROCESS; - - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - HSYNC_I_q <= HSYNC_I_d; - END IF; - END PROCESS; - - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - HSY_LEN_q <= HSY_LEN_d; - END IF; - END PROCESS; - - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - HSYNC_START_q <= HSYNC_START_d; + + IF HDB8_ena_ctrl = '1' THEN + HDB_q(11 downto 8) <= HDB_d(11 downto 8); + END IF; + IF HDB0_ena_ctrl = '1' THEN + HDB_q(7 downto 0) <= HDB_d(7 downto 0); + END IF; + + IF HDE8_ena_ctrl = '1' THEN + HDE_q(11 downto 8) <= HDE_d(11 downto 8); + END IF; + + IF HDE0_ena_ctrl = '1' THEN + HDE_q(7 downto 0) <= HDE_d(7 downto 0); + END IF; + + IF HBB8_ena_ctrl = '1' THEN + HBB_q(11 downto 8) <= HBB_d(11 downto 8); + END IF; + + IF HBB0_ena_ctrl = '1' THEN + HBB_q(7 downto 0) <= HBB_d(7 downto 0); + END IF; + + IF HSS8_ena_ctrl = '1' THEN + HSS_q(11 downto 8) <= HSS_d(11 downto 8); + END IF; + + IF HSS0_ena_ctrl='1' THEN + HSS_q(7 downto 0) <= HSS_d(7 downto 0); + END IF; + + DOP_ZEI_q <= DOP_ZEI_d; + + IF VBE8_ena_ctrl = '1' THEN + VBE_q(10 downto 8) <= VBE_d(10 downto 8); + END IF; + + IF VBE0_ena_ctrl = '1' THEN + VBE_q(7 downto 0) <= VBE_d(7 downto 0); + END IF; + + IF VDB8_ena_ctrl = '1' THEN + VDB_q(10 downto 8) <= VDB_d(10 downto 8); + END IF; + + IF VDB0_ena_ctrl = '1' THEN + VDB_q(7 downto 0) <= VDB_d(7 downto 0); + END IF; + + IF VDE8_ena_ctrl = '1' THEN + VDE_q(10 downto 8) <= VDE_d(10 downto 8); + END IF; + + IF VDE0_ena_ctrl = '1' THEN + VDE_q(7 downto 0) <= VDE_d(7 downto 0); + END IF; + + IF VBB8_ena_ctrl = '1' THEN + VBB_q(10 downto 8) <= VBB_d(10 downto 8); + END IF; + + IF VBB0_ena_ctrl = '1' THEN + VBB_q(7 downto 0) <= VBB_d(7 downto 0); + END IF; + + IF VSS8_ena_ctrl = '1' THEN + VSS_q(10 downto 8) <= VSS_d(10 downto 8); + END IF; + + IF VSS0_ena_ctrl = '1' THEN + VSS_q(7 downto 0) <= VSS_d(7 downto 0); + END IF; + + IF VFT8_ena_ctrl = '1' THEN + VFT_q(10 downto 8) <= VFT_d(10 downto 8); + END IF; + + IF VFT0_ena_ctrl = '1' THEN + VFT_q(7 downto 0) <= VFT_d(7 downto 0); + END IF; + + IF VCO_ena(8) = '1' THEN + VCO_q(8) <= VCO_d(8); + END IF; + + IF VCO0_ena_ctrl = '1' THEN + VCO_q(7 downto 0) <= VCO_d(7 downto 0); + END IF; + + IF VCNTRL0_ena_ctrl = '1' THEN + VCNTRL_q <= VCNTRL_d; + END IF; + END IF; + END PROCESS; + + PROCESS (pixel_clk_i) + BEGIN + IF rising_edge(pixel_clk_i) THEN + CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; + CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; + CLUT_TA_q <= CLUT_TA_d; + HSYNC_I_q <= HSYNC_I_d; + HSY_LEN_q <= HSY_LEN_d; + HSYNC_START_q <= HSYNC_START_d; LAST_q <= LAST_d; IF VSYNC_START_ena = '1' THEN @@ -907,213 +904,6 @@ begin END IF; END PROCESS; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HDB8_ena_ctrl = '1' THEN - HDB_q(11 downto 8) <= HDB_d(11 downto 8); - END IF; - IF HDB0_ena_ctrl = '1' THEN - HDB_q(7 downto 0) <= HDB_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HDE8_ena_ctrl = '1' THEN - HDE_q(11 downto 8) <= HDE_d(11 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HDE0_ena_ctrl = '1' THEN - HDE_q(7 downto 0) <= HDE_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HBB8_ena_ctrl = '1' THEN - HBB_q(11 downto 8) <= HBB_d(11 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HBB0_ena_ctrl = '1' THEN - HBB_q(7 downto 0) <= HBB_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HSS8_ena_ctrl = '1' THEN - HSS_q(11 downto 8) <= HSS_d(11 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF HSS0_ena_ctrl='1' THEN - HSS_q(7 downto 0) <= HSS_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - DOP_ZEI_q <= DOP_ZEI_d; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VBE8_ena_ctrl = '1' THEN - VBE_q(10 downto 8) <= VBE_d(10 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VBE0_ena_ctrl = '1' THEN - VBE_q(7 downto 0) <= VBE_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VDB8_ena_ctrl = '1' THEN - VDB_q(10 downto 8) <= VDB_d(10 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VDB0_ena_ctrl = '1' THEN - VDB_q(7 downto 0) <= VDB_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VDE8_ena_ctrl = '1' THEN - VDE_q(10 downto 8) <= VDE_d(10 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VDE0_ena_ctrl = '1' THEN - VDE_q(7 downto 0) <= VDE_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VBB8_ena_ctrl = '1' THEN - VBB_q(10 downto 8) <= VBB_d(10 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VBB0_ena_ctrl = '1' THEN - VBB_q(7 downto 0) <= VBB_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VSS8_ena_ctrl = '1' THEN - VSS_q(10 downto 8) <= VSS_d(10 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VSS0_ena_ctrl = '1' THEN - VSS_q(7 downto 0) <= VSS_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VFT8_ena_ctrl = '1' THEN - VFT_q(10 downto 8) <= VFT_d(10 downto 8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VFT0_ena_ctrl = '1' THEN - VFT_q(7 downto 0) <= VFT_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VCO_ena(8) = '1' THEN - VCO_q(8) <= VCO_d(8); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VCO0_ena_ctrl = '1' THEN - VCO_q(7 downto 0) <= VCO_d(7 downto 0); - END IF; - END IF; - END PROCESS; - - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - IF VCNTRL0_ena_ctrl = '1' THEN - VCNTRL_q <= VCNTRL_d; - END IF; - END IF; - END PROCESS; -- Start of original equations @@ -1604,16 +1394,17 @@ begin -- HDIS_START[] = HDB[] & ACP_VIDEO_ON -- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- - HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); - HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON,12)) or - ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); - RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or + HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); + HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON,12)) or + ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); + RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); hs_start <= hss_q when acp_video_on else atari_hl(11 downto 0) when not(acp_video_on) and atari_sync and vcntrl(2) else atari_hh(11 downto 0) when not(acp_video_on) and atari_sync and not vcntrl(2) else - std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync; + std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else + (others => '0'); -- HS_START[] = HSS[] & ACP_VIDEO_ON -- # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 @@ -1623,7 +1414,8 @@ begin h_total <= hht_q when acp_video_on else atari_hl(27 downto 16) when not acp_video_on and atari_sync and vcntrl(2) else atari_hh(27 downto 16) when not acp_video_on and atari_sync and not vcntrl(2) else - std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync; + std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync else + (others => '0'); -- H_TOTAL[] = HHT[] & ACP_VIDEO_ON -- # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index ec496e5..eb1cbd5 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -677,6 +677,8 @@ set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf set_global_assignment -name AHDL_FILE altpll4.tdf set_global_assignment -name SDC_FILE firebee_groups.sdc set_global_assignment -name VHDL_FILE Video/video.vhd From 1a972f2c648ce32552d45b7c73566ebf2288c826 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 26 Apr 2016 19:34:39 +0000 Subject: [PATCH 089/127] reformatting --- .../Video/video_mod_mux_clutctr.vhd | 16 +- FPGA_Quartus_13.1/firebee1.qsf | 1490 ++++++++--------- 2 files changed, 755 insertions(+), 751 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 4987f38..fbd43c5 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -496,7 +496,7 @@ architecture rtl of video_mod_mux_clutctr is -- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller -- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise - function f_addr_cmp(addr_const : std_logic_vector; addr : std_logic_vector; ignore : integer) return boolean is + function f_addr_cmp(signal addr : std_logic_vector; constant addr_const : std_logic_vector; constant ignore : integer) return boolean is variable c_len : integer := addr_const'high; variable a_len : integer := addr'high; variable len : integer; @@ -628,7 +628,7 @@ begin IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); END IF; - IF ACP_VCTR24_ena_ctrl = '1' THEN + IF ACP_VCTR24_ena_ctrl = '1' THEN ACP_VCTR_q(31 downto 24) <= ACP_VCTR_d(31 downto 24); END IF; @@ -1394,8 +1394,8 @@ begin -- HDIS_START[] = HDB[] & ACP_VIDEO_ON -- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- - HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); - HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON,12)) or + HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON, 12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); + HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON, 12)) or ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); @@ -1508,8 +1508,12 @@ begin -- 3 zeilen vsync length -- runterzählen bis 0 - VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or - ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); + VSYNC_I_d <= x"3" when VSYNC_START_q = '1' else + std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= '0' else + (others => '0'); + + -- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or + -- ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index eb1cbd5..d0dd521 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,311 +556,311 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From 6cf700019929b5038a4a300d094bcf17426a7a2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Tue, 26 Apr 2016 19:58:21 +0000 Subject: [PATCH 090/127] fix number of bits to compare --- .../Video/video_mod_mux_clutctr.vhd | 20 ++++++------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index fbd43c5..ab7f5cc 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -570,20 +570,8 @@ begin END PROCESS; VIDEO_RECONFIG <= VIDEO_RECONFIG_q; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; - END IF; - END PROCESS; VR_WR <= VR_WR_q; - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN - VR_WR_q <= VR_WR_d; - END IF; - END PROCESS; CLR_FIFO <= CLR_FIFO_q; PROCESS (pixel_clk_i) @@ -607,6 +595,10 @@ begin PROCESS (main_clk) BEGIN IF rising_edge(main_clk) THEN + VR_WR_q <= VR_WR_d; + + VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; + CLK17M_q <= CLK17M_d; IF VR_DOUT0_ena_ctrl = '1' THEN @@ -1508,8 +1500,8 @@ begin -- 3 zeilen vsync length -- runterzählen bis 0 - VSYNC_I_d <= x"3" when VSYNC_START_q = '1' else - std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= '0' else + VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else + std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else (others => '0'); -- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or From 195025b4be865c20553aa0009ade6ed4962a720d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 27 Apr 2016 05:10:46 +0000 Subject: [PATCH 091/127] fix hold time violations --- FPGA_Quartus_13.1/firebee1.qsf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index d0dd521..f42b241 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -671,7 +671,7 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF From 36f41e4fb7535a388b402b60b3ff8e661771056a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 27 Apr 2016 05:24:49 +0000 Subject: [PATCH 092/127] fix assignment vector length --- .../Video/video_mod_mux_clutctr.vhd | 26 ++++++++++++++----- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index ab7f5cc..56110e5 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -535,7 +535,18 @@ begin -- Register Section CLUT_MUX_ADR <= CLUT_MUX_ADR_q; + + -- missing signals that seem to got lost during conversion HSYNC <= HSYNC_q; + ACP_VCTR <= ACP_VCTR_q; + RAND <= RAND_q; + ATARI_HH <= ATARI_HH_q; + ATARI_HL <= ATARI_HL_q; + HBE <= HBE_q; + HSS <= HSS_q; + VCO <= VCO_q; + VCNTRL <= VCNTRL_q; + VSYNC <= VSYNC_q; nBLANK <= nBLANK_q; FIFO_RDE <= FIFO_RDE_q; @@ -545,6 +556,7 @@ begin CCSEL <= CCSEL_q; INTER_ZEI <= INTER_ZEI_q; DOP_FIFO_CLR <= DOP_FIFO_CLR_q; + HHT <= HHT_q; process (pixel_clk_i) begin @@ -1328,13 +1340,13 @@ begin -- 640 pixels, 25.175 MHz, VGA -- hsync pulse length in pixeln = frequenz / = 500ns - HSY_LEN_d <= std_logic_vector'(d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else - std_logic_vector'(d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else - std_logic_vector'(d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else - std_logic_vector'(d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else - std_logic_vector'(d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else - std_logic_vector'(d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else - std_logic_vector(d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else + HSY_LEN_d <= std_logic_vector'(8d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else + std_logic_vector'(8d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else + std_logic_vector'(8d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else + std_logic_vector'(8d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else + std_logic_vector'(8d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else + std_logic_vector'(8d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else + std_logic_vector(8d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else (others => '0'); -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or From 777e7a4b1c54e010d4c65757d7f27aec8cbd37be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 27 Apr 2016 05:59:07 +0000 Subject: [PATCH 093/127] remove strange constant assignment --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 138 ++++++++++++++-------------- FPGA_Quartus_13.1/firebee1.vhd | 4 +- 2 files changed, 69 insertions(+), 73 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index fdaf759..c005a60 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -187,8 +187,6 @@ architecture rtl of ddr_ctr is signal FIFO_BANK_OK_d_2 : std_logic; signal FIFO_BANK_OK_d_1 : std_logic; signal u0_enabledt : std_logic; - SiGNAL gnd : std_logic; - signal vcc : std_logic; signal VIDEO_CNT_H : std_logic; signal VIDEO_CNT_M : std_logic; signal VIDEO_CNT_L : std_logic; @@ -646,7 +644,7 @@ begin FB_REGDDR_0_clk_ctrl <= MAIN_CLK; - process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR, vcc) + process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR) variable stdVec3: std_logic_vector(2 downto 0); begin FB_REGDDR_d <= FB_REGDDR_q; @@ -669,12 +667,12 @@ begin when "001" => if DDR_CS_q = '1' then FB_LE(0) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; + VIDEO_DDR_TA <= '1'; if LINE ='1' then FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); FB_REGDDR_d <= "010"; else - BUS_CYC_END <= vcc; + BUS_CYC_END <= '1'; FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_REGDDR_d <= "000"; end if; @@ -686,7 +684,7 @@ begin if DDR_CS_q = '1' then FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); FB_LE(1) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; + VIDEO_DDR_TA <= '1'; FB_REGDDR_d <= "011"; else FB_REGDDR_d <= "000"; @@ -701,7 +699,7 @@ begin if ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' then FB_REGDDR_d <= "011"; else - VIDEO_DDR_TA <= vcc; + VIDEO_DDR_TA <= '1'; FB_REGDDR_d <= "100"; end if; else @@ -712,14 +710,15 @@ begin if DDR_CS_q = '1' then FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); FB_LE(3) <= not nFB_WR; - VIDEO_DDR_TA <= vcc; - BUS_CYC_END <= vcc; + VIDEO_DDR_TA <= '1'; + BUS_CYC_END <= '1'; FB_REGDDR_d <= "000"; else FB_REGDDR_d <= "000"; end if; when others => + video_ddr_ta <= '0'; end case; stdVec3 := (others => '0'); -- no storage needed end process; @@ -796,9 +795,9 @@ begin CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, - VIDEO_ADR_CNT_q, FIFO_COL_ADR, gnd, DDR_SEL, LINE, FIFO_BA, VA_P_q, + VIDEO_ADR_CNT_q, FIFO_COL_ADR, DDR_SEL, LINE, FIFO_BA, VA_P_q, BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, - DDR_REFRESH_SIG_q, vcc) + DDR_REFRESH_SIG_q) variable stdVec6: std_logic_vector(5 downto 0); begin DDR_SM_d <= DDR_SM_q; @@ -831,8 +830,8 @@ begin elsif (CPU_REQ_q)='1' then VA_S_d <= CPU_ROW_ADR; BA_S_d <= CPU_BA; - CPU_AC_d <= vcc; - BUS_CYC_d_2 <= vcc; + CPU_AC_d <= '1'; + BUS_CYC_d_2 <= '1'; DDR_SM_d <= "000010"; else -- FIFO IST DEFAULT @@ -840,12 +839,12 @@ begin VA_P_d <= FIFO_ROW_ADR; BA_P_d <= FIFO_BA; -- VORBESETZEN - FIFO_AC_d <= vcc; + FIFO_AC_d <= '1'; else VA_P_d <= BLITTER_ROW_ADR; BA_P_d <= BLITTER_BA; -- VORBESETZEN - BLITTER_AC_d <= vcc; + BLITTER_AC_d <= '1'; end if; DDR_SM_d <= "000001"; end if; @@ -857,14 +856,14 @@ begin when "000001" => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** if (DDR_SEL and (nFB_WR or (not LINE)))='1' then - VRAS <= vcc; + VRAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (BA1_2, BA0_2) <= FB_AD(13 downto 12); -- AUTO PRECHARGE DA NICHT FIFO PAGE - VA_S_d(10) <= vcc; - CPU_AC_d <= vcc; + VA_S_d(10) <= '1'; + CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; + BUS_CYC_d_2 <= '1'; else VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; @@ -877,12 +876,12 @@ begin DDR_SM_d <= "000011"; when "000010" => - VRAS <= vcc; - FIFO_BANK_NOT_OK <= vcc; - CPU_AC_d <= vcc; + VRAS <= '1'; + FIFO_BANK_NOT_OK <= '1'; + CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; + BUS_CYC_d_2 <= '1'; DDR_SM_d <= "000011"; when "000011" => @@ -917,7 +916,7 @@ begin when "001110" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - VCAS <= vcc; + VCAS <= '1'; -- READ DATEN FÜR CPU SR_DDR_FB <= CPU_AC_q; @@ -935,12 +934,12 @@ begin VA_S_d(9 downto 0) <= FIFO_COL_ADR; -- MANUELL PRECHARGE - VA_S_d(10) <= gnd; + VA_S_d(10) <= '0'; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; else -- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- WRITE DDR_SM_d <= "011101"; end if; @@ -975,14 +974,14 @@ begin when "010010" => CPU_AC_d <= CPU_AC_q; BLITTER_AC_d <= BLITTER_AC_q; - VCAS <= vcc; - VWE <= vcc; + VCAS <= '1'; + VWE <= '1'; -- WRITE COMMAND CPU UND BLITTER if WRITER - SR_DDR_WR_d <= vcc; + SR_DDR_WR_d <= '1'; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_DDRWR_D_SEL_d <= vcc; + SR_DDRWR_D_SEL_d <= '1'; -- WENN LINE DANN ACTIV SR_VDMP_d <= sizeIt(LINE,8) and "11111111"; @@ -993,10 +992,10 @@ begin BLITTER_AC_d <= BLITTER_AC_q; -- WRITE COMMAND CPU UND BLITTER if WRITE - SR_DDR_WR_d <= vcc; + SR_DDR_WR_d <= '1'; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_DDRWR_D_SEL_d <= vcc; + SR_DDRWR_D_SEL_d <= '1'; DDR_SM_d <= "010100"; when "010100" => @@ -1007,21 +1006,21 @@ begin VA_S_d(9 downto 0) <= FIFO_COL_ADR; -- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; + VA_S_d(10) <= '0'; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; else -- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- FIFO READ DDR_SM_d <= "011101"; end if; when "010110" => - VCAS <= vcc; + VCAS <= '1'; -- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; + SR_FIFO_WRE_d <= '1'; DDR_SM_d <= "010111"; when "010111" => @@ -1031,7 +1030,7 @@ begin if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; @@ -1039,31 +1038,31 @@ begin VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; + VA_S_d(10) <= '0'; BA_S_d <= FIFO_BA; DDR_SM_d <= "011000"; end if; else -- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- NOCH OFFEN LASSEN DDR_SM_d <= "011101"; end if; when "011000" => - VCAS <= vcc; + VCAS <= '1'; -- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; + SR_FIFO_WRE_d <= '1'; DDR_SM_d <= "011001"; when "011001" => if CPU_REQ_q='1' and (unsigned(FIFO_MW) > unsigned'("000000000")) then -- ALLE PAGES SCHLIESEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; @@ -1073,7 +1072,7 @@ begin if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE PAGES SCHLIESSEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; @@ -1081,24 +1080,24 @@ begin VA_S_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE - VA_S_d(10) <= gnd; + VA_S_d(10) <= '0'; BA_S_d <= FIFO_BA; DDR_SM_d <= "011010"; end if; else -- ALLE PAGES SCHLIESEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- BANK SCHLIESSEN DDR_SM_d <= "011110"; end if; when "011010" => - VCAS <= vcc; + VCAS <= '1'; -- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; + SR_FIFO_WRE_d <= '1'; -- NOTFALL? if (unsigned(FIFO_MW) < unsigned'("000000000")) then @@ -1116,7 +1115,7 @@ begin if VIDEO_ADR_CNT_q(7 downto 0) = "11111111" then -- ALLE BANKS SCHLIESEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; @@ -1124,14 +1123,14 @@ begin VA_P_d(9 downto 0) <= std_logic_vector'(unsigned(FIFO_COL_ADR) + unsigned'("0000000100")); -- NON AUTO PRECHARGE - VA_P_d(10) <= gnd; + VA_P_d(10) <= '0'; BA_P_d <= FIFO_BA; DDR_SM_d <= "011100"; end if; else -- ALLE BANKS SCHLIESEN - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; -- BANK SCHLIESSEN DDR_SM_d <= "011101"; @@ -1139,24 +1138,24 @@ begin when "011100" => if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then - VRAS <= vcc; + VRAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (BA1_2, BA0_2) <= FB_AD(13 downto 12); - CPU_AC_d <= vcc; + CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= vcc; + BUS_CYC_d_2 <= '1'; -- AUTO PRECHARGE DA NICHT FIFO BANK - VA_S_d(10) <= vcc; + VA_S_d(10) <= '1'; DDR_SM_d <= "000011"; else - VCAS <= vcc; + VCAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; (BA1_2, BA0_2) <= BA_P_q; -- DATEN WRITE FIFO - SR_FIFO_WRE_d <= vcc; + SR_FIFO_WRE_d <= '1'; -- CONFIG CYCLUS DDR_SM_d <= "011001"; @@ -1201,20 +1200,20 @@ begin when "011101" => -- AUF NOT OK - FIFO_BANK_NOT_OK <= vcc; + FIFO_BANK_NOT_OK <= '1'; -- BÄNKE SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; + VRAS <= '1'; + VWE <= '1'; DDR_SM_d <= "000110"; when "011110" => -- AUF NOT OK - FIFO_BANK_NOT_OK <= vcc; + FIFO_BANK_NOT_OK <= '1'; -- BÄNKE SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; + VRAS <= '1'; + VWE <= '1'; -- REFRESH 70NS = 10 ZYCLEN DDR_SM_d <= "000000"; @@ -1225,14 +1224,14 @@ begin if DDR_REFRESH_SIG_q = "1001" then -- ALLE BANKS SCHLIESSEN - VRAS <= vcc; - VWE <= vcc; - VA10_2 <= vcc; - FIFO_BANK_NOT_OK <= vcc; + VRAS <= '1'; + VWE <= '1'; + VA10_2 <= '1'; + FIFO_BANK_NOT_OK <= '1'; DDR_SM_d <= "100001"; else - VCAS <= vcc; - VRAS <= vcc; + VCAS <= '1'; + VRAS <= '1'; DDR_SM_d <= "100000"; end if; @@ -1421,7 +1420,4 @@ begin VA(11) <= VA11_1 or VA11_2; VA(12) <= VA12_1 or VA12_2; --- Define power signal(s) - vcc <= '1'; - gnd <= '0'; end architecture rtl; diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 4034aa9..699c1d4 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -604,9 +604,9 @@ BEGIN ); - nWR_GATE <= NOT(WR_GATE); + nWR_GATE <= not(WR_GATE); - nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA); + nFB_TA <= not(Video_TA or INT_HANDLER_TA or DSP_TA or FALCON_IO_TA); CLK33M <= MAIN_CLK; From 790663a7cf572558095cfe46a58ac2d2e9eb1850 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 27 Apr 2016 11:32:14 +0000 Subject: [PATCH 094/127] remove unneeded component declarations --- .../Interrupt_Handler/interrupt_handler.vhd | 21 +- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 12 +- FPGA_Quartus_13.1/Video/video.vhd | 892 ++-------- .../Video/video_mod_mux_clutctr.vhd | 41 +- FPGA_Quartus_13.1/firebee1.qsf | 1490 ++++++++--------- FPGA_Quartus_13.1/firebee1.vhd | 98 +- 6 files changed, 1005 insertions(+), 1549 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 2c56b5b..74699d5 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -5096,8 +5096,7 @@ BEGIN INT_CTR0_clk_ctrl <= MAIN_CLK; -- $10000/4 - INT_CTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000100000000000000"); + INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4000" else '0'; INT_CTR_d <= FB_AD; INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); @@ -5109,8 +5108,10 @@ BEGIN INT_ENA0_clrn_ctrl <= nRSTO; -- $10004/4 - INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000100000000000001"); + int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4001"; + + -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + -- "00000000000100000000000001"); INT_ENA_d <= FB_AD; INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); @@ -5121,8 +5122,8 @@ BEGIN INT_CLEAR0_clk_ctrl <= MAIN_CLK; -- $10008/4 - INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000100000000000010"); + int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4002" else '0'; + -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010"); INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) @@ -5134,8 +5135,10 @@ BEGIN -- INTERRUPT LATCH REGISTER READ ONLY -- $1000C/4 - INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = - "00000000000100000000000011"); + + int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4003"; + -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + -- "00000000000100000000000011"); -- INTERRUPT nIRQ(2) <= not (HSYNC and INT_ENA_q(26)); @@ -6238,7 +6241,7 @@ BEGIN u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); FB_AD(7 DOWNTO 0) <= u3_tridata; - INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS; + INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs; -- Assignments added to explicitly combine the diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index b083539..933b8b2 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -20,11 +20,11 @@ -- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) -- Created on Fri Oct 16 15:40:59 2009 -LIBRARY ieee; - USE ieee.std_logic_1164.ALL; - USE ieee.numeric_std.ALL; +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; -ENTITY blitter IS +entity blitter is -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( @@ -50,7 +50,7 @@ ENTITY blitter IS BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); BLITTER_SIG : OUT std_logic; BLITTER_WR : OUT std_logic; - BLITTER_TA : OUT std_logic; + blitter_ta : OUT std_logic; FB_AD : INOUT std_logic_vector(31 DOWNTO 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! @@ -67,6 +67,6 @@ BEGIN BLITTER_ADR <= x"76543210"; BLITTER_SIG <= '0'; BLITTER_WR <= '0'; - BLITTER_TA <= '0'; + blitter_ta <= '0'; END rtl; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 0706292..f99242b 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -72,638 +72,90 @@ END video; ARCHITECTURE rtl OF video IS ATTRIBUTE black_box : BOOLEAN; ATTRIBUTE noopt : BOOLEAN; - - COMPONENT mux41_0 - PORT - ( - S0 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic - ); - END COMPONENT mux41_0; - - ATTRIBUTE black_box OF mux41_0: COMPONENT IS true; - ATTRIBUTE noopt OF mux41_0: COMPONENT IS true; - - COMPONENT mux41_1 - PORT - ( - S0 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic - ); - END COMPONENT mux41_1; - - ATTRIBUTE black_box OF mux41_1: COMPONENT IS true; - ATTRIBUTE noopt OF mux41_1: COMPONENT IS true; - - COMPONENT mux41_2 - PORT - ( - S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic - ); - END COMPONENT mux41_2; - - ATTRIBUTE black_box OF mux41_2: COMPONENT IS true; - ATTRIBUTE noopt OF mux41_2: COMPONENT IS true; - - COMPONENT mux41_3 - PORT - ( - S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic - ); - END COMPONENT mux41_3; - - ATTRIBUTE black_box OF mux41_3: COMPONENT IS true; - ATTRIBUTE noopt OF mux41_3: COMPONENT IS true; - - COMPONENT mux41_4 - PORT - ( - S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic - ); - END COMPONENT; - - ATTRIBUTE black_box OF mux41_4: COMPONENT IS true; - ATTRIBUTE noopt OF mux41_4: COMPONENT IS true; - - COMPONENT mux41_5 - PORT - ( - S0 : IN std_logic; - D2 : IN std_logic; - S1 : IN std_logic; - D0 : IN std_logic; - INH : IN std_logic; - D1 : IN std_logic; - Q : OUT std_logic - ); - END COMPONENT; - - ATTRIBUTE black_box OF mux41_5: COMPONENT IS true; - ATTRIBUTE noopt OF mux41_5: COMPONENT IS true; - - COMPONENT altdpram2 - PORT - ( - wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(7 DOWNTO 0); - address_b : IN std_logic_vector(7 DOWNTO 0); - data_a : IN std_logic_vector(7 DOWNTO 0); - data_b : IN std_logic_vector(7 DOWNTO 0); - q_a : OUT std_logic_vector(7 DOWNTO 0); - q_b : OUT std_logic_vector(7 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT ddr_ctr - PORT - ( - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - DDR_SYNC_66M : IN std_logic; - BLITTER_SIG : IN std_logic; - BLITTER_WR : IN std_logic; - DDRCLK0 : IN std_logic; - CLK33M : IN std_logic; - CLR_FIFO : IN std_logic; - BLITTER_ADR : IN std_logic_vector(31 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - FIFO_MW : IN std_logic_vector(8 DOWNTO 0); - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - nVWE : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - VCKE : OUT std_logic; - nVCAS : OUT std_logic; - SR_FIFO_WRE : OUT std_logic; - SR_DDR_FB : OUT std_logic; - SR_DDR_WR : OUT std_logic; - SR_DDRWR_D_SEL : OUT std_logic; - VIDEO_DDR_TA : OUT std_logic; - SR_BLITTER_DACK : OUT std_logic; - DDRWR_D_SEL1 : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - FB_LE : OUT std_logic_vector(3 DOWNTO 0); - FB_VDOE : OUT std_logic_vector(3 DOWNTO 0); - SR_VDMP : OUT std_logic_vector(7 DOWNTO 0); - VA : OUT std_logic_vector(12 DOWNTO 0); - VDM_SEL : OUT std_logic_vector(3 DOWNTO 0) - ); - END COMPONENT ddr_ctr; - - COMPONENT altdpram1 - PORT - ( - wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(7 DOWNTO 0); - address_b : IN std_logic_vector(7 DOWNTO 0); - data_a : IN std_logic_vector(5 DOWNTO 0); - data_b : IN std_logic_vector(5 DOWNTO 0); - q_a : OUT std_logic_vector(5 DOWNTO 0); - q_b : OUT std_logic_vector(5 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_fifo_dc0 - PORT - ( - wrreq : IN std_logic; - wrclk : IN std_logic; - rdreq : IN std_logic; - rdclk : IN std_logic; - aclr : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - rdempty : OUT std_logic; - q : OUT std_logic_vector(127 DOWNTO 0); - wrusedw : OUT std_logic_vector(8 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT altddio_bidir0 - PORT - ( - oe : IN std_logic; - inclock : IN std_logic; - outclock : IN std_logic; - datain_h : IN std_logic_vector(31 DOWNTO 0); - datain_l : IN std_logic_vector(31 DOWNTO 0); - padio : INOUT std_logic_vector(31 DOWNTO 0); - combout : OUT std_logic_vector(31 DOWNTO 0); - dataout_h : OUT std_logic_vector(31 DOWNTO 0); - dataout_l : OUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_ff4 - PORT - ( - clock : IN std_logic; - data : IN std_logic_vector(15 DOWNTO 0); - q : OUT std_logic_vector(15 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_muxvdm - PORT - ( - data0x : IN std_logic_vector(127 DOWNTO 0); - data10x : IN std_logic_vector(127 DOWNTO 0); - data11x : IN std_logic_vector(127 DOWNTO 0); - data12x : IN std_logic_vector(127 DOWNTO 0); - data13x : IN std_logic_vector(127 DOWNTO 0); - data14x : IN std_logic_vector(127 DOWNTO 0); - data15x : IN std_logic_vector(127 DOWNTO 0); - data1x : IN std_logic_vector(127 DOWNTO 0); - data2x : IN std_logic_vector(127 DOWNTO 0); - data3x : IN std_logic_vector(127 DOWNTO 0); - data4x : IN std_logic_vector(127 DOWNTO 0); - data5x : IN std_logic_vector(127 DOWNTO 0); - data6x : IN std_logic_vector(127 DOWNTO 0); - data7x : IN std_logic_vector(127 DOWNTO 0); - data8x : IN std_logic_vector(127 DOWNTO 0); - data9x : IN std_logic_vector(127 DOWNTO 0); - sel : IN std_logic_vector(3 DOWNTO 0); - result : OUT std_logic_vector(127 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux3 - PORT - ( - data1 : IN std_logic; - data0 : IN std_logic; - sel : IN std_logic; - result : OUT std_logic - ); - END COMPONENT; - - COMPONENT lpm_bustri_long - PORT - ( - enabledt : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - tridata : INOUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_ff5 - PORT - ( - clock : IN std_logic; - data : IN std_logic_vector(7 DOWNTO 0); - q : OUT std_logic_vector(7 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_ff1 - PORT - ( - clock : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_ff0 - PORT - ( - clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT altddio_out0 - PORT - ( - outclock : IN std_logic; - datain_h : IN std_logic_vector(3 DOWNTO 0); - datain_l : IN std_logic_vector(3 DOWNTO 0); - dataout : OUT std_logic_vector(3 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux0 - PORT - ( - clock : IN std_logic; - data0x : IN std_logic_vector(31 DOWNTO 0); - data1x : IN std_logic_vector(31 DOWNTO 0); - data2x : IN std_logic_vector(31 DOWNTO 0); - data3x : IN std_logic_vector(31 DOWNTO 0); - sel : IN std_logic_vector(1 DOWNTO 0); - result : OUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux5 - PORT - ( - data0x : IN std_logic_vector(63 DOWNTO 0); - data1x : IN std_logic_vector(63 DOWNTO 0); - data2x : IN std_logic_vector(63 DOWNTO 0); - data3x : IN std_logic_vector(63 DOWNTO 0); - sel : IN std_logic_vector(1 DOWNTO 0); - result : OUT std_logic_vector(63 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_constant2 - PORT - ( - result : OUT std_logic_vector(7 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux1 - PORT - ( - clock : IN std_logic; - data0x : IN std_logic_vector(15 DOWNTO 0); - data1x : IN std_logic_vector(15 DOWNTO 0); - data2x : IN std_logic_vector(15 DOWNTO 0); - data3x : IN std_logic_vector(15 DOWNTO 0); - data4x : IN std_logic_vector(15 DOWNTO 0); - data5x : IN std_logic_vector(15 DOWNTO 0); - data6x : IN std_logic_vector(15 DOWNTO 0); - data7x : IN std_logic_vector(15 DOWNTO 0); - sel : IN std_logic_vector(2 DOWNTO 0); - result : OUT std_logic_vector(15 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux2 - PORT - ( - clock : IN std_logic; - data0x : IN std_logic_vector(7 DOWNTO 0); - data10x : IN std_logic_vector(7 DOWNTO 0); - data11x : IN std_logic_vector(7 DOWNTO 0); - data12x : IN std_logic_vector(7 DOWNTO 0); - data13x : IN std_logic_vector(7 DOWNTO 0); - data14x : IN std_logic_vector(7 DOWNTO 0); - data15x : IN std_logic_vector(7 DOWNTO 0); - data1x : IN std_logic_vector(7 DOWNTO 0); - data2x : IN std_logic_vector(7 DOWNTO 0); - data3x : IN std_logic_vector(7 DOWNTO 0); - data4x : IN std_logic_vector(7 DOWNTO 0); - data5x : IN std_logic_vector(7 DOWNTO 0); - data6x : IN std_logic_vector(7 DOWNTO 0); - data7x : IN std_logic_vector(7 DOWNTO 0); - data8x : IN std_logic_vector(7 DOWNTO 0); - data9x : IN std_logic_vector(7 DOWNTO 0); - sel : IN std_logic_vector(3 DOWNTO 0); - result : OUT std_logic_vector(7 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_shiftreg4 - PORT - ( - clock : IN std_logic; - shiftin : IN std_logic; - shiftout : OUT std_logic - ); - END COMPONENT; - - COMPONENT lpm_latch0 - PORT - ( - gate : IN std_logic; - data : IN std_logic_vector(31 DOWNTO 0); - q : OUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_ff6 - PORT - ( - clock : IN std_logic; - enable : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - q : OUT std_logic_vector(127 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_ff3 - PORT - ( - clock : IN std_logic; - data : IN std_logic_vector(23 DOWNTO 0); - q : OUT std_logic_vector(23 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT altddio_out2 - PORT - ( - outclock : IN std_logic; - datain_h : IN std_logic_vector(23 DOWNTO 0); - datain_l : IN std_logic_vector(23 DOWNTO 0); - dataout : OUT std_logic_vector(23 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_bustri1 - PORT - ( - enabledt : IN std_logic; - data : IN std_logic_vector(2 DOWNTO 0); - tridata : INOUT std_logic_vector(2 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_bustri_byt - PORT - ( - enabledt : IN std_logic; - data : IN std_logic_vector(7 DOWNTO 0); - tridata : INOUT std_logic_vector(7 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_constant0 - PORT - ( - result : OUT std_logic_vector(4 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_muxdz - PORT - ( - clock : IN std_logic; - clken : IN std_logic; - sel : IN std_logic; - data0x : IN std_logic_vector(127 DOWNTO 0); - data1x : IN std_logic_vector(127 DOWNTO 0); - result : OUT std_logic_vector(127 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_fifodz - PORT - ( - wrreq : IN std_logic; - rdreq : IN std_logic; - clock : IN std_logic; - aclr : IN std_logic; - data : IN std_logic_vector(127 DOWNTO 0); - q : OUT std_logic_vector(127 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_bustri3 - PORT - ( - enabledt : IN std_logic; - data : IN std_logic_vector(5 DOWNTO 0); - tridata : INOUT std_logic_vector(5 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux6 - PORT - ( - clock : IN std_logic; - data0x : IN std_logic_vector(23 DOWNTO 0); - data1x : IN std_logic_vector(23 DOWNTO 0); - data2x : IN std_logic_vector(23 DOWNTO 0); - data3x : IN std_logic_vector(23 DOWNTO 0); - data4x : IN std_logic_vector(23 DOWNTO 0); - data5x : IN std_logic_vector(23 DOWNTO 0); - data6x : IN std_logic_vector(23 DOWNTO 0); - data7x : IN std_logic_vector(23 DOWNTO 0); - sel : IN std_logic_vector(2 DOWNTO 0); - result : OUT std_logic_vector(23 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_constant1 - PORT - ( - result : OUT std_logic_vector(1 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_mux4 - PORT - ( - sel : IN std_logic; - data0x : IN std_logic_vector(6 DOWNTO 0); - data1x : IN std_logic_vector(6 DOWNTO 0); - result : OUT std_logic_vector(6 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_constant3 - PORT - ( - result : OUT std_logic_vector(6 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_shiftreg6 - PORT - ( - clock : IN std_logic; - shiftin : IN std_logic; - q : OUT std_logic_vector(4 DOWNTO 0) - ); - END COMPONENT; - - COMPONENT lpm_shiftreg0 - PORT - ( - load : IN std_logic; - clock : IN std_logic; - shiftin : IN std_logic; - data : IN std_logic_vector(15 DOWNTO 0); - shiftout : OUT std_logic - ); - END COMPONENT; - - COMPONENT altdpram0 - PORT - ( - wren_a : IN std_logic; - wren_b : IN std_logic; - clock_a : IN std_logic; - clock_b : IN std_logic; - address_a : IN std_logic_vector(3 DOWNTO 0); - address_b : IN std_logic_vector(3 DOWNTO 0); - data_a : IN std_logic_vector(2 DOWNTO 0); - data_b : IN std_logic_vector(2 DOWNTO 0); - q_a : OUT std_logic_vector(2 DOWNTO 0); - q_b : OUT std_logic_vector(2 DOWNTO 0) - ); - END COMPONENT; - - SIGNAL ACP_CLUT_RD : std_logic; - SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); - SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_ON : std_logic; - SIGNAL BLITTER_RUN : std_logic; - SIGNAL BLITTER_SIG : std_logic; - SIGNAL BLITTER_TA : std_logic; - SIGNAL BLITTER_WR : std_logic; - SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); - SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); - SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); - SIGNAL CCA : std_logic_vector(23 DOWNTO 0); - SIGNAL CCF : std_logic_vector(23 DOWNTO 0); - SIGNAL CCS : std_logic_vector(23 DOWNTO 0); - SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); - SIGNAL CLR_FIFO : std_logic; - SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); - SIGNAL CLUT_ADR1A : std_logic; - SIGNAL CLUT_ADR2A : std_logic; - SIGNAL CLUT_ADR3A : std_logic; - SIGNAL CLUT_ADR4A : std_logic; - SIGNAL CLUT_ADR5A : std_logic; - SIGNAL CLUT_ADR6A : std_logic; - SIGNAL CLUT_ADR7A : std_logic; - SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); - SIGNAL COLOR1 : std_logic; - SIGNAL COLOR2 : std_logic; - SIGNAL COLOR4 : std_logic; - SIGNAL COLOR8 : std_logic; - SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); - SIGNAL DDR_WR : std_logic; - SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); - SIGNAL DOP_FIFO_CLR : std_logic; - SIGNAL FALCON_CLUT_RDH : std_logic; - SIGNAL FALCON_CLUT_RDL : std_logic; - SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); - SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); - SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); - SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); - SIGNAL FIFO_RDE : std_logic; - SIGNAL FIFO_WRE : std_logic; - SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic := '0'; - SIGNAL pixel_clk_i : std_logic; - SIGNAL SR_BLITTER_DACK : std_logic; - SIGNAL SR_DDR_FB : std_logic; - SIGNAL SR_DDR_WR : std_logic; - SIGNAL SR_DDRWR_D_SEL : std_logic; - SIGNAL SR_FIFO_WRE : std_logic; - SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL ST_CLUT_RD : std_logic; - SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); - SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); - SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL VDOUT_OE : std_logic; - SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); - SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); - SIGNAL VDR : std_logic_vector(31 DOWNTO 0); - SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); - SIGNAL VIDEO_DDR_TA : std_logic; - SIGNAL VIDEO_MOD_TA : std_logic; - SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); - SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); - SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_0 : std_logic; - SIGNAL SYNTHESIZED_WIRE_1 : std_logic; - SIGNAL SYNTHESIZED_WIRE_2 : std_logic; - SIGNAL SYNTHESIZED_WIRE_3 : std_logic; - SIGNAL SYNTHESIZED_WIRE_4 : std_logic; - SIGNAL SYNTHESIZED_WIRE_5 : std_logic; + SIGNAL ACP_CLUT_RD : std_logic; + SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); + SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); + SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); + SIGNAL BLITTER_ON : std_logic; + SIGNAL BLITTER_RUN : std_logic; + SIGNAL BLITTER_SIG : std_logic; + SIGNAL BLITTER_TA : std_logic; + SIGNAL BLITTER_WR : std_logic; + SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); + SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); + SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); + SIGNAL CCA : std_logic_vector(23 DOWNTO 0); + SIGNAL CCF : std_logic_vector(23 DOWNTO 0); + SIGNAL CCS : std_logic_vector(23 DOWNTO 0); + SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); + SIGNAL CLR_FIFO : std_logic; + SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); + SIGNAL CLUT_ADR1A : std_logic; + SIGNAL CLUT_ADR2A : std_logic; + SIGNAL CLUT_ADR3A : std_logic; + SIGNAL CLUT_ADR4A : std_logic; + SIGNAL CLUT_ADR5A : std_logic; + SIGNAL CLUT_ADR6A : std_logic; + SIGNAL CLUT_ADR7A : std_logic; + SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); + SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); + SIGNAL COLOR1 : std_logic; + SIGNAL COLOR2 : std_logic; + SIGNAL COLOR4 : std_logic; + SIGNAL COLOR8 : std_logic; + SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); + SIGNAL DDR_WR : std_logic; + SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); + SIGNAL DOP_FIFO_CLR : std_logic; + SIGNAL FALCON_CLUT_RDH : std_logic; + SIGNAL FALCON_CLUT_RDL : std_logic; + SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); + SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); + SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); + SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); + SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); + SIGNAL FIFO_RDE : std_logic; + SIGNAL FIFO_WRE : std_logic; + SIGNAL INTER_ZEI : std_logic; + SIGNAL nFB_BURST : std_logic := '0'; + SIGNAL pixel_clk_i : std_logic; + SIGNAL SR_BLITTER_DACK : std_logic; + SIGNAL SR_DDR_FB : std_logic; + SIGNAL SR_DDR_WR : std_logic; + SIGNAL SR_DDRWR_D_SEL : std_logic; + SIGNAL SR_FIFO_WRE : std_logic; + SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL ST_CLUT_RD : std_logic; + SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); + SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); + SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); + SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); + SIGNAL VDOUT_OE : std_logic; + SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); + SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); + SIGNAL VDR : std_logic_vector(31 DOWNTO 0); + SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); + SIGNAL VIDEO_DDR_TA : std_logic; + SIGNAL VIDEO_MOD_TA : std_logic; + SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); + SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); + SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); + SIGNAL SYNTHESIZED_WIRE_0 : std_logic; + SIGNAL SYNTHESIZED_WIRE_1 : std_logic; + SIGNAL SYNTHESIZED_WIRE_2 : std_logic; + SIGNAL SYNTHESIZED_WIRE_3 : std_logic; + SIGNAL SYNTHESIZED_WIRE_4 : std_logic; + SIGNAL SYNTHESIZED_WIRE_5 : std_logic; SIGNAL SYNTHESIZED_WIRE_60 : std_logic; - SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); - SIGNAL DFF_inst93 : std_logic; - SIGNAL SYNTHESIZED_WIRE_8 : std_logic; - SIGNAL SYNTHESIZED_WIRE_9 : std_logic; + SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); + SIGNAL DFF_inst93 : std_logic; + SIGNAL SYNTHESIZED_WIRE_8 : std_logic; + SIGNAL SYNTHESIZED_WIRE_9 : std_logic; SIGNAL SYNTHESIZED_WIRE_61 : std_logic; SIGNAL SYNTHESIZED_WIRE_11 : std_logic_vector(31 DOWNTO 0); SIGNAL SYNTHESIZED_WIRE_12 : std_logic_vector(7 DOWNTO 0); @@ -828,7 +280,7 @@ BEGIN GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); - ACP_CLUT_RAM : altdpram2 + ACP_CLUT_RAM : entity work.altdpram2 PORT MAP ( wren_a => ACP_CLUT_WR(3), @@ -844,7 +296,7 @@ BEGIN ); - ACP_CLUT_RAM54 : altdpram2 + ACP_CLUT_RAM54 : entity work.altdpram2 PORT MAP ( wren_a => ACP_CLUT_WR(2), @@ -860,7 +312,7 @@ BEGIN ); - ACP_CLUT_RAM55 : altdpram2 + ACP_CLUT_RAM55 : entity work.altdpram2 PORT MAP ( wren_a => ACP_CLUT_WR(1), @@ -876,7 +328,7 @@ BEGIN ); - i_blitter : work.blitter + i_blitter : entity work.blitter PORT MAP ( nRSTO => nRSTO, @@ -900,13 +352,13 @@ BEGIN BLITTER_RUN => BLITTER_RUN, BLITTER_SIG => BLITTER_SIG, BLITTER_WR => BLITTER_WR, - BLITTER_TA => BLITTER_TA, + blitter_ta => blitter_ta, BLITTER_ADR => BLITTER_ADR, BLITTER_DOUT => BLITTER_DOUT ); - i_ddr_ctr : ddr_ctr + i_ddr_ctr : entity work.ddr_ctr PORT MAP ( nFB_CS1 => nFB_CS1, @@ -951,7 +403,7 @@ BEGIN ); - FALCON_CLUT_BLUE : altdpram1 + FALCON_CLUT_BLUE : entity work.altdpram1 PORT MAP ( wren_a => FALCON_CLUT_WR(3), @@ -967,7 +419,7 @@ BEGIN ); - FALCON_CLUT_GREEN : altdpram1 + FALCON_CLUT_GREEN : entity work.altdpram1 PORT MAP ( wren_a => FALCON_CLUT_WR(1), @@ -983,7 +435,7 @@ BEGIN ); - FALCON_CLUT_RED : altdpram1 + FALCON_CLUT_RED : entity work.altdpram1 PORT MAP ( wren_a => FALCON_CLUT_WR(0), @@ -999,7 +451,7 @@ BEGIN ); - inst : lpm_fifo_dc0 + inst : entity work.lpm_fifo_dc0 PORT MAP ( wrreq => FIFO_WRE, @@ -1013,7 +465,7 @@ BEGIN ); - inst1 : altddio_bidir0 + inst1 : entity work.altddio_bidir0 PORT MAP ( oe => VDOUT_OE, @@ -1028,7 +480,7 @@ BEGIN ); - inst10 : lpm_ff4 + inst10 : entity work.lpm_ff4 PORT MAP ( clock => pixel_clk_i, @@ -1037,7 +489,7 @@ BEGIN ); - inst100 : lpm_muxvdm + inst100 : entity work.lpm_muxvdm PORT MAP ( data0x => VDMB, @@ -1061,7 +513,7 @@ BEGIN ); - inst102 : lpm_mux3 + inst102 : entity work.lpm_mux3 PORT MAP ( data1 => DFF_inst93, @@ -1080,7 +532,7 @@ BEGIN SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; - inst108 : lpm_bustri_long + inst108 : entity work.lpm_bustri_long PORT MAP ( enabledt => FB_VDOE(0), @@ -1089,7 +541,7 @@ BEGIN ); - inst109 : lpm_bustri_long + inst109 : entity work.lpm_bustri_long PORT MAP ( enabledt => FB_VDOE(1), @@ -1098,7 +550,7 @@ BEGIN ); - inst11 : lpm_ff5 + inst11 : entity work.lpm_ff5 PORT MAP ( clock => pixel_clk_i, @@ -1107,7 +559,7 @@ BEGIN ); - inst110 : lpm_bustri_long + inst110 : entity work.lpm_bustri_long PORT MAP ( enabledt => FB_VDOE(2), @@ -1116,7 +568,7 @@ BEGIN ); - inst119 : lpm_bustri_long + inst119 : entity work.lpm_bustri_long PORT MAP ( enabledt => FB_VDOE(3), @@ -1125,7 +577,7 @@ BEGIN ); - inst12 : lpm_ff1 + inst12 : entity work.lpm_ff1 PORT MAP ( clock => DDRCLK(0), @@ -1134,7 +586,7 @@ BEGIN ); - inst13 : lpm_ff0 + inst13 : entity work.lpm_ff0 PORT MAP ( clock => DDR_SYNC_66M, @@ -1144,7 +596,7 @@ BEGIN ); - inst14 : lpm_ff0 + inst14 : entity work.lpm_ff0 PORT MAP ( clock => DDR_SYNC_66M, @@ -1154,7 +606,7 @@ BEGIN ); - inst15 : lpm_ff0 + inst15 : entity work.lpm_ff0 PORT MAP ( clock => DDR_SYNC_66M, @@ -1164,7 +616,7 @@ BEGIN ); - inst16 : lpm_ff0 + inst16 : entity work.lpm_ff0 PORT MAP ( clock => DDR_SYNC_66M, @@ -1174,7 +626,7 @@ BEGIN ); - inst17 : lpm_ff0 + inst17 : entity work.lpm_ff0 PORT MAP ( clock => DDRCLK(0), @@ -1184,7 +636,7 @@ BEGIN ); - inst18 : lpm_ff0 + inst18 : entity work.lpm_ff0 PORT MAP ( clock => DDRCLK(0), @@ -1194,7 +646,7 @@ BEGIN ); - inst19 : lpm_ff0 + inst19 : entity work.lpm_ff0 PORT MAP ( clock => DDRCLK(0), @@ -1204,7 +656,7 @@ BEGIN ); - inst2 : altddio_out0 + inst2 : entity work.altddio_out0 PORT MAP ( outclock => DDRCLK(3), @@ -1214,7 +666,7 @@ BEGIN ); - inst20 : lpm_ff1 + inst20 : entity work.lpm_ff1 PORT MAP ( clock => DDRCLK(0), @@ -1223,7 +675,7 @@ BEGIN ); - inst21 : lpm_mux0 + inst21 : entity work.lpm_mux0 PORT MAP ( clock => pixel_clk_i, @@ -1236,7 +688,7 @@ BEGIN ); - inst22 : lpm_mux5 + inst22 : entity work.lpm_mux5 PORT MAP ( data0x => FB_DDR(127 DOWNTO 64), @@ -1248,14 +700,14 @@ BEGIN ); - inst23 : lpm_constant2 + inst23 : entity work.lpm_constant2 PORT MAP ( result => GDFX_TEMP_SIGNAL_16 ); - inst24 : lpm_mux1 + inst24 : entity work.lpm_mux1 PORT MAP ( clock => pixel_clk_i, @@ -1272,7 +724,7 @@ BEGIN ); - inst25 : lpm_mux2 + inst25 : entity work.lpm_mux2 PORT MAP ( clock => pixel_clk_i, @@ -1297,7 +749,7 @@ BEGIN ); - inst26 : lpm_shiftreg4 + inst26 : entity work.lpm_shiftreg4 PORT MAP ( clock => DDRCLK(0), @@ -1306,7 +758,7 @@ BEGIN ); - inst27 : lpm_latch0 + inst27 : entity work.lpm_latch0 PORT MAP ( gate => DDR_SYNC_66M, @@ -1317,7 +769,7 @@ BEGIN CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; - inst3 : lpm_ff1 + inst3 : entity work.lpm_ff1 PORT MAP ( clock => DDRCLK(0), @@ -1332,7 +784,7 @@ BEGIN SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; - inst36 : lpm_ff6 + inst36 : entity work.lpm_ff6 PORT MAP ( clock => DDRCLK(0), @@ -1342,9 +794,9 @@ BEGIN ); VDOUT_OE <= DDR_WR OR SR_DDR_WR; - VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA; + video_ta <= blitter_ta or video_mod_ta or video_ddr_ta; - inst4 : lpm_ff1 + inst4 : entity work.lpm_ff1 PORT MAP ( clock => DDRCLK(0), @@ -1353,7 +805,7 @@ BEGIN ); - inst40 : mux41_0 + inst40 : entity work.mux41_0 PORT MAP ( S0 => COLOR2, @@ -1365,7 +817,7 @@ BEGIN ); - inst41 : mux41_1 + inst41 : entity work.mux41_1 PORT MAP ( S0 => COLOR2, @@ -1377,7 +829,7 @@ BEGIN ); - inst42 : mux41_2 + inst42 : entity work.mux41_2 PORT MAP ( S0 => COLOR2, @@ -1390,7 +842,7 @@ BEGIN ); - inst43 : mux41_3 + inst43 : entity work.mux41_3 PORT MAP ( S0 => COLOR2, @@ -1403,7 +855,7 @@ BEGIN ); - inst44 : mux41_4 + inst44 : entity work.mux41_4 PORT MAP ( S0 => COLOR2, @@ -1416,7 +868,7 @@ BEGIN ); - inst45 : mux41_5 + inst45 : entity work.mux41_5 PORT MAP ( S0 => COLOR2, @@ -1429,7 +881,7 @@ BEGIN ); - inst46 : lpm_ff3 + inst46 : entity work.lpm_ff3 PORT MAP ( clock => pixel_clk_i, @@ -1438,7 +890,7 @@ BEGIN ); - inst47 : lpm_ff3 + inst47 : entity work.lpm_ff3 PORT MAP ( clock => pixel_clk_i, @@ -1448,7 +900,7 @@ BEGIN - inst49 : lpm_ff3 + inst49 : entity work.lpm_ff3 PORT MAP ( clock => pixel_clk_i, @@ -1457,7 +909,7 @@ BEGIN ); - inst5 : altddio_out2 + inst5 : entity work.altddio_out2 PORT MAP ( outclock => pixel_clk_i, @@ -1468,7 +920,7 @@ BEGIN - inst51 : lpm_bustri1 + inst51 : entity work.lpm_bustri1 PORT MAP ( enabledt => ST_CLUT_RD, @@ -1477,7 +929,7 @@ BEGIN ); - inst52 : lpm_ff3 + inst52 : entity work.lpm_ff3 PORT MAP ( clock => pixel_clk_i, @@ -1486,7 +938,7 @@ BEGIN ); - inst53 : lpm_bustri_byt + inst53 : entity work.lpm_bustri_byt PORT MAP ( enabledt => ACP_CLUT_RD, @@ -1495,7 +947,7 @@ BEGIN ); - inst54 : lpm_constant0 + inst54 : entity work.lpm_constant0 PORT MAP ( result => CCS(20 DOWNTO 16) @@ -1503,7 +955,7 @@ BEGIN - inst56 : lpm_bustri1 + inst56 : entity work.lpm_bustri1 PORT MAP ( enabledt => ST_CLUT_RD, @@ -1512,7 +964,7 @@ BEGIN ); - inst57 : lpm_bustri_byt + inst57 : entity work.lpm_bustri_byt PORT MAP ( enabledt => ACP_CLUT_RD, @@ -1521,7 +973,7 @@ BEGIN ); - inst58 : lpm_bustri_byt + inst58 : entity work.lpm_bustri_byt PORT MAP ( enabledt => ACP_CLUT_RD, @@ -1530,7 +982,7 @@ BEGIN ); - inst59 : lpm_constant0 + inst59 : entity work.lpm_constant0 PORT MAP ( result => CCS(12 DOWNTO 8) @@ -1539,7 +991,7 @@ BEGIN - inst61 : lpm_bustri1 + inst61 : entity work.lpm_bustri1 PORT MAP ( enabledt => ST_CLUT_RD, @@ -1548,7 +1000,7 @@ BEGIN ); - inst62 : lpm_muxdz + inst62 : entity work.lpm_muxdz PORT MAP ( clock => pixel_clk_i, @@ -1560,7 +1012,7 @@ BEGIN ); - inst63 : lpm_fifodz + inst63 : entity work.lpm_fifodz PORT MAP ( wrreq => SYNTHESIZED_WIRE_60, @@ -1572,7 +1024,7 @@ BEGIN ); - inst64 : lpm_constant0 + inst64 : entity work.lpm_constant0 PORT MAP ( result => CCS(4 DOWNTO 0) @@ -1582,7 +1034,7 @@ BEGIN SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; - inst66 : lpm_bustri3 + inst66 : entity work.lpm_bustri3 PORT MAP ( enabledt => FALCON_CLUT_RDH, @@ -1594,7 +1046,7 @@ BEGIN SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); - inst7 : lpm_mux6 + inst7 : entity work.lpm_mux6 PORT MAP ( clock => pixel_clk_i, @@ -1611,7 +1063,7 @@ BEGIN ); - inst70 : lpm_bustri3 + inst70 : entity work.lpm_bustri3 PORT MAP ( enabledt => FALCON_CLUT_RDH, @@ -1620,7 +1072,7 @@ BEGIN ); - inst71 : lpm_ff6 + inst71 : entity work.lpm_ff6 PORT MAP ( clock => DDRCLK(0), @@ -1632,7 +1084,7 @@ BEGIN - inst74 : lpm_bustri3 + inst74 : entity work.lpm_bustri3 PORT MAP ( enabledt => FALCON_CLUT_RDL, @@ -1643,7 +1095,7 @@ BEGIN - inst77 : lpm_constant1 + inst77 : entity work.lpm_constant1 PORT MAP ( result => CCF(1 DOWNTO 0) @@ -1655,14 +1107,14 @@ BEGIN - inst80 : lpm_constant1 + inst80 : entity work.lpm_constant1 PORT MAP ( result => CCF(9 DOWNTO 8) ); - inst81 : lpm_mux4 + inst81 : entity work.lpm_mux4 PORT MAP ( sel => COLOR1, @@ -1672,14 +1124,14 @@ BEGIN ); - inst82 : lpm_constant3 + inst82 : entity work.lpm_constant3 PORT MAP ( result => SYNTHESIZED_WIRE_47 ); - inst83 : lpm_constant1 + inst83 : entity work.lpm_constant1 PORT MAP ( result => CCF(17 DOWNTO 16) @@ -1705,7 +1157,7 @@ BEGIN END PROCESS; - inst89 : lpm_shiftreg6 + inst89 : entity work.lpm_shiftreg6 PORT MAP ( clock => DDRCLK(0), @@ -1714,7 +1166,7 @@ BEGIN ); - inst9 : lpm_ff1 + inst9 : entity work.lpm_ff1 PORT MAP ( clock => pixel_clk_i, @@ -1731,7 +1183,7 @@ BEGIN END PROCESS; - inst92 : lpm_shiftreg6 + inst92 : entity work.lpm_shiftreg6 PORT MAP ( clock => DDRCLK(0), @@ -1748,7 +1200,7 @@ BEGIN END PROCESS; - inst94 : lpm_ff6 + inst94 : entity work.lpm_ff6 PORT MAP ( clock => DDRCLK(0), @@ -1767,7 +1219,7 @@ BEGIN - inst97 : lpm_ff5 + inst97 : entity work.lpm_ff5 PORT MAP ( clock => DDRCLK(2), @@ -1776,7 +1228,7 @@ BEGIN ); - sr0 : lpm_shiftreg0 + sr0 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1787,7 +1239,7 @@ BEGIN ); - sr1 : lpm_shiftreg0 + sr1 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1798,7 +1250,7 @@ BEGIN ); - sr2 : lpm_shiftreg0 + sr2 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1809,7 +1261,7 @@ BEGIN ); - sr3 : lpm_shiftreg0 + sr3 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1820,7 +1272,7 @@ BEGIN ); - sr4 : lpm_shiftreg0 + sr4 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1831,7 +1283,7 @@ BEGIN ); - sr5 : lpm_shiftreg0 + sr5 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1842,7 +1294,7 @@ BEGIN ); - sr6 : lpm_shiftreg0 + sr6 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1853,7 +1305,7 @@ BEGIN ); - sr7 : lpm_shiftreg0 + sr7 : entity work.lpm_shiftreg0 PORT MAP ( load => SYNTHESIZED_WIRE_64, @@ -1864,7 +1316,7 @@ BEGIN ); - ST_CLUT_BLUE : altdpram0 + ST_CLUT_BLUE : entity work.altdpram0 PORT MAP ( wren_a => ST_CLUT_WR(1), @@ -1880,7 +1332,7 @@ BEGIN ); - ST_CLUT_GREEN : altdpram0 + ST_CLUT_GREEN : entity work.altdpram0 PORT MAP ( wren_a => ST_CLUT_WR(1), @@ -1896,7 +1348,7 @@ BEGIN ); - ST_CLUT_RED : altdpram0 + ST_CLUT_RED : entity work.altdpram0 PORT MAP ( wren_a => ST_CLUT_WR(0), @@ -1912,7 +1364,7 @@ BEGIN ); - i_video_mod_mux_clutctr : work.video_mod_mux_clutctr + i_video_mod_mux_clutctr : entity work.video_mod_mux_clutctr PORT MAP ( nRSTO => nRSTO, diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 56110e5..1a1993d 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -116,7 +116,7 @@ end video_mod_mux_clutctr; architecture rtl of video_mod_mux_clutctr is -- DIV. CONTROL REGISTER -- BRAUCHT EIN WAITSTAT - -- LÄNGE HSYNC PULS IN PIXEL_CLK + -- LÄNGE HSYNC PULS IN PIXEL_CLK -- LETZTES PIXEL EINER ZEILE ERREICHT -- ATARI RESOLUTION -- HORIZONTAL TIMING 640x480 @@ -971,7 +971,8 @@ begin -- ST SHIFT MODE -- $F8260/2 - ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); + st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0'; + -- ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); ST_SHIFT_MODE_d <= FB_AD(25 downto 24); ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); @@ -1027,7 +1028,7 @@ begin nPD_VGA <= ACP_VCTR_q(1); -- ATARI MODUS - -- WENN 1 AUTOMATISCHE AUFLÖSUNG + -- WENN 1 AUTOMATISCHE AUFLÖSUNG ATARI_SYNC <= ACP_VCTR_q(26); -- HORIZONTAL TIMING 640x480 @@ -1310,7 +1311,7 @@ begin u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); FB_AD(15 downto 0) <= u1_tridata; - VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or + video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; @@ -1331,7 +1332,7 @@ begin (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); -- ------------------------------------------------------------ - -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK + -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -- -------------------------------------------------------------- -- 320 pixels, 32 MHz, RGB @@ -1378,7 +1379,7 @@ begin VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); --- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START +-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; -- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON @@ -1457,7 +1458,7 @@ begin VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - -- ZÄHLER + -- ZÄHLER LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); @@ -1469,7 +1470,7 @@ begin -- 1 ZEILE DAVOR ON OFF DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); - -- AM ZEILENENDE ÜBERNEHMEN + -- AM ZEILENENDE ÃœBERNEHMEN DPO_ZL_ena <= LAST_q; -- BESSER EINZELN WEGEN TIMING @@ -1485,7 +1486,7 @@ begin VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); - -- AM ZEILENENDE ÜBERNEHMEN + -- AM ZEILENENDE ÃœBERNEHMEN VCO_ZL_ena <= LAST_q; -- 1 ZEILE DAVOR ON OFF @@ -1493,7 +1494,7 @@ begin VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); - -- VERZÖGERUNG UND SYNC + -- VERZÖGERUNG UND SYNC HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); @@ -1511,7 +1512,7 @@ begin VSYNC_I0_ena_ctrl <= LAST_q; -- 3 zeilen vsync length - -- runterzählen bis 0 + -- runterzählen bis 0 VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else (others => '0'); @@ -1531,12 +1532,12 @@ begin VERZ0_d(0) <= DISP_ON_q; -- VERZ[1][0] = HSYNC_I[] != 0; - -- NUR MÖGLICH WENN BEIDE + -- NUR MÖGLICH WENN BEIDE VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); - -- NUR MÖGLICH WENN BEIDE + -- NUR MÖGLICH WENN BEIDE VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); @@ -1547,13 +1548,13 @@ begin -- nBLANK_d <= DISP_ON_q; -- HSYNC = VERZ[1][9]; - -- NUR MÖGLICH WENN BEIDE + -- NUR MÖGLICH WENN BEIDE HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); -- VSYNC = VERZ[2][9]; - -- NUR MÖGLICH WENN BEIDE + -- NUR MÖGLICH WENN BEIDE VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); @@ -1575,20 +1576,20 @@ begin -- -------------------------------------------------------- CLR_FIFO_ena <= LAST_q; - -- IN LETZTER ZEILE LÖSCHEN + -- IN LETZTER ZEILE LÖSCHEN CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); START_ZEILE_ena <= LAST_q; -- ZEILE 1 START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; @@ -1596,7 +1597,7 @@ begin -- count up if display on sonst clear bei sync pix SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index f42b241..78a9acc 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,311 +556,311 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 699c1d4..3388ae3 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -242,53 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS ); END COMPONENT altpll4; - COMPONENT video - PORT - ( - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - nFB_OE : IN std_logic; - FB_ALE : IN std_logic; - DDRCLK : IN std_logic_vector(3 DOWNTO 0); - DDR_SYNC_66M : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_D : IN std_logic_vector(8 DOWNTO 0); - VR_BUSY : IN std_logic; - VG : OUT std_logic_vector(7 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0); - nBLANK : OUT std_logic; - VA : OUT std_logic_vector(12 DOWNTO 0); - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - VDM : OUT std_logic_vector(3 DOWNTO 0); - nPD_VGA : OUT std_logic; - VCKE : OUT std_logic; - VSYNC : OUT std_logic; - HSYNC : OUT std_logic; - nSYNC : OUT std_logic; - VIDEO_TA : OUT std_logic; - PIXEL_CLK : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0) - ); - END COMPONENT video; +-- COMPONENT video +-- PORT +-- ( +-- FB_ADR : IN std_logic_vector(31 DOWNTO 0); +-- MAIN_CLK : IN std_logic; +-- nFB_CS1 : IN std_logic; +-- nFB_CS2 : IN std_logic; +-- nFB_CS3 : IN std_logic; +-- nFB_WR : IN std_logic; +-- FB_SIZE0 : IN std_logic; +-- FB_SIZE1 : IN std_logic; +-- nRSTO : IN std_logic; +-- nFB_OE : IN std_logic; +-- FB_ALE : IN std_logic; +-- DDRCLK : IN std_logic_vector(3 DOWNTO 0); +-- DDR_SYNC_66M : IN std_logic; +-- CLK33M : IN std_logic; +-- CLK25M : IN std_logic; +-- CLK_VIDEO : IN std_logic; +-- VR_D : IN std_logic_vector(8 DOWNTO 0); +-- VR_BUSY : IN std_logic; +-- VG : OUT std_logic_vector(7 DOWNTO 0); +-- VB : OUT std_logic_vector(7 DOWNTO 0); +-- VR : OUT std_logic_vector(7 DOWNTO 0); +-- nBLANK : OUT std_logic; +-- VA : OUT std_logic_vector(12 DOWNTO 0); +-- nVWE : OUT std_logic; +-- nVCAS : OUT std_logic; +-- nVRAS : OUT std_logic; +-- nVCS : OUT std_logic; +-- VDM : OUT std_logic_vector(3 DOWNTO 0); +-- nPD_VGA : OUT std_logic; +-- VCKE : OUT std_logic; +-- VSYNC : OUT std_logic; +-- HSYNC : OUT std_logic; +-- nSYNC : OUT std_logic; +-- VIDEO_TA : OUT std_logic; +-- PIXEL_CLK : OUT std_logic; +-- BA : OUT std_logic_vector(1 DOWNTO 0); +-- VIDEO_RECONFIG : OUT std_logic; +-- VR_WR : OUT std_logic; +-- VR_RD : OUT std_logic; +-- VDQS : INOUT std_logic_vector(3 DOWNTO 0); +-- FB_AD : INOUT std_logic_vector(31 DOWNTO 0); +-- VD : INOUT std_logic_vector(31 DOWNTO 0) +-- ); +-- END COMPONENT video; BEGIN nDREQ1 <= nDACK1; @@ -519,7 +519,7 @@ BEGIN ); - i_video : video + i_video : entity work.video PORT MAP ( MAIN_CLK => MAIN_CLK, @@ -606,7 +606,7 @@ BEGIN nWR_GATE <= not(WR_GATE); - nFB_TA <= not(Video_TA or INT_HANDLER_TA or DSP_TA or FALCON_IO_TA); + nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta); CLK33M <= MAIN_CLK; From 761b807e92594095f9ff10687f13deb63d3ec220 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 27 Apr 2016 15:08:14 +0000 Subject: [PATCH 095/127] reenable nFB_TA --- .../Interrupt_Handler/interrupt_handler.vhd | 15 +++++++++------ FPGA_Quartus_13.1/Video/video.vhd | 2 +- FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd | 4 ++-- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 74699d5..52c8703 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -394,9 +394,12 @@ ARCHITECTURE rtl OF interrupt_handler IS UPDATE_ON_2, UPDATE_ON_1, u3_enabledt, u2_enabledt, u1_enabledt, u0_enabledt, vcc, gnd, UPDATE_ON, INC_JAHR, INC_MONAT, SOMMERZEIT, WINTERZEIT, INC_TAG, INC_STD, INC_MIN, INC_SEC, UHR_DS, UHR_AS, - PSEUDO_BUS_ERROR, ACP_CONF_CS, INT_ENA_CS, INT_CLEAR_CS, INT_LATCH_CS, + PSEUDO_BUS_ERROR, ACP_CONF_CS, INT_CTR_CS: std_logic; - + signal INT_ENA_CS : std_logic := '0'; + signal INT_CLEAR_CS : std_logic := '0'; + signal INT_LATCH_CS : std_logic := '0'; + FUNCTION to_std_logic(X: IN boolean) RETURN std_logic IS VARIABLE ret : std_logic; BEGIN @@ -5096,7 +5099,7 @@ BEGIN INT_CTR0_clk_ctrl <= MAIN_CLK; -- $10000/4 - INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4000" else '0'; + INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; INT_CTR_d <= FB_AD; INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); @@ -5108,7 +5111,7 @@ BEGIN INT_ENA0_clrn_ctrl <= nRSTO; -- $10004/4 - int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4001"; + int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4001"; -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = -- "00000000000100000000000001"); @@ -5122,7 +5125,7 @@ BEGIN INT_CLEAR0_clk_ctrl <= MAIN_CLK; -- $10008/4 - int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4002" else '0'; + int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0'; -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010"); INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); @@ -5136,7 +5139,7 @@ BEGIN -- INTERRUPT LATCH REGISTER READ ONLY -- $1000C/4 - int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4003"; + int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4003"; -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = -- "00000000000100000000000011"); diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index f99242b..958dbde 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -794,7 +794,7 @@ BEGIN ); VDOUT_OE <= DDR_WR OR SR_DDR_WR; - video_ta <= blitter_ta or video_mod_ta or video_ddr_ta; + video_ta <= blitter_ta /* or video_mod_ta */ or video_ddr_ta; inst4 : entity work.lpm_ff1 PORT MAP diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 1a1993d..ade9e44 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -1512,9 +1512,9 @@ begin VSYNC_I0_ena_ctrl <= LAST_q; -- 3 zeilen vsync length - -- runterzählen bis 0 + -- runterzählen bis 0 VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else - std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else + std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else (others => '0'); -- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or From ba5713a1548acf4508d286b79aa108d64c4eecad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Apr 2016 04:34:30 +0000 Subject: [PATCH 096/127] multiple driver problem --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 96 +- .../Video/video_mod_mux_clutctr.vhd | 113 +- FPGA_Quartus_13.1/firebee1.qsf | 1490 ++++++++--------- FPGA_Quartus_13.1/firebee1.vhd | 555 +++--- 4 files changed, 1118 insertions(+), 1136 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index c005a60..742660f 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -281,19 +281,12 @@ architecture rtl of ddr_ctr is signal v_bash : std_logic_vector(7 downto 0); signal v_bash_cs : std_logic; - signal reg_ta : std_logic; + signal reg_ta : std_logic := '0'; + + type flexbus_states is (FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); + -- Sub Module Interface Section - --- component lpm_bustri_BYT --- port --- ( --- data : in std_logic_vector(7 downto 0); --- enabledt : in std_logic; --- tridata : buffer std_logic_vector(7 downto 0) --- ); --- end component lpm_bustri_BYT; - function to_std_logic(X : in boolean) return std_logic is variable ret : std_logic; begin @@ -578,45 +571,45 @@ begin end if; end process; - i_vbasx : work.flexbus_register - generic map - ( - reg_width => 2, - match_address => x"ffff8603", - match_mask => x"0000ffff", -- byte register - match_fbcs => 1 - ) - port map - ( - clk => clk33m, - fb_addr => fb_adr, - fb_data => fb_ad, - fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), - fb_ta_n => reg_ta, - fb_wr_n => nfb_wr, - reg_value => v_basx, - cs => v_basx_cs - ); - - i_vbash : work.flexbus_register - generic map - ( - reg_width => 8, - match_address => x"ffff8604", - match_mask => x"0000fffe", -- byte register - match_fbcs => 1 - ) - port map - ( - clk => clk33m, - fb_addr => fb_adr, - fb_data => fb_ad, - fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), - fb_ta_n => reg_ta, - fb_wr_n => nfb_wr, - reg_value => v_bash, - cs => v_bash_cs - ); +-- i_vbasx : work.flexbus_register +-- generic map +-- ( +-- reg_width => 2, +-- match_address => x"ffff8603", +-- match_mask => x"0000ffff", -- byte register +-- match_fbcs => 1 +-- ) +-- port map +-- ( +-- clk => clk33m, +-- fb_addr => fb_adr, +-- fb_data => fb_ad, +-- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), +-- fb_ta_n => reg_ta, +-- fb_wr_n => nfb_wr, +-- reg_value => v_basx, +-- cs => v_basx_cs +-- ); +-- +-- i_vbash : work.flexbus_register +-- generic map +-- ( +-- reg_width => 8, +-- match_address => x"ffff8604", +-- match_mask => x"0000fffe", -- byte register +-- match_fbcs => 1 +-- ) +-- port map +-- ( +-- clk => clk33m, +-- fb_addr => fb_adr, +-- fb_data => fb_ad, +-- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), +-- fb_ta_n => V, +-- fb_wr_n => nfb_wr, +-- reg_value => v_bash, +-- cs => v_bash_cs +-- ); -- Start of original equations line <= fb_size0 and fb_size1; @@ -654,6 +647,7 @@ begin bus_cyc_end <= '0'; stdVec3 := FB_REGDDR_q; + case stdVec3 is when "000" => FB_LE(0) <= not nFB_WR; @@ -718,7 +712,7 @@ begin end if; when others => - video_ddr_ta <= '0'; + end case; stdVec3 := (others => '0'); -- no storage needed end process; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index ade9e44..7afd582 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -545,7 +545,7 @@ begin HBE <= HBE_q; HSS <= HSS_q; VCO <= VCO_q; - VCNTRL <= VCNTRL_q; + VCNTRL <= VCNTRL_d; VSYNC <= VSYNC_q; nBLANK <= nBLANK_q; @@ -1269,47 +1269,82 @@ begin -- - REGISTER OUT -- low word register access - u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or - (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or - (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or - (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or - (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or - (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or - (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or - (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or - (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or - (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or - (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or - (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or - (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or - (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or - (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or - (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or - (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or - (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or - (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or - (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or - (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or - (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); +-- u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or +-- (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or +-- (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or +-- (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or +-- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or +-- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or +-- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or +-- (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or +-- (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or +-- (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or +-- (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or +-- (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or +-- (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or +-- (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or +-- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or +-- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or +-- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or +-- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or +-- (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or +-- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or +-- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or +-- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or +-- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or +-- (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or +-- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or +-- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); - u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or - HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or - VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); - FB_AD(31 downto 16) <= u0_tridata; + FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else + "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else + lwd_q when lof_cs = '1' and lwd_cs = '1' else + "0000" & hbe_q when hbe_cs = '1' else + "0000" & hdb_q when hdb_cs = '1' else + "0000" & hde_q when hde_cs = '1' else + "0000" & hbb_q when hbb_cs = '1' else + "0000" & hss_q when hss_cs = '1' else + "0000" & hht_q when hht_cs = '1' else + "00000" & vbe_q when vbe_cs = '1' else + "00000" & vdb_q when vdb_cs = '1' else + "00000" & vde_q when vde_cs = '1' else + "00000" & vbb_q when vbb_cs = '1' else + "00000" & vss_q when vss_cs = '1' else + "00000" & vft_q when vft_cs = '1' else + "0000000" & vco_q when vco_cs = '1' else + "000000000000" & vcntrl_q when vcntrl_cs = '1' else + acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else + atari_hh_q(31 downto 16) when atari_hh_cs = '1' else + atari_vh_q(31 downto 16) when atari_vh_cs = '1' else + atari_hl_q(31 downto 16) when atari_hl_cs = '1' else + atari_vl_q(31 downto 16) when atari_vl_cs = '1' else + "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else + "0000000" & vr_dout_q when video_pll_config_cs = '1' else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs else + (others => 'Z'); + +-- u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or +-- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or +-- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); +-- FB_AD(31 downto 16) <= u0_tridata; -- high word register access - u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or - (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); - u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); - FB_AD(15 downto 0) <= u1_tridata; +-- u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or +-- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or +-- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or +-- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or +-- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or +-- (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); +-- u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); +-- FB_AD(15 downto 0) <= u1_tridata; + + fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else + atari_hh_q(15 downto 0) when atari_hh_cs = '1' else + atari_vh_q(15 downto 0) when atari_vh_cs = '1' else + atari_hl_q(15 downto 0) when atari_hl_cs = '1' else + atari_vl_q(15 downto 0) when atari_vl_cs = '1' else + border_color_q(15 downto 0) when border_color_cs = '1' else + (others => 'Z'); video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 78a9acc..f42b241 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,311 +556,311 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 3388ae3..49d04e6 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -7,293 +7,246 @@ LIBRARY altera; LIBRARY work; ENTITY firebee1 IS - PORT + port ( - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - LP_BUSY : IN std_logic; - nACSI_DRQ : IN std_logic; - nACSI_INT : IN std_logic; - RxD : IN std_logic; - CTS : IN std_logic; - RI : IN std_logic; - DCD : IN std_logic; - AMKB_RX : IN std_logic; - PIC_AMKB_RX : IN std_logic; - IDE_RDY : IN std_logic; - IDE_INT : IN std_logic; - WP_CF_CARD : IN std_logic; - TRACK00 : IN std_logic; - nWP : IN std_logic; - nDCHG : IN std_logic; - SD_DATA0 : IN std_logic; - SD_DATA1 : IN std_logic; - SD_DATA2 : IN std_logic; - SD_CARD_DEDECT : IN std_logic; - nSCSI_DRQ : IN std_logic; - SD_WP : IN std_logic; - nRD_DATA : IN std_logic; - nSCSI_C_D : IN std_logic; - nSCSI_I_O : IN std_logic; - nSCSI_MSG : IN std_logic; - nDACK0 : IN std_logic; - PIC_INT : IN std_logic; - nFB_OE : IN std_logic; - TOUT0 : IN std_logic; - nMASTER : IN std_logic; - DVI_INT : IN std_logic; - nDACK1 : IN std_logic; - nPCI_INTD : IN std_logic; - nPCI_INTC : IN std_logic; - nPCI_INTB : IN std_logic; - nPCI_INTA : IN std_logic; - E0_INT : IN std_logic; - nINDEX : IN std_logic; - HD_DD : IN std_logic; - MAIN_CLK : IN std_logic; - nRSTO_MCF : IN std_logic; - CLK33MDIR : IN std_logic; - SCSI_PAR : INOUT std_logic; - nSCSI_RST : INOUT std_logic; - nSCSI_SEL : INOUT std_logic; - nSCSI_BUSY : INOUT std_logic; - SD_CD_DATA3 : INOUT std_logic; - SD_CMD_D1 : INOUT std_logic; - MIDI_IN_PIN : INOUT std_logic; - ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - IO : INOUT std_logic_vector(17 DOWNTO 0); - LP_D : INOUT std_logic_vector(7 DOWNTO 0); - SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); - SRD : INOUT std_logic_vector(15 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0); - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - LP_STR : OUT std_logic; - nACSI_ACK : OUT std_logic; - nACSI_RESET : OUT std_logic; - nACSI_CS : OUT std_logic; - ACSI_DIR : OUT std_logic; - ACSI_A1 : OUT std_logic; - nSCSI_ACK : OUT std_logic; - nSCSI_ATN : OUT std_logic; - SCSI_DIR : OUT std_logic; - MIDI_TLR : OUT std_logic; - TxD : OUT std_logic; - RTS : OUT std_logic; - DTR : OUT std_logic; - AMKB_TX : OUT std_logic; - IDE_RES : OUT std_logic; - nIDE_CS0 : OUT std_logic; - nIDE_CS1 : OUT std_logic; - nIDE_WR : OUT std_logic; - nIDE_RD : OUT std_logic; - nCF_CS0 : OUT std_logic; - nCF_CS1 : OUT std_logic; - nROM3 : OUT std_logic; - nROM4 : OUT std_logic; - nRP_UDS : OUT std_logic; - nRP_LDS : OUT std_logic; - nSDSEL : OUT std_logic; - nWR_GATE : OUT std_logic; - nWR : OUT std_logic; - YM_QA : OUT std_logic; - YM_QB : OUT std_logic; - YM_QC : OUT std_logic; - SD_CLK : OUT std_logic; - DSA_D : OUT std_logic; - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - nPD_VGA : OUT std_logic; - TIN0 : OUT std_logic; - nSRCS : OUT std_logic; - nSRBLE : OUT std_logic; - nSRBHE : OUT std_logic; - nSRWE : OUT std_logic; - nDREQ1 : OUT std_logic; - LED_FPGA_OK : OUT std_logic; - nSROE : OUT std_logic; - VCKE : OUT std_logic; - nFB_TA : OUT std_logic; - nDDR_CLK : OUT std_logic; - DDR_CLK : OUT std_logic; - VSYNC_PAD : OUT std_logic; - HSYNC_PAD : OUT std_logic; - nBLANK_PAD : OUT std_logic; - PIXEL_CLK_PAD : OUT std_logic; - nSYNC : OUT std_logic; - nMOT_ON : OUT std_logic; - nSTEP_DIR : OUT std_logic; - nSTEP : OUT std_logic; - LPDIR : OUT std_logic; - MIDI_OLR : OUT std_logic; - CLK25M : OUT std_logic; - CLKUSB : OUT std_logic; - CLK24M576 : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - nIRQ : OUT std_logic_vector(7 DOWNTO 2); - VA : OUT std_logic_vector(12 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VDM : OUT std_logic_vector(3 DOWNTO 0); - VG : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0) + FB_ALE : in std_logic; + nFB_WR : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; + LP_BUSY : in std_logic; + nACSI_DRQ : in std_logic; + nACSI_INT : in std_logic; + RxD : in std_logic; + CTS : in std_logic; + RI : in std_logic; + DCD : in std_logic; + AMKB_RX : in std_logic; + PIC_AMKB_RX : in std_logic; + IDE_RDY : in std_logic; + IDE_INT : in std_logic; + WP_CF_CARD : in std_logic; + TRACK00 : in std_logic; + nWP : in std_logic; + nDCHG : in std_logic; + SD_DATA0 : in std_logic; + SD_DATA1 : in std_logic; + SD_DATA2 : in std_logic; + SD_CARD_DEDECT : in std_logic; + nSCSI_DRQ : in std_logic; + SD_WP : in std_logic; + nRD_DATA : in std_logic; + nSCSI_C_D : in std_logic; + nSCSI_I_O : in std_logic; + nSCSI_MSG : in std_logic; + nDACK0 : in std_logic; + PIC_INT : in std_logic; + nFB_OE : in std_logic; + TOUT0 : in std_logic; + nMASTER : in std_logic; + DVI_INT : in std_logic; + nDACK1 : in std_logic; + nPCI_INTD : in std_logic; + nPCI_INTC : in std_logic; + nPCI_INTB : in std_logic; + nPCI_INTA : in std_logic; + E0_INT : in std_logic; + nINDEX : in std_logic; + HD_DD : in std_logic; + MAIN_CLK : in std_logic; + nRSTO_MCF : in std_logic; + CLK33MDIR : in std_logic; + SCSI_PAR : inout std_logic; + nSCSI_RST : inout std_logic; + nSCSI_SEL : inout std_logic; + nSCSI_BUSY : inout std_logic; + SD_CD_DATA3 : inout std_logic; + SD_CMD_D1 : inout std_logic; + MIDI_IN_PIN : inout std_logic; + ACSI_D : inout std_logic_vector(7 downto 0); + FB_AD : inout std_logic_vector(31 downto 0); + IO : inout std_logic_vector(17 downto 0); + LP_D : inout std_logic_vector(7 downto 0); + SCSI_D : inout std_logic_vector(7 downto 0); + SRD : inout std_logic_vector(15 downto 0); + VD : inout std_logic_vector(31 downto 0); + VDQS : inout std_logic_vector(3 downto 0); + LP_STR : out std_logic; + nACSI_ACK : out std_logic; + nACSI_RESET : out std_logic; + nACSI_CS : out std_logic; + ACSI_DIR : out std_logic; + ACSI_A1 : out std_logic; + nSCSI_ACK : out std_logic; + nSCSI_ATN : out std_logic; + SCSI_DIR : out std_logic; + MIDI_TLR : out std_logic; + TxD : out std_logic; + RTS : out std_logic; + DTR : out std_logic; + AMKB_TX : out std_logic; + IDE_RES : out std_logic; + nIDE_CS0 : out std_logic; + nIDE_CS1 : out std_logic; + nIDE_WR : out std_logic; + nIDE_RD : out std_logic; + nCF_CS0 : out std_logic; + nCF_CS1 : out std_logic; + nROM3 : out std_logic; + nROM4 : out std_logic; + nRP_UDS : out std_logic; + nRP_LDS : out std_logic; + nSDSEL : out std_logic; + nWR_GATE : out std_logic; + nWR : out std_logic; + YM_QA : out std_logic; + YM_QB : out std_logic; + YM_QC : out std_logic; + SD_CLK : out std_logic; + DSA_D : out std_logic; + nVWE : out std_logic; + nVCAS : out std_logic; + nVRAS : out std_logic; + nVCS : out std_logic; + nPD_VGA : out std_logic; + TIN0 : out std_logic; + nSRCS : out std_logic; + nSRBLE : out std_logic; + nSRBHE : out std_logic; + nSRWE : out std_logic; + nDREQ1 : out std_logic; + LED_FPGA_OK : out std_logic; + nSROE : out std_logic; + VCKE : out std_logic; + nFB_TA : out std_logic; + nDDR_CLK : out std_logic; + DDR_CLK : out std_logic; + VSYNC_PAD : out std_logic; + HSYNC_PAD : out std_logic; + nBLANK_PAD : out std_logic; + PIXEL_CLK_PAD : out std_logic; + nSYNC : out std_logic; + nMOT_ON : out std_logic; + nSTEP_DIR : out std_logic; + nSTEP : out std_logic; + LPDIR : out std_logic; + MIDI_OLR : out std_logic; + CLK25M : out std_logic; + CLKUSB : out std_logic; + CLK24M576 : out std_logic; + BA : out std_logic_vector(1 downto 0); + nIRQ : out std_logic_vector(7 downto 2); + VA : out std_logic_vector(12 downto 0); + VB : out std_logic_vector(7 downto 0); + VDM : out std_logic_vector(3 downto 0); + VG : out std_logic_vector(7 downto 0); + VR : out std_logic_vector(7 downto 0) ); -END firebee1; +end firebee1; -ARCHITECTURE rtl OF firebee1 IS - SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0); - SIGNAL clk25m_i : std_logic; - SIGNAL CLK2M : std_logic; - SIGNAL CLK2M4576 : std_logic; - SIGNAL CLK33M : std_logic; - SIGNAL CLK48M : std_logic; - SIGNAL CLK500k : std_logic; - SIGNAL CLK_VIDEO : std_logic; - SIGNAL DDR_SYNC_66M : std_logic; - SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); - SIGNAL DMA_DRQ : std_logic; - SIGNAL DSP_INT : std_logic; - SIGNAL DSP_TA : std_logic; - SIGNAL FALCON_IO_TA : std_logic; - SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL FDC_CLK : std_logic; - SIGNAL HSYNC : std_logic; - SIGNAL INT_HANDLER_TA : std_logic; - SIGNAL LP_DIR : std_logic; - SIGNAL MIDI_IN : std_logic; - SIGNAL MOT_ON : std_logic; - SIGNAL nBLANK : std_logic; - SIGNAL nDREQ0 : std_logic; - SIGNAL nMFP_INT : std_logic; - SIGNAL nRSTO : std_logic; - SIGNAL PIXEL_CLK : std_logic; - SIGNAL SD_CDM_D1 : std_logic; - SIGNAL STEP : std_logic; - SIGNAL STEP_DIR : std_logic; - SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0); - SIGNAL VIDEO_RECONFIG : std_logic; - SIGNAL Video_TA : std_logic; - SIGNAL VR_BUSY : std_logic; - SIGNAL VR_D : std_logic_vector(8 DOWNTO 0); - SIGNAL VR_RD : std_logic; - SIGNAL VR_WR : std_logic; - SIGNAL VSYNC : std_logic; - SIGNAL WR_DATA : std_logic; - SIGNAL WR_GATE : std_logic; - SIGNAL scandataout : std_logic; - SIGNAL scandone : std_logic; - SIGNAL reset : std_logic; - SIGNAL pll_reset : std_logic; - SIGNAL scanclk : std_logic; - SIGNAL scandata : std_logic; - SIGNAL scan_clkena : std_logic; - SIGNAL config_update : std_logic; - SIGNAL pll3_locked : std_logic; - SIGNAL pll1_locked : std_logic; - SIGNAL nSRCS_i : std_logic; - SIGNAL nFB_WR_i : std_logic; - SIGNAL nIDE_RD_i : std_logic; - SIGNAL nIDE_WR_i : std_logic; +architecture rtl OF firebee1 IS + signal ACP_CONF : std_logic_vector(31 downto 0); + signal clk25m_i : std_logic; + signal CLK2M : std_logic; + signal CLK2M4576 : std_logic; + signal CLK33M : std_logic; + signal CLK48M : std_logic; + signal CLK500k : std_logic; + signal CLK_VIDEO : std_logic; + signal DDR_SYNC_66M : std_logic; + signal DDRCLK : std_logic_vector(3 downto 0); + signal DMA_DRQ : std_logic; + signal DSP_INT : std_logic; + signal DSP_TA : std_logic; + signal FALCON_IO_TA : std_logic; + signal FB_ADR : std_logic_vector(31 downto 0); + signal FDC_CLK : std_logic; + signal HSYNC : std_logic; + signal INT_HANDLER_TA : std_logic; + signal LP_DIR : std_logic; + signal MIDI_IN : std_logic; + signal MOT_ON : std_logic; + signal nBLANK : std_logic; + signal nDREQ0 : std_logic; + signal nMFP_INT : std_logic; + signal nRSTO : std_logic; + signal PIXEL_CLK : std_logic; + signal SD_CDM_D1 : std_logic; + signal STEP : std_logic; + signal STEP_DIR : std_logic; + signal TIMEBASE : std_logic_vector(17 downto 0); + signal VIDEO_RECONFIG : std_logic; + signal Video_TA : std_logic; + signal VR_BUSY : std_logic; + signal VR_D : std_logic_vector(8 downto 0); + signal VR_RD : std_logic; + signal VR_WR : std_logic; + signal VSYNC : std_logic; + signal WR_DATA : std_logic; + signal WR_GATE : std_logic; + signal scandataout : std_logic; + signal scandone : std_logic; + signal reset : std_logic; + signal pll_reset : std_logic; + signal scanclk : std_logic; + signal scandata : std_logic; + signal scan_clkena : std_logic; + signal config_update : std_logic; + signal pll3_locked : std_logic; + signal pll1_locked : std_logic; + signal nSRCS_i : std_logic; + signal nFB_WR_i : std_logic; + signal nIDE_RD_i : std_logic; + signal nIDE_WR_i : std_logic; - COMPONENT altpll_reconfig1 - PORT + component altpll_reconfig1 + port ( - clock : IN std_logic ; - counter_param : IN std_logic_vector (2 DOWNTO 0); - counter_type : IN std_logic_vector (3 DOWNTO 0); - data_in : IN std_logic_vector (8 DOWNTO 0); - pll_areset_in : IN std_logic := '0'; - pll_scandataout : IN std_logic ; - pll_scandone : IN std_logic ; - read_param : IN std_logic ; - reconfig : IN std_logic ; - reset : IN std_logic ; - write_param : IN std_logic ; - busy : OUT std_logic ; - data_out : OUT std_logic_vector (8 DOWNTO 0); - pll_areset : OUT std_logic ; - pll_configupdate : OUT std_logic ; - pll_scanclk : OUT std_logic ; - pll_scanclkena : OUT std_logic ; - pll_scandata : OUT std_logic + clock : in std_logic ; + counter_param : in std_logic_vector (2 downto 0); + counter_type : in std_logic_vector (3 downto 0); + data_in : in std_logic_vector (8 downto 0); + pll_areset_in : in std_logic := '0'; + pll_scandataout : in std_logic ; + pll_scandone : in std_logic ; + read_param : in std_logic ; + reconfig : in std_logic ; + reset : in std_logic ; + write_param : in std_logic ; + busy : out std_logic ; + data_out : out std_logic_vector (8 downto 0); + pll_areset : out std_logic ; + pll_configupdate : out std_logic ; + pll_scanclk : out std_logic ; + pll_scanclkena : out std_logic ; + pll_scandata : out std_logic ); - END COMPONENT altpll_reconfig1; + end component altpll_reconfig1; - COMPONENT altpll4 - PORT + component altpll4 + port ( - areset : IN std_logic := '0'; - configupdate : IN std_logic := '0'; - inclk0 : IN std_logic := '0'; - scanclk : IN std_logic := '1'; - scanclkena : IN std_logic := '0'; - scandata : IN std_logic := '0'; - c0 : OUT std_logic ; - locked : OUT std_logic ; - scandataout : OUT std_logic ; - scandone : OUT std_logic + areset : in std_logic := '0'; + configupdate : in std_logic := '0'; + inclk0 : in std_logic := '0'; + scanclk : in std_logic := '1'; + scanclkena : in std_logic := '0'; + scandata : in std_logic := '0'; + c0 : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic ); - END COMPONENT altpll4; + end component altpll4; --- COMPONENT video --- PORT --- ( --- FB_ADR : IN std_logic_vector(31 DOWNTO 0); --- MAIN_CLK : IN std_logic; --- nFB_CS1 : IN std_logic; --- nFB_CS2 : IN std_logic; --- nFB_CS3 : IN std_logic; --- nFB_WR : IN std_logic; --- FB_SIZE0 : IN std_logic; --- FB_SIZE1 : IN std_logic; --- nRSTO : IN std_logic; --- nFB_OE : IN std_logic; --- FB_ALE : IN std_logic; --- DDRCLK : IN std_logic_vector(3 DOWNTO 0); --- DDR_SYNC_66M : IN std_logic; --- CLK33M : IN std_logic; --- CLK25M : IN std_logic; --- CLK_VIDEO : IN std_logic; --- VR_D : IN std_logic_vector(8 DOWNTO 0); --- VR_BUSY : IN std_logic; --- VG : OUT std_logic_vector(7 DOWNTO 0); --- VB : OUT std_logic_vector(7 DOWNTO 0); --- VR : OUT std_logic_vector(7 DOWNTO 0); --- nBLANK : OUT std_logic; --- VA : OUT std_logic_vector(12 DOWNTO 0); --- nVWE : OUT std_logic; --- nVCAS : OUT std_logic; --- nVRAS : OUT std_logic; --- nVCS : OUT std_logic; --- VDM : OUT std_logic_vector(3 DOWNTO 0); --- nPD_VGA : OUT std_logic; --- VCKE : OUT std_logic; --- VSYNC : OUT std_logic; --- HSYNC : OUT std_logic; --- nSYNC : OUT std_logic; --- VIDEO_TA : OUT std_logic; --- PIXEL_CLK : OUT std_logic; --- BA : OUT std_logic_vector(1 DOWNTO 0); --- VIDEO_RECONFIG : OUT std_logic; --- VR_WR : OUT std_logic; --- VR_RD : OUT std_logic; --- VDQS : INOUT std_logic_vector(3 DOWNTO 0); --- FB_AD : INOUT std_logic_vector(31 DOWNTO 0); --- VD : INOUT std_logic_vector(31 DOWNTO 0) --- ); --- END COMPONENT video; -BEGIN +begin nDREQ1 <= nDACK1; i_atari_clk_pll : work.altpll3 - PORT MAP + port map ( inclk0 => MAIN_CLK, c0 => clk25m_i, @@ -305,7 +258,7 @@ BEGIN i_ddr_clk_pll : work.altpll2 - PORT MAP + port map ( inclk0 => MAIN_CLK, c0 => DDRCLK(0), @@ -317,7 +270,7 @@ BEGIN i_dsp : work.dsp - PORT MAP + port map ( CLK33M => CLK33M, MAIN_CLK => MAIN_CLK, @@ -345,7 +298,7 @@ BEGIN i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf - PORT MAP + port map ( CLK33M => CLK33M, MAIN_CLK => MAIN_CLK, @@ -402,7 +355,7 @@ BEGIN nSCSI_RST => nSCSI_RST, SD_CD_DATA3 => SD_CD_DATA3, SD_CDM_D1 => SD_CDM_D1, - ACP_CONF => ACP_CONF(31 DOWNTO 24), + ACP_CONF => ACP_CONF(31 downto 24), ACSI_D => ACSI_D, FB_AD => FB_AD, FB_ADR => FB_ADR, @@ -453,7 +406,7 @@ BEGIN i_interrupt_handler : work.interrupt_handler - PORT MAP + port map ( MAIN_CLK => MAIN_CLK, nFB_WR => nFB_WR, @@ -485,7 +438,7 @@ BEGIN i_mfp_acia_clk_pll : work.altpll1 - PORT MAP + port map ( inclk0 => MAIN_CLK, c0 => CLK48M, @@ -496,7 +449,7 @@ BEGIN i_pll_reconfig : altpll_reconfig1 - PORT MAP + port map ( reconfig => VIDEO_RECONFIG, read_param => VR_RD, @@ -506,9 +459,9 @@ BEGIN pll_scandone => scandone, clock => MAIN_CLK, reset => reset, - counter_param => FB_ADR(8 DOWNTO 6), - counter_type => FB_ADR(5 DOWNTO 2), - data_in => FB_AD(24 DOWNTO 16), + counter_param => FB_ADR(8 downto 6), + counter_type => FB_ADR(5 downto 2), + data_in => FB_AD(24 downto 16), busy => VR_BUSY, pll_scandata => scandata, pll_scanclk => scanclk, @@ -520,7 +473,7 @@ BEGIN i_video : entity work.video - PORT MAP + port map ( MAIN_CLK => MAIN_CLK, nFB_CS1 => nFB_CS1, @@ -568,7 +521,7 @@ BEGIN i_video_clk_pll : altpll4 - PORT MAP + port map ( inclk0 => CLK48M, areset => pll_reset, @@ -583,7 +536,7 @@ BEGIN inst1 : work.lpm_ff0 - PORT MAP + port map ( clock => DDR_SYNC_66M, enable => FB_ALE, @@ -591,13 +544,13 @@ BEGIN q => FB_ADR ); - nMOT_ON <= NOT(MOT_ON); - nSTEP_DIR <= NOT(STEP_DIR); - nSTEP <= NOT(STEP); - nWR <= NOT(WR_DATA); + nMOT_ON <= not(MOT_ON); + nSTEP_DIR <= not(STEP_DIR); + nSTEP <= not(STEP); + nWR <= not(WR_DATA); inst18 : work.lpm_counter0 - PORT MAP + port map ( clock => CLK500k, q => TIMEBASE @@ -610,11 +563,11 @@ BEGIN CLK33M <= MAIN_CLK; - reset <= NOT(nRSTO); - nRSTO <= pll3_locked AND pll1_locked AND nRSTO_MCF; + reset <= not(nRSTO); + nRSTO <= pll3_locked and pll1_locked and nRSTO_MCF; inst29 : alt_iobuf - PORT MAP + port map ( i => CLK2M, oe => CLK2M, @@ -624,10 +577,10 @@ BEGIN LED_FPGA_OK <= TIMEBASE(17); - nDDR_CLK <= NOT(DDRCLK(0)); + nDDR_CLK <= not(DDRCLK(0)); inst5 : work.altddio_out3 - PORT MAP + port map ( datain_h => VSYNC, datain_l => VSYNC, @@ -637,7 +590,7 @@ BEGIN inst6 : work.altddio_out3 - PORT MAP + port map ( datain_h => HSYNC, datain_l => HSYNC, @@ -647,7 +600,7 @@ BEGIN inst8 : work.altddio_out3 - PORT MAP + port map ( datain_h => nBLANK, datain_l => nBLANK, @@ -656,7 +609,7 @@ BEGIN ); inst9 : work.altddio_out3 - PORT MAP + port map ( datain_h => '0', datain_l => '1', @@ -673,4 +626,4 @@ BEGIN nIDE_RD <= nIDE_RD_i; nIDE_WR <= nIDE_WR_i; -END rtl; \ No newline at end of file +end rtl; \ No newline at end of file From f03a1eb525455b2398b4cf9ccc0d5e305a85c837 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 2 Jun 2016 15:57:06 +0000 Subject: [PATCH 097/127] more fixes --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 302 ++-- .../Video/video_mod_mux_clutctr.vhd | 475 +++--- FPGA_Quartus_13.1/firebee1.qsf | 1491 +++++++++-------- 3 files changed, 1127 insertions(+), 1141 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 742660f..c657dd1 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -22,15 +22,15 @@ library ieee; entity ddr_ctr is port ( - FB_ADR : in std_logic_vector(31 downto 0); + fb_adr : in std_logic_vector(31 downto 0); nFB_CS1 : in std_logic; nFB_CS2 : in std_logic; nFB_CS3 : in std_logic; nFB_OE : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; + fb_size0 : in std_logic; + fb_size1 : in std_logic; nRSTO : in std_logic; - MAIN_CLK : in std_logic; + main_clk : in std_logic; FB_ALE : in std_logic; nFB_WR : in std_logic; DDR_SYNC_66M : in std_logic; @@ -46,16 +46,16 @@ entity ddr_ctr is nVWE : buffer std_logic; nVRAS : buffer std_logic; nVCS : buffer std_logic; - VCKE : buffer std_logic; + vcke : buffer std_logic; nVCAS : buffer std_logic; - FB_LE : buffer std_logic_vector(3 downto 0); - FB_VDOE : buffer std_logic_vector(3 downto 0); + fb_le : buffer std_logic_vector(3 downto 0); + fb_vdoe : buffer std_logic_vector(3 downto 0); SR_FIFO_WRE : buffer std_logic; SR_DDR_FB : buffer std_logic; SR_DDR_WR : buffer std_logic; SR_DDRWR_D_SEL : buffer std_logic; SR_VDMP : buffer std_logic_vector(7 downto 0); - VIDEO_DDR_TA : buffer std_logic; + video_ddr_ta : buffer std_logic; SR_BLITTER_DACK : buffer std_logic; BA : buffer std_logic_vector(1 downto 0); DDRWR_D_SEL1 : buffer std_logic; @@ -73,13 +73,13 @@ architecture rtl of ddr_ctr is -- READ FIFO -- CLOSE FIFO BANK -- REFRESH 10X7.5NfS=75NS - signal FB_REGDDR_3 : std_logic_vector(2 downto 0); - signal FB_REGDDR_d : std_logic_vector(2 downto 0); - signal FB_REGDDR_q : std_logic_vector(2 downto 0); + signal fb_regddr_3 : std_logic_vector(2 downto 0); + signal fb_regddr_d : std_logic_vector(2 downto 0); + signal fb_regddr_q : std_logic_vector(2 downto 0); signal DDR_SM_6 : std_logic_vector(5 downto 0); signal DDR_SM_d : std_logic_vector(5 downto 0); signal DDR_SM_q : std_logic_vector(5 downto 0); - signal FB_B : std_logic_vector(3 downto 0); + signal fb_b : std_logic_vector(3 downto 0); signal VA_P : std_logic_vector(12 downto 0); signal VA_P_d : std_logic_vector(12 downto 0); signal VA_P_q : std_logic_vector(12 downto 0); @@ -97,7 +97,7 @@ architecture rtl of ddr_ctr is signal MCS_q : std_logic_vector(1 downto 0); signal SR_VDMP_d : std_logic_vector(7 downto 0); signal SR_VDMP_q : std_logic_vector(7 downto 0); - signal CPU_ROW_ADR : std_logic_vector(12 downto 0); + signal cpu_row_adr : std_logic_vector(12 downto 0); signal CPU_BA : std_logic_vector(1 downto 0); signal CPU_COL_ADR : std_logic_vector(9 downto 0); signal BLITTER_ROW_ADR : std_logic_vector(12 downto 0); @@ -131,7 +131,7 @@ architecture rtl of ddr_ctr is signal VIDEO_ACT_ADR : std_logic_vector(26 downto 0); signal u0_data : std_logic_vector(7 downto 0); signal u0_tridata : std_logic_vector(7 downto 0); - signal FB_REGDDR_0_clk_ctrl : std_logic; + signal fb_regddr_0_clk_ctrl : std_logic; signal SR_VDMP0_clk_ctrl : std_logic; signal MCS0_clk_ctrl : std_logic; signal VA_S0_clk_ctrl : std_logic; @@ -182,8 +182,8 @@ architecture rtl of ddr_ctr is signal BA1_1 : std_logic; signal BA0_2 : std_logic; signal BA0_1 : std_logic; - signal BUS_CYC_d_2 : std_logic; - signal BUS_CYC_d_1 : std_logic; + signal bus_cyc_d_2 : std_logic; + signal bus_cyc_d_1 : std_logic; signal FIFO_BANK_OK_d_2 : std_logic; signal FIFO_BANK_OK_d_1 : std_logic; signal u0_enabledt : std_logic; @@ -201,7 +201,7 @@ architecture rtl of ddr_ctr is signal DDR_REFRESH_REQ_clk : std_logic; signal DDR_REFRESH_REQ_d : std_logic; signal DDR_REFRESH_REQ : std_logic; - signal DDR_REFRESH_ON : std_logic; + signal ddr_refresh_on : std_logic; signal FIFO_BANK_NOT_OK : std_logic; signal FIFO_BANK_OK_q : std_logic; signal FIFO_BANK_OK_clk : std_logic; @@ -239,11 +239,11 @@ architecture rtl of ddr_ctr is signal BLITTER_REQ_clk : std_logic; signal BLITTER_REQ_d : std_logic; signal BLITTER_REQ : std_logic; - signal BUS_CYC_END : std_logic; - signal BUS_CYC_q : std_logic; - signal BUS_CYC_clk : std_logic; - signal BUS_CYC_d : std_logic; - signal BUS_CYC : std_logic; + signal bus_cyc_end : std_logic; + signal bus_cyc_q : std_logic; + signal bus_cyc_clk : std_logic; + signal bus_cyc_d : std_logic; + signal bus_cyc : std_logic; signal CPU_AC_q : std_logic; signal CPU_AC_clk : std_logic; signal CPU_AC_d : std_logic; @@ -259,13 +259,13 @@ architecture rtl of ddr_ctr is signal SR_DDR_WR_q : std_logic; signal SR_DDR_WR_clk : std_logic; signal SR_DDR_WR_d : std_logic; - signal DDR_CONFIG : std_logic; - signal DDR_CS_q : std_logic; - signal DDR_CS_ena : std_logic; - signal DDR_CS_clk : std_logic; - signal DDR_CS_d : std_logic; - signal DDR_CS : std_logic; - signal DDR_SEL : std_logic; + signal ddr_config : std_logic; + signal ddr_cs_q : std_logic; + signal ddr_cs_ena : std_logic; + signal ddr_cs_clk : std_logic; + signal ddr_cs_d : std_logic; + signal ddr_cs : std_logic; + signal ddr_sel : std_logic; signal CPU_DDR_SYNC_q : std_logic; signal CPU_DDR_SYNC_clk : std_logic; signal CPU_DDR_SYNC_d : std_logic; @@ -354,10 +354,10 @@ begin end if; end process; - process (FB_REGDDR_0_clk_ctrl) + process (fb_regddr_0_clk_ctrl) begin if rising_edge(fb_regddr_0_clk_ctrl) then - FB_REGDDR_q <= FB_REGDDR_d; + fb_regddr_q <= fb_regddr_d; end if; end process; @@ -410,11 +410,11 @@ begin end if; end process; - process (DDR_CS_clk) + process (ddr_cs_clk) begin - if DDR_CS_clk'event and DDR_CS_clk='1' then - if DDR_CS_ena='1' then - DDR_CS_q <= DDR_CS_d; + if ddr_cs_clk'event and ddr_cs_clk='1' then + if ddr_cs_ena='1' then + ddr_cs_q <= ddr_cs_d; end if; end if; end process; @@ -433,10 +433,10 @@ begin end if; end process; - process (BUS_CYC_clk) + process (bus_cyc_clk) begin - if BUS_CYC_clk'event and BUS_CYC_clk='1' then - BUS_CYC_q <= BUS_CYC_d; + if bus_cyc_clk'event and bus_cyc_clk='1' then + bus_cyc_q <= bus_cyc_d; end if; end process; @@ -617,98 +617,98 @@ begin -- BYT SELECT -- ADR==0 -- LONG UND LINE - FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(0) <= to_std_logic(fb_adr(1 downto 0) = "00") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(1) <= to_std_logic(fb_adr(1 downto 0) = "01") or (fb_size1 and (not fb_size0) and (not fb_adr(1))) or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(2) <= to_std_logic(fb_adr(1 downto 0) = "10") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + fb_b(3) <= to_std_logic(fb_adr(1 downto 0) = "11") or (fb_size1 and (not fb_size0) and fb_adr(1)) or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR_0_clk_ctrl <= MAIN_CLK; + fb_regddr_0_clk_ctrl <= main_clk; - process (FB_REGDDR_q, DDR_SEL, BUS_CYC_q, LINE, DDR_CS_q, nFB_OE, MAIN_CLK, DDR_CONFIG, nFB_WR) + process (fb_regddr_q, ddr_sel, bus_cyc_q, LINE, ddr_cs_q, nFB_OE, main_clk, ddr_config, nFB_WR) variable stdVec3: std_logic_vector(2 downto 0); begin - FB_REGDDR_d <= FB_REGDDR_q; + fb_regddr_d <= fb_regddr_q; fb_vdoe <= (others => '0'); fb_le <= (others => '0'); video_ddr_ta <= '0'; bus_cyc_end <= '0'; - stdVec3 := FB_REGDDR_q; + stdVec3 := fb_regddr_q; case stdVec3 is when "000" => - FB_LE(0) <= not nFB_WR; + fb_le(0) <= not nFB_WR; -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - if (BUS_CYC_q or (DDR_SEL and LINE and (not nFB_WR))) = '1' then - FB_REGDDR_d <= "001"; + if (bus_cyc_q or (ddr_sel and LINE and (not nFB_WR))) = '1' then + fb_regddr_d <= "001"; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "001" => - if DDR_CS_q = '1' then - FB_LE(0) <= not nFB_WR; - VIDEO_DDR_TA <= '1'; + if ddr_cs_q = '1' then + fb_le(0) <= not nFB_WR; + video_ddr_ta <= '1'; if LINE ='1' then - FB_VDOE(0) <= (not nFB_OE) and (not DDR_CONFIG); - FB_REGDDR_d <= "010"; + fb_vdoe(0) <= (not nFB_OE) and (not ddr_config); + fb_regddr_d <= "010"; else - BUS_CYC_END <= '1'; - FB_VDOE(0) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); - FB_REGDDR_d <= "000"; + bus_cyc_end <= '1'; + fb_vdoe(0) <= (not nFB_OE) and (not main_clk) and (not ddr_config); + fb_regddr_d <= "000"; end if; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "010" => - if DDR_CS_q = '1' then - FB_VDOE(1) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(1) <= not nFB_WR; - VIDEO_DDR_TA <= '1'; - FB_REGDDR_d <= "011"; + if ddr_cs_q = '1' then + fb_vdoe(1) <= (not nFB_OE) and (not ddr_config); + fb_le(1) <= not nFB_WR; + video_ddr_ta <= '1'; + fb_regddr_d <= "011"; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "011" => - if DDR_CS_q ='1' then - FB_VDOE(2) <= (not nFB_OE) and (not DDR_CONFIG); - FB_LE(2) <= not nFB_WR; + if ddr_cs_q ='1' then + fb_vdoe(2) <= (not nFB_OE) and (not ddr_config); + fb_le(2) <= not nFB_WR; -- BEI LINE WRITE EVT. WARTEN - if ((not BUS_CYC_q) and LINE and (not nFB_WR)) = '1' then - FB_REGDDR_d <= "011"; + if ((not bus_cyc_q) and LINE and (not nFB_WR)) = '1' then + fb_regddr_d <= "011"; else - VIDEO_DDR_TA <= '1'; - FB_REGDDR_d <= "100"; + video_ddr_ta <= '1'; + fb_regddr_d <= "100"; end if; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when "100" => - if DDR_CS_q = '1' then - FB_VDOE(3) <= (not nFB_OE) and (not MAIN_CLK) and (not DDR_CONFIG); - FB_LE(3) <= not nFB_WR; - VIDEO_DDR_TA <= '1'; - BUS_CYC_END <= '1'; - FB_REGDDR_d <= "000"; + if ddr_cs_q = '1' then + fb_vdoe(3) <= (not nFB_OE) and (not main_clk) and (not ddr_config); + fb_le(3) <= not nFB_WR; + video_ddr_ta <= '1'; + bus_cyc_end <= '1'; + fb_regddr_d <= "000"; else - FB_REGDDR_d <= "000"; + fb_regddr_d <= "000"; end if; when others => @@ -718,17 +718,17 @@ begin end process; -- DDR STEUERUNG ----------------------------------------------------- - -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE <= VIDEO_RAM_CTR(0); + -- VIDEO RAM CONTROL REGISTER (IST in VIDEO_MUX_CTR) $F0000400: BIT 0: vcke; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + vcke <= VIDEO_RAM_CTR(0); nVCS <= not VIDEO_RAM_CTR(1); - DDR_REFRESH_ON <= VIDEO_RAM_CTR(2); - DDR_CONFIG <= VIDEO_RAM_CTR(3); + ddr_refresh_on <= VIDEO_RAM_CTR(2); + ddr_config <= VIDEO_RAM_CTR(3); FIFO_ACTIVE <= VIDEO_RAM_CTR(8); -- ------------------------------ - CPU_ROW_ADR <= FB_ADR(26 downto 14); - CPU_BA <= FB_ADR(13 downto 12); - CPU_COL_ADR <= FB_ADR(11 downto 2); + cpu_row_adr <= fb_adr(26 downto 14); + CPU_BA <= fb_adr(13 downto 12); + CPU_COL_ADR <= fb_adr(11 downto 2); nVRAS <= not VRAS; nVCAS <= not VCAS; nVWE <= not VWE; @@ -744,33 +744,33 @@ begin DDRWR_D_SEL1 <= BLITTER_AC_q; -- SELECT LOGIC - DDR_SEL <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); - DDR_CS_clk <= MAIN_CLK; - DDR_CS_ena <= FB_ALE; - DDR_CS_d <= DDR_SEL; + ddr_sel <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); + ddr_cs_clk <= main_clk; + ddr_cs_ena <= FB_ALE; + ddr_cs_d <= ddr_sel; - -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + -- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG -- CONFIG SOFORT LOS - -- LINE WRITE SPÄTER - CPU_SIG <= (DDR_SEL and (nFB_WR or (not LINE)) and (not DDR_CONFIG)) or - (DDR_SEL and DDR_CONFIG) or (to_std_logic(FB_REGDDR_q = "010") and (not nFB_WR)); + -- LINE WRITE SPÄTER + CPU_SIG <= (ddr_sel and (nFB_WR or (not LINE)) and (not ddr_config)) or + (ddr_sel and ddr_config) or (to_std_logic(fb_regddr_q = "010") and (not nFB_WR)); CPU_REQ_clk <= DDR_SYNC_66M; -- HALTEN BUS CYC BEGONNEN ODER FERTIG - CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and FB_REGDDR_q /= "010" - and FB_REGDDR_q /= "100") and (not BUS_CYC_END) and (not BUS_CYC_q)); - BUS_CYC_clk <= DDRCLK0; - BUS_CYC_d_1 <= BUS_CYC_q and (not BUS_CYC_END); + CPU_REQ_d <= CPU_SIG or (to_std_logic(CPU_REQ_q='1' and fb_regddr_q /= "010" + and fb_regddr_q /= "100") and (not bus_cyc_end) and (not bus_cyc_q)); + bus_cyc_clk <= DDRCLK0; + bus_cyc_d_1 <= bus_cyc_q and (not bus_cyc_end); -- STATE MACHINE SYNCHRONISIEREN ----------------- MCS0_clk_ctrl <= DDRCLK0; - MCS_d(0) <= MAIN_CLK; + MCS_d(0) <= main_clk; MCS_d(1) <= MCS_q(0); CPU_DDR_SYNC_clk <= DDRCLK0; -- NUR 1 WENN EIN - CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and VCKE and (not nVCS); + CPU_DDR_SYNC_d <= to_std_logic(MCS_q = "10") and vcke and (not nVCS); -- ------------------------------------------------- VA_S0_clk_ctrl <= DDRCLK0; @@ -785,12 +785,12 @@ begin DDR_SM_0_clk_ctrl <= DDRCLK0; - process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, DDR_CONFIG, - CPU_ROW_ADR, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, + process (DDR_SM_q, DDR_REFRESH_REQ_q, CPU_DDR_SYNC_q, ddr_config, + cpu_row_adr, FIFO_ROW_ADR, BLITTER_ROW_ADR, BLITTER_REQ_q, BLITTER_WR, FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, - FB_B, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, - VIDEO_ADR_CNT_q, FIFO_COL_ADR, DDR_SEL, LINE, FIFO_BA, VA_P_q, - BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, FB_SIZE0, FB_SIZE1, + fb_b, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, + VIDEO_ADR_CNT_q, FIFO_COL_ADR, ddr_sel, LINE, FIFO_BA, VA_P_q, + BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, fb_size0, fb_size1, DDR_REFRESH_SIG_q) variable stdVec6: std_logic_vector(5 downto 0); begin @@ -806,7 +806,7 @@ begin (FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d, SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2, - BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2, + BA1_2, BA0_2, SR_FIFO_WRE_d, bus_cyc_d_2, VWE, VA10_2, FIFO_BANK_NOT_OK, VCAS, VRAS) <= std_logic_vector'("00000000000000000000000000000"); stdVec6 := DDR_SM_q; @@ -818,14 +818,14 @@ begin -- SYNCHRON UND EIN? elsif (CPU_DDR_SYNC_q)='1' then -- JA - if (DDR_CONFIG)='1' then + if (ddr_config)='1' then DDR_SM_d <= "001000"; -- BEI WAIT UND LINE WRITE elsif (CPU_REQ_q)='1' then - VA_S_d <= CPU_ROW_ADR; + VA_S_d <= cpu_row_adr; BA_S_d <= CPU_BA; CPU_AC_d <= '1'; - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; DDR_SM_d <= "000010"; else -- FIFO IST DEFAULT @@ -849,7 +849,7 @@ begin when "000001" => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - if (DDR_SEL and (nFB_WR or (not LINE)))='1' then + if (ddr_sel and (nFB_WR or (not LINE)))='1' then VRAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (BA1_2, BA0_2) <= FB_AD(13 downto 12); @@ -857,7 +857,7 @@ begin VA_S_d(10) <= '1'; CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; else VRAS <= (FIFO_AC_q and FIFO_REQ_q) or (BLITTER_AC_q and BLITTER_REQ_q); (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= VA_P_q; @@ -875,7 +875,7 @@ begin CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; DDR_SM_d <= "000011"; when "000011" => @@ -912,7 +912,7 @@ begin BLITTER_AC_d <= BLITTER_AC_q; VCAS <= '1'; - -- READ DATEN FÜR CPU + -- READ DATEN FÃœR CPU SR_DDR_FB <= CPU_AC_q; -- BLITTER DACK AND BLITTER LATCH DATEN @@ -959,7 +959,7 @@ begin BA_S_d <= (std_logic_vector'(CPU_AC_q & CPU_AC_q) and CPU_BA) or (std_logic_vector'(BLITTER_AC_q & BLITTER_AC_q) and BLITTER_BA); -- BYTE ENABLE WRITE - SR_VDMP_d(7 downto 4) <= FB_B; + SR_VDMP_d(7 downto 4) <= fb_b; -- LINE ENABLE WRITE SR_VDMP_d(3 downto 0) <= sizeIt(LINE,4) and "1111"; @@ -974,7 +974,7 @@ begin -- WRITE COMMAND CPU UND BLITTER if WRITER SR_DDR_WR_d <= '1'; - -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL_d <= '1'; -- WENN LINE DANN ACTIV @@ -988,7 +988,7 @@ begin -- WRITE COMMAND CPU UND BLITTER if WRITE SR_DDR_WR_d <= '1'; - -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + -- 2. HÄLFTE WRITE DATEN SELEKTIEREN SR_DDRWR_D_SEL_d <= '1'; DDR_SM_d <= "010100"; @@ -1131,14 +1131,14 @@ begin end if; when "011100" => - if (DDR_SEL and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then + if (ddr_sel and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then VRAS <= '1'; (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); (BA1_2, BA0_2) <= FB_AD(13 downto 12); CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN - BUS_CYC_d_2 <= '1'; + bus_cyc_d_2 <= '1'; -- AUTO PRECHARGE DA NICHT FIFO BANK VA_S_d(10) <= '1'; @@ -1159,7 +1159,7 @@ begin DDR_SM_d <= "001001"; when "001001" => - BUS_CYC_d_2 <= CPU_REQ_q; + bus_cyc_d_2 <= CPU_REQ_q; DDR_SM_d <= "001010"; when "001010" => @@ -1180,13 +1180,13 @@ begin when "001101" => -- NUR BEI LONG WRITE - VRAS <= FB_AD(18) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + VRAS <= FB_AD(18) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- NUR BEI LONG WRITE - VCAS <= FB_AD(17) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + VCAS <= FB_AD(17) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- NUR BEI LONG WRITE - VWE <= FB_AD(16) and (not nFB_WR) and (not FB_SIZE0) and (not FB_SIZE1); + VWE <= FB_AD(16) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- CLOSE FIFO BANK DDR_SM_d <= "000111"; @@ -1196,7 +1196,7 @@ begin -- AUF NOT OK FIFO_BANK_NOT_OK <= '1'; - -- BÄNKE SCHLIESSEN + -- BÄNKE SCHLIESSEN VRAS <= '1'; VWE <= '1'; DDR_SM_d <= "000110"; @@ -1205,7 +1205,7 @@ begin -- AUF NOT OK FIFO_BANK_NOT_OK <= '1'; - -- BÄNKE SCHLIESSEN + -- BÄNKE SCHLIESSEN VRAS <= '1'; VWE <= '1'; @@ -1263,7 +1263,7 @@ begin -- BLITTER ---------------------- -- --------------------------------------- BLITTER_REQ_clk <= DDRCLK0; - BLITTER_REQ_d <= BLITTER_SIG and (not DDR_CONFIG) and VCKE and (not nVCS); + BLITTER_REQ_d <= BLITTER_SIG and (not ddr_config) and vcke and (not nVCS); BLITTER_ROW_ADR <= BLITTER_ADR(26 downto 14); BLITTER_BA(1) <= BLITTER_ADR(13); BLITTER_BA(0) <= BLITTER_ADR(12); @@ -1276,7 +1276,7 @@ begin FIFO_REQ_d <= (to_std_logic((unsigned(FIFO_MW) < unsigned'("011001000"))) or (to_std_logic((unsigned(FIFO_MW) < unsigned'("111110100"))) and FIFO_REQ_q)) and FIFO_ACTIVE and (not CLEAR_FIFO_CNT_q) and (not - STOP_q) and (not DDR_CONFIG) and VCKE and (not nVCS); + STOP_q) and (not ddr_config) and vcke and (not nVCS); FIFO_ROW_ADR <= VIDEO_ADR_CNT_q(22 downto 10); FIFO_BA(1) <= VIDEO_ADR_CNT_q(9); FIFO_BA(0) <= VIDEO_ADR_CNT_q(8); @@ -1286,7 +1286,7 @@ begin FIFO_BANK_OK_clk <= DDRCLK0; FIFO_BANK_OK_d_2 <= FIFO_BANK_OK_q and (not FIFO_BANK_NOT_OK); - -- ZÄHLER RÜCKSETZEN WENN CLR FIFO ---------------- + -- ZÄHLER RÃœCKSETZEN WENN CLR FIFO ---------------- CLR_FIFO_SYNC_clk <= DDRCLK0; -- SYNCHRONISIEREN @@ -1296,7 +1296,7 @@ begin STOP_clk <= DDRCLK0; STOP_d <= CLR_FIFO_SYNC_q or CLEAR_FIFO_CNT_q; - -- ZÄHLEN ----------------------------------------------- + -- ZÄHLEN ----------------------------------------------- VIDEO_ADR_CNT0_clk_ctrl <= DDRCLK0; VIDEO_ADR_CNT0_ena_ctrl <= SR_FIFO_WRE_q or CLEAR_FIFO_CNT_q; VIDEO_ADR_CNT_d <= (sizeIt(CLEAR_FIFO_CNT_q,23) and VIDEO_BASE_ADR) or @@ -1320,60 +1320,60 @@ begin -- --------------------------------------------------------------------------------------- DDR_REFRESH_CNT0_clk_ctrl <= CLK33M; - -- ZÄHLEN 0-2047 + -- ZÄHLEN 0-2047 DDR_REFRESH_CNT_d <= std_logic_vector'(unsigned(DDR_REFRESH_CNT_q) + unsigned'("00000000001")); REFRESH_TIME_clk <= DDRCLK0; -- SYNC - REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not MAIN_CLK); + REFRESH_TIME_d <= to_std_logic(DDR_REFRESH_CNT_q = "00000000000") and (not main_clk); DDR_REFRESH_SIG0_clk_ctrl <= DDRCLK0; DDR_REFRESH_SIG0_ena_ctrl <= to_std_logic(REFRESH_TIME_q='1' or DDR_SM_q = "100011"); - -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + -- 9 STÃœCK (8 REFRESH UND 1 ALS VORLAUF) -- MINUS 1 WENN GEMACHT DDR_REFRESH_SIG_d <= (sizeIt(REFRESH_TIME_q,4) and "1001" and - sizeIt(DDR_REFRESH_ON,4) and sizeIt(not DDR_CONFIG,4)) or (sizeIt(not + sizeIt(ddr_refresh_on,4) and sizeIt(not ddr_config,4)) or (sizeIt(not REFRESH_TIME_q,4) and (std_logic_vector'(unsigned(DDR_REFRESH_SIG_q) - - unsigned'("0001"))) and sizeIt(DDR_REFRESH_ON,4) and sizeIt(not - DDR_CONFIG,4)); + unsigned'("0001"))) and sizeIt(ddr_refresh_on,4) and sizeIt(not + ddr_config,4)); DDR_REFRESH_REQ_clk <= DDRCLK0; - DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and DDR_REFRESH_ON and (not REFRESH_TIME_q) and (not DDR_CONFIG); + DDR_REFRESH_REQ_d <= to_std_logic(DDR_REFRESH_SIG_q /= "0000") and ddr_refresh_on and (not REFRESH_TIME_q) and (not ddr_config); -- --------------------------------------------------------- -- VIDEO REGISTER ----------------------- -- ------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_L_D0_clk_ctrl <= main_clk; -- 820D/2 - VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000110"); + VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000110"); -- SORRY, NUR 16 BYT GRENZEN VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and FB_B(1); - VIDEO_BASE_M_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and fb_b(1); + VIDEO_BASE_M_D0_clk_ctrl <= main_clk; -- 8203/2 - VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000001"); + VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000001"); VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and FB_B(3); - VIDEO_BASE_H_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and fb_b(3); + VIDEO_BASE_H_D0_clk_ctrl <= main_clk; -- 8200-1/2 - VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000"); + VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000000"); VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); - VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(1); - VIDEO_BASE_X_D0_clk_ctrl <= MAIN_CLK; + VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(1); + VIDEO_BASE_X_D0_clk_ctrl <= main_clk; VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); - VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and FB_B(0); + VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(0); -- 8209/2 - VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000100"); + VIDEO_CNT_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000100"); -- 8207/2 - VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000011"); + VIDEO_CNT_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000011"); -- 8204,5/2 - VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000010"); + VIDEO_CNT_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000010"); -- FB_AD[31..24] = lpm_bustri_BYT( -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) @@ -1397,7 +1397,7 @@ begin -- Assignments added to explicitly combine the -- effects of multiple drivers in the source FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; - BUS_CYC_d <= BUS_CYC_d_1 or BUS_CYC_d_2; + bus_cyc_d <= bus_cyc_d_1 or bus_cyc_d_2; BA(0) <= BA0_1 or BA0_2; BA(1) <= BA1_1 or BA1_2; VA(0) <= VA0_1 or VA0_2; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 7afd582..ce2a412 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -35,18 +35,18 @@ -- VERZ2_.clk VERZ2_clk -- VERZ2_.d VERZ2_d -- VERZ2_ VERZ2 --- CLUT_MUX_AV0_.q CLUT_MUX_AV0_q --- CLUT_MUX_AV0_.prn CLUT_MUX_AV0_prn --- CLUT_MUX_AV0_.clrn CLUT_MUX_AV0_clrn --- CLUT_MUX_AV0_.clk CLUT_MUX_AV0_clk --- CLUT_MUX_AV0_.d CLUT_MUX_AV0_d --- CLUT_MUX_AV0_ CLUT_MUX_AV0 --- CLUT_MUX_AV1_.q CLUT_MUX_AV1_q --- CLUT_MUX_AV1_.prn CLUT_MUX_AV1_prn --- CLUT_MUX_AV1_.clrn CLUT_MUX_AV1_clrn --- CLUT_MUX_AV1_.clk CLUT_MUX_AV1_clk --- CLUT_MUX_AV1_.d CLUT_MUX_AV1_d --- CLUT_MUX_AV1_ CLUT_MUX_AV1 +-- clut_mux_av0_.q clut_mux_av0_q +-- clut_mux_av0_.prn clut_mux_av0_prn +-- clut_mux_av0_.clrn clut_mux_av0_clrn +-- clut_mux_av0_.clk clut_mux_av0_clk +-- clut_mux_av0_.d clut_mux_av0_d +-- clut_mux_av0_ clut_mux_av0 +-- clut_mux_av1_.q clut_mux_av1_q +-- clut_mux_av1_.prn clut_mux_av1_prn +-- clut_mux_av1_.clrn clut_mux_av1_clrn +-- clut_mux_av1_.clk clut_mux_av1_clk +-- clut_mux_av1_.d clut_mux_av1_d +-- clut_mux_av1_ clut_mux_av1 -- CREATED BY FREDI ASCHWANDEN @@ -56,6 +56,9 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; + +library work; + use work.firebee_utils_pkg.all; entity video_mod_mux_clutctr is port @@ -85,7 +88,7 @@ entity video_mod_mux_clutctr is FALCON_CLUT_WR : out std_logic_vector(3 downto 0); ST_CLUT_RD : out std_logic; ST_CLUT_WR : out std_logic_vector(1 downto 0); - CLUT_MUX_ADR : out std_logic_vector(3 downto 0); + clut_mux_adr : out std_logic_vector(3 downto 0); HSYNC : out std_logic; VSYNC : out std_logic; nBLANK : out std_logic; @@ -99,7 +102,7 @@ entity video_mod_mux_clutctr is BLITTER_ON : out std_logic; VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); VIDEO_MOD_TA : out std_logic; - BORDER_COLOR : out std_logic_vector(23 downto 0); + border_color : out std_logic_vector(23 downto 0); CCSEL : out std_logic_vector(2 downto 0); ACP_CLUT_WR : out std_logic_vector(3 downto 0); INTER_ZEI : out std_logic; @@ -116,7 +119,7 @@ end video_mod_mux_clutctr; architecture rtl of video_mod_mux_clutctr is -- DIV. CONTROL REGISTER -- BRAUCHT EIN WAITSTAT - -- LÄNGE HSYNC PULS IN PIXEL_CLK + -- LÄNGE HSYNC PULS IN PIXEL_CLK -- LETZTES PIXEL EINER ZEILE ERREICHT -- ATARI RESOLUTION -- HORIZONTAL TIMING 640x480 @@ -125,42 +128,42 @@ architecture rtl of video_mod_mux_clutctr is -- VERTIKAL TIMING 320x240 -- HORIZONTAL -- VERTIKAL - signal VR_DOUT : std_logic_vector(8 downto 0); - signal VR_DOUT_d : std_logic_vector(8 downto 0); - signal VR_DOUT_q : std_logic_vector(8 downto 0); - signal VR_FRQ : unsigned(7 downto 0); - signal VR_FRQ_d : std_logic_vector(7 downto 0); - signal VR_FRQ_q : std_logic_vector(7 downto 0); + signal vr_dout : std_logic_vector(8 downto 0); + signal vr_dout_d : std_logic_vector(8 downto 0); + signal vr_dout_q : std_logic_vector(8 downto 0); + signal vr_frq : unsigned(7 downto 0); + signal vr_frq_d : std_logic_vector(7 downto 0); + signal vr_frq_q : std_logic_vector(7 downto 0); signal FB_B : std_logic_vector(3 downto 0); signal FB_16B : std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE : std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE_d : std_logic_vector(1 downto 0); - signal ST_SHIFT_MODE_q : std_logic_vector(1 downto 0); - signal FALCON_SHIFT_MODE : std_logic_vector(10 downto 0); - signal FALCON_SHIFT_MODE_d : std_logic_vector(10 downto 0); - signal FALCON_SHIFT_MODE_q : std_logic_vector(10 downto 0); - signal CLUT_MUX_ADR_d : std_logic_vector(3 downto 0); - signal CLUT_MUX_ADR_q : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1 : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1_d : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV1_q : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0 : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0_d : std_logic_vector(3 downto 0); - signal CLUT_MUX_AV0_q : std_logic_vector(3 downto 0); - signal ACP_VCTR : std_logic_vector(31 downto 0); - signal ACP_VCTR_d : std_logic_vector(31 downto 0); - signal ACP_VCTR_q : std_logic_vector(31 downto 0); - signal BORDER_COLOR_d : std_logic_vector(23 downto 0); - signal BORDER_COLOR_q : std_logic_vector(23 downto 0); - signal SYS_CTR : std_logic_vector(6 downto 0); - signal SYS_CTR_d : std_logic_vector(6 downto 0); - signal SYS_CTR_q : std_logic_vector(6 downto 0); - signal LOF : std_logic_vector(15 downto 0); - signal LOF_d : std_logic_vector(15 downto 0); - signal LOF_q : std_logic_vector(15 downto 0); - signal LWD : std_logic_vector(15 downto 0); - signal LWD_d : std_logic_vector(15 downto 0); - signal LWD_q : std_logic_vector(15 downto 0); + signal st_shift_mode : std_logic_vector(1 downto 0); + signal st_shift_mode_d : std_logic_vector(1 downto 0); + signal st_shift_mode_q : std_logic_vector(1 downto 0); + signal falcon_shift_mode : std_logic_vector(10 downto 0); + signal falcon_shift_mode_d : std_logic_vector(10 downto 0); + signal falcon_shift_mode_q : std_logic_vector(10 downto 0); + signal clut_mux_adr_d : std_logic_vector(3 downto 0); + signal clut_mux_adr_q : std_logic_vector(3 downto 0); + signal clut_mux_av1 : std_logic_vector(3 downto 0); + signal clut_mux_av1_d : std_logic_vector(3 downto 0); + signal clut_mux_av1_q : std_logic_vector(3 downto 0); + signal clut_mux_av0 : std_logic_vector(3 downto 0); + signal clut_mux_av0_d : std_logic_vector(3 downto 0); + signal clut_mux_av0_q : std_logic_vector(3 downto 0); + signal acp_vctr : std_logic_vector(31 downto 0); + signal acp_vctr_d : std_logic_vector(31 downto 0); + signal acp_vctr_q : std_logic_vector(31 downto 0); + signal border_color_d : std_logic_vector(23 downto 0); + signal border_color_q : std_logic_vector(23 downto 0); + signal sys_ctr : std_logic_vector(6 downto 0); + signal sys_ctr_d : std_logic_vector(6 downto 0); + signal sys_ctr_q : std_logic_vector(6 downto 0); + signal lof : std_logic_vector(15 downto 0); + signal lof_d : std_logic_vector(15 downto 0); + signal lof_q : std_logic_vector(15 downto 0); + signal lwd : std_logic_vector(15 downto 0); + signal lwd_d : std_logic_vector(15 downto 0); + signal lwd_q : std_logic_vector(15 downto 0); signal HSYNC_I : std_logic_vector(7 downto 0); signal HSYNC_I_d : std_logic_vector(7 downto 0); signal HSYNC_I_q : std_logic_vector(7 downto 0); @@ -266,17 +269,17 @@ architecture rtl of video_mod_mux_clutctr is signal u0_tridata : std_logic_vector(15 downto 0); signal u1_data : std_logic_vector(15 downto 0); signal u1_tridata : std_logic_vector(15 downto 0); - -- signal ST_SHIFT_MODE0_clk_ctrl : std_logic; - signal ST_SHIFT_MODE0_ena_ctrl : std_logic; - -- signal FALCON_SHIFT_MODE0_clk_ctrl : std_logic; - signal FALCON_SHIFT_MODE8_ena_ctrl : std_logic; - signal FALCON_SHIFT_MODE0_ena_ctrl : std_logic; + -- signal st_shift_mode0_clk_ctrl : std_logic; + signal st_shift_mode0_ena_ctrl : std_logic; + -- signal falcon_shift_mode0_clk_ctrl : std_logic; + signal falcon_shift_mode8_ena_ctrl : std_logic; + signal falcon_shift_mode0_ena_ctrl : std_logic; - signal ACP_VCTR24_ena_ctrl : std_logic; - signal ACP_VCTR16_ena_ctrl : std_logic; - signal ACP_VCTR8_ena_ctrl : std_logic; - signal ACP_VCTR6_ena_ctrl : std_logic; - signal ACP_VCTR0_ena_ctrl : std_logic; + signal acp_vctr24_ena_ctrl : std_logic; + signal acp_vctr16_ena_ctrl : std_logic; + signal acp_vctr8_ena_ctrl : std_logic; + signal acp_vctr6_ena_ctrl : std_logic; + signal acp_vctr0_ena_ctrl : std_logic; signal ATARI_HH24_ena_ctrl : std_logic; signal ATARI_HH16_ena_ctrl : std_logic; @@ -295,16 +298,16 @@ architecture rtl of video_mod_mux_clutctr is signal ATARI_VL16_ena_ctrl : std_logic; signal ATARI_VL8_ena_ctrl : std_logic; signal ATARI_VL0_ena_ctrl : std_logic; - signal VR_DOUT0_ena_ctrl : std_logic; - signal VR_FRQ0_ena_ctrl : std_logic; - signal BORDER_COLOR16_ena_ctrl : std_logic; - signal BORDER_COLOR8_ena_ctrl : std_logic; - signal BORDER_COLOR0_ena_ctrl : std_logic; - signal SYS_CTR0_ena_ctrl : std_logic; - signal LOF8_ena_ctrl : std_logic; - signal LOF0_ena_ctrl : std_logic; - signal LWD8_ena_ctrl : std_logic; - signal LWD0_ena_ctrl : std_logic; + signal vr_dout0_ena_ctrl : std_logic; + signal vr_frq0_ena_ctrl : std_logic; + signal border_color16_ena_ctrl : std_logic; + signal border_color8_ena_ctrl : std_logic; + signal border_color0_ena_ctrl : std_logic; + signal sys_ctr0_ena_ctrl : std_logic; + signal lof8_ena_ctrl : std_logic; + signal lof0_ena_ctrl : std_logic; + signal lwd8_ena_ctrl : std_logic; + signal lwd0_ena_ctrl : std_logic; signal HHT8_ena_ctrl : std_logic; signal HHT0_ena_ctrl : std_logic; signal HBE8_ena_ctrl : std_logic; @@ -441,14 +444,14 @@ architecture rtl of video_mod_mux_clutctr is signal CLUT_TA_q : std_logic; signal CLUT_TA_d : std_logic; signal CLUT_TA : std_logic; - signal LWD_CS : std_logic; - signal LOF_CS : std_logic; - signal SYS_CTR_CS : std_logic; + signal lwd_CS : std_logic; + signal lof_CS : std_logic; + signal sys_ctr_CS : std_logic; signal ACP_VIDEO_ON : std_logic; - signal BORDER_COLOR_CS : std_logic; - signal ACP_VCTR_CS : std_logic; - signal FALCON_SHIFT_MODE_CS : std_logic; - signal ST_SHIFT_MODE_CS : std_logic; + signal border_color_CS : std_logic; + signal acp_vctr_CS : std_logic; + signal falcon_shift_mode_CS : std_logic; + signal st_shift_mode_CS : std_logic; signal ST_CLUT : std_logic; signal ST_CLUT_CS : std_logic; signal FALCON_CLUT : std_logic; @@ -493,26 +496,6 @@ architecture rtl of video_mod_mux_clutctr is end loop; return rep; end function sizeit; - - -- f_addr_cmp() compares addr against addr_const (only counting from the highest significant bit of the smaller - -- number, ignoring ignore least significant bits) and returns true if both addresses match, false otherwise - function f_addr_cmp(signal addr : std_logic_vector; constant addr_const : std_logic_vector; constant ignore : integer) return boolean is - variable c_len : integer := addr_const'high; - variable a_len : integer := addr'high; - variable len : integer; - variable result : boolean := false; - begin - if c_len < a_len then - len := c_len; - else - len := a_len; - end if; - for i in len downto len - ignore loop - result := addr_const(i) = addr(i); - exit when result = false; - end loop; - return result; - end function f_addr_cmp; begin -- Sub Module Section @@ -534,11 +517,11 @@ begin -- Register Section - CLUT_MUX_ADR <= CLUT_MUX_ADR_q; + clut_mux_adr <= clut_mux_adr_q; -- missing signals that seem to got lost during conversion HSYNC <= HSYNC_q; - ACP_VCTR <= ACP_VCTR_q; + acp_vctr <= acp_vctr_q; RAND <= RAND_q; ATARI_HH <= ATARI_HH_q; ATARI_HL <= ATARI_HL_q; @@ -550,9 +533,9 @@ begin VSYNC <= VSYNC_q; nBLANK <= nBLANK_q; FIFO_RDE <= FIFO_RDE_q; - BORDER_COLOR(23 downto 16) <= BORDER_COLOR_q(23 downto 16); - BORDER_COLOR(15 downto 8) <= BORDER_COLOR_q(15 downto 8); - BORDER_COLOR(7 downto 0) <= BORDER_COLOR_q(7 downto 0); + border_color(23 downto 16) <= border_color_q(23 downto 16); + border_color(15 downto 8) <= border_color_q(15 downto 8); + border_color(7 downto 0) <= border_color_q(7 downto 0); CCSEL <= CCSEL_q; INTER_ZEI <= INTER_ZEI_q; DOP_FIFO_CLR <= DOP_FIFO_CLR_q; @@ -561,18 +544,18 @@ begin process (pixel_clk_i) begin if rising_edge(pixel_clk_i) then - CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d; + clut_mux_adr_q <= clut_mux_adr_d; HSYNC_q <= HSYNC_d; VSYNC_q <= VSYNC_d; nBLANK_q <= nBLANK_d; FIFO_RDE_q <= FIFO_RDE_d; - if BORDER_COLOR16_ena_ctrl = '1' then + if border_color16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); end if; - if BORDER_COLOR8_ena_ctrl = '1' THEN + if border_color8_ena_ctrl = '1' THEN border_color_q(15 downto 8) <= border_color_d(15 downto 8); END IF; - IF BORDER_COLOR0_ena_ctrl = '1' THEN + IF border_color0_ena_ctrl = '1' THEN border_color_q(7 downto 0) <= border_color_d(7 downto 0); END IF; CCSEL_q <= CCSEL_d; @@ -602,7 +585,7 @@ begin END IF; END PROCESS; - VR_FRQ <= unsigned(VR_FRQ_q); + vr_frq <= unsigned(vr_frq_q); PROCESS (main_clk) BEGIN @@ -613,63 +596,63 @@ begin CLK17M_q <= CLK17M_d; - IF VR_DOUT0_ena_ctrl = '1' THEN - VR_DOUT_q <= VR_DOUT_d; + IF vr_dout0_ena_ctrl = '1' THEN + vr_dout_q <= vr_dout_d; END IF; - IF VR_FRQ0_ena_ctrl = '1' THEN - VR_FRQ_q <= VR_FRQ_d; + IF vr_frq0_ena_ctrl = '1' THEN + vr_frq_q <= vr_frq_d; END IF; - IF ST_SHIFT_MODE0_ena_ctrl = '1' THEN - ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d; + IF st_shift_mode0_ena_ctrl = '1' THEN + st_shift_mode_q <= st_shift_mode_d; END IF; - IF FALCON_SHIFT_MODE8_ena_ctrl = '1' THEN + IF falcon_shift_mode8_ena_ctrl = '1' THEN falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); END IF; - IF FALCON_SHIFT_MODE0_ena_ctrl = '1' THEN + IF falcon_shift_mode0_ena_ctrl = '1' THEN falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); END IF; - IF ACP_VCTR24_ena_ctrl = '1' THEN - ACP_VCTR_q(31 downto 24) <= ACP_VCTR_d(31 downto 24); + IF acp_vctr24_ena_ctrl = '1' THEN + acp_vctr_q(31 downto 24) <= acp_vctr_d(31 downto 24); END IF; - IF ACP_VCTR16_ena_ctrl = '1' THEN - ACP_VCTR_q(23 downto 16) <= ACP_VCTR_d(23 downto 16); + IF acp_vctr16_ena_ctrl = '1' THEN + acp_vctr_q(23 downto 16) <= acp_vctr_d(23 downto 16); END IF; - IF ACP_VCTR8_ena_ctrl = '1' THEN - ACP_VCTR_q(15 downto 8) <= ACP_VCTR_d(15 downto 8); + IF acp_vctr8_ena_ctrl = '1' THEN + acp_vctr_q(15 downto 8) <= acp_vctr_d(15 downto 8); END IF; - IF ACP_VCTR6_ena_ctrl = '1' THEN - ACP_VCTR_q(7 downto 6) <= ACP_VCTR_d(7 downto 6); + IF acp_vctr6_ena_ctrl = '1' THEN + acp_vctr_q(7 downto 6) <= acp_vctr_d(7 downto 6); END IF; - IF ACP_VCTR0_ena_ctrl = '1' THEN - ACP_VCTR_q(5 downto 0) <= ACP_VCTR_d(5 downto 0); + IF acp_vctr0_ena_ctrl = '1' THEN + acp_vctr_q(5 downto 0) <= acp_vctr_d(5 downto 0); END IF; - IF SYS_CTR0_ena_ctrl='1' THEN - SYS_CTR_q <= SYS_CTR_d; + IF sys_ctr0_ena_ctrl='1' THEN + sys_ctr_q <= sys_ctr_d; END IF; - IF LOF8_ena_ctrl = '1' THEN - LOF_q(15 downto 8) <= LOF_d(15 downto 8); + IF lof8_ena_ctrl = '1' THEN + lof_q(15 downto 8) <= lof_d(15 downto 8); END IF; - IF LOF0_ena_ctrl = '1' THEN - LOF_q(7 downto 0) <= LOF_d(7 downto 0); + IF lof0_ena_ctrl = '1' THEN + lof_q(7 downto 0) <= lof_d(7 downto 0); END IF; - IF LWD8_ena_ctrl = '1' THEN - LWD_q(15 downto 8) <= LWD_d(15 downto 8); + IF lwd8_ena_ctrl = '1' THEN + lwd_q(15 downto 8) <= lwd_d(15 downto 8); END IF; - IF LWD0_ena_ctrl = '1' THEN - LWD_q(7 downto 0) <= LWD_d(7 downto 0); + IF lwd0_ena_ctrl = '1' THEN + lwd_q(7 downto 0) <= lwd_d(7 downto 0); END IF; IF HDB8_ena_ctrl = '1' THEN @@ -771,8 +754,8 @@ begin PROCESS (pixel_clk_i) BEGIN IF rising_edge(pixel_clk_i) THEN - CLUT_MUX_AV1_q <= CLUT_MUX_AV1_d; - CLUT_MUX_AV0_q <= CLUT_MUX_AV0_d; + clut_mux_av1_q <= clut_mux_av1_d; + clut_mux_av0_q <= clut_mux_av0_d; CLUT_TA_q <= CLUT_TA_d; HSYNC_I_q <= HSYNC_I_d; HSY_LEN_q <= HSY_LEN_d; @@ -972,31 +955,31 @@ begin -- $F8260/2 st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0'; - -- ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); - ST_SHIFT_MODE_d <= FB_AD(25 downto 24); - ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0); + -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); + st_shift_mode_d <= FB_AD(25 downto 24); + st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0); -- MONO - COLOR1_1 <= to_std_logic(ST_SHIFT_MODE_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR1_1 <= to_std_logic(st_shift_mode_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); -- 4 FARBEN - COLOR2 <= to_std_logic(ST_SHIFT_MODE_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR2 <= to_std_logic(st_shift_mode_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); -- 16 FARBEN - COLOR4_1 <= to_std_logic(ST_SHIFT_MODE_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); -- FALCON SHIFT MODE -- $F8266/2 - FALCON_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); - FALCON_SHIFT_MODE_d <= FB_AD(26 downto 16); - FALCON_SHIFT_MODE8_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(2); - FALCON_SHIFT_MODE0_ena_ctrl <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and FB_B(3); + falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); + falcon_shift_mode_d <= FB_AD(26 downto 16); + falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2); + falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3); - CLUT_OFF <= FALCON_SHIFT_MODE_q(3 downto 0) and sizeIt(COLOR4_i, 4); - COLOR1_2 <= FALCON_SHIFT_MODE_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR8_1 <= FALCON_SHIFT_MODE_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR16_1 <= FALCON_SHIFT_MODE_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + CLUT_OFF <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); + COLOR1_2 <= falcon_shift_mode_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR8_1 <= falcon_shift_mode_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR16_1 <= falcon_shift_mode_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); -- ACP VIDEO CONTROL @@ -1015,21 +998,21 @@ begin -- BIT 26 = STANDARD ATARI SYNCS -- $400/4 - ACP_VCTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); + acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); - ACP_VCTR_d(31 downto 8) <= FB_AD(31 downto 8); - ACP_VCTR_d(5 downto 0) <= FB_AD(5 downto 0); + acp_vctr_d(31 downto 8) <= FB_AD(31 downto 8); + acp_vctr_d(5 downto 0) <= FB_AD(5 downto 0); - ACP_VCTR24_ena_ctrl <= ACP_VCTR_CS and FB_B(0) and (not nFB_WR); - ACP_VCTR16_ena_ctrl <= ACP_VCTR_CS and FB_B(1) and (not nFB_WR); - ACP_VCTR8_ena_ctrl <= ACP_VCTR_CS and FB_B(2) and (not nFB_WR); - ACP_VCTR0_ena_ctrl <= ACP_VCTR_CS and FB_B(3) and (not nFB_WR); - ACP_VIDEO_ON <= ACP_VCTR_q(0); - nPD_VGA <= ACP_VCTR_q(1); + acp_vctr24_ena_ctrl <= acp_vctr_CS and FB_B(0) and (not nFB_WR); + acp_vctr16_ena_ctrl <= acp_vctr_CS and FB_B(1) and (not nFB_WR); + acp_vctr8_ena_ctrl <= acp_vctr_CS and FB_B(2) and (not nFB_WR); + acp_vctr0_ena_ctrl <= acp_vctr_CS and FB_B(3) and (not nFB_WR); + ACP_VIDEO_ON <= acp_vctr_q(0); + nPD_VGA <= acp_vctr_q(1); -- ATARI MODUS - -- WENN 1 AUTOMATISCHE AUFLÖSUNG - ATARI_SYNC <= ACP_VCTR_q(26); + -- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC <= acp_vctr_q(26); -- HORIZONTAL TIMING 640x480 @@ -1076,10 +1059,10 @@ begin VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q); VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); - VR_DOUT0_ena_ctrl <= not VR_BUSY; - VR_DOUT_d <= VR_D; - VR_FRQ0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); - VR_FRQ_d <= FB_AD(23 downto 16); + vr_dout0_ena_ctrl <= not VR_BUSY; + vr_dout_d <= VR_D; + vr_frq0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); + vr_frq_d <= FB_AD(23 downto 16); -- VIDEO PLL RECONFIG -- $(F)000'0800 @@ -1087,23 +1070,23 @@ begin VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); -- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR <= ACP_VCTR_q(31 downto 16); + VIDEO_RAM_CTR <= acp_vctr_q(31 downto 16); -- ------------ COLOR MODE IM ACP SETZEN - COLOR1_3 <= ACP_VCTR_q(5) and (not ACP_VCTR_q(4)) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR8_2 <= ACP_VCTR_q(4) and (not ACP_VCTR_q(3)) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR16_2 <= ACP_VCTR_q(3) and (not ACP_VCTR_q(2)) and ACP_VIDEO_ON; - COLOR24 <= ACP_VCTR_q(2) and ACP_VIDEO_ON; + COLOR1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + COLOR8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + COLOR16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + COLOR24 <= acp_vctr_q(2) and ACP_VIDEO_ON; ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR_d(7) <= FALCON_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - ACP_VCTR_d(6) <= ST_SHIFT_MODE_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - ACP_VCTR6_ena_ctrl <= (FALCON_SHIFT_MODE_CS and (not nFB_WR)) or (ST_SHIFT_MODE_CS and (not nFB_WR)) or (ACP_VCTR_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); - FALCON_VIDEO <= ACP_VCTR_q(7); + acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); + FALCON_VIDEO <= acp_vctr_q(7); FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); - ST_VIDEO <= ACP_VCTR_q(6); + ST_VIDEO <= acp_vctr_q(6); ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not COLOR1); pixel_clk_i <= pixel_clk; @@ -1117,11 +1100,11 @@ begin -- RANDFARBE -- $404/4 - BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); - BORDER_COLOR_d <= FB_AD(23 downto 0); - BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR); - BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR); - BORDER_COLOR0_ena_ctrl <= BORDER_COLOR_CS and FB_B(3) and (not nFB_WR); + border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); + border_color_d <= FB_AD(23 downto 0); + border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR); + border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR); + border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR); -- System Config Register -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi @@ -1146,27 +1129,28 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp(FB_ADR, 20x"f8006", 1); + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(FB_ADR, 20x"f8006") = '1'; -- FB_ADR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; - -- SYS_CTR_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); - SYS_CTR_d <= FB_AD(22 downto 16); - SYS_CTR0_ena_ctrl <= SYS_CTR_CS and (not nFB_WR) and FB_B(3); - BLITTER_ON <= not SYS_CTR_q(3); + -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); + sys_ctr_d <= FB_AD(22 downto 16); + sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3); + BLITTER_ON <= not sys_ctr_q(3); - -- LOF + -- lof -- $820E/2 - LOF_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); - LOF_d <= FB_AD(31 downto 16); - LOF8_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(2); - LOF0_ena_ctrl <= LOF_CS and (not nFB_WR) and FB_B(3); - - -- LWD + lof_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); + lof_d <= FB_AD(31 downto 16); + lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2); + lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3); + lof <= lof_q; + + -- lwd -- $8210/2 - LWD_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); - LWD_d <= FB_AD(31 downto 16); - LWD8_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(0); - LWD0_ena_ctrl <= LWD_CS and (not nFB_WR) and FB_B(1); + lwd_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); + lwd_d <= FB_AD(31 downto 16); + lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0); + lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1); -- HORIZONTAL -- HHT @@ -1249,7 +1233,8 @@ begin -- VFT -- $82A2/2 - VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); + -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); + vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); VFT_d <= FB_AD(26 downto 16); VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); @@ -1269,10 +1254,10 @@ begin -- - REGISTER OUT -- low word register access --- u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or --- (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or --- (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or --- (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or +-- u0_data <= (sizeIt(st_shift_mode_CS,16) and std_logic_vector'("000000" & st_shift_mode_q & "00000000")) or +-- (sizeIt(falcon_shift_mode_CS,16) and std_logic_vector'("00000" & falcon_shift_mode_q)) or +-- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not BLITTER_RUN) & sys_ctr_q(2 downto 0))) or +-- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or -- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or -- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or -- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or @@ -1287,13 +1272,13 @@ begin -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or -- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or --- (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or +-- (sizeIt(acp_vctr_CS,16) and acp_vctr_q(31 downto 16)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or --- (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or --- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or +-- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or +-- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else @@ -1320,22 +1305,22 @@ begin atari_vl_q(31 downto 16) when atari_vl_cs = '1' else "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else "0000000" & vr_dout_q when video_pll_config_cs = '1' else - vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else (others => 'Z'); --- u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or +-- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); -- FB_AD(31 downto 16) <= u0_tridata; -- high word register access --- u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or +-- u1_data <= (sizeIt(acp_vctr_CS,16) and acp_vctr_q(15 downto 0)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or --- (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); --- u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); +-- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); +-- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); -- FB_AD(15 downto 0) <= u1_tridata; fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else @@ -1346,7 +1331,7 @@ begin border_color_q(15 downto 0) when border_color_cs = '1' else (others => 'Z'); - video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or + video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; @@ -1362,12 +1347,12 @@ begin (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or (CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or - (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "00")) or - (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and ACP_VCTR_q(9 downto 8) = "01")) or - (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9)); + (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "00")) or + (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "01")) or + (CLK_VIDEO and ACP_VIDEO_ON and acp_vctr_q(9)); -- ------------------------------------------------------------ - -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK + -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK -- -------------------------------------------------------------- -- 320 pixels, 32 MHz, RGB @@ -1389,9 +1374,9 @@ begin -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "00"), 8)) or - -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(ACP_VCTR_q(9 downto 8) = "01"), 8)) or - -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & VR_FRQ_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(ACP_VCTR_q(9), 8)); + -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or + -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or + -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(acp_vctr_q(9), 8)); -- MULTIPLIKATIONS FAKTOR MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or @@ -1414,7 +1399,7 @@ begin VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); --- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START +-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; -- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON @@ -1493,7 +1478,7 @@ begin VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - -- ZÄHLER + -- ZÄHLER LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); @@ -1505,7 +1490,7 @@ begin -- 1 ZEILE DAVOR ON OFF DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); - -- AM ZEILENENDE ÃœBERNEHMEN + -- AM ZEILENENDE ÃœBERNEHMEN DPO_ZL_ena <= LAST_q; -- BESSER EINZELN WEGEN TIMING @@ -1521,7 +1506,7 @@ begin VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); - -- AM ZEILENENDE ÃœBERNEHMEN + -- AM ZEILENENDE ÃœBERNEHMEN VCO_ZL_ena <= LAST_q; -- 1 ZEILE DAVOR ON OFF @@ -1529,7 +1514,7 @@ begin VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); - -- VERZÖGERUNG UND SYNC + -- VERZÖGERUNG UND SYNC HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); @@ -1547,7 +1532,7 @@ begin VSYNC_I0_ena_ctrl <= LAST_q; -- 3 zeilen vsync length - -- runterzählen bis 0 + -- runterzählen bis 0 VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else (others => '0'); @@ -1567,14 +1552,14 @@ begin VERZ0_d(0) <= DISP_ON_q; -- VERZ[1][0] = HSYNC_I[] != 0; - -- NUR MÖGLICH WENN BEIDE - VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') - and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + VERZ1_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') + and HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); - -- NUR MÖGLICH WENN BEIDE - VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') - and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + VERZ2_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') + and VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); -- nBLANK = VERZ[0][8]; @@ -1583,20 +1568,20 @@ begin -- nBLANK_d <= DISP_ON_q; -- HSYNC = VERZ[1][9]; - -- NUR MÖGLICH WENN BEIDE - HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and - HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + HSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and + HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); -- VSYNC = VERZ[2][9]; - -- NUR MÖGLICH WENN BEIDE - VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and - VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and + -- NUR MÖGLICH WENN BEIDE + VSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and + VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); nSYNC <= gnd; -- RANDFARBE MACHEN ------------------------------------ - RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); RAND_d(1) <= RAND_q(0); RAND_d(2) <= RAND_q(1); RAND_d(3) <= RAND_q(2); @@ -1606,25 +1591,25 @@ begin -- RAND_ON = RAND[6]; rand_on <= rand(6); - -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); + -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); -- -------------------------------------------------------- CLR_FIFO_ena <= LAST_q; - -- IN LETZTER ZEILE LÖSCHEN + -- IN LETZTER ZEILE LÖSCHEN CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); START_ZEILE_ena <= LAST_q; -- ZEILE 1 START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; @@ -1632,7 +1617,7 @@ begin -- count up if display on sonst clear bei sync pix SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or @@ -1641,9 +1626,9 @@ begin (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 downto 0); - CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; - CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; + clut_mux_av0_d <= SUB_PIXEL_CNT_q(3 downto 0); + clut_mux_av1_d <= clut_mux_av0_q; + clut_mux_adr_d <= clut_mux_av1_q; -- Assignments added to explicitly combine the diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index f42b241..5b8eadb 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,311 +556,312 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file From a40b7175e5d2ea0d38009138a419503d606c65ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 2 Jun 2016 16:28:02 +0000 Subject: [PATCH 098/127] replace translator output with more clear VHDL --- .../Video/video_mod_mux_clutctr.vhd | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index ce2a412..04b99f0 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -263,7 +263,7 @@ architecture rtl of video_mod_mux_clutctr is signal VCO_ena : std_logic_vector(8 downto 0); signal VCO_q : std_logic_vector(8 downto 0); signal VCNTRL : std_logic_vector(3 downto 0) := (others => '0'); - signal VCNTRL_d : std_logic_vector(3 downto 0); + signal vcntrl_d : std_logic_vector(3 downto 0); signal VCNTRL_q : std_logic_vector(3 downto 0); signal u0_data : std_logic_vector(15 downto 0); signal u0_tridata : std_logic_vector(15 downto 0); @@ -350,7 +350,7 @@ architecture rtl of video_mod_mux_clutctr is signal gnd : std_logic; signal u1_enabledt : std_logic; signal u0_enabledt : std_logic; - signal VCNTRL_CS : std_logic; + signal vcntrl_cs : std_logic; signal VCO_CS : std_logic; signal VFT_CS : std_logic; signal VSS_CS : std_logic; @@ -528,7 +528,7 @@ begin HBE <= HBE_q; HSS <= HSS_q; VCO <= VCO_q; - VCNTRL <= VCNTRL_d; + VCNTRL <= vcntrl_q; VSYNC <= VSYNC_q; nBLANK <= nBLANK_q; @@ -746,7 +746,7 @@ begin END IF; IF VCNTRL0_ena_ctrl = '1' THEN - VCNTRL_q <= VCNTRL_d; + VCNTRL_q <= vcntrl_d; END IF; END IF; END PROCESS; @@ -1248,9 +1248,9 @@ begin -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL - VCNTRL_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101100001"); - VCNTRL_d <= FB_AD(19 downto 16); - VCNTRL0_ena_ctrl <= VCNTRL_CS and (not nFB_WR) and FB_B(3); + vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; + vcntrl_d <= FB_AD(19 downto 16); + VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and FB_B(3); -- - REGISTER OUT -- low word register access @@ -1271,7 +1271,7 @@ begin -- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or --- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or +-- (sizeIt(vcntrl_cs,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or -- (sizeIt(acp_vctr_CS,16) and acp_vctr_q(31 downto 16)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or @@ -1310,7 +1310,7 @@ begin -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or --- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); +-- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); -- FB_AD(31 downto 16) <= u0_tridata; -- high word register access @@ -1333,7 +1333,7 @@ begin video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or - VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS; + VSS_CS or VFT_CS or VCO_CS or vcntrl_cs; -- VIDEO AUSGABE SETZEN CLK17M_d <= not CLK17M_q; From 26125ea4a8f00e5e5764f7d5138f81650535ca45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 3 Jun 2016 07:43:07 +0000 Subject: [PATCH 099/127] formatting --- .../Video/video_mod_mux_clutctr.vhd | 519 +++++++++--------- FPGA_Quartus_13.1/firebee1.qws | Bin 4388 -> 2309 bytes 2 files changed, 260 insertions(+), 259 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 04b99f0..57ea633 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -64,54 +64,54 @@ entity video_mod_mux_clutctr is port ( nRSTO : in std_logic; - MAIN_CLK : in std_logic; + main_clk : in std_logic; nFB_CS1 : in std_logic; nFB_CS2 : in std_logic; nFB_CS3 : in std_logic; nFB_WR : in std_logic; nFB_OE : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; + fb_size0 : in std_logic; + fb_size1 : in std_logic; nFB_BURST : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - CLK33M : in std_logic; - CLK25M : in std_logic; - BLITTER_RUN : in std_logic; - CLK_VIDEO : in std_logic; - VR_D : in std_logic_vector(8 downto 0); - VR_BUSY : in std_logic; - COLOR8 : out std_logic; - ACP_CLUT_RD : out std_logic; - COLOR1 : out std_logic; - FALCON_CLUT_RDH : out std_logic; - FALCON_CLUT_RDL : out std_logic; - FALCON_CLUT_WR : out std_logic_vector(3 downto 0); - ST_CLUT_RD : out std_logic; - ST_CLUT_WR : out std_logic_vector(1 downto 0); + fb_adR : in std_logic_vector(31 downto 0); + clk33m : in std_logic; + clk25m : in std_logic; + blitter_run : in std_logic; + clk_video : in std_logic; + vr_d : in std_logic_vector(8 downto 0); + vr_busy : in std_logic; + color8 : out std_logic; + acp_clut_rd : out std_logic; + color1 : out std_logic; + falcon_clut_rdh : out std_logic; + falcon_clut_rdl : out std_logic; + falcon_clut_wr : out std_logic_vector(3 downto 0); + st_clut_rd : out std_logic; + st_clut_wr : out std_logic_vector(1 downto 0); clut_mux_adr : out std_logic_vector(3 downto 0); - HSYNC : out std_logic; - VSYNC : out std_logic; + hsync : out std_logic; + vsync : out std_logic; nBLANK : out std_logic; nSYNC : out std_logic; nPD_VGA : out std_logic; - FIFO_RDE : out std_logic; - COLOR2 : out std_logic; + fifo_rde : out std_logic; + color2 : out std_logic; color4 : out std_logic; - PIXEL_CLK : out std_logic; - CLUT_OFF : out std_logic_vector(3 downto 0); - BLITTER_ON : out std_logic; - VIDEO_RAM_CTR : out std_logic_vector(15 downto 0); - VIDEO_MOD_TA : out std_logic; + pixel_clk : out std_logic; + clut_off : out std_logic_vector(3 downto 0); + blitter_on : out std_logic; + video_ram_ctr : out std_logic_vector(15 downto 0); + video_mod_ta : out std_logic; border_color : out std_logic_vector(23 downto 0); - CCSEL : out std_logic_vector(2 downto 0); - ACP_CLUT_WR : out std_logic_vector(3 downto 0); - INTER_ZEI : out std_logic; - DOP_FIFO_CLR : out std_logic; - VIDEO_RECONFIG : out std_logic; - VR_WR : out std_logic; - VR_RD : out std_logic; - CLR_FIFO : out std_logic; - FB_AD : out std_logic_vector(31 downto 0) + ccsel : out std_logic_vector(2 downto 0); + acp_clut_wr : out std_logic_vector(3 downto 0); + inter_zei : out std_logic; + dop_fifo_clr : out std_logic; + video_reconfig : out std_logic; + vr_wr : out std_logic; + vr_rd : out std_logic; + clr_fifo : out std_logic; + fb_ad : out std_logic_vector(31 downto 0) ); end video_mod_mux_clutctr; @@ -119,7 +119,7 @@ end video_mod_mux_clutctr; architecture rtl of video_mod_mux_clutctr is -- DIV. CONTROL REGISTER -- BRAUCHT EIN WAITSTAT - -- LÄNGE HSYNC PULS IN PIXEL_CLK + -- LÄNGE hsync PULS IN pixel_clk -- LETZTES PIXEL EINER ZEILE ERREICHT -- ATARI RESOLUTION -- HORIZONTAL TIMING 640x480 @@ -164,15 +164,15 @@ architecture rtl of video_mod_mux_clutctr is signal lwd : std_logic_vector(15 downto 0); signal lwd_d : std_logic_vector(15 downto 0); signal lwd_q : std_logic_vector(15 downto 0); - signal HSYNC_I : std_logic_vector(7 downto 0); - signal HSYNC_I_d : std_logic_vector(7 downto 0); - signal HSYNC_I_q : std_logic_vector(7 downto 0); + signal hsync_I : std_logic_vector(7 downto 0); + signal hsync_I_d : std_logic_vector(7 downto 0); + signal hsync_I_q : std_logic_vector(7 downto 0); signal HSY_LEN : std_logic_vector(7 downto 0); signal HSY_LEN_d : std_logic_vector(7 downto 0); signal HSY_LEN_q : std_logic_vector(7 downto 0); - signal VSYNC_I : std_logic_vector(2 downto 0); - signal VSYNC_I_d : std_logic_vector(2 downto 0); - signal VSYNC_I_q : std_logic_vector(2 downto 0); + signal vsync_I : std_logic_vector(2 downto 0); + signal vsync_I_d : std_logic_vector(2 downto 0); + signal vsync_I_q : std_logic_vector(2 downto 0); signal VHCNT : std_logic_vector(11 downto 0); signal VHCNT_d : std_logic_vector(11 downto 0); signal VHCNT_q : std_logic_vector(11 downto 0); @@ -194,8 +194,8 @@ architecture rtl of video_mod_mux_clutctr is signal RAND : std_logic_vector(6 downto 0) := (others => '0'); signal RAND_d : std_logic_vector(6 downto 0); signal RAND_q : std_logic_vector(6 downto 0); - signal CCSEL_d : std_logic_vector(2 downto 0); - signal CCSEL_q : std_logic_vector(2 downto 0); + signal ccsel_d : std_logic_vector(2 downto 0); + signal ccsel_q : std_logic_vector(2 downto 0); signal ATARI_HH : std_logic_vector(31 downto 0) := (others => '0'); signal ATARI_HH_d : std_logic_vector(31 downto 0); signal ATARI_HH_q : std_logic_vector(31 downto 0); @@ -336,17 +336,17 @@ architecture rtl of video_mod_mux_clutctr is signal VCO0_ena_ctrl : std_logic; signal VCNTRL0_ena_ctrl : std_logic; signal VVCNT0_ena_ctrl : std_logic; - signal VSYNC_I0_ena_ctrl : std_logic; + signal vsync_I0_ena_ctrl : std_logic; signal SUB_PIXEL_CNT0_ena_ctrl : std_logic; - signal COLOR8_2 : std_logic; - signal COLOR8_1 : std_logic; - signal COLOR1_3 : std_logic; - signal COLOR1_2 : std_logic; - signal COLOR1_1 : std_logic; + signal color8_2 : std_logic; + signal color8_1 : std_logic; + signal color1_3 : std_logic; + signal color1_2 : std_logic; + signal color1_1 : std_logic; signal COLOR4_2 : std_logic; signal COLOR4_1 : std_logic; - signal COLOR16_2 : std_logic; - signal COLOR16_1 : std_logic; + signal color16_2 : std_logic; + signal color16_1 : std_logic; signal gnd : std_logic; signal u1_enabledt : std_logic; signal u0_enabledt : std_logic; @@ -358,13 +358,13 @@ architecture rtl of video_mod_mux_clutctr is signal VDE_CS : std_logic; signal VDB_CS : std_logic; signal VBE_CS : std_logic; - signal DOP_FIFO_CLR_q : std_logic; - signal DOP_FIFO_CLR_d : std_logic; + signal dop_fifo_clr_q : std_logic; + signal dop_fifo_clr_d : std_logic; signal DOP_ZEI_q : std_logic; signal DOP_ZEI_d : std_logic; signal DOP_ZEI : std_logic; - signal INTER_ZEI_q : std_logic; - signal INTER_ZEI_d : std_logic; + signal inter_zei_q : std_logic; + signal inter_zei_d : std_logic; signal ST_VIDEO : std_logic; signal FALCON_VIDEO : std_logic; signal HSS_CS : std_logic; @@ -378,8 +378,8 @@ architecture rtl of video_mod_mux_clutctr is signal ATARI_VH_CS : std_logic; signal ATARI_HH_CS : std_logic; signal ATARI_SYNC : std_logic; - signal COLOR24 : std_logic; - signal COLOR16 : std_logic; + signal color24 : std_logic; + signal color16 : std_logic; signal SYNC_PIX2_q : std_logic; signal SYNC_PIX2_d : std_logic; signal SYNC_PIX2 : std_logic; @@ -393,11 +393,11 @@ architecture rtl of video_mod_mux_clutctr is signal START_ZEILE_ena : std_logic; signal START_ZEILE_d : std_logic; signal START_ZEILE : std_logic; - signal CLR_FIFO_q : std_logic; - signal CLR_FIFO_ena : std_logic; - signal CLR_FIFO_d : std_logic; - signal FIFO_RDE_q : std_logic; - signal FIFO_RDE_d : std_logic; + signal clr_fifo_q : std_logic; + signal clr_fifo_ena : std_logic; + signal clr_fifo_d : std_logic; + signal fifo_rde_q : std_logic; + signal fifo_rde_d : std_logic; signal RAND_ON : std_logic; signal VCO_OFF_q : std_logic; signal VCO_OFF_d : std_logic; @@ -427,20 +427,20 @@ architecture rtl of video_mod_mux_clutctr is signal DISP_ON : std_logic; signal nBLANK_q : std_logic; signal nBLANK_d : std_logic; - signal VSYNC_START_q : std_logic; - signal VSYNC_START_ena : std_logic; - signal VSYNC_START_d : std_logic; - signal VSYNC_START : std_logic; - signal VSYNC_q : std_logic; - signal VSYNC_d : std_logic; + signal vsync_START_q : std_logic; + signal vsync_START_ena : std_logic; + signal vsync_START_d : std_logic; + signal vsync_START : std_logic; + signal vsync_q : std_logic; + signal vsync_d : std_logic; signal LAST_q : std_logic; signal LAST_d : std_logic; signal LAST : std_logic; - signal HSYNC_START_q : std_logic; - signal HSYNC_START_d : std_logic; - signal HSYNC_START : std_logic; - signal HSYNC_q : std_logic; - signal HSYNC_d : std_logic; + signal hsync_START_q : std_logic; + signal hsync_START_d : std_logic; + signal hsync_START : std_logic; + signal hsync_q : std_logic; + signal hsync_d : std_logic; signal CLUT_TA_q : std_logic; signal CLUT_TA_d : std_logic; signal CLUT_TA : std_logic; @@ -456,11 +456,11 @@ architecture rtl of video_mod_mux_clutctr is signal ST_CLUT_CS : std_logic; signal FALCON_CLUT : std_logic; signal FALCON_CLUT_CS : std_logic; - signal VIDEO_RECONFIG_q : std_logic; - signal VIDEO_RECONFIG_d : std_logic; + signal video_reconfig_q : std_logic; + signal video_reconfig_d : std_logic; signal VIDEO_PLL_RECONFIG_CS : std_logic; - signal VR_WR_q : std_logic; - signal VR_WR_d : std_logic; + signal vr_wr_q : std_logic; + signal vr_wr_d : std_logic; signal VIDEO_PLL_CONFIG_CS : std_logic; signal ACP_CLUT : std_logic; signal ACP_CLUT_CS : std_logic; @@ -520,7 +520,7 @@ begin clut_mux_adr <= clut_mux_adr_q; -- missing signals that seem to got lost during conversion - HSYNC <= HSYNC_q; + hsync <= hsync_q; acp_vctr <= acp_vctr_q; RAND <= RAND_q; ATARI_HH <= ATARI_HH_q; @@ -530,25 +530,25 @@ begin VCO <= VCO_q; VCNTRL <= vcntrl_q; - VSYNC <= VSYNC_q; + vsync <= vsync_q; nBLANK <= nBLANK_q; - FIFO_RDE <= FIFO_RDE_q; + fifo_rde <= fifo_rde_q; border_color(23 downto 16) <= border_color_q(23 downto 16); border_color(15 downto 8) <= border_color_q(15 downto 8); border_color(7 downto 0) <= border_color_q(7 downto 0); - CCSEL <= CCSEL_q; - INTER_ZEI <= INTER_ZEI_q; - DOP_FIFO_CLR <= DOP_FIFO_CLR_q; + ccsel <= ccsel_q; + inter_zei <= inter_zei_q; + dop_fifo_clr <= dop_fifo_clr_q; HHT <= HHT_q; process (pixel_clk_i) begin if rising_edge(pixel_clk_i) then clut_mux_adr_q <= clut_mux_adr_d; - HSYNC_q <= HSYNC_d; - VSYNC_q <= VSYNC_d; + hsync_q <= hsync_d; + vsync_q <= vsync_d; nBLANK_q <= nBLANK_d; - FIFO_RDE_q <= FIFO_RDE_d; + fifo_rde_q <= fifo_rde_d; if border_color16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); end if; @@ -558,22 +558,22 @@ begin IF border_color0_ena_ctrl = '1' THEN border_color_q(7 downto 0) <= border_color_d(7 downto 0); END IF; - CCSEL_q <= CCSEL_d; - INTER_ZEI_q <= INTER_ZEI_d; - DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d; + ccsel_q <= ccsel_d; + inter_zei_q <= inter_zei_d; + dop_fifo_clr_q <= dop_fifo_clr_d; END IF; END PROCESS; - VIDEO_RECONFIG <= VIDEO_RECONFIG_q; + video_reconfig <= video_reconfig_q; - VR_WR <= VR_WR_q; + vr_wr <= vr_wr_q; - CLR_FIFO <= CLR_FIFO_q; + clr_fifo <= clr_fifo_q; PROCESS (pixel_clk_i) BEGIN IF rising_edge(pixel_clk_i) THEN - IF CLR_FIFO_ena = '1' THEN - CLR_FIFO_q <= CLR_FIFO_d; + IF clr_fifo_ena = '1' THEN + clr_fifo_q <= clr_fifo_d; END IF; END IF; END PROCESS; @@ -590,9 +590,9 @@ begin PROCESS (main_clk) BEGIN IF rising_edge(main_clk) THEN - VR_WR_q <= VR_WR_d; + vr_wr_q <= vr_wr_d; - VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d; + video_reconfig_q <= video_reconfig_d; CLK17M_q <= CLK17M_d; @@ -757,17 +757,17 @@ begin clut_mux_av1_q <= clut_mux_av1_d; clut_mux_av0_q <= clut_mux_av0_d; CLUT_TA_q <= CLUT_TA_d; - HSYNC_I_q <= HSYNC_I_d; + hsync_I_q <= hsync_I_d; HSY_LEN_q <= HSY_LEN_d; - HSYNC_START_q <= HSYNC_START_d; + hsync_START_q <= hsync_START_d; LAST_q <= LAST_d; - IF VSYNC_START_ena = '1' THEN - VSYNC_START_q <= VSYNC_START_d; + IF vsync_START_ena = '1' THEN + vsync_START_q <= vsync_START_d; END IF; - IF VSYNC_I0_ena_ctrl='1' THEN - VSYNC_I_q <= VSYNC_I_d; + IF vsync_I0_ena_ctrl='1' THEN + vsync_I_q <= vsync_I_d; END IF; DISP_ON_q <= DISP_ON_d; @@ -896,91 +896,92 @@ begin -- BYT SELECT 32 BIT -- ADR==0 - FB_B(0) <= to_std_logic(FB_ADR(1 downto 0) = "00"); + -- FB_B(0) <= to_std_logic(fb_adR(1 downto 0) = "00"); + fb_b(0) <= '1' when fb_adr(1 downto 0) = "00" else '0'; -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(FB_ADR(1 downto 0) = "01") or (FB_SIZE1 and (not - FB_SIZE0) and (not FB_ADR(1))) or (FB_SIZE1 and FB_SIZE0) or ((not - FB_SIZE1) and (not FB_SIZE0)); + FB_B(1) <= to_std_logic(fb_adR(1 downto 0) = "01") or (fb_size1 and (not + fb_size0) and (not fb_adR(1))) or (fb_size1 and fb_size0) or ((not + fb_size1) and (not fb_size0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(FB_ADR(1 downto 0) = "10") or (FB_SIZE1 and FB_SIZE0) or ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(2) <= to_std_logic(fb_adR(1 downto 0) = "10") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(FB_ADR(1 downto 0) = "11") or (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or - (FB_SIZE1 and FB_SIZE0) or - ((not FB_SIZE1) and (not FB_SIZE0)); + FB_B(3) <= to_std_logic(fb_adR(1 downto 0) = "11") or (fb_size1 and (not fb_size0) and fb_adR(1)) or + (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); -- BYT SELECT 16 BIT -- ADR==0 - FB_16B(0) <= to_std_logic(FB_ADR(0) = '0'); + FB_16B(0) <= to_std_logic(fb_adR(0) = '0'); -- ADR==1 -- NOT BYT - FB_16B(1) <= to_std_logic(FB_ADR(0) = '1') or (not ((not FB_SIZE1) and FB_SIZE0)); + FB_16B(1) <= to_std_logic(fb_adR(0) = '1') or (not ((not fb_size1) and fb_size0)); -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 10) = "000000000000000000"); - ACP_CLUT_RD <= ACP_CLUT_CS and (not nFB_OE); - ACP_CLUT_WR <= FB_B and sizeIt(ACP_CLUT_CS, 4) and sizeIt(not nFB_WR, 4); - CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not VIDEO_MOD_TA); + ACP_CLUT_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 10) = "000000000000000000"); + acp_clut_rd <= ACP_CLUT_CS and (not nFB_OE); + acp_clut_wr <= FB_B and sizeIt(ACP_CLUT_CS, 4) and sizeIt(not nFB_WR, 4); + CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not video_mod_ta); -- FALCON CLUT -- -- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 10) = "1111100110"); + FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 10) = "1111100110"); -- HIGH WORD - FALCON_CLUT_RDH <= FALCON_CLUT_CS and (not nFB_OE) and (not FB_ADR(1)); + falcon_clut_rdh <= FALCON_CLUT_CS and (not nFB_OE) and (not fb_adR(1)); -- LOW WORD - FALCON_CLUT_RDL <= FALCON_CLUT_CS and (not nFB_OE) and FB_ADR(1); - FALCON_CLUT_WR(1 downto 0) <= FB_16B and std_logic_vector'((not FB_ADR(1)) & - (not FB_ADR(1))) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - FALCON_CLUT_WR(3 downto 2) <= FB_16B and std_logic_vector'(FB_ADR(1) & FB_ADR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and + falcon_clut_rdl <= FALCON_CLUT_CS and (not nFB_OE) and fb_adR(1); + falcon_clut_wr(1 downto 0) <= FB_16B and std_logic_vector'((not fb_adR(1)) & + (not fb_adR(1))) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + falcon_clut_wr(3 downto 2) <= FB_16B and std_logic_vector'(fb_adR(1) & fb_adR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); -- ST CLUT -- -- $F8240/$20 - ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 5) = "111110000010010"); - ST_CLUT_RD <= ST_CLUT_CS and (not nFB_OE); - ST_CLUT_WR <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 5) = "111110000010010"); + st_clut_rd <= ST_CLUT_CS and (not nFB_OE); + st_clut_wr <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); -- ST SHIFT MODE -- $F8260/2 - st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0'; - -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000"); - st_shift_mode_d <= FB_AD(25 downto 24); + st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adR(19 downto 1) = 19x"7c130" else '0'; + -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110000"); + st_shift_mode_d <= fb_ad(25 downto 24); st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0); -- MONO - COLOR1_1 <= to_std_logic(st_shift_mode_q = "10") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + color1_1 <= to_std_logic(st_shift_mode_q = "10") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); -- 4 FARBEN - COLOR2 <= to_std_logic(st_shift_mode_q = "01") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + color2 <= to_std_logic(st_shift_mode_q = "01") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); -- 16 FARBEN - COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not COLOR8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); -- FALCON SHIFT MODE -- $F8266/2 - falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110011"); - falcon_shift_mode_d <= FB_AD(26 downto 16); + falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110011"); + falcon_shift_mode_d <= fb_ad(26 downto 16); falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2); falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3); - CLUT_OFF <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); - COLOR1_2 <= falcon_shift_mode_q(10) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR8_1 <= falcon_shift_mode_q(4) and (not COLOR16) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR16_1 <= falcon_shift_mode_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR4_2 <= (not COLOR1) and (not COLOR16) and (not COLOR8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + clut_off <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); + color1_2 <= falcon_shift_mode_q(10) and (not color16) and (not color8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + color8_1 <= falcon_shift_mode_q(4) and (not color16) and FALCON_VIDEO and (not ACP_VIDEO_ON); + color16_1 <= falcon_shift_mode_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + COLOR4_2 <= (not color1) and (not color16) and (not color8) and FALCON_VIDEO and (not ACP_VIDEO_ON); -- ACP VIDEO CONTROL -- BIT 0 = ACP VIDEO ON @@ -993,15 +994,15 @@ begin -- BIT 7 = ST SHIFT MODE -- BIT 9..8 = VCLK FREQUENZ -- BIT 15 =-SYNC ALLOWED - -- BIT 31..16 = VIDEO_RAM_CTR + -- BIT 31..16 = video_ram_ctr -- BIT 25 = RANDFARBE EINSCHALTEN -- BIT 26 = STANDARD ATARI SYNCS -- $400/4 - acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000000"); + acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000000"); - acp_vctr_d(31 downto 8) <= FB_AD(31 downto 8); - acp_vctr_d(5 downto 0) <= FB_AD(5 downto 0); + acp_vctr_d(31 downto 8) <= fb_ad(31 downto 8); + acp_vctr_d(5 downto 0) <= fb_ad(5 downto 0); acp_vctr24_ena_ctrl <= acp_vctr_CS and FB_B(0) and (not nFB_WR); acp_vctr16_ena_ctrl <= acp_vctr_CS and FB_B(1) and (not nFB_WR); @@ -1017,8 +1018,8 @@ begin -- HORIZONTAL TIMING 640x480 -- $410/4 - ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000100"); - ATARI_HH_d <= FB_AD; + ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000100"); + ATARI_HH_d <= fb_ad; ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); @@ -1027,8 +1028,8 @@ begin -- VERTIKAL TIMING 640x480 -- $414/4 - ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000101"); - ATARI_VH_d <= FB_AD; + ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000101"); + ATARI_VH_d <= fb_ad; ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); @@ -1037,8 +1038,8 @@ begin -- HORIZONTAL TIMING 320x240 -- $418/4 - ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000110"); - ATARI_HL_d <= FB_AD; + ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000110"); + ATARI_HL_d <= fb_ad; ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); @@ -1047,8 +1048,8 @@ begin -- VERTIKAL TIMING 320x240 -- $41C/4 - ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000000000100000111"); - ATARI_VL_d <= FB_AD; + ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000111"); + ATARI_VL_d <= fb_ad; ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); @@ -1056,52 +1057,52 @@ begin -- VIDEO PLL CONFIG -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); - VR_WR_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VR_WR_q); - VR_RD <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not VR_BUSY); - vr_dout0_ena_ctrl <= not VR_BUSY; - vr_dout_d <= VR_D; - vr_frq0_ena_ctrl <= to_std_logic(VR_WR_q='1' and FB_ADR(8 downto 0) = "000000100"); - vr_frq_d <= FB_AD(23 downto 16); + VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); + vr_wr_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not vr_busy) and (not vr_wr_q); + vr_rd <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not vr_busy); + vr_dout0_ena_ctrl <= not vr_busy; + vr_dout_d <= vr_d; + vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adR(8 downto 0) = "000000100"); + vr_frq_d <= fb_ad(23 downto 16); -- VIDEO PLL RECONFIG -- $(F)000'0800 - VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 0) = "0000000000000000100000000000") and FB_B(0); - VIDEO_RECONFIG_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not VR_BUSY) and (not VIDEO_RECONFIG_q); + VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 0) = "0000000000000000100000000000") and FB_B(0); + video_reconfig_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not vr_busy) and (not video_reconfig_q); -- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR <= acp_vctr_q(31 downto 16); + video_ram_ctr <= acp_vctr_q(31 downto 16); -- ------------ COLOR MODE IM ACP SETZEN - COLOR1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; - COLOR8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; - COLOR16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; - COLOR24 <= acp_vctr_q(2) and ACP_VIDEO_ON; - ACP_CLUT <= (ACP_VIDEO_ON and (COLOR1 or COLOR8)) or (ST_VIDEO and COLOR1); + color1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + color8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + color16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; + color24 <= acp_vctr_q(2) and ACP_VIDEO_ON; + ACP_CLUT <= (ACP_VIDEO_ON and (color1 or color8)) or (ST_VIDEO and color1); -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and FB_AD(0)); + acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and fb_ad(0)); FALCON_VIDEO <= acp_vctr_q(7); - FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not COLOR16); + FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not color16); ST_VIDEO <= acp_vctr_q(6); - ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not COLOR1); + ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not color1); pixel_clk_i <= pixel_clk; -- ONLY FOR INFORMATION - CCSEL_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and + ccsel_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and sizeIt(FALCON_CLUT,3)) or ("100" and sizeIt(ACP_CLUT,3)) or ("101" and - sizeIt(COLOR16,3)) or ("110" and sizeIt(COLOR24,3)) or ("111" and + sizeIt(color16,3)) or ("110" and sizeIt(color24,3)) or ("111" and sizeIt(RAND_ON,3)); -- DIVERSE (VIDEO)-REGISTER ---------------------------- -- RANDFARBE -- $404/4 - border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 downto 2) = "00000000000000000100000001"); - border_color_d <= FB_AD(23 downto 0); + border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 2) = "00000000000000000100000001"); + border_color_d <= fb_ad(23 downto 0); border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR); border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR); border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR); @@ -1129,134 +1130,134 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(FB_ADR, 20x"f8006") = '1'; - -- FB_ADR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1'; + -- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; - -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and FB_ADR(19 downto 1) = "1111100000000000011"); - sys_ctr_d <= FB_AD(22 downto 16); + -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011"); + sys_ctr_d <= fb_ad(22 downto 16); sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3); - BLITTER_ON <= not sys_ctr_q(3); + blitter_on <= not sys_ctr_q(3); -- lof -- $820E/2 - lof_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000111"); - lof_d <= FB_AD(31 downto 16); + lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100000111"); + lof_d <= fb_ad(31 downto 16); lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2); lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3); lof <= lof_q; -- lwd -- $8210/2 - lwd_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100001000"); - lwd_d <= FB_AD(31 downto 16); + lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100001000"); + lwd_d <= fb_ad(31 downto 16); lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0); lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1); -- HORIZONTAL -- HHT -- $8282/2 - HHT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000001"); - HHT_d <= FB_AD(27 downto 16); + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000001"); + HHT_d <= fb_ad(27 downto 16); HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); -- HBE -- $8286/2 - HBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000011"); - HBE_d <= FB_AD(27 downto 16); + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000011"); + HBE_d <= fb_ad(27 downto 16); HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); -- HDB -- $8288/2 - HDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000100"); - HDB_d <= FB_AD(27 downto 16); + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000100"); + HDB_d <= fb_ad(27 downto 16); HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); -- HDE -- $828A/2 - HDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000101"); - HDE_d <= FB_AD(27 downto 16); + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000101"); + HDE_d <= fb_ad(27 downto 16); HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); -- HBB -- $8284/2 - HBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000010"); - HBB_d <= FB_AD(27 downto 16); + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000010"); + HBB_d <= fb_ad(27 downto 16); HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); -- HSS - -- Videl HSYNC start register $828C / 2 - HSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101000110"); - HSS_d <= FB_AD(27 downto 16); + -- Videl hsync start register $828C / 2 + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000110"); + HSS_d <= fb_ad(27 downto 16); HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); -- VERTIKAL -- VBE -- $82A6/2 - VBE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010011"); - VBE_d <= FB_AD(26 downto 16); + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010011"); + VBE_d <= fb_ad(26 downto 16); VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); -- VDB -- $82A8/2 - VDB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010100"); - VDB_d <= FB_AD(26 downto 16); + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010100"); + VDB_d <= fb_ad(26 downto 16); VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); -- VDE -- $82AA/2 - VDE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010101"); - VDE_d <= FB_AD(26 downto 16); + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010101"); + VDE_d <= fb_ad(26 downto 16); VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); -- VBB -- $82A4/2 - VBB_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010010"); - VBB_d <= FB_AD(26 downto 16); + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010010"); + VBB_d <= fb_ad(26 downto 16); VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); -- VSS -- $82AC/2 - VSS_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010110"); - VSS_d <= FB_AD(26 downto 16); + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010110"); + VSS_d <= fb_ad(26 downto 16); VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); -- VFT -- $82A2/2 - -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101010001"); + -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010001"); vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); - VFT_d <= FB_AD(26 downto 16); + VFT_d <= fb_ad(26 downto 16); VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); -- VCO -- $82C0 / 2 Falcon clock control register VCO - VCO_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000101100000"); - VCO_d <= FB_AD(24 downto 16); + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101100000"); + VCO_d <= fb_ad(24 downto 16); VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; - vcntrl_d <= FB_AD(19 downto 16); + vcntrl_d <= fb_ad(19 downto 16); VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and FB_B(3); -- - REGISTER OUT -- low word register access -- u0_data <= (sizeIt(st_shift_mode_CS,16) and std_logic_vector'("000000" & st_shift_mode_q & "00000000")) or -- (sizeIt(falcon_shift_mode_CS,16) and std_logic_vector'("00000" & falcon_shift_mode_q)) or --- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not BLITTER_RUN) & sys_ctr_q(2 downto 0))) or +-- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0))) or -- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or -- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or -- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or @@ -1279,9 +1280,9 @@ begin -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or -- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or -- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or --- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); +-- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); - FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else + fb_ad(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else lwd_q when lof_cs = '1' and lwd_cs = '1' else "0000" & hbe_q when hbe_cs = '1' else @@ -1311,7 +1312,7 @@ begin -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); --- FB_AD(31 downto 16) <= u0_tridata; +-- fb_ad(31 downto 16) <= u0_tridata; -- high word register access -- u1_data <= (sizeIt(acp_vctr_CS,16) and acp_vctr_q(15 downto 0)) or @@ -1321,7 +1322,7 @@ begin -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or -- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); -- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); --- FB_AD(15 downto 0) <= u1_tridata; +-- fb_ad(15 downto 0) <= u1_tridata; fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else atari_hh_q(15 downto 0) when atari_hh_cs = '1' else @@ -1343,16 +1344,16 @@ begin -- 320 pixels, 25.175 MHz, -- 640 pixels, 32 MHz, VGA monitor -- 640 pixels, 25.175 MHz, VGA monitor - PIXEL_CLK <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or + pixel_clk <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or - (CLK25M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or - (CLK33M and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or - (to_std_logic((CLK25M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "00")) or - (to_std_logic((CLK33M and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "01")) or - (CLK_VIDEO and ACP_VIDEO_ON and acp_vctr_q(9)); + (clk25m and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or + (clk33m and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or + (to_std_logic((clk25m and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "00")) or + (to_std_logic((clk33m and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "01")) or + (clk_video and ACP_VIDEO_ON and acp_vctr_q(9)); -- ------------------------------------------------------------ - -- HORIZONTALE SYNC LÄNGE in PIXEL_CLK + -- HORIZONTALE SYNC LÄNGE in pixel_clk -- -------------------------------------------------------------- -- 320 pixels, 32 MHz, RGB @@ -1394,13 +1395,13 @@ begin -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC - INTER_ZEI_d <= (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) /= VDIS_START(0) + inter_zei_d <= (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) /= VDIS_START(0) and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) < unsigned(std_logic_vector(unsigned(HDIS_END) - 1))))) or (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q; + dop_fifo_clr_d <= (inter_zei_q and hsync_START_q) or SYNC_PIX_q; -- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON -- # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 @@ -1516,29 +1517,29 @@ begin -- VERZÖGERUNG UND SYNC - HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); + hsync_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); - HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or - ((std_logic_vector(unsigned(HSYNC_I_q) - 1)) and - sizeIt(not HSYNC_START_q,8) and sizeIt(to_std_logic(HSYNC_I_q /= + hsync_I_d <= (HSY_LEN_q and sizeIt(hsync_START_q,8)) or + ((std_logic_vector(unsigned(hsync_I_q) - 1)) and + sizeIt(not hsync_START_q,8) and sizeIt(to_std_logic(hsync_I_q /= "00000000"),8)); - VSYNC_START_ena <= LAST_q; + vsync_START_ena <= LAST_q; -- start am ende der Zeile vor dem vsync - VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); + vsync_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); -- start am ende der Zeile vor dem vsync - VSYNC_I0_ena_ctrl <= LAST_q; + vsync_I0_ena_ctrl <= LAST_q; -- 3 zeilen vsync length -- runterzählen bis 0 - VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else - std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= 3x"0" else + vsync_I_d <= 3x"3" when vsync_START_q = '1' else + std_logic_vector(unsigned(vsync_I_q) - 1) when vsync_START_q = '0' and vsync_I_q /= 3x"0" else (others => '0'); - -- VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or - -- ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); + -- vsync_I_d <= ("011" and sizeIt(vsync_START_q,3)) or + -- ((std_logic_vector(unsigned(vsync_I_q) - 1)) and sizeIt(not vsync_START_q,3) and sizeIt(to_std_logic(vsync_I_q /= "000"),3)); (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); @@ -1551,33 +1552,33 @@ begin (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & VERZ1_q(8) & VERZ0_q(8)); VERZ0_d(0) <= DISP_ON_q; - -- VERZ[1][0] = HSYNC_I[] != 0; + -- VERZ[1][0] = hsync_I[] != 0; -- NUR MÖGLICH WENN BEIDE VERZ1_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') - and HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(6))='1' and HSYNC_I_q = "00000000")); + and hsync_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(6))='1' and hsync_I_q = "00000000")); -- NUR MÖGLICH WENN BEIDE VERZ2_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') - and VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(5))='1' and VSYNC_I_q = "000")); + and vsync_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(5))='1' and vsync_I_q = "000")); -- nBLANK = VERZ[0][8]; nblank_d <= verz0_q(8); -- nBLANK_d <= DISP_ON_q; - -- HSYNC = VERZ[1][9]; + -- hsync = VERZ[1][9]; -- NUR MÖGLICH WENN BEIDE - HSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and - HSYNC_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(6))='1' and HSYNC_I_q = "00000000")); + hsync_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and + hsync_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(6))='1' and hsync_I_q = "00000000")); - -- VSYNC = VERZ[2][9]; + -- vsync = VERZ[2][9]; -- NUR MÖGLICH WENN BEIDE - VSYNC_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and - VSYNC_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(5))='1' and VSYNC_I_q = "000")); + vsync_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and + vsync_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(5))='1' and vsync_I_q = "000")); nSYNC <= gnd; -- RANDFARBE MACHEN ------------------------------------ @@ -1594,10 +1595,10 @@ begin -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); -- -------------------------------------------------------- - CLR_FIFO_ena <= LAST_q; + clr_fifo_ena <= LAST_q; -- IN LETZTER ZEILE LÖSCHEN - CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); + clr_fifo_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); START_ZEILE_ena <= LAST_q; -- ZEILE 1 @@ -1618,12 +1619,12 @@ begin SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or - (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or + fifo_rde_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and color1) or + (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and color2) or (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or - (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and COLOR8) or - (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and COLOR16) or - (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and COLOR24)) and + (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and color8) or + (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and color16) or + (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and color24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; clut_mux_av0_d <= SUB_PIXEL_CNT_q(3 downto 0); @@ -1633,11 +1634,11 @@ begin -- Assignments added to explicitly combine the -- effects of multiple drivers in the source - COLOR16 <= COLOR16_1 or COLOR16_2; + color16 <= color16_1 or color16_2; color4_i <= COLOR4_1 or COLOR4_2; color4 <= color4_i; - COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; - COLOR8 <= COLOR8_1 or COLOR8_2; + color1 <= color1_1 or color1_2 or color1_3; + color8 <= color8_1 or color8_2; -- Define power signal(s) gnd <= '0'; diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index cca85dd9557194a47310d37395700170f54caeed..f9c3c598df8372e82d773439fec4108bb645cd72 100644 GIT binary patch delta 200 zcmZ3Y)G9PVn~`ZU56>nR1_p+Xi3at&h75WPWegb%DL?_{$qjtLllgg$u(3n~d2X9) z`I{N}fD&N95(N~CpS*xgc5(+xI_pUW2FBf!zp$7HG42M+$1wc={~su{6fDfkb#n4K w=3WILryZ)B4amNa&YxVx7s&{62czNUDE?)PDj>y-GZ+|{>VcM(L$spv0VQuIuK)l5 delta 908 zcmaiz%WG3n5XQfAdy`v4vZzGyRf>ok+mhC_HQ+|2f>0MtT_{Lvo+>^Xo9aeNveD|I z)^c6B6pLLO*NWiAo&SK3rQItCM(S@)YeYAm!{p4&`Q~xvySdx*?7*YLi7rWxS28!_ z{wS56(Iw4kR<~4BU4uwjrTCS55rTTSl38pF>b5T9m6FJW?r1~>4eO|?XjSw9&aB4p z4QPm6Mh5U_kP2FcJ?yQj$B(E8rlN%nmYn3)$-IH+ClZ*#`i8pRZkQST;Agw?1l4GE zPV+=*FOd=F1(C-P+jN$abzN26vK~S{{=Vnr;Zc+GL))UAMWl3+d^d=h)iqVj&+@1z zmX${*7p;$YI(iqsOf2=`{B8n@i*Ofmk&rfagA!A5e>k7`LdaUY8fJTfH79S;zG}-WTpaQ(}r`c8*EfY;CHe%&m-;#Z%mxs?FJMGYli=cNR>QsGL6+ zDEJ?GYeBkoE_&b^K@%`5HdHu*1=_GdV;qwpcHhKsO<~Vn^jdV}YPMwCHswe$A<>z(92s3)08WKrw z5@nI@UTZo^y1rf=*ObOJsTrLj!vr73IOS$^f}6aHC%bpV%ia0juCFBc49mvDYdZML sjtj~2@f-J+VJ*2mh6~`>aDH`c!#Vr2w2noq?x0Ts!jjrl|Ftdn7k>Y?m;e9( From 43c8e5e1496f12190d3e34f4ae68a198c119fc33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 4 Jun 2016 06:36:00 +0000 Subject: [PATCH 100/127] add firebee_utils_pkg --- .../Video/video_mod_mux_clutctr.vhd | 652 +++++++++--------- FPGA_Quartus_13.1/firebee_utils_pkg.vhd | 171 +++++ 2 files changed, 497 insertions(+), 326 deletions(-) create mode 100644 FPGA_Quartus_13.1/firebee_utils_pkg.vhd diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 57ea633..293be1a 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -23,18 +23,18 @@ -- VERZ0_.clk VERZ0_clk -- VERZ0_.d VERZ0_d -- VERZ0_ VERZ0 --- VERZ1_.q VERZ1_q --- VERZ1_.prn VERZ1_prn --- VERZ1_.clrn VERZ1_clrn --- VERZ1_.clk VERZ1_clk --- VERZ1_.d VERZ1_d --- VERZ1_ VERZ1 --- VERZ2_.q VERZ2_q --- VERZ2_.prn VERZ2_prn --- VERZ2_.clrn VERZ2_clrn --- VERZ2_.clk VERZ2_clk --- VERZ2_.d VERZ2_d --- VERZ2_ VERZ2 +-- verz1_.q verz1_q +-- verz1_.prn verz1_prn +-- verz1_.clrn verz1_clrn +-- verz1_.clk verz1_clk +-- verz1_.d verz1_d +-- verz1_ verz1 +-- verz2_.q verz2_q +-- verz2_.prn verz2_prn +-- verz2_.clrn verz2_clrn +-- verz2_.clk verz2_clk +-- verz2_.d verz2_d +-- verz2_ verz2 -- clut_mux_av0_.q clut_mux_av0_q -- clut_mux_av0_.prn clut_mux_av0_prn -- clut_mux_av0_.clrn clut_mux_av0_clrn @@ -50,8 +50,8 @@ -- CREATED BY FREDI ASCHWANDEN --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_begin}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_end}} DO NOT REMOVE THIS LINE! library ieee; use ieee.std_logic_1164.all; @@ -134,7 +134,7 @@ architecture rtl of video_mod_mux_clutctr is signal vr_frq : unsigned(7 downto 0); signal vr_frq_d : std_logic_vector(7 downto 0); signal vr_frq_q : std_logic_vector(7 downto 0); - signal FB_B : std_logic_vector(3 downto 0); + signal fb_b : std_logic_vector(3 downto 0); signal FB_16B : std_logic_vector(1 downto 0); signal st_shift_mode : std_logic_vector(1 downto 0); signal st_shift_mode_d : std_logic_vector(1 downto 0); @@ -208,13 +208,13 @@ architecture rtl of video_mod_mux_clutctr is signal ATARI_VL : std_logic_vector(31 downto 0); signal ATARI_VL_d : std_logic_vector(31 downto 0); signal ATARI_VL_q : std_logic_vector(31 downto 0); - signal RAND_LINKS : std_logic_vector(11 downto 0); - signal HDIS_START : std_logic_vector(11 downto 0); - signal HDIS_END : std_logic_vector(11 downto 0); - signal RAND_RECHTS : std_logic_vector(11 downto 0); - signal HS_START : std_logic_vector(11 downto 0); - signal H_TOTAL : std_logic_vector(11 downto 0); - signal HDIS_LEN : std_logic_vector(11 downto 0); + signal rand_links : std_logic_vector(11 downto 0); + signal hdis_start : std_logic_vector(11 downto 0); + signal hdis_end : std_logic_vector(11 downto 0); + signal rand_rechts : std_logic_vector(11 downto 0); + signal hs_start : std_logic_vector(11 downto 0); + signal h_total : std_logic_vector(11 downto 0); + signal hdis_len : std_logic_vector(11 downto 0); signal MULF : std_logic_vector(5 downto 0); signal HHT : std_logic_vector(11 downto 0) := (others => '0'); signal HHT_d : std_logic_vector(11 downto 0); @@ -226,18 +226,18 @@ architecture rtl of video_mod_mux_clutctr is signal HDB_d : std_logic_vector(11 downto 0); signal HDB_q : std_logic_vector(11 downto 0); signal HDE : std_logic_vector(11 downto 0); - signal HDE_d : std_logic_vector(11 downto 0); - signal HDE_q : std_logic_vector(11 downto 0); + signal hde_d : std_logic_vector(11 downto 0); + signal hde_q : std_logic_vector(11 downto 0); signal HBB : std_logic_vector(11 downto 0); signal HBB_d : std_logic_vector(11 downto 0); signal HBB_q : std_logic_vector(11 downto 0); signal HSS : std_logic_vector(11 downto 0) := (others => '0'); signal HSS_d : std_logic_vector(11 downto 0); signal HSS_q : std_logic_vector(11 downto 0); - signal RAND_OBEN : std_logic_vector(10 downto 0); + signal rand_OBEN : std_logic_vector(10 downto 0); signal VDIS_START : std_logic_vector(10 downto 0); - signal VDIS_END : std_logic_vector(10 downto 0); - signal RAND_UNTEN : std_logic_vector(10 downto 0); + signal VDIS_end : std_logic_vector(10 downto 0); + signal rand_UNTEN : std_logic_vector(10 downto 0); signal VS_START : std_logic_vector(10 downto 0); signal V_TOTAL : std_logic_vector(10 downto 0); signal VBE : std_logic_vector(10 downto 0); @@ -264,7 +264,7 @@ architecture rtl of video_mod_mux_clutctr is signal VCO_q : std_logic_vector(8 downto 0); signal VCNTRL : std_logic_vector(3 downto 0) := (others => '0'); signal vcntrl_d : std_logic_vector(3 downto 0); - signal VCNTRL_q : std_logic_vector(3 downto 0); + signal vcntrl_q : std_logic_vector(3 downto 0); signal u0_data : std_logic_vector(15 downto 0); signal u0_tridata : std_logic_vector(15 downto 0); signal u1_data : std_logic_vector(15 downto 0); @@ -281,18 +281,18 @@ architecture rtl of video_mod_mux_clutctr is signal acp_vctr6_ena_ctrl : std_logic; signal acp_vctr0_ena_ctrl : std_logic; - signal ATARI_HH24_ena_ctrl : std_logic; - signal ATARI_HH16_ena_ctrl : std_logic; - signal ATARI_HH8_ena_ctrl : std_logic; - signal ATARI_HH0_ena_ctrl : std_logic; - signal ATARI_VH24_ena_ctrl : std_logic; - signal ATARI_VH16_ena_ctrl : std_logic; - signal ATARI_VH8_ena_ctrl : std_logic; - signal ATARI_VH0_ena_ctrl : std_logic; - signal ATARI_HL24_ena_ctrl : std_logic; - signal ATARI_HL16_ena_ctrl : std_logic; - signal ATARI_HL8_ena_ctrl : std_logic; - signal ATARI_HL0_ena_ctrl : std_logic; + signal atari_hh24_ena_ctrl : std_logic; + signal atari_hh16_ena_ctrl : std_logic; + signal atari_hh8_ena_ctrl : std_logic; + signal atari_hh0_ena_ctrl : std_logic; + signal atari_vh24_ena_ctrl : std_logic; + signal atari_vh16_ena_ctrl : std_logic; + signal atari_vh8_ena_ctrl : std_logic; + signal atari_vh0_ena_ctrl : std_logic; + signal atari_hl24_ena_ctrl : std_logic; + signal atari_hl16_ena_ctrl : std_logic; + signal atari_hl8_ena_ctrl : std_logic; + signal atari_hl0_ena_ctrl : std_logic; signal ATARI_VL0_clk_ctrl : std_logic; signal ATARI_VL24_ena_ctrl : std_logic; signal ATARI_VL16_ena_ctrl : std_logic; @@ -315,7 +315,7 @@ architecture rtl of video_mod_mux_clutctr is signal HDB8_ena_ctrl : std_logic; signal HDB0_ena_ctrl : std_logic; signal HDE8_ena_ctrl : std_logic; - signal HDE0_ena_ctrl : std_logic; + signal hde0_ena_ctrl : std_logic; signal HBB8_ena_ctrl : std_logic; signal HBB0_ena_ctrl : std_logic; signal HSS0_clk_ctrl : std_logic; @@ -326,7 +326,7 @@ architecture rtl of video_mod_mux_clutctr is signal VDB8_ena_ctrl : std_logic; signal VDB0_ena_ctrl : std_logic; signal VDE8_ena_ctrl : std_logic; - signal VDE0_ena_ctrl : std_logic; + signal vde0_ena_ctrl : std_logic; signal VBB8_ena_ctrl : std_logic; signal VBB0_ena_ctrl : std_logic; signal VSS8_ena_ctrl : std_logic; @@ -369,14 +369,14 @@ architecture rtl of video_mod_mux_clutctr is signal FALCON_VIDEO : std_logic; signal HSS_CS : std_logic; signal HBB_CS : std_logic; - signal HDE_CS : std_logic; + signal hde_CS : std_logic; signal HDB_CS : std_logic; signal HBE_CS : std_logic; signal HHT_CS : std_logic; signal ATARI_VL_CS : std_logic; - signal ATARI_HL_CS : std_logic; - signal ATARI_VH_CS : std_logic; - signal ATARI_HH_CS : std_logic; + signal atari_hl_CS : std_logic; + signal atari_vh_CS : std_logic; + signal atari_hh_CS : std_logic; signal ATARI_SYNC : std_logic; signal color24 : std_logic; signal color16 : std_logic; @@ -402,9 +402,9 @@ architecture rtl of video_mod_mux_clutctr is signal VCO_OFF_q : std_logic; signal VCO_OFF_d : std_logic; signal VCO_OFF : std_logic; - signal VCO_ON_q : std_logic; - signal VCO_ON_d : std_logic; - signal VCO_ON : std_logic; + signal vco_on_q : std_logic; + signal vco_on_d : std_logic; + signal vco_on : std_logic; signal VCO_ZL_q : std_logic; signal VCO_ZL_ena : std_logic; signal VCO_ZL_d : std_logic; @@ -415,15 +415,15 @@ architecture rtl of video_mod_mux_clutctr is signal DPO_OFF_q : std_logic; signal DPO_OFF_d : std_logic; signal DPO_OFF : std_logic; - signal DPO_ON_q : std_logic; - signal DPO_ON_d : std_logic; + signal dpo_on_q : std_logic; + signal dpo_on_d : std_logic; signal DPO_ON : std_logic; - signal DPO_ZL_q : std_logic; - signal DPO_ZL_ena : std_logic; - signal DPO_ZL_d : std_logic; + signal dpo_zl_q : std_logic; + signal dpo_zl_ena : std_logic; + signal dpo_zl_d : std_logic; signal DPO_ZL : std_logic; - signal DISP_ON_q : std_logic; - signal DISP_ON_d : std_logic; + signal disp_on_q : std_logic; + signal disp_on_d : std_logic; signal DISP_ON : std_logic; signal nBLANK_q : std_logic; signal nBLANK_d : std_logic; @@ -522,9 +522,9 @@ begin -- missing signals that seem to got lost during conversion hsync <= hsync_q; acp_vctr <= acp_vctr_q; - RAND <= RAND_q; - ATARI_HH <= ATARI_HH_q; - ATARI_HL <= ATARI_HL_q; + rand <= rand_q; + atari_hh <= atari_hh_q; + atari_hl <= atari_hl_q; HBE <= HBE_q; HSS <= HSS_q; VCO <= VCO_q; @@ -552,10 +552,10 @@ begin if border_color16_ena_ctrl = '1' then border_color_q(23 downto 16) <= border_color_d(23 downto 16); end if; - if border_color8_ena_ctrl = '1' THEN + if border_color8_ena_ctrl = '1' then border_color_q(15 downto 8) <= border_color_d(15 downto 8); - END IF; - IF border_color0_ena_ctrl = '1' THEN + end if; + if border_color0_ena_ctrl = '1' then border_color_q(7 downto 0) <= border_color_d(7 downto 0); END IF; ccsel_q <= ccsel_d; @@ -578,12 +578,12 @@ begin END IF; END PROCESS; - PROCESS (clk25m) - BEGIN - IF rising_edge(clk25m) THEN + process (clk25m) + begin + if rising_edge(clk25m) then CLK13M_q <= CLK13M_d; - END IF; - END PROCESS; + end if; + end process; vr_frq <= unsigned(vr_frq_q); @@ -596,164 +596,164 @@ begin CLK17M_q <= CLK17M_d; - IF vr_dout0_ena_ctrl = '1' THEN + if vr_dout0_ena_ctrl = '1' then vr_dout_q <= vr_dout_d; - END IF; + end if; - IF vr_frq0_ena_ctrl = '1' THEN + if vr_frq0_ena_ctrl = '1' then vr_frq_q <= vr_frq_d; - END IF; + end if; - IF st_shift_mode0_ena_ctrl = '1' THEN + if st_shift_mode0_ena_ctrl = '1' then st_shift_mode_q <= st_shift_mode_d; - END IF; + end if; - IF falcon_shift_mode8_ena_ctrl = '1' THEN + if falcon_shift_mode8_ena_ctrl = '1' then falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); - END IF; + end if; - IF falcon_shift_mode0_ena_ctrl = '1' THEN + if falcon_shift_mode0_ena_ctrl = '1' then falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); - END IF; - IF acp_vctr24_ena_ctrl = '1' THEN + end if; + if acp_vctr24_ena_ctrl = '1' then acp_vctr_q(31 downto 24) <= acp_vctr_d(31 downto 24); - END IF; + end if; - IF acp_vctr16_ena_ctrl = '1' THEN + if acp_vctr16_ena_ctrl = '1' then acp_vctr_q(23 downto 16) <= acp_vctr_d(23 downto 16); - END IF; + end if; - IF acp_vctr8_ena_ctrl = '1' THEN + if acp_vctr8_ena_ctrl = '1' then acp_vctr_q(15 downto 8) <= acp_vctr_d(15 downto 8); - END IF; + end if; - IF acp_vctr6_ena_ctrl = '1' THEN + if acp_vctr6_ena_ctrl = '1' then acp_vctr_q(7 downto 6) <= acp_vctr_d(7 downto 6); - END IF; + end if; - IF acp_vctr0_ena_ctrl = '1' THEN + if acp_vctr0_ena_ctrl = '1' then acp_vctr_q(5 downto 0) <= acp_vctr_d(5 downto 0); - END IF; + end if; - IF sys_ctr0_ena_ctrl='1' THEN + if sys_ctr0_ena_ctrl='1' then sys_ctr_q <= sys_ctr_d; - END IF; + end if; - IF lof8_ena_ctrl = '1' THEN + if lof8_ena_ctrl = '1' then lof_q(15 downto 8) <= lof_d(15 downto 8); - END IF; + end if; - IF lof0_ena_ctrl = '1' THEN + if lof0_ena_ctrl = '1' then lof_q(7 downto 0) <= lof_d(7 downto 0); - END IF; + end if; - IF lwd8_ena_ctrl = '1' THEN + if lwd8_ena_ctrl = '1' then lwd_q(15 downto 8) <= lwd_d(15 downto 8); - END IF; + end if; - IF lwd0_ena_ctrl = '1' THEN + if lwd0_ena_ctrl = '1' then lwd_q(7 downto 0) <= lwd_d(7 downto 0); - END IF; + end if; - IF HDB8_ena_ctrl = '1' THEN + if HDB8_ena_ctrl = '1' then HDB_q(11 downto 8) <= HDB_d(11 downto 8); - END IF; + end if; - IF HDB0_ena_ctrl = '1' THEN + if HDB0_ena_ctrl = '1' then HDB_q(7 downto 0) <= HDB_d(7 downto 0); - END IF; + end if; - IF HDE8_ena_ctrl = '1' THEN - HDE_q(11 downto 8) <= HDE_d(11 downto 8); - END IF; + if HDE8_ena_ctrl = '1' then + hde_q(11 downto 8) <= hde_d(11 downto 8); + end if; - IF HDE0_ena_ctrl = '1' THEN - HDE_q(7 downto 0) <= HDE_d(7 downto 0); - END IF; + if hde0_ena_ctrl = '1' then + hde_q(7 downto 0) <= hde_d(7 downto 0); + end if; - IF HBB8_ena_ctrl = '1' THEN + if HBB8_ena_ctrl = '1' then HBB_q(11 downto 8) <= HBB_d(11 downto 8); - END IF; + end if; - IF HBB0_ena_ctrl = '1' THEN + if HBB0_ena_ctrl = '1' then HBB_q(7 downto 0) <= HBB_d(7 downto 0); - END IF; + end if; - IF HSS8_ena_ctrl = '1' THEN + if HSS8_ena_ctrl = '1' then HSS_q(11 downto 8) <= HSS_d(11 downto 8); - END IF; + end if; - IF HSS0_ena_ctrl='1' THEN + if HSS0_ena_ctrl='1' then HSS_q(7 downto 0) <= HSS_d(7 downto 0); - END IF; + end if; - DOP_ZEI_q <= DOP_ZEI_d; + dop_zei_q <= dop_zei_d; - IF VBE8_ena_ctrl = '1' THEN + if VBE8_ena_ctrl = '1' then VBE_q(10 downto 8) <= VBE_d(10 downto 8); - END IF; + end if; - IF VBE0_ena_ctrl = '1' THEN + if VBE0_ena_ctrl = '1' then VBE_q(7 downto 0) <= VBE_d(7 downto 0); - END IF; + end if; - IF VDB8_ena_ctrl = '1' THEN + if VDB8_ena_ctrl = '1' then VDB_q(10 downto 8) <= VDB_d(10 downto 8); - END IF; + end if; - IF VDB0_ena_ctrl = '1' THEN + if VDB0_ena_ctrl = '1' then VDB_q(7 downto 0) <= VDB_d(7 downto 0); - END IF; + end if; - IF VDE8_ena_ctrl = '1' THEN + if VDE8_ena_ctrl = '1' then VDE_q(10 downto 8) <= VDE_d(10 downto 8); - END IF; + end if; - IF VDE0_ena_ctrl = '1' THEN + if vde0_ena_ctrl = '1' then VDE_q(7 downto 0) <= VDE_d(7 downto 0); - END IF; + end if; - IF VBB8_ena_ctrl = '1' THEN + if VBB8_ena_ctrl = '1' then VBB_q(10 downto 8) <= VBB_d(10 downto 8); - END IF; + end if; - IF VBB0_ena_ctrl = '1' THEN + if VBB0_ena_ctrl = '1' then VBB_q(7 downto 0) <= VBB_d(7 downto 0); - END IF; + end if; - IF VSS8_ena_ctrl = '1' THEN + if VSS8_ena_ctrl = '1' then VSS_q(10 downto 8) <= VSS_d(10 downto 8); - END IF; + end if; - IF VSS0_ena_ctrl = '1' THEN + if VSS0_ena_ctrl = '1' then VSS_q(7 downto 0) <= VSS_d(7 downto 0); - END IF; + end if; - IF VFT8_ena_ctrl = '1' THEN + if VFT8_ena_ctrl = '1' then VFT_q(10 downto 8) <= VFT_d(10 downto 8); - END IF; + end if; - IF VFT0_ena_ctrl = '1' THEN + if VFT0_ena_ctrl = '1' then VFT_q(7 downto 0) <= VFT_d(7 downto 0); - END IF; + end if; - IF VCO_ena(8) = '1' THEN + if VCO_ena(8) = '1' then VCO_q(8) <= VCO_d(8); - END IF; + end if; - IF VCO0_ena_ctrl = '1' THEN + if VCO0_ena_ctrl = '1' then VCO_q(7 downto 0) <= VCO_d(7 downto 0); - END IF; + end if; - IF VCNTRL0_ena_ctrl = '1' THEN - VCNTRL_q <= vcntrl_d; - END IF; - END IF; - END PROCESS; + if vcntrl0_ena_ctrl = '1' then + vcntrl_q <= vcntrl_d; + end if; + end if; + end process; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then clut_mux_av1_q <= clut_mux_av1_d; clut_mux_av0_q <= clut_mux_av0_d; CLUT_TA_q <= CLUT_TA_d; @@ -770,126 +770,126 @@ begin vsync_I_q <= vsync_I_d; END IF; - DISP_ON_q <= DISP_ON_d; + disp_on_q <= disp_on_d; - IF DPO_ZL_ena = '1' THEN - DPO_ZL_q <= DPO_ZL_d; - END IF; + if dpo_zl_ena = '1' then + dpo_zl_q <= dpo_zl_d; + end if; - DPO_ON_q <= DPO_ON_d; + dpo_on_q <= dpo_on_d; DPO_OFF_q <= DPO_OFF_d; VDTRON_q <= VDTRON_d; - IF VCO_ZL_ena = '1' THEN + if VCO_ZL_ena = '1' then VCO_ZL_q <= VCO_ZL_d; - END IF; + end if; - VCO_ON_q <= VCO_ON_d; + vco_on_q <= vco_on_d; VCO_OFF_q <= VCO_OFF_d; - VHCNT_q <= VHCNT_d; + vhcnt_q <= vhcnt_d; - IF SUB_PIXEL_CNT0_ena_ctrl = '1' THEN - SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d; - END IF; + if sub_pixel_cnt0_ena_ctrl = '1' then + sub_pixel_cnt_q <= sub_pixel_cnt_d; + end if; - IF VVCNT0_ena_ctrl='1' THEN - VVCNT_q <= VVCNT_d; - END IF; + if vvcnt0_ena_ctrl='1' then + vvcnt_q <= vvcnt_d; + end if; - VERZ2_q <= VERZ2_d; - VERZ1_q <= VERZ1_d; + verz2_q <= verz2_d; + verz1_q <= verz1_d; VERZ0_q <= VERZ0_d; - RAND_q <= RAND_d; + rand_q <= rand_d; - IF START_ZEILE_ena = '1' THEN + if START_ZEILE_ena = '1' then START_ZEILE_q <= START_ZEILE_d; - END IF; + end if; SYNC_PIX_q <= SYNC_PIX_d; SYNC_PIX1_q <= SYNC_PIX1_d; SYNC_PIX2_q <= SYNC_PIX2_d; - IF ATARI_HH24_ena_ctrl = '1' THEN - ATARI_HH_q(31 downto 24) <= ATARI_HH_d(31 downto 24); - END IF; + if atari_hh24_ena_ctrl = '1' then + atari_hh_q(31 downto 24) <= atari_hh_d(31 downto 24); + end if; - IF ATARI_HH16_ena_ctrl = '1' THEN - ATARI_HH_q(23 downto 16) <= ATARI_HH_d(23 downto 16); - END IF; + if atari_hh16_ena_ctrl = '1' then + atari_hh_q(23 downto 16) <= atari_hh_d(23 downto 16); + end if; - IF ATARI_HH8_ena_ctrl = '1' THEN - ATARI_HH_q(15 downto 8) <= ATARI_HH_d(15 downto 8); - END IF; + if atari_hh8_ena_ctrl = '1' then + atari_hh_q(15 downto 8) <= atari_hh_d(15 downto 8); + end if; - IF ATARI_HH0_ena_ctrl = '1' THEN - ATARI_HH_q(7 downto 0) <= ATARI_HH_d(7 downto 0); - END IF; + if atari_hh0_ena_ctrl = '1' then + atari_hh_q(7 downto 0) <= atari_hh_d(7 downto 0); + end if; - IF ATARI_VH24_ena_ctrl = '1' THEN - ATARI_VH_q(31 downto 24) <= ATARI_VH_d(31 downto 24); - END IF; + if atari_vh24_ena_ctrl = '1' then + atari_vh_q(31 downto 24) <= atari_vh_d(31 downto 24); + end if; - IF ATARI_VH16_ena_ctrl = '1' THEN - ATARI_VH_q(23 downto 16) <= ATARI_VH_d(23 downto 16); - END IF; + if atari_vh16_ena_ctrl = '1' then + atari_vh_q(23 downto 16) <= atari_vh_d(23 downto 16); + end if; - IF ATARI_VH8_ena_ctrl = '1' THEN - ATARI_VH_q(15 downto 8) <= ATARI_VH_d(15 downto 8); - END IF; + if atari_vh8_ena_ctrl = '1' then + atari_vh_q(15 downto 8) <= atari_vh_d(15 downto 8); + end if; - IF ATARI_VH0_ena_ctrl='1' THEN - ATARI_VH_q(7 downto 0) <= ATARI_VH_d(7 downto 0); - END IF; + if atari_vh0_ena_ctrl='1' then + atari_vh_q(7 downto 0) <= atari_vh_d(7 downto 0); + end if; - IF ATARI_HL24_ena_ctrl = '1' THEN - ATARI_HL_q(31 downto 24) <= ATARI_HL_d(31 downto 24); - END IF; + if atari_hl24_ena_ctrl = '1' then + atari_hl_q(31 downto 24) <= atari_hl_d(31 downto 24); + end if; - IF ATARI_HL16_ena_ctrl = '1' THEN - ATARI_HL_q(23 downto 16) <= ATARI_HL_d(23 downto 16); - END IF; + if atari_hl16_ena_ctrl = '1' then + atari_hl_q(23 downto 16) <= atari_hl_d(23 downto 16); + end if; - IF ATARI_HL8_ena_ctrl = '1' THEN - ATARI_HL_q(15 downto 8) <= ATARI_HL_d(15 downto 8); - END IF; + if atari_hl8_ena_ctrl = '1' then + atari_hl_q(15 downto 8) <= atari_hl_d(15 downto 8); + end if; - IF ATARI_HL0_ena_ctrl = '1' THEN - ATARI_HL_q(7 downto 0) <= ATARI_HL_d(7 downto 0); - END IF; + if atari_hl0_ena_ctrl = '1' then + atari_hl_q(7 downto 0) <= atari_hl_d(7 downto 0); + end if; - IF ATARI_VL24_ena_ctrl = '1' THEN + if ATARI_VL24_ena_ctrl = '1' then ATARI_VL_q(31 downto 24) <= ATARI_VL_d(31 downto 24); - END IF; + end if; - IF ATARI_VL16_ena_ctrl = '1' THEN + if ATARI_VL16_ena_ctrl = '1' then ATARI_VL_q(23 downto 16) <= ATARI_VL_d(23 downto 16); - END IF; + end if; - IF ATARI_VL8_ena_ctrl = '1' THEN + if ATARI_VL8_ena_ctrl = '1' then ATARI_VL_q(15 downto 8) <= ATARI_VL_d(15 downto 8); - END IF; + end if; - IF ATARI_VL0_ena_ctrl = '1' THEN + if ATARI_VL0_ena_ctrl = '1' then ATARI_VL_q(7 downto 0) <= ATARI_VL_d(7 downto 0); - END IF; + end if; - IF HHT8_ena_ctrl = '1' THEN + if HHT8_ena_ctrl = '1' then HHT_q(11 downto 8) <= HHT_d(11 downto 8); - END IF; + end if; - IF HHT0_ena_ctrl = '1' THEN + if HHT0_ena_ctrl = '1' then HHT_q(7 downto 0) <= HHT_d(7 downto 0); - END IF; + end if; - IF HBE8_ena_ctrl = '1' THEN + if HBE8_ena_ctrl = '1' then HBE_q(11 downto 8) <= HBE_d(11 downto 8); - END IF; + end if; - IF HBE0_ena_ctrl = '1' THEN + if HBE0_ena_ctrl = '1' then HBE_q(7 downto 0) <= HBE_d(7 downto 0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; -- Start of original equations @@ -952,7 +952,7 @@ begin st_clut_rd <= ST_CLUT_CS and (not nFB_OE); st_clut_wr <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - -- ST SHIFT MODE + -- ST SHifT MODE -- $F8260/2 st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adR(19 downto 1) = 19x"7c130" else '0'; @@ -969,7 +969,7 @@ begin -- 16 FARBEN COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); - -- FALCON SHIFT MODE + -- FALCON SHifT MODE -- $F8266/2 falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110011"); @@ -990,8 +990,8 @@ begin -- BIT 3 = ACP 16BIT -- BIT 4 = ACP 8BIT -- BIT 5 = ACP 1BIT - -- BIT 6 = FALCON SHIFT MODE - -- BIT 7 = ST SHIFT MODE + -- BIT 6 = FALCON SHifT MODE + -- BIT 7 = ST SHifT MODE -- BIT 9..8 = VCLK FREQUENZ -- BIT 15 =-SYNC ALLOWED -- BIT 31..16 = video_ram_ctr @@ -1004,10 +1004,10 @@ begin acp_vctr_d(31 downto 8) <= fb_ad(31 downto 8); acp_vctr_d(5 downto 0) <= fb_ad(5 downto 0); - acp_vctr24_ena_ctrl <= acp_vctr_CS and FB_B(0) and (not nFB_WR); - acp_vctr16_ena_ctrl <= acp_vctr_CS and FB_B(1) and (not nFB_WR); - acp_vctr8_ena_ctrl <= acp_vctr_CS and FB_B(2) and (not nFB_WR); - acp_vctr0_ena_ctrl <= acp_vctr_CS and FB_B(3) and (not nFB_WR); + acp_vctr24_ena_ctrl <= acp_vctr_CS and fb_b(0) and (not nFB_WR); + acp_vctr16_ena_ctrl <= acp_vctr_CS and fb_b(1) and (not nFB_WR); + acp_vctr8_ena_ctrl <= acp_vctr_CS and fb_b(2) and (not nFB_WR); + acp_vctr0_ena_ctrl <= acp_vctr_CS and fb_b(3) and (not nFB_WR); ACP_VIDEO_ON <= acp_vctr_q(0); nPD_VGA <= acp_vctr_q(1); @@ -1080,7 +1080,7 @@ begin color24 <= acp_vctr_q(2) and ACP_VIDEO_ON; ACP_CLUT <= (ACP_VIDEO_ON and (color1 or color8)) or (ST_VIDEO and color1); - -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + -- ST ODER FALCON SHifT MODE SETZEN WENN WRITE X..SHifT REGISTER acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); @@ -1098,7 +1098,7 @@ begin sizeIt(RAND_ON,3)); -- DIVERSE (VIDEO)-REGISTER ---------------------------- - -- RANDFARBE + -- randFARBE -- $404/4 border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 2) = "00000000000000000100000001"); @@ -1261,7 +1261,7 @@ begin -- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or -- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or -- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or --- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or +-- (sizeIt(hde_CS,16) and std_logic_vector'("0000" & hde_q)) or -- (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or -- (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or -- (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or @@ -1272,11 +1272,11 @@ begin -- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or --- (sizeIt(vcntrl_cs,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or +-- (sizeIt(vcntrl_cs,16) and std_logic_vector'("000000000000" & vcntrl_q)) or -- (sizeIt(acp_vctr_CS,16) and acp_vctr_q(31 downto 16)) or --- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or --- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or --- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or +-- (sizeIt(atari_hh_CS,16) and atari_hh_q(31 downto 16)) or +-- (sizeIt(atari_vh_CS,16) and atari_vh_q(31 downto 16)) or +-- (sizeIt(atari_hl_CS,16) and atari_hl_q(31 downto 16)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or -- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or -- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or @@ -1310,15 +1310,15 @@ begin (others => 'Z'); -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or --- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or +-- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); -- fb_ad(31 downto 16) <= u0_tridata; -- high word register access -- u1_data <= (sizeIt(acp_vctr_CS,16) and acp_vctr_q(15 downto 0)) or --- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or --- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or --- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or +-- (sizeIt(atari_hh_CS,16) and atari_hh_q(15 downto 0)) or +-- (sizeIt(atari_vh_CS,16) and atari_vh_q(15 downto 0)) or +-- (sizeIt(atari_hl_CS,16) and atari_hl_q(15 downto 0)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or -- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); -- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); @@ -1333,7 +1333,7 @@ begin (others => 'Z'); video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or - HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or + hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs; -- VIDEO AUSGABE SETZEN @@ -1362,7 +1362,7 @@ begin -- 640 pixels, 25.175 MHz, VGA -- hsync pulse length in pixeln = frequenz / = 500ns - HSY_LEN_d <= std_logic_vector'(8d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else + hsy_len_d <= std_logic_vector'(8d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else std_logic_vector'(8d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else std_logic_vector'(8d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else std_logic_vector'(8d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else @@ -1371,27 +1371,27 @@ begin std_logic_vector(8d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else (others => '0'); - -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or - -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or - -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not VCNTRL_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or + -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or + -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or - -- ((std_logic_vector(to_unsigned(16, HSY_LEN_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(acp_vctr_q(9), 8)); + -- ((std_logic_vector(to_unsigned(16, hsy_len_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(acp_vctr_q(9), 8)); -- MULTIPLIKATIONS FAKTOR - MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or - ("000100" and sizeIt(not ST_VIDEO,6) and sizeIt(not VCNTRL_q(2),6)) or - ("010000" and sizeIt(ST_VIDEO,6) and sizeIt(VCNTRL_q(2),6)) or - ("100000" and sizeIt(ST_VIDEO,6) and sizeIt(not VCNTRL_q(2),6)); + MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(vcntrl_q(2),6)) or + ("000100" and sizeIt(not ST_VIDEO,6) and sizeIt(not vcntrl_q(2),6)) or + ("010000" and sizeIt(ST_VIDEO,6) and sizeIt(vcntrl_q(2),6)) or + ("100000" and sizeIt(ST_VIDEO,6) and sizeIt(not vcntrl_q(2),6)); -- BREITE IN PIXELN - HDIS_LEN <= ("000101000000" and sizeIt(VCNTRL_q(2),12)) or ("001010000000" - and sizeIt(not VCNTRL_q(2),12)); + hdis_len <= ("000101000000" and sizeIt(vcntrl_q(2),12)) or ("001010000000" + and sizeIt(not vcntrl_q(2),12)); -- DOPPELZEILENMODUS -- ZEILENVERDOPPELUNG EIN AUS - DOP_ZEI_d <= VCNTRL_q(0) and (FALCON_VIDEO or ST_VIDEO); + dop_zei_d <= vcntrl_q(0) and (FALCON_VIDEO or ST_VIDEO); -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC @@ -1403,7 +1403,7 @@ begin -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START dop_fifo_clr_d <= (inter_zei_q and hsync_START_q) or SYNC_PIX_q; --- RAND_LINKS[] = HBE[] & ACP_VIDEO_ON +-- rand_links[] = HBE[] & ACP_VIDEO_ON -- # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- @@ -1418,13 +1418,13 @@ begin (std_logic_vector(to_unsigned(42, 12)) and sizeit(not acp_video_on and atari_sync and not vcntrl(2), 12)) or (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 downto 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ --- HDIS_START[] = HDB[] & ACP_VIDEO_ON --- # RAND_LINKS[] + 1 & !ACP_VIDEO_ON; -- - HDIS_START <= (HDB_q and sizeIt(ACP_VIDEO_ON, 12)) or ((std_logic_vector(unsigned(RAND_LINKS) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); - HDIS_END <= (HDE_q and sizeIt(ACP_VIDEO_ON, 12)) or - ((std_logic_vector(unsigned(RAND_LINKS) + unsigned(HDIS_LEN))) and sizeIt(not ACP_VIDEO_ON,12)); - RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or - ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); +-- hdis_start[] = HDB[] & ACP_VIDEO_ON +-- # rand_links[] + 1 & !ACP_VIDEO_ON; -- + hdis_start <= (HDB_q and sizeIt(ACP_VIDEO_ON, 12)) or ((std_logic_vector(unsigned(rand_links) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); + hdis_end <= (hde_q and sizeIt(ACP_VIDEO_ON, 12)) or + ((std_logic_vector(unsigned(rand_links) + unsigned(hdis_len))) and sizeIt(not ACP_VIDEO_ON,12)); + rand_rechts <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or + ((std_logic_vector(unsigned(hdis_end) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); hs_start <= hss_q when acp_video_on else atari_hl(11 downto 0) when not(acp_video_on) and atari_sync and vcntrl(2) else @@ -1432,9 +1432,9 @@ begin std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else (others => '0'); --- HS_START[] = HSS[] & ACP_VIDEO_ON --- # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 --- # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 +-- hs_start[] = HSS[] & ACP_VIDEO_ON +-- # atari_hl[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 +-- # atari_hh[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- -- h_total <= hht_q when acp_video_on else @@ -1443,11 +1443,11 @@ begin std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync else (others => '0'); --- H_TOTAL[] = HHT[] & ACP_VIDEO_ON --- # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 --- # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 +-- h_total[] = HHT[] & ACP_VIDEO_ON +-- # atari_hl[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 +-- # atari_hh[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and + rand_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); @@ -1457,63 +1457,63 @@ begin ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or + VDIS_end <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or - ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or + rand_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or + ((std_logic_vector(unsigned(VDIS_end) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 downto 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 downto 0) and sizeIt(not + sizeIt(vcntrl_q(2),11)) or (atari_vh_q(10 downto 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and + vcntrl_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 downto 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 downto 16) and sizeIt(not + sizeIt(vcntrl_q(2),11)) or (atari_vh_q(26 downto 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and + vcntrl_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); -- ZÄHLER - LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); + last_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(h_total) - 2))); - VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); + vhcnt_d <= (std_logic_vector(unsigned(vhcnt_q) + 1)) and sizeIt(not last_q,12); - VVCNT0_ena_ctrl <= LAST_q; - VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); + vvcnt0_ena_ctrl <= last_q; + vvcnt_d <= (std_logic_vector(unsigned(vvcnt_q) + 1)) and sizeIt(to_std_logic(vvcnt_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); -- DISPLAY ON OFF -- 1 ZEILE DAVOR ON OFF - DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); + dpo_zl_d <= to_std_logic((unsigned(vvcnt_q) > unsigned(std_logic_vector(unsigned(rand_OBEN) - 1))) and (unsigned(vvcnt_q) < unsigned(std_logic_vector(unsigned(rand_UNTEN) - 1)))); - -- AM ZEILENENDE ÃœBERNEHMEN - DPO_ZL_ena <= LAST_q; + -- AM ZEILENendE ÃœBERNEHMEN + dpo_zl_ena <= last_q; -- BESSER EINZELN WEGEN TIMING - DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); - DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); - DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); + dpo_on_d <= to_std_logic(vhcnt_q = rand_links); + DPO_OFF_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(rand_rechts) - 1))); + disp_on_d <= (disp_on_q and (not DPO_OFF_q)) or (dpo_on_q and dpo_zl_q); -- DATENTRANSFER ON OFF -- BESSER EINZELN WEGEN TIMING - VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); - VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); + vco_on_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(hdis_start) - 1))); + VCO_OFF_d <= to_std_logic(vhcnt_q = hdis_end); - -- AM ZEILENENDE ÃœBERNEHMEN - VCO_ZL_ena <= LAST_q; + -- AM ZEILENendE ÃœBERNEHMEN + VCO_ZL_ena <= last_q; -- 1 ZEILE DAVOR ON OFF - VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); + VCO_ZL_d <= to_std_logic((unsigned(vvcnt_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(vvcnt_q) < unsigned(VDIS_end))); - VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); + VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (vco_on_q and VCO_ZL_q); -- VERZÖGERUNG UND SYNC @@ -1541,16 +1541,16 @@ begin -- vsync_I_d <= ("011" and sizeIt(vsync_START_q,3)) or -- ((std_logic_vector(unsigned(vsync_I_q) - 1)) and sizeIt(not vsync_START_q,3) and sizeIt(to_std_logic(vsync_I_q /= "000"),3)); - (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); - (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); - (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & VERZ1_q(2) & VERZ0_q(2)); - (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & VERZ1_q(3) & VERZ0_q(3)); - (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & VERZ1_q(4) & VERZ0_q(4)); - (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & VERZ1_q(5) & VERZ0_q(5)); - (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & VERZ1_q(6) & VERZ0_q(6)); - (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & VERZ1_q(7) & VERZ0_q(7)); - (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & VERZ1_q(8) & VERZ0_q(8)); - VERZ0_d(0) <= DISP_ON_q; + (verz2_d(1), verz1_d(1), VERZ0_d(1)) <= std_logic_vector'(verz2_q(0) & verz1_q(0) & VERZ0_q(0)); + (verz2_d(2), verz1_d(2), VERZ0_d(2)) <= std_logic_vector'(verz2_q(1) & verz1_q(1) & VERZ0_q(1)); + (verz2_d(3), verz1_d(3), VERZ0_d(3)) <= std_logic_vector'(verz2_q(2) & verz1_q(2) & VERZ0_q(2)); + (verz2_d(4), verz1_d(4), VERZ0_d(4)) <= std_logic_vector'(verz2_q(3) & verz1_q(3) & VERZ0_q(3)); + (verz2_d(5), verz1_d(5), VERZ0_d(5)) <= std_logic_vector'(verz2_q(4) & verz1_q(4) & VERZ0_q(4)); + (verz2_d(6), verz1_d(6), VERZ0_d(6)) <= std_logic_vector'(verz2_q(5) & verz1_q(5) & VERZ0_q(5)); + (verz2_d(7), verz1_d(7), VERZ0_d(7)) <= std_logic_vector'(verz2_q(6) & verz1_q(6) & VERZ0_q(6)); + (verz2_d(8), verz1_d(8), VERZ0_d(8)) <= std_logic_vector'(verz2_q(7) & verz1_q(7) & VERZ0_q(7)); + (verz2_d(9), verz1_d(9), VERZ0_d(9)) <= std_logic_vector'(verz2_q(8) & verz1_q(8) & VERZ0_q(8)); + VERZ0_d(0) <= disp_on_q; -- VERZ[1][0] = hsync_I[] != 0; -- NUR MÖGLICH WENN BEIDE @@ -1566,7 +1566,7 @@ begin -- nBLANK = VERZ[0][8]; nblank_d <= verz0_q(8); - -- nBLANK_d <= DISP_ON_q; + -- nBLANK_d <= disp_on_q; -- hsync = VERZ[1][9]; -- NUR MÖGLICH WENN BEIDE @@ -1581,18 +1581,18 @@ begin VCO_q(5))='1' and vsync_I_q = "000")); nSYNC <= gnd; - -- RANDFARBE MACHEN ------------------------------------ - RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); - RAND_d(1) <= RAND_q(0); - RAND_d(2) <= RAND_q(1); - RAND_d(3) <= RAND_q(2); - RAND_d(4) <= RAND_q(3); - RAND_d(5) <= RAND_q(4); - RAND_d(6) <= RAND_q(5); + -- randFARBE MACHEN ------------------------------------ + rand_d(0) <= disp_on_q and (not VDTRON_q) and acp_vctr_q(25); + rand_d(1) <= rand_q(0); + rand_d(2) <= rand_q(1); + rand_d(3) <= rand_q(2); + rand_d(4) <= rand_q(3); + rand_d(5) <= rand_q(4); + rand_d(6) <= rand_q(5); - -- RAND_ON = RAND[6]; + -- rand_ON = rand[6]; rand_on <= rand(6); - -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and acp_vctr_q(25); + -- rand_ON <= disp_on_q and (not VDTRON_q) and acp_vctr_q(25); -- -------------------------------------------------------- clr_fifo_ena <= LAST_q; @@ -1602,21 +1602,21 @@ begin START_ZEILE_ena <= LAST_q; -- ZEILE 1 - START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); + START_ZEILE_d <= to_std_logic(vvcnt_q = "00000000000"); -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; + SYNC_PIX_d <= to_std_logic(vhcnt_q = "000000000011") and START_ZEILE_q; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; + SYNC_PIX1_d <= to_std_logic(vhcnt_q = "000000000101") and START_ZEILE_q; -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; + SYNC_PIX2_d <= to_std_logic(vhcnt_q = "000000000111") and START_ZEILE_q; - SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; + sub_pixel_cnt0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; -- count up if display on sonst clear bei sync pix - SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); + sub_pixel_cnt_d <= (std_logic_vector(unsigned(sub_pixel_cnt_q) + 1)) and sizeIt(not SYNC_PIX_q,7); -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION fifo_rde_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and color1) or @@ -1627,7 +1627,7 @@ begin (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and color24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - clut_mux_av0_d <= SUB_PIXEL_CNT_q(3 downto 0); + clut_mux_av0_d <= sub_pixel_cnt_q(3 downto 0); clut_mux_av1_d <= clut_mux_av0_q; clut_mux_adr_d <= clut_mux_av1_q; @@ -1642,4 +1642,4 @@ begin -- Define power signal(s) gnd <= '0'; -END ARCHITECTURE rtl; +end ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/firebee_utils_pkg.vhd b/FPGA_Quartus_13.1/firebee_utils_pkg.vhd new file mode 100644 index 0000000..5f31318 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee_utils_pkg.vhd @@ -0,0 +1,171 @@ +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This package contains utility functions, procedures and constants +---- for the Firebee project. +---- +---- Author(s): ---- +---- - Markus Fröschle, mfro@mubf.de +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2015 Markus Fröschle +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- + +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + +PACKAGE firebee_utils_pkg IS + FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; + FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; + FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; + FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic; + + COMPONENT synchronizer IS + PORT + ( + -- Input ports + source_signal : IN std_logic; + + target_clock : IN std_logic; + target_signal : OUT std_logic + ); + END COMPONENT synchronizer; + +END firebee_utils_pkg; + +PACKAGE BODY firebee_utils_pkg IS + + FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS + VARIABLE ret : std_logic := '1'; + VARIABLE c_low : integer; + VARIABLE c_hi : integer; + BEGIN + c_hi := addr_const'HIGH; + c_low := addr_const'LOW; + + -- synthesis translate_off + REPORT("addr_const'HIGH = " & integer'IMAGE(c_hi) & " addr_const'LOW = " & integer'IMAGE(c_low)) SEVERITY WARNING; + REPORT("addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING; + -- synthesis translate_on + + FOR i IN c_hi DOWNTO c_low + 2 LOOP + IF addr(i) /= addr_const(c_hi - i) THEN + + -- synthesis translate_off + REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & + " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; + REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & + " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); + -- synthesis translate_on + + ret := '0'; + EXIT; + END IF; + END LOOP; + RETURN ret; + END FUNCTION f_addr_cmp_l; + + FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS + VARIABLE ret : std_logic := '1'; + VARIABLE c_hi : integer; + VARIABLE c_low : integer; + BEGIN + REPORT("f_addr_cmp_w(): addr_const'HIGH = " & integer'IMAGE(addr_const'HIGH) & " addr_const'LOW = " & integer'IMAGE(addr_const'LOW)) SEVERITY WARNING; + REPORT("f_addr_cmp_w(): addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING; + + c_hi := addr_const'HIGH; + c_low := addr_const'LOW; + FOR i IN c_hi DOWNTO c_low + 1 LOOP + IF addr(i) /= addr_const(c_hi - i) THEN + + -- synthesis translate_off + REPORT("f_addr_cmp_w(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & + " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; + REPORT("f_addr_cmp_w(): addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & + " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); + -- synthesis translate_on + + ret := '0'; + EXIT; + END IF; + END LOOP; + RETURN ret; + END FUNCTION f_addr_cmp_w; + + -- this is just for completeness + FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS + VARIABLE ret : std_logic := '1'; + VARIABLE c_hi : integer; + VARIABLE c_low : integer; + BEGIN + c_hi := addr_const'HIGH; + c_low := addr_const'LOW; + + FOR i IN c_hi DOWNTO c_low LOOP + IF addr(i) /= addr_const(c_hi - i) THEN + + -- synthesis translate_off + REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & + " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; + REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & + " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); + -- synthesis translate_on + + ret := '0'; + EXIT; + END IF; + END LOOP; + RETURN ret; + END FUNCTION f_addr_cmp_b; + + -- this is for arbitrary sized address compares. It compares from the highest bit of addr_const to the lowest - num_ignore + -- bit, thus allowing any size of comparision. + FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic IS + VARIABLE ret : std_logic := '1'; + VARIABLE c_hi : integer; + VARIABLE c_low : integer; + BEGIN + c_hi := addr_const'HIGH; + c_low := addr_const'LOW; + + FOR i IN addr_const'HIGH DOWNTO addr_const'LOW + num_ignore LOOP + IF addr(i) /= addr_const(c_hi - i) THEN + + -- synthesis translate_off + REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & + " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; + REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & + " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); + -- synthesis translate_on + + ret := '0'; + EXIT; + END IF; + END LOOP; + RETURN ret; + END FUNCTION f_addr_cmp_mask; +END PACKAGE BODY firebee_utils_pkg; \ No newline at end of file From 8199db400a9a7e2086cfda0a46b4807890c69f41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 05:33:31 +0000 Subject: [PATCH 101/127] removed (most) stuck buffers --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 2 +- .../Video/video_mod_mux_clutctr.vhd | 106 +++++++++--------- 2 files changed, 54 insertions(+), 54 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index c657dd1..1a665ed 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -1391,7 +1391,7 @@ begin (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - FB_AD(23 downto 16) <= u0_tridata; + -- FB_AD(23 downto 16) <= u0_tridata when u0_enabledt; -- Assignments added to explicitly combine the diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 293be1a..50f65f0 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -957,7 +957,7 @@ begin -- $F8260/2 st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adR(19 downto 1) = 19x"7c130" else '0'; -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110000"); - st_shift_mode_d <= fb_ad(25 downto 24); + st_shift_mode_d <= fb_ad(25 downto 24) when st_shift_mode_cs; st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0); -- MONO @@ -973,7 +973,7 @@ begin -- $F8266/2 falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110011"); - falcon_shift_mode_d <= fb_ad(26 downto 16); + falcon_shift_mode_d <= fb_ad(26 downto 16) when falcon_shift_mode_cs; falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2); falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3); @@ -1001,8 +1001,8 @@ begin -- $400/4 acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000000"); - acp_vctr_d(31 downto 8) <= fb_ad(31 downto 8); - acp_vctr_d(5 downto 0) <= fb_ad(5 downto 0); + acp_vctr_d(31 downto 8) <= fb_ad(31 downto 8) when acp_vctr_cs; + acp_vctr_d(5 downto 0) <= fb_ad(5 downto 0) when acp_vctr_cs; acp_vctr24_ena_ctrl <= acp_vctr_CS and fb_b(0) and (not nFB_WR); acp_vctr16_ena_ctrl <= acp_vctr_CS and fb_b(1) and (not nFB_WR); @@ -1019,7 +1019,7 @@ begin -- $410/4 ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000100"); - ATARI_HH_d <= fb_ad; + ATARI_HH_d <= fb_ad when atari_hh_cs; ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); @@ -1029,7 +1029,7 @@ begin -- $414/4 ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000101"); - ATARI_VH_d <= fb_ad; + ATARI_VH_d <= fb_ad when atari_vh_cs; ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); @@ -1039,7 +1039,7 @@ begin -- $418/4 ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000110"); - ATARI_HL_d <= fb_ad; + ATARI_HL_d <= fb_ad when atari_hl_cs; ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); @@ -1049,7 +1049,7 @@ begin -- $41C/4 ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000111"); - ATARI_VL_d <= fb_ad; + ATARI_VL_d <= fb_ad when atari_vl_cs; ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); @@ -1063,7 +1063,7 @@ begin vr_dout0_ena_ctrl <= not vr_busy; vr_dout_d <= vr_d; vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adR(8 downto 0) = "000000100"); - vr_frq_d <= fb_ad(23 downto 16); + vr_frq_d <= fb_ad(23 downto 16) when video_pll_config_cs; -- VIDEO PLL RECONFIG -- $(F)000'0800 @@ -1102,7 +1102,7 @@ begin -- $404/4 border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 2) = "00000000000000000100000001"); - border_color_d <= fb_ad(23 downto 0); + border_color_d <= fb_ad(23 downto 0) when border_color_cs; border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR); border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR); border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR); @@ -1134,14 +1134,14 @@ begin -- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011"); - sys_ctr_d <= fb_ad(22 downto 16); + sys_ctr_d <= fb_ad(22 downto 16) when sys_ctr_cs; sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3); blitter_on <= not sys_ctr_q(3); -- lof -- $820E/2 lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100000111"); - lof_d <= fb_ad(31 downto 16); + lof_d <= fb_ad(31 downto 16) when lof_cs; lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2); lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3); lof <= lof_q; @@ -1149,7 +1149,7 @@ begin -- lwd -- $8210/2 lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100001000"); - lwd_d <= fb_ad(31 downto 16); + lwd_d <= fb_ad(31 downto 16) when lwd_cs; lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0); lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1); @@ -1157,42 +1157,42 @@ begin -- HHT -- $8282/2 HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000001"); - HHT_d <= fb_ad(27 downto 16); + HHT_d <= fb_ad(27 downto 16) when hht_cs; HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); -- HBE -- $8286/2 HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000011"); - HBE_d <= fb_ad(27 downto 16); + HBE_d <= fb_ad(27 downto 16) when hbe_cs; HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); -- HDB -- $8288/2 HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000100"); - HDB_d <= fb_ad(27 downto 16); + HDB_d <= fb_ad(27 downto 16) when hdb_cs; HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); -- HDE -- $828A/2 HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000101"); - HDE_d <= fb_ad(27 downto 16); + HDE_d <= fb_ad(27 downto 16) when hde_cs; HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); -- HBB -- $8284/2 HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000010"); - HBB_d <= fb_ad(27 downto 16); + HBB_d <= fb_ad(27 downto 16) when hbb_cs; HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); -- HSS -- Videl hsync start register $828C / 2 HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000110"); - HSS_d <= fb_ad(27 downto 16); + HSS_d <= fb_ad(27 downto 16) when hss_cs; HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); @@ -1200,35 +1200,35 @@ begin -- VBE -- $82A6/2 VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010011"); - VBE_d <= fb_ad(26 downto 16); + VBE_d <= fb_ad(26 downto 16) when vbe_cs; VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); -- VDB -- $82A8/2 VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010100"); - VDB_d <= fb_ad(26 downto 16); + VDB_d <= fb_ad(26 downto 16) when vdb_cs; VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); -- VDE -- $82AA/2 VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010101"); - VDE_d <= fb_ad(26 downto 16); + VDE_d <= fb_ad(26 downto 16) when vde_cs; VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); -- VBB -- $82A4/2 VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010010"); - VBB_d <= fb_ad(26 downto 16); + VBB_d <= fb_ad(26 downto 16) when vbb_cs; VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); -- VSS -- $82AC/2 VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010110"); - VSS_d <= fb_ad(26 downto 16); + VSS_d <= fb_ad(26 downto 16) when vss_cs; VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); @@ -1236,21 +1236,21 @@ begin -- $82A2/2 -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010001"); vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); - VFT_d <= fb_ad(26 downto 16); + VFT_d <= fb_ad(26 downto 16) when vft_cs; VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); -- VCO -- $82C0 / 2 Falcon clock control register VCO VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101100000"); - VCO_d <= fb_ad(24 downto 16); + VCO_d <= fb_ad(24 downto 16) when vco_cs; VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; - vcntrl_d <= fb_ad(19 downto 16); + vcntrl_d <= fb_ad(19 downto 16) when vcntrl_cs; VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and FB_B(3); -- - REGISTER OUT @@ -1282,32 +1282,32 @@ begin -- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); - fb_ad(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else - "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else - lwd_q when lof_cs = '1' and lwd_cs = '1' else - "0000" & hbe_q when hbe_cs = '1' else - "0000" & hdb_q when hdb_cs = '1' else - "0000" & hde_q when hde_cs = '1' else - "0000" & hbb_q when hbb_cs = '1' else - "0000" & hss_q when hss_cs = '1' else - "0000" & hht_q when hht_cs = '1' else - "00000" & vbe_q when vbe_cs = '1' else - "00000" & vdb_q when vdb_cs = '1' else - "00000" & vde_q when vde_cs = '1' else - "00000" & vbb_q when vbb_cs = '1' else - "00000" & vss_q when vss_cs = '1' else - "00000" & vft_q when vft_cs = '1' else - "0000000" & vco_q when vco_cs = '1' else - "000000000000" & vcntrl_q when vcntrl_cs = '1' else - acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else - atari_hh_q(31 downto 16) when atari_hh_cs = '1' else - atari_vh_q(31 downto 16) when atari_vh_cs = '1' else - atari_hl_q(31 downto 16) when atari_hl_cs = '1' else - atari_vl_q(31 downto 16) when atari_vl_cs = '1' else - "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else - "0000000" & vr_dout_q when video_pll_config_cs = '1' else - vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else - (others => 'Z'); +-- fb_ad(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else +-- "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else +-- lwd_q when lof_cs = '1' and lwd_cs = '1' else +-- "0000" & hbe_q when hbe_cs = '1' else +-- "0000" & hdb_q when hdb_cs = '1' else +-- "0000" & hde_q when hde_cs = '1' else +-- "0000" & hbb_q when hbb_cs = '1' else +-- "0000" & hss_q when hss_cs = '1' else +-- "0000" & hht_q when hht_cs = '1' else +-- "00000" & vbe_q when vbe_cs = '1' else +-- "00000" & vdb_q when vdb_cs = '1' else +-- "00000" & vde_q when vde_cs = '1' else +-- "00000" & vbb_q when vbb_cs = '1' else +-- "00000" & vss_q when vss_cs = '1' else +-- "00000" & vft_q when vft_cs = '1' else +-- "0000000" & vco_q when vco_cs = '1' else +-- "000000000000" & vcntrl_q when vcntrl_cs = '1' else +-- acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else +-- atari_hh_q(31 downto 16) when atari_hh_cs = '1' else +-- atari_vh_q(31 downto 16) when atari_vh_cs = '1' else +-- atari_hl_q(31 downto 16) when atari_hl_cs = '1' else +-- atari_vl_q(31 downto 16) when atari_vl_cs = '1' else +-- "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else +-- "0000000" & vr_dout_q when video_pll_config_cs = '1' else +-- vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else +-- (others => 'Z'); -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or From cf0c4492580751ace606cc78247992f4ff558c2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 06:08:31 +0000 Subject: [PATCH 102/127] remove inout buffers --- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 3 +- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 39 ++-- FPGA_Quartus_13.1/Video/video.vhd | 223 ++++++++++---------- FPGA_Quartus_13.1/firebee1.vhd | 2 +- 4 files changed, 136 insertions(+), 131 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index 933b8b2..f42df9b 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -51,7 +51,8 @@ entity blitter is BLITTER_SIG : OUT std_logic; BLITTER_WR : OUT std_logic; blitter_ta : OUT std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + fb_ad_in : in std_logic_vector(31 DOWNTO 0); + fb_ad_out : out std_logic_vector(31 downto 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 1a665ed..907266f 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -60,7 +60,8 @@ entity ddr_ctr is BA : buffer std_logic_vector(1 downto 0); DDRWR_D_SEL1 : buffer std_logic; VDM_SEL : buffer std_logic_vector(3 downto 0); - FB_AD : inout std_logic_vector(31 downto 0) + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0) ); end ddr_ctr; @@ -744,7 +745,7 @@ begin DDRWR_D_SEL1 <= BLITTER_AC_q; -- SELECT LOGIC - ddr_sel <= to_std_logic(FB_ALE='1' and FB_AD(31 downto 30) = "01"); + ddr_sel <= to_std_logic(FB_ALE='1' and fb_ad_in(31 downto 30) = "01"); ddr_cs_clk <= main_clk; ddr_cs_ena <= FB_ALE; ddr_cs_d <= ddr_sel; @@ -790,7 +791,7 @@ begin FIFO_AC_q, CPU_COL_ADR, BLITTER_COL_ADR, VA_S_q, CPU_BA, BLITTER_BA, fb_b, CPU_AC_q, BLITTER_AC_q, FIFO_BANK_OK_q, FIFO_MW, FIFO_REQ_q, VIDEO_ADR_CNT_q, FIFO_COL_ADR, ddr_sel, LINE, FIFO_BA, VA_P_q, - BA_P_q, CPU_REQ_q, FB_AD, nFB_WR, fb_size0, fb_size1, + BA_P_q, CPU_REQ_q, fb_ad_in, nFB_WR, fb_size0, fb_size1, DDR_REFRESH_SIG_q) variable stdVec6: std_logic_vector(5 downto 0); begin @@ -851,8 +852,8 @@ begin -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** if (ddr_sel and (nFB_WR or (not LINE)))='1' then VRAS <= '1'; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); - (BA1_2, BA0_2) <= FB_AD(13 downto 12); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= fb_ad_in(26 downto 14); + (BA1_2, BA0_2) <= fb_ad_in(13 downto 12); -- AUTO PRECHARGE DA NICHT FIFO PAGE VA_S_d(10) <= '1'; CPU_AC_d <= '1'; @@ -1131,10 +1132,10 @@ begin end if; when "011100" => - if (ddr_sel and (nFB_WR or (not LINE)))='1' and FB_AD(13 downto 12) /= FIFO_BA then + if (ddr_sel and (nFB_WR or (not LINE)))='1' and fb_ad_in(13 downto 12) /= FIFO_BA then VRAS <= '1'; - (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= FB_AD(26 downto 14); - (BA1_2, BA0_2) <= FB_AD(13 downto 12); + (VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2) <= fb_ad_in(26 downto 14); + (BA1_2, BA0_2) <= fb_ad_in(13 downto 12); CPU_AC_d <= '1'; -- BUS CYCLUS LOSTRETEN @@ -1173,20 +1174,20 @@ begin DDR_SM_d <= "001100"; when "001100" => - VA_S_d <= FB_AD(12 downto 0); - BA_S_d <= FB_AD(14 downto 13); + VA_S_d <= fb_ad_in(12 downto 0); + BA_S_d <= fb_ad_in(14 downto 13); DDR_SM_d <= "001101"; when "001101" => -- NUR BEI LONG WRITE - VRAS <= FB_AD(18) and (not nFB_WR) and (not fb_size0) and (not fb_size1); + VRAS <= fb_ad_in(18) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- NUR BEI LONG WRITE - VCAS <= FB_AD(17) and (not nFB_WR) and (not fb_size0) and (not fb_size1); + VCAS <= fb_ad_in(17) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- NUR BEI LONG WRITE - VWE <= FB_AD(16) and (not nFB_WR) and (not fb_size0) and (not fb_size1); + VWE <= fb_ad_in(16) and (not nFB_WR) and (not fb_size0) and (not fb_size1); -- CLOSE FIFO BANK DDR_SM_d <= "000111"; @@ -1348,22 +1349,22 @@ begin VIDEO_BASE_L <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000110"); -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D_d <= FB_AD(23 downto 16); + VIDEO_BASE_L_D_d <= fb_ad_in(23 downto 16); VIDEO_BASE_L_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_L and fb_b(1); VIDEO_BASE_M_D0_clk_ctrl <= main_clk; -- 8203/2 VIDEO_BASE_M <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000001"); - VIDEO_BASE_M_D_d <= FB_AD(23 downto 16); + VIDEO_BASE_M_D_d <= fb_ad_in(23 downto 16); VIDEO_BASE_M_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_M and fb_b(3); VIDEO_BASE_H_D0_clk_ctrl <= main_clk; -- 8200-1/2 VIDEO_BASE_H <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000000"); - VIDEO_BASE_H_D_d <= FB_AD(23 downto 16); + VIDEO_BASE_H_D_d <= fb_ad_in(23 downto 16); VIDEO_BASE_H_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(1); VIDEO_BASE_X_D0_clk_ctrl <= main_clk; - VIDEO_BASE_X_D_d <= FB_AD(26 downto 24); + VIDEO_BASE_X_D_d <= fb_ad_in(26 downto 24); VIDEO_BASE_X_D0_ena_ctrl <= (not nFB_WR) and VIDEO_BASE_H and fb_b(0); -- 8209/2 @@ -1379,7 +1380,7 @@ begin -- VIDEO_BASE_H & (0, VIDEO_BASE_X_D[]) -- # VIDEO_CNT_H & (0, VIDEO_ACT_ADR[26..24]), -- (VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - fb_ad(31 downto 24) <= "00000" & video_base_x_d_d when video_base_h and not nfb_oe else + fb_ad_out(31 downto 24) <= "00000" & video_base_x_d_d when video_base_h and not nfb_oe else "00000" & video_act_adr(26 downto 24) when video_cnt_h and not nfb_oe else (others => 'Z'); @@ -1391,7 +1392,7 @@ begin (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - -- FB_AD(23 downto 16) <= u0_tridata when u0_enabledt; + fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt; -- Assignments added to explicitly combine the diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 958dbde..bf4f310 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -40,7 +40,8 @@ ENTITY video IS CLK_VIDEO : IN std_logic; VR_BUSY : IN std_logic; DDRCLK : IN std_logic_vector(3 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + fb_ad_in : in std_logic_vector(31 DOWNTO 0); + fb_ad_out : out std_logic_vector(31 downto 0); FB_ADR : IN std_logic_vector(31 DOWNTO 0); VD : INOUT std_logic_vector(31 DOWNTO 0); VDQS : INOUT std_logic_vector(3 DOWNTO 0); @@ -280,8 +281,8 @@ BEGIN GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); - ACP_CLUT_RAM : entity work.altdpram2 - PORT MAP + acp_clut_ram : entity work.altdpram2 + port map ( wren_a => ACP_CLUT_WR(3), wren_b => SYNTHESIZED_WIRE_0, @@ -289,15 +290,15 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => ZR_C8B, - data_a => FB_AD(7 DOWNTO 0), + data_a => fb_ad_in(7 DOWNTO 0), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_30, q_b => CCA(7 DOWNTO 0) ); - ACP_CLUT_RAM54 : entity work.altdpram2 - PORT MAP + acp_clut_ram_54 : entity work.altdpram2 + port map ( wren_a => ACP_CLUT_WR(2), wren_b => SYNTHESIZED_WIRE_1, @@ -305,15 +306,15 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => ZR_C8B, - data_a => FB_AD(15 DOWNTO 8), + data_a => fb_ad_in(15 DOWNTO 8), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_32, q_b => CCA(15 DOWNTO 8) ); - ACP_CLUT_RAM55 : entity work.altdpram2 - PORT MAP + acp_clut_ram55 : entity work.altdpram2 + port map ( wren_a => ACP_CLUT_WR(1), wren_b => SYNTHESIZED_WIRE_2, @@ -321,7 +322,7 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => ZR_C8B, - data_a => FB_AD(23 DOWNTO 16), + data_a => fb_ad_in(23 DOWNTO 16), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_33, q_b => CCA(23 DOWNTO 16) @@ -329,7 +330,7 @@ BEGIN i_blitter : entity work.blitter - PORT MAP + port map ( nRSTO => nRSTO, MAIN_CLK => MAIN_CLK, @@ -346,7 +347,8 @@ BEGIN SR_BLITTER_DACK => SR_BLITTER_DACK, BLITTER_DACK => BLITTER_DACK, BLITTER_DIN => BLITTER_DIN, - FB_AD => FB_AD, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, VIDEO_RAM_CTR => VIDEO_RAM_CTR, BLITTER_RUN => BLITTER_RUN, @@ -359,7 +361,7 @@ BEGIN i_ddr_ctr : entity work.ddr_ctr - PORT MAP + port map ( nFB_CS1 => nFB_CS1, nFB_CS2 => nFB_CS2, @@ -378,7 +380,8 @@ BEGIN CLK33M => CLK33M, CLR_FIFO => CLR_FIFO, BLITTER_ADR => BLITTER_ADR, - FB_AD => FB_AD, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, FIFO_MW => FIFO_MW, VIDEO_RAM_CTR => VIDEO_RAM_CTR, @@ -403,8 +406,8 @@ BEGIN ); - FALCON_CLUT_BLUE : entity work.altdpram1 - PORT MAP + falcon_clut_blue : entity work.altdpram1 + port map ( wren_a => FALCON_CLUT_WR(3), wren_b => SYNTHESIZED_WIRE_3, @@ -412,15 +415,15 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), + data_a => fb_ad_in(23 DOWNTO 18), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_45, q_b => CCF(7 DOWNTO 2) ); - FALCON_CLUT_GREEN : entity work.altdpram1 - PORT MAP + falcon_clut_green : entity work.altdpram1 + port map ( wren_a => FALCON_CLUT_WR(1), wren_b => SYNTHESIZED_WIRE_4, @@ -428,15 +431,15 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => CLUT_ADR, - data_a => FB_AD(23 DOWNTO 18), + data_a => fb_ad_in(23 DOWNTO 18), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_44, q_b => CCF(15 DOWNTO 10) ); - FALCON_CLUT_RED : entity work.altdpram1 - PORT MAP + falcon_clut_red : entity work.altdpram1 + port map ( wren_a => FALCON_CLUT_WR(0), wren_b => SYNTHESIZED_WIRE_5, @@ -444,7 +447,7 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(9 DOWNTO 2), address_b => CLUT_ADR, - data_a => FB_AD(31 DOWNTO 26), + data_a => fb_ad_in(31 DOWNTO 26), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_41, q_b => CCF(23 DOWNTO 18) @@ -452,7 +455,7 @@ BEGIN inst : entity work.lpm_fifo_dc0 - PORT MAP + port map ( wrreq => FIFO_WRE, wrclk => DDRCLK(0), @@ -466,7 +469,7 @@ BEGIN inst1 : entity work.altddio_bidir0 - PORT MAP + port map ( oe => VDOUT_OE, inclock => DDRCLK(1), @@ -481,7 +484,7 @@ BEGIN inst10 : entity work.lpm_ff4 - PORT MAP + port map ( clock => pixel_clk_i, data => SYNTHESIZED_WIRE_7, @@ -490,7 +493,7 @@ BEGIN inst100 : entity work.lpm_muxvdm - PORT MAP + port map ( data0x => VDMB, data10x => GDFX_TEMP_SIGNAL_1, @@ -514,7 +517,7 @@ BEGIN inst102 : entity work.lpm_mux3 - PORT MAP + port map ( data1 => DFF_inst93, data0 => ZR_C8(0), @@ -533,25 +536,25 @@ BEGIN inst108 : entity work.lpm_bustri_long - PORT MAP + port map ( enabledt => FB_VDOE(0), data => VDR, - tridata => FB_AD + tridata => fb_ad_out ); inst109 : entity work.lpm_bustri_long - PORT MAP + port map ( enabledt => FB_VDOE(1), data => SYNTHESIZED_WIRE_11, - tridata => FB_AD + tridata => fb_ad_out ); inst11 : entity work.lpm_ff5 - PORT MAP + port map ( clock => pixel_clk_i, data => SYNTHESIZED_WIRE_12, @@ -560,25 +563,25 @@ BEGIN inst110 : entity work.lpm_bustri_long - PORT MAP + port map ( enabledt => FB_VDOE(2), data => SYNTHESIZED_WIRE_13, - tridata => FB_AD + tridata => fb_ad_out ); inst119 : entity work.lpm_bustri_long - PORT MAP + port map ( enabledt => FB_VDOE(3), data => SYNTHESIZED_WIRE_14, - tridata => FB_AD + tridata => fb_ad_out ); inst12 : entity work.lpm_ff1 - PORT MAP + port map ( clock => DDRCLK(0), data => VDP_IN(31 DOWNTO 0), @@ -587,47 +590,47 @@ BEGIN inst13 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDR_SYNC_66M, enable => FB_LE(0), - data => FB_AD, + data => fb_ad_out, q => FB_DDR(127 DOWNTO 96) ); inst14 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDR_SYNC_66M, enable => FB_LE(1), - data => FB_AD, + data => fb_ad_out, q => FB_DDR(95 DOWNTO 64) ); inst15 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDR_SYNC_66M, enable => FB_LE(2), - data => FB_AD, + data => fb_ad_out, q => FB_DDR(63 DOWNTO 32) ); inst16 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDR_SYNC_66M, enable => FB_LE(3), - data => FB_AD, + data => fb_ad_out, q => FB_DDR(31 DOWNTO 0) ); inst17 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDRCLK(0), enable => DDR_FB(1), @@ -637,7 +640,7 @@ BEGIN inst18 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDRCLK(0), enable => DDR_FB(0), @@ -647,7 +650,7 @@ BEGIN inst19 : entity work.lpm_ff0 - PORT MAP + port map ( clock => DDRCLK(0), enable => DDR_FB(0), @@ -657,7 +660,7 @@ BEGIN inst2 : entity work.altddio_out0 - PORT MAP + port map ( outclock => DDRCLK(3), datain_h => VDMP(7 DOWNTO 4), @@ -667,7 +670,7 @@ BEGIN inst20 : entity work.lpm_ff1 - PORT MAP + port map ( clock => DDRCLK(0), data => VDVZ(31 DOWNTO 0), @@ -676,7 +679,7 @@ BEGIN inst21 : entity work.lpm_mux0 - PORT MAP + port map ( clock => pixel_clk_i, data0x => FIFO_D(127 DOWNTO 96), @@ -689,7 +692,7 @@ BEGIN inst22 : entity work.lpm_mux5 - PORT MAP + port map ( data0x => FB_DDR(127 DOWNTO 64), data1x => FB_DDR(63 DOWNTO 0), @@ -701,14 +704,14 @@ BEGIN inst23 : entity work.lpm_constant2 - PORT MAP + port map ( result => GDFX_TEMP_SIGNAL_16 ); inst24 : entity work.lpm_mux1 - PORT MAP + port map ( clock => pixel_clk_i, data0x => FIFO_D(127 DOWNTO 112), @@ -725,7 +728,7 @@ BEGIN inst25 : entity work.lpm_mux2 - PORT MAP + port map ( clock => pixel_clk_i, data0x => FIFO_D(127 DOWNTO 120), @@ -750,7 +753,7 @@ BEGIN inst26 : entity work.lpm_shiftreg4 - PORT MAP + port map ( clock => DDRCLK(0), shiftin => SR_FIFO_WRE, @@ -759,7 +762,7 @@ BEGIN inst27 : entity work.lpm_latch0 - PORT MAP + port map ( gate => DDR_SYNC_66M, data => SYNTHESIZED_WIRE_15, @@ -770,7 +773,7 @@ BEGIN inst3 : entity work.lpm_ff1 - PORT MAP + port map ( clock => DDRCLK(0), data => VDP_IN(63 DOWNTO 32), @@ -785,7 +788,7 @@ BEGIN SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; inst36 : entity work.lpm_ff6 - PORT MAP + port map ( clock => DDRCLK(0), enable => BLITTER_DACK(0), @@ -797,7 +800,7 @@ BEGIN video_ta <= blitter_ta /* or video_mod_ta */ or video_ddr_ta; inst4 : entity work.lpm_ff1 - PORT MAP + port map ( clock => DDRCLK(0), data => VDVZ(63 DOWNTO 32), @@ -806,7 +809,7 @@ BEGIN inst40 : entity work.mux41_0 - PORT MAP + port map ( S0 => COLOR2, S1 => COLOR4, @@ -818,7 +821,7 @@ BEGIN inst41 : entity work.mux41_1 - PORT MAP + port map ( S0 => COLOR2, S1 => COLOR4, @@ -830,7 +833,7 @@ BEGIN inst42 : entity work.mux41_2 - PORT MAP + port map ( S0 => COLOR2, D2 => CLUT_ADR7A, @@ -843,7 +846,7 @@ BEGIN inst43 : entity work.mux41_3 - PORT MAP + port map ( S0 => COLOR2, D2 => CLUT_ADR6A, @@ -856,7 +859,7 @@ BEGIN inst44 : entity work.mux41_4 - PORT MAP + port map ( S0 => COLOR2, D2 => CLUT_ADR5A, @@ -869,7 +872,7 @@ BEGIN inst45 : entity work.mux41_5 - PORT MAP + port map ( S0 => COLOR2, D2 => CLUT_ADR4A, @@ -882,7 +885,7 @@ BEGIN inst46 : entity work.lpm_ff3 - PORT MAP + port map ( clock => pixel_clk_i, data => SYNTHESIZED_WIRE_25, @@ -891,7 +894,7 @@ BEGIN inst47 : entity work.lpm_ff3 - PORT MAP + port map ( clock => pixel_clk_i, data => CCF, @@ -901,7 +904,7 @@ BEGIN inst49 : entity work.lpm_ff3 - PORT MAP + port map ( clock => pixel_clk_i, data => SYNTHESIZED_WIRE_26, @@ -910,7 +913,7 @@ BEGIN inst5 : entity work.altddio_out2 - PORT MAP + port map ( outclock => pixel_clk_i, datain_h => SYNTHESIZED_WIRE_62, @@ -921,7 +924,7 @@ BEGIN inst51 : entity work.lpm_bustri1 - PORT MAP + port map ( enabledt => ST_CLUT_RD, data => SYNTHESIZED_WIRE_29, @@ -930,7 +933,7 @@ BEGIN inst52 : entity work.lpm_ff3 - PORT MAP + port map ( clock => pixel_clk_i, data => CCS, @@ -939,7 +942,7 @@ BEGIN inst53 : entity work.lpm_bustri_byt - PORT MAP + port map ( enabledt => ACP_CLUT_RD, data => SYNTHESIZED_WIRE_30, @@ -948,7 +951,7 @@ BEGIN inst54 : entity work.lpm_constant0 - PORT MAP + port map ( result => CCS(20 DOWNTO 16) ); @@ -956,7 +959,7 @@ BEGIN inst56 : entity work.lpm_bustri1 - PORT MAP + port map ( enabledt => ST_CLUT_RD, data => SYNTHESIZED_WIRE_31, @@ -965,7 +968,7 @@ BEGIN inst57 : entity work.lpm_bustri_byt - PORT MAP + port map ( enabledt => ACP_CLUT_RD, data => SYNTHESIZED_WIRE_32, @@ -974,7 +977,7 @@ BEGIN inst58 : entity work.lpm_bustri_byt - PORT MAP + port map ( enabledt => ACP_CLUT_RD, data => SYNTHESIZED_WIRE_33, @@ -983,7 +986,7 @@ BEGIN inst59 : entity work.lpm_constant0 - PORT MAP + port map ( result => CCS(12 DOWNTO 8) ); @@ -992,7 +995,7 @@ BEGIN inst61 : entity work.lpm_bustri1 - PORT MAP + port map ( enabledt => ST_CLUT_RD, data => SYNTHESIZED_WIRE_34, @@ -1001,7 +1004,7 @@ BEGIN inst62 : entity work.lpm_muxdz - PORT MAP + port map ( clock => pixel_clk_i, clken => FIFO_RDE, @@ -1013,7 +1016,7 @@ BEGIN inst63 : entity work.lpm_fifodz - PORT MAP + port map ( wrreq => SYNTHESIZED_WIRE_60, rdreq => SYNTHESIZED_WIRE_38, @@ -1025,7 +1028,7 @@ BEGIN inst64 : entity work.lpm_constant0 - PORT MAP + port map ( result => CCS(4 DOWNTO 0) ); @@ -1035,7 +1038,7 @@ BEGIN inst66 : entity work.lpm_bustri3 - PORT MAP + port map ( enabledt => FALCON_CLUT_RDH, data => SYNTHESIZED_WIRE_41, @@ -1047,7 +1050,7 @@ BEGIN SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); inst7 : entity work.lpm_mux6 - PORT MAP + port map ( clock => pixel_clk_i, data0x => SYNTHESIZED_WIRE_42, @@ -1064,7 +1067,7 @@ BEGIN inst70 : entity work.lpm_bustri3 - PORT MAP + port map ( enabledt => FALCON_CLUT_RDH, data => SYNTHESIZED_WIRE_44, @@ -1073,7 +1076,7 @@ BEGIN inst71 : entity work.lpm_ff6 - PORT MAP + port map ( clock => DDRCLK(0), enable => FIFO_WRE, @@ -1085,7 +1088,7 @@ BEGIN inst74 : entity work.lpm_bustri3 - PORT MAP + port map ( enabledt => FALCON_CLUT_RDL, data => SYNTHESIZED_WIRE_45, @@ -1096,7 +1099,7 @@ BEGIN inst77 : entity work.lpm_constant1 - PORT MAP + port map ( result => CCF(1 DOWNTO 0) ); @@ -1108,14 +1111,14 @@ BEGIN inst80 : entity work.lpm_constant1 - PORT MAP + port map ( result => CCF(9 DOWNTO 8) ); inst81 : entity work.lpm_mux4 - PORT MAP + port map ( sel => COLOR1, data0x => ZR_C8(7 DOWNTO 1), @@ -1125,14 +1128,14 @@ BEGIN inst82 : entity work.lpm_constant3 - PORT MAP + port map ( result => SYNTHESIZED_WIRE_47 ); inst83 : entity work.lpm_constant1 - PORT MAP + port map ( result => CCF(17 DOWNTO 16) ); @@ -1158,7 +1161,7 @@ BEGIN inst89 : entity work.lpm_shiftreg6 - PORT MAP + port map ( clock => DDRCLK(0), shiftin => SR_BLITTER_DACK, @@ -1167,7 +1170,7 @@ BEGIN inst9 : entity work.lpm_ff1 - PORT MAP + port map ( clock => pixel_clk_i, data => SYNTHESIZED_WIRE_48, @@ -1184,7 +1187,7 @@ BEGIN inst92 : entity work.lpm_shiftreg6 - PORT MAP + port map ( clock => DDRCLK(0), shiftin => SR_DDR_FB, @@ -1201,7 +1204,7 @@ BEGIN inst94 : entity work.lpm_ff6 - PORT MAP + port map ( clock => DDRCLK(0), enable => FIFO_WRE, @@ -1220,7 +1223,7 @@ BEGIN inst97 : entity work.lpm_ff5 - PORT MAP + port map ( clock => DDRCLK(2), data => SR_VDMP, @@ -1229,7 +1232,7 @@ BEGIN sr0 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1240,7 +1243,7 @@ BEGIN sr1 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1251,7 +1254,7 @@ BEGIN sr2 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1262,7 +1265,7 @@ BEGIN sr3 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1273,7 +1276,7 @@ BEGIN sr4 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1284,7 +1287,7 @@ BEGIN sr5 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1295,7 +1298,7 @@ BEGIN sr6 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1306,7 +1309,7 @@ BEGIN sr7 : entity work.lpm_shiftreg0 - PORT MAP + port map ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, @@ -1317,7 +1320,7 @@ BEGIN ST_CLUT_BLUE : entity work.altdpram0 - PORT MAP + port map ( wren_a => ST_CLUT_WR(1), wren_b => '0', @@ -1333,7 +1336,7 @@ BEGIN ST_CLUT_GREEN : entity work.altdpram0 - PORT MAP + port map ( wren_a => ST_CLUT_WR(1), wren_b => '0', @@ -1349,7 +1352,7 @@ BEGIN ST_CLUT_RED : entity work.altdpram0 - PORT MAP + port map ( wren_a => ST_CLUT_WR(0), wren_b => '0', @@ -1365,7 +1368,7 @@ BEGIN i_video_mod_mux_clutctr : entity work.video_mod_mux_clutctr - PORT MAP + port map ( nRSTO => nRSTO, MAIN_CLK => MAIN_CLK, diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 49d04e6..d2f601b 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -297,7 +297,7 @@ begin ); - i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf + i_falconio_sdcard_ide_cf : work.falconio_sdcard_ide_cf port map ( CLK33M => CLK33M, From c6f8a7d4e870f03275a8dd9c0f245ff24489b799 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 07:11:19 +0000 Subject: [PATCH 103/127] compiles again, but needs reconnecting the split FlexBus signal at top level --- FPGA_Quartus_13.1/Video/video.vhd | 147 +++--------------- .../Video/video_mod_mux_clutctr.vhd | 113 +++++++------- FPGA_Quartus_13.1/firebee1.vhd | 5 +- 3 files changed, 85 insertions(+), 180 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index bf4f310..17e6fcd 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -534,23 +534,9 @@ BEGIN SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; - - inst108 : entity work.lpm_bustri_long - port map - ( - enabledt => FB_VDOE(0), - data => VDR, - tridata => fb_ad_out - ); - - - inst109 : entity work.lpm_bustri_long - port map - ( - enabledt => FB_VDOE(1), - data => SYNTHESIZED_WIRE_11, - tridata => fb_ad_out - ); + + fb_ad_out <= vdr when fb_vdoe(0) else (others => 'Z'); + fb_ad_out <= synthesized_wire_11 when fb_vdoe(1) else (others => 'Z'); inst11 : entity work.lpm_ff5 @@ -561,23 +547,8 @@ BEGIN q => ZR_C8 ); - - inst110 : entity work.lpm_bustri_long - port map - ( - enabledt => FB_VDOE(2), - data => SYNTHESIZED_WIRE_13, - tridata => fb_ad_out - ); - - - inst119 : entity work.lpm_bustri_long - port map - ( - enabledt => FB_VDOE(3), - data => SYNTHESIZED_WIRE_14, - tridata => fb_ad_out - ); + fb_ad_out <= synthesized_wire_13 when fb_vdoe(2) else (others => 'Z'); + fb_ad_out <= synthesized_wire_14 when fb_vdoe(3) else (others => 'Z'); inst12 : entity work.lpm_ff1 @@ -594,7 +565,7 @@ BEGIN ( clock => DDR_SYNC_66M, enable => FB_LE(0), - data => fb_ad_out, + data => fb_ad_in, q => FB_DDR(127 DOWNTO 96) ); @@ -604,7 +575,7 @@ BEGIN ( clock => DDR_SYNC_66M, enable => FB_LE(1), - data => fb_ad_out, + data => fb_ad_in, q => FB_DDR(95 DOWNTO 64) ); @@ -614,7 +585,7 @@ BEGIN ( clock => DDR_SYNC_66M, enable => FB_LE(2), - data => fb_ad_out, + data => fb_ad_in, q => FB_DDR(63 DOWNTO 32) ); @@ -624,7 +595,7 @@ BEGIN ( clock => DDR_SYNC_66M, enable => FB_LE(3), - data => fb_ad_out, + data => fb_ad_in, q => FB_DDR(31 DOWNTO 0) ); @@ -921,15 +892,7 @@ BEGIN dataout => SYNTHESIZED_WIRE_65 ); - - - inst51 : entity work.lpm_bustri1 - port map - ( - enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_29, - tridata => FB_AD(26 DOWNTO 24) - ); + fb_ad_out(26 downto 24) <= synthesized_wire_29 when st_clut_rd else (others => 'Z'); inst52 : entity work.lpm_ff3 @@ -940,14 +903,7 @@ BEGIN q => SYNTHESIZED_WIRE_26 ); - - inst53 : entity work.lpm_bustri_byt - port map - ( - enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_30, - tridata => FB_AD(7 DOWNTO 0) - ); + fb_ad_out(7 downto 0) <= synthesized_wire_30 when acp_clut_rd else (others => 'Z'); inst54 : entity work.lpm_constant0 @@ -957,32 +913,10 @@ BEGIN ); + fb_ad_out(22 downto 20) <= synthesized_wire_31 when st_clut_rd else (others => 'Z'); + fb_ad_out(15 downto 8) <= synthesized_wire_32 when acp_clut_rd else (others => 'Z'); - inst56 : entity work.lpm_bustri1 - port map - ( - enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_31, - tridata => FB_AD(22 DOWNTO 20) - ); - - - inst57 : entity work.lpm_bustri_byt - port map - ( - enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_32, - tridata => FB_AD(15 DOWNTO 8) - ); - - - inst58 : entity work.lpm_bustri_byt - port map - ( - enabledt => ACP_CLUT_RD, - data => SYNTHESIZED_WIRE_33, - tridata => FB_AD(23 DOWNTO 16) - ); + fb_ad_out(23 downto 16) <= synthesized_wire_33 when acp_clut_rd else (others => 'Z'); inst59 : entity work.lpm_constant0 @@ -991,16 +925,7 @@ BEGIN result => CCS(12 DOWNTO 8) ); - - - - inst61 : entity work.lpm_bustri1 - port map - ( - enabledt => ST_CLUT_RD, - data => SYNTHESIZED_WIRE_34, - tridata => FB_AD(18 DOWNTO 16) - ); + fb_ad_out(18 downto 16) <= synthesized_wire_34 when st_clut_rd else (others => 'Z'); inst62 : entity work.lpm_muxdz @@ -1036,15 +961,9 @@ BEGIN SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; - - inst66 : entity work.lpm_bustri3 - port map - ( - enabledt => FALCON_CLUT_RDH, - data => SYNTHESIZED_WIRE_41, - tridata => FB_AD(31 DOWNTO 26) - ); - + fb_ad_out(31 downto 26) <= synthesized_wire_41 when falcon_clut_rdh else (others => 'Z'); + -- the following line results in a syntax error. No idea what's wrong with it: + -- fb_ad_out(23 downto 18) <= synthesized_wire_44 when falcon_clut_rdh else (others <= 'Z'); SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); @@ -1066,15 +985,6 @@ BEGIN ); - inst70 : entity work.lpm_bustri3 - port map - ( - enabledt => FALCON_CLUT_RDH, - data => SYNTHESIZED_WIRE_44, - tridata => FB_AD(23 DOWNTO 18) - ); - - inst71 : entity work.lpm_ff6 port map ( @@ -1084,17 +994,7 @@ BEGIN q => VDMA ); - - - - inst74 : entity work.lpm_bustri3 - port map - ( - enabledt => FALCON_CLUT_RDL, - data => SYNTHESIZED_WIRE_45, - tridata => FB_AD(23 DOWNTO 18) - ); - + fb_ad_out(23 downto 18) <= synthesized_wire_45 when falcon_clut_rdl else (others => 'Z'); @@ -1328,7 +1228,7 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(18 DOWNTO 16), + data_a => fb_ad_in(18 DOWNTO 16), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_34, q_b => CCS(7 DOWNTO 5) @@ -1344,7 +1244,7 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(22 DOWNTO 20), + data_a => fb_ad_in(22 DOWNTO 20), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_31, q_b => CCS(15 DOWNTO 13) @@ -1360,7 +1260,7 @@ BEGIN clock_b => pixel_clk_i, address_a => FB_ADR(4 DOWNTO 1), address_b => CLUT_ADR(3 DOWNTO 0), - data_a => FB_AD(26 DOWNTO 24), + data_a => fb_ad_in(26 DOWNTO 24), data_b => (OTHERS => '0'), q_a => SYNTHESIZED_WIRE_29, q_b => CCS(23 DOWNTO 21) @@ -1385,7 +1285,8 @@ BEGIN BLITTER_RUN => BLITTER_RUN, CLK_VIDEO => CLK_VIDEO, VR_BUSY => VR_BUSY, - FB_AD => FB_AD, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, VR_D => VR_D, COLOR8 => COLOR8, diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 50f65f0..a44b48e 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -111,7 +111,8 @@ entity video_mod_mux_clutctr is vr_wr : out std_logic; vr_rd : out std_logic; clr_fifo : out std_logic; - fb_ad : out std_logic_vector(31 downto 0) + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0) ); end video_mod_mux_clutctr; @@ -957,7 +958,7 @@ begin -- $F8260/2 st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adR(19 downto 1) = 19x"7c130" else '0'; -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110000"); - st_shift_mode_d <= fb_ad(25 downto 24) when st_shift_mode_cs; + st_shift_mode_d <= fb_ad_in(25 downto 24) when st_shift_mode_cs; st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0); -- MONO @@ -973,7 +974,7 @@ begin -- $F8266/2 falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110011"); - falcon_shift_mode_d <= fb_ad(26 downto 16) when falcon_shift_mode_cs; + falcon_shift_mode_d <= fb_ad_in(26 downto 16) when falcon_shift_mode_cs; falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2); falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3); @@ -1001,8 +1002,8 @@ begin -- $400/4 acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000000"); - acp_vctr_d(31 downto 8) <= fb_ad(31 downto 8) when acp_vctr_cs; - acp_vctr_d(5 downto 0) <= fb_ad(5 downto 0) when acp_vctr_cs; + acp_vctr_d(31 downto 8) <= fb_ad_in(31 downto 8) when acp_vctr_cs; + acp_vctr_d(5 downto 0) <= fb_ad_in(5 downto 0) when acp_vctr_cs; acp_vctr24_ena_ctrl <= acp_vctr_CS and fb_b(0) and (not nFB_WR); acp_vctr16_ena_ctrl <= acp_vctr_CS and fb_b(1) and (not nFB_WR); @@ -1019,7 +1020,7 @@ begin -- $410/4 ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000100"); - ATARI_HH_d <= fb_ad when atari_hh_cs; + ATARI_HH_d <= fb_ad_in when atari_hh_cs; ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); @@ -1029,7 +1030,7 @@ begin -- $414/4 ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000101"); - ATARI_VH_d <= fb_ad when atari_vh_cs; + ATARI_VH_d <= fb_ad_in when atari_vh_cs; ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); @@ -1039,7 +1040,7 @@ begin -- $418/4 ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000110"); - ATARI_HL_d <= fb_ad when atari_hl_cs; + ATARI_HL_d <= fb_ad_in when atari_hl_cs; ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); @@ -1049,7 +1050,7 @@ begin -- $41C/4 ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000111"); - ATARI_VL_d <= fb_ad when atari_vl_cs; + ATARI_VL_d <= fb_ad_in when atari_vl_cs; ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); @@ -1063,7 +1064,7 @@ begin vr_dout0_ena_ctrl <= not vr_busy; vr_dout_d <= vr_d; vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adR(8 downto 0) = "000000100"); - vr_frq_d <= fb_ad(23 downto 16) when video_pll_config_cs; + vr_frq_d <= fb_ad_in(23 downto 16) when video_pll_config_cs; -- VIDEO PLL RECONFIG -- $(F)000'0800 @@ -1084,7 +1085,7 @@ begin acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and fb_ad(0)); + acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and fb_ad_in(0)); FALCON_VIDEO <= acp_vctr_q(7); FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not color16); ST_VIDEO <= acp_vctr_q(6); @@ -1102,7 +1103,7 @@ begin -- $404/4 border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 2) = "00000000000000000100000001"); - border_color_d <= fb_ad(23 downto 0) when border_color_cs; + border_color_d <= fb_ad_in(23 downto 0) when border_color_cs; border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR); border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR); border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR); @@ -1134,14 +1135,14 @@ begin -- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011"); - sys_ctr_d <= fb_ad(22 downto 16) when sys_ctr_cs; + sys_ctr_d <= fb_ad_in(22 downto 16) when sys_ctr_cs; sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3); blitter_on <= not sys_ctr_q(3); -- lof -- $820E/2 lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100000111"); - lof_d <= fb_ad(31 downto 16) when lof_cs; + lof_d <= fb_ad_in(31 downto 16) when lof_cs; lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2); lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3); lof <= lof_q; @@ -1149,7 +1150,7 @@ begin -- lwd -- $8210/2 lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100001000"); - lwd_d <= fb_ad(31 downto 16) when lwd_cs; + lwd_d <= fb_ad_in(31 downto 16) when lwd_cs; lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0); lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1); @@ -1157,42 +1158,42 @@ begin -- HHT -- $8282/2 HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000001"); - HHT_d <= fb_ad(27 downto 16) when hht_cs; + HHT_d <= fb_ad_in(27 downto 16) when hht_cs; HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); -- HBE -- $8286/2 HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000011"); - HBE_d <= fb_ad(27 downto 16) when hbe_cs; + HBE_d <= fb_ad_in(27 downto 16) when hbe_cs; HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); -- HDB -- $8288/2 HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000100"); - HDB_d <= fb_ad(27 downto 16) when hdb_cs; + HDB_d <= fb_ad_in(27 downto 16) when hdb_cs; HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); -- HDE -- $828A/2 HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000101"); - HDE_d <= fb_ad(27 downto 16) when hde_cs; + HDE_d <= fb_ad_in(27 downto 16) when hde_cs; HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); -- HBB -- $8284/2 HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000010"); - HBB_d <= fb_ad(27 downto 16) when hbb_cs; + HBB_d <= fb_ad_in(27 downto 16) when hbb_cs; HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); -- HSS -- Videl hsync start register $828C / 2 HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000110"); - HSS_d <= fb_ad(27 downto 16) when hss_cs; + HSS_d <= fb_ad_in(27 downto 16) when hss_cs; HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); @@ -1200,35 +1201,35 @@ begin -- VBE -- $82A6/2 VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010011"); - VBE_d <= fb_ad(26 downto 16) when vbe_cs; + VBE_d <= fb_ad_in(26 downto 16) when vbe_cs; VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); -- VDB -- $82A8/2 VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010100"); - VDB_d <= fb_ad(26 downto 16) when vdb_cs; + VDB_d <= fb_ad_in(26 downto 16) when vdb_cs; VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); -- VDE -- $82AA/2 VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010101"); - VDE_d <= fb_ad(26 downto 16) when vde_cs; + VDE_d <= fb_ad_in(26 downto 16) when vde_cs; VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); -- VBB -- $82A4/2 VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010010"); - VBB_d <= fb_ad(26 downto 16) when vbb_cs; + VBB_d <= fb_ad_in(26 downto 16) when vbb_cs; VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); -- VSS -- $82AC/2 VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010110"); - VSS_d <= fb_ad(26 downto 16) when vss_cs; + VSS_d <= fb_ad_in(26 downto 16) when vss_cs; VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); @@ -1236,21 +1237,21 @@ begin -- $82A2/2 -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010001"); vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); - VFT_d <= fb_ad(26 downto 16) when vft_cs; + VFT_d <= fb_ad_in(26 downto 16) when vft_cs; VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); -- VCO -- $82C0 / 2 Falcon clock control register VCO VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101100000"); - VCO_d <= fb_ad(24 downto 16) when vco_cs; + VCO_d <= fb_ad_in(24 downto 16) when vco_cs; VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; - vcntrl_d <= fb_ad(19 downto 16) when vcntrl_cs; + vcntrl_d <= fb_ad_in(19 downto 16) when vcntrl_cs; VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and FB_B(3); -- - REGISTER OUT @@ -1282,32 +1283,32 @@ begin -- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); --- fb_ad(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else --- "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else --- lwd_q when lof_cs = '1' and lwd_cs = '1' else --- "0000" & hbe_q when hbe_cs = '1' else --- "0000" & hdb_q when hdb_cs = '1' else --- "0000" & hde_q when hde_cs = '1' else --- "0000" & hbb_q when hbb_cs = '1' else --- "0000" & hss_q when hss_cs = '1' else --- "0000" & hht_q when hht_cs = '1' else --- "00000" & vbe_q when vbe_cs = '1' else --- "00000" & vdb_q when vdb_cs = '1' else --- "00000" & vde_q when vde_cs = '1' else --- "00000" & vbb_q when vbb_cs = '1' else --- "00000" & vss_q when vss_cs = '1' else --- "00000" & vft_q when vft_cs = '1' else --- "0000000" & vco_q when vco_cs = '1' else --- "000000000000" & vcntrl_q when vcntrl_cs = '1' else --- acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else --- atari_hh_q(31 downto 16) when atari_hh_cs = '1' else --- atari_vh_q(31 downto 16) when atari_vh_cs = '1' else --- atari_hl_q(31 downto 16) when atari_hl_cs = '1' else --- atari_vl_q(31 downto 16) when atari_vl_cs = '1' else --- "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else --- "0000000" & vr_dout_q when video_pll_config_cs = '1' else --- vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else --- (others => 'Z'); + fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else + "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else + lwd_q when lof_cs = '1' and lwd_cs = '1' else + "0000" & hbe_q when hbe_cs = '1' else + "0000" & hdb_q when hdb_cs = '1' else + "0000" & hde_q when hde_cs = '1' else + "0000" & hbb_q when hbb_cs = '1' else + "0000" & hss_q when hss_cs = '1' else + "0000" & hht_q when hht_cs = '1' else + "00000" & vbe_q when vbe_cs = '1' else + "00000" & vdb_q when vdb_cs = '1' else + "00000" & vde_q when vde_cs = '1' else + "00000" & vbb_q when vbb_cs = '1' else + "00000" & vss_q when vss_cs = '1' else + "00000" & vft_q when vft_cs = '1' else + "0000000" & vco_q when vco_cs = '1' else + "000000000000" & vcntrl_q when vcntrl_cs = '1' else + acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else + atari_hh_q(31 downto 16) when atari_hh_cs = '1' else + atari_vh_q(31 downto 16) when atari_vh_cs = '1' else + atari_hl_q(31 downto 16) when atari_hl_cs = '1' else + atari_vl_q(31 downto 16) when atari_vl_cs = '1' else + "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else + "0000000" & vr_dout_q when video_pll_config_cs = '1' else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else + (others => 'Z'); -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or @@ -1324,7 +1325,7 @@ begin -- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); -- fb_ad(15 downto 0) <= u1_tridata; - fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else + fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else atari_hh_q(15 downto 0) when atari_hh_cs = '1' else atari_vh_q(15 downto 0) when atari_vh_cs = '1' else atari_hl_q(15 downto 0) when atari_hl_cs = '1' else diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index d2f601b..39d550e 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -201,6 +201,8 @@ architecture rtl OF firebee1 IS signal nFB_WR_i : std_logic; signal nIDE_RD_i : std_logic; signal nIDE_WR_i : std_logic; + signal fb_ad_in : std_logic_vector(31 downto 0); + signal fb_ad_out : std_logic_vector(31 downto 0); component altpll_reconfig1 port @@ -491,7 +493,8 @@ begin CLK_VIDEO => CLK_VIDEO, VR_BUSY => VR_BUSY, DDRCLK => DDRCLK, - FB_AD => FB_AD, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, VD => VD, VDQS => VDQS, From f1a038e3a5171f0a17416180047d824111d7ac1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 11:48:10 +0000 Subject: [PATCH 104/127] finally fixed multiple drivers problem --- FPGA_Quartus_13.1/DSP/DSP.vhd | 8 +- .../FalconIO_SDCard_IDE_CF.vhd | 137 +-- .../Interrupt_Handler/interrupt_handler.vhd | 155 +-- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 100 +- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 30 +- FPGA_Quartus_13.1/Video/video.vhd | 926 +++++++++--------- .../Video/video_mod_mux_clutctr.vhd | 94 +- FPGA_Quartus_13.1/firebee1.vhd | 46 +- FPGA_Quartus_13.1/firebee_utils_pkg.vhd | 171 ---- 9 files changed, 760 insertions(+), 907 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebee_utils_pkg.vhd diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 22ae2ee..2873ce7 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -49,7 +49,8 @@ ENTITY dsp IS nSROE : OUT std_logic; DSP_INT : OUT std_logic; DSP_TA : OUT std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0); IO : INOUT std_logic_vector(17 DOWNTO 0); SRD : INOUT std_logic_vector(15 DOWNTO 0) ); @@ -72,6 +73,7 @@ BEGIN DSP_INT <= '0'; DSP_TA <= '0'; IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); - SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + SRD(15 DOWNTO 0) <= fb_ad_in(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE (others => 'Z'); + -- fb_ad_out(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z'); + fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index 2529551..78e8ae2 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -130,7 +130,8 @@ ENTITY falconio_sdcard_ide_cf IS WR_DATA : OUT std_logic; WR_GATE : OUT std_logic; DMA_DRQ : OUT std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0); LP_D : INOUT std_logic_vector(7 DOWNTO 0); SND_A : INOUT std_logic_vector(7 downto 0); ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); @@ -302,11 +303,11 @@ BEGIN nDREQ0 <= '0'; -- input daten halten - p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0)) + p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, fb_ad_in(31 DOWNTO 16), FB_ADI(15 DOWNTO 0)) BEGIN IF rising_edge(MAIN_CLK) THEN IF nFB_WR = '0' THEN - FB_ADI <= FB_AD(31 downto 16); + FB_ADI <= fb_ad_in(31 downto 16); ELSE FB_ADI <= FB_ADI; END IF; @@ -403,9 +404,9 @@ BEGIN wrusedw => RDF_AZ ); FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY - FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY + FCF_APH <= '1' WHEN FB_ALE = '1' AND fb_ad_in(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE - FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' + fb_ad_out <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; @@ -413,7 +414,7 @@ BEGIN WRF: dcfifo1 PORT MAP( aclr => CLR_FIFO, - data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), + data => fb_ad_in(7 DOWNTO 0) & fb_ad_in(15 DOWNTO 8) & fb_ad_in(23 DOWNTO 16) & fb_ad_in(31 DOWNTO 24), rdclk => FDC_CLK, rdreq => WRF_RDE, wrclk => MAIN_CLK, @@ -423,7 +424,7 @@ BEGIN ); CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG - FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' + fb_ad_out <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; @@ -581,9 +582,9 @@ BEGIN CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); - FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z'); - FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE + fb_ad_out(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z'); + fb_ad_out(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- WDC BSL REGISTER ------------------------------------------------------- @@ -593,7 +594,7 @@ BEGIN WDC_BSL <= "00"; ELSIF rising_edge(MAIN_CLK) AND WDC_BSL_CS = '1' AND nFB_WR = '0' THEN IF FB_B0 = '1' THEN - WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + WDC_BSL(1 DOWNTO 0) <= fb_ad_in(25 DOWNTO 24); ELSE WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); END IF; @@ -606,12 +607,12 @@ BEGIN DMA_MODUS <= x"0000"; ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '1' AND nFB_WR = '0' THEN IF FB_B0 = '1' THEN - DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24); + DMA_MODUS(15 DOWNTO 8) <= fb_ad_in(31 DOWNTO 24); ELSE DMA_MODUS(15 DOWNTO 8) <= DMA_MODUS(15 DOWNTO 8); END IF; IF FB_B1 = '1' THEN - DMA_MODUS(7 DOWNTO 0) <= FB_AD(23 DOWNTO 16); + DMA_MODUS(7 DOWNTO 0) <= fb_ad_in(23 DOWNTO 16); ELSE DMA_MODUS(7 DOWNTO 0) <= DMA_MODUS(7 DOWNTO 0); END IF; @@ -626,16 +627,16 @@ BEGIN DMA_BYT_CNT <= x"00000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); + DMA_BYT_CNT(16 DOWNTO 9) <= fb_ad_in(23 DOWNTO 16); DMA_BYT_CNT(8 downto 0) <= "000000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN - DMA_BYT_CNT <= FB_AD; + DMA_BYT_CNT <= fb_ad_in; ELSE DMA_BYT_CNT <= DMA_BYT_CNT; END IF; END PROCESS; -------------------------------------------------------------------- - FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; + fb_ad_out(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; DMA_STATUS(0) <= '1'; -- DMA OK DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0'; @@ -660,7 +661,7 @@ BEGIN IF nRSTO = '0' THEN DMA_TOP <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_TOP_CS = '1' OR DMA_ADR_CS = '1') THEN - DMA_TOP <= FB_AD(31 DOWNTO 24); + DMA_TOP <= fb_ad_in(31 DOWNTO 24); ELSE DMA_TOP <= DMA_TOP; END IF; @@ -670,7 +671,7 @@ BEGIN IF nRSTO = '0' THEN DMA_HIGH <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_HIGH_CS = '1' OR DMA_ADR_CS = '1') THEN - DMA_HIGH <= FB_AD(23 DOWNTO 16); + DMA_HIGH <= fb_ad_in(23 DOWNTO 16); ELSE DMA_HIGH <= DMA_HIGH; END IF; @@ -682,9 +683,9 @@ BEGIN DMA_MID <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN IF DMA_MID_CS = '1' THEN - DMA_MID <= FB_AD(23 DOWNTO 16); + DMA_MID <= fb_ad_in(23 DOWNTO 16); ELSIF DMA_ADR_CS = '1' THEN - DMA_MID <= FB_AD(15 DOWNTO 8); + DMA_MID <= fb_ad_in(15 DOWNTO 8); END IF; END IF; END PROCESS; @@ -695,9 +696,9 @@ BEGIN DMA_LOW <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN IF DMA_LOW_CS = '1'THEN - DMA_LOW <= FB_AD(23 DOWNTO 16); + DMA_LOW <= fb_ad_in(23 DOWNTO 16); ELSIF DMA_ADR_CS = '1' THEN - DMA_LOW <= FB_AD(7 DOWNTO 0); + DMA_LOW <= fb_ad_in(7 DOWNTO 0); END IF; END IF; END PROCESS; @@ -707,18 +708,18 @@ BEGIN DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 - FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; -- DIRECTZUGRIFF DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG - FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + fb_ad_out <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + fb_ad_out(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + fb_ad_out <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -- DMA RW TOGGLE ------------------------------------------ PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) @@ -840,8 +841,8 @@ BEGIN ); ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL // - FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE - DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE + DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE (others => 'Z'); -- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------ PROCESS(CLK2M, AMKB_RX, AMKB_REG) @@ -916,7 +917,7 @@ BEGIN DTACKn => DTACK_OUT_MFPn, -- Data and Adresses: RS => FB_ADR(5 DOWNTO 1), - DATA_IN => FB_AD(23 DOWNTO 16), + DATA_IN => fb_ad_in(23 DOWNTO 16), DATA_OUT => DATA_OUT_MFP, -- DATA_EN => DATA_EN_MFP, GPIP_IN(7) => NOT DMA_DRQ_Q, @@ -957,10 +958,10 @@ BEGIN MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; - FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ"; - FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; + fb_ad_out(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (others => 'Z'); DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE '0' WHEN FDINT = '1' ELSE '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; @@ -1000,7 +1001,7 @@ BEGIN SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0'; - FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (others => 'Z'); nnIDE_RES <= SND_A_X(7); LP_DIR_X <= SND_A_X(6); @@ -1012,7 +1013,7 @@ BEGIN DSA_D <= SND_A_X(1); nSDSEL <= SND_A_X(0); SND_A <= SND_A_X; - LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ"; + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (others => 'Z'); LP_DIR <= LP_DIR_X; @@ -1027,143 +1028,143 @@ BEGIN IF nRSTO = '0' THEN sndmactl <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN - sndmactl <= FB_AD(23 DOWNTO 16); + sndmactl <= fb_ad_in(23 DOWNTO 16); ELSE sndmactl <= sndmactl; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) begin IF nRSTO = '0' THEN sndbashi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN - sndbashi <= FB_AD(23 DOWNTO 16); + sndbashi <= fb_ad_in(23 DOWNTO 16); ELSE sndbashi <= sndbashi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndbasmi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN - sndbasmi <= FB_AD(23 DOWNTO 16); + sndbasmi <= fb_ad_in(23 DOWNTO 16); ELSE sndbasmi <= sndbasmi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndbaslo <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN - sndbaslo <= FB_AD(23 DOWNTO 16); + sndbaslo <= fb_ad_in(23 DOWNTO 16); ELSE sndbaslo <= sndbaslo; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndadrhi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN - sndadrhi <= FB_AD(23 DOWNTO 16); + sndadrhi <= fb_ad_in(23 DOWNTO 16); ELSE sndadrhi <= sndadrhi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndadrmi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN - sndadrmi <= FB_AD(23 DOWNTO 16); + sndadrmi <= fb_ad_in(23 DOWNTO 16); ELSE sndadrmi <= sndadrmi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndadrlo <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN - sndadrlo <= FB_AD(23 DOWNTO 16); + sndadrlo <= fb_ad_in(23 DOWNTO 16); ELSE sndadrlo <= sndadrlo; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndendhi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN - sndendhi <= FB_AD(23 DOWNTO 16); + sndendhi <= fb_ad_in(23 DOWNTO 16); ELSE sndendhi <= sndendhi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndendmi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN - sndendmi <= FB_AD(23 DOWNTO 16); + sndendmi <= fb_ad_in(23 DOWNTO 16); ELSE sndendmi <= sndendmi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndendlo <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN - sndendlo <= FB_AD(23 DOWNTO 16); + sndendlo <= fb_ad_in(23 DOWNTO 16); ELSE sndendlo <= sndendlo; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndmode <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN - sndmode <= FB_AD(23 DOWNTO 16); + sndmode <= fb_ad_in(23 DOWNTO 16); ELSE sndmode <= sndmode; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE (others => 'Z'); ---------------------------------------------------------------------------- -- Paddle @@ -1171,13 +1172,13 @@ BEGIN paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F - FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + fb_ad_out(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE (others => 'Z'); END rtl; diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 52c8703..1fce052 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -174,7 +174,8 @@ ENTITY interrupt_handler IS INT_HANDLER_TA : BUFFER std_logic; ACP_CONF : BUFFER std_logic_vector(31 DOWNTO 0); TIN0 : BUFFER std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0) ); END interrupt_handler; @@ -5100,7 +5101,7 @@ BEGIN -- $10000/4 INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; - INT_CTR_d <= FB_AD; + INT_CTR_d <= fb_ad_in; INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR); @@ -5115,7 +5116,7 @@ BEGIN -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = -- "00000000000100000000000001"); - INT_ENA_d <= FB_AD; + INT_ENA_d <= fb_ad_in; INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR); @@ -5127,13 +5128,13 @@ BEGIN -- $10008/4 int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0'; -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010"); - INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(15 DOWNTO 8) <= FB_AD(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(7 DOWNTO 0) <= FB_AD(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and + INT_CLEAR_d(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); -- INTERRUPT LATCH REGISTER READ ONLY @@ -5341,7 +5342,7 @@ BEGIN -- $4'0000/4 ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000010000000000000000"); - ACP_CONF_d <= FB_AD; + ACP_CONF_d <= fb_ad_in; ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR); ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR); ACP_CONF8_ena_ctrl <= ACP_CONF_CS and FB_B(2) and (not nFB_WR); @@ -5352,7 +5353,7 @@ BEGIN -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR -- -------------------------------------------------------- RTC_ADR0_clk_ctrl <= MAIN_CLK; - RTC_ADR_d <= FB_AD(21 DOWNTO 16); + RTC_ADR_d <= fb_ad_in(21 DOWNTO 16); -- FFFF8961 UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110000") and FB_B(1); @@ -5370,210 +5371,210 @@ BEGIN WERTE0_0_clk_ctrl <= MAIN_CLK; (WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1, WERTE3_0_d_1, - WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(1), WERTE6_d(1), WERTE5_d(1), WERTE4_d(1), WERTE3_d(1), - WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1, WERTE3_2_d_1, - WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(3), WERTE6_d(3), WERTE5_d(3), WERTE4_d(3), WERTE3_d(3), - WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1, WERTE3_4_d_1, - WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(5), WERTE6_d(5), WERTE5_d(5), WERTE4_d(5), WERTE3_d(5), - WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1, WERTE3_6_d_1, - WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1, WERTE3_7_d_1, - WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1, WERTE3_8_d_1, - WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1, WERTE3_9_d_1, - WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(10), WERTE6_d(10), WERTE5_d(10), WERTE4_d(10), WERTE3_d(10), - WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(11), WERTE6_d(11), WERTE5_d(11), WERTE4_d(11), WERTE3_d(11), - WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= FB_AD(23 DOWNTO 16); + WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(12), WERTE6_d(12), WERTE5_d(12), WERTE4_d(12), WERTE3_d(12), - WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_13_d_1, WERTE6_d(13), WERTE5_d(13), WERTE4_d(13), WERTE3_d(13), - WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= FB_AD(23 DOWNTO 16); + WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(14), WERTE6_d(14), WERTE5_d(14), WERTE4_d(14), WERTE3_d(14), - WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(15), WERTE6_d(15), WERTE5_d(15), WERTE4_d(15), WERTE3_d(15), - WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(16), WERTE6_d(16), WERTE5_d(16), WERTE4_d(16), WERTE3_d(16), - WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(17), WERTE6_d(17), WERTE5_d(17), WERTE4_d(17), WERTE3_d(17), - WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(18), WERTE6_d(18), WERTE5_d(18), WERTE4_d(18), WERTE3_d(18), - WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(19), WERTE6_d(19), WERTE5_d(19), WERTE4_d(19), WERTE3_d(19), - WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(20), WERTE6_d(20), WERTE5_d(20), WERTE4_d(20), WERTE3_d(20), - WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(21), WERTE6_d(21), WERTE5_d(21), WERTE4_d(21), WERTE3_d(21), - WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(22), WERTE6_d(22), WERTE5_d(22), WERTE4_d(22), WERTE3_d(22), - WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(23), WERTE6_d(23), WERTE5_d(23), WERTE4_d(23), WERTE3_d(23), - WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(24), WERTE6_d(24), WERTE5_d(24), WERTE4_d(24), WERTE3_d(24), - WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(25), WERTE6_d(25), WERTE5_d(25), WERTE4_d(25), WERTE3_d(25), - WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(26), WERTE6_d(26), WERTE5_d(26), WERTE4_d(26), WERTE3_d(26), - WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(27), WERTE6_d(27), WERTE5_d(27), WERTE4_d(27), WERTE3_d(27), - WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(28), WERTE6_d(28), WERTE5_d(28), WERTE4_d(28), WERTE3_d(28), - WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(29), WERTE6_d(29), WERTE5_d(29), WERTE4_d(29), WERTE3_d(29), - WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(30), WERTE6_d(30), WERTE5_d(30), WERTE4_d(30), WERTE3_d(30), - WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(31), WERTE6_d(31), WERTE5_d(31), WERTE4_d(31), WERTE3_d(31), - WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(32), WERTE6_d(32), WERTE5_d(32), WERTE4_d(32), WERTE3_d(32), - WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(33), WERTE6_d(33), WERTE5_d(33), WERTE4_d(33), WERTE3_d(33), - WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(34), WERTE6_d(34), WERTE5_d(34), WERTE4_d(34), WERTE3_d(34), - WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(35), WERTE6_d(35), WERTE5_d(35), WERTE4_d(35), WERTE3_d(35), - WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(36), WERTE6_d(36), WERTE5_d(36), WERTE4_d(36), WERTE3_d(36), - WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(37), WERTE6_d(37), WERTE5_d(37), WERTE4_d(37), WERTE3_d(37), - WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(38), WERTE6_d(38), WERTE5_d(38), WERTE4_d(38), WERTE3_d(38), - WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(39), WERTE6_d(39), WERTE5_d(39), WERTE4_d(39), WERTE3_d(39), - WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(40), WERTE6_d(40), WERTE5_d(40), WERTE4_d(40), WERTE3_d(40), - WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(41), WERTE6_d(41), WERTE5_d(41), WERTE4_d(41), WERTE3_d(41), - WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(42), WERTE6_d(42), WERTE5_d(42), WERTE4_d(42), WERTE3_d(42), - WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(43), WERTE6_d(43), WERTE5_d(43), WERTE4_d(43), WERTE3_d(43), - WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(44), WERTE6_d(44), WERTE5_d(44), WERTE4_d(44), WERTE3_d(44), - WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(45), WERTE6_d(45), WERTE5_d(45), WERTE4_d(45), WERTE3_d(45), - WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(46), WERTE6_d(46), WERTE5_d(46), WERTE4_d(46), WERTE3_d(46), - WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(47), WERTE6_d(47), WERTE5_d(47), WERTE4_d(47), WERTE3_d(47), - WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(48), WERTE6_d(48), WERTE5_d(48), WERTE4_d(48), WERTE3_d(48), - WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(49), WERTE6_d(49), WERTE5_d(49), WERTE4_d(49), WERTE3_d(49), - WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(50), WERTE6_d(50), WERTE5_d(50), WERTE4_d(50), WERTE3_d(50), - WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(51), WERTE6_d(51), WERTE5_d(51), WERTE4_d(51), WERTE3_d(51), - WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(52), WERTE6_d(52), WERTE5_d(52), WERTE4_d(52), WERTE3_d(52), - WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(53), WERTE6_d(53), WERTE5_d(53), WERTE4_d(53), WERTE3_d(53), - WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(54), WERTE6_d(54), WERTE5_d(54), WERTE4_d(54), WERTE3_d(54), - WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(55), WERTE6_d(55), WERTE5_d(55), WERTE4_d(55), WERTE3_d(55), - WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(56), WERTE6_d(56), WERTE5_d(56), WERTE4_d(56), WERTE3_d(56), - WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(57), WERTE6_d(57), WERTE5_d(57), WERTE4_d(57), WERTE3_d(57), - WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(58), WERTE6_d(58), WERTE5_d(58), WERTE4_d(58), WERTE3_d(58), - WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(59), WERTE6_d(59), WERTE5_d(59), WERTE4_d(59), WERTE3_d(59), - WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(60), WERTE6_d(60), WERTE5_d(60), WERTE4_d(60), WERTE3_d(60), - WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(61), WERTE6_d(61), WERTE5_d(61), WERTE4_d(61), WERTE3_d(61), - WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(62), WERTE6_d(62), WERTE5_d(62), WERTE4_d(62), WERTE3_d(62), - WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(63), WERTE6_d(63), WERTE5_d(63), WERTE4_d(63), WERTE3_d(63), - WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1, WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1) <= @@ -6008,7 +6009,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(31 DOWNTO 24)); u0_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(31 DOWNTO 24) <= u0_tridata; + fb_ad_out(31 DOWNTO 24) <= u0_tridata; u1_data <= (std_logic_vector'(WERTE7_q(0) & WERTE6_q(0) & WERTE5_q(0) & WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & WERTE1_q(0) & WERTE0_q(0)) and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8)) @@ -6227,7 +6228,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(23 DOWNTO 16)); u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(23 DOWNTO 16) <= u1_tridata; + fb_ad_out(23 DOWNTO 16) <= u1_tridata; u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 DOWNTO 8)) or (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 DOWNTO 8)) or (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 DOWNTO 8)) or @@ -6235,7 +6236,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(15 DOWNTO 8)); u2_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(15 DOWNTO 8) <= u2_tridata; + fb_ad_out(15 DOWNTO 8) <= u2_tridata; u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 DOWNTO 0)) or (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 DOWNTO 0)) or (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 DOWNTO 0)) or @@ -6243,7 +6244,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(7 DOWNTO 0)); u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(7 DOWNTO 0) <= u3_tridata; + fb_ad_out(7 DOWNTO 0) <= u3_tridata; INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs; diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index f42df9b..eedb5e0 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -1,73 +1,47 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Fri Oct 16 15:40:59 2009 - library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; entity blitter is - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT + port ( - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_ON : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - DDRCLK0 : IN std_logic; - BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); - BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); - SR_BLITTER_DACK : IN std_logic; - BLITTER_RUN : OUT std_logic; - BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0); - BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); - BLITTER_SIG : OUT std_logic; - BLITTER_WR : OUT std_logic; - blitter_ta : OUT std_logic; - fb_ad_in : in std_logic_vector(31 DOWNTO 0); + nRSTO : in std_logic; + MAIN_CLK : in std_logic; + FB_ALE : in std_logic; + nFB_WR : in std_logic; + nFB_OE : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + VIDEO_RAM_CTR : in std_logic_vector(15 downto 0); + BLITTER_ON : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + DDRCLK0 : in std_logic; + BLITTER_DIN : in std_logic_vector(127 downto 0); + BLITTER_DACK : in std_logic_vector(4 downto 0); + SR_BLITTER_DACK : in std_logic; + blitter_run : out std_logic; + blitter_dout : out std_logic_vector(127 downto 0); + blitter_adr : out std_logic_vector(31 downto 0); + blitter_sig : out std_logic; + blitter_wr : out std_logic; + blitter_ta : out std_logic; + fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0) ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END BLITTER; +end BLITTER; -ARCHITECTURE rtl OF blitter IS +architecture rtl of blitter is - -BEGIN - BLITTER_RUN <= '0'; - BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; - BLITTER_ADR <= x"76543210"; - BLITTER_SIG <= '0'; - BLITTER_WR <= '0'; +begin + blitter_run <= '0'; + blitter_dout <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + blitter_adr <= x"76543210"; + blitter_sig <= '0'; + blitter_wr <= '0'; blitter_ta <= '0'; - -END rtl; + fb_ad_out <= (others => 'Z'); +end rtl; diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 907266f..321e14c 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -1384,17 +1384,25 @@ begin "00000" & video_act_adr(26 downto 24) when video_cnt_h and not nfb_oe else (others => 'Z'); - u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or - (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or - (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or - (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or - (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or - (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); - u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L - or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt; - - +-- u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or +-- (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or +-- (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or +-- (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or +-- (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or +-- (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); +-- u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L +-- or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); +-- fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt else (others => 'Z'); + + fb_ad_out(23 downto 16) <= video_base_l_d_q when video_base_l and not nfb_oe else + video_base_m_d_q when video_base_m and not nfb_oe else + video_base_h_d_q when video_base_h and not nfb_oe else + video_act_adr(7 downto 0) when video_cnt_l and not nfb_oe else + video_act_adr(15 downto 8) when video_cnt_m and not nfb_oe else + video_act_adr(23 downto 16) when video_cnt_h and not nfb_oe else + (others => 'Z'); + fb_ad_out(15 downto 0) <= (others => 'Z'); + -- Assignments added to explicitly combine the -- effects of multiple drivers in the source FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 17e6fcd..0ab7374 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -1,229 +1,248 @@ --- Copyright (C) 1991-2014 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://firebee.org ---- +---- ---- +---- Description: ---- +---- This package contains utility functions, procedures and constants +---- for the Firebee project. +---- +---- Author(s): ---- +---- Fredi Aschwanden +---- Markus Fröschle, mfro@mubf.de +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2015 Markus Fröschle & the FireBee project +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- --- PROGRAM "Quartus II 64-Bit" --- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" --- CREATED "Mon Jan 11 09:20:56 2016" +library ieee; +use ieee.std_logic_1164.all; -LIBRARY ieee; - USE ieee.std_logic_1164.all; +library work; -LIBRARY work; - -ENTITY video IS - PORT +entity video is + port ( - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - nFB_OE : IN std_logic; - FB_ALE : IN std_logic; - DDR_SYNC_66M : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_BUSY : IN std_logic; - DDRCLK : IN std_logic_vector(3 DOWNTO 0); - fb_ad_in : in std_logic_vector(31 DOWNTO 0); + MAIN_CLK : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_WR : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nRSTO : in std_logic; + nFB_OE : in std_logic; + FB_ALE : in std_logic; + DDR_SYNC_66M : in std_logic; + CLK33M : in std_logic; + CLK25M : in std_logic; + CLK_VIDEO : in std_logic; + VR_BUSY : in std_logic; + ddrclk : in std_logic_vector(3 downto 0); + fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0); - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - VR_D : IN std_logic_vector(8 DOWNTO 0); - nBLANK : OUT std_logic; - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - nPD_VGA : OUT std_logic; - VCKE : OUT std_logic; - VSYNC : OUT std_logic; - HSYNC : OUT std_logic; - nSYNC : OUT std_logic; - VIDEO_TA : OUT std_logic; - PIXEL_CLK : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - VA : OUT std_logic_vector(12 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VDM : OUT std_logic_vector(3 DOWNTO 0); - VG : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0) + FB_ADR : in std_logic_vector(31 downto 0); + VD : inout std_logic_vector(31 downto 0); + vdqs : inout std_logic_vector(3 downto 0); + VR_D : in std_logic_vector(8 downto 0); + nBLANK : out std_logic; + nVWE : out std_logic; + nVCAS : out std_logic; + nVRAS : out std_logic; + nVCS : out std_logic; + nPD_VGA : out std_logic; + VCKE : out std_logic; + VSYNC : out std_logic; + HSYNC : out std_logic; + nSYNC : out std_logic; + VIDEO_TA : out std_logic; + pixel_clk : out std_logic; + VIDEO_RECONFIG : out std_logic; + VR_WR : out std_logic; + VR_RD : out std_logic; + BA : out std_logic_vector(1 downto 0); + VA : out std_logic_vector(12 downto 0); + VB : out std_logic_vector(7 downto 0); + VDM : out std_logic_vector(3 downto 0); + VG : out std_logic_vector(7 downto 0); + VR : out std_logic_vector(7 downto 0) ); -END video; +end video; ARCHITECTURE rtl OF video IS - ATTRIBUTE black_box : BOOLEAN; - ATTRIBUTE noopt : BOOLEAN; - SIGNAL ACP_CLUT_RD : std_logic; - SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); - SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_ON : std_logic; - SIGNAL BLITTER_RUN : std_logic; - SIGNAL BLITTER_SIG : std_logic; - SIGNAL BLITTER_TA : std_logic; - SIGNAL BLITTER_WR : std_logic; - SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); - SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); - SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); - SIGNAL CCA : std_logic_vector(23 DOWNTO 0); - SIGNAL CCF : std_logic_vector(23 DOWNTO 0); - SIGNAL CCS : std_logic_vector(23 DOWNTO 0); - SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); - SIGNAL CLR_FIFO : std_logic; - SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); - SIGNAL CLUT_ADR1A : std_logic; - SIGNAL CLUT_ADR2A : std_logic; - SIGNAL CLUT_ADR3A : std_logic; - SIGNAL CLUT_ADR4A : std_logic; - SIGNAL CLUT_ADR5A : std_logic; - SIGNAL CLUT_ADR6A : std_logic; - SIGNAL CLUT_ADR7A : std_logic; - SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); - SIGNAL COLOR1 : std_logic; - SIGNAL COLOR2 : std_logic; - SIGNAL COLOR4 : std_logic; - SIGNAL COLOR8 : std_logic; - SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); - SIGNAL DDR_WR : std_logic; - SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); - SIGNAL DOP_FIFO_CLR : std_logic; - SIGNAL FALCON_CLUT_RDH : std_logic; - SIGNAL FALCON_CLUT_RDL : std_logic; - SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); - SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); - SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); - SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); - SIGNAL FIFO_RDE : std_logic; - SIGNAL FIFO_WRE : std_logic; - SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic := '0'; - SIGNAL pixel_clk_i : std_logic; - SIGNAL SR_BLITTER_DACK : std_logic; - SIGNAL SR_DDR_FB : std_logic; - SIGNAL SR_DDR_WR : std_logic; - SIGNAL SR_DDRWR_D_SEL : std_logic; - SIGNAL SR_FIFO_WRE : std_logic; - SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL ST_CLUT_RD : std_logic; - SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); - SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); - SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL VDOUT_OE : std_logic; - SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); - SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); - SIGNAL VDR : std_logic_vector(31 DOWNTO 0); - SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); - SIGNAL VIDEO_DDR_TA : std_logic; - SIGNAL VIDEO_MOD_TA : std_logic; - SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); - SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); - SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_0 : std_logic; - SIGNAL SYNTHESIZED_WIRE_1 : std_logic; - SIGNAL SYNTHESIZED_WIRE_2 : std_logic; - SIGNAL SYNTHESIZED_WIRE_3 : std_logic; - SIGNAL SYNTHESIZED_WIRE_4 : std_logic; - SIGNAL SYNTHESIZED_WIRE_5 : std_logic; - SIGNAL SYNTHESIZED_WIRE_60 : std_logic; - SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); - SIGNAL DFF_inst93 : std_logic; - SIGNAL SYNTHESIZED_WIRE_8 : std_logic; - SIGNAL SYNTHESIZED_WIRE_9 : std_logic; - SIGNAL SYNTHESIZED_WIRE_61 : std_logic; - SIGNAL SYNTHESIZED_WIRE_11 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_12 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_13 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_14 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_15 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_16 : std_logic; - SIGNAL SYNTHESIZED_WIRE_18 : std_logic; - SIGNAL SYNTHESIZED_WIRE_19 : std_logic; - SIGNAL SYNTHESIZED_WIRE_20 : std_logic; - SIGNAL SYNTHESIZED_WIRE_21 : std_logic; - SIGNAL SYNTHESIZED_WIRE_22 : std_logic; - SIGNAL SYNTHESIZED_WIRE_23 : std_logic; - SIGNAL SYNTHESIZED_WIRE_24 : std_logic; - SIGNAL SYNTHESIZED_WIRE_25 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_26 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_62 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_29 : std_logic_vector(2 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_30 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_31 : std_logic_vector(2 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_32 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_33 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_34 : std_logic_vector(2 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_63 : std_logic_vector(127 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_36 : std_logic_vector(127 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_38 : std_logic; - SIGNAL SYNTHESIZED_WIRE_40 : std_logic; - SIGNAL SYNTHESIZED_WIRE_41 : std_logic_vector(5 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_42 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_43 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_44 : std_logic_vector(5 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_45 : std_logic_vector(5 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_46 : std_logic; - SIGNAL SYNTHESIZED_WIRE_47 : std_logic_vector(6 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_48 : std_logic_vector(31 DOWNTO 0); - SIGNAL DFF_inst91 : std_logic; - SIGNAL SYNTHESIZED_WIRE_64 : std_logic; - SIGNAL SYNTHESIZED_WIRE_49 : std_logic; - SIGNAL SYNTHESIZED_WIRE_50 : std_logic; - SIGNAL SYNTHESIZED_WIRE_51 : std_logic; - SIGNAL SYNTHESIZED_WIRE_52 : std_logic; - SIGNAL SYNTHESIZED_WIRE_53 : std_logic; - SIGNAL SYNTHESIZED_WIRE_54 : std_logic; - SIGNAL SYNTHESIZED_WIRE_65 : std_logic_vector(23 DOWNTO 0); + attribute black_box : BOOLEAN; + attribute noopt : BOOLEAN; + signal ACP_CLUT_RD : std_logic; + signal ACP_CLUT_WR : std_logic_vector(3 downto 0); + signal BLITTER_ADR : std_logic_vector(31 downto 0); + signal blitter_dack : std_logic_vector(4 downto 0); + signal blitter_din : std_logic_vector(127 downto 0); + signal BLITTER_DOUT : std_logic_vector(127 downto 0); + signal BLITTER_ON : std_logic; + signal BLITTER_RUN : std_logic; + signal BLITTER_SIG : std_logic; + signal BLITTER_TA : std_logic; + signal BLITTER_WR : std_logic; + signal BORDER_COLOR : std_logic_vector(23 downto 0); + signal CC16 : std_logic_vector(23 downto 0); + signal CC24 : std_logic_vector(31 downto 0); + signal CCA : std_logic_vector(23 downto 0); + signal ccf : std_logic_vector(23 downto 0); + signal CCS : std_logic_vector(23 downto 0); + signal CCSEL : std_logic_vector(2 downto 0); + signal CLR_FIFO : std_logic; + signal clut_adr : std_logic_vector(7 downto 0); + signal CLUT_ADR1A : std_logic; + signal CLUT_ADR2A : std_logic; + signal CLUT_ADR3A : std_logic; + signal CLUT_ADR4A : std_logic; + signal CLUT_ADR5A : std_logic; + signal CLUT_ADR6A : std_logic; + signal CLUT_ADR7A : std_logic; + signal CLUT_MUX_ADR : std_logic_vector(3 downto 0); + signal CLUT_OFF : std_logic_vector(3 downto 0); + signal color1 : std_logic; + signal color2 : std_logic; + signal color4 : std_logic; + signal color8 : std_logic; + signal DDR_FB : std_logic_vector(4 downto 0); + signal ddr_wr : std_logic; + signal ddrwr_d_sel : std_logic_vector(1 downto 0); + signal DOP_FIFO_CLR : std_logic; + signal FALCON_CLUT_RDH : std_logic; + signal FALCON_CLUT_RDL : std_logic; + signal FALCON_CLUT_WR : std_logic_vector(3 downto 0); + signal FB_DDR : std_logic_vector(127 downto 0); + signal FB_LE : std_logic_vector(3 downto 0); + signal FB_VDOE : std_logic_vector(3 downto 0); + signal FIFO_D : std_logic_vector(127 downto 0); + signal FIFO_MW : std_logic_vector(8 downto 0); + signal FIFO_RDE : std_logic; + signal FIFO_WRE : std_logic; + signal INTER_ZEI : std_logic; + signal nFB_BURST : std_logic := '0'; + signal pixel_clk_i : std_logic; + signal SR_BLITTER_DACK : std_logic; + signal SR_DDR_FB : std_logic; + signal sr_ddr_wr : std_logic; + signal SR_DDRWR_D_SEL : std_logic; + signal SR_FIFO_WRE : std_logic; + signal SR_VDMP : std_logic_vector(7 downto 0); + signal ST_CLUT_RD : std_logic; + signal ST_CLUT_WR : std_logic_vector(1 downto 0); + signal VDM_SEL : std_logic_vector(3 downto 0); + signal VDMA : std_logic_vector(127 downto 0); + signal VDMB : std_logic_vector(127 downto 0); + signal VDMC : std_logic_vector(127 downto 0); + signal VDMP : std_logic_vector(7 downto 0); + signal vdout_oe : std_logic; + signal VDP_IN : std_logic_vector(63 downto 0); + signal VDP_OUT : std_logic_vector(63 downto 0); + signal VDR : std_logic_vector(31 downto 0); + signal vdvz : std_logic_vector(127 downto 0); + signal VIDEO_DDR_TA : std_logic; + signal VIDEO_MOD_TA : std_logic; + signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0); + signal ZR_C8 : std_logic_vector(7 downto 0); + signal ZR_C8B : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_0 : std_logic; + signal SYNTHESIZED_WIRE_1 : std_logic; + signal SYNTHESIZED_WIRE_2 : std_logic; + signal SYNTHESIZED_WIRE_3 : std_logic; + signal SYNTHESIZED_WIRE_4 : std_logic; + signal SYNTHESIZED_WIRE_5 : std_logic; + signal SYNTHESIZED_WIRE_60 : std_logic; + signal SYNTHESIZED_WIRE_7 : std_logic_vector(15 downto 0); + signal DFF_inst93 : std_logic; + signal SYNTHESIZED_WIRE_8 : std_logic; + signal SYNTHESIZED_WIRE_9 : std_logic; + signal SYNTHESIZED_WIRE_61 : std_logic; + signal SYNTHESIZED_WIRE_11 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_12 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_13 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_14 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_15 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_16 : std_logic; + signal SYNTHESIZED_WIRE_18 : std_logic; + signal SYNTHESIZED_WIRE_19 : std_logic; + signal SYNTHESIZED_WIRE_20 : std_logic; + signal SYNTHESIZED_WIRE_21 : std_logic; + signal SYNTHESIZED_WIRE_22 : std_logic; + signal SYNTHESIZED_WIRE_23 : std_logic; + signal SYNTHESIZED_WIRE_24 : std_logic; + signal SYNTHESIZED_WIRE_25 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_26 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_62 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_29 : std_logic_vector(2 downto 0); + signal SYNTHESIZED_WIRE_30 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_31 : std_logic_vector(2 downto 0); + signal SYNTHESIZED_WIRE_32 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_33 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_34 : std_logic_vector(2 downto 0); + signal SYNTHESIZED_WIRE_63 : std_logic_vector(127 downto 0); + signal SYNTHESIZED_WIRE_36 : std_logic_vector(127 downto 0); + signal SYNTHESIZED_WIRE_38 : std_logic; + signal SYNTHESIZED_WIRE_40 : std_logic; + signal SYNTHESIZED_WIRE_41 : std_logic_vector(5 downto 0); + signal SYNTHESIZED_WIRE_42 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_43 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_44 : std_logic_vector(5 downto 0); + signal SYNTHESIZED_WIRE_45 : std_logic_vector(5 downto 0); + signal SYNTHESIZED_WIRE_46 : std_logic; + signal SYNTHESIZED_WIRE_47 : std_logic_vector(6 downto 0); + signal SYNTHESIZED_WIRE_48 : std_logic_vector(31 downto 0); + signal DFF_inst91 : std_logic; + signal SYNTHESIZED_WIRE_64 : std_logic; + signal SYNTHESIZED_WIRE_49 : std_logic; + signal SYNTHESIZED_WIRE_50 : std_logic; + signal SYNTHESIZED_WIRE_51 : std_logic; + signal SYNTHESIZED_WIRE_52 : std_logic; + signal SYNTHESIZED_WIRE_53 : std_logic; + signal SYNTHESIZED_WIRE_54 : std_logic; + signal SYNTHESIZED_WIRE_65 : std_logic_vector(23 downto 0); - SIGNAL GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); + signal GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 downto 0); + signal GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 downto 0); + signal GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 downto 0); -BEGIN - VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); - VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); - VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); +begin + VB(7 downto 0) <= SYNTHESIZED_WIRE_65(7 downto 0); + VG(7 downto 0) <= SYNTHESIZED_WIRE_65(15 downto 8); + VR(7 downto 0) <= SYNTHESIZED_WIRE_65(23 downto 16); SYNTHESIZED_WIRE_0 <= '0'; SYNTHESIZED_WIRE_1 <= '0'; @@ -264,21 +283,21 @@ BEGIN CC16(0) <= GDFX_TEMP_SIGNAL_16(0); - GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); - GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); - GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); - GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80)); - GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88)); - GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96)); - GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); - GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); - GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); - GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); - GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); - GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); - GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); - GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); - GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); + GDFX_TEMP_SIGNAL_15 <= (VDMB(55 downto 0) & VDMA(127 downto 56)); + GDFX_TEMP_SIGNAL_14 <= (VDMB(63 downto 0) & VDMA(127 downto 64)); + GDFX_TEMP_SIGNAL_13 <= (VDMB(71 downto 0) & VDMA(127 downto 72)); + GDFX_TEMP_SIGNAL_12 <= (VDMB(79 downto 0) & VDMA(127 downto 80)); + GDFX_TEMP_SIGNAL_11 <= (VDMB(87 downto 0) & VDMA(127 downto 88)); + GDFX_TEMP_SIGNAL_10 <= (VDMB(95 downto 0) & VDMA(127 downto 96)); + GDFX_TEMP_SIGNAL_9 <= (VDMB(103 downto 0) & VDMA(127 downto 104)); + GDFX_TEMP_SIGNAL_8 <= (VDMB(111 downto 0) & VDMA(127 downto 112)); + GDFX_TEMP_SIGNAL_7 <= (VDMB(119 downto 0) & VDMA(127 downto 120)); + GDFX_TEMP_SIGNAL_6 <= (VDMB(7 downto 0) & VDMA(127 downto 8)); + GDFX_TEMP_SIGNAL_5 <= (VDMB(15 downto 0) & VDMA(127 downto 16)); + GDFX_TEMP_SIGNAL_4 <= (VDMB(23 downto 0) & VDMA(127 downto 24)); + GDFX_TEMP_SIGNAL_3 <= (VDMB(31 downto 0) & VDMA(127 downto 32)); + GDFX_TEMP_SIGNAL_2 <= (VDMB(39 downto 0) & VDMA(127 downto 40)); + GDFX_TEMP_SIGNAL_1 <= (VDMB(47 downto 0) & VDMA(127 downto 48)); acp_clut_ram : entity work.altdpram2 @@ -288,12 +307,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_0, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), + address_a => FB_ADR(9 downto 2), address_b => ZR_C8B, - data_a => fb_ad_in(7 DOWNTO 0), - data_b => (OTHERS => '0'), + data_a => fb_ad_in(7 downto 0), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_30, - q_b => CCA(7 DOWNTO 0) + q_b => CCA(7 downto 0) ); @@ -304,12 +323,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_1, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), + address_a => FB_ADR(9 downto 2), address_b => ZR_C8B, - data_a => fb_ad_in(15 DOWNTO 8), - data_b => (OTHERS => '0'), + data_a => fb_ad_in(15 downto 8), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_32, - q_b => CCA(15 DOWNTO 8) + q_b => CCA(15 downto 8) ); @@ -320,15 +339,14 @@ BEGIN wren_b => SYNTHESIZED_WIRE_2, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), + address_a => FB_ADR(9 downto 2), address_b => ZR_C8B, - data_a => fb_ad_in(23 DOWNTO 16), - data_b => (OTHERS => '0'), + data_a => fb_ad_in(23 downto 16), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_33, - q_b => CCA(23 DOWNTO 16) + q_b => CCA(23 downto 16) ); - i_blitter : entity work.blitter port map ( @@ -343,10 +361,10 @@ BEGIN nFB_CS1 => nFB_CS1, nFB_CS2 => nFB_CS2, nFB_CS3 => nFB_CS3, - DDRCLK0 => DDRCLK(0), + DDRCLK0 => ddrclk(0), SR_BLITTER_DACK => SR_BLITTER_DACK, - BLITTER_DACK => BLITTER_DACK, - BLITTER_DIN => BLITTER_DIN, + blitter_dack => blitter_dack, + blitter_din => blitter_din, fb_ad_in => fb_ad_in, fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, @@ -357,9 +375,8 @@ BEGIN blitter_ta => blitter_ta, BLITTER_ADR => BLITTER_ADR, BLITTER_DOUT => BLITTER_DOUT - ); - - + ); + i_ddr_ctr : entity work.ddr_ctr port map ( @@ -376,7 +393,7 @@ BEGIN DDR_SYNC_66M => DDR_SYNC_66M, BLITTER_SIG => BLITTER_SIG, BLITTER_WR => BLITTER_WR, - DDRCLK0 => DDRCLK(0), + DDRCLK0 => ddrclk(0), CLK33M => CLK33M, CLR_FIFO => CLR_FIFO, BLITTER_ADR => BLITTER_ADR, @@ -392,19 +409,19 @@ BEGIN nVCAS => nVCAS, SR_FIFO_WRE => SR_FIFO_WRE, SR_DDR_FB => SR_DDR_FB, - SR_DDR_WR => SR_DDR_WR, + sr_ddr_wr => sr_ddr_wr, SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, VIDEO_DDR_TA => VIDEO_DDR_TA, SR_BLITTER_DACK => SR_BLITTER_DACK, - DDRWR_D_SEL1 => DDRWR_D_SEL(1), + DDRWR_D_SEL1 => ddrwr_d_sel(1), BA => BA, FB_LE => FB_LE, FB_VDOE => FB_VDOE, SR_VDMP => SR_VDMP, VA => VA, VDM_SEL => VDM_SEL - ); - + ); + falcon_clut_blue : entity work.altdpram1 port map @@ -413,12 +430,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_3, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => fb_ad_in(23 DOWNTO 18), - data_b => (OTHERS => '0'), + address_a => FB_ADR(9 downto 2), + address_b => clut_adr, + data_a => fb_ad_in(23 downto 18), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_45, - q_b => CCF(7 DOWNTO 2) + q_b => ccf(7 downto 2) ); @@ -429,12 +446,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_4, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => fb_ad_in(23 DOWNTO 18), - data_b => (OTHERS => '0'), + address_a => FB_ADR(9 downto 2), + address_b => clut_adr, + data_a => fb_ad_in(23 downto 18), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_44, - q_b => CCF(15 DOWNTO 10) + q_b => ccf(15 downto 10) ); @@ -445,12 +462,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_5, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => fb_ad_in(31 DOWNTO 26), - data_b => (OTHERS => '0'), + address_a => FB_ADR(9 downto 2), + address_b => clut_adr, + data_a => fb_ad_in(31 downto 26), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_41, - q_b => CCF(23 DOWNTO 18) + q_b => ccf(23 downto 18) ); @@ -458,7 +475,7 @@ BEGIN port map ( wrreq => FIFO_WRE, - wrclk => DDRCLK(0), + wrclk => ddrclk(0), rdreq => SYNTHESIZED_WIRE_60, rdclk => pixel_clk_i, aclr => CLR_FIFO, @@ -471,15 +488,15 @@ BEGIN inst1 : entity work.altddio_bidir0 port map ( - oe => VDOUT_OE, - inclock => DDRCLK(1), - outclock => DDRCLK(3), - datain_h => VDP_OUT(63 DOWNTO 32), - datain_l => VDP_OUT(31 DOWNTO 0), + oe => vdout_oe, + inclock => ddrclk(1), + outclock => ddrclk(3), + datain_h => VDP_OUT(63 downto 32), + datain_l => VDP_OUT(31 downto 0), padio => VD, combout => SYNTHESIZED_WIRE_15, - dataout_h => VDP_IN(31 DOWNTO 0), - dataout_l => VDP_IN(63 DOWNTO 32) + dataout_h => VDP_IN(31 downto 0), + dataout_l => VDP_IN(63 downto 32) ); @@ -521,18 +538,18 @@ BEGIN ( data1 => DFF_inst93, data0 => ZR_C8(0), - sel => COLOR1, + sel => color1, result => ZR_C8B(0) ); - CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; - CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; - CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; + clut_adr(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; + clut_adr(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; + clut_adr(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; - SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; - SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; + SYNTHESIZED_WIRE_61 <= color8 OR color4; + SYNTHESIZED_WIRE_16 <= color4 OR color8 OR color2; fb_ad_out <= vdr when fb_vdoe(0) else (others => 'Z'); @@ -554,9 +571,9 @@ BEGIN inst12 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDP_IN(31 DOWNTO 0), - q => VDVZ(31 DOWNTO 0) + clock => ddrclk(0), + data => VDP_IN(31 downto 0), + q => vdvz(31 downto 0) ); @@ -566,7 +583,7 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(0), data => fb_ad_in, - q => FB_DDR(127 DOWNTO 96) + q => FB_DDR(127 downto 96) ); @@ -576,7 +593,7 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(1), data => fb_ad_in, - q => FB_DDR(95 DOWNTO 64) + q => FB_DDR(95 downto 64) ); @@ -586,7 +603,7 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(2), data => fb_ad_in, - q => FB_DDR(63 DOWNTO 32) + q => FB_DDR(63 downto 32) ); @@ -596,16 +613,16 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(3), data => fb_ad_in, - q => FB_DDR(31 DOWNTO 0) + q => FB_DDR(31 downto 0) ); inst17 : entity work.lpm_ff0 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => DDR_FB(1), - data => VDP_IN(31 DOWNTO 0), + data => VDP_IN(31 downto 0), q => SYNTHESIZED_WIRE_11 ); @@ -613,9 +630,9 @@ BEGIN inst18 : entity work.lpm_ff0 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => DDR_FB(0), - data => VDP_IN(63 DOWNTO 32), + data => VDP_IN(63 downto 32), q => SYNTHESIZED_WIRE_13 ); @@ -623,9 +640,9 @@ BEGIN inst19 : entity work.lpm_ff0 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => DDR_FB(0), - data => VDP_IN(31 DOWNTO 0), + data => VDP_IN(31 downto 0), q => SYNTHESIZED_WIRE_14 ); @@ -633,9 +650,9 @@ BEGIN inst2 : entity work.altddio_out0 port map ( - outclock => DDRCLK(3), - datain_h => VDMP(7 DOWNTO 4), - datain_l => VDMP(3 DOWNTO 0), + outclock => ddrclk(3), + datain_h => VDMP(7 downto 4), + datain_l => VDMP(3 downto 0), dataout => VDM ); @@ -643,9 +660,9 @@ BEGIN inst20 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDVZ(31 DOWNTO 0), - q => VDVZ(95 DOWNTO 64) + clock => ddrclk(0), + data => vdvz(31 downto 0), + q => vdvz(95 downto 64) ); @@ -653,11 +670,11 @@ BEGIN port map ( clock => pixel_clk_i, - data0x => FIFO_D(127 DOWNTO 96), - data1x => FIFO_D(95 DOWNTO 64), - data2x => FIFO_D(63 DOWNTO 32), - data3x => FIFO_D(31 DOWNTO 0), - sel => CLUT_MUX_ADR(1 DOWNTO 0), + data0x => FIFO_D(127 downto 96), + data1x => FIFO_D(95 downto 64), + data2x => FIFO_D(63 downto 32), + data3x => FIFO_D(31 downto 0), + sel => CLUT_MUX_ADR(1 downto 0), result => SYNTHESIZED_WIRE_48 ); @@ -665,11 +682,11 @@ BEGIN inst22 : entity work.lpm_mux5 port map ( - data0x => FB_DDR(127 DOWNTO 64), - data1x => FB_DDR(63 DOWNTO 0), - data2x => BLITTER_DOUT(127 DOWNTO 64), - data3x => BLITTER_DOUT(63 DOWNTO 0), - sel => DDRWR_D_SEL, + data0x => FB_DDR(127 downto 64), + data1x => FB_DDR(63 downto 0), + data2x => BLITTER_DOUT(127 downto 64), + data3x => BLITTER_DOUT(63 downto 0), + sel => ddrwr_d_sel, result => VDP_OUT ); @@ -685,15 +702,15 @@ BEGIN port map ( clock => pixel_clk_i, - data0x => FIFO_D(127 DOWNTO 112), - data1x => FIFO_D(111 DOWNTO 96), - data2x => FIFO_D(95 DOWNTO 80), - data3x => FIFO_D(79 DOWNTO 64), - data4x => FIFO_D(63 DOWNTO 48), - data5x => FIFO_D(47 DOWNTO 32), - data6x => FIFO_D(31 DOWNTO 16), - data7x => FIFO_D(15 DOWNTO 0), - sel => CLUT_MUX_ADR(2 DOWNTO 0), + data0x => FIFO_D(127 downto 112), + data1x => FIFO_D(111 downto 96), + data2x => FIFO_D(95 downto 80), + data3x => FIFO_D(79 downto 64), + data4x => FIFO_D(63 downto 48), + data5x => FIFO_D(47 downto 32), + data6x => FIFO_D(31 downto 16), + data7x => FIFO_D(15 downto 0), + sel => CLUT_MUX_ADR(2 downto 0), result => SYNTHESIZED_WIRE_7 ); @@ -702,22 +719,22 @@ BEGIN port map ( clock => pixel_clk_i, - data0x => FIFO_D(127 DOWNTO 120), - data10x => FIFO_D(47 DOWNTO 40), - data11x => FIFO_D(39 DOWNTO 32), - data12x => FIFO_D(31 DOWNTO 24), - data13x => FIFO_D(23 DOWNTO 16), - data14x => FIFO_D(15 DOWNTO 8), - data15x => FIFO_D(7 DOWNTO 0), - data1x => FIFO_D(119 DOWNTO 112), - data2x => FIFO_D(111 DOWNTO 104), - data3x => FIFO_D(103 DOWNTO 96), - data4x => FIFO_D(95 DOWNTO 88), - data5x => FIFO_D(87 DOWNTO 80), - data6x => FIFO_D(79 DOWNTO 72), - data7x => FIFO_D(71 DOWNTO 64), - data8x => FIFO_D(63 DOWNTO 56), - data9x => FIFO_D(55 DOWNTO 48), + data0x => FIFO_D(127 downto 120), + data10x => FIFO_D(47 downto 40), + data11x => FIFO_D(39 downto 32), + data12x => FIFO_D(31 downto 24), + data13x => FIFO_D(23 downto 16), + data14x => FIFO_D(15 downto 8), + data15x => FIFO_D(7 downto 0), + data1x => FIFO_D(119 downto 112), + data2x => FIFO_D(111 downto 104), + data3x => FIFO_D(103 downto 96), + data4x => FIFO_D(95 downto 88), + data5x => FIFO_D(87 downto 80), + data6x => FIFO_D(79 downto 72), + data7x => FIFO_D(71 downto 64), + data8x => FIFO_D(63 downto 56), + data9x => FIFO_D(55 downto 48), sel => CLUT_MUX_ADR, result => SYNTHESIZED_WIRE_12 ); @@ -726,7 +743,7 @@ BEGIN inst26 : entity work.lpm_shiftreg4 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), shiftin => SR_FIFO_WRE, shiftout => FIFO_WRE ); @@ -740,50 +757,50 @@ BEGIN q => VDR ); - CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; + clut_adr(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; inst3 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDP_IN(63 DOWNTO 32), - q => VDVZ(63 DOWNTO 32) + clock => ddrclk(0), + data => VDP_IN(63 downto 32), + q => vdvz(63 downto 32) ); - CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; - CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; - SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; - SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; - SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; - SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; + clut_adr(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; + clut_adr(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; + SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND color8; + SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND color8; + SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND color8; + SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND color8; inst36 : entity work.lpm_ff6 port map ( - clock => DDRCLK(0), - enable => BLITTER_DACK(0), - data => VDVZ, - q => BLITTER_DIN + clock => ddrclk(0), + enable => blitter_dack(0), + data => vdvz, + q => blitter_din ); - VDOUT_OE <= DDR_WR OR SR_DDR_WR; - video_ta <= blitter_ta /* or video_mod_ta */ or video_ddr_ta; + vdout_oe <= ddr_wr OR sr_ddr_wr; + video_ta <= blitter_ta or video_mod_ta or video_ddr_ta; inst4 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDVZ(63 DOWNTO 32), - q => VDVZ(127 DOWNTO 96) + clock => ddrclk(0), + data => vdvz(63 downto 32), + q => vdvz(127 downto 96) ); inst40 : entity work.mux41_0 port map ( - S0 => COLOR2, - S1 => COLOR4, + S0 => color2, + S1 => color4, D0 => CLUT_ADR6A, INH => SYNTHESIZED_WIRE_19, D1 => CLUT_ADR7A, @@ -794,8 +811,8 @@ BEGIN inst41 : entity work.mux41_1 port map ( - S0 => COLOR2, - S1 => COLOR4, + S0 => color2, + S1 => color4, D0 => CLUT_ADR5A, INH => SYNTHESIZED_WIRE_20, D1 => CLUT_ADR6A, @@ -806,9 +823,9 @@ BEGIN inst42 : entity work.mux41_2 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR7A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR4A, INH => SYNTHESIZED_WIRE_21, D1 => CLUT_ADR5A, @@ -819,9 +836,9 @@ BEGIN inst43 : entity work.mux41_3 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR6A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR3A, INH => SYNTHESIZED_WIRE_22, D1 => CLUT_ADR4A, @@ -832,9 +849,9 @@ BEGIN inst44 : entity work.mux41_4 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR5A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR2A, INH => SYNTHESIZED_WIRE_23, D1 => CLUT_ADR3A, @@ -845,9 +862,9 @@ BEGIN inst45 : entity work.mux41_5 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR4A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR1A, INH => SYNTHESIZED_WIRE_24, D1 => CLUT_ADR2A, @@ -868,7 +885,7 @@ BEGIN port map ( clock => pixel_clk_i, - data => CCF, + data => ccf, q => SYNTHESIZED_WIRE_25 ); @@ -909,7 +926,7 @@ BEGIN inst54 : entity work.lpm_constant0 port map ( - result => CCS(20 DOWNTO 16) + result => CCS(20 downto 16) ); @@ -922,7 +939,7 @@ BEGIN inst59 : entity work.lpm_constant0 port map ( - result => CCS(12 DOWNTO 8) + result => CCS(12 downto 8) ); fb_ad_out(18 downto 16) <= synthesized_wire_34 when st_clut_rd else (others => 'Z'); @@ -955,15 +972,14 @@ BEGIN inst64 : entity work.lpm_constant0 port map ( - result => CCS(4 DOWNTO 0) + result => CCS(4 downto 0) ); SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; fb_ad_out(31 downto 26) <= synthesized_wire_41 when falcon_clut_rdh else (others => 'Z'); - -- the following line results in a syntax error. No idea what's wrong with it: - -- fb_ad_out(23 downto 18) <= synthesized_wire_44 when falcon_clut_rdh else (others <= 'Z'); + fb_ad_out(23 downto 18) <= synthesized_wire_44 when falcon_clut_rdh else (others => 'Z'); SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); @@ -974,11 +990,11 @@ BEGIN clock => pixel_clk_i, data0x => SYNTHESIZED_WIRE_42, data1x => SYNTHESIZED_WIRE_43, - data2x => (OTHERS => '0'), - data3x => (OTHERS => '0'), + data2x => (others => '0'), + data3x => (others => '0'), data4x => CCA, data5x => CC16, - data6x => CC24(23 DOWNTO 0), + data6x => CC24(23 downto 0), data7x => BORDER_COLOR, sel => CCSEL, result => SYNTHESIZED_WIRE_62 @@ -988,9 +1004,9 @@ BEGIN inst71 : entity work.lpm_ff6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => FIFO_WRE, - data => VDVZ, + data => vdvz, q => VDMA ); @@ -1001,29 +1017,29 @@ BEGIN inst77 : entity work.lpm_constant1 port map ( - result => CCF(1 DOWNTO 0) + result => ccf(1 downto 0) ); - CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; + clut_adr(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; inst80 : entity work.lpm_constant1 port map ( - result => CCF(9 DOWNTO 8) + result => ccf(9 downto 8) ); inst81 : entity work.lpm_mux4 port map ( - sel => COLOR1, - data0x => ZR_C8(7 DOWNTO 1), + sel => color1, + data0x => ZR_C8(7 downto 1), data1x => SYNTHESIZED_WIRE_47, - result => ZR_C8B(7 DOWNTO 1) + result => ZR_C8B(7 downto 1) ); @@ -1037,35 +1053,35 @@ BEGIN inst83 : entity work.lpm_constant1 port map ( - result => CCF(17 DOWNTO 16) + result => ccf(17 downto 16) ); - PROCESS(DDRCLK(0), DDR_WR) - BEGIN - IF (DDR_WR = '1') THEN - VDQS <= (OTHERS => DDRCLK(0)); + process(ddrclk(0), ddr_wr) + begin + if (ddr_wr = '1') then + vdqs <= (others => ddrclk(0)); ELSE - VDQS <= (OTHERS => 'Z'); - END IF; - END PROCESS; + vdqs <= (others => 'Z'); + end if; + end process; - PROCESS(DDRCLK(3)) - BEGIN - IF (rising_edge(DDRCLK(3))) THEN - DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; - DDR_WR <= SR_DDR_WR; - END IF; - END PROCESS; + process(ddrclk(3)) + begin + if (rising_edge(ddrclk(3))) then + ddrwr_d_sel(0) <= SR_DDRWR_D_SEL; + ddr_wr <= sr_ddr_wr; + end if; + end process; inst89 : entity work.lpm_shiftreg6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), shiftin => SR_BLITTER_DACK, - q => BLITTER_DACK + q => blitter_dack ); @@ -1078,54 +1094,54 @@ BEGIN ); - PROCESS(pixel_clk_i) - BEGIN - IF (rising_edge(pixel_clk_i)) THEN - DFF_inst91 <= CLUT_ADR(0); - END IF; - END PROCESS; + process(pixel_clk_i) + begin + if (rising_edge(pixel_clk_i)) then + DFF_inst91 <= clut_adr(0); + end if; + end process; inst92 : entity work.lpm_shiftreg6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), shiftin => SR_DDR_FB, q => DDR_FB ); - PROCESS(pixel_clk_i) - BEGIN - IF (rising_edge(pixel_clk_i)) THEN + process(pixel_clk_i) + begin + if (rising_edge(pixel_clk_i)) then DFF_inst93 <= DFF_inst91; - END IF; - END PROCESS; + end if; + end process; inst94 : entity work.lpm_ff6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => FIFO_WRE, data => VDMA, q => VDMB ); - PROCESS(pixel_clk_i) - BEGIN - IF (rising_edge(pixel_clk_i)) THEN + process(pixel_clk_i) + begin + if (rising_edge(pixel_clk_i)) then SYNTHESIZED_WIRE_64 <= FIFO_RDE; - END IF; - END PROCESS; + end if; + end process; inst97 : entity work.lpm_ff5 port map ( - clock => DDRCLK(2), + clock => ddrclk(2), data => SR_VDMP, q => VDMP ); @@ -1137,8 +1153,8 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_49, - data => FIFO_D(127 DOWNTO 112), - shiftout => CLUT_ADR(0) + data => FIFO_D(127 downto 112), + shiftout => clut_adr(0) ); @@ -1148,7 +1164,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_50, - data => FIFO_D(111 DOWNTO 96), + data => FIFO_D(111 downto 96), shiftout => CLUT_ADR1A ); @@ -1159,7 +1175,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_51, - data => FIFO_D(95 DOWNTO 80), + data => FIFO_D(95 downto 80), shiftout => CLUT_ADR2A ); @@ -1170,7 +1186,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_52, - data => FIFO_D(79 DOWNTO 64), + data => FIFO_D(79 downto 64), shiftout => CLUT_ADR3A ); @@ -1181,7 +1197,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_53, - data => FIFO_D(63 DOWNTO 48), + data => FIFO_D(63 downto 48), shiftout => CLUT_ADR4A ); @@ -1192,7 +1208,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_54, - data => FIFO_D(47 DOWNTO 32), + data => FIFO_D(47 downto 32), shiftout => CLUT_ADR5A ); @@ -1203,7 +1219,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => CLUT_ADR7A, - data => FIFO_D(31 DOWNTO 16), + data => FIFO_D(31 downto 16), shiftout => CLUT_ADR6A ); @@ -1213,8 +1229,8 @@ BEGIN ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, - shiftin => CLUT_ADR(0), - data => FIFO_D(15 DOWNTO 0), + shiftin => clut_adr(0), + data => FIFO_D(15 downto 0), shiftout => CLUT_ADR7A ); @@ -1226,12 +1242,12 @@ BEGIN wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => fb_ad_in(18 DOWNTO 16), - data_b => (OTHERS => '0'), + address_a => FB_ADR(4 downto 1), + address_b => clut_adr(3 downto 0), + data_a => fb_ad_in(18 downto 16), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_34, - q_b => CCS(7 DOWNTO 5) + q_b => CCS(7 downto 5) ); @@ -1242,12 +1258,12 @@ BEGIN wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => fb_ad_in(22 DOWNTO 20), - data_b => (OTHERS => '0'), + address_a => FB_ADR(4 downto 1), + address_b => clut_adr(3 downto 0), + data_a => fb_ad_in(22 downto 20), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_31, - q_b => CCS(15 DOWNTO 13) + q_b => CCS(15 downto 13) ); @@ -1258,12 +1274,12 @@ BEGIN wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => fb_ad_in(26 DOWNTO 24), - data_b => (OTHERS => '0'), + address_a => FB_ADR(4 downto 1), + address_b => clut_adr(3 downto 0), + data_a => fb_ad_in(26 downto 24), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_29, - q_b => CCS(23 DOWNTO 21) + q_b => CCS(23 downto 21) ); @@ -1289,9 +1305,9 @@ BEGIN fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, VR_D => VR_D, - COLOR8 => COLOR8, + color8 => color8, ACP_CLUT_RD => ACP_CLUT_RD, - COLOR1 => COLOR1, + color1 => color1, FALCON_CLUT_RDH => FALCON_CLUT_RDH, FALCON_CLUT_RDL => FALCON_CLUT_RDL, ST_CLUT_RD => ST_CLUT_RD, @@ -1301,9 +1317,9 @@ BEGIN nSYNC => nSYNC, nPD_VGA => nPD_VGA, FIFO_RDE => FIFO_RDE, - COLOR2 => COLOR2, - COLOR4 => COLOR4, - PIXEL_CLK => pixel_clk_i, + color2 => color2, + color4 => color4, + pixel_clk => pixel_clk_i, BLITTER_ON => BLITTER_ON, VIDEO_MOD_TA => VIDEO_MOD_TA, INTER_ZEI => INTER_ZEI, @@ -1322,5 +1338,5 @@ BEGIN VIDEO_RAM_CTR => VIDEO_RAM_CTR ); - PIXEL_CLK <= pixel_clk_i; -END rtl; \ No newline at end of file + pixel_clk <= pixel_clk_i; +end rtl; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index a44b48e..7eac92f 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -1131,7 +1131,7 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1'; + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1' else '0'; -- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011"); @@ -1284,32 +1284,32 @@ begin -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else - "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else - lwd_q when lof_cs = '1' and lwd_cs = '1' else - "0000" & hbe_q when hbe_cs = '1' else - "0000" & hdb_q when hdb_cs = '1' else - "0000" & hde_q when hde_cs = '1' else - "0000" & hbb_q when hbb_cs = '1' else - "0000" & hss_q when hss_cs = '1' else - "0000" & hht_q when hht_cs = '1' else - "00000" & vbe_q when vbe_cs = '1' else - "00000" & vdb_q when vdb_cs = '1' else - "00000" & vde_q when vde_cs = '1' else - "00000" & vbb_q when vbb_cs = '1' else - "00000" & vss_q when vss_cs = '1' else - "00000" & vft_q when vft_cs = '1' else - "0000000" & vco_q when vco_cs = '1' else - "000000000000" & vcntrl_q when vcntrl_cs = '1' else - acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else - atari_hh_q(31 downto 16) when atari_hh_cs = '1' else - atari_vh_q(31 downto 16) when atari_vh_cs = '1' else - atari_hl_q(31 downto 16) when atari_hl_cs = '1' else - atari_vl_q(31 downto 16) when atari_vl_cs = '1' else - "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else - "0000000" & vr_dout_q when video_pll_config_cs = '1' else - vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else - (others => 'Z'); - + "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else + lwd_q when lof_cs = '1' and lwd_cs = '1' else + "0000" & hbe_q when hbe_cs = '1' else + "0000" & hdb_q when hdb_cs = '1' else + "0000" & hde_q when hde_cs = '1' else + "0000" & hbb_q when hbb_cs = '1' else + "0000" & hss_q when hss_cs = '1' else + "0000" & hht_q when hht_cs = '1' else + "00000" & vbe_q when vbe_cs = '1' else + "00000" & vdb_q when vdb_cs = '1' else + "00000" & vde_q when vde_cs = '1' else + "00000" & vbb_q when vbb_cs = '1' else + "00000" & vss_q when vss_cs = '1' else + "00000" & vft_q when vft_cs = '1' else + "0000000" & vco_q when vco_cs = '1' else + "000000000000" & vcntrl_q when vcntrl_cs = '1' else + acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else + atari_hh_q(31 downto 16) when atari_hh_cs = '1' else + atari_vh_q(31 downto 16) when atari_vh_cs = '1' else + atari_hl_q(31 downto 16) when atari_hl_cs = '1' else + atari_vl_q(31 downto 16) when atari_vl_cs = '1' else + "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else + "0000000" & vr_dout_q when video_pll_config_cs = '1' else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else + (others => 'Z'); + -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); @@ -1326,16 +1326,38 @@ begin -- fb_ad(15 downto 0) <= u1_tridata; fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else - atari_hh_q(15 downto 0) when atari_hh_cs = '1' else - atari_vh_q(15 downto 0) when atari_vh_cs = '1' else - atari_hl_q(15 downto 0) when atari_hl_cs = '1' else - atari_vl_q(15 downto 0) when atari_vl_cs = '1' else - border_color_q(15 downto 0) when border_color_cs = '1' else - (others => 'Z'); + atari_hh_q(15 downto 0) when atari_hh_cs = '1' else + atari_vh_q(15 downto 0) when atari_vh_cs = '1' else + atari_hl_q(15 downto 0) when atari_hl_cs = '1' else + atari_vl_q(15 downto 0) when atari_vl_cs = '1' else + border_color_q(15 downto 0) when border_color_cs = '1' else + (others => 'Z'); - video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or - hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or - VSS_CS or VFT_CS or VCO_CS or vcntrl_cs; + video_mod_ta <= clut_ta_q or + st_shift_mode_cs or + falcon_shift_mode_cs or + acp_vctr_cs or + sys_ctr_cs or + lof_cs or + lwd_cs or + hbe_cs or + hdb_cs or + hde_cs or + hbb_cs or + hss_cs or + hht_cs or + atari_hh_cs or + atari_vh_cs or + atari_hl_cs or + atari_vl_cs or + vbe_cs or + vdb_cs or + vde_cs or + vbb_cs or + vss_cs or + vft_cs or + vco_cs or + vcntrl_cs; -- VIDEO AUSGABE SETZEN CLK17M_d <= not CLK17M_q; diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 39d550e..8883449 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -1,12 +1,12 @@ -LIBRARY ieee; - USE ieee.std_logic_1164.all; +library ieee; +use ieee.std_logic_1164.all; -LIBRARY altera; - USE altera.altera_primitives_components.all; +library altera; +use altera.altera_primitives_components.all; -LIBRARY work; +library work; -ENTITY firebee1 IS +entity firebee1 is port ( FB_ALE : in std_logic; @@ -147,7 +147,7 @@ ENTITY firebee1 IS ); end firebee1; -architecture rtl OF firebee1 IS +architecture rtl of firebee1 is signal ACP_CONF : std_logic_vector(31 downto 0); signal clk25m_i : std_logic; signal CLK2M : std_logic; @@ -269,8 +269,7 @@ begin c3 => DDRCLK(3), c4 => DDR_SYNC_66M ); - - + i_dsp : work.dsp port map ( @@ -284,8 +283,9 @@ begin FB_SIZE1 => FB_SIZE1, nFB_BURST => nFB_BURST, nRSTO => nRSTO, - nFB_CS3 => nFB_CS3, - FB_AD => FB_AD, + nFB_CS3 => nFB_CS3, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, IO => IO, SRD => SRD, @@ -297,8 +297,7 @@ begin DSP_INT => DSP_INT, DSP_TA => DSP_TA ); - - + i_falconio_sdcard_ide_cf : work.falconio_sdcard_ide_cf port map ( @@ -358,8 +357,9 @@ begin SD_CD_DATA3 => SD_CD_DATA3, SD_CDM_D1 => SD_CDM_D1, ACP_CONF => ACP_CONF(31 downto 24), - ACSI_D => ACSI_D, - FB_AD => FB_AD, + ACSI_D => ACSI_D, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, LP_D => LP_D, SCSI_D => SCSI_D, @@ -405,7 +405,7 @@ begin DMA_DRQ => DMA_DRQ, MIDI_TLR => MIDI_TLR ); - + i_interrupt_handler : work.interrupt_handler port map @@ -429,16 +429,16 @@ begin VSYNC => VSYNC, HSYNC => HSYNC, DMA_DRQ => DMA_DRQ, - nRSTO => nRSTO, - FB_AD => FB_AD, + nRSTO => nRSTO, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, INT_HANDLER_TA => INT_HANDLER_TA, TIN0 => TIN0, ACP_CONF => ACP_CONF, nIRQ => nIRQ - ); - - + ); + i_mfp_acia_clk_pll : work.altpll1 port map ( @@ -473,7 +473,6 @@ begin data_out => VR_D ); - i_video : entity work.video port map ( @@ -522,7 +521,6 @@ begin VR => VR ); - i_video_clk_pll : altpll4 port map ( @@ -563,6 +561,8 @@ begin nWR_GATE <= not(WR_GATE); nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta); + fb_ad_in <= fb_ad; + fb_ad <= fb_ad_out when (video_ta or int_handler_ta or dsp_ta or falcon_io_ta) else (others => 'Z'); CLK33M <= MAIN_CLK; diff --git a/FPGA_Quartus_13.1/firebee_utils_pkg.vhd b/FPGA_Quartus_13.1/firebee_utils_pkg.vhd deleted file mode 100644 index 5f31318..0000000 --- a/FPGA_Quartus_13.1/firebee_utils_pkg.vhd +++ /dev/null @@ -1,171 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This package contains utility functions, procedures and constants ----- for the Firebee project. ----- ----- Author(s): ---- ----- - Markus Fröschle, mfro@mubf.de ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2015 Markus Fröschle ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- - -LIBRARY ieee; - USE ieee.std_logic_1164.ALL; - USE ieee.numeric_std.ALL; - -PACKAGE firebee_utils_pkg IS - FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; - FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; - FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; - FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic; - - COMPONENT synchronizer IS - PORT - ( - -- Input ports - source_signal : IN std_logic; - - target_clock : IN std_logic; - target_signal : OUT std_logic - ); - END COMPONENT synchronizer; - -END firebee_utils_pkg; - -PACKAGE BODY firebee_utils_pkg IS - - FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_low : integer; - VARIABLE c_hi : integer; - BEGIN - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - - -- synthesis translate_off - REPORT("addr_const'HIGH = " & integer'IMAGE(c_hi) & " addr_const'LOW = " & integer'IMAGE(c_low)) SEVERITY WARNING; - REPORT("addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING; - -- synthesis translate_on - - FOR i IN c_hi DOWNTO c_low + 2 LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_l; - - FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_hi : integer; - VARIABLE c_low : integer; - BEGIN - REPORT("f_addr_cmp_w(): addr_const'HIGH = " & integer'IMAGE(addr_const'HIGH) & " addr_const'LOW = " & integer'IMAGE(addr_const'LOW)) SEVERITY WARNING; - REPORT("f_addr_cmp_w(): addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING; - - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - FOR i IN c_hi DOWNTO c_low + 1 LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_w(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("f_addr_cmp_w(): addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_w; - - -- this is just for completeness - FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_hi : integer; - VARIABLE c_low : integer; - BEGIN - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - - FOR i IN c_hi DOWNTO c_low LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_b; - - -- this is for arbitrary sized address compares. It compares from the highest bit of addr_const to the lowest - num_ignore - -- bit, thus allowing any size of comparision. - FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_hi : integer; - VARIABLE c_low : integer; - BEGIN - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - - FOR i IN addr_const'HIGH DOWNTO addr_const'LOW + num_ignore LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_mask; -END PACKAGE BODY firebee_utils_pkg; \ No newline at end of file From 00511897bf23fae69f62ffed01c947bc3eaae8c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 12:33:14 +0000 Subject: [PATCH 105/127] fix capitalisation --- .../Video/video_mod_mux_clutctr.vhd | 554 +++++++++--------- 1 file changed, 270 insertions(+), 284 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 7eac92f..83f4c56 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -73,7 +73,7 @@ entity video_mod_mux_clutctr is fb_size0 : in std_logic; fb_size1 : in std_logic; nFB_BURST : in std_logic; - fb_adR : in std_logic_vector(31 downto 0); + fb_adr : in std_logic_vector(31 downto 0); clk33m : in std_logic; clk25m : in std_logic; blitter_run : in std_logic; @@ -197,18 +197,18 @@ architecture rtl of video_mod_mux_clutctr is signal RAND_q : std_logic_vector(6 downto 0); signal ccsel_d : std_logic_vector(2 downto 0); signal ccsel_q : std_logic_vector(2 downto 0); - signal ATARI_HH : std_logic_vector(31 downto 0) := (others => '0'); - signal ATARI_HH_d : std_logic_vector(31 downto 0); - signal ATARI_HH_q : std_logic_vector(31 downto 0); - signal ATARI_VH : std_logic_vector(31 downto 0); - signal ATARI_VH_d : std_logic_vector(31 downto 0); - signal ATARI_VH_q : std_logic_vector(31 downto 0); - signal ATARI_HL : std_logic_vector(31 downto 0) := (others => '0'); - signal ATARI_HL_d : std_logic_vector(31 downto 0); - signal ATARI_HL_q : std_logic_vector(31 downto 0); - signal ATARI_VL : std_logic_vector(31 downto 0); - signal ATARI_VL_d : std_logic_vector(31 downto 0); - signal ATARI_VL_q : std_logic_vector(31 downto 0); + signal atari_hh : std_logic_vector(31 downto 0) := (others => '0'); + signal atari_hh_d : std_logic_vector(31 downto 0); + signal atari_hh_q : std_logic_vector(31 downto 0); + signal atari_vh : std_logic_vector(31 downto 0); + signal atari_vh_d : std_logic_vector(31 downto 0); + signal atari_vh_q : std_logic_vector(31 downto 0); + signal atari_hl : std_logic_vector(31 downto 0) := (others => '0'); + signal atari_hl_d : std_logic_vector(31 downto 0); + signal atari_hl_q : std_logic_vector(31 downto 0); + signal atari_vl : std_logic_vector(31 downto 0); + signal atari_vl_d : std_logic_vector(31 downto 0); + signal atari_vl_q : std_logic_vector(31 downto 0); signal rand_links : std_logic_vector(11 downto 0); signal hdis_start : std_logic_vector(11 downto 0); signal hdis_end : std_logic_vector(11 downto 0); @@ -238,7 +238,7 @@ architecture rtl of video_mod_mux_clutctr is signal rand_OBEN : std_logic_vector(10 downto 0); signal VDIS_START : std_logic_vector(10 downto 0); signal VDIS_end : std_logic_vector(10 downto 0); - signal rand_UNTEN : std_logic_vector(10 downto 0); + signal border_bottom : std_logic_vector(10 downto 0); signal VS_START : std_logic_vector(10 downto 0); signal V_TOTAL : std_logic_vector(10 downto 0); signal VBE : std_logic_vector(10 downto 0); @@ -294,11 +294,11 @@ architecture rtl of video_mod_mux_clutctr is signal atari_hl16_ena_ctrl : std_logic; signal atari_hl8_ena_ctrl : std_logic; signal atari_hl0_ena_ctrl : std_logic; - signal ATARI_VL0_clk_ctrl : std_logic; - signal ATARI_VL24_ena_ctrl : std_logic; - signal ATARI_VL16_ena_ctrl : std_logic; - signal ATARI_VL8_ena_ctrl : std_logic; - signal ATARI_VL0_ena_ctrl : std_logic; + signal atari_vl0_clk_ctrl : std_logic; + signal atari_vl24_ena_ctrl : std_logic; + signal atari_vl16_ena_ctrl : std_logic; + signal atari_vl8_ena_ctrl : std_logic; + signal atari_vl0_ena_ctrl : std_logic; signal vr_dout0_ena_ctrl : std_logic; signal vr_frq0_ena_ctrl : std_logic; signal border_color16_ena_ctrl : std_logic; @@ -366,15 +366,15 @@ architecture rtl of video_mod_mux_clutctr is signal DOP_ZEI : std_logic; signal inter_zei_q : std_logic; signal inter_zei_d : std_logic; - signal ST_VIDEO : std_logic; - signal FALCON_VIDEO : std_logic; + signal st_video : std_logic; + signal falcon_video : std_logic; signal HSS_CS : std_logic; signal HBB_CS : std_logic; signal hde_CS : std_logic; signal HDB_CS : std_logic; signal HBE_CS : std_logic; signal HHT_CS : std_logic; - signal ATARI_VL_CS : std_logic; + signal atari_vl_cs : std_logic; signal atari_hl_CS : std_logic; signal atari_vh_CS : std_logic; signal atari_hh_CS : std_logic; @@ -448,23 +448,23 @@ architecture rtl of video_mod_mux_clutctr is signal lwd_CS : std_logic; signal lof_CS : std_logic; signal sys_ctr_CS : std_logic; - signal ACP_VIDEO_ON : std_logic; + signal acp_video_on : std_logic; signal border_color_CS : std_logic; - signal acp_vctr_CS : std_logic; + signal acp_vctr_cs : std_logic; signal falcon_shift_mode_CS : std_logic; signal st_shift_mode_CS : std_logic; signal ST_CLUT : std_logic; - signal ST_CLUT_CS : std_logic; - signal FALCON_CLUT : std_logic; - signal FALCON_CLUT_CS : std_logic; + signal st_clut_cs : std_logic; + signal falcon_clut : std_logic; + signal falcon_clut_cs : std_logic; signal video_reconfig_q : std_logic; signal video_reconfig_d : std_logic; - signal VIDEO_PLL_RECONFIG_CS : std_logic; + signal video_pll_reconfig_cs : std_logic; signal vr_wr_q : std_logic; signal vr_wr_d : std_logic; - signal VIDEO_PLL_CONFIG_CS : std_logic; - signal ACP_CLUT : std_logic; - signal ACP_CLUT_CS : std_logic; + signal video_pll_config_cs : std_logic; + signal acp_clut : std_logic; + signal acp_clut_cs : std_logic; signal CLK13M_q : std_logic; signal CLK13M_d : std_logic; signal CLK13M : std_logic; @@ -499,23 +499,6 @@ architecture rtl of video_mod_mux_clutctr is end function sizeit; begin - -- Sub Module Section - u0 : entity work.lpm_bustri_WORD - port map - ( - data => u0_data, - enabledt => u0_enabledt, - tridata => u0_tridata - ); - - u1 : entity work.lpm_bustri_WORD - port map - ( - data => u1_data, - enabledt => u1_enabledt, - tridata => u1_tridata - ); - -- Register Section clut_mux_adr <= clut_mux_adr_q; @@ -558,26 +541,26 @@ begin end if; if border_color0_ena_ctrl = '1' then border_color_q(7 downto 0) <= border_color_d(7 downto 0); - END IF; + end if; ccsel_q <= ccsel_d; inter_zei_q <= inter_zei_d; dop_fifo_clr_q <= dop_fifo_clr_d; - END IF; - END PROCESS; + end if; + end process; video_reconfig <= video_reconfig_q; vr_wr <= vr_wr_q; clr_fifo <= clr_fifo_q; - PROCESS (pixel_clk_i) - BEGIN - IF rising_edge(pixel_clk_i) THEN - IF clr_fifo_ena = '1' THEN + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then + if clr_fifo_ena = '1' then clr_fifo_q <= clr_fifo_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; process (clk25m) begin @@ -588,9 +571,9 @@ begin vr_frq <= unsigned(vr_frq_q); - PROCESS (main_clk) - BEGIN - IF rising_edge(main_clk) THEN + process (main_clk) + begin + if rising_edge(main_clk) then vr_wr_q <= vr_wr_d; video_reconfig_q <= video_reconfig_d; @@ -763,13 +746,13 @@ begin hsync_START_q <= hsync_START_d; LAST_q <= LAST_d; - IF vsync_START_ena = '1' THEN + if vsync_START_ena = '1' then vsync_START_q <= vsync_START_d; - END IF; + end if; - IF vsync_I0_ena_ctrl='1' THEN + if vsync_I0_ena_ctrl='1' then vsync_I_q <= vsync_I_d; - END IF; + end if; disp_on_q <= disp_on_d; @@ -858,20 +841,20 @@ begin atari_hl_q(7 downto 0) <= atari_hl_d(7 downto 0); end if; - if ATARI_VL24_ena_ctrl = '1' then - ATARI_VL_q(31 downto 24) <= ATARI_VL_d(31 downto 24); + if atari_vl24_ena_ctrl = '1' then + atari_vl_q(31 downto 24) <= atari_vl_d(31 downto 24); end if; - if ATARI_VL16_ena_ctrl = '1' then - ATARI_VL_q(23 downto 16) <= ATARI_VL_d(23 downto 16); + if atari_vl16_ena_ctrl = '1' then + atari_vl_q(23 downto 16) <= atari_vl_d(23 downto 16); end if; - if ATARI_VL8_ena_ctrl = '1' then - ATARI_VL_q(15 downto 8) <= ATARI_VL_d(15 downto 8); + if atari_vl8_ena_ctrl = '1' then + atari_vl_q(15 downto 8) <= atari_vl_d(15 downto 8); end if; - if ATARI_VL0_ena_ctrl = '1' then - ATARI_VL_q(7 downto 0) <= ATARI_VL_d(7 downto 0); + if atari_vl0_ena_ctrl = '1' then + atari_vl_q(7 downto 0) <= atari_vl_d(7 downto 0); end if; if HHT8_ena_ctrl = '1' then @@ -897,92 +880,95 @@ begin -- BYT SELECT 32 BIT -- ADR==0 - -- FB_B(0) <= to_std_logic(fb_adR(1 downto 0) = "00"); + -- fb_b(0) <= to_std_logic(fb_adr(1 downto 0) = "00"); fb_b(0) <= '1' when fb_adr(1 downto 0) = "00" else '0'; -- ADR==1 -- HIGH WORD -- LONG UND LINE - FB_B(1) <= to_std_logic(fb_adR(1 downto 0) = "01") or (fb_size1 and (not - fb_size0) and (not fb_adR(1))) or (fb_size1 and fb_size0) or ((not - fb_size1) and (not fb_size0)); + fb_b(1) <= to_std_logic(fb_adr(1 downto 0) = "01") or + (fb_size1 and (not fb_size0) and (not fb_adr(1))) or (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); -- ADR==2 -- LONG UND LINE - FB_B(2) <= to_std_logic(fb_adR(1 downto 0) = "10") or (fb_size1 and fb_size0) or ((not fb_size1) and (not fb_size0)); + fb_b(2) <= to_std_logic(fb_adr(1 downto 0) = "10") or + (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); -- ADR==3 -- LOW WORD -- LONG UND LINE - FB_B(3) <= to_std_logic(fb_adR(1 downto 0) = "11") or (fb_size1 and (not fb_size0) and fb_adR(1)) or - (fb_size1 and fb_size0) or - ((not fb_size1) and (not fb_size0)); + fb_b(3) <= to_std_logic(fb_adr(1 downto 0) = "11") or + (fb_size1 and (not fb_size0) and fb_adr(1)) or + (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); -- BYT SELECT 16 BIT -- ADR==0 - FB_16B(0) <= to_std_logic(fb_adR(0) = '0'); + FB_16B(0) <= to_std_logic(fb_adr(0) = '0'); -- ADR==1 -- NOT BYT - FB_16B(1) <= to_std_logic(fb_adR(0) = '1') or (not ((not fb_size1) and fb_size0)); + FB_16B(1) <= to_std_logic(fb_adr(0) = '1') or (not ((not fb_size1) and fb_size0)); -- ACP CLUT -- -- 0-3FF/1024 - ACP_CLUT_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 10) = "000000000000000000"); - acp_clut_rd <= ACP_CLUT_CS and (not nFB_OE); - acp_clut_wr <= FB_B and sizeIt(ACP_CLUT_CS, 4) and sizeIt(not nFB_WR, 4); - CLUT_TA_d <= (ACP_CLUT_CS or FALCON_CLUT_CS or ST_CLUT_CS) and (not video_mod_ta); + acp_clut_cs <= to_std_logic(((not nFB_CS2) = '1') and fb_adr(27 downto 10) = "000000000000000000"); + acp_clut_rd <= acp_clut_cs and (not nFB_OE); + acp_clut_wr <= fb_b and sizeIt(acp_clut_cs, 4) and sizeIt(not nFB_WR, 4); + CLUT_TA_d <= (acp_clut_cs or falcon_clut_cs or st_clut_cs) and (not video_mod_ta); -- FALCON CLUT -- -- $F9800/$400 - FALCON_CLUT_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 10) = "1111100110"); + falcon_clut_cs <= to_std_logic(((not nFB_CS1) = '1') and fb_adr(19 downto 10) = "1111100110"); -- HIGH WORD - falcon_clut_rdh <= FALCON_CLUT_CS and (not nFB_OE) and (not fb_adR(1)); + falcon_clut_rdh <= falcon_clut_cs and (not nFB_OE) and (not fb_adr(1)); -- LOW WORD - falcon_clut_rdl <= FALCON_CLUT_CS and (not nFB_OE) and fb_adR(1); - falcon_clut_wr(1 downto 0) <= FB_16B and std_logic_vector'((not fb_adR(1)) & - (not fb_adR(1))) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - falcon_clut_wr(3 downto 2) <= FB_16B and std_logic_vector'(fb_adR(1) & fb_adR(1)) and std_logic_vector'(FALCON_CLUT_CS & FALCON_CLUT_CS) and + falcon_clut_rdl <= falcon_clut_cs and (not nFB_OE) and fb_adr(1); + falcon_clut_wr(1 downto 0) <= FB_16B and std_logic_vector'((not fb_adr(1)) & + (not fb_adr(1))) and std_logic_vector'(falcon_clut_cs & falcon_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + falcon_clut_wr(3 downto 2) <= FB_16B and std_logic_vector'(fb_adr(1) & fb_adr(1)) and std_logic_vector'(falcon_clut_cs & falcon_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); -- ST CLUT -- -- $F8240/$20 - ST_CLUT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 5) = "111110000010010"); - st_clut_rd <= ST_CLUT_CS and (not nFB_OE); - st_clut_wr <= FB_16B and std_logic_vector'(ST_CLUT_CS & ST_CLUT_CS) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + st_clut_cs <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 5) = "111110000010010"); + st_clut_rd <= st_clut_cs and (not nFB_OE); + st_clut_wr <= FB_16B and std_logic_vector'(st_clut_cs & st_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - -- ST SHifT MODE + -- ST shift mode -- $F8260/2 - st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adR(19 downto 1) = 19x"7c130" else '0'; - -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110000"); + st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adr(19 downto 1) = 19x"7c130" else '0'; + -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100110000"); st_shift_mode_d <= fb_ad_in(25 downto 24) when st_shift_mode_cs; - st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and FB_B(0); + st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and fb_b(0); -- MONO - color1_1 <= to_std_logic(st_shift_mode_q = "10") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); + color1_1 <= to_std_logic(st_shift_mode_q = "10") and (not color8) and st_video and (not acp_video_on); -- 4 FARBEN - color2 <= to_std_logic(st_shift_mode_q = "01") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); + color2 <= to_std_logic(st_shift_mode_q = "01") and (not color8) and st_video and (not acp_video_on); -- 16 FARBEN - COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not color8) and ST_VIDEO and (not ACP_VIDEO_ON); + COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not color8) and st_video and (not acp_video_on); - -- FALCON SHifT MODE + -- FALCON shift mode -- $F8266/2 - falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100110011"); + falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100110011"); falcon_shift_mode_d <= fb_ad_in(26 downto 16) when falcon_shift_mode_cs; - falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(2); - falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and FB_B(3); + falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and fb_b(2); + falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and fb_b(3); clut_off <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); - color1_2 <= falcon_shift_mode_q(10) and (not color16) and (not color8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - color8_1 <= falcon_shift_mode_q(4) and (not color16) and FALCON_VIDEO and (not ACP_VIDEO_ON); - color16_1 <= falcon_shift_mode_q(8) and FALCON_VIDEO and (not ACP_VIDEO_ON); - COLOR4_2 <= (not color1) and (not color16) and (not color8) and FALCON_VIDEO and (not ACP_VIDEO_ON); + color1_2 <= falcon_shift_mode_q(10) and (not color16) and (not color8) and falcon_video and (not acp_video_on); + color8_1 <= falcon_shift_mode_q(4) and (not color16) and falcon_video and (not acp_video_on); + color16_1 <= falcon_shift_mode_q(8) and falcon_video and (not acp_video_on); + COLOR4_2 <= (not color1) and (not color16) and (not color8) and falcon_video and (not acp_video_on); -- ACP VIDEO CONTROL -- BIT 0 = ACP VIDEO ON @@ -1000,16 +986,16 @@ begin -- BIT 26 = STANDARD ATARI SYNCS -- $400/4 - acp_vctr_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000000"); + acp_vctr_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000000"); acp_vctr_d(31 downto 8) <= fb_ad_in(31 downto 8) when acp_vctr_cs; acp_vctr_d(5 downto 0) <= fb_ad_in(5 downto 0) when acp_vctr_cs; - acp_vctr24_ena_ctrl <= acp_vctr_CS and fb_b(0) and (not nFB_WR); - acp_vctr16_ena_ctrl <= acp_vctr_CS and fb_b(1) and (not nFB_WR); - acp_vctr8_ena_ctrl <= acp_vctr_CS and fb_b(2) and (not nFB_WR); - acp_vctr0_ena_ctrl <= acp_vctr_CS and fb_b(3) and (not nFB_WR); - ACP_VIDEO_ON <= acp_vctr_q(0); + acp_vctr24_ena_ctrl <= acp_vctr_cs and fb_b(0) and (not nFB_WR); + acp_vctr16_ena_ctrl <= acp_vctr_cs and fb_b(1) and (not nFB_WR); + acp_vctr8_ena_ctrl <= acp_vctr_cs and fb_b(2) and (not nFB_WR); + acp_vctr0_ena_ctrl <= acp_vctr_cs and fb_b(3) and (not nFB_WR); + acp_video_on <= acp_vctr_q(0); nPD_VGA <= acp_vctr_q(1); -- ATARI MODUS @@ -1019,82 +1005,82 @@ begin -- HORIZONTAL TIMING 640x480 -- $410/4 - ATARI_HH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000100"); - ATARI_HH_d <= fb_ad_in when atari_hh_cs; - ATARI_HH24_ena_ctrl <= ATARI_HH_CS and FB_B(0) and (not nFB_WR); - ATARI_HH16_ena_ctrl <= ATARI_HH_CS and FB_B(1) and (not nFB_WR); - ATARI_HH8_ena_ctrl <= ATARI_HH_CS and FB_B(2) and (not nFB_WR); - ATARI_HH0_ena_ctrl <= ATARI_HH_CS and FB_B(3) and (not nFB_WR); + atari_hh_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000100"); + atari_hh_d <= fb_ad_in when atari_hh_cs; + atari_hh24_ena_ctrl <= atari_hh_cs and fb_b(0) and (not nFB_WR); + atari_hh16_ena_ctrl <= atari_hh_cs and fb_b(1) and (not nFB_WR); + atari_hh8_ena_ctrl <= atari_hh_cs and fb_b(2) and (not nFB_WR); + atari_hh0_ena_ctrl <= atari_hh_cs and fb_b(3) and (not nFB_WR); -- VERTIKAL TIMING 640x480 -- $414/4 - ATARI_VH_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000101"); - ATARI_VH_d <= fb_ad_in when atari_vh_cs; - ATARI_VH24_ena_ctrl <= ATARI_VH_CS and FB_B(0) and (not nFB_WR); - ATARI_VH16_ena_ctrl <= ATARI_VH_CS and FB_B(1) and (not nFB_WR); - ATARI_VH8_ena_ctrl <= ATARI_VH_CS and FB_B(2) and (not nFB_WR); - ATARI_VH0_ena_ctrl <= ATARI_VH_CS and FB_B(3) and (not nFB_WR); + atari_vh_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000101"); + atari_vh_d <= fb_ad_in when atari_vh_cs; + atari_vh24_ena_ctrl <= atari_vh_cs and fb_b(0) and (not nFB_WR); + atari_vh16_ena_ctrl <= atari_vh_cs and fb_b(1) and (not nFB_WR); + atari_vh8_ena_ctrl <= atari_vh_cs and fb_b(2) and (not nFB_WR); + atari_vh0_ena_ctrl <= atari_vh_cs and fb_b(3) and (not nFB_WR); -- HORIZONTAL TIMING 320x240 -- $418/4 - ATARI_HL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000110"); - ATARI_HL_d <= fb_ad_in when atari_hl_cs; - ATARI_HL24_ena_ctrl <= ATARI_HL_CS and FB_B(0) and (not nFB_WR); - ATARI_HL16_ena_ctrl <= ATARI_HL_CS and FB_B(1) and (not nFB_WR); - ATARI_HL8_ena_ctrl <= ATARI_HL_CS and FB_B(2) and (not nFB_WR); - ATARI_HL0_ena_ctrl <= ATARI_HL_CS and FB_B(3) and (not nFB_WR); + atari_hl_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000110"); + atari_hl_d <= fb_ad_in when atari_hl_cs; + atari_hl24_ena_ctrl <= atari_hl_cs and fb_b(0) and (not nFB_WR); + atari_hl16_ena_ctrl <= atari_hl_cs and fb_b(1) and (not nFB_WR); + atari_hl8_ena_ctrl <= atari_hl_cs and fb_b(2) and (not nFB_WR); + atari_hl0_ena_ctrl <= atari_hl_cs and fb_b(3) and (not nFB_WR); -- VERTIKAL TIMING 320x240 -- $41C/4 - ATARI_VL_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 2) = "00000000000000000100000111"); - ATARI_VL_d <= fb_ad_in when atari_vl_cs; - ATARI_VL24_ena_ctrl <= ATARI_VL_CS and FB_B(0) and (not nFB_WR); - ATARI_VL16_ena_ctrl <= ATARI_VL_CS and FB_B(1) and (not nFB_WR); - ATARI_VL8_ena_ctrl <= ATARI_VL_CS and FB_B(2) and (not nFB_WR); - ATARI_VL0_ena_ctrl <= ATARI_VL_CS and FB_B(3) and (not nFB_WR); + atari_vl_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000111"); + atari_vl_d <= fb_ad_in when atari_vl_cs; + atari_vl24_ena_ctrl <= atari_vl_cs and fb_b(0) and (not nFB_WR); + atari_vl16_ena_ctrl <= atari_vl_cs and fb_b(1) and (not nFB_WR); + atari_vl8_ena_ctrl <= atari_vl_cs and fb_b(2) and (not nFB_WR); + atari_vl0_ena_ctrl <= atari_vl_cs and fb_b(3) and (not nFB_WR); -- VIDEO PLL CONFIG -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VIDEO_PLL_CONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 9) = "0000000000000000011") and FB_B(0) and FB_B(1); - vr_wr_d <= VIDEO_PLL_CONFIG_CS and (not nFB_WR) and (not vr_busy) and (not vr_wr_q); - vr_rd <= VIDEO_PLL_CONFIG_CS and nFB_WR and (not vr_busy); + video_pll_config_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 9) = "0000000000000000011") and fb_b(0) and fb_b(1); + vr_wr_d <= video_pll_config_cs and (not nFB_WR) and (not vr_busy) and (not vr_wr_q); + vr_rd <= video_pll_config_cs and nFB_WR and (not vr_busy); vr_dout0_ena_ctrl <= not vr_busy; vr_dout_d <= vr_d; - vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adR(8 downto 0) = "000000100"); + vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adr(8 downto 0) = "000000100"); vr_frq_d <= fb_ad_in(23 downto 16) when video_pll_config_cs; -- VIDEO PLL RECONFIG -- $(F)000'0800 - VIDEO_PLL_RECONFIG_CS <= to_std_logic(((not nFB_CS2)='1') and fb_adR(27 downto 0) = "0000000000000000100000000000") and FB_B(0); - video_reconfig_d <= VIDEO_PLL_RECONFIG_CS and (not nFB_WR) and (not vr_busy) and (not video_reconfig_q); + video_pll_reconfig_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 0) = "0000000000000000100000000000") and fb_b(0); + video_reconfig_d <= video_pll_reconfig_cs and (not nFB_WR) and (not vr_busy) and (not video_reconfig_q); -- ---------------------------------------------------------------------------------------------------------------------- video_ram_ctr <= acp_vctr_q(31 downto 16); -- ------------ COLOR MODE IM ACP SETZEN - color1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; - color8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; - color16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and ACP_VIDEO_ON; - color24 <= acp_vctr_q(2) and ACP_VIDEO_ON; - ACP_CLUT <= (ACP_VIDEO_ON and (color1 or color8)) or (ST_VIDEO and color1); + color1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and acp_video_on; + color8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and acp_video_on; + color16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and acp_video_on; + color24 <= acp_vctr_q(2) and acp_video_on; + acp_clut <= (acp_video_on and (color1 or color8)) or (st_video and color1); -- ST ODER FALCON SHifT MODE SETZEN WENN WRITE X..SHifT REGISTER - acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); - acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not ACP_VIDEO_ON); + acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not acp_video_on); + acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not acp_video_on); - acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_CS and FB_B(3) and (not nFB_WR) and fb_ad_in(0)); - FALCON_VIDEO <= acp_vctr_q(7); - FALCON_CLUT <= FALCON_VIDEO and (not ACP_VIDEO_ON) and (not color16); - ST_VIDEO <= acp_vctr_q(6); - ST_CLUT <= ST_VIDEO and (not ACP_VIDEO_ON) and (not FALCON_CLUT) and (not color1); + acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_cs and fb_b(3) and (not nFB_WR) and fb_ad_in(0)); + falcon_video <= acp_vctr_q(7); + falcon_clut <= falcon_video and (not acp_video_on) and (not color16); + st_video <= acp_vctr_q(6); + ST_CLUT <= st_video and (not acp_video_on) and (not falcon_clut) and (not color1); pixel_clk_i <= pixel_clk; -- ONLY FOR INFORMATION ccsel_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and - sizeIt(FALCON_CLUT,3)) or ("100" and sizeIt(ACP_CLUT,3)) or ("101" and + sizeIt(falcon_clut,3)) or ("100" and sizeIt(acp_clut,3)) or ("101" and sizeIt(color16,3)) or ("110" and sizeIt(color24,3)) or ("111" and sizeIt(RAND_ON,3)); @@ -1102,11 +1088,11 @@ begin -- randFARBE -- $404/4 - border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adR(27 downto 2) = "00000000000000000100000001"); + border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adr(27 downto 2) = "00000000000000000100000001"); border_color_d <= fb_ad_in(23 downto 0) when border_color_cs; - border_color16_ena_ctrl <= border_color_CS and FB_B(1) and (not nFB_WR); - border_color8_ena_ctrl <= border_color_CS and FB_B(2) and (not nFB_WR); - border_color0_ena_ctrl <= border_color_CS and FB_B(3) and (not nFB_WR); + border_color16_ena_ctrl <= border_color_CS and fb_b(1) and (not nFB_WR); + border_color8_ena_ctrl <= border_color_CS and fb_b(2) and (not nFB_WR); + border_color0_ena_ctrl <= border_color_CS and fb_b(3) and (not nFB_WR); -- System Config Register -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi @@ -1131,128 +1117,128 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1' else '0'; - -- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr, 20x"f8006") = '1' else '0'; + -- fb_adr(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; - -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011"); + -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adr(19 downto 1) = "1111100000000000011"); sys_ctr_d <= fb_ad_in(22 downto 16) when sys_ctr_cs; - sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and FB_B(3); + sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and fb_b(3); blitter_on <= not sys_ctr_q(3); -- lof -- $820E/2 - lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100000111"); + lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000111"); lof_d <= fb_ad_in(31 downto 16) when lof_cs; - lof8_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(2); - lof0_ena_ctrl <= lof_CS and (not nFB_WR) and FB_B(3); + lof8_ena_ctrl <= lof_CS and (not nFB_WR) and fb_b(2); + lof0_ena_ctrl <= lof_CS and (not nFB_WR) and fb_b(3); lof <= lof_q; -- lwd -- $8210/2 - lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000100001000"); + lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100001000"); lwd_d <= fb_ad_in(31 downto 16) when lwd_cs; - lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(0); - lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and FB_B(1); + lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and fb_b(0); + lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and fb_b(1); -- HORIZONTAL -- HHT -- $8282/2 - HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000001"); + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000001"); HHT_d <= fb_ad_in(27 downto 16) when hht_cs; - HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(2); - HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and FB_B(3); + HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and fb_b(2); + HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and fb_b(3); -- HBE -- $8286/2 - HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000011"); + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000011"); HBE_d <= fb_ad_in(27 downto 16) when hbe_cs; - HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(2); - HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and FB_B(3); + HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and fb_b(2); + HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and fb_b(3); -- HDB -- $8288/2 - HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000100"); + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000100"); HDB_d <= fb_ad_in(27 downto 16) when hdb_cs; - HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(0); - HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and FB_B(1); + HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and fb_b(0); + HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and fb_b(1); -- HDE -- $828A/2 - HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000101"); + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000101"); HDE_d <= fb_ad_in(27 downto 16) when hde_cs; - HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(2); - HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and FB_B(3); + HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and fb_b(2); + HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and fb_b(3); -- HBB -- $8284/2 - HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000010"); + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000010"); HBB_d <= fb_ad_in(27 downto 16) when hbb_cs; - HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(0); - HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and FB_B(1); + HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and fb_b(0); + HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and fb_b(1); -- HSS -- Videl hsync start register $828C / 2 - HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101000110"); + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000110"); HSS_d <= fb_ad_in(27 downto 16) when hss_cs; - HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(0); - HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and FB_B(1); + HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and fb_b(0); + HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and fb_b(1); -- VERTIKAL -- VBE -- $82A6/2 - VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010011"); + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010011"); VBE_d <= fb_ad_in(26 downto 16) when vbe_cs; - VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(2); - VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and FB_B(3); + VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and fb_b(2); + VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and fb_b(3); -- VDB -- $82A8/2 - VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010100"); + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010100"); VDB_d <= fb_ad_in(26 downto 16) when vdb_cs; - VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(0); - VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and FB_B(1); + VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and fb_b(0); + VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and fb_b(1); -- VDE -- $82AA/2 - VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010101"); + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010101"); VDE_d <= fb_ad_in(26 downto 16) when vde_cs; - VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(2); - VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and FB_B(3); + VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and fb_b(2); + VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and fb_b(3); -- VBB -- $82A4/2 - VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010010"); + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010010"); VBB_d <= fb_ad_in(26 downto 16) when vbb_cs; - VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(0); - VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and FB_B(1); + VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and fb_b(0); + VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and fb_b(1); -- VSS -- $82AC/2 - VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010110"); + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010110"); VSS_d <= fb_ad_in(26 downto 16) when vss_cs; - VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(0); - VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and FB_B(1); + VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and fb_b(0); + VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and fb_b(1); -- VFT -- $82A2/2 - -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101010001"); + -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010001"); vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); VFT_d <= fb_ad_in(26 downto 16) when vft_cs; - VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(2); - VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and FB_B(3); + VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and fb_b(2); + VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and fb_b(3); -- VCO -- $82C0 / 2 Falcon clock control register VCO - VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adR(19 downto 1) = "1111100000101100000"); + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101100000"); VCO_d <= fb_ad_in(24 downto 16) when vco_cs; - VCO_ena(8) <= VCO_CS and (not nFB_WR) and FB_B(0); - VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and FB_B(1); + VCO_ena(8) <= VCO_CS and (not nFB_WR) and fb_b(0); + VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and fb_b(1); -- VCNTRL -- $82C2 / 2 Falcon resolution control register VCNTRL vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; vcntrl_d <= fb_ad_in(19 downto 16) when vcntrl_cs; - VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and FB_B(3); + VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and fb_b(3); -- - REGISTER OUT -- low word register access @@ -1274,14 +1260,14 @@ begin -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or -- (sizeIt(vcntrl_cs,16) and std_logic_vector'("000000000000" & vcntrl_q)) or --- (sizeIt(acp_vctr_CS,16) and acp_vctr_q(31 downto 16)) or +-- (sizeIt(acp_vctr_cs,16) and acp_vctr_q(31 downto 16)) or -- (sizeIt(atari_hh_CS,16) and atari_hh_q(31 downto 16)) or -- (sizeIt(atari_vh_CS,16) and atari_vh_q(31 downto 16)) or -- (sizeIt(atari_hl_CS,16) and atari_hl_q(31 downto 16)) or --- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or +-- (sizeIt(atari_vl_cs,16) and atari_vl_q(31 downto 16)) or -- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or --- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & vr_dout_q)) or --- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); +-- (sizeIt(video_pll_config_cs,16) and std_logic_vector'("0000000" & vr_dout_q)) or +-- (sizeIt(video_pll_reconfig_cs,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else @@ -1310,19 +1296,19 @@ begin vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else (others => 'Z'); --- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or --- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or --- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); +-- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_cs or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or +-- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or atari_vl_cs or video_pll_config_cs or +-- video_pll_reconfig_cs or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); -- fb_ad(31 downto 16) <= u0_tridata; -- high word register access --- u1_data <= (sizeIt(acp_vctr_CS,16) and acp_vctr_q(15 downto 0)) or +-- u1_data <= (sizeIt(acp_vctr_cs,16) and acp_vctr_q(15 downto 0)) or -- (sizeIt(atari_hh_CS,16) and atari_hh_q(15 downto 0)) or -- (sizeIt(atari_vh_CS,16) and atari_vh_q(15 downto 0)) or -- (sizeIt(atari_hl_CS,16) and atari_hl_q(15 downto 0)) or --- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or +-- (sizeIt(atari_vl_cs,16) and atari_vl_q(15 downto 0)) or -- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); --- u1_enabledt <= (acp_vctr_CS or border_color_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); +-- u1_enabledt <= (acp_vctr_cs or border_color_CS or atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs) and (not nFB_OE); -- fb_ad(15 downto 0) <= u1_tridata; fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else @@ -1367,13 +1353,13 @@ begin -- 320 pixels, 25.175 MHz, -- 640 pixels, 32 MHz, VGA monitor -- 640 pixels, 25.175 MHz, VGA monitor - pixel_clk <= (CLK13M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or - (CLK17M_q and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or - (clk25m and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or - (clk33m and (not ACP_VIDEO_ON) and (FALCON_VIDEO or ST_VIDEO) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or - (to_std_logic((clk25m and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "00")) or - (to_std_logic((clk33m and ACP_VIDEO_ON)='1' and acp_vctr_q(9 downto 8) = "01")) or - (clk_video and ACP_VIDEO_ON and acp_vctr_q(9)); + pixel_clk <= (CLK13M_q and (not acp_video_on) and (falcon_video or st_video) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or + (CLK17M_q and (not acp_video_on) and (falcon_video or st_video) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or + (clk25m and (not acp_video_on) and (falcon_video or st_video) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or + (clk33m and (not acp_video_on) and (falcon_video or st_video) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or + (to_std_logic((clk25m and acp_video_on)='1' and acp_vctr_q(9 downto 8) = "00")) or + (to_std_logic((clk33m and acp_video_on)='1' and acp_vctr_q(9 downto 8) = "01")) or + (clk_video and acp_video_on and acp_vctr_q(9)); -- ------------------------------------------------------------ -- HORIZONTALE SYNC LÄNGE in pixel_clk @@ -1394,19 +1380,19 @@ begin std_logic_vector(8d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else (others => '0'); - -- ("00001110" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or - -- ("00010000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or - -- ("00011100" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00100000" and sizeIt(not ACP_VIDEO_ON, 8) and (sizeIt(FALCON_VIDEO, 8) or sizeIt(ST_VIDEO, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00011100" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or - -- ("00100000" and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or - -- ((std_logic_vector(to_unsigned(16, hsy_len_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(ACP_VIDEO_ON, 8) and sizeIt(acp_vctr_q(9), 8)); + -- ("00001110" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or + -- ("00010000" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or + -- ("00011100" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00100000" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00011100" and sizeIt(acp_video_on, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or + -- ("00100000" and sizeIt(acp_video_on, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or + -- ((std_logic_vector(to_unsigned(16, hsy_len_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(acp_video_on, 8) and sizeIt(acp_vctr_q(9), 8)); -- MULTIPLIKATIONS FAKTOR - MULF <= ("000010" and sizeIt(not ST_VIDEO,6) and sizeIt(vcntrl_q(2),6)) or - ("000100" and sizeIt(not ST_VIDEO,6) and sizeIt(not vcntrl_q(2),6)) or - ("010000" and sizeIt(ST_VIDEO,6) and sizeIt(vcntrl_q(2),6)) or - ("100000" and sizeIt(ST_VIDEO,6) and sizeIt(not vcntrl_q(2),6)); + MULF <= ("000010" and sizeIt(not st_video,6) and sizeIt(vcntrl_q(2),6)) or + ("000100" and sizeIt(not st_video,6) and sizeIt(not vcntrl_q(2),6)) or + ("010000" and sizeIt(st_video,6) and sizeIt(vcntrl_q(2),6)) or + ("100000" and sizeIt(st_video,6) and sizeIt(not vcntrl_q(2),6)); -- BREITE IN PIXELN hdis_len <= ("000101000000" and sizeIt(vcntrl_q(2),12)) or ("001010000000" @@ -1414,7 +1400,7 @@ begin -- DOPPELZEILENMODUS -- ZEILENVERDOPPELUNG EIN AUS - dop_zei_d <= vcntrl_q(0) and (FALCON_VIDEO or ST_VIDEO); + dop_zei_d <= vcntrl_q(0) and (falcon_video or st_video); -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC @@ -1426,10 +1412,10 @@ begin -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START dop_fifo_clr_d <= (inter_zei_q and hsync_START_q) or SYNC_PIX_q; --- rand_links[] = HBE[] & ACP_VIDEO_ON --- # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 --- # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 --- # HBE[] * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- +-- rand_links[] = HBE[] & acp_video_on +-- # 21 & !acp_video_on & ATARI_SYNC & VCNTRL2 +-- # 42 & !acp_video_on & ATARI_SYNC & !VCNTRL2 +-- # HBE[] * (0, MULF[5..1]) & !acp_video_on & !ATARI_SYNC; -- rand_links <= HBE_q when acp_video_on else 12d"21" when not acp_video_on and atari_sync and vcntrl(2) else 12d"42" when not acp_video_on and atari_sync and not(vcntrl(2)) else @@ -1441,13 +1427,13 @@ begin (std_logic_vector(to_unsigned(42, 12)) and sizeit(not acp_video_on and atari_sync and not vcntrl(2), 12)) or (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 downto 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ --- hdis_start[] = HDB[] & ACP_VIDEO_ON --- # rand_links[] + 1 & !ACP_VIDEO_ON; -- - hdis_start <= (HDB_q and sizeIt(ACP_VIDEO_ON, 12)) or ((std_logic_vector(unsigned(rand_links) + 1)) and sizeIt(not ACP_VIDEO_ON,12)); - hdis_end <= (hde_q and sizeIt(ACP_VIDEO_ON, 12)) or - ((std_logic_vector(unsigned(rand_links) + unsigned(hdis_len))) and sizeIt(not ACP_VIDEO_ON,12)); - rand_rechts <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or - ((std_logic_vector(unsigned(hdis_end) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); +-- hdis_start[] = HDB[] & acp_video_on +-- # rand_links[] + 1 & !acp_video_on; -- + hdis_start <= (HDB_q and sizeIt(acp_video_on, 12)) or ((std_logic_vector(unsigned(rand_links) + 1)) and sizeIt(not acp_video_on,12)); + hdis_end <= (hde_q and sizeIt(acp_video_on, 12)) or + ((std_logic_vector(unsigned(rand_links) + unsigned(hdis_len))) and sizeIt(not acp_video_on,12)); + rand_rechts <= (HBB_q and sizeIt(acp_video_on,12)) or + ((std_logic_vector(unsigned(hdis_end) + 1)) and sizeIt(not acp_video_on, 12)); hs_start <= hss_q when acp_video_on else atari_hl(11 downto 0) when not(acp_video_on) and atari_sync and vcntrl(2) else @@ -1455,10 +1441,10 @@ begin std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else (others => '0'); --- hs_start[] = HSS[] & ACP_VIDEO_ON --- # atari_hl[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 --- # atari_hh[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 --- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- +-- hs_start[] = HSS[] & acp_video_on +-- # atari_hl[11..0] & !acp_video_on & ATARI_SYNC & VCNTRL2 +-- # atari_hh[11..0] & !acp_video_on & ATARI_SYNC & !VCNTRL2 +-- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !acp_video_on & !ATARI_SYNC; -- -- h_total <= hht_q when acp_video_on else atari_hl(27 downto 16) when not acp_video_on and atari_sync and vcntrl(2) else @@ -1466,41 +1452,41 @@ begin std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync else (others => '0'); --- h_total[] = HHT[] & ACP_VIDEO_ON --- # atari_hl[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 --- # atari_hh[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 --- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - rand_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and - sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or +-- h_total[] = HHT[] & acp_video_on +-- # atari_hl[27..16] & !acp_video_on & ATARI_SYNC & VCNTRL2 +-- # atari_hh[27..16] & !acp_video_on & ATARI_SYNC & !VCNTRL2 +-- # (HHT[] + 2) * (0, MULF[]) & !acp_video_on & !ATARI_SYNC; -- + rand_OBEN <= (VBE_q and sizeIt(acp_video_on,11)) or ("00000011111" and + sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not - ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or - ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_START <= (VDB_q and sizeIt(acp_video_on,11)) or + ("00000100000" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_end <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or - ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(ST_VIDEO,11)) or - ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or - (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + VDIS_end <= (VDE_q and sizeIt(acp_video_on,11)) or + ("00110101111" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(st_video,11)) or + ("00111111111" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not st_video,11)) or + (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - rand_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or - ((std_logic_vector(unsigned(VDIS_end) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + border_bottom <= (VBB_q and sizeIt(acp_video_on,11)) or + ((std_logic_vector(unsigned(VDIS_end) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 downto 0) - and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and + VS_START <= (VSS_q and sizeIt(acp_video_on,11)) or (atari_vl_q(10 downto 0) + and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(vcntrl_q(2),11)) or (atari_vh_q(10 downto 0) and sizeIt(not - ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not + acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not vcntrl_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and - sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 downto 16) - and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and + sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + V_TOTAL <= (VFT_q and sizeIt(acp_video_on,11)) or (atari_vl_q(26 downto 16) + and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(vcntrl_q(2),11)) or (atari_vh_q(26 downto 16) and sizeIt(not - ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not + acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not vcntrl_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and - sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); + sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); -- ZÄHLER last_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(h_total) - 2))); @@ -1512,7 +1498,7 @@ begin -- DISPLAY ON OFF -- 1 ZEILE DAVOR ON OFF - dpo_zl_d <= to_std_logic((unsigned(vvcnt_q) > unsigned(std_logic_vector(unsigned(rand_OBEN) - 1))) and (unsigned(vvcnt_q) < unsigned(std_logic_vector(unsigned(rand_UNTEN) - 1)))); + dpo_zl_d <= to_std_logic((unsigned(vvcnt_q) > unsigned(std_logic_vector(unsigned(rand_OBEN) - 1))) and (unsigned(vvcnt_q) < unsigned(std_logic_vector(unsigned(border_bottom) - 1)))); -- AM ZEILENendE ÃœBERNEHMEN dpo_zl_ena <= last_q; From 87a7353ee810ea58beb3ada22a4c5b997547a871 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 12:46:05 +0000 Subject: [PATCH 106/127] remove unneeded tristate bus driver --- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 321e14c..b7d5087 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -311,16 +311,6 @@ architecture rtl of ddr_ctr is end sizeIt; begin - - -- Sub Module Section - u0 : entity work.lpm_bustri_BYT - port map - ( - data => u0_data, - enabledt => u0_enabledt, - tridata => u0_tridata - ); - -- Register Section SR_FIFO_WRE <= SR_FIFO_WRE_q; From d2e11f660aed3e85e0237c0dc3348fa818b631f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 15:06:33 +0000 Subject: [PATCH 107/127] fix inthandler_ta which was errornously always enabled --- .../Interrupt_Handler/interrupt_handler.vhd | 7424 ++++++++--------- 1 file changed, 3704 insertions(+), 3720 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 1fce052..96ffa57 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -147,158 +147,149 @@ LIBRARY ieee; LIBRARY work; ENTITY interrupt_handler IS - PORT + port ( - MAIN_CLK : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - PIC_INT : IN std_logic; - E0_INT : IN std_logic; - DVI_INT : IN std_logic; - nPCI_INTA : IN std_logic; - nPCI_INTB : IN std_logic; - nPCI_INTC : IN std_logic; - nPCI_INTD : IN std_logic; - nMFP_INT : IN std_logic; - nFB_OE : IN std_logic; - DSP_INT : IN std_logic; - VSYNC : IN std_logic; - HSYNC : IN std_logic; - DMA_DRQ : IN std_logic; - nRSTO : IN std_logic; - nIRQ : BUFFER std_logic_vector(7 DOWNTO 2); - INT_HANDLER_TA : BUFFER std_logic; - ACP_CONF : BUFFER std_logic_vector(31 DOWNTO 0); - TIN0 : BUFFER std_logic; + MAIN_CLK : in std_logic; + nFB_WR : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + PIC_INT : in std_logic; + E0_INT : in std_logic; + DVI_INT : in std_logic; + nPCI_INTA : in std_logic; + nPCI_INTB : in std_logic; + nPCI_INTC : in std_logic; + nPCI_INTD : in std_logic; + nMFP_INT : in std_logic; + nFB_OE : in std_logic; + DSP_INT : in std_logic; + VSYNC : in std_logic; + HSYNC : in std_logic; + DMA_DRQ : in std_logic; + nRSTO : in std_logic; + nIRQ : buffer std_logic_vector(7 downto 2); + INT_HANDLER_TA : out std_logic; + ACP_CONF : buffer std_logic_vector(31 downto 0); + TIN0 : buffer std_logic; fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0) ); -END interrupt_handler; +end interrupt_handler; ARCHITECTURE rtl OF interrupt_handler IS -- WERTE REGISTER 0-63 - SIGNAL FB_B : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_CTR : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_CTR_d : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_CTR_q : std_logic_vector(31 DOWNTO 0); + signal FB_B : std_logic_vector(3 downto 0); + signal INT_CTR : std_logic_vector(31 downto 0); + signal INT_CTR_d : std_logic_vector(31 downto 0); + signal INT_CTR_q : std_logic_vector(31 downto 0); - SIGNAL INT_LATCH : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_LATCH_d : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_LATCH_clrn : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_LATCH_q : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_LATCH_clk : std_logic_vector(31 DOWNTO 0); + signal INT_LATCH : std_logic_vector(31 downto 0); + signal INT_LATCH_d : std_logic_vector(31 downto 0); + signal INT_LATCH_clrn : std_logic_vector(31 downto 0); + signal INT_LATCH_q : std_logic_vector(31 downto 0); + signal INT_LATCH_clk : std_logic_vector(31 downto 0); - SIGNAL INT_CLEAR : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_CLEAR_d : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_CLEAR_q : std_logic_vector(31 DOWNTO 0); + signal INT_CLEAR : std_logic_vector(31 downto 0); + signal INT_CLEAR_d : std_logic_vector(31 downto 0); + signal INT_CLEAR_q : std_logic_vector(31 downto 0); - SIGNAL INT_IN : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_ENA : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_ENA_d : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_ENA_q : std_logic_vector(31 DOWNTO 0); - SIGNAL INT_L : std_logic_vector(9 DOWNTO 0); - SIGNAL INT_L_d : std_logic_vector(9 DOWNTO 0); - SIGNAL INT_L_q : std_logic_vector(9 DOWNTO 0); - SIGNAL INT_LA9 : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA9_d : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA9_q : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA8 : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA8_d : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA8_q : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA7 : std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA7_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA7_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA6: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA6_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA6_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA5: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA5_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA5_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA4: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA4_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA4_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA3: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA3_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA3_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA2: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA2_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA2_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA1: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA1_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA1_q: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA0: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA0_d: std_logic_vector(3 DOWNTO 0); - SIGNAL INT_LA0_q: std_logic_vector(3 DOWNTO 0); + signal INT_IN : std_logic_vector(31 downto 0); + signal INT_ENA : std_logic_vector(31 downto 0); + signal INT_ENA_d : std_logic_vector(31 downto 0); + signal INT_ENA_q : std_logic_vector(31 downto 0); + signal INT_L : std_logic_vector(9 downto 0); + signal INT_L_d : std_logic_vector(9 downto 0); + signal INT_L_q : std_logic_vector(9 downto 0); + signal INT_LA9 : std_logic_vector(3 downto 0); + signal INT_LA9_d : std_logic_vector(3 downto 0); + signal INT_LA9_q : std_logic_vector(3 downto 0); + signal INT_LA8 : std_logic_vector(3 downto 0); + signal INT_LA8_d : std_logic_vector(3 downto 0); + signal INT_LA8_q : std_logic_vector(3 downto 0); + signal INT_LA7 : std_logic_vector(3 downto 0); + signal INT_LA7_d: std_logic_vector(3 downto 0); + signal INT_LA7_q: std_logic_vector(3 downto 0); + signal INT_LA6: std_logic_vector(3 downto 0); + signal INT_LA6_d: std_logic_vector(3 downto 0); + signal INT_LA6_q: std_logic_vector(3 downto 0); + signal INT_LA5: std_logic_vector(3 downto 0); + signal INT_LA5_d: std_logic_vector(3 downto 0); + signal INT_LA5_q: std_logic_vector(3 downto 0); + signal INT_LA4: std_logic_vector(3 downto 0); + signal INT_LA4_d: std_logic_vector(3 downto 0); + signal INT_LA4_q: std_logic_vector(3 downto 0); + signal INT_LA3: std_logic_vector(3 downto 0); + signal INT_LA3_d: std_logic_vector(3 downto 0); + signal INT_LA3_q: std_logic_vector(3 downto 0); + signal INT_LA2: std_logic_vector(3 downto 0); + signal INT_LA2_d: std_logic_vector(3 downto 0); + signal INT_LA2_q: std_logic_vector(3 downto 0); + signal INT_LA1: std_logic_vector(3 downto 0); + signal INT_LA1_d: std_logic_vector(3 downto 0); + signal INT_LA1_q: std_logic_vector(3 downto 0); + signal INT_LA0: std_logic_vector(3 downto 0); + signal INT_LA0_d: std_logic_vector(3 downto 0); + signal INT_LA0_q: std_logic_vector(3 downto 0); - SIGNAL ACP_CONF_d: std_logic_vector(31 DOWNTO 0); - SIGNAL ACP_CONF_q: std_logic_vector(31 DOWNTO 0); + signal ACP_CONF_d: std_logic_vector(31 downto 0); + signal ACP_CONF_q: std_logic_vector(31 downto 0); - SIGNAL RTC_ADR: std_logic_vector(5 DOWNTO 0); - SIGNAL RTC_ADR_d: std_logic_vector(5 DOWNTO 0); - SIGNAL RTC_ADR_q: std_logic_vector(5 DOWNTO 0); + signal RTC_ADR: std_logic_vector(5 downto 0); + signal RTC_ADR_d: std_logic_vector(5 downto 0); + signal RTC_ADR_q: std_logic_vector(5 downto 0); - SIGNAL ACHTELSEKUNDEN: std_logic_vector(2 DOWNTO 0); - SIGNAL ACHTELSEKUNDEN_d: std_logic_vector(2 DOWNTO 0); - SIGNAL ACHTELSEKUNDEN_q: std_logic_vector(2 DOWNTO 0); + signal ACHTELSEKUNDEN: std_logic_vector(2 downto 0); + signal ACHTELSEKUNDEN_d: std_logic_vector(2 downto 0); + signal ACHTELSEKUNDEN_q: std_logic_vector(2 downto 0); - SIGNAL WERTE7: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE7_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE7_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE7_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE6: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE6_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE6_clrn: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE6_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE6_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE5: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE5_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE5_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE5_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE4: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE4_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE4_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE4_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE3: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE3_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE3_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE3_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE2: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE2_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE2_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE2_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE1: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE1_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE1_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE1_q: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE0: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE0_d: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE0_ena: std_logic_vector(63 DOWNTO 0); - SIGNAL WERTE0_q: std_logic_vector(63 DOWNTO 0); + signal WERTE7: std_logic_vector(63 downto 0); + signal WERTE7_d: std_logic_vector(63 downto 0); + signal WERTE7_ena: std_logic_vector(63 downto 0); + signal WERTE7_q: std_logic_vector(63 downto 0); + signal WERTE6: std_logic_vector(63 downto 0); + signal WERTE6_d: std_logic_vector(63 downto 0); + signal WERTE6_clrn: std_logic_vector(63 downto 0); + signal WERTE6_ena: std_logic_vector(63 downto 0); + signal WERTE6_q: std_logic_vector(63 downto 0); + signal WERTE5: std_logic_vector(63 downto 0); + signal WERTE5_d: std_logic_vector(63 downto 0); + signal WERTE5_ena: std_logic_vector(63 downto 0); + signal WERTE5_q: std_logic_vector(63 downto 0); + signal WERTE4: std_logic_vector(63 downto 0); + signal WERTE4_d: std_logic_vector(63 downto 0); + signal WERTE4_ena: std_logic_vector(63 downto 0); + signal WERTE4_q: std_logic_vector(63 downto 0); + signal WERTE3: std_logic_vector(63 downto 0); + signal WERTE3_d: std_logic_vector(63 downto 0); + signal WERTE3_ena: std_logic_vector(63 downto 0); + signal WERTE3_q: std_logic_vector(63 downto 0); + signal WERTE2: std_logic_vector(63 downto 0); + signal WERTE2_d: std_logic_vector(63 downto 0); + signal WERTE2_ena: std_logic_vector(63 downto 0); + signal WERTE2_q: std_logic_vector(63 downto 0); + signal WERTE1: std_logic_vector(63 downto 0); + signal WERTE1_d: std_logic_vector(63 downto 0); + signal WERTE1_ena: std_logic_vector(63 downto 0); + signal WERTE1_q: std_logic_vector(63 downto 0); + signal WERTE0: std_logic_vector(63 downto 0); + signal WERTE0_d: std_logic_vector(63 downto 0); + signal WERTE0_ena: std_logic_vector(63 downto 0); + signal WERTE0_q: std_logic_vector(63 downto 0); - SIGNAL PIC_INT_SYNC: std_logic_vector(2 DOWNTO 0); - SIGNAL PIC_INT_SYNC_d: std_logic_vector(2 DOWNTO 0); - SIGNAL PIC_INT_SYNC_q: std_logic_vector(2 DOWNTO 0); + signal PIC_INT_SYNC: std_logic_vector(2 downto 0); + signal PIC_INT_SYNC_d: std_logic_vector(2 downto 0); + signal PIC_INT_SYNC_q: std_logic_vector(2 downto 0); - SIGNAL ANZAHL_TAGE_DES_MONATS: std_logic_vector(7 DOWNTO 0); + signal ANZAHL_TAGE_DES_MONATS: std_logic_vector(7 downto 0); - SIGNAL u0_data: std_logic_vector(7 DOWNTO 0); - SIGNAL u0_tridata: std_logic_vector(7 DOWNTO 0); - - SIGNAL u1_data: std_logic_vector(7 DOWNTO 0); - SIGNAL u1_tridata: std_logic_vector(7 DOWNTO 0); - - SIGNAL u2_data: std_logic_vector(7 DOWNTO 0); - SIGNAL u2_tridata: std_logic_vector(7 DOWNTO 0); - - SIGNAL u3_data: std_logic_vector(7 DOWNTO 0); - SIGNAL u3_tridata: std_logic_vector(7 DOWNTO 0); - - SIGNAL INT_LATCH0_clk_1, INT_LATCH1_clk_1, INT_LATCH2_clk_1, + signal u1_data: std_logic_vector(7 downto 0); + signal u1_tridata: std_logic_vector(7 downto 0); + + signal INT_LATCH0_clk_1, INT_LATCH1_clk_1, INT_LATCH2_clk_1, INT_LATCH3_clk_1, INT_LATCH4_clk_1, INT_LATCH5_clk_1, INT_LATCH6_clk_1, INT_LATCH7_clk_1, INT_LATCH8_clk_1, INT_LATCH9_clk_1, INT_CTR0_clk_ctrl, INT_CTR24_ena_ctrl, @@ -401,4669 +392,4637 @@ ARCHITECTURE rtl OF interrupt_handler IS signal INT_CLEAR_CS : std_logic := '0'; signal INT_LATCH_CS : std_logic := '0'; - FUNCTION to_std_logic(X: IN boolean) RETURN std_logic IS + FUNCTION to_std_logic(X: in boolean) RETURN std_logic IS VARIABLE ret : std_logic; - BEGIN - IF x THEN + begin + if x then ret := '1'; ELSE ret := '0'; - END IF; + end if; RETURN ret; - END to_std_logic; + end to_std_logic; -- sizeIt replicates a value to an array of specific length. FUNCTION sizeIt(a: std_logic; len: integer) RETURN std_logic_vector IS - VARIABLE rep: std_logic_vector( len - 1 DOWNTO 0); - BEGIN - FOR i IN rep'RANGE LOOP + VARIABLE rep: std_logic_vector( len - 1 downto 0); + begin + FOR i in rep'RANGE LOOP rep(i) := a; - END loop; + end loop; RETURN rep; - END sizeit; -BEGIN + end sizeit; +begin -- Sub Module Section - u0: work.lpm_bustri_BYT - PORT MAP - ( - data => u0_data, - enabledt => u0_enabledt, - tridata => u0_tridata - ); - + u1: work.lpm_bustri_BYT - PORT MAP + port map ( data => u1_data, enabledt => u1_enabledt, tridata => u1_tridata ); - - u2: work.lpm_bustri_BYT - PORT MAP - ( - data => u2_data, - enabledt => u2_enabledt, - tridata => u2_tridata - ); - - u3: work.lpm_bustri_BYT - PORT MAP - ( - data => u3_data, - enabledt => u3_enabledt, - tridata => u3_tridata - ); -- Register Section - ACP_CONF(31 DOWNTO 24) <= ACP_CONF_q(31 DOWNTO 24); + ACP_CONF(31 downto 24) <= ACP_CONF_q(31 downto 24); - PROCESS (ACP_CONF0_clk_ctrl) - BEGIN - IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN - IF ACP_CONF24_ena_ctrl='1' THEN - (ACP_CONF_q(31), ACP_CONF_q(30), ACP_CONF_q(29), ACP_CONF_q(28), - ACP_CONF_q(27), ACP_CONF_q(26), ACP_CONF_q(25), - ACP_CONF_q(24)) <= ACP_CONF_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; + process (ACP_CONF0_clk_ctrl) + begin + if ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' then + if ACP_CONF24_ena_ctrl='1' then + ACP_CONF_q(31 downto 24) <= ACP_CONF_d(31 downto 24); + end if; + end if; + end process; - ACP_CONF(23 DOWNTO 16) <= ACP_CONF_q(23 DOWNTO 16); + ACP_CONF(23 downto 16) <= ACP_CONF_q(23 downto 16); - PROCESS (ACP_CONF0_clk_ctrl) - BEGIN - IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN - IF ACP_CONF16_ena_ctrl='1' THEN - (ACP_CONF_q(23), ACP_CONF_q(22), ACP_CONF_q(21), ACP_CONF_q(20), - ACP_CONF_q(19), ACP_CONF_q(18), ACP_CONF_q(17), - ACP_CONF_q(16)) <= ACP_CONF_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; + process (ACP_CONF0_clk_ctrl) + begin + if ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' then + if ACP_CONF16_ena_ctrl='1' then + ACP_CONF_q(23 downto 16) <= ACP_CONF_d(23 downto 16); + end if; + end if; + end process; - ACP_CONF(15 DOWNTO 8) <= ACP_CONF_q(15 DOWNTO 8); + ACP_CONF(15 downto 8) <= ACP_CONF_q(15 downto 8); - PROCESS (ACP_CONF0_clk_ctrl) - BEGIN - IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN - IF ACP_CONF8_ena_ctrl='1' THEN - (ACP_CONF_q(15), ACP_CONF_q(14), ACP_CONF_q(13), ACP_CONF_q(12), - ACP_CONF_q(11), ACP_CONF_q(10), ACP_CONF_q(9), ACP_CONF_q(8)) - <= ACP_CONF_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; + process (ACP_CONF0_clk_ctrl) + begin + if ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' then + if ACP_CONF8_ena_ctrl='1' then + ACP_CONF_q(15 downto 8) <= ACP_CONF_d(15 downto 8); + end if; + end if; + end process; - ACP_CONF(7 DOWNTO 0) <= ACP_CONF_q(7 DOWNTO 0); + ACP_CONF(7 downto 0) <= ACP_CONF_q(7 downto 0); - PROCESS (ACP_CONF0_clk_ctrl) - BEGIN - IF ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' THEN - IF ACP_CONF0_ena_ctrl='1' THEN - (ACP_CONF_q(7), ACP_CONF_q(6), ACP_CONF_q(5), ACP_CONF_q(4), - ACP_CONF_q(3), ACP_CONF_q(2), ACP_CONF_q(1), ACP_CONF_q(0)) - <= ACP_CONF_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + process (ACP_CONF0_clk_ctrl) + begin + if ACP_CONF0_clk_ctrl'event and ACP_CONF0_clk_ctrl='1' then + if ACP_CONF0_ena_ctrl='1' then + ACP_CONF_q(7 downto 0) <= ACP_CONF_d(7 downto 0); + end if; + end if; + end process; - PROCESS (INT_CTR0_clk_ctrl) BEGIN - IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN - IF INT_CTR24_ena_ctrl='1' THEN - (INT_CTR_q(31), INT_CTR_q(30), INT_CTR_q(29), INT_CTR_q(28), - INT_CTR_q(27), INT_CTR_q(26), INT_CTR_q(25), INT_CTR_q(24)) - <= INT_CTR_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; + process (INT_CTR0_clk_ctrl) + begin + if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then + if INT_CTR24_ena_ctrl='1' then + INT_CTR_q(31 downto 24) <= INT_CTR_d(31 downto 24); + end if; + end if; + end process; - PROCESS (INT_CTR0_clk_ctrl) BEGIN - IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN - IF INT_CTR16_ena_ctrl='1' THEN - (INT_CTR_q(23), INT_CTR_q(22), INT_CTR_q(21), INT_CTR_q(20), - INT_CTR_q(19), INT_CTR_q(18), INT_CTR_q(17), INT_CTR_q(16)) - <= INT_CTR_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; + process (INT_CTR0_clk_ctrl) + begin + if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then + if INT_CTR16_ena_ctrl='1' then + INT_CTR_q(23 downto 16) <= INT_CTR_d(23 downto 16); + end if; + end if; + end process; - PROCESS (INT_CTR0_clk_ctrl) BEGIN - IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN - IF INT_CTR8_ena_ctrl='1' THEN - (INT_CTR_q(15), INT_CTR_q(14), INT_CTR_q(13), INT_CTR_q(12), - INT_CTR_q(11), INT_CTR_q(10), INT_CTR_q(9), INT_CTR_q(8)) <= - INT_CTR_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; + process (INT_CTR0_clk_ctrl) + begin + if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then + if INT_CTR8_ena_ctrl='1' then + INT_CTR_q(15 downto 8) <= INT_CTR_d(15 downto 8); + end if; + end if; + end process; - PROCESS (INT_CTR0_clk_ctrl) BEGIN - IF INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' THEN - IF INT_CTR0_ena_ctrl='1' THEN - (INT_CTR_q(7), INT_CTR_q(6), INT_CTR_q(5), INT_CTR_q(4), - INT_CTR_q(3), INT_CTR_q(2), INT_CTR_q(1), INT_CTR_q(0)) <= - INT_CTR_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + process (INT_CTR0_clk_ctrl) + begin + if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then + if INT_CTR0_ena_ctrl='1' then + INT_CTR_q(7 downto 0) <= INT_CTR_d(7 downto 0); + end if; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(31)='0' THEN - INT_LATCH_q(31) <= '0'; - ELSIF INT_LATCH_clk(31)'event and INT_LATCH_clk(31)='1' THEN - INT_LATCH_q(31) <= INT_LATCH_d(31); - END IF; - END PROCESS; + process (INT_LATCH_clk, INT_LATCH_clrn) + begin + if INT_LATCH_clrn(31)='0' then + INT_LATCH_q(31) <= '0'; + elsif INT_LATCH_clk(31)'event and INT_LATCH_clk(31)='1' then + INT_LATCH_q(31) <= INT_LATCH_d(31); + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(30)='0' THEN - INT_LATCH_q(30) <= '0'; - ELSIF INT_LATCH_clk(30)'event and INT_LATCH_clk(30)='1' THEN - INT_LATCH_q(30) <= INT_LATCH_d(30); - END IF; - END PROCESS; + process (INT_LATCH_clk, INT_LATCH_clrn) + begin + if INT_LATCH_clrn(30)='0' then + INT_LATCH_q(30) <= '0'; + elsif INT_LATCH_clk(30)'event and INT_LATCH_clk(30)='1' then + INT_LATCH_q(30) <= INT_LATCH_d(30); + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(29)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) + begin + if INT_LATCH_clrn(29)='0' then INT_LATCH_q(29) <= '0'; - ELSIF INT_LATCH_clk(29)'event and INT_LATCH_clk(29)='1' THEN + elsif INT_LATCH_clk(29)'event and INT_LATCH_clk(29)='1' then INT_LATCH_q(29) <= INT_LATCH_d(29); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(28)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(28)='0' then INT_LATCH_q(28) <= '0'; - ELSIF INT_LATCH_clk(28)'event and INT_LATCH_clk(28)='1' THEN + elsif INT_LATCH_clk(28)'event and INT_LATCH_clk(28)='1' then INT_LATCH_q(28) <= INT_LATCH_d(28); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(27)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(27)='0' then INT_LATCH_q(27) <= '0'; - ELSIF INT_LATCH_clk(27)'event and INT_LATCH_clk(27)='1' THEN + elsif INT_LATCH_clk(27)'event and INT_LATCH_clk(27)='1' then INT_LATCH_q(27) <= INT_LATCH_d(27); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(26)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(26)='0' then INT_LATCH_q(26) <= '0'; - ELSIF INT_LATCH_clk(26)'event and INT_LATCH_clk(26)='1' THEN + elsif INT_LATCH_clk(26)'event and INT_LATCH_clk(26)='1' then INT_LATCH_q(26) <= INT_LATCH_d(26); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(25)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(25)='0' then INT_LATCH_q(25) <= '0'; - ELSIF INT_LATCH_clk(25)'event and INT_LATCH_clk(25)='1' THEN + elsif INT_LATCH_clk(25)'event and INT_LATCH_clk(25)='1' then INT_LATCH_q(25) <= INT_LATCH_d(25); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(24)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(24)='0' then INT_LATCH_q(24) <= '0'; - ELSIF INT_LATCH_clk(24)'event and INT_LATCH_clk(24)='1' THEN + elsif INT_LATCH_clk(24)'event and INT_LATCH_clk(24)='1' then INT_LATCH_q(24) <= INT_LATCH_d(24); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(23)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(23)='0' then INT_LATCH_q(23) <= '0'; - ELSIF INT_LATCH_clk(23)'event and INT_LATCH_clk(23)='1' THEN + elsif INT_LATCH_clk(23)'event and INT_LATCH_clk(23)='1' then INT_LATCH_q(23) <= INT_LATCH_d(23); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(22)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(22)='0' then INT_LATCH_q(22) <= '0'; - ELSIF INT_LATCH_clk(22)'event and INT_LATCH_clk(22)='1' THEN + elsif INT_LATCH_clk(22)'event and INT_LATCH_clk(22)='1' then INT_LATCH_q(22) <= INT_LATCH_d(22); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(21)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(21)='0' then INT_LATCH_q(21) <= '0'; - ELSIF INT_LATCH_clk(21)'event and INT_LATCH_clk(21)='1' THEN + elsif INT_LATCH_clk(21)'event and INT_LATCH_clk(21)='1' then INT_LATCH_q(21) <= INT_LATCH_d(21); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(20)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(20)='0' then INT_LATCH_q(20) <= '0'; - ELSIF INT_LATCH_clk(20)'event and INT_LATCH_clk(20)='1' THEN + elsif INT_LATCH_clk(20)'event and INT_LATCH_clk(20)='1' then INT_LATCH_q(20) <= INT_LATCH_d(20); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(19)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(19)='0' then INT_LATCH_q(19) <= '0'; - ELSIF INT_LATCH_clk(19)'event and INT_LATCH_clk(19)='1' THEN + elsif INT_LATCH_clk(19)'event and INT_LATCH_clk(19)='1' then INT_LATCH_q(19) <= INT_LATCH_d(19); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(18)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(18)='0' then INT_LATCH_q(18) <= '0'; - ELSIF INT_LATCH_clk(18)'event and INT_LATCH_clk(18)='1' THEN + elsif INT_LATCH_clk(18)'event and INT_LATCH_clk(18)='1' then INT_LATCH_q(18) <= INT_LATCH_d(18); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(17)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(17)='0' then INT_LATCH_q(17) <= '0'; - ELSIF INT_LATCH_clk(17)'event and INT_LATCH_clk(17)='1' THEN + elsif INT_LATCH_clk(17)'event and INT_LATCH_clk(17)='1' then INT_LATCH_q(17) <= INT_LATCH_d(17); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(16)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(16)='0' then INT_LATCH_q(16) <= '0'; - ELSIF INT_LATCH_clk(16)'event and INT_LATCH_clk(16)='1' THEN + elsif INT_LATCH_clk(16)'event and INT_LATCH_clk(16)='1' then INT_LATCH_q(16) <= INT_LATCH_d(16); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(15)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(15)='0' then INT_LATCH_q(15) <= '0'; - ELSIF INT_LATCH_clk(15)'event and INT_LATCH_clk(15)='1' THEN + elsif INT_LATCH_clk(15)'event and INT_LATCH_clk(15)='1' then INT_LATCH_q(15) <= INT_LATCH_d(15); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(14)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(14)='0' then INT_LATCH_q(14) <= '0'; - ELSIF INT_LATCH_clk(14)'event and INT_LATCH_clk(14)='1' THEN + elsif INT_LATCH_clk(14)'event and INT_LATCH_clk(14)='1' then INT_LATCH_q(14) <= INT_LATCH_d(14); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(13)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(13)='0' then INT_LATCH_q(13) <= '0'; - ELSIF INT_LATCH_clk(13)'event and INT_LATCH_clk(13)='1' THEN + elsif INT_LATCH_clk(13)'event and INT_LATCH_clk(13)='1' then INT_LATCH_q(13) <= INT_LATCH_d(13); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(12)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(12)='0' then INT_LATCH_q(12) <= '0'; - ELSIF INT_LATCH_clk(12)'event and INT_LATCH_clk(12)='1' THEN + elsif INT_LATCH_clk(12)'event and INT_LATCH_clk(12)='1' then INT_LATCH_q(12) <= INT_LATCH_d(12); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(11)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(11)='0' then INT_LATCH_q(11) <= '0'; - ELSIF INT_LATCH_clk(11)'event and INT_LATCH_clk(11)='1' THEN + elsif INT_LATCH_clk(11)'event and INT_LATCH_clk(11)='1' then INT_LATCH_q(11) <= INT_LATCH_d(11); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH_clk, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(10)='0' THEN + process (INT_LATCH_clk, INT_LATCH_clrn) begin + if INT_LATCH_clrn(10)='0' then INT_LATCH_q(10) <= '0'; - ELSIF INT_LATCH_clk(10)'event and INT_LATCH_clk(10)='1' THEN + elsif INT_LATCH_clk(10)'event and INT_LATCH_clk(10)='1' then INT_LATCH_q(10) <= INT_LATCH_d(10); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH9_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(9)='0' THEN + process (INT_LATCH9_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(9)='0' then INT_LATCH_q(9) <= '0'; - ELSIF INT_LATCH9_clk_1'event and INT_LATCH9_clk_1='1' THEN + elsif INT_LATCH9_clk_1'event and INT_LATCH9_clk_1='1' then INT_LATCH_q(9) <= INT_LATCH_d(9); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH8_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(8)='0' THEN + process (INT_LATCH8_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(8)='0' then INT_LATCH_q(8) <= '0'; - ELSIF INT_LATCH8_clk_1'event and INT_LATCH8_clk_1='1' THEN + elsif INT_LATCH8_clk_1'event and INT_LATCH8_clk_1='1' then INT_LATCH_q(8) <= INT_LATCH_d(8); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH7_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(7)='0' THEN + process (INT_LATCH7_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(7)='0' then INT_LATCH_q(7) <= '0'; - ELSIF INT_LATCH7_clk_1'event and INT_LATCH7_clk_1='1' THEN + elsif INT_LATCH7_clk_1'event and INT_LATCH7_clk_1='1' then INT_LATCH_q(7) <= INT_LATCH_d(7); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH6_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(6)='0' THEN + process (INT_LATCH6_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(6)='0' then INT_LATCH_q(6) <= '0'; - ELSIF INT_LATCH6_clk_1'event and INT_LATCH6_clk_1='1' THEN + elsif INT_LATCH6_clk_1'event and INT_LATCH6_clk_1='1' then INT_LATCH_q(6) <= INT_LATCH_d(6); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH5_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(5)='0' THEN + process (INT_LATCH5_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(5)='0' then INT_LATCH_q(5) <= '0'; - ELSIF INT_LATCH5_clk_1'event and INT_LATCH5_clk_1='1' THEN + elsif INT_LATCH5_clk_1'event and INT_LATCH5_clk_1='1' then INT_LATCH_q(5) <= INT_LATCH_d(5); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH4_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(4)='0' THEN + process (INT_LATCH4_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(4)='0' then INT_LATCH_q(4) <= '0'; - ELSIF INT_LATCH4_clk_1'event and INT_LATCH4_clk_1='1' THEN + elsif INT_LATCH4_clk_1'event and INT_LATCH4_clk_1='1' then INT_LATCH_q(4) <= INT_LATCH_d(4); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH3_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(3)='0' THEN + process (INT_LATCH3_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(3)='0' then INT_LATCH_q(3) <= '0'; - ELSIF INT_LATCH3_clk_1'event and INT_LATCH3_clk_1='1' THEN + elsif INT_LATCH3_clk_1'event and INT_LATCH3_clk_1='1' then INT_LATCH_q(3) <= INT_LATCH_d(3); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH2_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(2)='0' THEN + process (INT_LATCH2_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(2)='0' then INT_LATCH_q(2) <= '0'; - ELSIF INT_LATCH2_clk_1'event and INT_LATCH2_clk_1='1' THEN + elsif INT_LATCH2_clk_1'event and INT_LATCH2_clk_1='1' then INT_LATCH_q(2) <= INT_LATCH_d(2); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH1_clk_1, INT_LATCH_clrn) BEGIN - IF INT_LATCH_clrn(1)='0' THEN + process (INT_LATCH1_clk_1, INT_LATCH_clrn) begin + if INT_LATCH_clrn(1)='0' then INT_LATCH_q(1) <= '0'; - ELSIF INT_LATCH1_clk_1'event and INT_LATCH1_clk_1='1' THEN + elsif INT_LATCH1_clk_1'event and INT_LATCH1_clk_1='1' then INT_LATCH_q(1) <= INT_LATCH_d(1); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LATCH0_clk_1, INT_LATCH_clrn) - BEGIN - IF INT_LATCH_clrn(0)='0' THEN + process (INT_LATCH0_clk_1, INT_LATCH_clrn) + begin + if INT_LATCH_clrn(0)='0' then INT_LATCH_q(0) <= '0'; - ELSIF INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' THEN + elsif INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' then INT_LATCH_q(0) <= INT_LATCH_d(0); - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_CLEAR0_clk_ctrl) - BEGIN - IF INT_CLEAR0_clk_ctrl'event and INT_CLEAR0_clk_ctrl='1' THEN + process (INT_CLEAR0_clk_ctrl) + begin + if INT_CLEAR0_clk_ctrl'event and INT_CLEAR0_clk_ctrl='1' then INT_CLEAR_q <= INT_CLEAR_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) - BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN + process (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) + begin + if INT_ENA0_clrn_ctrl='0' then (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA24_ena_ctrl='1' THEN - (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= INT_ENA_d(31 DOWNTO 24); - END IF; - END IF; - END PROCESS; + elsif INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' then + if INT_ENA24_ena_ctrl='1' then + (INT_ENA_q(31), INT_ENA_q(30), INT_ENA_q(29), INT_ENA_q(28), INT_ENA_q(27), INT_ENA_q(26), INT_ENA_q(25), INT_ENA_q(24)) <= INT_ENA_d(31 downto 24); + end if; + end if; + end process; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN + process (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) begin + if INT_ENA0_clrn_ctrl='0' then (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA16_ena_ctrl='1' THEN - (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= INT_ENA_d(23 DOWNTO 16); - END IF; - END IF; - END PROCESS; + elsif INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' then + if INT_ENA16_ena_ctrl='1' then + (INT_ENA_q(23), INT_ENA_q(22), INT_ENA_q(21), INT_ENA_q(20), INT_ENA_q(19), INT_ENA_q(18), INT_ENA_q(17), INT_ENA_q(16)) <= INT_ENA_d(23 downto 16); + end if; + end if; + end process; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN + process (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) begin + if INT_ENA0_clrn_ctrl='0' then (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA8_ena_ctrl='1' THEN - (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= INT_ENA_d(15 DOWNTO 8); - END IF; - END IF; - END PROCESS; + elsif INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' then + if INT_ENA8_ena_ctrl='1' then + (INT_ENA_q(15), INT_ENA_q(14), INT_ENA_q(13), INT_ENA_q(12), INT_ENA_q(11), INT_ENA_q(10), INT_ENA_q(9), INT_ENA_q(8)) <= INT_ENA_d(15 downto 8); + end if; + end if; + end process; - PROCESS (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) BEGIN - IF INT_ENA0_clrn_ctrl='0' THEN + process (INT_ENA0_clk_ctrl, INT_ENA0_clrn_ctrl) begin + if INT_ENA0_clrn_ctrl='0' then (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= std_logic_vector'("00000000"); - ELSIF INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' THEN - IF INT_ENA0_ena_ctrl='1' THEN - (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= INT_ENA_d(7 DOWNTO 0); - END IF; - END IF; - END PROCESS; + elsif INT_ENA0_clk_ctrl'event and INT_ENA0_clk_ctrl='1' then + if INT_ENA0_ena_ctrl='1' then + (INT_ENA_q(7), INT_ENA_q(6), INT_ENA_q(5), INT_ENA_q(4), INT_ENA_q(3), INT_ENA_q(2), INT_ENA_q(1), INT_ENA_q(0)) <= INT_ENA_d(7 downto 0); + end if; + end if; + end process; - PROCESS (INT_L0_clk_ctrl, INT_L0_clrn_ctrl) BEGIN - IF INT_L0_clrn_ctrl='0' THEN + process (INT_L0_clk_ctrl, INT_L0_clrn_ctrl) begin + if INT_L0_clrn_ctrl='0' then INT_L_q <= std_logic_vector'("0000000000"); - ELSIF INT_L0_clk_ctrl'event and INT_L0_clk_ctrl='1' THEN + elsif INT_L0_clk_ctrl'event and INT_L0_clk_ctrl='1' then INT_L_q <= INT_L_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA9_0_clk_ctrl, INT_LA9_0_clrn_ctrl) BEGIN - IF INT_LA9_0_clrn_ctrl='0' THEN + process (INT_LA9_0_clk_ctrl, INT_LA9_0_clrn_ctrl) begin + if INT_LA9_0_clrn_ctrl='0' then INT_LA9_q <= std_logic_vector'("0000"); - ELSIF INT_LA9_0_clk_ctrl'event and INT_LA9_0_clk_ctrl='1' THEN + elsif INT_LA9_0_clk_ctrl'event and INT_LA9_0_clk_ctrl='1' then INT_LA9_q <= INT_LA9_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA8_0_clk_ctrl, INT_LA8_0_clrn_ctrl) BEGIN - IF INT_LA8_0_clrn_ctrl='0' THEN + process (INT_LA8_0_clk_ctrl, INT_LA8_0_clrn_ctrl) begin + if INT_LA8_0_clrn_ctrl='0' then INT_LA8_q <= std_logic_vector'("0000"); - ELSIF INT_LA8_0_clk_ctrl'event and INT_LA8_0_clk_ctrl='1' THEN + elsif INT_LA8_0_clk_ctrl'event and INT_LA8_0_clk_ctrl='1' then INT_LA8_q <= INT_LA8_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA7_0_clk_ctrl, INT_LA7_0_clrn_ctrl) BEGIN - IF INT_LA7_0_clrn_ctrl='0' THEN + process (INT_LA7_0_clk_ctrl, INT_LA7_0_clrn_ctrl) begin + if INT_LA7_0_clrn_ctrl='0' then INT_LA7_q <= std_logic_vector'("0000"); - ELSIF INT_LA7_0_clk_ctrl'event and INT_LA7_0_clk_ctrl='1' THEN + elsif INT_LA7_0_clk_ctrl'event and INT_LA7_0_clk_ctrl='1' then INT_LA7_q <= INT_LA7_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA6_0_clk_ctrl, INT_LA6_0_clrn_ctrl) BEGIN - IF INT_LA6_0_clrn_ctrl='0' THEN + process (INT_LA6_0_clk_ctrl, INT_LA6_0_clrn_ctrl) begin + if INT_LA6_0_clrn_ctrl='0' then INT_LA6_q <= std_logic_vector'("0000"); - ELSIF INT_LA6_0_clk_ctrl'event and INT_LA6_0_clk_ctrl='1' THEN + elsif INT_LA6_0_clk_ctrl'event and INT_LA6_0_clk_ctrl='1' then INT_LA6_q <= INT_LA6_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA5_0_clk_ctrl, INT_LA5_0_clrn_ctrl) BEGIN - IF INT_LA5_0_clrn_ctrl='0' THEN + process (INT_LA5_0_clk_ctrl, INT_LA5_0_clrn_ctrl) begin + if INT_LA5_0_clrn_ctrl='0' then INT_LA5_q <= std_logic_vector'("0000"); - ELSIF INT_LA5_0_clk_ctrl'event and INT_LA5_0_clk_ctrl='1' THEN + elsif INT_LA5_0_clk_ctrl'event and INT_LA5_0_clk_ctrl='1' then INT_LA5_q <= INT_LA5_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA4_0_clk_ctrl, INT_LA4_0_clrn_ctrl) BEGIN - IF INT_LA4_0_clrn_ctrl='0' THEN + process (INT_LA4_0_clk_ctrl, INT_LA4_0_clrn_ctrl) begin + if INT_LA4_0_clrn_ctrl='0' then INT_LA4_q <= std_logic_vector'("0000"); - ELSIF INT_LA4_0_clk_ctrl'event and INT_LA4_0_clk_ctrl='1' THEN + elsif INT_LA4_0_clk_ctrl'event and INT_LA4_0_clk_ctrl='1' then INT_LA4_q <= INT_LA4_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA3_0_clk_ctrl, INT_LA3_0_clrn_ctrl) BEGIN - IF INT_LA3_0_clrn_ctrl='0' THEN + process (INT_LA3_0_clk_ctrl, INT_LA3_0_clrn_ctrl) begin + if INT_LA3_0_clrn_ctrl='0' then INT_LA3_q <= std_logic_vector'("0000"); - ELSIF INT_LA3_0_clk_ctrl'event and INT_LA3_0_clk_ctrl='1' THEN + elsif INT_LA3_0_clk_ctrl'event and INT_LA3_0_clk_ctrl='1' then INT_LA3_q <= INT_LA3_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA2_0_clk_ctrl, INT_LA2_0_clrn_ctrl) BEGIN - IF INT_LA2_0_clrn_ctrl='0' THEN + process (INT_LA2_0_clk_ctrl, INT_LA2_0_clrn_ctrl) begin + if INT_LA2_0_clrn_ctrl='0' then INT_LA2_q <= std_logic_vector'("0000"); - ELSIF INT_LA2_0_clk_ctrl'event and INT_LA2_0_clk_ctrl='1' THEN + elsif INT_LA2_0_clk_ctrl'event and INT_LA2_0_clk_ctrl='1' then INT_LA2_q <= INT_LA2_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA1_0_clk_ctrl, INT_LA1_0_clrn_ctrl) BEGIN - IF INT_LA1_0_clrn_ctrl='0' THEN + process (INT_LA1_0_clk_ctrl, INT_LA1_0_clrn_ctrl) begin + if INT_LA1_0_clrn_ctrl='0' then INT_LA1_q <= std_logic_vector'("0000"); - ELSIF INT_LA1_0_clk_ctrl'event and INT_LA1_0_clk_ctrl='1' THEN + elsif INT_LA1_0_clk_ctrl'event and INT_LA1_0_clk_ctrl='1' then INT_LA1_q <= INT_LA1_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (INT_LA0_0_clk_ctrl, INT_LA0_0_clrn_ctrl) BEGIN - IF INT_LA0_0_clrn_ctrl='0' THEN + process (INT_LA0_0_clk_ctrl, INT_LA0_0_clrn_ctrl) begin + if INT_LA0_0_clrn_ctrl='0' then INT_LA0_q <= std_logic_vector'("0000"); - ELSIF INT_LA0_0_clk_ctrl'event and INT_LA0_0_clk_ctrl='1' THEN + elsif INT_LA0_0_clk_ctrl'event and INT_LA0_0_clk_ctrl='1' then INT_LA0_q <= INT_LA0_d; - END IF; - END PROCESS; + end if; + end process; - PROCESS (RTC_ADR0_clk_ctrl) BEGIN - IF RTC_ADR0_clk_ctrl'event and RTC_ADR0_clk_ctrl='1' THEN - IF RTC_ADR0_ena_ctrl='1' THEN + process (RTC_ADR0_clk_ctrl) begin + if RTC_ADR0_clk_ctrl'event and RTC_ADR0_clk_ctrl='1' then + if RTC_ADR0_ena_ctrl='1' then RTC_ADR_q <= RTC_ADR_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (ACHTELSEKUNDEN0_clk_ctrl) BEGIN - IF ACHTELSEKUNDEN0_clk_ctrl'event and ACHTELSEKUNDEN0_clk_ctrl='1' THEN - IF ACHTELSEKUNDEN0_ena_ctrl='1' THEN + process (ACHTELSEKUNDEN0_clk_ctrl) begin + if ACHTELSEKUNDEN0_clk_ctrl'event and ACHTELSEKUNDEN0_clk_ctrl='1' then + if ACHTELSEKUNDEN0_ena_ctrl='1' then ACHTELSEKUNDEN_q <= ACHTELSEKUNDEN_d; - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE7_q(63) <= WERTE7_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE7_q(62) <= WERTE7_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE7_q(61) <= WERTE7_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE7_q(60) <= WERTE7_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE7_q(59) <= WERTE7_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE7_q(58) <= WERTE7_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE7_q(57) <= WERTE7_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE7_q(56) <= WERTE7_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE7_q(55) <= WERTE7_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE7_q(54) <= WERTE7_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE7_q(53) <= WERTE7_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE7_q(52) <= WERTE7_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE7_q(51) <= WERTE7_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE7_q(50) <= WERTE7_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE7_q(49) <= WERTE7_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE7_q(48) <= WERTE7_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE7_q(47) <= WERTE7_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE7_q(46) <= WERTE7_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE7_q(45) <= WERTE7_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE7_q(44) <= WERTE7_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE7_q(43) <= WERTE7_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE7_q(42) <= WERTE7_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE7_q(41) <= WERTE7_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE7_q(40) <= WERTE7_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE7_q(39) <= WERTE7_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE7_q(38) <= WERTE7_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE7_q(37) <= WERTE7_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE7_q(36) <= WERTE7_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE7_q(35) <= WERTE7_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE7_q(34) <= WERTE7_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE7_q(33) <= WERTE7_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE7_q(32) <= WERTE7_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE7_q(31) <= WERTE7_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE7_q(30) <= WERTE7_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE7_q(29) <= WERTE7_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE7_q(28) <= WERTE7_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE7_q(27) <= WERTE7_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE7_q(26) <= WERTE7_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE7_q(25) <= WERTE7_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE7_q(24) <= WERTE7_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE7_q(23) <= WERTE7_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE7_q(22) <= WERTE7_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE7_q(21) <= WERTE7_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE7_q(20) <= WERTE7_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE7_q(19) <= WERTE7_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE7_q(18) <= WERTE7_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE7_q(17) <= WERTE7_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE7_q(16) <= WERTE7_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE7_q(15) <= WERTE7_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE7_q(14) <= WERTE7_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(13)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(13)='1' then WERTE7_q(13) <= WERTE7_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE7_q(12) <= WERTE7_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE7_q(11) <= WERTE7_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE7_q(10) <= WERTE7_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(9)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(9)='1' then WERTE7_q(9) <= WERTE7_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(8)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(8)='1' then WERTE7_q(8) <= WERTE7_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(7)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(7)='1' then WERTE7_q(7) <= WERTE7_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(6)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(6)='1' then WERTE7_q(6) <= WERTE7_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE7_q(5) <= WERTE7_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(4)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(4)='1' then WERTE7_q(4) <= WERTE7_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE7_q(3) <= WERTE7_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(2)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(2)='1' then WERTE7_q(2) <= WERTE7_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE7_q(1) <= WERTE7_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE7_0_clk_ctrl) BEGIN - IF WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' THEN - IF WERTE7_ena(0)='1' THEN + process (WERTE7_0_clk_ctrl) begin + if WERTE7_0_clk_ctrl'event and WERTE7_0_clk_ctrl='1' then + if WERTE7_ena(0)='1' then WERTE7_q(0) <= WERTE7_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE6_q(63) <= WERTE6_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE6_q(62) <= WERTE6_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE6_q(61) <= WERTE6_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE6_q(60) <= WERTE6_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE6_q(59) <= WERTE6_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE6_q(58) <= WERTE6_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE6_q(57) <= WERTE6_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE6_q(56) <= WERTE6_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE6_q(55) <= WERTE6_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE6_q(54) <= WERTE6_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE6_q(53) <= WERTE6_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE6_q(52) <= WERTE6_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE6_q(51) <= WERTE6_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE6_q(50) <= WERTE6_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE6_q(49) <= WERTE6_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE6_q(48) <= WERTE6_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE6_q(47) <= WERTE6_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE6_q(46) <= WERTE6_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE6_q(45) <= WERTE6_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE6_q(44) <= WERTE6_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE6_q(43) <= WERTE6_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE6_q(42) <= WERTE6_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE6_q(41) <= WERTE6_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE6_q(40) <= WERTE6_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE6_q(39) <= WERTE6_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE6_q(38) <= WERTE6_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE6_q(37) <= WERTE6_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE6_q(36) <= WERTE6_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE6_q(35) <= WERTE6_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE6_q(34) <= WERTE6_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE6_q(33) <= WERTE6_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE6_q(32) <= WERTE6_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE6_q(31) <= WERTE6_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE6_q(30) <= WERTE6_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE6_q(29) <= WERTE6_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE6_q(28) <= WERTE6_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE6_q(27) <= WERTE6_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE6_q(26) <= WERTE6_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE6_q(25) <= WERTE6_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE6_q(24) <= WERTE6_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE6_q(23) <= WERTE6_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE6_q(22) <= WERTE6_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE6_q(21) <= WERTE6_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE6_q(20) <= WERTE6_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE6_q(19) <= WERTE6_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE6_q(18) <= WERTE6_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE6_q(17) <= WERTE6_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE6_q(16) <= WERTE6_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE6_q(15) <= WERTE6_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE6_q(14) <= WERTE6_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(13)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(13)='1' then WERTE6_q(13) <= WERTE6_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE6_q(12) <= WERTE6_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE6_q(11) <= WERTE6_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl, WERTE6_clrn) BEGIN - IF WERTE6_clrn(10)='0' THEN + process (WERTE6_0_clk_ctrl, WERTE6_clrn) begin + if WERTE6_clrn(10)='0' then WERTE6_q(10) <= '0'; - ELSIF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + elsif WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE6_q(10) <= WERTE6_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(9)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(9)='1' then WERTE6_q(9) <= WERTE6_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(8)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(8)='1' then WERTE6_q(8) <= WERTE6_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(7)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(7)='1' then WERTE6_q(7) <= WERTE6_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(6)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(6)='1' then WERTE6_q(6) <= WERTE6_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE6_q(5) <= WERTE6_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(4)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(4)='1' then WERTE6_q(4) <= WERTE6_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE6_q(3) <= WERTE6_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(2)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(2)='1' then WERTE6_q(2) <= WERTE6_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE6_q(1) <= WERTE6_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE6_0_clk_ctrl) BEGIN - IF WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' THEN - IF WERTE6_ena(0)='1' THEN + process (WERTE6_0_clk_ctrl) begin + if WERTE6_0_clk_ctrl'event and WERTE6_0_clk_ctrl='1' then + if WERTE6_ena(0)='1' then WERTE6_q(0) <= WERTE6_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE5_q(63) <= WERTE5_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE5_q(62) <= WERTE5_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE5_q(61) <= WERTE5_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE5_q(60) <= WERTE5_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE5_q(59) <= WERTE5_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE5_q(58) <= WERTE5_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE5_q(57) <= WERTE5_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE5_q(56) <= WERTE5_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE5_q(55) <= WERTE5_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE5_q(54) <= WERTE5_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE5_q(53) <= WERTE5_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE5_q(52) <= WERTE5_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE5_q(51) <= WERTE5_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE5_q(50) <= WERTE5_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE5_q(49) <= WERTE5_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE5_q(48) <= WERTE5_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE5_q(47) <= WERTE5_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE5_q(46) <= WERTE5_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE5_q(45) <= WERTE5_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE5_q(44) <= WERTE5_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE5_q(43) <= WERTE5_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE5_q(42) <= WERTE5_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE5_q(41) <= WERTE5_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE5_q(40) <= WERTE5_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE5_q(39) <= WERTE5_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE5_q(38) <= WERTE5_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE5_q(37) <= WERTE5_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE5_q(36) <= WERTE5_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE5_q(35) <= WERTE5_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE5_q(34) <= WERTE5_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE5_q(33) <= WERTE5_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE5_q(32) <= WERTE5_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE5_q(31) <= WERTE5_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE5_q(30) <= WERTE5_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE5_q(29) <= WERTE5_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE5_q(28) <= WERTE5_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE5_q(27) <= WERTE5_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE5_q(26) <= WERTE5_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE5_q(25) <= WERTE5_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE5_q(24) <= WERTE5_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE5_q(23) <= WERTE5_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE5_q(22) <= WERTE5_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE5_q(21) <= WERTE5_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE5_q(20) <= WERTE5_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE5_q(19) <= WERTE5_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE5_q(18) <= WERTE5_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE5_q(17) <= WERTE5_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE5_q(16) <= WERTE5_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE5_q(15) <= WERTE5_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE5_q(14) <= WERTE5_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(13)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(13)='1' then WERTE5_q(13) <= WERTE5_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE5_q(12) <= WERTE5_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE5_q(11) <= WERTE5_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE5_q(10) <= WERTE5_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(9)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(9)='1' then WERTE5_q(9) <= WERTE5_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(8)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(8)='1' then WERTE5_q(8) <= WERTE5_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(7)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(7)='1' then WERTE5_q(7) <= WERTE5_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(6)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(6)='1' then WERTE5_q(6) <= WERTE5_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE5_q(5) <= WERTE5_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(4)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(4)='1' then WERTE5_q(4) <= WERTE5_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE5_q(3) <= WERTE5_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(2)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(2)='1' then WERTE5_q(2) <= WERTE5_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE5_q(1) <= WERTE5_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE5_0_clk_ctrl) BEGIN - IF WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' THEN - IF WERTE5_ena(0)='1' THEN + process (WERTE5_0_clk_ctrl) begin + if WERTE5_0_clk_ctrl'event and WERTE5_0_clk_ctrl='1' then + if WERTE5_ena(0)='1' then WERTE5_q(0) <= WERTE5_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE4_q(63) <= WERTE4_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE4_q(62) <= WERTE4_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE4_q(61) <= WERTE4_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE4_q(60) <= WERTE4_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE4_q(59) <= WERTE4_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE4_q(58) <= WERTE4_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE4_q(57) <= WERTE4_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE4_q(56) <= WERTE4_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE4_q(55) <= WERTE4_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE4_q(54) <= WERTE4_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE4_q(53) <= WERTE4_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE4_q(52) <= WERTE4_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE4_q(51) <= WERTE4_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE4_q(50) <= WERTE4_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE4_q(49) <= WERTE4_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE4_q(48) <= WERTE4_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE4_q(47) <= WERTE4_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE4_q(46) <= WERTE4_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE4_q(45) <= WERTE4_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE4_q(44) <= WERTE4_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE4_q(43) <= WERTE4_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE4_q(42) <= WERTE4_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE4_q(41) <= WERTE4_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE4_q(40) <= WERTE4_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE4_q(39) <= WERTE4_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE4_q(38) <= WERTE4_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE4_q(37) <= WERTE4_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE4_q(36) <= WERTE4_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE4_q(35) <= WERTE4_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE4_q(34) <= WERTE4_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE4_q(33) <= WERTE4_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE4_q(32) <= WERTE4_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE4_q(31) <= WERTE4_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE4_q(30) <= WERTE4_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE4_q(29) <= WERTE4_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE4_q(28) <= WERTE4_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE4_q(27) <= WERTE4_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE4_q(26) <= WERTE4_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE4_q(25) <= WERTE4_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE4_q(24) <= WERTE4_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE4_q(23) <= WERTE4_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE4_q(22) <= WERTE4_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE4_q(21) <= WERTE4_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE4_q(20) <= WERTE4_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE4_q(19) <= WERTE4_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE4_q(18) <= WERTE4_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE4_q(17) <= WERTE4_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE4_q(16) <= WERTE4_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE4_q(15) <= WERTE4_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE4_q(14) <= WERTE4_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(13)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(13)='1' then WERTE4_q(13) <= WERTE4_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE4_q(12) <= WERTE4_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE4_q(11) <= WERTE4_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE4_q(10) <= WERTE4_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(9)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(9)='1' then WERTE4_q(9) <= WERTE4_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(8)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(8)='1' then WERTE4_q(8) <= WERTE4_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(7)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(7)='1' then WERTE4_q(7) <= WERTE4_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(6)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(6)='1' then WERTE4_q(6) <= WERTE4_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE4_q(5) <= WERTE4_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(4)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(4)='1' then WERTE4_q(4) <= WERTE4_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE4_q(3) <= WERTE4_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(2)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(2)='1' then WERTE4_q(2) <= WERTE4_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE4_q(1) <= WERTE4_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE4_0_clk_ctrl) BEGIN - IF WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' THEN - IF WERTE4_ena(0)='1' THEN + process (WERTE4_0_clk_ctrl) begin + if WERTE4_0_clk_ctrl'event and WERTE4_0_clk_ctrl='1' then + if WERTE4_ena(0)='1' then WERTE4_q(0) <= WERTE4_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE3_q(63) <= WERTE3_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE3_q(62) <= WERTE3_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE3_q(61) <= WERTE3_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE3_q(60) <= WERTE3_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE3_q(59) <= WERTE3_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE3_q(58) <= WERTE3_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE3_q(57) <= WERTE3_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE3_q(56) <= WERTE3_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE3_q(55) <= WERTE3_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE3_q(54) <= WERTE3_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE3_q(53) <= WERTE3_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE3_q(52) <= WERTE3_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE3_q(51) <= WERTE3_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE3_q(50) <= WERTE3_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE3_q(49) <= WERTE3_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE3_q(48) <= WERTE3_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE3_q(47) <= WERTE3_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE3_q(46) <= WERTE3_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE3_q(45) <= WERTE3_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE3_q(44) <= WERTE3_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE3_q(43) <= WERTE3_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE3_q(42) <= WERTE3_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE3_q(41) <= WERTE3_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE3_q(40) <= WERTE3_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE3_q(39) <= WERTE3_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE3_q(38) <= WERTE3_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE3_q(37) <= WERTE3_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE3_q(36) <= WERTE3_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE3_q(35) <= WERTE3_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE3_q(34) <= WERTE3_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE3_q(33) <= WERTE3_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE3_q(32) <= WERTE3_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE3_q(31) <= WERTE3_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE3_q(30) <= WERTE3_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE3_q(29) <= WERTE3_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE3_q(28) <= WERTE3_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE3_q(27) <= WERTE3_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE3_q(26) <= WERTE3_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE3_q(25) <= WERTE3_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE3_q(24) <= WERTE3_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE3_q(23) <= WERTE3_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE3_q(22) <= WERTE3_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE3_q(21) <= WERTE3_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE3_q(20) <= WERTE3_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE3_q(19) <= WERTE3_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE3_q(18) <= WERTE3_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE3_q(17) <= WERTE3_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE3_q(16) <= WERTE3_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE3_q(15) <= WERTE3_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE3_q(14) <= WERTE3_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(13)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(13)='1' then WERTE3_q(13) <= WERTE3_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE3_q(12) <= WERTE3_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE3_q(11) <= WERTE3_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE3_q(10) <= WERTE3_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(9)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(9)='1' then WERTE3_q(9) <= WERTE3_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(8)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(8)='1' then WERTE3_q(8) <= WERTE3_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(7)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(7)='1' then WERTE3_q(7) <= WERTE3_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(6)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(6)='1' then WERTE3_q(6) <= WERTE3_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE3_q(5) <= WERTE3_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(4)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(4)='1' then WERTE3_q(4) <= WERTE3_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE3_q(3) <= WERTE3_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(2)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(2)='1' then WERTE3_q(2) <= WERTE3_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE3_q(1) <= WERTE3_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE3_0_clk_ctrl) BEGIN - IF WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' THEN - IF WERTE3_ena(0)='1' THEN + process (WERTE3_0_clk_ctrl) begin + if WERTE3_0_clk_ctrl'event and WERTE3_0_clk_ctrl='1' then + if WERTE3_ena(0)='1' then WERTE3_q(0) <= WERTE3_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE2_q(63) <= WERTE2_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE2_q(62) <= WERTE2_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE2_q(61) <= WERTE2_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE2_q(60) <= WERTE2_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE2_q(59) <= WERTE2_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE2_q(58) <= WERTE2_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE2_q(57) <= WERTE2_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE2_q(56) <= WERTE2_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE2_q(55) <= WERTE2_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE2_q(54) <= WERTE2_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE2_q(53) <= WERTE2_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE2_q(52) <= WERTE2_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE2_q(51) <= WERTE2_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE2_q(50) <= WERTE2_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE2_q(49) <= WERTE2_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE2_q(48) <= WERTE2_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE2_q(47) <= WERTE2_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE2_q(46) <= WERTE2_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE2_q(45) <= WERTE2_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE2_q(44) <= WERTE2_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE2_q(43) <= WERTE2_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE2_q(42) <= WERTE2_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE2_q(41) <= WERTE2_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE2_q(40) <= WERTE2_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE2_q(39) <= WERTE2_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE2_q(38) <= WERTE2_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE2_q(37) <= WERTE2_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE2_q(36) <= WERTE2_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE2_q(35) <= WERTE2_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE2_q(34) <= WERTE2_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE2_q(33) <= WERTE2_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE2_q(32) <= WERTE2_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE2_q(31) <= WERTE2_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE2_q(30) <= WERTE2_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE2_q(29) <= WERTE2_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE2_q(28) <= WERTE2_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE2_q(27) <= WERTE2_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE2_q(26) <= WERTE2_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE2_q(25) <= WERTE2_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE2_q(24) <= WERTE2_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE2_q(23) <= WERTE2_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE2_q(22) <= WERTE2_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE2_q(21) <= WERTE2_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE2_q(20) <= WERTE2_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE2_q(19) <= WERTE2_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE2_q(18) <= WERTE2_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE2_q(17) <= WERTE2_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE2_q(16) <= WERTE2_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE2_q(15) <= WERTE2_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE2_q(14) <= WERTE2_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(13)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(13)='1' then WERTE2_q(13) <= WERTE2_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE2_q(12) <= WERTE2_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE2_q(11) <= WERTE2_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE2_q(10) <= WERTE2_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(9)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(9)='1' then WERTE2_q(9) <= WERTE2_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(8)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(8)='1' then WERTE2_q(8) <= WERTE2_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(7)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(7)='1' then WERTE2_q(7) <= WERTE2_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(6)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(6)='1' then WERTE2_q(6) <= WERTE2_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE2_q(5) <= WERTE2_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(4)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(4)='1' then WERTE2_q(4) <= WERTE2_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE2_q(3) <= WERTE2_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(2)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(2)='1' then WERTE2_q(2) <= WERTE2_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE2_q(1) <= WERTE2_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE2_0_clk_ctrl) BEGIN - IF WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' THEN - IF WERTE2_ena(0)='1' THEN + process (WERTE2_0_clk_ctrl) begin + if WERTE2_0_clk_ctrl'event and WERTE2_0_clk_ctrl='1' then + if WERTE2_ena(0)='1' then WERTE2_q(0) <= WERTE2_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE1_q(63) <= WERTE1_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE1_q(62) <= WERTE1_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE1_q(61) <= WERTE1_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE1_q(60) <= WERTE1_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE1_q(59) <= WERTE1_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE1_q(58) <= WERTE1_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE1_q(57) <= WERTE1_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE1_q(56) <= WERTE1_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE1_q(55) <= WERTE1_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE1_q(54) <= WERTE1_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE1_q(53) <= WERTE1_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE1_q(52) <= WERTE1_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE1_q(51) <= WERTE1_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE1_q(50) <= WERTE1_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE1_q(49) <= WERTE1_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE1_q(48) <= WERTE1_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE1_q(47) <= WERTE1_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE1_q(46) <= WERTE1_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE1_q(45) <= WERTE1_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE1_q(44) <= WERTE1_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE1_q(43) <= WERTE1_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE1_q(42) <= WERTE1_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE1_q(41) <= WERTE1_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE1_q(40) <= WERTE1_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE1_q(39) <= WERTE1_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE1_q(38) <= WERTE1_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE1_q(37) <= WERTE1_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE1_q(36) <= WERTE1_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE1_q(35) <= WERTE1_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE1_q(34) <= WERTE1_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE1_q(33) <= WERTE1_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE1_q(32) <= WERTE1_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE1_q(31) <= WERTE1_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE1_q(30) <= WERTE1_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE1_q(29) <= WERTE1_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE1_q(28) <= WERTE1_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE1_q(27) <= WERTE1_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE1_q(26) <= WERTE1_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE1_q(25) <= WERTE1_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE1_q(24) <= WERTE1_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE1_q(23) <= WERTE1_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE1_q(22) <= WERTE1_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE1_q(21) <= WERTE1_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE1_q(20) <= WERTE1_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE1_q(19) <= WERTE1_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE1_q(18) <= WERTE1_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE1_q(17) <= WERTE1_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE1_q(16) <= WERTE1_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE1_q(15) <= WERTE1_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE1_q(14) <= WERTE1_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(13)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(13)='1' then WERTE1_q(13) <= WERTE1_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE1_q(12) <= WERTE1_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE1_q(11) <= WERTE1_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE1_q(10) <= WERTE1_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(9)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(9)='1' then WERTE1_q(9) <= WERTE1_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(8)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(8)='1' then WERTE1_q(8) <= WERTE1_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(7)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(7)='1' then WERTE1_q(7) <= WERTE1_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(6)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(6)='1' then WERTE1_q(6) <= WERTE1_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE1_q(5) <= WERTE1_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(4)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(4)='1' then WERTE1_q(4) <= WERTE1_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE1_q(3) <= WERTE1_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(2)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(2)='1' then WERTE1_q(2) <= WERTE1_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE1_q(1) <= WERTE1_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE1_0_clk_ctrl) BEGIN - IF WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' THEN - IF WERTE1_ena(0)='1' THEN + process (WERTE1_0_clk_ctrl) begin + if WERTE1_0_clk_ctrl'event and WERTE1_0_clk_ctrl='1' then + if WERTE1_ena(0)='1' then WERTE1_q(0) <= WERTE1_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_63_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_63_ena_ctrl='1' then WERTE0_q(63) <= WERTE0_d(63); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_62_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_62_ena_ctrl='1' then WERTE0_q(62) <= WERTE0_d(62); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_61_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_61_ena_ctrl='1' then WERTE0_q(61) <= WERTE0_d(61); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_60_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_60_ena_ctrl='1' then WERTE0_q(60) <= WERTE0_d(60); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_59_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_59_ena_ctrl='1' then WERTE0_q(59) <= WERTE0_d(59); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_58_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_58_ena_ctrl='1' then WERTE0_q(58) <= WERTE0_d(58); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_57_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_57_ena_ctrl='1' then WERTE0_q(57) <= WERTE0_d(57); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_56_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_56_ena_ctrl='1' then WERTE0_q(56) <= WERTE0_d(56); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_55_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_55_ena_ctrl='1' then WERTE0_q(55) <= WERTE0_d(55); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_54_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_54_ena_ctrl='1' then WERTE0_q(54) <= WERTE0_d(54); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_53_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_53_ena_ctrl='1' then WERTE0_q(53) <= WERTE0_d(53); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_52_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_52_ena_ctrl='1' then WERTE0_q(52) <= WERTE0_d(52); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_51_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_51_ena_ctrl='1' then WERTE0_q(51) <= WERTE0_d(51); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_50_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_50_ena_ctrl='1' then WERTE0_q(50) <= WERTE0_d(50); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_49_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_49_ena_ctrl='1' then WERTE0_q(49) <= WERTE0_d(49); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_48_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_48_ena_ctrl='1' then WERTE0_q(48) <= WERTE0_d(48); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_47_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_47_ena_ctrl='1' then WERTE0_q(47) <= WERTE0_d(47); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_46_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_46_ena_ctrl='1' then WERTE0_q(46) <= WERTE0_d(46); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_45_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_45_ena_ctrl='1' then WERTE0_q(45) <= WERTE0_d(45); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_44_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_44_ena_ctrl='1' then WERTE0_q(44) <= WERTE0_d(44); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_43_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_43_ena_ctrl='1' then WERTE0_q(43) <= WERTE0_d(43); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_42_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_42_ena_ctrl='1' then WERTE0_q(42) <= WERTE0_d(42); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_41_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_41_ena_ctrl='1' then WERTE0_q(41) <= WERTE0_d(41); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_40_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_40_ena_ctrl='1' then WERTE0_q(40) <= WERTE0_d(40); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_39_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_39_ena_ctrl='1' then WERTE0_q(39) <= WERTE0_d(39); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_38_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_38_ena_ctrl='1' then WERTE0_q(38) <= WERTE0_d(38); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_37_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_37_ena_ctrl='1' then WERTE0_q(37) <= WERTE0_d(37); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_36_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_36_ena_ctrl='1' then WERTE0_q(36) <= WERTE0_d(36); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_35_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_35_ena_ctrl='1' then WERTE0_q(35) <= WERTE0_d(35); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_34_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_34_ena_ctrl='1' then WERTE0_q(34) <= WERTE0_d(34); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_33_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_33_ena_ctrl='1' then WERTE0_q(33) <= WERTE0_d(33); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_32_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_32_ena_ctrl='1' then WERTE0_q(32) <= WERTE0_d(32); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_31_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_31_ena_ctrl='1' then WERTE0_q(31) <= WERTE0_d(31); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_30_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_30_ena_ctrl='1' then WERTE0_q(30) <= WERTE0_d(30); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_29_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_29_ena_ctrl='1' then WERTE0_q(29) <= WERTE0_d(29); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_28_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_28_ena_ctrl='1' then WERTE0_q(28) <= WERTE0_d(28); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_27_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_27_ena_ctrl='1' then WERTE0_q(27) <= WERTE0_d(27); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_26_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_26_ena_ctrl='1' then WERTE0_q(26) <= WERTE0_d(26); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_25_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_25_ena_ctrl='1' then WERTE0_q(25) <= WERTE0_d(25); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_24_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_24_ena_ctrl='1' then WERTE0_q(24) <= WERTE0_d(24); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_23_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_23_ena_ctrl='1' then WERTE0_q(23) <= WERTE0_d(23); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_22_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_22_ena_ctrl='1' then WERTE0_q(22) <= WERTE0_d(22); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_21_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_21_ena_ctrl='1' then WERTE0_q(21) <= WERTE0_d(21); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_20_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_20_ena_ctrl='1' then WERTE0_q(20) <= WERTE0_d(20); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_19_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_19_ena_ctrl='1' then WERTE0_q(19) <= WERTE0_d(19); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_18_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_18_ena_ctrl='1' then WERTE0_q(18) <= WERTE0_d(18); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_17_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_17_ena_ctrl='1' then WERTE0_q(17) <= WERTE0_d(17); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_16_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_16_ena_ctrl='1' then WERTE0_q(16) <= WERTE0_d(16); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_15_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_15_ena_ctrl='1' then WERTE0_q(15) <= WERTE0_d(15); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_14_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_14_ena_ctrl='1' then WERTE0_q(14) <= WERTE0_d(14); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(13)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(13)='1' then WERTE0_q(13) <= WERTE0_d(13); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_12_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_12_ena_ctrl='1' then WERTE0_q(12) <= WERTE0_d(12); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_11_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_11_ena_ctrl='1' then WERTE0_q(11) <= WERTE0_d(11); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_10_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_10_ena_ctrl='1' then WERTE0_q(10) <= WERTE0_d(10); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(9)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(9)='1' then WERTE0_q(9) <= WERTE0_d(9); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(8)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(8)='1' then WERTE0_q(8) <= WERTE0_d(8); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(7)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(7)='1' then WERTE0_q(7) <= WERTE0_d(7); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(6)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(6)='1' then WERTE0_q(6) <= WERTE0_d(6); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_5_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_5_ena_ctrl='1' then WERTE0_q(5) <= WERTE0_d(5); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(4)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(4)='1' then WERTE0_q(4) <= WERTE0_d(4); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_3_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_3_ena_ctrl='1' then WERTE0_q(3) <= WERTE0_d(3); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(2)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(2)='1' then WERTE0_q(2) <= WERTE0_d(2); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_1_ena_ctrl='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_1_ena_ctrl='1' then WERTE0_q(1) <= WERTE0_d(1); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (WERTE0_0_clk_ctrl) BEGIN - IF WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' THEN - IF WERTE0_ena(0)='1' THEN + process (WERTE0_0_clk_ctrl) begin + if WERTE0_0_clk_ctrl'event and WERTE0_0_clk_ctrl='1' then + if WERTE0_ena(0)='1' then WERTE0_q(0) <= WERTE0_d(0); - END IF; - END IF; - END PROCESS; + end if; + end if; + end process; - PROCESS (PIC_INT_SYNC0_clk_ctrl) BEGIN - IF PIC_INT_SYNC0_clk_ctrl'event and PIC_INT_SYNC0_clk_ctrl='1' THEN + process (PIC_INT_SYNC0_clk_ctrl) begin + if PIC_INT_SYNC0_clk_ctrl'event and PIC_INT_SYNC0_clk_ctrl='1' then PIC_INT_SYNC_q <= PIC_INT_SYNC_d; - END IF; - END PROCESS; + end if; + end process; -- Start of original equations @@ -5100,7 +5059,7 @@ BEGIN INT_CTR0_clk_ctrl <= MAIN_CLK; -- $10000/4 - INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; + int_ctr_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; INT_CTR_d <= fb_ad_in; INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); @@ -5112,9 +5071,9 @@ BEGIN INT_ENA0_clrn_ctrl <= nRSTO; -- $10004/4 - int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4001"; + int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4001" else '0'; - -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = -- "00000000000100000000000001"); INT_ENA_d <= fb_ad_in; INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); @@ -5127,21 +5086,21 @@ BEGIN -- $10008/4 int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0'; - -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010"); - INT_CLEAR_d(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) + -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000100000000000010"); + INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and + INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); -- INTERRUPT LATCH REGISTER READ ONLY -- $1000C/4 - int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4003"; - -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = + int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4003" else '0'; + -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = -- "00000000000100000000000011"); -- INTERRUPT @@ -5168,17 +5127,17 @@ BEGIN -- # FB_ADR[19..4]==H"F890" -- DMA SOUND -- # FB_ADR[19..4]==H"F891" -- DMA SOUND -- # FB_ADR[19..4]==H"F892" -- DMA SOUND - PSEUDO_BUS_ERROR <= (not nFB_CS1) and (to_std_logic(FB_ADR(19 DOWNTO 4) = - "1111100011001000" or FB_ADR(19 DOWNTO 4) = "1111100011100000" or - FB_ADR(19 DOWNTO 4) = "1111111110101000" or FB_ADR(19 DOWNTO 4) = - "1111111110101001" or FB_ADR(19 DOWNTO 4) = "1111111110101010" or - FB_ADR(19 DOWNTO 4) = "1111111110101000" or FB_ADR(19 DOWNTO 8) = - "111110000111" or FB_ADR(19 DOWNTO 4) = "1111111111000010" or - FB_ADR(19 DOWNTO 4) = "1111111111000011")); + PSEUDO_BUS_ERROR <= (not nFB_CS1) and (to_std_logic(FB_ADR(19 downto 4) = + "1111100011001000" or FB_ADR(19 downto 4) = "1111100011100000" or + FB_ADR(19 downto 4) = "1111111110101000" or FB_ADR(19 downto 4) = + "1111111110101001" or FB_ADR(19 downto 4) = "1111111110101010" or + FB_ADR(19 downto 4) = "1111111110101000" or FB_ADR(19 downto 8) = + "111110000111" or FB_ADR(19 downto 4) = "1111111111000010" or + FB_ADR(19 downto 4) = "1111111111000011")); --- IF VIDEO ADR CHANGE +-- if VIDEO ADR CHANGE -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 - TIN0 <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = + TIN0 <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000") and (not nFB_WR); -- INTERRUPT LATCH @@ -5328,7 +5287,7 @@ BEGIN INT_IN(7) <= DSP_INT; INT_IN(8) <= VSYNC; INT_IN(9) <= HSYNC; - INT_IN(25 DOWNTO 10) <= "0000000000000000"; + INT_IN(25 downto 10) <= "0000000000000000"; INT_IN(26) <= HSYNC; INT_IN(27) <= INT_CTR_q(0); INT_IN(28) <= VSYNC; @@ -5341,7 +5300,7 @@ BEGIN ACP_CONF0_clk_ctrl <= MAIN_CLK; -- $4'0000/4 - ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000010000000000000000"); + ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000010000000000000000"); ACP_CONF_d <= fb_ad_in; ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR); ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR); @@ -5353,13 +5312,13 @@ BEGIN -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR -- -------------------------------------------------------- RTC_ADR0_clk_ctrl <= MAIN_CLK; - RTC_ADR_d <= fb_ad_in(21 DOWNTO 16); + RTC_ADR_d <= fb_ad_in(21 downto 16); -- FFFF8961 - UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110000") and FB_B(1); + UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110000") and FB_B(1); -- FFFF8963 - UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110001") and FB_B(3); + UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110001") and FB_B(3); RTC_ADR0_ena_ctrl <= UHR_AS and (not nFB_WR); WERTE7_0_clk_ctrl <= MAIN_CLK; WERTE6_0_clk_ctrl <= MAIN_CLK; @@ -5371,210 +5330,210 @@ BEGIN WERTE0_0_clk_ctrl <= MAIN_CLK; (WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1, WERTE3_0_d_1, - WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(1), WERTE6_d(1), WERTE5_d(1), WERTE4_d(1), WERTE3_d(1), - WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= fb_ad_in(23 downto 16); (WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1, WERTE3_2_d_1, - WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(3), WERTE6_d(3), WERTE5_d(3), WERTE4_d(3), WERTE3_d(3), - WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= fb_ad_in(23 downto 16); (WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1, WERTE3_4_d_1, - WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(5), WERTE6_d(5), WERTE5_d(5), WERTE4_d(5), WERTE3_d(5), - WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= fb_ad_in(23 downto 16); (WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1, WERTE3_6_d_1, - WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1, WERTE3_7_d_1, - WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1, WERTE3_8_d_1, - WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1, WERTE3_9_d_1, - WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= fb_ad_in(23 DOWNTO 16) and + WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= fb_ad_in(23 downto 16) and sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(10), WERTE6_d(10), WERTE5_d(10), WERTE4_d(10), WERTE3_d(10), - WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= fb_ad_in(23 downto 16); (WERTE7_d(11), WERTE6_d(11), WERTE5_d(11), WERTE4_d(11), WERTE3_d(11), - WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= fb_ad_in(23 DOWNTO 16); + WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= fb_ad_in(23 downto 16); (WERTE7_d(12), WERTE6_d(12), WERTE5_d(12), WERTE4_d(12), WERTE3_d(12), - WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= fb_ad_in(23 downto 16); (WERTE7_13_d_1, WERTE6_d(13), WERTE5_d(13), WERTE4_d(13), WERTE3_d(13), - WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= fb_ad_in(23 downto 16); (WERTE7_d(14), WERTE6_d(14), WERTE5_d(14), WERTE4_d(14), WERTE3_d(14), - WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= fb_ad_in(23 downto 16); (WERTE7_d(15), WERTE6_d(15), WERTE5_d(15), WERTE4_d(15), WERTE3_d(15), - WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= fb_ad_in(23 downto 16); (WERTE7_d(16), WERTE6_d(16), WERTE5_d(16), WERTE4_d(16), WERTE3_d(16), - WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= fb_ad_in(23 downto 16); (WERTE7_d(17), WERTE6_d(17), WERTE5_d(17), WERTE4_d(17), WERTE3_d(17), - WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= fb_ad_in(23 downto 16); (WERTE7_d(18), WERTE6_d(18), WERTE5_d(18), WERTE4_d(18), WERTE3_d(18), - WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= fb_ad_in(23 downto 16); (WERTE7_d(19), WERTE6_d(19), WERTE5_d(19), WERTE4_d(19), WERTE3_d(19), - WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= fb_ad_in(23 downto 16); (WERTE7_d(20), WERTE6_d(20), WERTE5_d(20), WERTE4_d(20), WERTE3_d(20), - WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= fb_ad_in(23 downto 16); (WERTE7_d(21), WERTE6_d(21), WERTE5_d(21), WERTE4_d(21), WERTE3_d(21), - WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= fb_ad_in(23 downto 16); (WERTE7_d(22), WERTE6_d(22), WERTE5_d(22), WERTE4_d(22), WERTE3_d(22), - WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= fb_ad_in(23 downto 16); (WERTE7_d(23), WERTE6_d(23), WERTE5_d(23), WERTE4_d(23), WERTE3_d(23), - WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= fb_ad_in(23 downto 16); (WERTE7_d(24), WERTE6_d(24), WERTE5_d(24), WERTE4_d(24), WERTE3_d(24), - WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= fb_ad_in(23 downto 16); (WERTE7_d(25), WERTE6_d(25), WERTE5_d(25), WERTE4_d(25), WERTE3_d(25), - WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= fb_ad_in(23 downto 16); (WERTE7_d(26), WERTE6_d(26), WERTE5_d(26), WERTE4_d(26), WERTE3_d(26), - WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= fb_ad_in(23 downto 16); (WERTE7_d(27), WERTE6_d(27), WERTE5_d(27), WERTE4_d(27), WERTE3_d(27), - WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= fb_ad_in(23 downto 16); (WERTE7_d(28), WERTE6_d(28), WERTE5_d(28), WERTE4_d(28), WERTE3_d(28), - WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= fb_ad_in(23 downto 16); (WERTE7_d(29), WERTE6_d(29), WERTE5_d(29), WERTE4_d(29), WERTE3_d(29), - WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= fb_ad_in(23 downto 16); (WERTE7_d(30), WERTE6_d(30), WERTE5_d(30), WERTE4_d(30), WERTE3_d(30), - WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= fb_ad_in(23 downto 16); (WERTE7_d(31), WERTE6_d(31), WERTE5_d(31), WERTE4_d(31), WERTE3_d(31), - WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= fb_ad_in(23 downto 16); (WERTE7_d(32), WERTE6_d(32), WERTE5_d(32), WERTE4_d(32), WERTE3_d(32), - WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= fb_ad_in(23 downto 16); (WERTE7_d(33), WERTE6_d(33), WERTE5_d(33), WERTE4_d(33), WERTE3_d(33), - WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= fb_ad_in(23 downto 16); (WERTE7_d(34), WERTE6_d(34), WERTE5_d(34), WERTE4_d(34), WERTE3_d(34), - WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= fb_ad_in(23 downto 16); (WERTE7_d(35), WERTE6_d(35), WERTE5_d(35), WERTE4_d(35), WERTE3_d(35), - WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= fb_ad_in(23 downto 16); (WERTE7_d(36), WERTE6_d(36), WERTE5_d(36), WERTE4_d(36), WERTE3_d(36), - WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= fb_ad_in(23 downto 16); (WERTE7_d(37), WERTE6_d(37), WERTE5_d(37), WERTE4_d(37), WERTE3_d(37), - WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= fb_ad_in(23 downto 16); (WERTE7_d(38), WERTE6_d(38), WERTE5_d(38), WERTE4_d(38), WERTE3_d(38), - WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= fb_ad_in(23 downto 16); (WERTE7_d(39), WERTE6_d(39), WERTE5_d(39), WERTE4_d(39), WERTE3_d(39), - WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= fb_ad_in(23 downto 16); (WERTE7_d(40), WERTE6_d(40), WERTE5_d(40), WERTE4_d(40), WERTE3_d(40), - WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= fb_ad_in(23 downto 16); (WERTE7_d(41), WERTE6_d(41), WERTE5_d(41), WERTE4_d(41), WERTE3_d(41), - WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= fb_ad_in(23 downto 16); (WERTE7_d(42), WERTE6_d(42), WERTE5_d(42), WERTE4_d(42), WERTE3_d(42), - WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= fb_ad_in(23 downto 16); (WERTE7_d(43), WERTE6_d(43), WERTE5_d(43), WERTE4_d(43), WERTE3_d(43), - WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= fb_ad_in(23 downto 16); (WERTE7_d(44), WERTE6_d(44), WERTE5_d(44), WERTE4_d(44), WERTE3_d(44), - WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= fb_ad_in(23 downto 16); (WERTE7_d(45), WERTE6_d(45), WERTE5_d(45), WERTE4_d(45), WERTE3_d(45), - WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= fb_ad_in(23 downto 16); (WERTE7_d(46), WERTE6_d(46), WERTE5_d(46), WERTE4_d(46), WERTE3_d(46), - WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= fb_ad_in(23 downto 16); (WERTE7_d(47), WERTE6_d(47), WERTE5_d(47), WERTE4_d(47), WERTE3_d(47), - WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= fb_ad_in(23 downto 16); (WERTE7_d(48), WERTE6_d(48), WERTE5_d(48), WERTE4_d(48), WERTE3_d(48), - WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= fb_ad_in(23 downto 16); (WERTE7_d(49), WERTE6_d(49), WERTE5_d(49), WERTE4_d(49), WERTE3_d(49), - WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= fb_ad_in(23 downto 16); (WERTE7_d(50), WERTE6_d(50), WERTE5_d(50), WERTE4_d(50), WERTE3_d(50), - WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= fb_ad_in(23 downto 16); (WERTE7_d(51), WERTE6_d(51), WERTE5_d(51), WERTE4_d(51), WERTE3_d(51), - WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= fb_ad_in(23 downto 16); (WERTE7_d(52), WERTE6_d(52), WERTE5_d(52), WERTE4_d(52), WERTE3_d(52), - WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= fb_ad_in(23 downto 16); (WERTE7_d(53), WERTE6_d(53), WERTE5_d(53), WERTE4_d(53), WERTE3_d(53), - WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= fb_ad_in(23 downto 16); (WERTE7_d(54), WERTE6_d(54), WERTE5_d(54), WERTE4_d(54), WERTE3_d(54), - WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= fb_ad_in(23 downto 16); (WERTE7_d(55), WERTE6_d(55), WERTE5_d(55), WERTE4_d(55), WERTE3_d(55), - WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= fb_ad_in(23 downto 16); (WERTE7_d(56), WERTE6_d(56), WERTE5_d(56), WERTE4_d(56), WERTE3_d(56), - WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= fb_ad_in(23 downto 16); (WERTE7_d(57), WERTE6_d(57), WERTE5_d(57), WERTE4_d(57), WERTE3_d(57), - WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= fb_ad_in(23 downto 16); (WERTE7_d(58), WERTE6_d(58), WERTE5_d(58), WERTE4_d(58), WERTE3_d(58), - WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= fb_ad_in(23 downto 16); (WERTE7_d(59), WERTE6_d(59), WERTE5_d(59), WERTE4_d(59), WERTE3_d(59), - WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= fb_ad_in(23 downto 16); (WERTE7_d(60), WERTE6_d(60), WERTE5_d(60), WERTE4_d(60), WERTE3_d(60), - WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= fb_ad_in(23 downto 16); (WERTE7_d(61), WERTE6_d(61), WERTE5_d(61), WERTE4_d(61), WERTE3_d(61), - WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= fb_ad_in(23 downto 16); (WERTE7_d(62), WERTE6_d(62), WERTE5_d(62), WERTE4_d(62), WERTE3_d(62), - WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= fb_ad_in(23 downto 16); (WERTE7_d(63), WERTE6_d(63), WERTE5_d(63), WERTE4_d(63), WERTE3_d(63), - WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= fb_ad_in(23 DOWNTO 16); + WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= fb_ad_in(23 downto 16); (WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1, WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1) <= @@ -6002,14 +5961,22 @@ BEGIN "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); -- TRISTATE OUTPUT - u0_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(31 DOWNTO 24)) or - (sizeIt(INT_ENA_CS,8) and INT_ENA_q(31 DOWNTO 24)) or - (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(31 DOWNTO 24)) or - (sizeIt(INT_CLEAR_CS,8) and INT_IN(31 DOWNTO 24)) or - (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(31 DOWNTO 24)); - u0_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or - ACP_CONF_CS) and (not nFB_OE); - fb_ad_out(31 DOWNTO 24) <= u0_tridata; +-- u0_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(31 downto 24)) or +-- (sizeIt(INT_ENA_CS,8) and INT_ENA_q(31 downto 24)) or +-- (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(31 downto 24)) or +-- (sizeIt(INT_CLEAR_CS,8) and INT_IN(31 downto 24)) or +-- (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(31 downto 24)); +-- u0_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or +-- ACP_CONF_CS) and (not nFB_OE); +-- fb_ad_out(31 downto 24) <= u0_tridata; + + fb_ad_out(31 downto 24) <= int_ctr_q(31 downto 24) when int_ctr_cs and not nfb_oe else + int_ena_q(31 downto 24) when int_ena_cs and not nfb_oe else + int_latch_q(31 downto 24) when int_latch_cs and not nfb_oe else + int_clear_q(31 downto 24) when int_clear_cs and not nfb_oe else + acp_conf_q(31 downto 24) when acp_conf_cs and not nfb_oe else + (others => 'Z'); + u1_data <= (std_logic_vector'(WERTE7_q(0) & WERTE6_q(0) & WERTE5_q(0) & WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & WERTE1_q(0) & WERTE0_q(0)) and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8)) @@ -6221,31 +6188,48 @@ BEGIN WERTE2_q(63) & WERTE1_q(63) & WERTE0_q(63)) and sizeIt(to_std_logic(RTC_ADR_q = "111111"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'("00" & RTC_ADR_q) and sizeIt(UHR_AS,8)) or - (sizeIt(INT_CTR_CS,8) and INT_CTR_q(23 DOWNTO 16)) or - (sizeIt(INT_ENA_CS,8) and INT_ENA_q(23 DOWNTO 16)) or - (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(23 DOWNTO 16)) or - (sizeIt(INT_CLEAR_CS,8) and INT_IN(23 DOWNTO 16)) or - (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(23 DOWNTO 16)); - u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS - or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - fb_ad_out(23 DOWNTO 16) <= u1_tridata; - u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 DOWNTO 8)) or - (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 DOWNTO 8)) or - (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 DOWNTO 8)) or - (sizeIt(INT_CLEAR_CS,8) and INT_IN(15 DOWNTO 8)) or - (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(15 DOWNTO 8)); - u2_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or - ACP_CONF_CS) and (not nFB_OE); - fb_ad_out(15 DOWNTO 8) <= u2_tridata; - u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 DOWNTO 0)) or - (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 DOWNTO 0)) or - (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 DOWNTO 0)) or - (sizeIt(INT_CLEAR_CS,8) and INT_IN(7 DOWNTO 0)) or - (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(7 DOWNTO 0)); - u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or - ACP_CONF_CS) and (not nFB_OE); - fb_ad_out(7 DOWNTO 0) <= u3_tridata; - INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs; + (sizeIt(INT_CTR_CS,8) and INT_CTR_q(23 downto 16)) or + (sizeIt(INT_ENA_CS,8) and INT_ENA_q(23 downto 16)) or + (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(23 downto 16)) or + (sizeIt(INT_CLEAR_CS,8) and INT_IN(23 downto 16)) or + (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(23 downto 16)); + + u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); + fb_ad_out(23 downto 16) <= u1_tridata; + +-- u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 downto 8)) or +-- (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 downto 8)) or +-- (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 downto 8)) or +-- (sizeIt(INT_CLEAR_CS,8) and INT_IN(15 downto 8)) or +-- (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(15 downto 8)); +-- u2_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or +-- ACP_CONF_CS) and (not nFB_OE); +-- fb_ad_out(15 downto 8) <= u2_tridata; + + fb_ad_out(15 downto 8) <= int_ctr_q(15 downto 8) when int_ctr_cs and not nfb_oe else + int_ena_q(15 downto 8) when int_ena_cs and not nfb_oe else + int_latch_q(15 downto 8) when int_latch_cs and not nfb_oe else + int_clear_q(15 downto 8) when int_clear_cs and not nfb_oe else + acp_conf_q(15 downto 8) when acp_conf_cs and not nfb_oe else + (others => 'Z'); + +-- u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 downto 0)) or +-- (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 downto 0)) or +-- (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 downto 0)) or +-- (sizeIt(INT_CLEAR_CS,8) and INT_IN(7 downto 0)) or +-- (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(7 downto 0)); +-- u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or +-- ACP_CONF_CS) and (not nFB_OE); +-- fb_ad_out(7 downto 0) <= u3_tridata; + + fb_ad_out(7 downto 0) <= int_ctr_q(7 downto 0) when int_ctr_cs and not nfb_oe else + int_ena_q(7 downto 0) when int_ena_cs and not nfb_oe else + int_latch_q(7 downto 0) when int_latch_cs and not nfb_oe else + int_clear_q(7 downto 0) when int_clear_cs and not nfb_oe else + acp_conf_q(7 downto 0) when acp_conf_cs and not nfb_oe else + (others => 'Z'); + + int_handler_ta <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs or acp_conf_cs; -- Assignments added to explicitly combine the @@ -6370,7 +6354,7 @@ BEGIN WERTE7_d(9) <= WERTE7_9_d_1 or WERTE7_9_d_2; WERTE7_d(13) <= WERTE7_13_d_1 or WERTE7_13_d_2; --- Define power SIGNAL(s) +-- Define power signal(s) vcc <= '1'; gnd <= '0'; -END ; +end ; From 80880574d852655fc6ecfdf1561426fcebbcf673 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 15:41:03 +0000 Subject: [PATCH 108/127] cleanup interrupt handler chip selects --- .../Interrupt_Handler/interrupt_handler.vhd | 223 +++++++++--------- 1 file changed, 113 insertions(+), 110 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 96ffa57..b88570c 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -5030,87 +5030,91 @@ begin -- HWORD -- HHBYT -- LONG UND LINE - FB_B(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or ((not - FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and (not FB_ADR(0))) or - ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + FB_B(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or + ((not FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and (not FB_ADR(0))) or + ((not FB_SIZE1) and (not FB_SIZE0)) or + (FB_SIZE1 and FB_SIZE0); -- HWORD -- HLBYT -- LONG UND LINE - FB_B(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or ((not - FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and FB_ADR(0)) or ((not - FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + FB_B(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or + ((not FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and FB_ADR(0)) or + ((not FB_SIZE1) and (not FB_SIZE0)) or + (FB_SIZE1 and FB_SIZE0); -- LWORD -- LHBYT -- LONG UND LINE - FB_B(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or ((not FB_SIZE1) - and FB_SIZE0 and FB_ADR(1) and (not FB_ADR(0))) or ((not FB_SIZE1) and - (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + FB_B(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or + ((not FB_SIZE1) and FB_SIZE0 and FB_ADR(1) and (not FB_ADR(0))) or + ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); -- LWORD -- LLBYT -- LONG UND LINE - FB_B(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or ((not FB_SIZE1) - and FB_SIZE0 and FB_ADR(1) and FB_ADR(0)) or ((not FB_SIZE1) and (not - FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); + FB_B(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or + ((not FB_SIZE1) and FB_SIZE0 and FB_ADR(1) and FB_ADR(0)) or + ((not FB_SIZE1) and (not FB_SIZE0)) or + (FB_SIZE1 and FB_SIZE0); -- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN - INT_CTR0_clk_ctrl <= MAIN_CLK; + INT_CTR0_clk_ctrl <= MAIN_CLK; -- $10000/4 - int_ctr_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; - INT_CTR_d <= fb_ad_in; - INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); - INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); - INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR); - INT_CTR0_ena_ctrl <= INT_CTR_CS and FB_B(3) and (not nFB_WR); + int_ctr_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; + INT_CTR_d <= fb_ad_in; + INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); + INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); + INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR); + INT_CTR0_ena_ctrl <= INT_CTR_CS and FB_B(3) and (not nFB_WR); -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 - INT_ENA0_clk_ctrl <= MAIN_CLK; - INT_ENA0_clrn_ctrl <= nRSTO; + INT_ENA0_clk_ctrl <= MAIN_CLK; + INT_ENA0_clrn_ctrl <= nRSTO; -- $10004/4 int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4001" else '0'; -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = -- "00000000000100000000000001"); - INT_ENA_d <= fb_ad_in; - INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); - INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); - INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR); - INT_ENA0_ena_ctrl <= INT_ENA_CS and FB_B(3) and (not nFB_WR); + INT_ENA_d <= fb_ad_in; + INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); + INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); + INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR); + INT_ENA0_ena_ctrl <= INT_ENA_CS and FB_B(3) and (not nFB_WR); -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR - INT_CLEAR0_clk_ctrl <= MAIN_CLK; + INT_CLEAR0_clk_ctrl <= MAIN_CLK; -- $10008/4 int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0'; -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000100000000000010"); - INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) - and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) - and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) - and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and - sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); + + int_clear_d(31 downto 24) <= fb_ad_in(31 downto 24) when int_clear_cs and fb_b(0) and not nfb_wr; + int_clear_d(23 downto 16) <= fb_ad_in(23 downto 16) when int_clear_cs and fb_b(1) and not nfb_wr; + int_clear_d(15 downto 8) <= fb_ad_in(15 downto 8) when int_clear_cs and fb_b(2) and not nfb_wr; + int_clear_d(7 downto 0) <= fb_ad_in(7 downto 0) when int_clear_cs and fb_b(3) and not nfb_wr; + + +-- INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); -- INTERRUPT LATCH REGISTER READ ONLY -- $1000C/4 int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4003" else '0'; - -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = - -- "00000000000100000000000011"); + -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000100000000000011"); -- INTERRUPT - nIRQ(2) <= not (HSYNC and INT_ENA_q(26)); - nIRQ(3) <= not (INT_CTR_q(0) and INT_ENA_q(27)); - nIRQ(4) <= not (VSYNC and INT_ENA_q(28)); - nIRQ(5) <= not (to_std_logic(INT_LATCH_q /= - "00000000000000000000000000000000") and INT_ENA_q(29)); - nIRQ(6) <= not ((not nMFP_INT) and INT_ENA_q(30)); - nIRQ(7) <= not (PSEUDO_BUS_ERROR and INT_ENA_q(31)); + nIRQ(2) <= not (HSYNC and INT_ENA_q(26)); + nIRQ(3) <= not (INT_CTR_q(0) and INT_ENA_q(27)); + nIRQ(4) <= not (VSYNC and INT_ENA_q(28)); + nIRQ(5) <= not (to_std_logic(INT_LATCH_q /= "00000000000000000000000000000000") and INT_ENA_q(29)); + nIRQ(6) <= not ((not nMFP_INT) and INT_ENA_q(30)); + nIRQ(7) <= not (PSEUDO_BUS_ERROR and INT_ENA_q(31)); -- SCC -- VME @@ -5127,79 +5131,78 @@ begin -- # FB_ADR[19..4]==H"F890" -- DMA SOUND -- # FB_ADR[19..4]==H"F891" -- DMA SOUND -- # FB_ADR[19..4]==H"F892" -- DMA SOUND - PSEUDO_BUS_ERROR <= (not nFB_CS1) and (to_std_logic(FB_ADR(19 downto 4) = - "1111100011001000" or FB_ADR(19 downto 4) = "1111100011100000" or - FB_ADR(19 downto 4) = "1111111110101000" or FB_ADR(19 downto 4) = - "1111111110101001" or FB_ADR(19 downto 4) = "1111111110101010" or - FB_ADR(19 downto 4) = "1111111110101000" or FB_ADR(19 downto 8) = - "111110000111" or FB_ADR(19 downto 4) = "1111111111000010" or - FB_ADR(19 downto 4) = "1111111111000011")); + PSEUDO_BUS_ERROR <= (not nFB_CS1) and (to_std_logic(FB_ADR(19 downto 4) = "1111100011001000" or + FB_ADR(19 downto 4) = "1111100011100000" or + FB_ADR(19 downto 4) = "1111111110101000" or + FB_ADR(19 downto 4) = "1111111110101001" or + FB_ADR(19 downto 4) = "1111111110101010" or + FB_ADR(19 downto 4) = "1111111110101000" or + FB_ADR(19 downto 8) = "111110000111" or + FB_ADR(19 downto 4) = "1111111111000010" or + FB_ADR(19 downto 4) = "1111111111000011")); -- if VIDEO ADR CHANGE -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 - TIN0 <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = - "1111100000100000000") and (not nFB_WR); + TIN0 <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100000000") and (not nFB_WR); -- INTERRUPT LATCH - INT_L0_clk_ctrl <= MAIN_CLK; - INT_L0_clrn_ctrl <= nRSTO; - INT_L_d(0) <= PIC_INT and INT_ENA_q(0); - INT_L_d(1) <= E0_INT and INT_ENA_q(1); - INT_L_d(2) <= DVI_INT and INT_ENA_q(2); - INT_L_d(3) <= (not nPCI_INTA) and INT_ENA_q(3); - INT_L_d(4) <= (not nPCI_INTB) and INT_ENA_q(4); - INT_L_d(5) <= (not nPCI_INTC) and INT_ENA_q(5); - INT_L_d(6) <= (not nPCI_INTD) and INT_ENA_q(6); - INT_L_d(7) <= DSP_INT and INT_ENA_q(7); - INT_L_d(8) <= VSYNC and INT_ENA_q(8); - INT_L_d(9) <= HSYNC and INT_ENA_q(9); - INT_LA9_0_clk_ctrl <= MAIN_CLK; - INT_LA8_0_clk_ctrl <= MAIN_CLK; - INT_LA7_0_clk_ctrl <= MAIN_CLK; - INT_LA6_0_clk_ctrl <= MAIN_CLK; - INT_LA5_0_clk_ctrl <= MAIN_CLK; - INT_LA4_0_clk_ctrl <= MAIN_CLK; - INT_LA3_0_clk_ctrl <= MAIN_CLK; - INT_LA2_0_clk_ctrl <= MAIN_CLK; - INT_LA1_0_clk_ctrl <= MAIN_CLK; - INT_LA0_0_clk_ctrl <= MAIN_CLK; - INT_LATCH_d <= "11111111111111111111111111111111"; - INT_LATCH_clrn <= (not INT_CLEAR_q) and sizeIt(nRSTO,32); - INT_LA0_0_clrn_ctrl <= INT_ENA_q(0) and nRSTO; - INT_LA0_d <= ((std_logic_vector'(unsigned(INT_LA0_q) + unsigned'("0001"))) - and sizeIt(INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q) - < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA0_q) - - unsigned'("0001"))) and sizeIt(not INT_L_q(0),4) and - sizeIt(to_std_logic((unsigned(INT_LA0_q) > unsigned'("1000"))),4)) or - ("1111" and sizeIt(INT_L_q(0),4) and - sizeIt(to_std_logic((unsigned(INT_LA0_q) > unsigned'("0110"))),4)) or - ("0000" and sizeIt(not INT_L_q(0),4) and - sizeIt(to_std_logic((unsigned(INT_LA0_q) < unsigned'("1001"))),4)); - INT_LATCH0_clk_1 <= INT_LA0_q(3); - INT_LA1_0_clrn_ctrl <= INT_ENA_q(1) and nRSTO; - INT_LA1_d <= ((std_logic_vector'(unsigned(INT_LA1_q) + unsigned'("0001"))) - and sizeIt(INT_L_q(1),4) and sizeIt(to_std_logic((unsigned(INT_LA1_q) - < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA1_q) - - unsigned'("0001"))) and sizeIt(not INT_L_q(1),4) and - sizeIt(to_std_logic((unsigned(INT_LA1_q) > unsigned'("1000"))),4)) or - ("1111" and sizeIt(INT_L_q(1),4) and - sizeIt(to_std_logic((unsigned(INT_LA1_q) > unsigned'("0110"))),4)) or - ("0000" and sizeIt(not INT_L_q(1),4) and - sizeIt(to_std_logic((unsigned(INT_LA1_q) < unsigned'("1001"))),4)); - INT_LATCH1_clk_1 <= INT_LA1_q(3); + INT_L0_clk_ctrl <= MAIN_CLK; + INT_L0_clrn_ctrl <= nRSTO; + INT_L_d(0) <= PIC_INT and INT_ENA_q(0); + INT_L_d(1) <= E0_INT and INT_ENA_q(1); + INT_L_d(2) <= DVI_INT and INT_ENA_q(2); + INT_L_d(3) <= (not nPCI_INTA) and INT_ENA_q(3); + INT_L_d(4) <= (not nPCI_INTB) and INT_ENA_q(4); + INT_L_d(5) <= (not nPCI_INTC) and INT_ENA_q(5); + INT_L_d(6) <= (not nPCI_INTD) and INT_ENA_q(6); + INT_L_d(7) <= DSP_INT and INT_ENA_q(7); + INT_L_d(8) <= VSYNC and INT_ENA_q(8); + INT_L_d(9) <= HSYNC and INT_ENA_q(9); + INT_LA9_0_clk_ctrl <= MAIN_CLK; + INT_LA8_0_clk_ctrl <= MAIN_CLK; + INT_LA7_0_clk_ctrl <= MAIN_CLK; + INT_LA6_0_clk_ctrl <= MAIN_CLK; + INT_LA5_0_clk_ctrl <= MAIN_CLK; + INT_LA4_0_clk_ctrl <= MAIN_CLK; + INT_LA3_0_clk_ctrl <= MAIN_CLK; + INT_LA2_0_clk_ctrl <= MAIN_CLK; + INT_LA1_0_clk_ctrl <= MAIN_CLK; + INT_LA0_0_clk_ctrl <= MAIN_CLK; + INT_LATCH_d <= "11111111111111111111111111111111"; + INT_LATCH_clrn <= (not INT_CLEAR_q) and sizeIt(nRSTO,32); + INT_LA0_0_clrn_ctrl <= INT_ENA_q(0) and nRSTO; + INT_LA0_d <= ((std_logic_vector'(unsigned(INT_LA0_q) + unsigned'("0001"))) and sizeIt(INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA0_q) - unsigned'("0001"))) and sizeIt(not INT_L_q(0),4) and + sizeIt(to_std_logic((unsigned(INT_LA0_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q) < unsigned'("1001"))),4)); + INT_LATCH0_clk_1 <= INT_LA0_q(3); + INT_LA1_0_clrn_ctrl <= INT_ENA_q(1) and nRSTO; + INT_LA1_d <= ((std_logic_vector'(unsigned(INT_LA1_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(1),4) and sizeIt(to_std_logic((unsigned(INT_LA1_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA1_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(1),4) and + sizeIt(to_std_logic((unsigned(INT_LA1_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(1),4) and + sizeIt(to_std_logic((unsigned(INT_LA1_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(1),4) and + sizeIt(to_std_logic((unsigned(INT_LA1_q) < unsigned'("1001"))),4)); + INT_LATCH1_clk_1 <= INT_LA1_q(3); + INT_LA2_0_clrn_ctrl <= INT_ENA_q(2) and nRSTO; INT_LA2_d <= ((std_logic_vector'(unsigned(INT_LA2_q) + unsigned'("0001"))) - and sizeIt(INT_L_q(2),4) and sizeIt(to_std_logic((unsigned(INT_LA2_q) - < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA2_q) - - unsigned'("0001"))) and sizeIt(not INT_L_q(2),4) and - sizeIt(to_std_logic((unsigned(INT_LA2_q) > unsigned'("1000"))),4)) or - ("1111" and sizeIt(INT_L_q(2),4) and - sizeIt(to_std_logic((unsigned(INT_LA2_q) > unsigned'("0110"))),4)) or - ("0000" and sizeIt(not INT_L_q(2),4) and - sizeIt(to_std_logic((unsigned(INT_LA2_q) < unsigned'("1001"))),4)); - INT_LATCH2_clk_1 <= INT_LA2_q(3); - INT_LA3_0_clrn_ctrl <= INT_ENA_q(3) and nRSTO; - INT_LA3_d <= ((std_logic_vector'(unsigned(INT_LA3_q) + unsigned'("0001"))) + and sizeIt(INT_L_q(2),4) and sizeIt(to_std_logic((unsigned(INT_LA2_q) + < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA2_q) - + unsigned'("0001"))) and sizeIt(not INT_L_q(2),4) and + sizeIt(to_std_logic((unsigned(INT_LA2_q) > unsigned'("1000"))),4)) or + ("1111" and sizeIt(INT_L_q(2),4) and + sizeIt(to_std_logic((unsigned(INT_LA2_q) > unsigned'("0110"))),4)) or + ("0000" and sizeIt(not INT_L_q(2),4) and + sizeIt(to_std_logic((unsigned(INT_LA2_q) < unsigned'("1001"))),4)); + + INT_LATCH2_clk_1 <= INT_LA2_q(3); + INT_LA3_0_clrn_ctrl <= INT_ENA_q(3) and nRSTO; + INT_LA3_d <= ((std_logic_vector'(unsigned(INT_LA3_q) + unsigned'("0001"))) and sizeIt(INT_L_q(3),4) and sizeIt(to_std_logic((unsigned(INT_LA3_q) < unsigned'("0111"))),4)) or ((std_logic_vector'(unsigned(INT_LA3_q) - unsigned'("0001"))) and sizeIt(not INT_L_q(3),4) and From 4e6efb55fc3900284d56ef212e298b350e732ed0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 16:39:46 +0000 Subject: [PATCH 109/127] add missing file --- FPGA_Quartus_13.1/firebee_utils_pkg.vhd | 170 ++++++++++++++++++++++++ 1 file changed, 170 insertions(+) create mode 100644 FPGA_Quartus_13.1/firebee_utils_pkg.vhd diff --git a/FPGA_Quartus_13.1/firebee_utils_pkg.vhd b/FPGA_Quartus_13.1/firebee_utils_pkg.vhd new file mode 100644 index 0000000..4283606 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee_utils_pkg.vhd @@ -0,0 +1,170 @@ +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://acp.atari.org ---- +---- ---- +---- Description: ---- +---- This package contains utility functions, procedures and constants +---- for the Firebee project. +---- +---- Author(s): ---- +---- - Markus Froeschle, mfro@mubf.de +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2015 Markus Froeschle +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +package firebee_utils_pkg is + function f_addr_cmp_l(signal addr : std_logic_vector; constant addr_const : std_logic_vector) return std_logic; + function f_addr_cmp_w(signal addr : std_logic_vector; constant addr_const : std_logic_vector) return std_logic; + function f_addr_cmp_b(signal addr : std_logic_vector; constant addr_const : std_logic_vector) return std_logic; + function f_addr_cmp_mask(signal addr : std_logic_vector; constant addr_const : std_logic_vector; constant num_ignore : integer) return std_logic; + + function max(left : integer; right : integer) return integer; + function min(left : integer; right : integer) return integer; + + component synchronizer IS + PORT + ( + -- Input ports + source_signal : in std_logic; + + target_clock : in std_logic; + target_signal : out std_logic + ); + end component synchronizer; + + -- size constants for the TSIZE vector + type tsize_t is (SIZE_LONG, SIZE_WORD, SIZE_BYTE, SIZE_LINE, SIZE_TRISTATE); + attribute enum_encoding : string; + attribute enum_encoding of tsize_t: type is "00 10 01 11 ZZ"; +-- constant SIZE_LONG : std_logic_vector(1 downto 0) := "00"; +-- constant SIZE_WORD : std_logic_vector(1 downto 0) := "10"; +-- constant SIZE_BYTE : std_logic_vector(1 downto 0) := "01"; +-- constant SIZE_LINE : std_logic_vector(1 downto 0) := "11"; +end firebee_utils_pkg; + +package body firebee_utils_pkg is + -- returns the smaller of two integers + function min(left : integer; right : integer) return integer is + begin + if left < right then + return left; + else + return right; + end if; + end function min; + + -- returns the larger of two integers + function max(left : integer; right : integer) return integer is + begin + if left > right then + return left; + else + return right; + end if; + end function max; + + -- returns the number of bits needed to represent n + function log2ceil(n : natural) return natural is + variable n_bit : unsigned(31 downto 0); + begin -- log2ceil + if n = 0 then + return 0; + end if; + n_bit := to_unsigned(n-1,32); + for i in 31 downto 0 loop + if n_bit(i) = '1' then + return i + 1; + end if; + end loop; -- i + return 1; + end log2ceil; + + -- this is for arbitrary sized address compares. It compares from the highest bit of addr_const to the lowest - num_ignore + -- bit, thus allowing any size of comparision. + function f_addr_cmp_mask(signal addr : std_logic_vector; + constant addr_const : std_logic_vector; + constant num_ignore : integer + ) return std_logic is + variable ret : std_logic := '1'; + variable hi : integer; + variable lo : integer; + begin + hi := min(addr_const'high, addr'high); + lo := max(addr_const'low, addr'low); + + -- report("faddr_cmp_mask(): hi = " & to_string(hi) & " lo = " & to_string(lo) & " log2ceil(num_ignore) = " & to_string(log2ceil(num_ignore))); + l_loop: for i in hi downto lo + log2ceil(num_ignore) - 1 loop + if addr(i) /= addr_const(i) then + + -- synthesis translate_off + -- report("f_addr_cmp_mask(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & + -- " at bit = " & integer'image(i)); + -- report("addr(" & integer'image(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & + -- " addr_const(" & integer'image(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); + -- synthesis translate_on + + ret := '0'; + exit l_loop; + else + -- pragma synthesis off + -- report("f_addr_cmp_mask(): addr = " & to_hstring(unsigned(addr)) & " equals to addr_const = " & to_hstring(unsigned(addr_const)) & + -- " at bit = " & integer'image(i)); + -- report("addr(" & integer'image(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & + -- " addr_const(" & integer'image(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); + -- pragma synthesis on + end if; + end loop; + -- pragma synthesis off + report("f_addr_cmp_mask(" & to_hstring(unsigned(addr)) & ", " & to_hstring(unsigned(addr_const)) & "): return " & to_string(ret)); + -- pragma synthesis on + return ret; + end function f_addr_cmp_mask; + + + function f_addr_cmp_l(signal addr : std_logic_vector; + constant addr_const : std_logic_vector + ) return std_logic is + begin + return f_addr_cmp_mask(addr, addr_const, 2); + end function f_addr_cmp_l; + + function f_addr_cmp_w(signal addr : std_logic_vector; + constant addr_const : std_logic_vector + ) return std_logic is + begin + return f_addr_cmp_mask(addr, addr_const, 1); + end function f_addr_cmp_w; + + function f_addr_cmp_b(signal addr : std_logic_vector; + constant addr_const : std_logic_vector + ) return std_logic is + begin + return f_addr_cmp_mask(addr, addr_const, 0); + end function f_addr_cmp_b; +end package body firebee_utils_pkg; \ No newline at end of file From 479861c1c08d89289d2a7dbdec5afce021288347 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 21:05:55 +0000 Subject: [PATCH 110/127] fix hold time violations in .sdc --- FPGA_Quartus_13.1/altpll1.qip | 3 - FPGA_Quartus_13.1/altpll1.vhd | 27 +- FPGA_Quartus_13.1/firebee1.qsf | 1492 +++++++++++++------------- FPGA_Quartus_13.1/firebee1.vhd | 307 +++--- FPGA_Quartus_13.1/firebee_groups.sdc | 7 + 5 files changed, 919 insertions(+), 917 deletions(-) diff --git a/FPGA_Quartus_13.1/altpll1.qip b/FPGA_Quartus_13.1/altpll1.qip index 01791b7..27ede3b 100644 --- a/FPGA_Quartus_13.1/altpll1.qip +++ b/FPGA_Quartus_13.1/altpll1.qip @@ -1,7 +1,4 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" set_global_assignment -name IP_TOOL_VERSION "13.1" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"] diff --git a/FPGA_Quartus_13.1/altpll1.vhd b/FPGA_Quartus_13.1/altpll1.vhd index 3019552..4d3c142 100644 --- a/FPGA_Quartus_13.1/altpll1.vhd +++ b/FPGA_Quartus_13.1/altpll1.vhd @@ -80,7 +80,6 @@ ARCHITECTURE SYN OF altpll1 IS clk2_duty_cycle : NATURAL; clk2_multiply_by : NATURAL; clk2_phase_shift : STRING; - compensate_clock : STRING; inclk0_input_frequency : NATURAL; intended_device_family : STRING; lpm_type : STRING; @@ -152,7 +151,7 @@ BEGIN altpll_component : altpll GENERIC MAP ( - bandwidth_type => "AUTO", + bandwidth_type => "LOW", clk0_divide_by => 11, clk0_duty_cycle => 50, clk0_multiply_by => 16, @@ -165,11 +164,10 @@ BEGIN clk2_duty_cycle => 50, clk2_multiply_by => 1024, clk2_phase_shift => "0", - compensate_clock => "CLK0", inclk0_input_frequency => 30303, intended_device_family => "Cyclone III", lpm_type => "altpll", - operation_mode => "SOURCE_SYNCHRONOUS", + operation_mode => "NO_COMPENSATION", pll_type => "AUTO", port_activeclock => "PORT_UNUSED", port_areset => "PORT_UNUSED", @@ -233,12 +231,12 @@ END SYN; -- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" -- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1" -- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" @@ -321,7 +319,7 @@ END SYN; -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" @@ -337,7 +335,7 @@ END SYN; -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" @@ -350,11 +348,10 @@ END SYN; -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION" -- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" @@ -414,10 +411,10 @@ END SYN; -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 5b8eadb..5353743 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,312 +556,312 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 8883449..fbce6a1 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -16,7 +16,7 @@ entity firebee1 is nFB_CS3 : in std_logic; FB_SIZE0 : in std_logic; FB_SIZE1 : in std_logic; - nFB_BURST : in std_logic; + nFB_BURST : in std_logic; LP_BUSY : in std_logic; nACSI_DRQ : in std_logic; nACSI_INT : in std_logic; @@ -148,45 +148,45 @@ entity firebee1 is end firebee1; architecture rtl of firebee1 is - signal ACP_CONF : std_logic_vector(31 downto 0); + signal acp_conf : std_logic_vector(31 downto 0); signal clk25m_i : std_logic; - signal CLK2M : std_logic; - signal CLK2M4576 : std_logic; - signal CLK33M : std_logic; - signal CLK48M : std_logic; - signal CLK500k : std_logic; - signal CLK_VIDEO : std_logic; - signal DDR_SYNC_66M : std_logic; - signal DDRCLK : std_logic_vector(3 downto 0); - signal DMA_DRQ : std_logic; - signal DSP_INT : std_logic; - signal DSP_TA : std_logic; - signal FALCON_IO_TA : std_logic; - signal FB_ADR : std_logic_vector(31 downto 0); - signal FDC_CLK : std_logic; - signal HSYNC : std_logic; - signal INT_HANDLER_TA : std_logic; - signal LP_DIR : std_logic; - signal MIDI_IN : std_logic; - signal MOT_ON : std_logic; - signal nBLANK : std_logic; - signal nDREQ0 : std_logic; - signal nMFP_INT : std_logic; - signal nRSTO : std_logic; - signal PIXEL_CLK : std_logic; - signal SD_CDM_D1 : std_logic; - signal STEP : std_logic; - signal STEP_DIR : std_logic; - signal TIMEBASE : std_logic_vector(17 downto 0); - signal VIDEO_RECONFIG : std_logic; - signal Video_TA : std_logic; - signal VR_BUSY : std_logic; - signal VR_D : std_logic_vector(8 downto 0); - signal VR_RD : std_logic; - signal VR_WR : std_logic; - signal VSYNC : std_logic; - signal WR_DATA : std_logic; - signal WR_GATE : std_logic; + signal clk2m : std_logic; + signal clk2m4576 : std_logic; + signal clk33m : std_logic; + signal clk48m : std_logic; + signal clk500k : std_logic; + signal clk_video : std_logic; + signal ddr_sync_66m : std_logic; + signal ddrclk : std_logic_vector(3 downto 0); + signal dma_drq : std_logic; + signal dsp_int : std_logic; + signal dsp_ta : std_logic; + signal falcon_io_ta : std_logic; + signal fb_adr : std_logic_vector(31 downto 0); + signal fdc_clk : std_logic; + signal hsync : std_logic; + signal int_handler_ta : std_logic; + signal lp_dir : std_logic; + signal midi_in : std_logic; + signal mot_on : std_logic; + signal blank_n : std_logic; + signal dreq0_n : std_logic; + signal mfp_int_n : std_logic; + signal rsto_n : std_logic; + signal pixel_clk : std_logic; + signal sd_cdm_d1 : std_logic; + signal step : std_logic; + signal step_dir : std_logic; + signal timebase : std_logic_vector(17 downto 0); + signal video_reconfig : std_logic; + signal video_ta : std_logic; + signal vr_busy : std_logic; + signal vr_d : std_logic_vector(8 downto 0); + signal vr_rd : std_logic; + signal vr_wr : std_logic; + signal vsync : std_logic; + signal wr_data : std_logic; + signal wr_gate : std_logic; signal scandataout : std_logic; signal scandone : std_logic; signal reset : std_logic; @@ -197,10 +197,10 @@ architecture rtl of firebee1 is signal config_update : std_logic; signal pll3_locked : std_logic; signal pll1_locked : std_logic; - signal nSRCS_i : std_logic; - signal nFB_WR_i : std_logic; - signal nIDE_RD_i : std_logic; - signal nIDE_WR_i : std_logic; + signal srcs_n_i : std_logic; + signal fb_wr_n_i : std_logic; + signal ide_rd_n_i : std_logic; + signal ide_wr_n_i : std_logic; signal fb_ad_in : std_logic_vector(31 downto 0); signal fb_ad_out : std_logic_vector(31 downto 0); @@ -252,9 +252,9 @@ begin ( inclk0 => MAIN_CLK, c0 => clk25m_i, - c1 => CLK2M, - c2 => CLK500k, - c3 => CLK2M4576, + c1 => clk2m, + c2 => clk500k, + c3 => clk2m4576, locked => pll3_locked ); @@ -263,17 +263,17 @@ begin port map ( inclk0 => MAIN_CLK, - c0 => DDRCLK(0), - c1 => DDRCLK(1), - c2 => DDRCLK(2), - c3 => DDRCLK(3), - c4 => DDR_SYNC_66M + c0 => ddrclk(0), + c1 => ddrclk(1), + c2 => ddrclk(2), + c3 => ddrclk(3), + c4 => ddr_sync_66m ); i_dsp : work.dsp port map ( - CLK33M => CLK33M, + clk33m => main_clk, MAIN_CLK => MAIN_CLK, nFB_OE => nFB_OE, nFB_WR => nFB_WR, @@ -281,30 +281,30 @@ begin nFB_CS2 => nFB_CS2, FB_SIZE0 => FB_SIZE0, FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - nRSTO => nRSTO, + nFB_BURST => nFB_BURST, + nrsto => rsto_n, nFB_CS3 => nFB_CS3, fb_ad_in => fb_ad_in, fb_ad_out => fb_ad_out, - FB_ADR => FB_ADR, + fb_adr => fb_adr, IO => IO, SRD => SRD, - nSRCS => nSRCS_i, + nSRCS => srcs_n_i, nSRBLE => nSRBLE, nSRBHE => nSRBHE, nSRWE => nSRWE, nSROE => nSROE, - DSP_INT => DSP_INT, - DSP_TA => DSP_TA + dsp_int => dsp_int, + dsp_ta => dsp_ta ); i_falconio_sdcard_ide_cf : work.falconio_sdcard_ide_cf port map ( - CLK33M => CLK33M, + clk33m => main_clk, MAIN_CLK => MAIN_CLK, - CLK2M => CLK2M, - CLK500k => CLK500k, + clk2m => clk2m, + clk500k => clk500k, nFB_CS1 => nFB_CS1, FB_SIZE0 => FB_SIZE0, FB_SIZE1 => FB_SIZE1, @@ -314,7 +314,7 @@ begin nACSI_INT => nACSI_INT, nSCSI_DRQ => nSCSI_DRQ, nSCSI_MSG => nSCSI_MSG, - MIDI_IN => MIDI_IN, + midi_in => midi_in, RxD => RxD, CTS => CTS, RI => RI, @@ -338,16 +338,16 @@ begin WP_CF_CARD => WP_CF_CARD, nWP => nWP, nFB_CS2 => nFB_CS2, - nRSTO => nRSTO, + nrsto => rsto_n, nSCSI_C_D => nSCSI_C_D, nSCSI_I_O => nSCSI_I_O, - CLK2M4576 => CLK2M4576, + clk2m4576 => clk2m4576, nFB_OE => nFB_OE, - VSYNC => VSYNC, - HSYNC => HSYNC, - DSP_INT => DSP_INT, - nBLANK => nBLANK, - FDC_CLK => FDC_CLK, + vsync => vsync, + hsync => hsync, + dsp_int => dsp_int, + nblank => blank_n, + fdc_clk => fdc_clk, FB_ALE => FB_ALE, HD_DD => HD_DD, SCSI_PAR => SCSI_PAR, @@ -355,18 +355,18 @@ begin nSCSI_BUSY => nSCSI_BUSY, nSCSI_RST => nSCSI_RST, SD_CD_DATA3 => SD_CD_DATA3, - SD_CDM_D1 => SD_CDM_D1, - ACP_CONF => ACP_CONF(31 downto 24), + sd_cdm_d1 => sd_cdm_d1, + acp_conf => acp_conf(31 downto 24), ACSI_D => ACSI_D, fb_ad_in => fb_ad_in, fb_ad_out => fb_ad_out, - FB_ADR => FB_ADR, + fb_adr => fb_adr, LP_D => LP_D, SCSI_D => SCSI_D, nIDE_CS1 => nIDE_CS1, nIDE_CS0 => nIDE_CS0, LP_STR => LP_STR, - LP_DIR => LP_DIR, + lp_dir => lp_dir, nACSI_ACK => nACSI_ACK, nACSI_RESET => nACSI_RESET, nACSI_CS => nACSI_CS, @@ -380,16 +380,16 @@ begin YM_QC => YM_QC, YM_QB => YM_QB, nSDSEL => nSDSEL, - STEP => STEP, - MOT_ON => MOT_ON, + step => step, + mot_on => mot_on, nRP_LDS => nRP_LDS, nRP_UDS => nRP_UDS, nROM4 => nROM4, nROM3 => nROM3, nCF_CS1 => nCF_CS1, nCF_CS0 => nCF_CS0, - nIDE_RD => nIDE_RD_i, - nIDE_WR => nIDE_WR_i, + nIDE_RD => ide_rd_n_i, + nIDE_WR => ide_wr_n_i, AMKB_TX => AMKB_TX, IDE_RES => IDE_RES, DTR => DTR, @@ -397,12 +397,12 @@ begin TxD => TxD, MIDI_OLR => MIDI_OLR, DSA_D => DSA_D, - nMFP_INT => nMFP_INT, - FALCON_IO_TA => FALCON_IO_TA, - STEP_DIR => STEP_DIR, - WR_DATA => WR_DATA, - WR_GATE => WR_GATE, - DMA_DRQ => DMA_DRQ, + nmfp_int => mfp_int_n, + falcon_io_ta => falcon_io_ta, + step_dir => step_dir, + wr_data => wr_data, + wr_gate => wr_gate, + dma_drq => dma_drq, MIDI_TLR => MIDI_TLR ); @@ -423,19 +423,19 @@ begin nPCI_INTB => nPCI_INTB, nPCI_INTC => nPCI_INTC, nPCI_INTD => nPCI_INTD, - nMFP_INT => nMFP_INT, + nmfp_int => mfp_int_n, nFB_OE => nFB_OE, - DSP_INT => DSP_INT, - VSYNC => VSYNC, - HSYNC => HSYNC, - DMA_DRQ => DMA_DRQ, - nRSTO => nRSTO, + dsp_int => dsp_int, + vsync => vsync, + hsync => hsync, + dma_drq => dma_drq, + nrsto => rsto_n, fb_ad_in => fb_ad_in, fb_ad_out => fb_ad_out, - FB_ADR => FB_ADR, - INT_HANDLER_TA => INT_HANDLER_TA, + fb_adr => fb_adr, + int_handler_ta => int_handler_ta, TIN0 => TIN0, - ACP_CONF => ACP_CONF, + acp_conf => acp_conf, nIRQ => nIRQ ); @@ -443,8 +443,8 @@ begin port map ( inclk0 => MAIN_CLK, - c0 => CLK48M, - c1 => FDC_CLK, + c0 => clk48m, + c1 => fdc_clk, c2 => CLK24M576, locked => pll1_locked ); @@ -453,24 +453,24 @@ begin i_pll_reconfig : altpll_reconfig1 port map ( - reconfig => VIDEO_RECONFIG, - read_param => VR_RD, - write_param => VR_WR, + reconfig => video_reconfig, + read_param => vr_rd, + write_param => vr_wr, pll_areset_in => '0', pll_scandataout => scandataout, pll_scandone => scandone, clock => MAIN_CLK, reset => reset, - counter_param => FB_ADR(8 downto 6), - counter_type => FB_ADR(5 downto 2), + counter_param => fb_adr(8 downto 6), + counter_type => fb_adr(5 downto 2), data_in => FB_AD(24 downto 16), - busy => VR_BUSY, + busy => vr_busy, pll_scandata => scandata, pll_scanclk => scanclk, pll_scanclkena => scan_clkena, pll_configupdate => config_update, pll_areset => pll_reset, - data_out => VR_D + data_out => vr_d ); i_video : entity work.video @@ -483,36 +483,37 @@ begin nFB_WR => nFB_WR, FB_SIZE0 => FB_SIZE0, FB_SIZE1 => FB_SIZE1, - nRSTO => nRSTO, + nrsto => rsto_n, nFB_OE => nFB_OE, FB_ALE => FB_ALE, - DDR_SYNC_66M => DDR_SYNC_66M, - CLK33M => CLK33M, + ddr_sync_66m => ddr_sync_66m, + -- clk33m => clk33m, + clk33m => main_clk, CLK25M => clk25m_i, - CLK_VIDEO => CLK_VIDEO, - VR_BUSY => VR_BUSY, - DDRCLK => DDRCLK, + clk_video => clk_video, + vr_busy => vr_busy, + ddrclk => ddrclk, fb_ad_in => fb_ad_in, fb_ad_out => fb_ad_out, - FB_ADR => FB_ADR, + fb_adr => fb_adr, VD => VD, VDQS => VDQS, - VR_D => VR_D, - VR_RD => VR_RD, - nBLANK => nBLANK, + vr_d => vr_d, + vr_rd => vr_rd, + nblank => blank_n, nVWE => nVWE, nVCAS => nVCAS, nVRAS => nVRAS, nVCS => nVCS, nPD_VGA => nPD_VGA, VCKE => VCKE, - VSYNC => VSYNC, - HSYNC => HSYNC, + vsync => vsync, + hsync => hsync, nSYNC => nSYNC, - VIDEO_TA => Video_TA, - PIXEL_CLK => PIXEL_CLK, - VIDEO_RECONFIG => VIDEO_RECONFIG, - VR_WR => VR_WR, + VIDEO_TA => video_ta, + pixel_clk => pixel_clk, + video_reconfig => video_reconfig, + vr_wr => vr_wr, BA => BA, VA => VA, VB => VB, @@ -524,13 +525,13 @@ begin i_video_clk_pll : altpll4 port map ( - inclk0 => CLK48M, + inclk0 => clk48m, areset => pll_reset, scanclk => scanclk, scandata => scandata, scanclkena => scan_clkena, configupdate => config_update, - c0 => CLK_VIDEO, + c0 => clk_video, scandataout => scandataout, scandone => scandone ); @@ -539,55 +540,55 @@ begin inst1 : work.lpm_ff0 port map ( - clock => DDR_SYNC_66M, + clock => ddr_sync_66m, enable => FB_ALE, data => FB_AD, - q => FB_ADR + q => fb_adr ); - nMOT_ON <= not(MOT_ON); - nSTEP_DIR <= not(STEP_DIR); - nSTEP <= not(STEP); - nWR <= not(WR_DATA); + nMOT_ON <= not(mot_on); + nSTEP_DIR <= not(step_dir); + nSTEP <= not(step); + nWR <= not(wr_data); inst18 : work.lpm_counter0 port map ( - clock => CLK500k, - q => TIMEBASE + clock => clk500k, + q => timebase ); - nWR_GATE <= not(WR_GATE); + nWR_GATE <= not(wr_gate); nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta); fb_ad_in <= fb_ad; fb_ad <= fb_ad_out when (video_ta or int_handler_ta or dsp_ta or falcon_io_ta) else (others => 'Z'); - CLK33M <= MAIN_CLK; + clk33m <= MAIN_CLK; - reset <= not(nRSTO); - nRSTO <= pll3_locked and pll1_locked and nRSTO_MCF; + reset <= not(rsto_n); + rsto_n <= pll3_locked and pll1_locked and nRSTO_MCF; inst29 : alt_iobuf port map ( - i => CLK2M, - oe => CLK2M, + i => clk2m, + oe => clk2m, io => MIDI_IN_PIN, - o => MIDI_IN + o => midi_in ); - LED_FPGA_OK <= TIMEBASE(17); + LED_FPGA_OK <= timebase(17); - nDDR_CLK <= not(DDRCLK(0)); + nDDR_CLK <= not(ddrclk(0)); inst5 : work.altddio_out3 port map ( - datain_h => VSYNC, - datain_l => VSYNC, - outclock => PIXEL_CLK, + datain_h => vsync, + datain_l => vsync, + outclock => pixel_clk, dataout => VSYNC_PAD ); @@ -595,9 +596,9 @@ begin inst6 : work.altddio_out3 port map ( - datain_h => HSYNC, - datain_l => HSYNC, - outclock => PIXEL_CLK, + datain_h => hsync, + datain_l => hsync, + outclock => pixel_clk, dataout => HSYNC_PAD ); @@ -605,9 +606,9 @@ begin inst8 : work.altddio_out3 port map ( - datain_h => nBLANK, - datain_l => nBLANK, - outclock => PIXEL_CLK, + datain_h => blank_n, + datain_l => blank_n, + outclock => pixel_clk, dataout => nBLANK_PAD ); @@ -616,17 +617,17 @@ begin ( datain_h => '0', datain_l => '1', - outclock => PIXEL_CLK, + outclock => pixel_clk, dataout => PIXEL_CLK_PAD ); - SD_CMD_D1 <= SD_CDM_D1; - DDR_CLK <= DDRCLK(0); - LPDIR <= LP_DIR; + SD_CMD_D1 <= sd_cdm_d1; + DDR_CLK <= ddrclk(0); + LPDIR <= lp_dir; CLK25M <= clk25m_i; - CLKUSB <= CLK48M; - nSRCS <= nSRCS_i; + CLKUSB <= clk48m; + nSRCS <= srcs_n_i; - nIDE_RD <= nIDE_RD_i; - nIDE_WR <= nIDE_WR_i; + nIDE_RD <= ide_rd_n_i; + nIDE_WR <= ide_wr_n_i; end rtl; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 5358126..16b6afb 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -193,3 +193,10 @@ set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \ #************************************************************** # Set Input Transition #************************************************************** + +if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } { + post_message -type info "Over constraining hold" + set_clock_uncertainty -add -enable_same_physical_edge -from { MAIN_CLK } -to { MAIN_CLK } -hold 0.2 +} + + From 7bb446d5ce844df6d5f60df56881984987be4083 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 21:12:58 +0000 Subject: [PATCH 111/127] fix hold timing violations --- FPGA_Quartus_13.1/firebee1.qws | Bin 2309 -> 6086 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index f9c3c598df8372e82d773439fec4108bb645cd72..fd8a23da25f1aa3b21f9c52816ac7ca1e79e85b1 100644 GIT binary patch literal 6086 zcmeI0OKX!+5QZmd)gmfx6c=3-DN@8tqWX?QzZ!(64&l z7OAtGZ64{fbQ;2*AL!f$Qq-Swjpw!))2p8 zrwTql!QBu-m)1xYF^hbK^BUQHlA~(Sd5q@ERZ-C&6o;@%9)0MZm04sx%(+ILG1zFv zK`f^?fSWI-0eNhFoVvs8zcD~@38z-Cz!a2xXKCux?w5m(-gUP%GnS;Nzp@*;~aXdrnZ{o0yDo4 z9ZZ6aiS6tp#$wd#LKXimstZ>qDhhN4r#WMQ1Ulo)zq1*LeERso85s|$*$FiM1O<=y zo@Qs*r5n9|7wy^*=(1?%ETBuEsRUpXz~c0(RSUW#v;G8KoYe(jxCGOteh6fO$O{V4 z6#||rx=80+8hZm~vf8#`b{u@>`9$e5UBTLu4z!Z=raS3sQ=8NPM23tl3L+z)D+E;? zz0-*N4_t#bZmV8$2Syzjn~K}$(-5njTo2*4o(@O-^SzTVX$v@uZCti8E<5Hx-g~os z-@xQ6UhF!$LAY#@@S%;(R>r1d4{Yk&E^KZ|har!A&UnT5%;87&<4wl#CKcY)dY_{n z{M3g$ac0NxOT&Mw9LN{GDkannf7SCBy-otB+YjNdD7$t>Pd4q eu!?qp!zXPg-M}XPFV)6l%YR}4U0wKGL;nUaTl|gy delta 419 zcmX@6-zqdg+meZafngnkGlLa_K0_!&F+(at5s=hpNCVROKwdFJE`uSE?*il{Gn4{( zsSJ4xB@D%r6WMGh8*tiM01fCM(|`~bpl0UD`rN^$l(->?jU^grj@#x7Y~75~EKxvq zJkVe;`2YX^KM)3Sm?kF)6fAs!?d0UAg8fpA w?O^Q;ENnpG`#=omPtN6tH6_=_S*%4svlaqf+RmuJI0NXWdZ25|A$Fnj0qJ*GGynhq From 02e1530cce449f0f1590730c3abacc21815c00b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 04:49:50 +0000 Subject: [PATCH 112/127] fix capitalization --- FPGA_Quartus_13.1/firebee1.qsf | 4 +- FPGA_Quartus_13.1/flexbus_register.vhd | 76 +++++++++++++------------- 2 files changed, 40 insertions(+), 40 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 5353743..af39682 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -677,6 +677,7 @@ set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf @@ -863,5 +864,4 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name VHDL_FILE flexbus_register.vhd \ No newline at end of file diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd index 0fdf3c8..c488e1b 100644 --- a/FPGA_Quartus_13.1/flexbus_register.vhd +++ b/FPGA_Quartus_13.1/flexbus_register.vhd @@ -1,51 +1,51 @@ -LIBRARY ieee; - USE ieee.std_logic_1164.all; - USE ieee.numeric_std.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; -ENTITY flexbus_register IS - GENERIC +entity flexbus_register is + generic ( reg_width : integer := 11; - match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); - match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1'); + match_address : std_logic_vector(31 downto 0) := (others => '0'); + match_mask : std_logic_vector(31 downto 0) := (others => '1'); match_fbcs : integer := 0 ); - PORT + port ( - clk : IN std_logic; - fb_addr : IN std_logic_vector(31 DOWNTO 0); - fb_data : INOUT std_logic_vector(31 DOWNTO 0); - fb_cs : IN std_logic_vector(5 DOWNTO 1); - fb_wr_n : IN std_logic; - fb_ta_n : OUT std_logic; - reg_value : INOUT std_logic_vector(reg_width - 1 DOWNTO 0); - cs : OUT std_logic := '0' + clk : in std_logic; + fb_addr : in std_logic_vector(31 downto 0); + fb_data : inout std_logic_vector(31 downto 0); + fb_cs : in std_logic_vector(5 downto 1); + fb_wr_n : in std_logic; + fb_ta_n : out std_logic; + reg_value : inout std_logic_vector(reg_width - 1 downto 0); + cs : out std_logic := '0' ); -END ENTITY flexbus_register; +end entity flexbus_register; -ARCHITECTURE rtl OF flexbus_register IS - SIGNAL fbcs_match : std_logic; - SIGNAL address_match : std_logic; -BEGIN - fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0'; - address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0'; +architecture rtl of flexbus_register is + signal fbcs_match : std_logic; + signal address_match : std_logic; +begin + fbcs_match <= '1' when fb_cs(match_fbcs) = '1' else '0'; + address_match <= '1' when (fb_addr and match_mask) = (match_address and match_mask) else '0'; - p_register_access : PROCESS(ALL) - BEGIN - IF rising_edge(clk) THEN - IF fbcs_match = '1' and address_match = '1' THEN + p_register_access : process(all) + begin + if rising_edge(clk) then + if fbcs_match = '1' and address_match = '1' then cs <= '1'; - IF fb_wr_n = '0' THEN -- write access - reg_value <= fb_data(reg_width - 1 DOWNTO 0); - ELSE -- read access - fb_data(reg_width - 1 DOWNTO 0) <= reg_value; + if fb_wr_n = '0' then -- write access + reg_value <= fb_data(reg_width - 1 downto 0); + else -- read access + fb_data(reg_width - 1 downto 0) <= reg_value; fb_ta_n <= '0'; - END IF; - ELSE - fb_data <= (OTHERS => 'Z'); + end if; + else + fb_data <= (others => 'Z'); fb_ta_n <= 'Z'; cs <= '0'; - END IF; - END IF; - END PROCESS p_register_access; -END ARCHITECTURE rtl; \ No newline at end of file + end if; + end if; + end process p_register_access; +end architecture rtl; \ No newline at end of file From 268147a9be4b5500b19cd5a2a20e03efa6fb2c9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 05:25:13 +0000 Subject: [PATCH 113/127] extend flexbus_register --- FPGA_Quartus_13.1/firebee1.qsf | 4 +- FPGA_Quartus_13.1/flexbus_register.vhd | 71 ++++++++++++++++++-------- 2 files changed, 52 insertions(+), 23 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index af39682..5353743 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -677,7 +677,6 @@ set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf @@ -864,4 +863,5 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd \ No newline at end of file +set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd index c488e1b..d7aea7e 100644 --- a/FPGA_Quartus_13.1/flexbus_register.vhd +++ b/FPGA_Quartus_13.1/flexbus_register.vhd @@ -2,50 +2,79 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library work; +use work.firebee_utils_pkg.all; + entity flexbus_register is generic ( reg_width : integer := 11; match_address : std_logic_vector(31 downto 0) := (others => '0'); - match_mask : std_logic_vector(31 downto 0) := (others => '1'); + num_ignore : integer range 0 to 31; match_fbcs : integer := 0 ); port ( clk : in std_logic; + + -- FlexBus signals fb_addr : in std_logic_vector(31 downto 0); - fb_data : inout std_logic_vector(31 downto 0); - fb_cs : in std_logic_vector(5 downto 1); + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0); + fb_cs_n : in std_logic_vector(5 downto 1); fb_wr_n : in std_logic; - fb_ta_n : out std_logic; - reg_value : inout std_logic_vector(reg_width - 1 downto 0); - cs : out std_logic := '0' + fb_oe_n : in std_logic; + fb_size : in std_logic_vector(1 downto 0); + + register_ta : out std_logic ); end entity flexbus_register; architecture rtl of flexbus_register is signal fbcs_match : std_logic; signal address_match : std_logic; + signal fb_b : std_logic_vector(3 downto 0); -- byte selects + signal cs : std_logic; + signal reg_value : std_logic_vector(reg_width - 1 downto 0); begin - fbcs_match <= '1' when fb_cs(match_fbcs) = '1' else '0'; - address_match <= '1' when (fb_addr and match_mask) = (match_address and match_mask) else '0'; + -- byte selects + -- HWORD + -- HHBYT + -- LONG UND LINE + fb_b(0) <= (fb_size(1) and (not fb_size(0)) and (not fb_addr(1))) or + ((not fb_size(1)) and fb_size(0) and (not fb_addr(1)) and (not fb_addr(0))) or + ((not fb_size(1)) and (not fb_size(0))) or + (fb_size(1) and fb_size(0)); + + -- HWORD + -- HLBYT + -- LONG UND LINE + fb_b(1) <= (fb_size(1) and (not fb_size(0) and (not fb_addr(1)))) or + ((not fb_size(1)) and fb_size(0) and (not fb_addr(1)) and fb_addr(0)) or + ((not fb_size(1)) and (not fb_size(0))) or + (fb_size(1) and fb_size(0)); + + -- LWORD + -- LHBYT + -- LONG UND LINE + fb_b(2) <= (fb_size(1) and (not fb_size(0)) and fb_addr(1)) or + ((not fb_size(1)) and fb_size(0) and fb_addr(1) and (not fb_addr(0))) or + ((not fb_size(1)) and (not fb_size(0))) or (fb_size(1) and fb_size(0)); + + -- LWORD + -- LLBYT + -- LONG UND LINE + fb_b(3) <= (fb_size(1) and (not fb_size(0)) and fb_addr(1)) or + ((not fb_size(1)) and fb_size(0) and fb_addr(1) and fb_addr(0)) or + ((not fb_size(1)) and (not fb_size(0))) or + (fb_size(1) and fb_size(0)); + + fbcs_match <= '1' when not(fb_cs_n(match_fbcs)) = '1' else '0'; + address_match <= f_addr_cmp_mask(fb_addr, match_address, num_ignore); p_register_access : process(all) begin if rising_edge(clk) then - if fbcs_match = '1' and address_match = '1' then - cs <= '1'; - if fb_wr_n = '0' then -- write access - reg_value <= fb_data(reg_width - 1 downto 0); - else -- read access - fb_data(reg_width - 1 downto 0) <= reg_value; - fb_ta_n <= '0'; - end if; - else - fb_data <= (others => 'Z'); - fb_ta_n <= 'Z'; - cs <= '0'; - end if; end if; end process p_register_access; end architecture rtl; \ No newline at end of file From 799f41e8d590cbf86130e7c0c7d2631cd8695a2f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 06:29:14 +0000 Subject: [PATCH 114/127] rename file and paths to lower case --- FPGA_Quartus_13.1/firebee1.qsf | 264 +++++++++--------- .../{Video => video}/BLITTER/BLITTER.vhd | 0 .../{Video => video}/BLITTER/altsyncram0.qip | 0 .../{Video => video}/BLITTER/lpm_clshift0.qip | 0 .../{Video => video}/altddio_bidir0.bsf | 0 .../{Video => video}/altddio_bidir0.cmp | 0 .../{Video => video}/altddio_bidir0.inc | 0 .../{Video => video}/altddio_bidir0.ppf | 0 .../{Video => video}/altddio_bidir0.qip | 0 .../{Video => video}/altddio_bidir0.vhd | 0 .../{Video => video}/altddio_out0.bsf | 0 .../{Video => video}/altddio_out0.cmp | 0 .../{Video => video}/altddio_out0.inc | 0 .../{Video => video}/altddio_out0.ppf | 0 .../{Video => video}/altddio_out0.qip | 0 .../{Video => video}/altddio_out0.vhd | 0 .../{Video => video}/altddio_out1.bsf | 0 .../{Video => video}/altddio_out1.cmp | 0 .../{Video => video}/altddio_out1.inc | 0 .../{Video => video}/altddio_out1.ppf | 0 .../{Video => video}/altddio_out1.qip | 0 .../{Video => video}/altddio_out1.vhd | 0 .../{Video => video}/altddio_out2.bsf | 0 .../{Video => video}/altddio_out2.cmp | 0 .../{Video => video}/altddio_out2.inc | 0 .../{Video => video}/altddio_out2.ppf | 0 .../{Video => video}/altddio_out2.qip | 0 .../{Video => video}/altddio_out2.vhd | 0 .../{Video => video}/altdpram0.bsf | 0 .../{Video => video}/altdpram0.cmp | 0 .../{Video => video}/altdpram0.inc | 0 .../{Video => video}/altdpram0.qip | 0 .../{Video => video}/altdpram0.vhd | 0 .../{Video => video}/altdpram1.bsf | 0 .../{Video => video}/altdpram1.cmp | 0 .../{Video => video}/altdpram1.inc | 0 .../{Video => video}/altdpram1.qip | 0 .../{Video => video}/altdpram1.vhd | 0 .../{Video => video}/altdpram2.bsf | 0 .../{Video => video}/altdpram2.cmp | 0 .../{Video => video}/altdpram2.inc | 0 .../{Video => video}/altdpram2.qip | 0 .../{Video => video}/altdpram2.vhd | 0 .../DDR_CTR.vhd => video/ddr_controller.vhd} | 0 .../{Video => video}/lpm_bustri0.bsf | 0 .../{Video => video}/lpm_bustri0.cmp | 0 .../{Video => video}/lpm_bustri0.inc | 0 .../{Video => video}/lpm_bustri0.qip | 0 .../{Video => video}/lpm_bustri0.vhd | 0 .../{Video => video}/lpm_bustri1.bsf | 0 .../{Video => video}/lpm_bustri1.cmp | 0 .../{Video => video}/lpm_bustri1.qip | 0 .../{Video => video}/lpm_bustri1.vhd | 0 .../{Video => video}/lpm_bustri2.bsf | 0 .../{Video => video}/lpm_bustri2.cmp | 0 .../{Video => video}/lpm_bustri2.qip | 0 .../{Video => video}/lpm_bustri2.vhd | 0 .../{Video => video}/lpm_bustri3.bsf | 0 .../{Video => video}/lpm_bustri3.cmp | 0 .../{Video => video}/lpm_bustri3.qip | 0 .../{Video => video}/lpm_bustri3.vhd | 0 .../{Video => video}/lpm_bustri4.bsf | 0 .../{Video => video}/lpm_bustri4.cmp | 0 .../{Video => video}/lpm_bustri4.qip | 0 .../{Video => video}/lpm_bustri4.vhd | 0 .../{Video => video}/lpm_bustri5.bsf | 0 .../{Video => video}/lpm_bustri5.cmp | 0 .../{Video => video}/lpm_bustri5.inc | 0 .../{Video => video}/lpm_bustri5.qip | 0 .../{Video => video}/lpm_bustri5.vhd | 0 .../{Video => video}/lpm_bustri6.bsf | 0 .../{Video => video}/lpm_bustri6.cmp | 0 .../{Video => video}/lpm_bustri6.qip | 0 .../{Video => video}/lpm_bustri6.vhd | 0 .../{Video => video}/lpm_bustri7.bsf | 0 .../{Video => video}/lpm_bustri7.cmp | 0 .../{Video => video}/lpm_bustri7.qip | 0 .../{Video => video}/lpm_bustri7.vhd | 0 .../{Video => video}/lpm_compare1.bsf | 0 .../{Video => video}/lpm_compare1.cmp | 0 .../{Video => video}/lpm_compare1.inc | 0 .../{Video => video}/lpm_compare1.qip | 0 .../{Video => video}/lpm_compare1.vhd | 0 .../{Video => video}/lpm_constant0.bsf | 0 .../{Video => video}/lpm_constant0.cmp | 0 .../{Video => video}/lpm_constant0.qip | 0 .../{Video => video}/lpm_constant0.vhd | 0 .../{Video => video}/lpm_constant1.bsf | 0 .../{Video => video}/lpm_constant1.cmp | 0 .../{Video => video}/lpm_constant1.inc | 0 .../{Video => video}/lpm_constant1.qip | 0 .../{Video => video}/lpm_constant1.vhd | 0 .../{Video => video}/lpm_constant2.bsf | 0 .../{Video => video}/lpm_constant2.cmp | 0 .../{Video => video}/lpm_constant2.qip | 0 .../{Video => video}/lpm_constant2.vhd | 0 .../{Video => video}/lpm_constant3.bsf | 0 .../{Video => video}/lpm_constant3.cmp | 0 .../{Video => video}/lpm_constant3.qip | 0 .../{Video => video}/lpm_constant3.vhd | 0 .../{Video => video}/lpm_constant4.bsf | 0 .../{Video => video}/lpm_constant4.cmp | 0 .../{Video => video}/lpm_constant4.inc | 0 .../{Video => video}/lpm_constant4.qip | 0 .../{Video => video}/lpm_constant4.vhd | 0 .../{Video => video}/lpm_ff0.bsf | 0 .../{Video => video}/lpm_ff0.cmp | 0 .../{Video => video}/lpm_ff0.qip | 0 .../{Video => video}/lpm_ff0.vhd | 0 .../{Video => video}/lpm_ff1.bsf | 0 .../{Video => video}/lpm_ff1.cmp | 0 .../{Video => video}/lpm_ff1.qip | 0 .../{Video => video}/lpm_ff1.vhd | 0 .../{Video => video}/lpm_ff2.bsf | 0 .../{Video => video}/lpm_ff2.cmp | 0 .../{Video => video}/lpm_ff2.qip | 0 .../{Video => video}/lpm_ff2.vhd | 0 .../{Video => video}/lpm_ff3.bsf | 0 .../{Video => video}/lpm_ff3.cmp | 0 .../{Video => video}/lpm_ff3.qip | 0 .../{Video => video}/lpm_ff3.vhd | 0 .../{Video => video}/lpm_ff4.bsf | 0 .../{Video => video}/lpm_ff4.cmp | 0 .../{Video => video}/lpm_ff4.inc | 0 .../{Video => video}/lpm_ff4.qip | 0 .../{Video => video}/lpm_ff4.vhd | 0 .../{Video => video}/lpm_ff5.bsf | 0 .../{Video => video}/lpm_ff5.cmp | 0 .../{Video => video}/lpm_ff5.inc | 0 .../{Video => video}/lpm_ff5.qip | 0 .../{Video => video}/lpm_ff5.vhd | 0 .../{Video => video}/lpm_ff6.bsf | 0 .../{Video => video}/lpm_ff6.cmp | 0 .../{Video => video}/lpm_ff6.inc | 0 .../{Video => video}/lpm_ff6.qip | 0 .../{Video => video}/lpm_ff6.vhd | 0 .../{Video => video}/lpm_fifoDZ.bsf | 0 .../{Video => video}/lpm_fifoDZ.cmp | 0 .../{Video => video}/lpm_fifoDZ.qip | 0 .../{Video => video}/lpm_fifoDZ.vhd | 0 .../{Video => video}/lpm_fifo_dc0.bsf | 0 .../{Video => video}/lpm_fifo_dc0.cmp | 0 .../{Video => video}/lpm_fifo_dc0.inc | 0 .../{Video => video}/lpm_fifo_dc0.qip | 0 .../{Video => video}/lpm_fifo_dc0.vhd | 0 .../{Video => video}/lpm_latch1.bsf | 0 .../{Video => video}/lpm_latch1.cmp | 0 .../{Video => video}/lpm_latch1.qip | 0 .../{Video => video}/lpm_latch1.vhd | 0 .../{Video => video}/lpm_mux0.bsf | 0 .../{Video => video}/lpm_mux0.cmp | 0 .../{Video => video}/lpm_mux0.inc | 0 .../{Video => video}/lpm_mux0.qip | 0 .../{Video => video}/lpm_mux0.vhd | 0 .../{Video => video}/lpm_mux1.bsf | 0 .../{Video => video}/lpm_mux1.cmp | 0 .../{Video => video}/lpm_mux1.inc | 0 .../{Video => video}/lpm_mux1.qip | 0 .../{Video => video}/lpm_mux1.vhd | 0 .../{Video => video}/lpm_mux2.bsf | 0 .../{Video => video}/lpm_mux2.cmp | 0 .../{Video => video}/lpm_mux2.inc | 0 .../{Video => video}/lpm_mux2.qip | 0 .../{Video => video}/lpm_mux2.vhd | 0 .../{Video => video}/lpm_mux3.bsf | 0 .../{Video => video}/lpm_mux3.cmp | 0 .../{Video => video}/lpm_mux3.qip | 0 .../{Video => video}/lpm_mux3.vhd | 0 .../{Video => video}/lpm_mux4.bsf | 0 .../{Video => video}/lpm_mux4.cmp | 0 .../{Video => video}/lpm_mux4.qip | 0 .../{Video => video}/lpm_mux4.vhd | 0 .../{Video => video}/lpm_mux5.bsf | 0 .../{Video => video}/lpm_mux5.cmp | 0 .../{Video => video}/lpm_mux5.inc | 0 .../{Video => video}/lpm_mux5.qip | 0 .../{Video => video}/lpm_mux5.vhd | 0 .../{Video => video}/lpm_mux6.bsf | 0 .../{Video => video}/lpm_mux6.cmp | 0 .../{Video => video}/lpm_mux6.inc | 0 .../{Video => video}/lpm_mux6.qip | 0 .../{Video => video}/lpm_mux6.vhd | 0 .../{Video => video}/lpm_muxDZ.bsf | 0 .../{Video => video}/lpm_muxDZ.cmp | 0 .../{Video => video}/lpm_muxDZ.qip | 0 .../{Video => video}/lpm_muxDZ.vhd | 0 .../{Video => video}/lpm_muxDZ2.bsf | 0 .../{Video => video}/lpm_muxDZ2.cmp | 0 .../{Video => video}/lpm_muxDZ2.qip | 0 .../{Video => video}/lpm_muxDZ2.vhd | 0 .../{Video => video}/lpm_muxVDM.bsf | 0 .../{Video => video}/lpm_muxVDM.cmp | 0 .../{Video => video}/lpm_muxVDM.qip | 0 .../{Video => video}/lpm_muxVDM.vhd | 0 .../{Video => video}/lpm_shiftreg0.bsf | 0 .../{Video => video}/lpm_shiftreg0.cmp | 0 .../{Video => video}/lpm_shiftreg0.inc | 0 .../{Video => video}/lpm_shiftreg0.qip | 0 .../{Video => video}/lpm_shiftreg0.vhd | 0 .../{Video => video}/lpm_shiftreg1.bsf | 0 .../{Video => video}/lpm_shiftreg1.cmp | 0 .../{Video => video}/lpm_shiftreg1.qip | 0 .../{Video => video}/lpm_shiftreg1.vhd | 0 .../{Video => video}/lpm_shiftreg2.bsf | 0 .../{Video => video}/lpm_shiftreg2.cmp | 0 .../{Video => video}/lpm_shiftreg2.qip | 0 .../{Video => video}/lpm_shiftreg2.vhd | 0 .../{Video => video}/lpm_shiftreg3.bsf | 0 .../{Video => video}/lpm_shiftreg3.cmp | 0 .../{Video => video}/lpm_shiftreg3.inc | 0 .../{Video => video}/lpm_shiftreg3.qip | 0 .../{Video => video}/lpm_shiftreg3.vhd | 0 .../{Video => video}/lpm_shiftreg4.bsf | 0 .../{Video => video}/lpm_shiftreg4.cmp | 0 .../{Video => video}/lpm_shiftreg4.inc | 0 .../{Video => video}/lpm_shiftreg4.qip | 0 .../{Video => video}/lpm_shiftreg4.vhd | 0 .../{Video => video}/lpm_shiftreg5.bsf | 0 .../{Video => video}/lpm_shiftreg5.cmp | 0 .../{Video => video}/lpm_shiftreg5.inc | 0 .../{Video => video}/lpm_shiftreg5.qip | 0 .../{Video => video}/lpm_shiftreg5.vhd | 0 .../{Video => video}/lpm_shiftreg6.bsf | 0 .../{Video => video}/lpm_shiftreg6.cmp | 0 .../{Video => video}/lpm_shiftreg6.inc | 0 .../{Video => video}/lpm_shiftreg6.qip | 0 .../{Video => video}/lpm_shiftreg6.vhd | 0 FPGA_Quartus_13.1/{Video => video}/mux41.vhd | 0 .../{Video => video}/mux41_0.vhd | 0 .../{Video => video}/mux41_1.vhd | 0 .../{Video => video}/mux41_2.vhd | 0 .../{Video => video}/mux41_3.vhd | 0 .../{Video => video}/mux41_4.vhd | 0 .../{Video => video}/mux41_5.vhd | 0 FPGA_Quartus_13.1/{Video => video}/video.vhd | 0 .../video_mod_mux_clutctr.vhd | 0 236 files changed, 133 insertions(+), 131 deletions(-) rename FPGA_Quartus_13.1/{Video => video}/BLITTER/BLITTER.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/BLITTER/altsyncram0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/BLITTER/lpm_clshift0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_bidir0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_bidir0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_bidir0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_bidir0.ppf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_bidir0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_bidir0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out0.ppf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out1.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out1.ppf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out2.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out2.ppf (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altddio_out2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram1.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram2.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/altdpram2.vhd (100%) rename FPGA_Quartus_13.1/{Video/DDR_CTR.vhd => video/ddr_controller.vhd} (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri3.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri3.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri3.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri3.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri4.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri4.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri4.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri4.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri5.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri5.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri5.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri5.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri5.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri6.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri6.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri6.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri6.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri7.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri7.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri7.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_bustri7.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_compare1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_compare1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_compare1.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_compare1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_compare1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant1.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant3.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant3.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant3.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant3.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant4.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant4.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant4.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant4.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_constant4.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff3.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff3.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff3.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff3.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff4.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff4.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff4.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff4.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff4.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff5.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff5.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff5.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff5.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff5.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff6.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff6.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff6.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff6.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_ff6.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifoDZ.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifoDZ.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifoDZ.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifoDZ.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifo_dc0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifo_dc0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifo_dc0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifo_dc0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_fifo_dc0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_latch1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_latch1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_latch1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_latch1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux1.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux2.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux3.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux3.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux3.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux3.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux4.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux4.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux4.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux4.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux5.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux5.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux5.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux5.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux5.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux6.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux6.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux6.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux6.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_mux6.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxDZ2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxVDM.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxVDM.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxVDM.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_muxVDM.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg0.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg0.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg0.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg0.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg1.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg1.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg1.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg2.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg2.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg2.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg3.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg3.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg3.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg3.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg3.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg4.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg4.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg4.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg4.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg4.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg5.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg5.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg5.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg5.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg5.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg6.bsf (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg6.cmp (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg6.inc (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg6.qip (100%) rename FPGA_Quartus_13.1/{Video => video}/lpm_shiftreg6.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41_0.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41_1.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41_2.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41_3.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41_4.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/mux41_5.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/video.vhd (100%) rename FPGA_Quartus_13.1/{Video => video}/video_mod_mux_clutctr.vhd (100%) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 5353743..a9a68e7 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -446,16 +446,16 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -470,16 +470,16 @@ set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA @@ -677,126 +677,126 @@ set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE video/video.vhd set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf set_global_assignment -name AHDL_FILE altpll4.tdf set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE video/ddr_controller.vhd set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd set_global_assignment -name SOURCE_FILE altpll4.cmp set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE video/mux41.vhd +set_global_assignment -name VHDL_FILE video/mux41_5.vhd +set_global_assignment -name VHDL_FILE video/mux41_4.vhd +set_global_assignment -name VHDL_FILE video/mux41_3.vhd +set_global_assignment -name VHDL_FILE video/mux41_2.vhd +set_global_assignment -name VHDL_FILE video/mux41_1.vhd +set_global_assignment -name VHDL_FILE video/mux41_0.vhd +set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE video/altdpram2.cmp +set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE video/altdpram0.qip +set_global_assignment -name QIP_FILE video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE video/altdpram1.qip +set_global_assignment -name QIP_FILE video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE video/lpm_constant0.qip +set_global_assignment -name QIP_FILE video/lpm_constant1.qip +set_global_assignment -name QIP_FILE video/lpm_mux0.qip +set_global_assignment -name QIP_FILE video/lpm_mux1.qip +set_global_assignment -name QIP_FILE video/lpm_mux2.qip +set_global_assignment -name QIP_FILE video/lpm_constant2.qip +set_global_assignment -name QIP_FILE video/altdpram2.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE video/altddio_out0.qip +set_global_assignment -name QIP_FILE video/lpm_mux5.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE video/altddio_out1.qip +set_global_assignment -name QIP_FILE video/altddio_out2.qip +set_global_assignment -name QIP_FILE video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE video/lpm_mux6.qip +set_global_assignment -name QIP_FILE video/lpm_mux3.qip +set_global_assignment -name QIP_FILE video/lpm_mux4.qip +set_global_assignment -name QIP_FILE video/lpm_constant3.qip +set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE video/lpm_latch1.qip +set_global_assignment -name QIP_FILE video/lpm_constant4.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE video/lpm_ff4.qip +set_global_assignment -name QIP_FILE video/lpm_ff5.qip +set_global_assignment -name QIP_FILE video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip set_global_assignment -name VHDL_FILE DSP/DSP.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd @@ -864,4 +864,6 @@ set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_global_assignment -name VHDL_FILE flexbus_register.vhd + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/video/BLITTER/BLITTER.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd rename to FPGA_Quartus_13.1/video/BLITTER/BLITTER.vhd diff --git a/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip b/FPGA_Quartus_13.1/video/BLITTER/altsyncram0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip rename to FPGA_Quartus_13.1/video/BLITTER/altsyncram0.qip diff --git a/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip b/FPGA_Quartus_13.1/video/BLITTER/lpm_clshift0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip rename to FPGA_Quartus_13.1/video/BLITTER/lpm_clshift0.qip diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.bsf b/FPGA_Quartus_13.1/video/altddio_bidir0.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_bidir0.bsf rename to FPGA_Quartus_13.1/video/altddio_bidir0.bsf diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.cmp b/FPGA_Quartus_13.1/video/altddio_bidir0.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_bidir0.cmp rename to FPGA_Quartus_13.1/video/altddio_bidir0.cmp diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.inc b/FPGA_Quartus_13.1/video/altddio_bidir0.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_bidir0.inc rename to FPGA_Quartus_13.1/video/altddio_bidir0.inc diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.ppf b/FPGA_Quartus_13.1/video/altddio_bidir0.ppf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_bidir0.ppf rename to FPGA_Quartus_13.1/video/altddio_bidir0.ppf diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.qip b/FPGA_Quartus_13.1/video/altddio_bidir0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_bidir0.qip rename to FPGA_Quartus_13.1/video/altddio_bidir0.qip diff --git a/FPGA_Quartus_13.1/Video/altddio_bidir0.vhd b/FPGA_Quartus_13.1/video/altddio_bidir0.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_bidir0.vhd rename to FPGA_Quartus_13.1/video/altddio_bidir0.vhd diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.bsf b/FPGA_Quartus_13.1/video/altddio_out0.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out0.bsf rename to FPGA_Quartus_13.1/video/altddio_out0.bsf diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.cmp b/FPGA_Quartus_13.1/video/altddio_out0.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out0.cmp rename to FPGA_Quartus_13.1/video/altddio_out0.cmp diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.inc b/FPGA_Quartus_13.1/video/altddio_out0.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out0.inc rename to FPGA_Quartus_13.1/video/altddio_out0.inc diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.ppf b/FPGA_Quartus_13.1/video/altddio_out0.ppf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out0.ppf rename to FPGA_Quartus_13.1/video/altddio_out0.ppf diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.qip b/FPGA_Quartus_13.1/video/altddio_out0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out0.qip rename to FPGA_Quartus_13.1/video/altddio_out0.qip diff --git a/FPGA_Quartus_13.1/Video/altddio_out0.vhd b/FPGA_Quartus_13.1/video/altddio_out0.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out0.vhd rename to FPGA_Quartus_13.1/video/altddio_out0.vhd diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.bsf b/FPGA_Quartus_13.1/video/altddio_out1.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out1.bsf rename to FPGA_Quartus_13.1/video/altddio_out1.bsf diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.cmp b/FPGA_Quartus_13.1/video/altddio_out1.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out1.cmp rename to FPGA_Quartus_13.1/video/altddio_out1.cmp diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.inc b/FPGA_Quartus_13.1/video/altddio_out1.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out1.inc rename to FPGA_Quartus_13.1/video/altddio_out1.inc diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.ppf b/FPGA_Quartus_13.1/video/altddio_out1.ppf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out1.ppf rename to FPGA_Quartus_13.1/video/altddio_out1.ppf diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.qip b/FPGA_Quartus_13.1/video/altddio_out1.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out1.qip rename to FPGA_Quartus_13.1/video/altddio_out1.qip diff --git a/FPGA_Quartus_13.1/Video/altddio_out1.vhd b/FPGA_Quartus_13.1/video/altddio_out1.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out1.vhd rename to FPGA_Quartus_13.1/video/altddio_out1.vhd diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.bsf b/FPGA_Quartus_13.1/video/altddio_out2.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out2.bsf rename to FPGA_Quartus_13.1/video/altddio_out2.bsf diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.cmp b/FPGA_Quartus_13.1/video/altddio_out2.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out2.cmp rename to FPGA_Quartus_13.1/video/altddio_out2.cmp diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.inc b/FPGA_Quartus_13.1/video/altddio_out2.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out2.inc rename to FPGA_Quartus_13.1/video/altddio_out2.inc diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.ppf b/FPGA_Quartus_13.1/video/altddio_out2.ppf similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out2.ppf rename to FPGA_Quartus_13.1/video/altddio_out2.ppf diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.qip b/FPGA_Quartus_13.1/video/altddio_out2.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out2.qip rename to FPGA_Quartus_13.1/video/altddio_out2.qip diff --git a/FPGA_Quartus_13.1/Video/altddio_out2.vhd b/FPGA_Quartus_13.1/video/altddio_out2.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altddio_out2.vhd rename to FPGA_Quartus_13.1/video/altddio_out2.vhd diff --git a/FPGA_Quartus_13.1/Video/altdpram0.bsf b/FPGA_Quartus_13.1/video/altdpram0.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram0.bsf rename to FPGA_Quartus_13.1/video/altdpram0.bsf diff --git a/FPGA_Quartus_13.1/Video/altdpram0.cmp b/FPGA_Quartus_13.1/video/altdpram0.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram0.cmp rename to FPGA_Quartus_13.1/video/altdpram0.cmp diff --git a/FPGA_Quartus_13.1/Video/altdpram0.inc b/FPGA_Quartus_13.1/video/altdpram0.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram0.inc rename to FPGA_Quartus_13.1/video/altdpram0.inc diff --git a/FPGA_Quartus_13.1/Video/altdpram0.qip b/FPGA_Quartus_13.1/video/altdpram0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram0.qip rename to FPGA_Quartus_13.1/video/altdpram0.qip diff --git a/FPGA_Quartus_13.1/Video/altdpram0.vhd b/FPGA_Quartus_13.1/video/altdpram0.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram0.vhd rename to FPGA_Quartus_13.1/video/altdpram0.vhd diff --git a/FPGA_Quartus_13.1/Video/altdpram1.bsf b/FPGA_Quartus_13.1/video/altdpram1.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram1.bsf rename to FPGA_Quartus_13.1/video/altdpram1.bsf diff --git a/FPGA_Quartus_13.1/Video/altdpram1.cmp b/FPGA_Quartus_13.1/video/altdpram1.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram1.cmp rename to FPGA_Quartus_13.1/video/altdpram1.cmp diff --git a/FPGA_Quartus_13.1/Video/altdpram1.inc b/FPGA_Quartus_13.1/video/altdpram1.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram1.inc rename to FPGA_Quartus_13.1/video/altdpram1.inc diff --git a/FPGA_Quartus_13.1/Video/altdpram1.qip b/FPGA_Quartus_13.1/video/altdpram1.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram1.qip rename to FPGA_Quartus_13.1/video/altdpram1.qip diff --git a/FPGA_Quartus_13.1/Video/altdpram1.vhd b/FPGA_Quartus_13.1/video/altdpram1.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram1.vhd rename to FPGA_Quartus_13.1/video/altdpram1.vhd diff --git a/FPGA_Quartus_13.1/Video/altdpram2.bsf b/FPGA_Quartus_13.1/video/altdpram2.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram2.bsf rename to FPGA_Quartus_13.1/video/altdpram2.bsf diff --git a/FPGA_Quartus_13.1/Video/altdpram2.cmp b/FPGA_Quartus_13.1/video/altdpram2.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram2.cmp rename to FPGA_Quartus_13.1/video/altdpram2.cmp diff --git a/FPGA_Quartus_13.1/Video/altdpram2.inc b/FPGA_Quartus_13.1/video/altdpram2.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram2.inc rename to FPGA_Quartus_13.1/video/altdpram2.inc diff --git a/FPGA_Quartus_13.1/Video/altdpram2.qip b/FPGA_Quartus_13.1/video/altdpram2.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram2.qip rename to FPGA_Quartus_13.1/video/altdpram2.qip diff --git a/FPGA_Quartus_13.1/Video/altdpram2.vhd b/FPGA_Quartus_13.1/video/altdpram2.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/altdpram2.vhd rename to FPGA_Quartus_13.1/video/altdpram2.vhd diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/video/ddr_controller.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/DDR_CTR.vhd rename to FPGA_Quartus_13.1/video/ddr_controller.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.bsf b/FPGA_Quartus_13.1/video/lpm_bustri0.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri0.bsf rename to FPGA_Quartus_13.1/video/lpm_bustri0.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.cmp b/FPGA_Quartus_13.1/video/lpm_bustri0.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri0.cmp rename to FPGA_Quartus_13.1/video/lpm_bustri0.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.inc b/FPGA_Quartus_13.1/video/lpm_bustri0.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri0.inc rename to FPGA_Quartus_13.1/video/lpm_bustri0.inc diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.qip b/FPGA_Quartus_13.1/video/lpm_bustri0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri0.qip rename to FPGA_Quartus_13.1/video/lpm_bustri0.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri0.vhd b/FPGA_Quartus_13.1/video/lpm_bustri0.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri0.vhd rename to FPGA_Quartus_13.1/video/lpm_bustri0.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri1.bsf b/FPGA_Quartus_13.1/video/lpm_bustri1.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri1.bsf rename to FPGA_Quartus_13.1/video/lpm_bustri1.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_bustri1.cmp b/FPGA_Quartus_13.1/video/lpm_bustri1.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_bustri1.cmp rename to FPGA_Quartus_13.1/video/lpm_bustri1.cmp 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b/FPGA_Quartus_13.1/video/lpm_mux6.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_mux6.qip rename to FPGA_Quartus_13.1/video/lpm_mux6.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_mux6.vhd b/FPGA_Quartus_13.1/video/lpm_mux6.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_mux6.vhd rename to FPGA_Quartus_13.1/video/lpm_mux6.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.bsf b/FPGA_Quartus_13.1/video/lpm_muxDZ.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ.bsf rename to FPGA_Quartus_13.1/video/lpm_muxDZ.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.cmp b/FPGA_Quartus_13.1/video/lpm_muxDZ.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ.cmp rename to FPGA_Quartus_13.1/video/lpm_muxDZ.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.qip b/FPGA_Quartus_13.1/video/lpm_muxDZ.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ.qip rename to FPGA_Quartus_13.1/video/lpm_muxDZ.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ.vhd b/FPGA_Quartus_13.1/video/lpm_muxDZ.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ.vhd rename to FPGA_Quartus_13.1/video/lpm_muxDZ.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.bsf b/FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ2.bsf rename to FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.cmp b/FPGA_Quartus_13.1/video/lpm_muxDZ2.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ2.cmp rename to FPGA_Quartus_13.1/video/lpm_muxDZ2.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.qip b/FPGA_Quartus_13.1/video/lpm_muxDZ2.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ2.qip rename to FPGA_Quartus_13.1/video/lpm_muxDZ2.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_muxDZ2.vhd b/FPGA_Quartus_13.1/video/lpm_muxDZ2.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxDZ2.vhd rename to FPGA_Quartus_13.1/video/lpm_muxDZ2.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.bsf b/FPGA_Quartus_13.1/video/lpm_muxVDM.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxVDM.bsf rename to FPGA_Quartus_13.1/video/lpm_muxVDM.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.cmp b/FPGA_Quartus_13.1/video/lpm_muxVDM.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxVDM.cmp rename to FPGA_Quartus_13.1/video/lpm_muxVDM.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.qip b/FPGA_Quartus_13.1/video/lpm_muxVDM.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxVDM.qip rename to FPGA_Quartus_13.1/video/lpm_muxVDM.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_muxVDM.vhd b/FPGA_Quartus_13.1/video/lpm_muxVDM.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_muxVDM.vhd rename to FPGA_Quartus_13.1/video/lpm_muxVDM.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg0.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg0.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg0.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg0.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg0.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg0.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.inc b/FPGA_Quartus_13.1/video/lpm_shiftreg0.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg0.inc rename to FPGA_Quartus_13.1/video/lpm_shiftreg0.inc diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg0.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg0.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg0.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg0.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg0.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg0.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg0.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg1.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg1.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg1.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg1.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg1.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg1.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg1.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg1.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg1.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg1.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg1.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg2.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg2.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg2.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg2.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg2.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg2.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg2.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg2.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg2.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg2.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg2.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg3.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg3.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg3.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg3.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.inc b/FPGA_Quartus_13.1/video/lpm_shiftreg3.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg3.inc rename to FPGA_Quartus_13.1/video/lpm_shiftreg3.inc diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg3.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg3.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg3.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg3.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg3.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg3.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg3.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg4.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg4.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg4.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg4.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.inc b/FPGA_Quartus_13.1/video/lpm_shiftreg4.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg4.inc rename to FPGA_Quartus_13.1/video/lpm_shiftreg4.inc diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg4.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg4.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg4.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg4.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg4.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg4.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg4.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg5.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg5.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg5.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg5.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.inc b/FPGA_Quartus_13.1/video/lpm_shiftreg5.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg5.inc rename to FPGA_Quartus_13.1/video/lpm_shiftreg5.inc diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg5.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg5.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg5.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg5.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg5.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg5.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg5.vhd diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg6.bsf rename to FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.cmp b/FPGA_Quartus_13.1/video/lpm_shiftreg6.cmp similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg6.cmp rename to FPGA_Quartus_13.1/video/lpm_shiftreg6.cmp diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.inc b/FPGA_Quartus_13.1/video/lpm_shiftreg6.inc similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg6.inc rename to FPGA_Quartus_13.1/video/lpm_shiftreg6.inc diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.qip b/FPGA_Quartus_13.1/video/lpm_shiftreg6.qip similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg6.qip rename to FPGA_Quartus_13.1/video/lpm_shiftreg6.qip diff --git a/FPGA_Quartus_13.1/Video/lpm_shiftreg6.vhd b/FPGA_Quartus_13.1/video/lpm_shiftreg6.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/lpm_shiftreg6.vhd rename to FPGA_Quartus_13.1/video/lpm_shiftreg6.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41.vhd b/FPGA_Quartus_13.1/video/mux41.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41.vhd rename to FPGA_Quartus_13.1/video/mux41.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41_0.vhd b/FPGA_Quartus_13.1/video/mux41_0.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41_0.vhd rename to FPGA_Quartus_13.1/video/mux41_0.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41_1.vhd b/FPGA_Quartus_13.1/video/mux41_1.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41_1.vhd rename to FPGA_Quartus_13.1/video/mux41_1.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41_2.vhd b/FPGA_Quartus_13.1/video/mux41_2.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41_2.vhd rename to FPGA_Quartus_13.1/video/mux41_2.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41_3.vhd b/FPGA_Quartus_13.1/video/mux41_3.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41_3.vhd rename to FPGA_Quartus_13.1/video/mux41_3.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41_4.vhd b/FPGA_Quartus_13.1/video/mux41_4.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41_4.vhd rename to FPGA_Quartus_13.1/video/mux41_4.vhd diff --git a/FPGA_Quartus_13.1/Video/mux41_5.vhd b/FPGA_Quartus_13.1/video/mux41_5.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/mux41_5.vhd rename to FPGA_Quartus_13.1/video/mux41_5.vhd diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/video/video.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/video.vhd rename to FPGA_Quartus_13.1/video/video.vhd diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/video/video_mod_mux_clutctr.vhd similarity index 100% rename from FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd rename to FPGA_Quartus_13.1/video/video_mod_mux_clutctr.vhd From e0269dc6c9133a04ce903009f5edf121eb8dc67d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 06:43:24 +0000 Subject: [PATCH 115/127] remove remaining .bsf (schematics) files --- FPGA_Quartus_13.1/altddio_out0.bsf | 64 ---------- FPGA_Quartus_13.1/altddio_out3.bsf | 64 ---------- FPGA_Quartus_13.1/altpll0.bsf | 117 ------------------ FPGA_Quartus_13.1/altpll2.bsf | 117 ------------------ FPGA_Quartus_13.1/altpll3.bsf | 112 ----------------- FPGA_Quartus_13.1/altpll4.bsf | 125 ------------------- FPGA_Quartus_13.1/altpll_reconfig0.bsf | 162 ------------------------- FPGA_Quartus_13.1/altpll_reconfig1.bsf | 162 ------------------------- FPGA_Quartus_13.1/lpm_bustri_BYT.bsf | 56 --------- FPGA_Quartus_13.1/lpm_bustri_LONG.bsf | 56 --------- FPGA_Quartus_13.1/lpm_bustri_WORD.bsf | 56 --------- FPGA_Quartus_13.1/lpm_counter0.bsf | 49 -------- FPGA_Quartus_13.1/lpm_latch0.bsf | 53 -------- 13 files changed, 1193 deletions(-) delete mode 100644 FPGA_Quartus_13.1/altddio_out0.bsf delete mode 100644 FPGA_Quartus_13.1/altddio_out3.bsf delete mode 100644 FPGA_Quartus_13.1/altpll0.bsf delete mode 100644 FPGA_Quartus_13.1/altpll2.bsf delete mode 100644 FPGA_Quartus_13.1/altpll3.bsf delete mode 100644 FPGA_Quartus_13.1/altpll4.bsf delete mode 100644 FPGA_Quartus_13.1/altpll_reconfig0.bsf delete mode 100644 FPGA_Quartus_13.1/altpll_reconfig1.bsf delete mode 100644 FPGA_Quartus_13.1/lpm_bustri_BYT.bsf delete mode 100644 FPGA_Quartus_13.1/lpm_bustri_LONG.bsf delete mode 100644 FPGA_Quartus_13.1/lpm_bustri_WORD.bsf delete mode 100644 FPGA_Quartus_13.1/lpm_counter0.bsf delete mode 100644 FPGA_Quartus_13.1/lpm_latch0.bsf diff --git a/FPGA_Quartus_13.1/altddio_out0.bsf b/FPGA_Quartus_13.1/altddio_out0.bsf deleted file mode 100644 index 9889d79..0000000 --- a/FPGA_Quartus_13.1/altddio_out0.bsf +++ /dev/null @@ -1,64 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 232 120) - (text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 104 25 116)(font "Arial" )) - (port - (pt 0 24) - (input) - (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) - (line (pt 0 24)(pt 88 24)(line_width 1)) - ) - (port - (pt 0 40) - (input) - (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) - (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 88 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) - (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 88 56)(line_width 1)) - ) - (port - (pt 232 24) - (output) - (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) - (line (pt 232 24)(pt 152 24)(line_width 1)) - ) - (drawing - (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) - (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) - (text "power up" (rect 92 74 129 86)(font "Arial" )) - (text "low" (rect 92 84 105 96)(font "Arial" )) - (line (pt 88 16)(pt 152 16)(line_width 1)) - (line (pt 152 16)(pt 152 96)(line_width 1)) - (line (pt 152 96)(pt 88 96)(line_width 1)) - (line (pt 88 96)(pt 88 16)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/altddio_out3.bsf b/FPGA_Quartus_13.1/altddio_out3.bsf deleted file mode 100644 index ba8c153..0000000 --- a/FPGA_Quartus_13.1/altddio_out3.bsf +++ /dev/null @@ -1,64 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 232 120) - (text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 104 25 116)(font "Arial" )) - (port - (pt 0 24) - (input) - (text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8))) - (line (pt 0 24)(pt 88 24)(line_width 1)) - ) - (port - (pt 0 40) - (input) - (text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8))) - (text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 88 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8))) - (text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 88 56)(line_width 1)) - ) - (port - (pt 232 24) - (output) - (text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8))) - (line (pt 232 24)(pt 152 24)(line_width 1)) - ) - (drawing - (text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8))) - (text "output" (rect 105 42 135 55)(font "Arial" (font_size 8))) - (text "power up" (rect 92 74 129 86)(font "Arial" )) - (text "low" (rect 92 84 105 96)(font "Arial" )) - (line (pt 88 16)(pt 152 16)(line_width 1)) - (line (pt 152 16)(pt 152 96)(line_width 1)) - (line (pt 152 96)(pt 88 96)(line_width 1)) - (line (pt 88 96)(pt 88 16)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/altpll0.bsf b/FPGA_Quartus_13.1/altpll0.bsf deleted file mode 100644 index b9a2853..0000000 --- a/FPGA_Quartus_13.1/altpll0.bsf +++ /dev/null @@ -1,117 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 280 248) - (text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 229 31 244)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)(line_width 1)) - ) - (port - (pt 280 72) - (output) - (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8))) - (line (pt 280 72)(pt 248 72)(line_width 1)) - ) - (port - (pt 280 96) - (output) - (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8))) - (line (pt 280 96)(pt 248 96)(line_width 1)) - ) - (port - (pt 280 120) - (output) - (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8))) - (line (pt 280 120)(pt 248 120)(line_width 1)) - ) - (port - (pt 280 144) - (output) - (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8))) - (line (pt 280 144)(pt 248 144)(line_width 1)) - ) - (port - (pt 280 168) - (output) - (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) - (text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8))) - (line (pt 280 168)(pt 248 168)(line_width 1)) - ) - (drawing - (text "Cyclone III" (rect 205 230 253 244)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) - (text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" )) - (text "Clk " (rect 59 111 76 125)(font "Arial" )) - (text "Ratio" (rect 90 111 114 125)(font "Arial" )) - (text "Ph (dg)" (rect 128 111 163 125)(font "Arial" )) - (text "DC (%)" (rect 173 111 208 125)(font "Arial" )) - (text "c0" (rect 63 129 75 143)(font "Arial" )) - (text "16/11" (rect 89 129 116 143)(font "Arial" )) - (text "0.00" (rect 136 129 157 143)(font "Arial" )) - (text "50.00" (rect 178 129 205 143)(font "Arial" )) - (text "c1" (rect 63 147 75 161)(font "Arial" )) - (text "50/11" (rect 89 147 116 161)(font "Arial" )) - (text "0.00" (rect 136 147 157 161)(font "Arial" )) - (text "50.00" (rect 178 147 205 161)(font "Arial" )) - (text "c2" (rect 63 165 75 179)(font "Arial" )) - (text "40/11" (rect 89 165 116 179)(font "Arial" )) - (text "0.00" (rect 136 165 157 179)(font "Arial" )) - (text "50.00" (rect 178 165 205 179)(font "Arial" )) - (text "c3" (rect 63 183 75 197)(font "Arial" )) - (text "109/33" (rect 85 183 118 197)(font "Arial" )) - (text "0.00" (rect 136 183 157 197)(font "Arial" )) - (text "50.00" (rect 178 183 205 197)(font "Arial" )) - (text "c4" (rect 63 201 75 215)(font "Arial" )) - (text "109/39" (rect 85 201 118 215)(font "Arial" )) - (text "0.00" (rect 136 201 157 215)(font "Arial" )) - (text "50.00" (rect 178 201 205 215)(font "Arial" )) - (line (pt 0 0)(pt 281 0)(line_width 1)) - (line (pt 281 0)(pt 281 249)(line_width 1)) - (line (pt 0 249)(pt 281 249)(line_width 1)) - (line (pt 0 0)(pt 0 249)(line_width 1)) - (line (pt 56 108)(pt 215 108)(line_width 1)) - (line (pt 56 125)(pt 215 125)(line_width 1)) - (line (pt 56 143)(pt 215 143)(line_width 1)) - (line (pt 56 161)(pt 215 161)(line_width 1)) - (line (pt 56 179)(pt 215 179)(line_width 1)) - (line (pt 56 197)(pt 215 197)(line_width 1)) - (line (pt 56 215)(pt 215 215)(line_width 1)) - (line (pt 56 108)(pt 56 215)(line_width 1)) - (line (pt 82 108)(pt 82 215)(line_width 3)) - (line (pt 125 108)(pt 125 215)(line_width 3)) - (line (pt 170 108)(pt 170 215)(line_width 3)) - (line (pt 214 108)(pt 214 215)(line_width 1)) - (line (pt 48 56)(pt 248 56)(line_width 1)) - (line (pt 248 56)(pt 248 232)(line_width 1)) - (line (pt 48 232)(pt 248 232)(line_width 1)) - (line (pt 48 56)(pt 48 232)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/altpll2.bsf b/FPGA_Quartus_13.1/altpll2.bsf deleted file mode 100644 index 4bad59d..0000000 --- a/FPGA_Quartus_13.1/altpll2.bsf +++ /dev/null @@ -1,117 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2014 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 256 200) - (text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 185 26 196)(font "Arial" )) - (port - (pt 0 64) - (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) - ) - (port - (pt 256 64) - (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) - ) - (port - (pt 256 80) - (output) - (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) - ) - (port - (pt 256 96) - (output) - (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8))) - ) - (port - (pt 256 112) - (output) - (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8))) - ) - (port - (pt 256 128) - (output) - (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8))) - ) - (drawing - (text "Cyclone III" (rect 198 186 442 382)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) - (text "Clk " (rect 51 91 117 192)(font "Arial" )) - (text "Ratio" (rect 71 91 165 192)(font "Arial" )) - (text "Ph (dg)" (rect 97 91 225 192)(font "Arial" )) - (text "DC (%)" (rect 132 91 296 192)(font "Arial" )) - (text "c0" (rect 54 104 119 218)(font "Arial" )) - (text "4/1" (rect 76 104 165 218)(font "Arial" )) - (text "240.00" (rect 98 104 225 218)(font "Arial" )) - (text "50.00" (rect 136 104 296 218)(font "Arial" )) - (text "c1" (rect 54 117 118 244)(font "Arial" )) - (text "4/1" (rect 76 117 165 244)(font "Arial" )) - (text "0.00" (rect 103 117 225 244)(font "Arial" )) - (text "50.00" (rect 136 117 296 244)(font "Arial" )) - (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "4/1" (rect 76 130 165 270)(font "Arial" )) - (text "180.00" (rect 98 130 224 270)(font "Arial" )) - (text "50.00" (rect 136 130 296 270)(font "Arial" )) - (text "c3" (rect 54 143 119 296)(font "Arial" )) - (text "4/1" (rect 76 143 165 296)(font "Arial" )) - (text "105.00" (rect 98 143 224 296)(font "Arial" )) - (text "50.00" (rect 136 143 296 296)(font "Arial" )) - (text "c4" (rect 54 156 119 322)(font "Arial" )) - (text "2/1" (rect 76 156 165 322)(font "Arial" )) - (text "270.00" (rect 98 156 225 322)(font "Arial" )) - (text "50.00" (rect 136 156 296 322)(font "Arial" )) - (line (pt 0 0)(pt 257 0)) - (line (pt 257 0)(pt 257 201)) - (line (pt 0 201)(pt 257 201)) - (line (pt 0 0)(pt 0 201)) - (line (pt 48 89)(pt 164 89)) - (line (pt 48 101)(pt 164 101)) - (line (pt 48 114)(pt 164 114)) - (line (pt 48 127)(pt 164 127)) - (line (pt 48 140)(pt 164 140)) - (line (pt 48 153)(pt 164 153)) - (line (pt 48 166)(pt 164 166)) - (line (pt 48 89)(pt 48 166)) - (line (pt 68 89)(pt 68 166)(line_width 3)) - (line (pt 94 89)(pt 94 166)(line_width 3)) - (line (pt 129 89)(pt 129 166)(line_width 3)) - (line (pt 163 89)(pt 163 166)) - (line (pt 40 48)(pt 223 48)) - (line (pt 223 48)(pt 223 183)) - (line (pt 40 183)(pt 223 183)) - (line (pt 40 48)(pt 40 183)) - (line (pt 255 64)(pt 223 64)) - (line (pt 255 80)(pt 223 80)) - (line (pt 255 96)(pt 223 96)) - (line (pt 255 112)(pt 223 112)) - (line (pt 255 128)(pt 223 128)) - ) -) diff --git a/FPGA_Quartus_13.1/altpll3.bsf b/FPGA_Quartus_13.1/altpll3.bsf deleted file mode 100644 index 1665956..0000000 --- a/FPGA_Quartus_13.1/altpll3.bsf +++ /dev/null @@ -1,112 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2014 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 216 296) - (text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 277 31 292)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 16 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) - (text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) - (text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) - (text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8))) - 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 216 296) - (text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10))) - (text "inst" (rect 8 277 31 292)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8))) - (text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 16 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8))) - (text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8))) - (text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8))) - (text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8))) - 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(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8))) - (line (pt 216 248)(pt 200 248)(line_width 1)) - ) - (drawing - (line (pt 0 0)(pt 217 0)(line_width 1)) - (line (pt 217 0)(pt 217 297)(line_width 1)) - (line (pt 0 297)(pt 217 297)(line_width 1)) - (line (pt 0 0)(pt 0 297)(line_width 1)) - (line (pt 16 24)(pt 201 24)(line_width 1)) - (line (pt 201 24)(pt 201 273)(line_width 1)) - (line (pt 16 273)(pt 201 273)(line_width 1)) - (line (pt 16 24)(pt 16 273)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/lpm_bustri_BYT.bsf b/FPGA_Quartus_13.1/lpm_bustri_BYT.bsf deleted file mode 100644 index dcc4b63..0000000 --- a/FPGA_Quartus_13.1/lpm_bustri_BYT.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 96 40) - (text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 96 24) - (bidir) - (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) - (text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 96 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "8" (rect 71 25 76 37)(font "Arial" )) - (text "8" (rect 15 25 20 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 66 28)(pt 74 20)(line_width 1)) - (line (pt 10 28)(pt 18 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/lpm_bustri_LONG.bsf b/FPGA_Quartus_13.1/lpm_bustri_LONG.bsf deleted file mode 100644 index 6535d3e..0000000 --- a/FPGA_Quartus_13.1/lpm_bustri_LONG.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 112 40) - (text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 112 24) - (bidir) - (text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) - (text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 112 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "32" (rect 77 25 87 37)(font "Arial" )) - (text "32" (rect 13 25 23 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 72 28)(pt 80 20)(line_width 1)) - (line (pt 8 28)(pt 16 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/lpm_bustri_WORD.bsf b/FPGA_Quartus_13.1/lpm_bustri_WORD.bsf deleted file mode 100644 index 4e882d1..0000000 --- a/FPGA_Quartus_13.1/lpm_bustri_WORD.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 112 40) - (text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 112 24) - (bidir) - (text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) - (text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 112 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "16" (rect 77 25 87 37)(font "Arial" )) - (text "16" (rect 13 25 23 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 72 28)(pt 80 20)(line_width 1)) - (line (pt 8 28)(pt 16 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/lpm_counter0.bsf b/FPGA_Quartus_13.1/lpm_counter0.bsf deleted file mode 100644 index 7fc7aaa..0000000 --- a/FPGA_Quartus_13.1/lpm_counter0.bsf +++ /dev/null @@ -1,49 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 64) - (text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 48 25 60)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 144 40) - (output) - (text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8))) - (line (pt 144 40)(pt 128 40)(line_width 3)) - ) - (drawing - (text "up counter" (rect 84 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 48)(line_width 1)) - (line (pt 128 48)(pt 16 48)(line_width 1)) - (line (pt 16 48)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/lpm_latch0.bsf b/FPGA_Quartus_13.1/lpm_latch0.bsf deleted file mode 100644 index ddb325c..0000000 --- a/FPGA_Quartus_13.1/lpm_latch0.bsf +++ /dev/null @@ -1,53 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 80) - (text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) - (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (drawing - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 64)(line_width 1)) - (line (pt 144 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - ) -) From 386851c02b634aa90da66c2f87bc86cb60445f4b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 07:13:44 +0000 Subject: [PATCH 116/127] delete remaininf .bsf (schematics) files --- .../FalconIO_SDCard_IDE_CF/dcfifo0.bsf | 95 ---------- .../FalconIO_SDCard_IDE_CF/dcfifo1.bsf | 95 ---------- FPGA_Quartus_13.1/video/altddio_bidir0.bsf | 99 ---------- FPGA_Quartus_13.1/video/altddio_out0.bsf | 64 ------- FPGA_Quartus_13.1/video/altddio_out1.bsf | 64 ------- FPGA_Quartus_13.1/video/altddio_out2.bsf | 64 ------- FPGA_Quartus_13.1/video/altdpram0.bsf | 173 ------------------ FPGA_Quartus_13.1/video/altdpram1.bsf | 173 ------------------ FPGA_Quartus_13.1/video/altdpram2.bsf | 173 ------------------ FPGA_Quartus_13.1/video/lpm_bustri0.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri1.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri2.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri3.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri4.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri5.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri6.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_bustri7.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_compare1.bsf | 54 ------ FPGA_Quartus_13.1/video/lpm_constant0.bsf | 42 ----- FPGA_Quartus_13.1/video/lpm_constant1.bsf | 42 ----- FPGA_Quartus_13.1/video/lpm_constant2.bsf | 42 ----- FPGA_Quartus_13.1/video/lpm_constant3.bsf | 42 ----- FPGA_Quartus_13.1/video/lpm_constant4.bsf | 42 ----- FPGA_Quartus_13.1/video/lpm_ff0.bsf | 63 ------- FPGA_Quartus_13.1/video/lpm_ff1.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_ff2.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_ff3.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_ff4.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_ff5.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_ff6.bsf | 63 ------- FPGA_Quartus_13.1/video/lpm_fifoDZ.bsf | 79 -------- FPGA_Quartus_13.1/video/lpm_fifo_dc0.bsf | 102 ----------- FPGA_Quartus_13.1/video/lpm_latch1.bsf | 53 ------ FPGA_Quartus_13.1/video/lpm_mux0.bsf | 83 --------- FPGA_Quartus_13.1/video/lpm_mux1.bsf | 111 ----------- FPGA_Quartus_13.1/video/lpm_mux2.bsf | 167 ----------------- FPGA_Quartus_13.1/video/lpm_mux3.bsf | 60 ------ FPGA_Quartus_13.1/video/lpm_mux4.bsf | 60 ------ FPGA_Quartus_13.1/video/lpm_mux5.bsf | 74 -------- FPGA_Quartus_13.1/video/lpm_mux6.bsf | 111 ----------- FPGA_Quartus_13.1/video/lpm_muxDZ.bsf | 76 -------- FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf | 60 ------ FPGA_Quartus_13.1/video/lpm_muxVDM.bsf | 158 ---------------- FPGA_Quartus_13.1/video/lpm_shiftreg0.bsf | 70 ------- FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf | 56 ------ FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf | 56 ------ 50 files changed, 3718 deletions(-) delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf delete mode 100644 FPGA_Quartus_13.1/video/altddio_bidir0.bsf delete mode 100644 FPGA_Quartus_13.1/video/altddio_out0.bsf delete mode 100644 FPGA_Quartus_13.1/video/altddio_out1.bsf delete mode 100644 FPGA_Quartus_13.1/video/altddio_out2.bsf delete mode 100644 FPGA_Quartus_13.1/video/altdpram0.bsf delete mode 100644 FPGA_Quartus_13.1/video/altdpram1.bsf delete mode 100644 FPGA_Quartus_13.1/video/altdpram2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri0.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri3.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri4.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri5.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri6.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_bustri7.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_compare1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_constant0.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_constant1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_constant2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_constant3.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_constant4.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff0.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff3.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff4.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff5.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_ff6.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_fifoDZ.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_fifo_dc0.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_latch1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux0.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux3.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux4.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux5.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_mux6.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_muxDZ.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_muxVDM.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg0.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf delete mode 100644 FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf deleted file mode 100644 index f4d66a5..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf +++ /dev/null @@ -1,95 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 168) - (text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 152 25 164)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 104) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 16 104)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) - (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 0 144) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 16 144)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) - (text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 3)) - ) - (port - (pt 160 96) - (output) - (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8))) - (line (pt 160 96)(pt 144 96)(line_width 3)) - ) - (drawing - (text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 152)(line_width 1)) - (line (pt 144 152)(pt 16 152)(line_width 1)) - (line (pt 16 152)(pt 16 16)(line_width 1)) - (line (pt 16 84)(pt 144 84)(line_width 1)) - (line (pt 16 132)(pt 144 132)(line_width 1)) - (line (pt 16 66)(pt 22 72)(line_width 1)) - (line (pt 22 72)(pt 16 78)(line_width 1)) - (line (pt 16 114)(pt 22 120)(line_width 1)) - (line (pt 22 120)(pt 16 126)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf deleted file mode 100644 index 7a4a386..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf +++ /dev/null @@ -1,95 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) - (text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "3" (rect 63 25 68 37)(font "Arial" )) - (text "3" (rect 15 25 20 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 58 28)(pt 66 20)(line_width 1)) - (line (pt 10 28)(pt 18 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_bustri2.bsf b/FPGA_Quartus_13.1/video/lpm_bustri2.bsf deleted file mode 100644 index 36a4813..0000000 --- a/FPGA_Quartus_13.1/video/lpm_bustri2.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) - (text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "18" (rect 61 25 71 37)(font "Arial" )) - (text "18" (rect 13 25 23 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 56 28)(pt 64 20)(line_width 1)) - (line (pt 8 28)(pt 16 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_bustri3.bsf b/FPGA_Quartus_13.1/video/lpm_bustri3.bsf deleted file mode 100644 index 2dde401..0000000 --- a/FPGA_Quartus_13.1/video/lpm_bustri3.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) - (text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "6" (rect 63 25 68 37)(font "Arial" )) - (text "6" (rect 15 25 20 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 58 28)(pt 66 20)(line_width 1)) - (line (pt 10 28)(pt 18 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_bustri4.bsf b/FPGA_Quartus_13.1/video/lpm_bustri4.bsf deleted file mode 100644 index cd9edcc..0000000 --- a/FPGA_Quartus_13.1/video/lpm_bustri4.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) - (text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "5" (rect 63 25 68 37)(font "Arial" )) - (text "5" (rect 15 25 20 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 58 28)(pt 66 20)(line_width 1)) - (line (pt 10 28)(pt 18 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_bustri5.bsf b/FPGA_Quartus_13.1/video/lpm_bustri5.bsf deleted file mode 100644 index 1d9b178..0000000 --- a/FPGA_Quartus_13.1/video/lpm_bustri5.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) - (text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "8" (rect 63 25 68 37)(font "Arial" )) - (text "8" (rect 15 25 20 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 58 28)(pt 66 20)(line_width 1)) - (line (pt 10 28)(pt 18 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_bustri6.bsf b/FPGA_Quartus_13.1/video/lpm_bustri6.bsf deleted file mode 100644 index 4c9344e..0000000 --- a/FPGA_Quartus_13.1/video/lpm_bustri6.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8))) - (text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "24" (rect 61 25 71 37)(font "Arial" )) - (text "24" (rect 13 25 23 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 56 28)(pt 64 20)(line_width 1)) - (line (pt 8 28)(pt 16 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_bustri7.bsf b/FPGA_Quartus_13.1/video/lpm_bustri7.bsf deleted file mode 100644 index 399a828..0000000 --- a/FPGA_Quartus_13.1/video/lpm_bustri7.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 40) - (text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 24 25 36)(font "Arial" )) - (port - (pt 40 40) - (input) - (text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8))) - (text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible)) - (line (pt 40 40)(pt 40 28)(line_width 1)) - ) - (port - (pt 0 24) - (input) - (text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 0 24)(pt 32 24)(line_width 3)) - ) - (port - (pt 80 24) - (bidir) - (text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8))) - (text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 80 24)(pt 48 24)(line_width 3)) - ) - (drawing - (text "4" (rect 63 25 68 37)(font "Arial" )) - (text "4" (rect 15 25 20 37)(font "Arial" )) - (line (pt 32 16)(pt 48 24)(line_width 1)) - (line (pt 48 24)(pt 32 32)(line_width 1)) - (line (pt 32 32)(pt 32 16)(line_width 1)) - (line (pt 58 28)(pt 66 20)(line_width 1)) - (line (pt 10 28)(pt 18 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_compare1.bsf b/FPGA_Quartus_13.1/video/lpm_compare1.bsf deleted file mode 100644 index 9ec3796..0000000 --- a/FPGA_Quartus_13.1/video/lpm_compare1.bsf +++ /dev/null @@ -1,54 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 128 96) - (text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 80 25 92)(font "Arial" )) - (port - (pt 0 48) - (input) - (text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 3)) - ) - (port - (pt 0 64) - (input) - (text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 16 64)(line_width 3)) - ) - (port - (pt 128 56) - (output) - (text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8))) - (line (pt 128 56)(pt 112 56)(line_width 1)) - ) - (drawing - (text "unsigned compare" (rect 36 17 112 29)(font "Arial" )) - (line (pt 16 16)(pt 112 16)(line_width 1)) - (line (pt 112 16)(pt 112 80)(line_width 1)) - (line (pt 112 80)(pt 16 80)(line_width 1)) - (line (pt 16 80)(pt 16 16)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_constant0.bsf b/FPGA_Quartus_13.1/video/lpm_constant0.bsf deleted file mode 100644 index 684bbae..0000000 --- a/FPGA_Quartus_13.1/video/lpm_constant0.bsf +++ /dev/null @@ -1,42 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 96 48) - (text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 32 25 44)(font "Arial" )) - (port - (pt 96 24) - (output) - (text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 96 24)(pt 80 24)(line_width 3)) - ) - (drawing - (text "0" (rect 75 18 80 30)(font "Arial" )) - (text "5" (rect 87 25 92 37)(font "Arial" )) - (line (pt 16 16)(pt 80 16)(line_width 1)) - (line (pt 80 16)(pt 80 32)(line_width 1)) - (line (pt 80 32)(pt 16 32)(line_width 1)) - (line (pt 16 32)(pt 16 16)(line_width 1)) - (line (pt 82 28)(pt 90 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_constant1.bsf b/FPGA_Quartus_13.1/video/lpm_constant1.bsf deleted file mode 100644 index 01fdb2b..0000000 --- a/FPGA_Quartus_13.1/video/lpm_constant1.bsf +++ /dev/null @@ -1,42 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 96 48) - (text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 32 25 44)(font "Arial" )) - (port - (pt 96 24) - (output) - (text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 96 24)(pt 80 24)(line_width 3)) - ) - (drawing - (text "0" (rect 75 18 80 30)(font "Arial" )) - (text "2" (rect 87 25 92 37)(font "Arial" )) - (line (pt 16 16)(pt 80 16)(line_width 1)) - (line (pt 80 16)(pt 80 32)(line_width 1)) - (line (pt 80 32)(pt 16 32)(line_width 1)) - (line (pt 16 32)(pt 16 16)(line_width 1)) - (line (pt 82 28)(pt 90 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_constant2.bsf b/FPGA_Quartus_13.1/video/lpm_constant2.bsf deleted file mode 100644 index a4b7697..0000000 --- a/FPGA_Quartus_13.1/video/lpm_constant2.bsf +++ /dev/null @@ -1,42 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 96 48) - (text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 32 25 44)(font "Arial" )) - (port - (pt 96 24) - (output) - (text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 96 24)(pt 80 24)(line_width 3)) - ) - (drawing - (text "0" (rect 75 18 80 30)(font "Arial" )) - (text "8" (rect 87 25 92 37)(font "Arial" )) - (line (pt 16 16)(pt 80 16)(line_width 1)) - (line (pt 80 16)(pt 80 32)(line_width 1)) - (line (pt 80 32)(pt 16 32)(line_width 1)) - (line (pt 16 32)(pt 16 16)(line_width 1)) - (line (pt 82 28)(pt 90 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_constant3.bsf b/FPGA_Quartus_13.1/video/lpm_constant3.bsf deleted file mode 100644 index 7616869..0000000 --- a/FPGA_Quartus_13.1/video/lpm_constant3.bsf +++ /dev/null @@ -1,42 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 96 48) - (text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 32 25 44)(font "Arial" )) - (port - (pt 96 24) - (output) - (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 96 24)(pt 80 24)(line_width 3)) - ) - (drawing - (text "0" (rect 75 18 80 30)(font "Arial" )) - (text "7" (rect 87 25 92 37)(font "Arial" )) - (line (pt 16 16)(pt 80 16)(line_width 1)) - (line (pt 80 16)(pt 80 32)(line_width 1)) - (line (pt 80 32)(pt 16 32)(line_width 1)) - (line (pt 16 32)(pt 16 16)(line_width 1)) - (line (pt 82 28)(pt 90 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_constant4.bsf b/FPGA_Quartus_13.1/video/lpm_constant4.bsf deleted file mode 100644 index 181c667..0000000 --- a/FPGA_Quartus_13.1/video/lpm_constant4.bsf +++ /dev/null @@ -1,42 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 96 48) - (text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 32 25 44)(font "Arial" )) - (port - (pt 96 24) - (output) - (text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible)) - (line (pt 96 24)(pt 80 24)(line_width 3)) - ) - (drawing - (text "2040" (rect 60 18 80 30)(font "Arial" )) - (text "11" (rect 85 25 95 37)(font "Arial" )) - (line (pt 16 16)(pt 80 16)(line_width 1)) - (line (pt 80 16)(pt 80 32)(line_width 1)) - (line (pt 80 32)(pt 16 32)(line_width 1)) - (line (pt 16 32)(pt 16 16)(line_width 1)) - (line (pt 80 28)(pt 88 20)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff0.bsf b/FPGA_Quartus_13.1/video/lpm_ff0.bsf deleted file mode 100644 index 6675606..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff0.bsf +++ /dev/null @@ -1,63 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 96) - (text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 80 25 92)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 0 64) - (input) - (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) - (text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 16 64)(line_width 1)) - ) - (port - (pt 144 56) - (output) - (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 89 50 125 63)(font "Arial" (font_size 8))) - (line (pt 144 56)(pt 128 56)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 80)(line_width 1)) - (line (pt 128 80)(pt 16 80)(line_width 1)) - (line (pt 16 80)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff1.bsf b/FPGA_Quartus_13.1/video/lpm_ff1.bsf deleted file mode 100644 index 947a023..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff1.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff2.bsf b/FPGA_Quartus_13.1/video/lpm_ff2.bsf deleted file mode 100644 index b52c75b..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff2.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) - (text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff3.bsf b/FPGA_Quartus_13.1/video/lpm_ff3.bsf deleted file mode 100644 index 51248ea..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff3.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff4.bsf b/FPGA_Quartus_13.1/video/lpm_ff4.bsf deleted file mode 100644 index be432cb..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff4.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff5.bsf b/FPGA_Quartus_13.1/video/lpm_ff5.bsf deleted file mode 100644 index a69af6e..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff5.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_ff6.bsf b/FPGA_Quartus_13.1/video/lpm_ff6.bsf deleted file mode 100644 index 73a2df0..0000000 --- a/FPGA_Quartus_13.1/video/lpm_ff6.bsf +++ /dev/null @@ -1,63 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 96) - (text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 80 25 92)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 0 64) - (input) - (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) - (text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 16 64)(line_width 1)) - ) - (port - (pt 144 56) - (output) - (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) - (text "q[127..0]" (rect 83 50 125 63)(font "Arial" (font_size 8))) - (line (pt 144 56)(pt 128 56)(line_width 3)) - ) - (drawing - (text "DFF" (rect 109 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 80)(line_width 1)) - (line (pt 128 80)(pt 16 80)(line_width 1)) - (line (pt 16 80)(pt 16 16)(line_width 1)) - (line (pt 16 42)(pt 22 48)(line_width 1)) - (line (pt 22 48)(pt 16 54)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_fifoDZ.bsf b/FPGA_Quartus_13.1/video/lpm_fifoDZ.bsf deleted file mode 100644 index 1e24640..0000000 --- a/FPGA_Quartus_13.1/video/lpm_fifoDZ.bsf +++ /dev/null @@ -1,79 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 144) - (text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10))) - (text "inst" (rect 8 125 31 140)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8))) - (text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8))) - (text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8))) - (text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (drawing - (text "(ack)" (rect 51 67 76 81)(font "Arial" )) - (text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 128)(line_width 1)) - (line (pt 144 128)(pt 16 128)(line_width 1)) - (line (pt 16 128)(pt 16 16)(line_width 1)) - (line (pt 16 108)(pt 144 108)(line_width 1)) - (line (pt 16 90)(pt 22 96)(line_width 1)) - (line (pt 22 96)(pt 16 102)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_fifo_dc0.bsf b/FPGA_Quartus_13.1/video/lpm_fifo_dc0.bsf deleted file mode 100644 index 61b485b..0000000 --- a/FPGA_Quartus_13.1/video/lpm_fifo_dc0.bsf +++ /dev/null @@ -1,102 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 168) - (text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 152 25 164)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 16 56)(line_width 1)) - ) - (port - (pt 0 72) - (input) - (text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 16 72)(line_width 1)) - ) - (port - (pt 0 104) - (input) - (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) - (text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 16 104)(line_width 1)) - ) - (port - (pt 0 120) - (input) - (text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8))) - (text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 16 120)(line_width 1)) - ) - (port - (pt 0 144) - (input) - (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) - (text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 16 144)(line_width 1)) - ) - (port - (pt 160 72) - (output) - (text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8))) - (text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8))) - (line (pt 160 72)(pt 144 72)(line_width 3)) - ) - (port - (pt 160 96) - (output) - (text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8))) - (text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8))) - (line (pt 160 96)(pt 144 96)(line_width 3)) - ) - (port - (pt 160 120) - (output) - (text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8))) - (text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8))) - (line (pt 160 120)(pt 144 120)(line_width 1)) - ) - (drawing - (text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" )) - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 152)(line_width 1)) - (line (pt 144 152)(pt 16 152)(line_width 1)) - (line (pt 16 152)(pt 16 16)(line_width 1)) - (line (pt 16 84)(pt 144 84)(line_width 1)) - (line (pt 16 132)(pt 144 132)(line_width 1)) - (line (pt 16 66)(pt 22 72)(line_width 1)) - (line (pt 22 72)(pt 16 78)(line_width 1)) - (line (pt 16 114)(pt 22 120)(line_width 1)) - (line (pt 22 120)(pt 16 126)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_latch1.bsf b/FPGA_Quartus_13.1/video/lpm_latch1.bsf deleted file mode 100644 index 7197b2f..0000000 --- a/FPGA_Quartus_13.1/video/lpm_latch1.bsf +++ /dev/null @@ -1,53 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 160 80) - (text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 3)) - ) - (port - (pt 0 48) - (input) - (text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8))) - (text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 160 32) - (output) - (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8))) - (line (pt 160 32)(pt 144 32)(line_width 3)) - ) - (drawing - (line (pt 16 16)(pt 144 16)(line_width 1)) - (line (pt 144 16)(pt 144 64)(line_width 1)) - (line (pt 144 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_mux0.bsf b/FPGA_Quartus_13.1/video/lpm_mux0.bsf deleted file mode 100644 index ce1e27e..0000000 --- a/FPGA_Quartus_13.1/video/lpm_mux0.bsf +++ /dev/null @@ -1,83 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 152 128) - (text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 112 25 124)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 72 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 72 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 72 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 72 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 72 104)(line_width 1)) - ) - (port - (pt 80 128) - (input) - (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) - (text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8))) - (line (pt 80 128)(pt 80 116)(line_width 3)) - ) - (port - (pt 152 72) - (output) - (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8))) - (line (pt 152 72)(pt 88 72)(line_width 3)) - ) - (drawing - (line (pt 72 24)(pt 72 120)(line_width 1)) - (line (pt 88 32)(pt 88 112)(line_width 1)) - (line (pt 72 24)(pt 88 32)(line_width 1)) - (line (pt 72 120)(pt 88 112)(line_width 1)) - (line (pt 72 98)(pt 78 104)(line_width 1)) - (line (pt 78 104)(pt 72 110)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_mux1.bsf b/FPGA_Quartus_13.1/video/lpm_mux1.bsf deleted file mode 100644 index 24ee953..0000000 --- a/FPGA_Quartus_13.1/video/lpm_mux1.bsf +++ /dev/null @@ -1,111 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 152 192) - (text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 176 25 188)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 72 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 72 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 72 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 72 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 72 104)(line_width 3)) - ) - (port - (pt 0 120) - (input) - (text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 72 120)(line_width 3)) - ) - (port - (pt 0 136) - (input) - (text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) - (line (pt 0 136)(pt 72 136)(line_width 3)) - ) - (port - (pt 0 152) - (input) - (text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 72 152)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 72 168)(line_width 1)) - ) - (port - (pt 80 192) - (input) - (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) - (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) - (line (pt 80 192)(pt 80 180)(line_width 3)) - ) - (port - (pt 152 104) - (output) - (text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) - (line (pt 152 104)(pt 88 104)(line_width 3)) - ) - (drawing - (line (pt 72 24)(pt 72 184)(line_width 1)) - (line (pt 88 32)(pt 88 176)(line_width 1)) - (line (pt 72 24)(pt 88 32)(line_width 1)) - (line (pt 72 184)(pt 88 176)(line_width 1)) - (line (pt 72 162)(pt 78 168)(line_width 1)) - (line (pt 78 168)(pt 72 174)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_mux2.bsf b/FPGA_Quartus_13.1/video/lpm_mux2.bsf deleted file mode 100644 index b37c425..0000000 --- a/FPGA_Quartus_13.1/video/lpm_mux2.bsf +++ /dev/null @@ -1,167 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 80 80) - (text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 32 40)(line_width 1)) - ) - (port - (pt 0 56) - (input) - (text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 32 56)(line_width 1)) - ) - (port - (pt 40 80) - (input) - (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8))) - (line (pt 40 80)(pt 40 68)(line_width 1)) - ) - (port - (pt 80 48) - (output) - (text "result" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "result" (rect 50 35 75 48)(font "Arial" (font_size 8))) - (line (pt 80 48)(pt 48 48)(line_width 1)) - ) - (drawing - (line (pt 32 24)(pt 32 72)(line_width 1)) - (line (pt 48 32)(pt 48 64)(line_width 1)) - (line (pt 32 24)(pt 48 32)(line_width 1)) - (line (pt 32 72)(pt 48 64)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_mux4.bsf b/FPGA_Quartus_13.1/video/lpm_mux4.bsf deleted file mode 100644 index a1c9ca0..0000000 --- a/FPGA_Quartus_13.1/video/lpm_mux4.bsf +++ /dev/null @@ -1,60 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 136 80) - (text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 64 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 64 56)(line_width 3)) - ) - (port - (pt 72 80) - (input) - (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8))) - (line (pt 72 80)(pt 72 68)(line_width 1)) - ) - (port - (pt 136 48) - (output) - (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8))) - (line (pt 136 48)(pt 80 48)(line_width 3)) - ) - (drawing - (line (pt 64 24)(pt 64 72)(line_width 1)) - (line (pt 80 32)(pt 80 64)(line_width 1)) - (line (pt 64 24)(pt 80 32)(line_width 1)) - (line (pt 64 72)(pt 80 64)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_mux5.bsf b/FPGA_Quartus_13.1/video/lpm_mux5.bsf deleted file mode 100644 index e63ce50..0000000 --- a/FPGA_Quartus_13.1/video/lpm_mux5.bsf +++ /dev/null @@ -1,74 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 152 112) - (text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 96 25 108)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 72 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 72 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 72 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 72 88)(line_width 3)) - ) - (port - (pt 80 112) - (input) - (text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) - (text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8))) - (line (pt 80 112)(pt 80 100)(line_width 3)) - ) - (port - (pt 152 64) - (output) - (text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8))) - (line (pt 152 64)(pt 88 64)(line_width 3)) - ) - (drawing - (line (pt 72 24)(pt 72 104)(line_width 1)) - (line (pt 88 32)(pt 88 96)(line_width 1)) - (line (pt 72 24)(pt 88 32)(line_width 1)) - (line (pt 72 104)(pt 88 96)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_mux6.bsf b/FPGA_Quartus_13.1/video/lpm_mux6.bsf deleted file mode 100644 index 2196842..0000000 --- a/FPGA_Quartus_13.1/video/lpm_mux6.bsf +++ /dev/null @@ -1,111 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 152 192) - (text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 176 25 188)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 72 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 72 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 72 72)(line_width 3)) - ) - (port - (pt 0 88) - (input) - (text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 72 88)(line_width 3)) - ) - (port - (pt 0 104) - (input) - (text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8))) - (line (pt 0 104)(pt 72 104)(line_width 3)) - ) - (port - (pt 0 120) - (input) - (text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8))) - (line (pt 0 120)(pt 72 120)(line_width 3)) - ) - (port - (pt 0 136) - (input) - (text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8))) - (line (pt 0 136)(pt 72 136)(line_width 3)) - ) - (port - (pt 0 152) - (input) - (text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8))) - (line (pt 0 152)(pt 72 152)(line_width 3)) - ) - (port - (pt 0 168) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8))) - (line (pt 0 168)(pt 72 168)(line_width 1)) - ) - (port - (pt 80 192) - (input) - (text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8))) - (text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8))) - (line (pt 80 192)(pt 80 180)(line_width 3)) - ) - (port - (pt 152 104) - (output) - (text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) - (text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8))) - (line (pt 152 104)(pt 88 104)(line_width 3)) - ) - (drawing - (line (pt 72 24)(pt 72 184)(line_width 1)) - (line (pt 88 32)(pt 88 176)(line_width 1)) - (line (pt 72 24)(pt 88 32)(line_width 1)) - (line (pt 72 184)(pt 88 176)(line_width 1)) - (line (pt 72 162)(pt 78 168)(line_width 1)) - (line (pt 78 168)(pt 72 174)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_muxDZ.bsf b/FPGA_Quartus_13.1/video/lpm_muxDZ.bsf deleted file mode 100644 index f4f1c7d..0000000 --- a/FPGA_Quartus_13.1/video/lpm_muxDZ.bsf +++ /dev/null @@ -1,76 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 168 112) - (text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10))) - (text "inst" (rect 8 96 25 108)(font "Arial" )) - (port - (pt 0 40) - (input) - (text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) - (text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8))) - (line (pt 0 40)(pt 80 40)(line_width 3)) - ) - (port - (pt 0 56) - (input) - (text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) - (text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8))) - (line (pt 0 56)(pt 80 56)(line_width 3)) - ) - (port - (pt 0 72) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 80 72)(line_width 1)) - ) - (port - (pt 0 88) - (input) - (text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8))) - (line (pt 0 88)(pt 80 88)(line_width 1)) - ) - (port - (pt 88 112) - (input) - (text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8))) - (text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8))) - (line (pt 88 112)(pt 88 100)(line_width 1)) - ) - (port - (pt 168 64) - (output) - (text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8))) - (line (pt 168 64)(pt 96 64)(line_width 3)) - ) - (drawing - (line (pt 80 24)(pt 80 104)(line_width 1)) - (line (pt 96 32)(pt 96 96)(line_width 1)) - (line (pt 80 24)(pt 96 32)(line_width 1)) - (line (pt 80 104)(pt 96 96)(line_width 1)) - (line (pt 80 66)(pt 86 72)(line_width 1)) - (line (pt 86 72)(pt 80 78)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf b/FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf deleted file mode 100644 index b7e3184..0000000 --- a/FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf +++ /dev/null @@ -1,60 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2009 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. 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File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 128) - (text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 112 25 124)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "load" (rect 0 0 23 14)(font "Arial" (font_size 8))) - (text "load" (rect 20 26 41 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) - (text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 3)) - ) - (port - (pt 0 80) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8))) - (line (pt 0 80)(pt 16 80)(line_width 1)) - ) - (port - (pt 0 96) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 16 96)(line_width 1)) - ) - (port - (pt 144 72) - (output) - (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8))) - (line (pt 144 72)(pt 128 72)(line_width 1)) - ) - (drawing - (text "left shift" (rect 92 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 112)(line_width 1)) - (line (pt 128 112)(pt 16 112)(line_width 1)) - (line (pt 16 112)(pt 16 16)(line_width 1)) - (line (pt 16 74)(pt 22 80)(line_width 1)) - (line (pt 22 80)(pt 16 86)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf deleted file mode 100644 index aa20405..0000000 --- a/FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "left shift" (rect 92 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf deleted file mode 100644 index 0caa084..0000000 --- a/FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 1)) - ) - (drawing - (text "right shift" (rect 88 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf deleted file mode 100644 index d18b388..0000000 --- a/FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 1)) - ) - (drawing - (text "right shift" (rect 88 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf deleted file mode 100644 index 658958d..0000000 --- a/FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8))) - (text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 1)) - ) - (drawing - (text "right shift" (rect 88 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf deleted file mode 100644 index a528c96..0000000 --- a/FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "right shift" (rect 88 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) diff --git a/FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf b/FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf deleted file mode 100644 index aa0296b..0000000 --- a/FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf +++ /dev/null @@ -1,56 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2008 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.1")) -(symbol - (rect 0 0 144 80) - (text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10))) - (text "inst" (rect 8 64 25 76)(font "Arial" )) - (port - (pt 0 32) - (input) - (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) - (text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8))) - (line (pt 0 32)(pt 16 32)(line_width 1)) - ) - (port - (pt 0 48) - (input) - (text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8))) - (text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8))) - (line (pt 0 48)(pt 16 48)(line_width 1)) - ) - (port - (pt 144 48) - (output) - (text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8))) - (text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8))) - (line (pt 144 48)(pt 128 48)(line_width 3)) - ) - (drawing - (text "right shift" (rect 88 17 128 29)(font "Arial" )) - (line (pt 16 16)(pt 128 16)(line_width 1)) - (line (pt 128 16)(pt 128 64)(line_width 1)) - (line (pt 128 64)(pt 16 64)(line_width 1)) - (line (pt 16 64)(pt 16 16)(line_width 1)) - (line (pt 16 26)(pt 22 32)(line_width 1)) - (line (pt 22 32)(pt 16 38)(line_width 1)) - ) -) From 4ae6e349cdc44cf21b0a6f30683fb150ac8e2703 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 07:16:07 +0000 Subject: [PATCH 117/127] this one escaped me ... --- FPGA_Quartus_13.1/altpll1.bsf | 100 ---------------------------------- 1 file changed, 100 deletions(-) delete mode 100644 FPGA_Quartus_13.1/altpll1.bsf diff --git a/FPGA_Quartus_13.1/altpll1.bsf b/FPGA_Quartus_13.1/altpll1.bsf deleted file mode 100644 index 9649e11..0000000 --- a/FPGA_Quartus_13.1/altpll1.bsf +++ /dev/null @@ -1,100 +0,0 @@ -/* -WARNING: Do NOT edit the input and output ports in this file in a text -editor if you plan to continue editing the block that represents it in -the Block Editor! File corruption is VERY likely to occur. -*/ -/* -Copyright (C) 1991-2014 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. -*/ -(header "symbol" (version "1.2")) -(symbol - (rect 0 0 272 176) - (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 161 26 172)(font "Arial" )) - (port - (pt 0 64) - (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) - ) - (port - (pt 272 64) - (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8))) - ) - (port - (pt 272 80) - (output) - (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8))) - ) - (port - (pt 272 96) - (output) - (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8))) - ) - (port - (pt 272 112) - (output) - (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) - (text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8))) - ) - (drawing - (text "Cyclone III" (rect 214 162 474 334)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) - (text "Clk " (rect 51 91 117 192)(font "Arial" )) - (text "Ratio" (rect 82 91 187 192)(font "Arial" )) - (text "Ph (dg)" (rect 119 91 269 192)(font "Arial" )) - (text "DC (%)" (rect 154 91 340 192)(font "Arial" )) - (text "c0" (rect 54 104 119 218)(font "Arial" )) - (text "16/11" (rect 82 104 186 218)(font "Arial" )) - (text "0.00" (rect 125 104 269 218)(font "Arial" )) - (text "50.00" (rect 158 104 340 218)(font "Arial" )) - (text "c1" (rect 54 117 118 244)(font "Arial" )) - (text "16/33" (rect 82 117 187 244)(font "Arial" )) - (text "0.00" (rect 125 117 269 244)(font "Arial" )) - (text "50.00" (rect 158 117 340 244)(font "Arial" )) - (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "1024/1375" (rect 71 130 185 270)(font "Arial" )) - (text "0.00" (rect 125 130 269 270)(font "Arial" )) - (text "50.00" (rect 158 130 340 270)(font "Arial" )) - (line (pt 0 0)(pt 273 0)) - (line (pt 273 0)(pt 273 177)) - (line (pt 0 177)(pt 273 177)) - (line (pt 0 0)(pt 0 177)) - (line (pt 48 89)(pt 186 89)) - (line (pt 48 101)(pt 186 101)) - (line (pt 48 114)(pt 186 114)) - (line (pt 48 127)(pt 186 127)) - (line (pt 48 140)(pt 186 140)) - (line (pt 48 89)(pt 48 140)) - (line (pt 68 89)(pt 68 140)(line_width 3)) - (line (pt 116 89)(pt 116 140)(line_width 3)) - (line (pt 151 89)(pt 151 140)(line_width 3)) - (line (pt 185 89)(pt 185 140)) - (line (pt 40 48)(pt 223 48)) - (line (pt 223 48)(pt 223 159)) - (line (pt 40 159)(pt 223 159)) - (line (pt 40 48)(pt 40 159)) - (line (pt 271 64)(pt 223 64)) - (line (pt 271 80)(pt 223 80)) - (line (pt 271 96)(pt 223 96)) - (line (pt 271 112)(pt 223 112)) - ) -) From 7a046661542e175f516ee99611ad58228c0e4abf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 13:27:25 +0000 Subject: [PATCH 118/127] complete flexbus_register component (nearly) --- .../Interrupt_Handler/interrupt_handler.vhd | 145 +- FPGA_Quartus_13.1/firebee1.qsf | 1496 ++++++++--------- FPGA_Quartus_13.1/firebee1.vhd | 4 +- FPGA_Quartus_13.1/firebee_groups.sdc | 7 +- FPGA_Quartus_13.1/flexbus_register.vhd | 49 +- FPGA_Quartus_13.1/video/ddr_controller.vhd | 43 +- 6 files changed, 892 insertions(+), 852 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index b88570c..e832ccf 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -182,13 +182,13 @@ end interrupt_handler; ARCHITECTURE rtl OF interrupt_handler IS -- WERTE REGISTER 0-63 - signal FB_B : std_logic_vector(3 downto 0); - signal INT_CTR : std_logic_vector(31 downto 0); - signal INT_CTR_d : std_logic_vector(31 downto 0); - signal INT_CTR_q : std_logic_vector(31 downto 0); + signal fb_b : std_logic_vector(3 downto 0); + signal int_ctr : std_logic_vector(31 downto 0); + signal int_ctr_d : std_logic_vector(31 downto 0); + signal int_ctr_q : std_logic_vector(31 downto 0); - signal INT_LATCH : std_logic_vector(31 downto 0); - signal INT_LATCH_d : std_logic_vector(31 downto 0); + signal int_latch : std_logic_vector(31 downto 0); + signal int_latch_d : std_logic_vector(31 downto 0); signal INT_LATCH_clrn : std_logic_vector(31 downto 0); signal INT_LATCH_q : std_logic_vector(31 downto 0); signal INT_LATCH_clk : std_logic_vector(31 downto 0); @@ -475,7 +475,7 @@ begin begin if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then if INT_CTR24_ena_ctrl='1' then - INT_CTR_q(31 downto 24) <= INT_CTR_d(31 downto 24); + int_ctr_q(31 downto 24) <= int_ctr_d(31 downto 24); end if; end if; end process; @@ -484,7 +484,7 @@ begin begin if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then if INT_CTR16_ena_ctrl='1' then - INT_CTR_q(23 downto 16) <= INT_CTR_d(23 downto 16); + int_ctr_q(23 downto 16) <= int_ctr_d(23 downto 16); end if; end if; end process; @@ -493,7 +493,7 @@ begin begin if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then if INT_CTR8_ena_ctrl='1' then - INT_CTR_q(15 downto 8) <= INT_CTR_d(15 downto 8); + int_ctr_q(15 downto 8) <= int_ctr_d(15 downto 8); end if; end if; end process; @@ -502,7 +502,7 @@ begin begin if INT_CTR0_clk_ctrl'event and INT_CTR0_clk_ctrl='1' then if INT_CTR0_ena_ctrl='1' then - INT_CTR_q(7 downto 0) <= INT_CTR_d(7 downto 0); + int_ctr_q(7 downto 0) <= int_ctr_d(7 downto 0); end if; end if; end process; @@ -512,7 +512,7 @@ begin if INT_LATCH_clrn(31)='0' then INT_LATCH_q(31) <= '0'; elsif INT_LATCH_clk(31)'event and INT_LATCH_clk(31)='1' then - INT_LATCH_q(31) <= INT_LATCH_d(31); + INT_LATCH_q(31) <= int_latch_d(31); end if; end process; @@ -521,7 +521,7 @@ begin if INT_LATCH_clrn(30)='0' then INT_LATCH_q(30) <= '0'; elsif INT_LATCH_clk(30)'event and INT_LATCH_clk(30)='1' then - INT_LATCH_q(30) <= INT_LATCH_d(30); + INT_LATCH_q(30) <= int_latch_d(30); end if; end process; @@ -530,7 +530,7 @@ begin if INT_LATCH_clrn(29)='0' then INT_LATCH_q(29) <= '0'; elsif INT_LATCH_clk(29)'event and INT_LATCH_clk(29)='1' then - INT_LATCH_q(29) <= INT_LATCH_d(29); + INT_LATCH_q(29) <= int_latch_d(29); end if; end process; @@ -538,7 +538,7 @@ begin if INT_LATCH_clrn(28)='0' then INT_LATCH_q(28) <= '0'; elsif INT_LATCH_clk(28)'event and INT_LATCH_clk(28)='1' then - INT_LATCH_q(28) <= INT_LATCH_d(28); + INT_LATCH_q(28) <= int_latch_d(28); end if; end process; @@ -546,7 +546,7 @@ begin if INT_LATCH_clrn(27)='0' then INT_LATCH_q(27) <= '0'; elsif INT_LATCH_clk(27)'event and INT_LATCH_clk(27)='1' then - INT_LATCH_q(27) <= INT_LATCH_d(27); + INT_LATCH_q(27) <= int_latch_d(27); end if; end process; @@ -554,7 +554,7 @@ begin if INT_LATCH_clrn(26)='0' then INT_LATCH_q(26) <= '0'; elsif INT_LATCH_clk(26)'event and INT_LATCH_clk(26)='1' then - INT_LATCH_q(26) <= INT_LATCH_d(26); + INT_LATCH_q(26) <= int_latch_d(26); end if; end process; @@ -562,7 +562,7 @@ begin if INT_LATCH_clrn(25)='0' then INT_LATCH_q(25) <= '0'; elsif INT_LATCH_clk(25)'event and INT_LATCH_clk(25)='1' then - INT_LATCH_q(25) <= INT_LATCH_d(25); + INT_LATCH_q(25) <= int_latch_d(25); end if; end process; @@ -570,7 +570,7 @@ begin if INT_LATCH_clrn(24)='0' then INT_LATCH_q(24) <= '0'; elsif INT_LATCH_clk(24)'event and INT_LATCH_clk(24)='1' then - INT_LATCH_q(24) <= INT_LATCH_d(24); + INT_LATCH_q(24) <= int_latch_d(24); end if; end process; @@ -578,7 +578,7 @@ begin if INT_LATCH_clrn(23)='0' then INT_LATCH_q(23) <= '0'; elsif INT_LATCH_clk(23)'event and INT_LATCH_clk(23)='1' then - INT_LATCH_q(23) <= INT_LATCH_d(23); + INT_LATCH_q(23) <= int_latch_d(23); end if; end process; @@ -586,7 +586,7 @@ begin if INT_LATCH_clrn(22)='0' then INT_LATCH_q(22) <= '0'; elsif INT_LATCH_clk(22)'event and INT_LATCH_clk(22)='1' then - INT_LATCH_q(22) <= INT_LATCH_d(22); + INT_LATCH_q(22) <= int_latch_d(22); end if; end process; @@ -594,7 +594,7 @@ begin if INT_LATCH_clrn(21)='0' then INT_LATCH_q(21) <= '0'; elsif INT_LATCH_clk(21)'event and INT_LATCH_clk(21)='1' then - INT_LATCH_q(21) <= INT_LATCH_d(21); + INT_LATCH_q(21) <= int_latch_d(21); end if; end process; @@ -602,7 +602,7 @@ begin if INT_LATCH_clrn(20)='0' then INT_LATCH_q(20) <= '0'; elsif INT_LATCH_clk(20)'event and INT_LATCH_clk(20)='1' then - INT_LATCH_q(20) <= INT_LATCH_d(20); + INT_LATCH_q(20) <= int_latch_d(20); end if; end process; @@ -610,7 +610,7 @@ begin if INT_LATCH_clrn(19)='0' then INT_LATCH_q(19) <= '0'; elsif INT_LATCH_clk(19)'event and INT_LATCH_clk(19)='1' then - INT_LATCH_q(19) <= INT_LATCH_d(19); + INT_LATCH_q(19) <= int_latch_d(19); end if; end process; @@ -618,7 +618,7 @@ begin if INT_LATCH_clrn(18)='0' then INT_LATCH_q(18) <= '0'; elsif INT_LATCH_clk(18)'event and INT_LATCH_clk(18)='1' then - INT_LATCH_q(18) <= INT_LATCH_d(18); + INT_LATCH_q(18) <= int_latch_d(18); end if; end process; @@ -626,7 +626,7 @@ begin if INT_LATCH_clrn(17)='0' then INT_LATCH_q(17) <= '0'; elsif INT_LATCH_clk(17)'event and INT_LATCH_clk(17)='1' then - INT_LATCH_q(17) <= INT_LATCH_d(17); + INT_LATCH_q(17) <= int_latch_d(17); end if; end process; @@ -634,7 +634,7 @@ begin if INT_LATCH_clrn(16)='0' then INT_LATCH_q(16) <= '0'; elsif INT_LATCH_clk(16)'event and INT_LATCH_clk(16)='1' then - INT_LATCH_q(16) <= INT_LATCH_d(16); + INT_LATCH_q(16) <= int_latch_d(16); end if; end process; @@ -642,7 +642,7 @@ begin if INT_LATCH_clrn(15)='0' then INT_LATCH_q(15) <= '0'; elsif INT_LATCH_clk(15)'event and INT_LATCH_clk(15)='1' then - INT_LATCH_q(15) <= INT_LATCH_d(15); + INT_LATCH_q(15) <= int_latch_d(15); end if; end process; @@ -650,7 +650,7 @@ begin if INT_LATCH_clrn(14)='0' then INT_LATCH_q(14) <= '0'; elsif INT_LATCH_clk(14)'event and INT_LATCH_clk(14)='1' then - INT_LATCH_q(14) <= INT_LATCH_d(14); + INT_LATCH_q(14) <= int_latch_d(14); end if; end process; @@ -658,7 +658,7 @@ begin if INT_LATCH_clrn(13)='0' then INT_LATCH_q(13) <= '0'; elsif INT_LATCH_clk(13)'event and INT_LATCH_clk(13)='1' then - INT_LATCH_q(13) <= INT_LATCH_d(13); + INT_LATCH_q(13) <= int_latch_d(13); end if; end process; @@ -666,7 +666,7 @@ begin if INT_LATCH_clrn(12)='0' then INT_LATCH_q(12) <= '0'; elsif INT_LATCH_clk(12)'event and INT_LATCH_clk(12)='1' then - INT_LATCH_q(12) <= INT_LATCH_d(12); + INT_LATCH_q(12) <= int_latch_d(12); end if; end process; @@ -674,7 +674,7 @@ begin if INT_LATCH_clrn(11)='0' then INT_LATCH_q(11) <= '0'; elsif INT_LATCH_clk(11)'event and INT_LATCH_clk(11)='1' then - INT_LATCH_q(11) <= INT_LATCH_d(11); + INT_LATCH_q(11) <= int_latch_d(11); end if; end process; @@ -682,7 +682,7 @@ begin if INT_LATCH_clrn(10)='0' then INT_LATCH_q(10) <= '0'; elsif INT_LATCH_clk(10)'event and INT_LATCH_clk(10)='1' then - INT_LATCH_q(10) <= INT_LATCH_d(10); + INT_LATCH_q(10) <= int_latch_d(10); end if; end process; @@ -690,7 +690,7 @@ begin if INT_LATCH_clrn(9)='0' then INT_LATCH_q(9) <= '0'; elsif INT_LATCH9_clk_1'event and INT_LATCH9_clk_1='1' then - INT_LATCH_q(9) <= INT_LATCH_d(9); + INT_LATCH_q(9) <= int_latch_d(9); end if; end process; @@ -698,7 +698,7 @@ begin if INT_LATCH_clrn(8)='0' then INT_LATCH_q(8) <= '0'; elsif INT_LATCH8_clk_1'event and INT_LATCH8_clk_1='1' then - INT_LATCH_q(8) <= INT_LATCH_d(8); + INT_LATCH_q(8) <= int_latch_d(8); end if; end process; @@ -706,7 +706,7 @@ begin if INT_LATCH_clrn(7)='0' then INT_LATCH_q(7) <= '0'; elsif INT_LATCH7_clk_1'event and INT_LATCH7_clk_1='1' then - INT_LATCH_q(7) <= INT_LATCH_d(7); + INT_LATCH_q(7) <= int_latch_d(7); end if; end process; @@ -714,7 +714,7 @@ begin if INT_LATCH_clrn(6)='0' then INT_LATCH_q(6) <= '0'; elsif INT_LATCH6_clk_1'event and INT_LATCH6_clk_1='1' then - INT_LATCH_q(6) <= INT_LATCH_d(6); + INT_LATCH_q(6) <= int_latch_d(6); end if; end process; @@ -722,7 +722,7 @@ begin if INT_LATCH_clrn(5)='0' then INT_LATCH_q(5) <= '0'; elsif INT_LATCH5_clk_1'event and INT_LATCH5_clk_1='1' then - INT_LATCH_q(5) <= INT_LATCH_d(5); + INT_LATCH_q(5) <= int_latch_d(5); end if; end process; @@ -730,7 +730,7 @@ begin if INT_LATCH_clrn(4)='0' then INT_LATCH_q(4) <= '0'; elsif INT_LATCH4_clk_1'event and INT_LATCH4_clk_1='1' then - INT_LATCH_q(4) <= INT_LATCH_d(4); + INT_LATCH_q(4) <= int_latch_d(4); end if; end process; @@ -738,7 +738,7 @@ begin if INT_LATCH_clrn(3)='0' then INT_LATCH_q(3) <= '0'; elsif INT_LATCH3_clk_1'event and INT_LATCH3_clk_1='1' then - INT_LATCH_q(3) <= INT_LATCH_d(3); + INT_LATCH_q(3) <= int_latch_d(3); end if; end process; @@ -746,7 +746,7 @@ begin if INT_LATCH_clrn(2)='0' then INT_LATCH_q(2) <= '0'; elsif INT_LATCH2_clk_1'event and INT_LATCH2_clk_1='1' then - INT_LATCH_q(2) <= INT_LATCH_d(2); + INT_LATCH_q(2) <= int_latch_d(2); end if; end process; @@ -754,7 +754,7 @@ begin if INT_LATCH_clrn(1)='0' then INT_LATCH_q(1) <= '0'; elsif INT_LATCH1_clk_1'event and INT_LATCH1_clk_1='1' then - INT_LATCH_q(1) <= INT_LATCH_d(1); + INT_LATCH_q(1) <= int_latch_d(1); end if; end process; @@ -763,7 +763,7 @@ begin if INT_LATCH_clrn(0)='0' then INT_LATCH_q(0) <= '0'; elsif INT_LATCH0_clk_1'event and INT_LATCH0_clk_1='1' then - INT_LATCH_q(0) <= INT_LATCH_d(0); + INT_LATCH_q(0) <= int_latch_d(0); end if; end process; @@ -5030,7 +5030,7 @@ begin -- HWORD -- HHBYT -- LONG UND LINE - FB_B(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or + fb_b(0) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or ((not FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and (not FB_ADR(0))) or ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); @@ -5038,7 +5038,7 @@ begin -- HWORD -- HLBYT -- LONG UND LINE - FB_B(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or + fb_b(1) <= (FB_SIZE1 and (not FB_SIZE0) and (not FB_ADR(1))) or ((not FB_SIZE1) and FB_SIZE0 and (not FB_ADR(1)) and FB_ADR(0)) or ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); @@ -5046,14 +5046,14 @@ begin -- LWORD -- LHBYT -- LONG UND LINE - FB_B(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or + fb_b(2) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or ((not FB_SIZE1) and FB_SIZE0 and FB_ADR(1) and (not FB_ADR(0))) or ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); -- LWORD -- LLBYT -- LONG UND LINE - FB_B(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or + fb_b(3) <= (FB_SIZE1 and (not FB_SIZE0) and FB_ADR(1)) or ((not FB_SIZE1) and FB_SIZE0 and FB_ADR(1) and FB_ADR(0)) or ((not FB_SIZE1) and (not FB_SIZE0)) or (FB_SIZE1 and FB_SIZE0); @@ -5063,11 +5063,11 @@ begin -- $10000/4 int_ctr_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; - INT_CTR_d <= fb_ad_in; - INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); - INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); - INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR); - INT_CTR0_ena_ctrl <= INT_CTR_CS and FB_B(3) and (not nFB_WR); + int_ctr_d <= fb_ad_in; + INT_CTR24_ena_ctrl <= INT_CTR_CS and fb_b(0) and (not nFB_WR); + INT_CTR16_ena_ctrl <= INT_CTR_CS and fb_b(1) and (not nFB_WR); + INT_CTR8_ena_ctrl <= INT_CTR_CS and fb_b(2) and (not nFB_WR); + INT_CTR0_ena_ctrl <= INT_CTR_CS and fb_b(3) and (not nFB_WR); -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA0_clk_ctrl <= MAIN_CLK; @@ -5079,10 +5079,10 @@ begin -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = -- "00000000000100000000000001"); INT_ENA_d <= fb_ad_in; - INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); - INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); - INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR); - INT_ENA0_ena_ctrl <= INT_ENA_CS and FB_B(3) and (not nFB_WR); + INT_ENA24_ena_ctrl <= INT_ENA_CS and fb_b(0) and (not nFB_WR); + INT_ENA16_ena_ctrl <= INT_ENA_CS and fb_b(1) and (not nFB_WR); + INT_ENA8_ena_ctrl <= INT_ENA_CS and fb_b(2) and (not nFB_WR); + INT_ENA0_ena_ctrl <= INT_ENA_CS and fb_b(3) and (not nFB_WR); -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR0_clk_ctrl <= MAIN_CLK; @@ -5091,16 +5091,17 @@ begin int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0'; -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000000100000000000010"); + int_clear_d(31 downto 24) <= fb_ad_in(31 downto 24) when int_clear_cs and fb_b(0) and not nfb_wr; int_clear_d(23 downto 16) <= fb_ad_in(23 downto 16) when int_clear_cs and fb_b(1) and not nfb_wr; int_clear_d(15 downto 8) <= fb_ad_in(15 downto 8) when int_clear_cs and fb_b(2) and not nfb_wr; int_clear_d(7 downto 0) <= fb_ad_in(7 downto 0) when int_clear_cs and fb_b(3) and not nfb_wr; --- INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); --- INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); --- INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); --- INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(31 downto 24) <= fb_ad_in(31 downto 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(0),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(23 downto 16) <= fb_ad_in(23 downto 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(1),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(15 downto 8) <= fb_ad_in(15 downto 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(2),8) and sizeIt(not nFB_WR,8); +-- INT_CLEAR_d(7 downto 0) <= fb_ad_in(7 downto 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(fb_b(3),8) and sizeIt(not nFB_WR,8); -- INTERRUPT LATCH REGISTER READ ONLY -- $1000C/4 @@ -5110,7 +5111,7 @@ begin -- INTERRUPT nIRQ(2) <= not (HSYNC and INT_ENA_q(26)); - nIRQ(3) <= not (INT_CTR_q(0) and INT_ENA_q(27)); + nIRQ(3) <= not (int_ctr_q(0) and INT_ENA_q(27)); nIRQ(4) <= not (VSYNC and INT_ENA_q(28)); nIRQ(5) <= not (to_std_logic(INT_LATCH_q /= "00000000000000000000000000000000") and INT_ENA_q(29)); nIRQ(6) <= not ((not nMFP_INT) and INT_ENA_q(30)); @@ -5168,7 +5169,7 @@ begin INT_LA2_0_clk_ctrl <= MAIN_CLK; INT_LA1_0_clk_ctrl <= MAIN_CLK; INT_LA0_0_clk_ctrl <= MAIN_CLK; - INT_LATCH_d <= "11111111111111111111111111111111"; + int_latch_d <= "11111111111111111111111111111111"; INT_LATCH_clrn <= (not INT_CLEAR_q) and sizeIt(nRSTO,32); INT_LA0_0_clrn_ctrl <= INT_ENA_q(0) and nRSTO; INT_LA0_d <= ((std_logic_vector'(unsigned(INT_LA0_q) + unsigned'("0001"))) and sizeIt(INT_L_q(0),4) and sizeIt(to_std_logic((unsigned(INT_LA0_q) @@ -5292,7 +5293,7 @@ begin INT_IN(9) <= HSYNC; INT_IN(25 downto 10) <= "0000000000000000"; INT_IN(26) <= HSYNC; - INT_IN(27) <= INT_CTR_q(0); + INT_IN(27) <= int_ctr_q(0); INT_IN(28) <= VSYNC; INT_IN(29) <= to_std_logic(INT_LATCH_q /= "00000000000000000000000000000000"); INT_IN(30) <= not nMFP_INT; @@ -5305,10 +5306,10 @@ begin -- $4'0000/4 ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 downto 2) = "00000000010000000000000000"); ACP_CONF_d <= fb_ad_in; - ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR); - ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR); - ACP_CONF8_ena_ctrl <= ACP_CONF_CS and FB_B(2) and (not nFB_WR); - ACP_CONF0_ena_ctrl <= ACP_CONF_CS and FB_B(3) and (not nFB_WR); + ACP_CONF24_ena_ctrl <= ACP_CONF_CS and fb_b(0) and (not nFB_WR); + ACP_CONF16_ena_ctrl <= ACP_CONF_CS and fb_b(1) and (not nFB_WR); + ACP_CONF8_ena_ctrl <= ACP_CONF_CS and fb_b(2) and (not nFB_WR); + ACP_CONF0_ena_ctrl <= ACP_CONF_CS and fb_b(3) and (not nFB_WR); -- *************************************************************************************** -- ------------------------------------------------------------ @@ -5318,10 +5319,10 @@ begin RTC_ADR_d <= fb_ad_in(21 downto 16); -- FFFF8961 - UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110000") and FB_B(1); + UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110000") and fb_b(1); -- FFFF8963 - UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110001") and FB_B(3); + UHR_DS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100010010110001") and fb_b(3); RTC_ADR0_ena_ctrl <= UHR_AS and (not nFB_WR); WERTE7_0_clk_ctrl <= MAIN_CLK; WERTE6_0_clk_ctrl <= MAIN_CLK; @@ -5964,7 +5965,7 @@ begin "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8))); -- TRISTATE OUTPUT --- u0_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(31 downto 24)) or +-- u0_data <= (sizeIt(INT_CTR_CS,8) and int_ctr_q(31 downto 24)) or -- (sizeIt(INT_ENA_CS,8) and INT_ENA_q(31 downto 24)) or -- (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(31 downto 24)) or -- (sizeIt(INT_CLEAR_CS,8) and INT_IN(31 downto 24)) or @@ -6191,7 +6192,7 @@ begin WERTE2_q(63) & WERTE1_q(63) & WERTE0_q(63)) and sizeIt(to_std_logic(RTC_ADR_q = "111111"),8) and sizeIt(UHR_DS,8)) or (std_logic_vector'("00" & RTC_ADR_q) and sizeIt(UHR_AS,8)) or - (sizeIt(INT_CTR_CS,8) and INT_CTR_q(23 downto 16)) or + (sizeIt(INT_CTR_CS,8) and int_ctr_q(23 downto 16)) or (sizeIt(INT_ENA_CS,8) and INT_ENA_q(23 downto 16)) or (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(23 downto 16)) or (sizeIt(INT_CLEAR_CS,8) and INT_IN(23 downto 16)) or @@ -6200,7 +6201,7 @@ begin u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); fb_ad_out(23 downto 16) <= u1_tridata; --- u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 downto 8)) or +-- u2_data <= (sizeIt(INT_CTR_CS,8) and int_ctr_q(15 downto 8)) or -- (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 downto 8)) or -- (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 downto 8)) or -- (sizeIt(INT_CLEAR_CS,8) and INT_IN(15 downto 8)) or @@ -6216,7 +6217,7 @@ begin acp_conf_q(15 downto 8) when acp_conf_cs and not nfb_oe else (others => 'Z'); --- u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 downto 0)) or +-- u3_data <= (sizeIt(INT_CTR_CS,8) and int_ctr_q(7 downto 0)) or -- (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 downto 0)) or -- (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 downto 0)) or -- (sizeIt(INT_CLEAR_CS,8) and INT_IN(7 downto 0)) or diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index a9a68e7..85aadb8 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,314 +556,314 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name VHDL_FILE video/video.vhd -set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE video/ddr_controller.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE video/mux41.vhd -set_global_assignment -name VHDL_FILE video/mux41_5.vhd -set_global_assignment -name VHDL_FILE video/mux41_4.vhd -set_global_assignment -name VHDL_FILE video/mux41_3.vhd -set_global_assignment -name VHDL_FILE video/mux41_2.vhd -set_global_assignment -name VHDL_FILE video/mux41_1.vhd -set_global_assignment -name VHDL_FILE video/mux41_0.vhd -set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE video/altdpram2.cmp -set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE video/altdpram0.qip -set_global_assignment -name QIP_FILE video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE video/altdpram1.qip -set_global_assignment -name QIP_FILE video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE video/lpm_constant0.qip -set_global_assignment -name QIP_FILE video/lpm_constant1.qip -set_global_assignment -name QIP_FILE video/lpm_mux0.qip -set_global_assignment -name QIP_FILE video/lpm_mux1.qip -set_global_assignment -name QIP_FILE video/lpm_mux2.qip -set_global_assignment -name QIP_FILE video/lpm_constant2.qip -set_global_assignment -name QIP_FILE video/altdpram2.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE video/altddio_out0.qip -set_global_assignment -name QIP_FILE video/lpm_mux5.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE video/altddio_out1.qip -set_global_assignment -name QIP_FILE video/altddio_out2.qip -set_global_assignment -name QIP_FILE video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE video/lpm_mux6.qip -set_global_assignment -name QIP_FILE video/lpm_mux3.qip -set_global_assignment -name QIP_FILE video/lpm_mux4.qip -set_global_assignment -name QIP_FILE video/lpm_constant3.qip -set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE video/lpm_latch1.qip -set_global_assignment -name QIP_FILE video/lpm_constant4.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE video/lpm_ff4.qip -set_global_assignment -name QIP_FILE video/lpm_ff5.qip -set_global_assignment -name QIP_FILE video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd - - +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE video/video.vhd +set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE video/ddr_controller.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE video/mux41.vhd +set_global_assignment -name VHDL_FILE video/mux41_5.vhd +set_global_assignment -name VHDL_FILE video/mux41_4.vhd +set_global_assignment -name VHDL_FILE video/mux41_3.vhd +set_global_assignment -name VHDL_FILE video/mux41_2.vhd +set_global_assignment -name VHDL_FILE video/mux41_1.vhd +set_global_assignment -name VHDL_FILE video/mux41_0.vhd +set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE video/altdpram2.cmp +set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE video/altdpram0.qip +set_global_assignment -name QIP_FILE video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE video/altdpram1.qip +set_global_assignment -name QIP_FILE video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE video/lpm_constant0.qip +set_global_assignment -name QIP_FILE video/lpm_constant1.qip +set_global_assignment -name QIP_FILE video/lpm_mux0.qip +set_global_assignment -name QIP_FILE video/lpm_mux1.qip +set_global_assignment -name QIP_FILE video/lpm_mux2.qip +set_global_assignment -name QIP_FILE video/lpm_constant2.qip +set_global_assignment -name QIP_FILE video/altdpram2.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE video/altddio_out0.qip +set_global_assignment -name QIP_FILE video/lpm_mux5.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE video/altddio_out1.qip +set_global_assignment -name QIP_FILE video/altddio_out2.qip +set_global_assignment -name QIP_FILE video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE video/lpm_mux6.qip +set_global_assignment -name QIP_FILE video/lpm_mux3.qip +set_global_assignment -name QIP_FILE video/lpm_mux4.qip +set_global_assignment -name QIP_FILE video/lpm_constant3.qip +set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE video/lpm_latch1.qip +set_global_assignment -name QIP_FILE video/lpm_constant4.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE video/lpm_ff4.qip +set_global_assignment -name QIP_FILE video/lpm_ff5.qip +set_global_assignment -name QIP_FILE video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd + + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index fbce6a1..4c78b37 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -35,7 +35,7 @@ entity firebee1 is SD_DATA0 : in std_logic; SD_DATA1 : in std_logic; SD_DATA2 : in std_logic; - SD_CARD_DEDECT : in std_logic; + sd_card_detect : in std_logic; nSCSI_DRQ : in std_logic; SD_WP : in std_logic; nRD_DATA : in std_logic; @@ -331,7 +331,7 @@ begin SD_DATA0 => SD_DATA0, SD_DATA1 => SD_DATA1, SD_DATA2 => SD_DATA2, - SD_CARD_DEDECT => SD_CARD_DEDECT, + sd_card_dedect => sd_card_detect, SD_WP => SD_WP, nDACK0 => nDACK0, nFB_WR => nFB_WR, diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 16b6afb..02b3cb1 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -195,8 +195,11 @@ set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \ #************************************************************** if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } { - post_message -type info "Over constraining hold" + post_message -type info "Over constraining hold for MAIN_CLK" set_clock_uncertainty -add -enable_same_physical_edge -from { MAIN_CLK } -to { MAIN_CLK } -hold 0.2 } - +if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } { + post_message -type info "Over constraining setup for i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]" + set_clock_uncertainty -add -enable_same_physical_edge -from { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -to { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -setup 0.2 +} diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd index d7aea7e..df202a5 100644 --- a/FPGA_Quartus_13.1/flexbus_register.vhd +++ b/FPGA_Quartus_13.1/flexbus_register.vhd @@ -25,7 +25,7 @@ entity flexbus_register is fb_wr_n : in std_logic; fb_oe_n : in std_logic; fb_size : in std_logic_vector(1 downto 0); - + register_ta : out std_logic ); end entity flexbus_register; @@ -71,10 +71,45 @@ begin fbcs_match <= '1' when not(fb_cs_n(match_fbcs)) = '1' else '0'; address_match <= f_addr_cmp_mask(fb_addr, match_address, num_ignore); - - p_register_access : process(all) - begin - if rising_edge(clk) then - end if; - end process p_register_access; + cs <= '1' when fbcs_match and address_match else '0'; + + p_copy_data_in : process (all) + begin + reg_value <= reg_value; + if cs and not fb_wr_n then + if reg_width > 24 and fb_b(0) = '1' then -- HH byte + reg_value(reg_width - 1 downto 24) <= fb_ad_in(work.firebee_utils_pkg.min(31, reg_width - 1) downto 24); + end if; + if reg_width > 16 and fb_b(1) = '1' then -- HL byte + reg_value(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16) <= fb_ad_in(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16); + end if; + if reg_width > 8 and fb_b(2) = '1' then -- LH byte + reg_value(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8) <= fb_ad_in(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8); + end if; + if reg_width > 0 and fb_b(3) = '1' then -- LL byte + reg_value(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0) <= fb_ad_in(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0); + end if; + end if; + end process p_copy_data_in; + + p_copy_data_out : process (all) + begin + fb_ad_out <= (others => 'Z'); + if cs and not fb_oe_n then + if reg_width > 24 and fb_b(0) = '1' then -- HH byte + fb_ad_out(work.firebee_utils_pkg.min(31, reg_width - 1) downto 24) <= reg_value(work.firebee_utils_pkg.min(31, reg_width - 1) downto 24); + end if; + if reg_width > 16 and fb_b(1) = '1' then -- HL byte + fb_ad_out(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16) <= reg_value(work.firebee_utils_pkg.min(23, reg_width - 1) downto 16); + end if; + if reg_width > 8 and fb_b(2) = '1' then -- LH byte + fb_ad_out(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8) <= reg_value(work.firebee_utils_pkg.min(15, reg_width - 1) downto 8); + end if; + if reg_width > 0 and fb_b(3) = '1' then -- LL byte + fb_ad_out(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0) <= reg_value(work.firebee_utils_pkg.min(7, reg_width - 1) downto 0); + end if; + end if; + end process p_copy_data_out; + + register_ta <= cs; end architecture rtl; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/video/ddr_controller.vhd b/FPGA_Quartus_13.1/video/ddr_controller.vhd index b7d5087..c288688 100755 --- a/FPGA_Quartus_13.1/video/ddr_controller.vhd +++ b/FPGA_Quartus_13.1/video/ddr_controller.vhd @@ -277,7 +277,7 @@ architecture rtl of ddr_ctr is signal LINE : std_logic; signal v_basx : std_logic_vector(1 downto 0); - signal v_basx_cs : std_logic; + signal v_basx_ta : std_logic; signal v_bash : std_logic_vector(7 downto 0); signal v_bash_cs : std_logic; @@ -562,26 +562,27 @@ begin end if; end process; --- i_vbasx : work.flexbus_register --- generic map --- ( --- reg_width => 2, --- match_address => x"ffff8603", --- match_mask => x"0000ffff", -- byte register --- match_fbcs => 1 --- ) --- port map --- ( --- clk => clk33m, --- fb_addr => fb_adr, --- fb_data => fb_ad, --- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), --- fb_ta_n => reg_ta, --- fb_wr_n => nfb_wr, --- reg_value => v_basx, --- cs => v_basx_cs --- ); --- + i_vbasx : work.flexbus_register + generic map + ( + reg_width => 8, + match_address => x"ffff8603", + num_ignore => 4, + match_fbcs => 1 + ) + port map + ( + clk => clk33m, + fb_addr => fb_adr, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, + fb_cs_n => ('1', '1', nfb_cs3, nfb_cs2, nfb_cs1), + fb_wr_n => nfb_wr, + fb_oe_n => nfb_oe, + fb_size => (fb_size1, fb_size0), + register_ta => v_basx_ta + ); + -- i_vbash : work.flexbus_register -- generic map -- ( From dc54546004e3b7666a0a74add26cffb6e0438687 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 13:27:45 +0000 Subject: [PATCH 119/127] updated workspace --- FPGA_Quartus_13.1/firebee1.qws | Bin 6086 -> 2872 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index fd8a23da25f1aa3b21f9c52816ac7ca1e79e85b1..0457c8f1521e827d6d475587b61b80b0af576558 100644 GIT binary patch literal 2872 zcmeH}O-~b16o%iSXjp+OS1uZ32q77uA5!W{EMQ1TB!28n$k3T8p*XdzNJ5A!31Q`5 zaOrRGC%7T(T)A`SFAzVTb33gt8WV`9A>8KNd(NFR=bn4s_ulEv5p~-Y)fK3vwwCl< zv6@=NYA{z-gi{}~uZnJHTn~5>;n6~`F~(Rettp2+gH_cttVmCYWqwnvjoy=S z&1q4$HO-1oc_ScFo3Vv$>#y+U9J6)e#l)J|9iH4HTE+Q>So2u3j1@eO=RHP7j}@}3 zoxi@T8hdL}k7XpHYCm%6C!YmvYKr;m{K_iPNAmG1X%gL65j`MtAFmL}p-s}~@vHGG zX+j0w3>mk+(TFK;iOy+X%mmLSlW$RMNs|GSgT!EPh!2yEMQtmqTVT`XXINx)pD_lT zWy8YAq3%+q(=GvtZ7*~#RjvNY$-~iPM0cslBM>>kN*36HTyse^NbWbO;`dXk8Kx}2 zC@;pz9@mZ^X3TrP_s#{fHC*d^LF5lzi<%y_4eAh3i-?UOrS<`@=)g44bIcjQ0bq8Z zo#j_jlHOko_uW{kTH{NBAf20j}+s<;utf2ADbw@sR zkDn6H2b0V26Wg$swmaX!Kgsj|<~x7R&O?749QY~9{Zn>&uR3h(AL6=zooU+={tkAO B+5i9m literal 6086 zcmeI0OKX!+5QZmd)gmfx6c=3-DN@8tqWX?QzZ!(64&l z7OAtGZ64{fbQ;2*AL!f$Qq-Swjpw!))2p8 zrwTql!QBu-m)1xYF^hbK^BUQHlA~(Sd5q@ERZ-C&6o;@%9)0MZm04sx%(+ILG1zFv zK`f^?fSWI-0eNhFoVvs8zcD~@38z-Cz!a2xXKCux?w5m(-gUP%GnS;Nzp@*;~aXdrnZ{o0yDo4 z9ZZ6aiS6tp#$wd#LKXimstZ>qDhhN4r#WMQ1Ulo)zq1*LeERso85s|$*$FiM1O<=y zo@Qs*r5n9|7wy^*=(1?%ETBuEsRUpXz~c0(RSUW#v;G8KoYe(jxCGOteh6fO$O{V4 z6#||rx=80+8hZm~vf8#`b{u@>`9$e5UBTLu4z!Z=raS3sQ=8NPM23tl3L+z)D+E;? zz0-*N4_t#bZmV8$2Syzjn~K}$(-5njTo2*4o(@O-^SzTVX$v@uZCti8E<5Hx-g~os z-@xQ6UhF!$LAY#@@S%;(R>r1d4{Yk&E^KZ|har!A&UnT5%;87&<4wl#CKcY)dY_{n z{M3g$ac0NxOT&Mw9LN{GDkannf7SCBy-otB+YjNdD7$t>Pd4q eu!?qp!zXPg-M}XPFV)6l%YR}4U0wKGL;nUaTl|gy From c458e4babec8eefeaa34d199c268fc5e6c6f2f3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Fri, 29 Jul 2016 18:22:56 +0000 Subject: [PATCH 120/127] increased setup overconstraint --- FPGA_Quartus_13.1/firebee1.qsf | 1492 +++++++++++++------------- FPGA_Quartus_13.1/firebee_groups.sdc | 2 +- 2 files changed, 747 insertions(+), 747 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 85aadb8..bf05838 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,314 +556,314 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name VHDL_FILE video/video.vhd -set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE video/ddr_controller.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE video/mux41.vhd -set_global_assignment -name VHDL_FILE video/mux41_5.vhd -set_global_assignment -name VHDL_FILE video/mux41_4.vhd -set_global_assignment -name VHDL_FILE video/mux41_3.vhd -set_global_assignment -name VHDL_FILE video/mux41_2.vhd -set_global_assignment -name VHDL_FILE video/mux41_1.vhd -set_global_assignment -name VHDL_FILE video/mux41_0.vhd -set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE video/altdpram2.cmp -set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE video/altdpram0.qip -set_global_assignment -name QIP_FILE video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE video/altdpram1.qip -set_global_assignment -name QIP_FILE video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE video/lpm_constant0.qip -set_global_assignment -name QIP_FILE video/lpm_constant1.qip -set_global_assignment -name QIP_FILE video/lpm_mux0.qip -set_global_assignment -name QIP_FILE video/lpm_mux1.qip -set_global_assignment -name QIP_FILE video/lpm_mux2.qip -set_global_assignment -name QIP_FILE video/lpm_constant2.qip -set_global_assignment -name QIP_FILE video/altdpram2.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE video/altddio_out0.qip -set_global_assignment -name QIP_FILE video/lpm_mux5.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE video/altddio_out1.qip -set_global_assignment -name QIP_FILE video/altddio_out2.qip -set_global_assignment -name QIP_FILE video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE video/lpm_mux6.qip -set_global_assignment -name QIP_FILE video/lpm_mux3.qip -set_global_assignment -name QIP_FILE video/lpm_mux4.qip -set_global_assignment -name QIP_FILE video/lpm_constant3.qip -set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE video/lpm_latch1.qip -set_global_assignment -name QIP_FILE video/lpm_constant4.qip -set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE video/lpm_ff4.qip -set_global_assignment -name QIP_FILE video/lpm_ff5.qip -set_global_assignment -name QIP_FILE video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name VHDL_FILE video/video.vhd +set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE video/ddr_controller.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE video/mux41.vhd +set_global_assignment -name VHDL_FILE video/mux41_5.vhd +set_global_assignment -name VHDL_FILE video/mux41_4.vhd +set_global_assignment -name VHDL_FILE video/mux41_3.vhd +set_global_assignment -name VHDL_FILE video/mux41_2.vhd +set_global_assignment -name VHDL_FILE video/mux41_1.vhd +set_global_assignment -name VHDL_FILE video/mux41_0.vhd +set_global_assignment -name VHDL_FILE video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE video/altdpram2.cmp +set_global_assignment -name VHDL_FILE video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE video/altdpram0.qip +set_global_assignment -name QIP_FILE video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE video/altdpram1.qip +set_global_assignment -name QIP_FILE video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE video/lpm_constant0.qip +set_global_assignment -name QIP_FILE video/lpm_constant1.qip +set_global_assignment -name QIP_FILE video/lpm_mux0.qip +set_global_assignment -name QIP_FILE video/lpm_mux1.qip +set_global_assignment -name QIP_FILE video/lpm_mux2.qip +set_global_assignment -name QIP_FILE video/lpm_constant2.qip +set_global_assignment -name QIP_FILE video/altdpram2.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE video/altddio_out0.qip +set_global_assignment -name QIP_FILE video/lpm_mux5.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE video/altddio_out1.qip +set_global_assignment -name QIP_FILE video/altddio_out2.qip +set_global_assignment -name QIP_FILE video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE video/lpm_mux6.qip +set_global_assignment -name QIP_FILE video/lpm_mux3.qip +set_global_assignment -name QIP_FILE video/lpm_mux4.qip +set_global_assignment -name QIP_FILE video/lpm_constant3.qip +set_global_assignment -name QIP_FILE video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE video/lpm_latch1.qip +set_global_assignment -name QIP_FILE video/lpm_constant4.qip +set_global_assignment -name QIP_FILE video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE video/lpm_ff4.qip +set_global_assignment -name QIP_FILE video/lpm_ff5.qip +set_global_assignment -name QIP_FILE video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 02b3cb1..35d21a5 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -201,5 +201,5 @@ if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } { if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } { post_message -type info "Over constraining setup for i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]" - set_clock_uncertainty -add -enable_same_physical_edge -from { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -to { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -setup 0.2 + set_clock_uncertainty -add -enable_same_physical_edge -from { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -to { i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] } -setup 0.25 } From 22b53a856007a3e9e1e4c7bec79969854b8938ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 30 Jul 2016 07:17:34 +0000 Subject: [PATCH 121/127] rename video (again?) --- FPGA_Quartus_13.1/firebee1.qsf | 179 ++++++++++++++++++++++++++++++++- FPGA_Quartus_13.1/firebee1.vhd | 101 ++++++++++++------- 2 files changed, 240 insertions(+), 40 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index bf05838..e20802e 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -866,4 +866,181 @@ set_global_assignment -name QIP_FILE altiobuf_bidir0.qip set_global_assignment -name VHDL_FILE flexbus_register.vhd -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name SIGNALTAP_FILE stp1.stp +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to MAIN_CLK -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to FB_AD[0] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to FB_AD[10] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to FB_AD[11] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to FB_AD[12] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to FB_AD[13] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to FB_AD[14] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to FB_AD[15] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to FB_AD[16] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to FB_AD[17] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to FB_AD[18] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to FB_AD[19] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to FB_AD[1] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to FB_AD[20] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to FB_AD[21] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to FB_AD[22] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to FB_AD[23] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to FB_AD[24] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to FB_AD[25] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to FB_AD[26] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to FB_AD[27] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to FB_AD[28] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to FB_AD[29] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to FB_AD[2] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to FB_AD[30] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to FB_AD[31] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to FB_AD[3] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to FB_AD[4] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to FB_AD[5] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to FB_AD[6] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to FB_AD[7] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to FB_AD[8] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to FB_AD[9] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to FB_ALE -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to FB_SIZE0 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to FB_SIZE1 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to fb_ad_in[0] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to fb_ad_in[10] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to fb_ad_in[11] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to fb_ad_in[12] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to fb_ad_in[13] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to fb_ad_in[14] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to fb_ad_in[15] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to fb_ad_in[16] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to fb_ad_in[17] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to fb_ad_in[18] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to fb_ad_in[19] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to fb_ad_in[1] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to fb_ad_in[20] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to fb_ad_in[21] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to fb_ad_in[22] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to fb_ad_in[23] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to fb_ad_in[24] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to fb_ad_in[25] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to fb_ad_in[26] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to fb_ad_in[27] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to fb_ad_in[28] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to fb_ad_in[29] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to fb_ad_in[2] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to fb_ad_in[30] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to fb_ad_in[31] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to fb_ad_in[3] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to fb_ad_in[4] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to fb_ad_in[5] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to fb_ad_in[6] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to fb_ad_in[7] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to fb_ad_in[8] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to fb_ad_in[9] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to FB_AD[0] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to FB_AD[10] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to FB_AD[11] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to FB_AD[12] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to FB_AD[13] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to FB_AD[14] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to FB_AD[15] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to FB_AD[16] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to FB_AD[17] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to FB_AD[18] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to FB_AD[19] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to FB_AD[1] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to FB_AD[20] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to FB_AD[21] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to FB_AD[22] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to FB_AD[23] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to FB_AD[24] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to FB_AD[25] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to FB_AD[26] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to FB_AD[27] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to FB_AD[28] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to FB_AD[29] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to FB_AD[2] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to FB_AD[30] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to FB_AD[31] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to FB_AD[3] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to FB_AD[4] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to FB_AD[5] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to FB_AD[6] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to FB_AD[7] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to FB_AD[8] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to FB_AD[9] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to FB_ALE -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to FB_SIZE0 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to FB_SIZE1 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to fb_ad_in[0] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to fb_ad_in[10] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to fb_ad_in[11] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to fb_ad_in[12] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to fb_ad_in[13] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to fb_ad_in[14] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to fb_ad_in[15] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to fb_ad_in[16] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to fb_ad_in[17] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to fb_ad_in[18] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to fb_ad_in[19] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to fb_ad_in[1] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to fb_ad_in[20] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to fb_ad_in[21] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to fb_ad_in[22] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to fb_ad_in[23] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to fb_ad_in[24] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to fb_ad_in[25] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to fb_ad_in[26] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to fb_ad_in[27] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to fb_ad_in[28] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to fb_ad_in[29] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to fb_ad_in[2] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to fb_ad_in[30] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to fb_ad_in[31] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to fb_ad_in[3] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to fb_ad_in[4] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to fb_ad_in[5] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to fb_ad_in[6] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to fb_ad_in[7] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to fb_ad_in[8] -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to fb_ad_in[9] -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to nFB_BURST -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to nFB_CS1 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to nFB_CS2 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to nFB_CS3 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to nFB_OE -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to nFB_TA -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to nFB_WR -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to nFB_BURST -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to nFB_CS1 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to nFB_CS2 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to nFB_CS3 -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to nFB_OE -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to nFB_TA -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to nFB_WR -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=74" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=74" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=243" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=44632" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=49597" -section_id auto_signaltap_0 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 4c78b37..94e2515 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -8,24 +8,46 @@ library work; entity firebee1 is port - ( + ( + MAIN_CLK : in std_logic; + nRSTO_MCF : in std_logic; + CLK33MDIR : in std_logic; + + -- the ColdFire FlexBus signals FB_ALE : in std_logic; + FB_AD : inout std_logic_vector(31 downto 0); + nFB_OE : in std_logic; nFB_WR : in std_logic; + nFB_TA : out std_logic; nFB_CS1 : in std_logic; nFB_CS2 : in std_logic; nFB_CS3 : in std_logic; FB_SIZE0 : in std_logic; FB_SIZE1 : in std_logic; - nFB_BURST : in std_logic; - LP_BUSY : in std_logic; + nFB_BURST : in std_logic; + + LP_BUSY : in std_logic; + nACSI_DRQ : in std_logic; - nACSI_INT : in std_logic; + nACSI_INT : in std_logic; + + -- serial port pins RxD : in std_logic; CTS : in std_logic; RI : in std_logic; - DCD : in std_logic; + DCD : in std_logic; + TxD : out std_logic; + RTS : out std_logic; + DTR : out std_logic; + + -- parallel port + LP_D : inout std_logic_vector(7 downto 0); + LP_STR : out std_logic; + LPDIR : out std_logic; + AMKB_RX : in std_logic; PIC_AMKB_RX : in std_logic; + IDE_RDY : in std_logic; IDE_INT : in std_logic; WP_CF_CARD : in std_logic; @@ -38,56 +60,58 @@ entity firebee1 is sd_card_detect : in std_logic; nSCSI_DRQ : in std_logic; SD_WP : in std_logic; - nRD_DATA : in std_logic; + nRD_DATA : in std_logic; + nSCSI_C_D : in std_logic; nSCSI_I_O : in std_logic; nSCSI_MSG : in std_logic; - nDACK0 : in std_logic; + nDACK0 : in std_logic; + PIC_INT : in std_logic; - nFB_OE : in std_logic; TOUT0 : in std_logic; nMASTER : in std_logic; DVI_INT : in std_logic; - nDACK1 : in std_logic; + nDACK1 : in std_logic; + nPCI_INTD : in std_logic; nPCI_INTC : in std_logic; nPCI_INTB : in std_logic; - nPCI_INTA : in std_logic; - E0_INT : in std_logic; + nPCI_INTA : in std_logic; + + E0_INT : in std_logic; + nINDEX : in std_logic; HD_DD : in std_logic; - MAIN_CLK : in std_logic; - nRSTO_MCF : in std_logic; - CLK33MDIR : in std_logic; + SCSI_PAR : inout std_logic; nSCSI_RST : inout std_logic; nSCSI_SEL : inout std_logic; nSCSI_BUSY : inout std_logic; + SCSI_D : inout std_logic_vector(7 downto 0); + nSCSI_ACK : out std_logic; + nSCSI_ATN : out std_logic; + SCSI_DIR : out std_logic; + SD_CD_DATA3 : inout std_logic; SD_CMD_D1 : inout std_logic; MIDI_IN_PIN : inout std_logic; + ACSI_D : inout std_logic_vector(7 downto 0); - FB_AD : inout std_logic_vector(31 downto 0); + IO : inout std_logic_vector(17 downto 0); - LP_D : inout std_logic_vector(7 downto 0); - SCSI_D : inout std_logic_vector(7 downto 0); + SRD : inout std_logic_vector(15 downto 0); VD : inout std_logic_vector(31 downto 0); VDQS : inout std_logic_vector(3 downto 0); - LP_STR : out std_logic; + nACSI_ACK : out std_logic; nACSI_RESET : out std_logic; nACSI_CS : out std_logic; ACSI_DIR : out std_logic; ACSI_A1 : out std_logic; - nSCSI_ACK : out std_logic; - nSCSI_ATN : out std_logic; - SCSI_DIR : out std_logic; MIDI_TLR : out std_logic; - TxD : out std_logic; - RTS : out std_logic; - DTR : out std_logic; AMKB_TX : out std_logic; + IDE_RES : out std_logic; nIDE_CS0 : out std_logic; nIDE_CS1 : out std_logic; @@ -118,10 +142,10 @@ entity firebee1 is nSRBHE : out std_logic; nSRWE : out std_logic; nDREQ1 : out std_logic; + LED_FPGA_OK : out std_logic; nSROE : out std_logic; VCKE : out std_logic; - nFB_TA : out std_logic; nDDR_CLK : out std_logic; DDR_CLK : out std_logic; VSYNC_PAD : out std_logic; @@ -132,14 +156,13 @@ entity firebee1 is nMOT_ON : out std_logic; nSTEP_DIR : out std_logic; nSTEP : out std_logic; - LPDIR : out std_logic; MIDI_OLR : out std_logic; CLK25M : out std_logic; CLKUSB : out std_logic; CLK24M576 : out std_logic; BA : out std_logic_vector(1 downto 0); nIRQ : out std_logic_vector(7 downto 2); - VA : out std_logic_vector(12 downto 0); + VA : out std_logic_vector(12 downto 0); VB : out std_logic_vector(7 downto 0); VDM : out std_logic_vector(3 downto 0); VG : out std_logic_vector(7 downto 0); @@ -298,7 +321,7 @@ begin dsp_ta => dsp_ta ); - i_falconio_sdcard_ide_cf : work.falconio_sdcard_ide_cf + i_falconio_sdcard_ide_cf : entity work.falconio_sdcard_ide_cf port map ( clk33m => main_clk, @@ -407,7 +430,7 @@ begin ); - i_interrupt_handler : work.interrupt_handler + i_interrupt_handler : entity work.interrupt_handler port map ( MAIN_CLK => MAIN_CLK, @@ -439,7 +462,7 @@ begin nIRQ => nIRQ ); - i_mfp_acia_clk_pll : work.altpll1 + i_mfp_acia_clk_pll : entity work.altpll1 port map ( inclk0 => MAIN_CLK, @@ -537,7 +560,7 @@ begin ); - inst1 : work.lpm_ff0 + i_fb_adr_latch : entity work.lpm_ff0 port map ( clock => ddr_sync_66m, @@ -551,7 +574,7 @@ begin nSTEP <= not(step); nWR <= not(wr_data); - inst18 : work.lpm_counter0 + inst18 : entity work.lpm_counter0 port map ( clock => clk500k, @@ -562,8 +585,8 @@ begin nWR_GATE <= not(wr_gate); nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta); - fb_ad_in <= fb_ad; - fb_ad <= fb_ad_out when (video_ta or int_handler_ta or dsp_ta or falcon_io_ta) else (others => 'Z'); + fb_ad_in <= FB_AD; + FB_AD <= fb_ad_out when (video_ta or int_handler_ta or dsp_ta or falcon_io_ta) else (others => 'Z'); clk33m <= MAIN_CLK; @@ -579,11 +602,11 @@ begin o => midi_in ); - LED_FPGA_OK <= timebase(17); + led_fpga_ok <= timebase(17); nDDR_CLK <= not(ddrclk(0)); - inst5 : work.altddio_out3 + inst5 : entity work.altddio_out3 port map ( datain_h => vsync, @@ -593,7 +616,7 @@ begin ); - inst6 : work.altddio_out3 + inst6 : entity work.altddio_out3 port map ( datain_h => hsync, @@ -603,7 +626,7 @@ begin ); - inst8 : work.altddio_out3 + inst8 : entity work.altddio_out3 port map ( datain_h => blank_n, @@ -612,7 +635,7 @@ begin dataout => nBLANK_PAD ); - inst9 : work.altddio_out3 + inst9 : entity work.altddio_out3 port map ( datain_h => '0', From f0405d6aa771e1dec95a62e9a4157a387c65a6d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sat, 30 Jul 2016 07:30:45 +0000 Subject: [PATCH 122/127] reordered pins --- FPGA_Quartus_13.1/firebee1.qsf | 176 +-------------------------------- FPGA_Quartus_13.1/firebee1.vhd | 55 ++++++----- 2 files changed, 33 insertions(+), 198 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index e20802e..07c3af5 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -869,178 +869,4 @@ set_global_assignment -name VHDL_FILE flexbus_register.vhd set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp set_global_assignment -name SIGNALTAP_FILE stp1.stp -set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to MAIN_CLK -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to FB_AD[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to FB_AD[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to FB_AD[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to FB_AD[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to FB_AD[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to FB_AD[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to FB_AD[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to FB_AD[16] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to FB_AD[17] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to FB_AD[18] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to FB_AD[19] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to FB_AD[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to FB_AD[20] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to FB_AD[21] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to FB_AD[22] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to FB_AD[23] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to FB_AD[24] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to FB_AD[25] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to FB_AD[26] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to FB_AD[27] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to FB_AD[28] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to FB_AD[29] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to FB_AD[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to FB_AD[30] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to FB_AD[31] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to FB_AD[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to FB_AD[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to FB_AD[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to FB_AD[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to FB_AD[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to FB_AD[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to FB_AD[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to FB_ALE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to FB_SIZE0 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to FB_SIZE1 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to fb_ad_in[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to fb_ad_in[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to fb_ad_in[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to fb_ad_in[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to fb_ad_in[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to fb_ad_in[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to fb_ad_in[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to fb_ad_in[16] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to fb_ad_in[17] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to fb_ad_in[18] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to fb_ad_in[19] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to fb_ad_in[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to fb_ad_in[20] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to fb_ad_in[21] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to fb_ad_in[22] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to fb_ad_in[23] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to fb_ad_in[24] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to fb_ad_in[25] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to fb_ad_in[26] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to fb_ad_in[27] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to fb_ad_in[28] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to fb_ad_in[29] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to fb_ad_in[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to fb_ad_in[30] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to fb_ad_in[31] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to fb_ad_in[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to fb_ad_in[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to fb_ad_in[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to fb_ad_in[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to fb_ad_in[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to fb_ad_in[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to fb_ad_in[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to FB_AD[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to FB_AD[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to FB_AD[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to FB_AD[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to FB_AD[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to FB_AD[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to FB_AD[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to FB_AD[16] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to FB_AD[17] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to FB_AD[18] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to FB_AD[19] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to FB_AD[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to FB_AD[20] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to FB_AD[21] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to FB_AD[22] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to FB_AD[23] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to FB_AD[24] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to FB_AD[25] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to FB_AD[26] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to FB_AD[27] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to FB_AD[28] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to FB_AD[29] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to FB_AD[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to FB_AD[30] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to FB_AD[31] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to FB_AD[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to FB_AD[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to FB_AD[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to FB_AD[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to FB_AD[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to FB_AD[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to FB_AD[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to FB_ALE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to FB_SIZE0 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to FB_SIZE1 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to fb_ad_in[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to fb_ad_in[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to fb_ad_in[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to fb_ad_in[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to fb_ad_in[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to fb_ad_in[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to fb_ad_in[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to fb_ad_in[16] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to fb_ad_in[17] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to fb_ad_in[18] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to fb_ad_in[19] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to fb_ad_in[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to fb_ad_in[20] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to fb_ad_in[21] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to fb_ad_in[22] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to fb_ad_in[23] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to fb_ad_in[24] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to fb_ad_in[25] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to fb_ad_in[26] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to fb_ad_in[27] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to fb_ad_in[28] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to fb_ad_in[29] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to fb_ad_in[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to fb_ad_in[30] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to fb_ad_in[31] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to fb_ad_in[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to fb_ad_in[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to fb_ad_in[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to fb_ad_in[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to fb_ad_in[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to fb_ad_in[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to fb_ad_in[9] -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to nFB_BURST -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to nFB_CS1 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to nFB_CS2 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to nFB_CS3 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to nFB_OE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to nFB_TA -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to nFB_WR -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to nFB_BURST -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to nFB_CS1 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to nFB_CS2 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to nFB_CS3 -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to nFB_OE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to nFB_TA -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to nFB_WR -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=74" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=74" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=243" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=44632" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=49597" -section_id auto_signaltap_0 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 94e2515..061f058 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -26,11 +26,7 @@ entity firebee1 is FB_SIZE1 : in std_logic; nFB_BURST : in std_logic; - LP_BUSY : in std_logic; - nACSI_DRQ : in std_logic; - nACSI_INT : in std_logic; - -- serial port pins RxD : in std_logic; CTS : in std_logic; @@ -44,6 +40,7 @@ entity firebee1 is LP_D : inout std_logic_vector(7 downto 0); LP_STR : out std_logic; LPDIR : out std_logic; + LP_BUSY : in std_logic; AMKB_RX : in std_logic; PIC_AMKB_RX : in std_logic; @@ -96,7 +93,6 @@ entity firebee1 is SD_CMD_D1 : inout std_logic; MIDI_IN_PIN : inout std_logic; - ACSI_D : inout std_logic_vector(7 downto 0); IO : inout std_logic_vector(17 downto 0); @@ -104,11 +100,15 @@ entity firebee1 is VD : inout std_logic_vector(31 downto 0); VDQS : inout std_logic_vector(3 downto 0); + nACSI_DRQ : in std_logic; + nACSI_INT : in std_logic; nACSI_ACK : out std_logic; nACSI_RESET : out std_logic; nACSI_CS : out std_logic; ACSI_DIR : out std_logic; ACSI_A1 : out std_logic; + ACSI_D : inout std_logic_vector(7 downto 0); + MIDI_TLR : out std_logic; AMKB_TX : out std_logic; @@ -126,15 +126,13 @@ entity firebee1 is nSDSEL : out std_logic; nWR_GATE : out std_logic; nWR : out std_logic; - YM_QA : out std_logic; + + YM_QA : out std_logic; YM_QB : out std_logic; - YM_QC : out std_logic; + YM_QC : out std_logic; + SD_CLK : out std_logic; DSA_D : out std_logic; - nVWE : out std_logic; - nVCAS : out std_logic; - nVRAS : out std_logic; - nVCS : out std_logic; nPD_VGA : out std_logic; TIN0 : out std_logic; nSRCS : out std_logic; @@ -144,29 +142,40 @@ entity firebee1 is nDREQ1 : out std_logic; LED_FPGA_OK : out std_logic; + nSROE : out std_logic; - VCKE : out std_logic; - nDDR_CLK : out std_logic; - DDR_CLK : out std_logic; - VSYNC_PAD : out std_logic; - HSYNC_PAD : out std_logic; - nBLANK_PAD : out std_logic; - PIXEL_CLK_PAD : out std_logic; nSYNC : out std_logic; nMOT_ON : out std_logic; nSTEP_DIR : out std_logic; nSTEP : out std_logic; + MIDI_OLR : out std_logic; CLK25M : out std_logic; CLKUSB : out std_logic; CLK24M576 : out std_logic; - BA : out std_logic_vector(1 downto 0); + nIRQ : out std_logic_vector(7 downto 2); - VA : out std_logic_vector(12 downto 0); - VB : out std_logic_vector(7 downto 0); - VDM : out std_logic_vector(3 downto 0); - VG : out std_logic_vector(7 downto 0); + + -- DDR memory signals + BA : out std_logic_vector(1 downto 0); + VA : out std_logic_vector(12 downto 0); + VDM : out std_logic_vector(3 downto 0); + VCKE : out std_logic; + nDDR_CLK : out std_logic; + DDR_CLK : out std_logic; + nVWE : out std_logic; + nVCAS : out std_logic; + nVRAS : out std_logic; + nVCS : out std_logic; + + -- video signals VR : out std_logic_vector(7 downto 0) + VG : out std_logic_vector(7 downto 0); + VB : out std_logic_vector(7 downto 0); + VSYNC_PAD : out std_logic; + HSYNC_PAD : out std_logic; + nBLANK_PAD : out std_logic; + PIXEL_CLK_PAD : out std_logic; ); end firebee1; From 992ac9dc6315d9e58618d6011a115cf9d902b2cf Mon Sep 17 00:00:00 2001 From: Markus Date: Sat, 28 Apr 2018 08:17:13 +0200 Subject: [PATCH 123/127] Create README.md Beware. This code doesn't work (yet). --- FPGA_Quartus_13.1/README.md | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 FPGA_Quartus_13.1/README.md diff --git a/FPGA_Quartus_13.1/README.md b/FPGA_Quartus_13.1/README.md new file mode 100644 index 0000000..c3e368a --- /dev/null +++ b/FPGA_Quartus_13.1/README.md @@ -0,0 +1,2 @@ +# FPGA_Quartus_13.1 +FireBee's FPGA developed on Quartus 13.1 From 81f5aa6f2390fe4f43fabe30ec75b1db2b46b087 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 19 Aug 2018 18:18:13 +0200 Subject: [PATCH 124/127] fix wrong semicolon --- FPGA_Quartus_13.1/firebee1.qws | Bin 2872 -> 0 bytes FPGA_Quartus_13.1/firebee1.vhd | 4 ++-- 2 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebee1.qws diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws deleted file mode 100644 index 0457c8f1521e827d6d475587b61b80b0af576558..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2872 zcmeH}O-~b16o%iSXjp+OS1uZ32q77uA5!W{EMQ1TB!28n$k3T8p*XdzNJ5A!31Q`5 zaOrRGC%7T(T)A`SFAzVTb33gt8WV`9A>8KNd(NFR=bn4s_ulEv5p~-Y)fK3vwwCl< zv6@=NYA{z-gi{}~uZnJHTn~5>;n6~`F~(Rettp2+gH_cttVmCYWqwnvjoy=S z&1q4$HO-1oc_ScFo3Vv$>#y+U9J6)e#l)J|9iH4HTE+Q>So2u3j1@eO=RHP7j}@}3 zoxi@T8hdL}k7XpHYCm%6C!YmvYKr;m{K_iPNAmG1X%gL65j`MtAFmL}p-s}~@vHGG zX+j0w3>mk+(TFK;iOy+X%mmLSlW$RMNs|GSgT!EPh!2yEMQtmqTVT`XXINx)pD_lT zWy8YAq3%+q(=GvtZ7*~#RjvNY$-~iPM0cslBM>>kN*36HTyse^NbWbO;`dXk8Kx}2 zC@;pz9@mZ^X3TrP_s#{fHC*d^LF5lzi<%y_4eAh3i-?UOrS<`@=)g44bIcjQ0bq8Z zo#j_jlHOko_uW{kTH{NBAf20j}+s<;utf2ADbw@sR zkDn6H2b0V26Wg$swmaX!Kgsj|<~x7R&O?749QY~9{Zn>&uR3h(AL6=zooU+={tkAO B+5i9m diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 061f058..949d923 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -169,13 +169,13 @@ entity firebee1 is nVCS : out std_logic; -- video signals - VR : out std_logic_vector(7 downto 0) + VR : out std_logic_vector(7 downto 0); VG : out std_logic_vector(7 downto 0); VB : out std_logic_vector(7 downto 0); VSYNC_PAD : out std_logic; HSYNC_PAD : out std_logic; nBLANK_PAD : out std_logic; - PIXEL_CLK_PAD : out std_logic; + PIXEL_CLK_PAD : out std_logic ); end firebee1; From d774f3bd95bff57f9bf38f8315551ea4ebcbfc5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 19 Aug 2018 19:01:52 +0200 Subject: [PATCH 125/127] fix formatting --- FPGA_Quartus_13.1/DSP/DSP.vhd | 101 +++++++++++++--------------------- 1 file changed, 37 insertions(+), 64 deletions(-) diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 2873ce7..7f91a79 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -1,79 +1,52 @@ --- WARNING: Do NOT edit the input AND output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- AND other software AND tools, AND its AMPP partner logic --- functions, AND any output files from any of the foregoing --- (including device programming or simulation files), AND any --- associated documentation or information are expressly subject --- to the terms AND conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera AND sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:57 2009 - -LIBRARY ieee; - USE ieee.std_logic_1164.all; +library ieee; + use ieee.std_logic_1164.all; -- Entity Declaration -ENTITY dsp IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT +entity dsp is + port ( - CLK33M : IN std_logic; - MAIN_CLK : IN std_logic; - nFB_OE : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - nRSTO : IN std_logic; - nFB_CS3 : IN std_logic; - nSRCS : INOUT std_logic; - nSRBLE : OUT std_logic; - nSRBHE : OUT std_logic; - nSRWE : OUT std_logic; - nSROE : OUT std_logic; - DSP_INT : OUT std_logic; - DSP_TA : OUT std_logic; + CLK33M : in std_logic; + MAIN_CLK : in std_logic; + nFB_OE : in std_logic; + nFB_WR : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + nRSTO : in std_logic; + nFB_CS3 : in std_logic; + nSRCS : inout std_logic; + nSRBLE : out std_logic; + nSRBHE : out std_logic; + nSRWE : out std_logic; + nSROE : out std_logic; + DSP_INT : out std_logic; + DSP_TA : out std_logic; fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0); - IO : INOUT std_logic_vector(17 DOWNTO 0); - SRD : INOUT std_logic_vector(15 DOWNTO 0) + IO : inout std_logic_vector(17 downto 0); + SRD : inout std_logic_vector(15 downto 0) ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END dsp; +end dsp; -- Architecture Body -ARCHITECTURE rtl OF dsp IS - - -BEGIN - nSRCS <= '0' WHEN nFB_CS2 = '0' AND FB_ADR(27 DOWNTO 24) = x"4" ELSE '1'; --nFB_CS3; - nSRBHE <= '0' WHEN FB_ADR(0 DOWNTO 0) = "0" ELSE '1'; - nSRBLE <= '1' WHEN FB_ADR(0 DOWNTO 0) = "0" AND FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0'; - nSRWE <= '0' WHEN nFB_WR = '0' AND nSRCS = '0' AND MAIN_CLK = '0' ELSE '1'; - nSROE <= '0' WHEN nFB_OE = '0' AND nSRCS = '0' ELSE '1'; +architecture rtl of dsp is +begin + nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; + nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; + nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; + nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; + nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; DSP_INT <= '0'; DSP_TA <= '0'; - IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); - SRD(15 DOWNTO 0) <= fb_ad_in(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE (others => 'Z'); - -- fb_ad_out(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z'); + IO(17 downto 0) <= FB_ADR(18 downto 1); + SRD(15 downto 0) <= fb_ad_in(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else (others => 'Z'); + -- fb_ad_out(31 downto 16) <= srd(15 DOWNTO 0 )when nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z'); fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error -END rtl; +end rtl; From 4164ee3a7b488162a67bdbee396587a4bd4c4b5f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 19 Aug 2018 19:02:11 +0200 Subject: [PATCH 126/127] improve formatting --- FPGA_Quartus_13.1/firebee1.vhd | 824 ++++++++++++++++----------------- 1 file changed, 412 insertions(+), 412 deletions(-) diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 949d923..87f8a3d 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -9,173 +9,173 @@ library work; entity firebee1 is port ( - MAIN_CLK : in std_logic; - nRSTO_MCF : in std_logic; - CLK33MDIR : in std_logic; + MAIN_CLK : in std_logic; + nRSTO_MCF : in std_logic; + CLK33MDIR : in std_logic; -- the ColdFire FlexBus signals - FB_ALE : in std_logic; - FB_AD : inout std_logic_vector(31 downto 0); - nFB_OE : in std_logic; - nFB_WR : in std_logic; - nFB_TA : out std_logic; - nFB_CS1 : in std_logic; - nFB_CS2 : in std_logic; - nFB_CS3 : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - nFB_BURST : in std_logic; + FB_ALE : in std_logic; + FB_AD : inout std_logic_vector(31 downto 0); + nFB_OE : in std_logic; + nFB_WR : in std_logic; + nFB_TA : out std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; -- serial port pins - RxD : in std_logic; - CTS : in std_logic; - RI : in std_logic; - DCD : in std_logic; - TxD : out std_logic; - RTS : out std_logic; - DTR : out std_logic; + RxD : in std_logic; + CTS : in std_logic; + RI : in std_logic; + DCD : in std_logic; + TxD : out std_logic; + RTS : out std_logic; + DTR : out std_logic; -- parallel port - LP_D : inout std_logic_vector(7 downto 0); - LP_STR : out std_logic; - LPDIR : out std_logic; - LP_BUSY : in std_logic; + LP_D : inout std_logic_vector(7 downto 0); + LP_STR : out std_logic; + LPDIR : out std_logic; + LP_BUSY : in std_logic; - AMKB_RX : in std_logic; - PIC_AMKB_RX : in std_logic; + AMKB_RX : in std_logic; + PIC_AMKB_RX : in std_logic; - IDE_RDY : in std_logic; - IDE_INT : in std_logic; - WP_CF_CARD : in std_logic; - TRACK00 : in std_logic; - nWP : in std_logic; - nDCHG : in std_logic; - SD_DATA0 : in std_logic; - SD_DATA1 : in std_logic; - SD_DATA2 : in std_logic; - sd_card_detect : in std_logic; - nSCSI_DRQ : in std_logic; - SD_WP : in std_logic; - nRD_DATA : in std_logic; + IDE_RDY : in std_logic; + IDE_INT : in std_logic; + WP_CF_CARD : in std_logic; + TRACK00 : in std_logic; + nWP : in std_logic; + nDCHG : in std_logic; + SD_DATA0 : in std_logic; + SD_DATA1 : in std_logic; + SD_DATA2 : in std_logic; + sd_card_detect : in std_logic; + nSCSI_DRQ : in std_logic; + SD_WP : in std_logic; + nRD_DATA : in std_logic; - nSCSI_C_D : in std_logic; - nSCSI_I_O : in std_logic; - nSCSI_MSG : in std_logic; - nDACK0 : in std_logic; + nSCSI_C_D : in std_logic; + nSCSI_I_O : in std_logic; + nSCSI_MSG : in std_logic; + nDACK0 : in std_logic; - PIC_INT : in std_logic; - TOUT0 : in std_logic; - nMASTER : in std_logic; - DVI_INT : in std_logic; - nDACK1 : in std_logic; + PIC_INT : in std_logic; + TOUT0 : in std_logic; + nMASTER : in std_logic; + DVI_INT : in std_logic; + nDACK1 : in std_logic; - nPCI_INTD : in std_logic; - nPCI_INTC : in std_logic; - nPCI_INTB : in std_logic; - nPCI_INTA : in std_logic; + nPCI_INTD : in std_logic; + nPCI_INTC : in std_logic; + nPCI_INTB : in std_logic; + nPCI_INTA : in std_logic; - E0_INT : in std_logic; + E0_INT : in std_logic; - nINDEX : in std_logic; - HD_DD : in std_logic; + nINDEX : in std_logic; + HD_DD : in std_logic; - SCSI_PAR : inout std_logic; - nSCSI_RST : inout std_logic; - nSCSI_SEL : inout std_logic; - nSCSI_BUSY : inout std_logic; - SCSI_D : inout std_logic_vector(7 downto 0); - nSCSI_ACK : out std_logic; - nSCSI_ATN : out std_logic; - SCSI_DIR : out std_logic; + SCSI_PAR : inout std_logic; + nSCSI_RST : inout std_logic; + nSCSI_SEL : inout std_logic; + nSCSI_BUSY : inout std_logic; + SCSI_D : inout std_logic_vector(7 downto 0); + nSCSI_ACK : out std_logic; + nSCSI_ATN : out std_logic; + SCSI_DIR : out std_logic; - SD_CD_DATA3 : inout std_logic; - SD_CMD_D1 : inout std_logic; - MIDI_IN_PIN : inout std_logic; + SD_CD_DATA3 : inout std_logic; + SD_CMD_D1 : inout std_logic; + MIDI_IN_PIN : inout std_logic; - IO : inout std_logic_vector(17 downto 0); + IO : inout std_logic_vector(17 downto 0); - SRD : inout std_logic_vector(15 downto 0); - VD : inout std_logic_vector(31 downto 0); - VDQS : inout std_logic_vector(3 downto 0); + SRD : inout std_logic_vector(15 downto 0); + VD : inout std_logic_vector(31 downto 0); + VDQS : inout std_logic_vector(3 downto 0); - nACSI_DRQ : in std_logic; - nACSI_INT : in std_logic; - nACSI_ACK : out std_logic; - nACSI_RESET : out std_logic; - nACSI_CS : out std_logic; - ACSI_DIR : out std_logic; - ACSI_A1 : out std_logic; - ACSI_D : inout std_logic_vector(7 downto 0); + nACSI_DRQ : in std_logic; + nACSI_INT : in std_logic; + nACSI_ACK : out std_logic; + nACSI_RESET : out std_logic; + nACSI_CS : out std_logic; + ACSI_DIR : out std_logic; + ACSI_A1 : out std_logic; + ACSI_D : inout std_logic_vector(7 downto 0); - MIDI_TLR : out std_logic; - AMKB_TX : out std_logic; + MIDI_TLR : out std_logic; + AMKB_TX : out std_logic; - IDE_RES : out std_logic; - nIDE_CS0 : out std_logic; - nIDE_CS1 : out std_logic; - nIDE_WR : out std_logic; - nIDE_RD : out std_logic; - nCF_CS0 : out std_logic; - nCF_CS1 : out std_logic; - nROM3 : out std_logic; - nROM4 : out std_logic; - nRP_UDS : out std_logic; - nRP_LDS : out std_logic; - nSDSEL : out std_logic; - nWR_GATE : out std_logic; - nWR : out std_logic; + IDE_RES : out std_logic; + nIDE_CS0 : out std_logic; + nIDE_CS1 : out std_logic; + nIDE_WR : out std_logic; + nIDE_RD : out std_logic; + nCF_CS0 : out std_logic; + nCF_CS1 : out std_logic; + nROM3 : out std_logic; + nROM4 : out std_logic; + nRP_UDS : out std_logic; + nRP_LDS : out std_logic; + nSDSEL : out std_logic; + nWR_GATE : out std_logic; + nWR : out std_logic; - YM_QA : out std_logic; - YM_QB : out std_logic; - YM_QC : out std_logic; + YM_QA : out std_logic; + YM_QB : out std_logic; + YM_QC : out std_logic; - SD_CLK : out std_logic; - DSA_D : out std_logic; - nPD_VGA : out std_logic; - TIN0 : out std_logic; - nSRCS : out std_logic; - nSRBLE : out std_logic; - nSRBHE : out std_logic; - nSRWE : out std_logic; - nDREQ1 : out std_logic; + SD_CLK : out std_logic; + DSA_D : out std_logic; + nPD_VGA : out std_logic; + TIN0 : out std_logic; + nSRCS : out std_logic; + nSRBLE : out std_logic; + nSRBHE : out std_logic; + nSRWE : out std_logic; + nDREQ1 : out std_logic; - LED_FPGA_OK : out std_logic; + LED_FPGA_OK : out std_logic; - nSROE : out std_logic; - nSYNC : out std_logic; - nMOT_ON : out std_logic; - nSTEP_DIR : out std_logic; - nSTEP : out std_logic; + nSROE : out std_logic; + nSYNC : out std_logic; + nMOT_ON : out std_logic; + nSTEP_DIR : out std_logic; + nSTEP : out std_logic; - MIDI_OLR : out std_logic; - CLK25M : out std_logic; - CLKUSB : out std_logic; - CLK24M576 : out std_logic; + MIDI_OLR : out std_logic; + CLK25M : out std_logic; + CLKUSB : out std_logic; + CLK24M576 : out std_logic; - nIRQ : out std_logic_vector(7 downto 2); + nIRQ : out std_logic_vector(7 downto 2); -- DDR memory signals - BA : out std_logic_vector(1 downto 0); - VA : out std_logic_vector(12 downto 0); - VDM : out std_logic_vector(3 downto 0); - VCKE : out std_logic; - nDDR_CLK : out std_logic; - DDR_CLK : out std_logic; - nVWE : out std_logic; - nVCAS : out std_logic; - nVRAS : out std_logic; - nVCS : out std_logic; + BA : out std_logic_vector(1 downto 0); + VA : out std_logic_vector(12 downto 0); + VDM : out std_logic_vector(3 downto 0); + VCKE : out std_logic; + nDDR_CLK : out std_logic; + DDR_CLK : out std_logic; + nVWE : out std_logic; + nVCAS : out std_logic; + nVRAS : out std_logic; + nVCS : out std_logic; -- video signals - VR : out std_logic_vector(7 downto 0); - VG : out std_logic_vector(7 downto 0); - VB : out std_logic_vector(7 downto 0); - VSYNC_PAD : out std_logic; - HSYNC_PAD : out std_logic; - nBLANK_PAD : out std_logic; - PIXEL_CLK_PAD : out std_logic + VR : out std_logic_vector(7 downto 0); + VG : out std_logic_vector(7 downto 0); + VB : out std_logic_vector(7 downto 0); + VSYNC_PAD : out std_logic; + HSYNC_PAD : out std_logic; + nBLANK_PAD : out std_logic; + PIXEL_CLK_PAD : out std_logic ); end firebee1; @@ -239,23 +239,23 @@ architecture rtl of firebee1 is component altpll_reconfig1 port ( - clock : in std_logic ; + clock : in std_logic; counter_param : in std_logic_vector (2 downto 0); counter_type : in std_logic_vector (3 downto 0); data_in : in std_logic_vector (8 downto 0); - pll_areset_in : in std_logic := '0'; - pll_scandataout : in std_logic ; - pll_scandone : in std_logic ; - read_param : in std_logic ; - reconfig : in std_logic ; - reset : in std_logic ; - write_param : in std_logic ; - busy : out std_logic ; + pll_areset_in : in std_logic := '0'; + pll_scandataout : in std_logic; + pll_scandone : in std_logic; + read_param : in std_logic; + reconfig : in std_logic; + reset : in std_logic; + write_param : in std_logic; + busy : out std_logic; data_out : out std_logic_vector (8 downto 0); - pll_areset : out std_logic ; - pll_configupdate : out std_logic ; - pll_scanclk : out std_logic ; - pll_scanclkena : out std_logic ; + pll_areset : out std_logic; + pll_configupdate : out std_logic; + pll_scanclk : out std_logic; + pll_scanclkena : out std_logic; pll_scandata : out std_logic ); end component altpll_reconfig1; @@ -282,300 +282,300 @@ begin i_atari_clk_pll : work.altpll3 port map ( - inclk0 => MAIN_CLK, - c0 => clk25m_i, - c1 => clk2m, - c2 => clk500k, - c3 => clk2m4576, - locked => pll3_locked + inclk0 => MAIN_CLK, + c0 => clk25m_i, + c1 => clk2m, + c2 => clk500k, + c3 => clk2m4576, + locked => pll3_locked ); i_ddr_clk_pll : work.altpll2 port map ( - inclk0 => MAIN_CLK, - c0 => ddrclk(0), - c1 => ddrclk(1), - c2 => ddrclk(2), - c3 => ddrclk(3), - c4 => ddr_sync_66m + inclk0 => MAIN_CLK, + c0 => ddrclk(0), + c1 => ddrclk(1), + c2 => ddrclk(2), + c3 => ddrclk(3), + c4 => ddr_sync_66m ); i_dsp : work.dsp port map ( - clk33m => main_clk, - MAIN_CLK => MAIN_CLK, - nFB_OE => nFB_OE, - nFB_WR => nFB_WR, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - nrsto => rsto_n, - nFB_CS3 => nFB_CS3, - fb_ad_in => fb_ad_in, - fb_ad_out => fb_ad_out, - fb_adr => fb_adr, - IO => IO, - SRD => SRD, - nSRCS => srcs_n_i, - nSRBLE => nSRBLE, - nSRBHE => nSRBHE, - nSRWE => nSRWE, - nSROE => nSROE, - dsp_int => dsp_int, - dsp_ta => dsp_ta + clk33m => main_clk, + MAIN_CLK => MAIN_CLK, + nFB_OE => nFB_OE, + nFB_WR => nFB_WR, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + nrsto => rsto_n, + nFB_CS3 => nFB_CS3, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, + fb_adr => fb_adr, + IO => IO, + SRD => SRD, + nSRCS => srcs_n_i, + nSRBLE => nSRBLE, + nSRBHE => nSRBHE, + nSRWE => nSRWE, + nSROE => nSROE, + dsp_int => dsp_int, + dsp_ta => dsp_ta ); i_falconio_sdcard_ide_cf : entity work.falconio_sdcard_ide_cf port map ( - clk33m => main_clk, - MAIN_CLK => MAIN_CLK, - clk2m => clk2m, - clk500k => clk500k, - nFB_CS1 => nFB_CS1, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nFB_BURST => nFB_BURST, - LP_BUSY => LP_BUSY, - nACSI_DRQ => nACSI_DRQ, - nACSI_INT => nACSI_INT, - nSCSI_DRQ => nSCSI_DRQ, - nSCSI_MSG => nSCSI_MSG, - midi_in => midi_in, - RxD => RxD, - CTS => CTS, - RI => RI, - DCD => DCD, - AMKB_RX => AMKB_RX, - PIC_AMKB_RX => PIC_AMKB_RX, - IDE_RDY => IDE_RDY, - IDE_INT => IDE_INT, - WP_CS_CARD => '0', - nINDEX => nINDEX, - TRACK00 => TRACK00, - nRD_DATA => nRD_DATA, - nDCHG => nDCHG, - SD_DATA0 => SD_DATA0, - SD_DATA1 => SD_DATA1, - SD_DATA2 => SD_DATA2, - sd_card_dedect => sd_card_detect, - SD_WP => SD_WP, - nDACK0 => nDACK0, - nFB_WR => nFB_WR, - WP_CF_CARD => WP_CF_CARD, - nWP => nWP, - nFB_CS2 => nFB_CS2, - nrsto => rsto_n, - nSCSI_C_D => nSCSI_C_D, - nSCSI_I_O => nSCSI_I_O, - clk2m4576 => clk2m4576, - nFB_OE => nFB_OE, - vsync => vsync, - hsync => hsync, - dsp_int => dsp_int, - nblank => blank_n, - fdc_clk => fdc_clk, - FB_ALE => FB_ALE, - HD_DD => HD_DD, - SCSI_PAR => SCSI_PAR, - nSCSI_SEL => nSCSI_SEL, - nSCSI_BUSY => nSCSI_BUSY, - nSCSI_RST => nSCSI_RST, - SD_CD_DATA3 => SD_CD_DATA3, - sd_cdm_d1 => sd_cdm_d1, - acp_conf => acp_conf(31 downto 24), - ACSI_D => ACSI_D, - fb_ad_in => fb_ad_in, - fb_ad_out => fb_ad_out, - fb_adr => fb_adr, - LP_D => LP_D, - SCSI_D => SCSI_D, - nIDE_CS1 => nIDE_CS1, - nIDE_CS0 => nIDE_CS0, - LP_STR => LP_STR, - lp_dir => lp_dir, - nACSI_ACK => nACSI_ACK, - nACSI_RESET => nACSI_RESET, - nACSI_CS => nACSI_CS, - ACSI_DIR => ACSI_DIR, - ACSI_A1 => ACSI_A1, - nSCSI_ACK => nSCSI_ACK, - nSCSI_ATN => nSCSI_ATN, - SCSI_DIR => SCSI_DIR, - SD_CLK => SD_CLK, - YM_QA => YM_QA, - YM_QC => YM_QC, - YM_QB => YM_QB, - nSDSEL => nSDSEL, - step => step, - mot_on => mot_on, - nRP_LDS => nRP_LDS, - nRP_UDS => nRP_UDS, - nROM4 => nROM4, - nROM3 => nROM3, - nCF_CS1 => nCF_CS1, - nCF_CS0 => nCF_CS0, - nIDE_RD => ide_rd_n_i, - nIDE_WR => ide_wr_n_i, - AMKB_TX => AMKB_TX, - IDE_RES => IDE_RES, - DTR => DTR, - RTS => RTS, - TxD => TxD, - MIDI_OLR => MIDI_OLR, - DSA_D => DSA_D, - nmfp_int => mfp_int_n, - falcon_io_ta => falcon_io_ta, - step_dir => step_dir, - wr_data => wr_data, - wr_gate => wr_gate, - dma_drq => dma_drq, - MIDI_TLR => MIDI_TLR + clk33m => main_clk, + MAIN_CLK => MAIN_CLK, + clk2m => clk2m, + clk500k => clk500k, + nFB_CS1 => nFB_CS1, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nFB_BURST => nFB_BURST, + LP_BUSY => LP_BUSY, + nACSI_DRQ => nACSI_DRQ, + nACSI_INT => nACSI_INT, + nSCSI_DRQ => nSCSI_DRQ, + nSCSI_MSG => nSCSI_MSG, + midi_in => midi_in, + RxD => RxD, + CTS => CTS, + RI => RI, + DCD => DCD, + AMKB_RX => AMKB_RX, + PIC_AMKB_RX => PIC_AMKB_RX, + IDE_RDY => IDE_RDY, + IDE_INT => IDE_INT, + WP_CS_CARD => '0', + nINDEX => nINDEX, + TRACK00 => TRACK00, + nRD_DATA => nRD_DATA, + nDCHG => nDCHG, + SD_DATA0 => SD_DATA0, + SD_DATA1 => SD_DATA1, + SD_DATA2 => SD_DATA2, + sd_card_dedect => sd_card_detect, + SD_WP => SD_WP, + nDACK0 => nDACK0, + nFB_WR => nFB_WR, + WP_CF_CARD => WP_CF_CARD, + nWP => nWP, + nFB_CS2 => nFB_CS2, + nrsto => rsto_n, + nSCSI_C_D => nSCSI_C_D, + nSCSI_I_O => nSCSI_I_O, + clk2m4576 => clk2m4576, + nFB_OE => nFB_OE, + vsync => vsync, + hsync => hsync, + dsp_int => dsp_int, + nblank => blank_n, + fdc_clk => fdc_clk, + FB_ALE => FB_ALE, + HD_DD => HD_DD, + SCSI_PAR => SCSI_PAR, + nSCSI_SEL => nSCSI_SEL, + nSCSI_BUSY => nSCSI_BUSY, + nSCSI_RST => nSCSI_RST, + SD_CD_DATA3 => SD_CD_DATA3, + sd_cdm_d1 => sd_cdm_d1, + acp_conf => acp_conf(31 downto 24), + ACSI_D => ACSI_D, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, + fb_adr => fb_adr, + LP_D => LP_D, + SCSI_D => SCSI_D, + nIDE_CS1 => nIDE_CS1, + nIDE_CS0 => nIDE_CS0, + LP_STR => LP_STR, + lp_dir => lp_dir, + nACSI_ACK => nACSI_ACK, + nACSI_RESET => nACSI_RESET, + nACSI_CS => nACSI_CS, + ACSI_DIR => ACSI_DIR, + ACSI_A1 => ACSI_A1, + nSCSI_ACK => nSCSI_ACK, + nSCSI_ATN => nSCSI_ATN, + SCSI_DIR => SCSI_DIR, + SD_CLK => SD_CLK, + YM_QA => YM_QA, + YM_QC => YM_QC, + YM_QB => YM_QB, + nSDSEL => nSDSEL, + step => step, + mot_on => mot_on, + nRP_LDS => nRP_LDS, + nRP_UDS => nRP_UDS, + nROM4 => nROM4, + nROM3 => nROM3, + nCF_CS1 => nCF_CS1, + nCF_CS0 => nCF_CS0, + nIDE_RD => ide_rd_n_i, + nIDE_WR => ide_wr_n_i, + AMKB_TX => AMKB_TX, + IDE_RES => IDE_RES, + DTR => DTR, + RTS => RTS, + TxD => TxD, + MIDI_OLR => MIDI_OLR, + DSA_D => DSA_D, + nmfp_int => mfp_int_n, + falcon_io_ta => falcon_io_ta, + step_dir => step_dir, + wr_data => wr_data, + wr_gate => wr_gate, + dma_drq => dma_drq, + MIDI_TLR => MIDI_TLR ); i_interrupt_handler : entity work.interrupt_handler port map ( - MAIN_CLK => MAIN_CLK, - nFB_WR => nFB_WR, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - PIC_INT => PIC_INT, - E0_INT => E0_INT, - DVI_INT => DVI_INT, - nPCI_INTA => nPCI_INTA, - nPCI_INTB => nPCI_INTB, - nPCI_INTC => nPCI_INTC, - nPCI_INTD => nPCI_INTD, - nmfp_int => mfp_int_n, - nFB_OE => nFB_OE, - dsp_int => dsp_int, - vsync => vsync, - hsync => hsync, - dma_drq => dma_drq, - nrsto => rsto_n, - fb_ad_in => fb_ad_in, - fb_ad_out => fb_ad_out, - fb_adr => fb_adr, - int_handler_ta => int_handler_ta, - TIN0 => TIN0, - acp_conf => acp_conf, - nIRQ => nIRQ + MAIN_CLK => MAIN_CLK, + nFB_WR => nFB_WR, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + PIC_INT => PIC_INT, + E0_INT => E0_INT, + DVI_INT => DVI_INT, + nPCI_INTA => nPCI_INTA, + nPCI_INTB => nPCI_INTB, + nPCI_INTC => nPCI_INTC, + nPCI_INTD => nPCI_INTD, + nmfp_int => mfp_int_n, + nFB_OE => nFB_OE, + dsp_int => dsp_int, + vsync => vsync, + hsync => hsync, + dma_drq => dma_drq, + nrsto => rsto_n, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, + fb_adr => fb_adr, + int_handler_ta => int_handler_ta, + TIN0 => TIN0, + acp_conf => acp_conf, + nIRQ => nIRQ ); i_mfp_acia_clk_pll : entity work.altpll1 port map ( - inclk0 => MAIN_CLK, - c0 => clk48m, - c1 => fdc_clk, - c2 => CLK24M576, - locked => pll1_locked + inclk0 => MAIN_CLK, + c0 => clk48m, + c1 => fdc_clk, + c2 => CLK24M576, + locked => pll1_locked ); i_pll_reconfig : altpll_reconfig1 port map ( - reconfig => video_reconfig, - read_param => vr_rd, - write_param => vr_wr, - pll_areset_in => '0', + reconfig => video_reconfig, + read_param => vr_rd, + write_param => vr_wr, + pll_areset_in => '0', pll_scandataout => scandataout, - pll_scandone => scandone, - clock => MAIN_CLK, - reset => reset, - counter_param => fb_adr(8 downto 6), - counter_type => fb_adr(5 downto 2), - data_in => FB_AD(24 downto 16), - busy => vr_busy, - pll_scandata => scandata, - pll_scanclk => scanclk, - pll_scanclkena => scan_clkena, + pll_scandone => scandone, + clock => MAIN_CLK, + reset => reset, + counter_param => fb_adr(8 downto 6), + counter_type => fb_adr(5 downto 2), + data_in => FB_AD(24 downto 16), + busy => vr_busy, + pll_scandata => scandata, + pll_scanclk => scanclk, + pll_scanclkena => scan_clkena, pll_configupdate => config_update, - pll_areset => pll_reset, - data_out => vr_d + pll_areset => pll_reset, + data_out => vr_d ); i_video : entity work.video port map ( - MAIN_CLK => MAIN_CLK, - nFB_CS1 => nFB_CS1, - nFB_CS2 => nFB_CS2, - nFB_CS3 => nFB_CS3, - nFB_WR => nFB_WR, - FB_SIZE0 => FB_SIZE0, - FB_SIZE1 => FB_SIZE1, - nrsto => rsto_n, - nFB_OE => nFB_OE, - FB_ALE => FB_ALE, - ddr_sync_66m => ddr_sync_66m, + MAIN_CLK => MAIN_CLK, + nFB_CS1 => nFB_CS1, + nFB_CS2 => nFB_CS2, + nFB_CS3 => nFB_CS3, + nFB_WR => nFB_WR, + FB_SIZE0 => FB_SIZE0, + FB_SIZE1 => FB_SIZE1, + nrsto => rsto_n, + nFB_OE => nFB_OE, + FB_ALE => FB_ALE, + ddr_sync_66m => ddr_sync_66m, -- clk33m => clk33m, - clk33m => main_clk, - CLK25M => clk25m_i, - clk_video => clk_video, - vr_busy => vr_busy, - ddrclk => ddrclk, - fb_ad_in => fb_ad_in, - fb_ad_out => fb_ad_out, - fb_adr => fb_adr, - VD => VD, - VDQS => VDQS, - vr_d => vr_d, - vr_rd => vr_rd, - nblank => blank_n, - nVWE => nVWE, - nVCAS => nVCAS, - nVRAS => nVRAS, - nVCS => nVCS, - nPD_VGA => nPD_VGA, - VCKE => VCKE, - vsync => vsync, - hsync => hsync, - nSYNC => nSYNC, - VIDEO_TA => video_ta, - pixel_clk => pixel_clk, - video_reconfig => video_reconfig, - vr_wr => vr_wr, - BA => BA, - VA => VA, - VB => VB, - VDM => VDM, - VG => VG, - VR => VR + clk33m => main_clk, + CLK25M => clk25m_i, + clk_video => clk_video, + vr_busy => vr_busy, + ddrclk => ddrclk, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, + fb_adr => fb_adr, + VD => VD, + VDQS => VDQS, + vr_d => vr_d, + vr_rd => vr_rd, + nblank => blank_n, + nVWE => nVWE, + nVCAS => nVCAS, + nVRAS => nVRAS, + nVCS => nVCS, + nPD_VGA => nPD_VGA, + VCKE => VCKE, + vsync => vsync, + hsync => hsync, + nSYNC => nSYNC, + VIDEO_TA => video_ta, + pixel_clk => pixel_clk, + video_reconfig => video_reconfig, + vr_wr => vr_wr, + BA => BA, + VA => VA, + VB => VB, + VDM => VDM, + VG => VG, + VR => VR ); i_video_clk_pll : altpll4 port map ( - inclk0 => clk48m, - areset => pll_reset, - scanclk => scanclk, - scandata => scandata, - scanclkena => scan_clkena, - configupdate => config_update, - c0 => clk_video, - scandataout => scandataout, - scandone => scandone + inclk0 => clk48m, + areset => pll_reset, + scanclk => scanclk, + scandata => scandata, + scanclkena => scan_clkena, + configupdate => config_update, + c0 => clk_video, + scandataout => scandataout, + scandone => scandone ); i_fb_adr_latch : entity work.lpm_ff0 port map ( - clock => ddr_sync_66m, - enable => FB_ALE, - data => FB_AD, - q => fb_adr + clock => ddr_sync_66m, + enable => FB_ALE, + data => FB_AD, + q => fb_adr ); nMOT_ON <= not(mot_on); @@ -586,8 +586,8 @@ begin inst18 : entity work.lpm_counter0 port map ( - clock => clk500k, - q => timebase + clock => clk500k, + q => timebase ); @@ -605,10 +605,10 @@ begin inst29 : alt_iobuf port map ( - i => clk2m, - oe => clk2m, - io => MIDI_IN_PIN, - o => midi_in + i => clk2m, + oe => clk2m, + io => MIDI_IN_PIN, + o => midi_in ); led_fpga_ok <= timebase(17); @@ -618,39 +618,39 @@ begin inst5 : entity work.altddio_out3 port map ( - datain_h => vsync, - datain_l => vsync, - outclock => pixel_clk, - dataout => VSYNC_PAD + datain_h => vsync, + datain_l => vsync, + outclock => pixel_clk, + dataout => VSYNC_PAD ); inst6 : entity work.altddio_out3 port map ( - datain_h => hsync, - datain_l => hsync, - outclock => pixel_clk, - dataout => HSYNC_PAD + datain_h => hsync, + datain_l => hsync, + outclock => pixel_clk, + dataout => HSYNC_PAD ); inst8 : entity work.altddio_out3 port map ( - datain_h => blank_n, - datain_l => blank_n, - outclock => pixel_clk, - dataout => nBLANK_PAD + datain_h => blank_n, + datain_l => blank_n, + outclock => pixel_clk, + dataout => nBLANK_PAD ); inst9 : entity work.altddio_out3 port map ( - datain_h => '0', - datain_l => '1', - outclock => pixel_clk, - dataout => PIXEL_CLK_PAD + datain_h => '0', + datain_l => '1', + outclock => pixel_clk, + dataout => PIXEL_CLK_PAD ); SD_CMD_D1 <= sd_cdm_d1; From 384f7f42a6be173a1269406abfe83e01c012e0d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 19 Aug 2018 19:10:37 +0200 Subject: [PATCH 127/127] fix file format --- .../video/video_mod_mux_clutctr.vhd | 3308 ++++++++--------- 1 file changed, 1654 insertions(+), 1654 deletions(-) diff --git a/FPGA_Quartus_13.1/video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/video/video_mod_mux_clutctr.vhd index 83f4c56..636cb3d 100755 --- a/FPGA_Quartus_13.1/video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/video/video_mod_mux_clutctr.vhd @@ -1,1654 +1,1654 @@ --- Xilinx XPort Language Converter, Version 4.1 (110) --- --- AHDL Design Source: .tdf --- VHDL Design Output: .vhd --- Created 13-Jan-2016 10:03 AM --- --- Copyright (c) 2016, Xilinx, Inc. All Rights Reserved. --- Xilinx Inc makes no warranty, expressed or implied, with respect to --- the operation and/or functionality of the converted output files. --- - --- VIDEO MODUSE UND CLUT CONTROL - - --- Some names could not be written out to VHDL as they were --- in the source, and have been changed: --- --- AHDL VHDL --- ==== ==== --- VERZ0_.q VERZ0_q --- VERZ0_.prn VERZ0_prn --- VERZ0_.clrn VERZ0_clrn --- VERZ0_.clk VERZ0_clk --- VERZ0_.d VERZ0_d --- VERZ0_ VERZ0 --- verz1_.q verz1_q --- verz1_.prn verz1_prn --- verz1_.clrn verz1_clrn --- verz1_.clk verz1_clk --- verz1_.d verz1_d --- verz1_ verz1 --- verz2_.q verz2_q --- verz2_.prn verz2_prn --- verz2_.clrn verz2_clrn --- verz2_.clk verz2_clk --- verz2_.d verz2_d --- verz2_ verz2 --- clut_mux_av0_.q clut_mux_av0_q --- clut_mux_av0_.prn clut_mux_av0_prn --- clut_mux_av0_.clrn clut_mux_av0_clrn --- clut_mux_av0_.clk clut_mux_av0_clk --- clut_mux_av0_.d clut_mux_av0_d --- clut_mux_av0_ clut_mux_av0 --- clut_mux_av1_.q clut_mux_av1_q --- clut_mux_av1_.prn clut_mux_av1_prn --- clut_mux_av1_.clrn clut_mux_av1_clrn --- clut_mux_av1_.clk clut_mux_av1_clk --- clut_mux_av1_.d clut_mux_av1_d --- clut_mux_av1_ clut_mux_av1 - - --- CREATED BY FREDI ASCHWANDEN --- {{ALTERA_PARAMETERS_begin}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_end}} DO NOT REMOVE THIS LINE! - -library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; - -library work; - use work.firebee_utils_pkg.all; - -entity video_mod_mux_clutctr is - port - ( - nRSTO : in std_logic; - main_clk : in std_logic; - nFB_CS1 : in std_logic; - nFB_CS2 : in std_logic; - nFB_CS3 : in std_logic; - nFB_WR : in std_logic; - nFB_OE : in std_logic; - fb_size0 : in std_logic; - fb_size1 : in std_logic; - nFB_BURST : in std_logic; - fb_adr : in std_logic_vector(31 downto 0); - clk33m : in std_logic; - clk25m : in std_logic; - blitter_run : in std_logic; - clk_video : in std_logic; - vr_d : in std_logic_vector(8 downto 0); - vr_busy : in std_logic; - color8 : out std_logic; - acp_clut_rd : out std_logic; - color1 : out std_logic; - falcon_clut_rdh : out std_logic; - falcon_clut_rdl : out std_logic; - falcon_clut_wr : out std_logic_vector(3 downto 0); - st_clut_rd : out std_logic; - st_clut_wr : out std_logic_vector(1 downto 0); - clut_mux_adr : out std_logic_vector(3 downto 0); - hsync : out std_logic; - vsync : out std_logic; - nBLANK : out std_logic; - nSYNC : out std_logic; - nPD_VGA : out std_logic; - fifo_rde : out std_logic; - color2 : out std_logic; - color4 : out std_logic; - pixel_clk : out std_logic; - clut_off : out std_logic_vector(3 downto 0); - blitter_on : out std_logic; - video_ram_ctr : out std_logic_vector(15 downto 0); - video_mod_ta : out std_logic; - border_color : out std_logic_vector(23 downto 0); - ccsel : out std_logic_vector(2 downto 0); - acp_clut_wr : out std_logic_vector(3 downto 0); - inter_zei : out std_logic; - dop_fifo_clr : out std_logic; - video_reconfig : out std_logic; - vr_wr : out std_logic; - vr_rd : out std_logic; - clr_fifo : out std_logic; - fb_ad_in : in std_logic_vector(31 downto 0); - fb_ad_out : out std_logic_vector(31 downto 0) - ); -end video_mod_mux_clutctr; - - -architecture rtl of video_mod_mux_clutctr is - -- DIV. CONTROL REGISTER - -- BRAUCHT EIN WAITSTAT - -- LÄNGE hsync PULS IN pixel_clk - -- LETZTES PIXEL EINER ZEILE ERREICHT - -- ATARI RESOLUTION - -- HORIZONTAL TIMING 640x480 - -- VERTIKAL TIMING 640x480 - -- HORIZONTAL TIMING 320x240 - -- VERTIKAL TIMING 320x240 - -- HORIZONTAL - -- VERTIKAL - signal vr_dout : std_logic_vector(8 downto 0); - signal vr_dout_d : std_logic_vector(8 downto 0); - signal vr_dout_q : std_logic_vector(8 downto 0); - signal vr_frq : unsigned(7 downto 0); - signal vr_frq_d : std_logic_vector(7 downto 0); - signal vr_frq_q : std_logic_vector(7 downto 0); - signal fb_b : std_logic_vector(3 downto 0); - signal FB_16B : std_logic_vector(1 downto 0); - signal st_shift_mode : std_logic_vector(1 downto 0); - signal st_shift_mode_d : std_logic_vector(1 downto 0); - signal st_shift_mode_q : std_logic_vector(1 downto 0); - signal falcon_shift_mode : std_logic_vector(10 downto 0); - signal falcon_shift_mode_d : std_logic_vector(10 downto 0); - signal falcon_shift_mode_q : std_logic_vector(10 downto 0); - signal clut_mux_adr_d : std_logic_vector(3 downto 0); - signal clut_mux_adr_q : std_logic_vector(3 downto 0); - signal clut_mux_av1 : std_logic_vector(3 downto 0); - signal clut_mux_av1_d : std_logic_vector(3 downto 0); - signal clut_mux_av1_q : std_logic_vector(3 downto 0); - signal clut_mux_av0 : std_logic_vector(3 downto 0); - signal clut_mux_av0_d : std_logic_vector(3 downto 0); - signal clut_mux_av0_q : std_logic_vector(3 downto 0); - signal acp_vctr : std_logic_vector(31 downto 0); - signal acp_vctr_d : std_logic_vector(31 downto 0); - signal acp_vctr_q : std_logic_vector(31 downto 0); - signal border_color_d : std_logic_vector(23 downto 0); - signal border_color_q : std_logic_vector(23 downto 0); - signal sys_ctr : std_logic_vector(6 downto 0); - signal sys_ctr_d : std_logic_vector(6 downto 0); - signal sys_ctr_q : std_logic_vector(6 downto 0); - signal lof : std_logic_vector(15 downto 0); - signal lof_d : std_logic_vector(15 downto 0); - signal lof_q : std_logic_vector(15 downto 0); - signal lwd : std_logic_vector(15 downto 0); - signal lwd_d : std_logic_vector(15 downto 0); - signal lwd_q : std_logic_vector(15 downto 0); - signal hsync_I : std_logic_vector(7 downto 0); - signal hsync_I_d : std_logic_vector(7 downto 0); - signal hsync_I_q : std_logic_vector(7 downto 0); - signal HSY_LEN : std_logic_vector(7 downto 0); - signal HSY_LEN_d : std_logic_vector(7 downto 0); - signal HSY_LEN_q : std_logic_vector(7 downto 0); - signal vsync_I : std_logic_vector(2 downto 0); - signal vsync_I_d : std_logic_vector(2 downto 0); - signal vsync_I_q : std_logic_vector(2 downto 0); - signal VHCNT : std_logic_vector(11 downto 0); - signal VHCNT_d : std_logic_vector(11 downto 0); - signal VHCNT_q : std_logic_vector(11 downto 0); - signal SUB_PIXEL_CNT : std_logic_vector(6 downto 0); - signal SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); - signal SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); - signal VVCNT : std_logic_vector(10 downto 0); - signal VVCNT_d : std_logic_vector(10 downto 0); - signal VVCNT_q : std_logic_vector(10 downto 0); - signal VERZ2 : std_logic_vector(9 downto 0); - signal VERZ2_d : std_logic_vector(9 downto 0); - signal VERZ2_q : std_logic_vector(9 downto 0); - signal VERZ1 : std_logic_vector(9 downto 0); - signal VERZ1_d : std_logic_vector(9 downto 0); - signal VERZ1_q : std_logic_vector(9 downto 0); - signal VERZ0 : std_logic_vector(9 downto 0); - signal VERZ0_d : std_logic_vector(9 downto 0); - signal VERZ0_q : std_logic_vector(9 downto 0); - signal RAND : std_logic_vector(6 downto 0) := (others => '0'); - signal RAND_d : std_logic_vector(6 downto 0); - signal RAND_q : std_logic_vector(6 downto 0); - signal ccsel_d : std_logic_vector(2 downto 0); - signal ccsel_q : std_logic_vector(2 downto 0); - signal atari_hh : std_logic_vector(31 downto 0) := (others => '0'); - signal atari_hh_d : std_logic_vector(31 downto 0); - signal atari_hh_q : std_logic_vector(31 downto 0); - signal atari_vh : std_logic_vector(31 downto 0); - signal atari_vh_d : std_logic_vector(31 downto 0); - signal atari_vh_q : std_logic_vector(31 downto 0); - signal atari_hl : std_logic_vector(31 downto 0) := (others => '0'); - signal atari_hl_d : std_logic_vector(31 downto 0); - signal atari_hl_q : std_logic_vector(31 downto 0); - signal atari_vl : std_logic_vector(31 downto 0); - signal atari_vl_d : std_logic_vector(31 downto 0); - signal atari_vl_q : std_logic_vector(31 downto 0); - signal rand_links : std_logic_vector(11 downto 0); - signal hdis_start : std_logic_vector(11 downto 0); - signal hdis_end : std_logic_vector(11 downto 0); - signal rand_rechts : std_logic_vector(11 downto 0); - signal hs_start : std_logic_vector(11 downto 0); - signal h_total : std_logic_vector(11 downto 0); - signal hdis_len : std_logic_vector(11 downto 0); - signal MULF : std_logic_vector(5 downto 0); - signal HHT : std_logic_vector(11 downto 0) := (others => '0'); - signal HHT_d : std_logic_vector(11 downto 0); - signal HHT_q : std_logic_vector(11 downto 0); - signal HBE : std_logic_vector(11 downto 0) := (others => '0'); - signal HBE_d : std_logic_vector(11 downto 0); - signal HBE_q : std_logic_vector(11 downto 0); - signal HDB : std_logic_vector(11 downto 0); - signal HDB_d : std_logic_vector(11 downto 0); - signal HDB_q : std_logic_vector(11 downto 0); - signal HDE : std_logic_vector(11 downto 0); - signal hde_d : std_logic_vector(11 downto 0); - signal hde_q : std_logic_vector(11 downto 0); - signal HBB : std_logic_vector(11 downto 0); - signal HBB_d : std_logic_vector(11 downto 0); - signal HBB_q : std_logic_vector(11 downto 0); - signal HSS : std_logic_vector(11 downto 0) := (others => '0'); - signal HSS_d : std_logic_vector(11 downto 0); - signal HSS_q : std_logic_vector(11 downto 0); - signal rand_OBEN : std_logic_vector(10 downto 0); - signal VDIS_START : std_logic_vector(10 downto 0); - signal VDIS_end : std_logic_vector(10 downto 0); - signal border_bottom : std_logic_vector(10 downto 0); - signal VS_START : std_logic_vector(10 downto 0); - signal V_TOTAL : std_logic_vector(10 downto 0); - signal VBE : std_logic_vector(10 downto 0); - signal VBE_d : std_logic_vector(10 downto 0); - signal VBE_q : std_logic_vector(10 downto 0); - signal VDB : std_logic_vector(10 downto 0); - signal VDB_d : std_logic_vector(10 downto 0); - signal VDB_q : std_logic_vector(10 downto 0); - signal VDE : std_logic_vector(10 downto 0); - signal VDE_d : std_logic_vector(10 downto 0); - signal VDE_q : std_logic_vector(10 downto 0); - signal VBB : std_logic_vector(10 downto 0); - signal VBB_d : std_logic_vector(10 downto 0); - signal VBB_q : std_logic_vector(10 downto 0); - signal VSS : std_logic_vector(10 downto 0); - signal VSS_d : std_logic_vector(10 downto 0); - signal VSS_q : std_logic_vector(10 downto 0); - signal VFT : std_logic_vector(10 downto 0); - signal VFT_d : std_logic_vector(10 downto 0); - signal VFT_q : std_logic_vector(10 downto 0); - signal VCO : std_logic_vector(8 downto 0); - signal VCO_d : std_logic_vector(8 downto 0); - signal VCO_ena : std_logic_vector(8 downto 0); - signal VCO_q : std_logic_vector(8 downto 0); - signal VCNTRL : std_logic_vector(3 downto 0) := (others => '0'); - signal vcntrl_d : std_logic_vector(3 downto 0); - signal vcntrl_q : std_logic_vector(3 downto 0); - signal u0_data : std_logic_vector(15 downto 0); - signal u0_tridata : std_logic_vector(15 downto 0); - signal u1_data : std_logic_vector(15 downto 0); - signal u1_tridata : std_logic_vector(15 downto 0); - -- signal st_shift_mode0_clk_ctrl : std_logic; - signal st_shift_mode0_ena_ctrl : std_logic; - -- signal falcon_shift_mode0_clk_ctrl : std_logic; - signal falcon_shift_mode8_ena_ctrl : std_logic; - signal falcon_shift_mode0_ena_ctrl : std_logic; - - signal acp_vctr24_ena_ctrl : std_logic; - signal acp_vctr16_ena_ctrl : std_logic; - signal acp_vctr8_ena_ctrl : std_logic; - signal acp_vctr6_ena_ctrl : std_logic; - signal acp_vctr0_ena_ctrl : std_logic; - - signal atari_hh24_ena_ctrl : std_logic; - signal atari_hh16_ena_ctrl : std_logic; - signal atari_hh8_ena_ctrl : std_logic; - signal atari_hh0_ena_ctrl : std_logic; - signal atari_vh24_ena_ctrl : std_logic; - signal atari_vh16_ena_ctrl : std_logic; - signal atari_vh8_ena_ctrl : std_logic; - signal atari_vh0_ena_ctrl : std_logic; - signal atari_hl24_ena_ctrl : std_logic; - signal atari_hl16_ena_ctrl : std_logic; - signal atari_hl8_ena_ctrl : std_logic; - signal atari_hl0_ena_ctrl : std_logic; - signal atari_vl0_clk_ctrl : std_logic; - signal atari_vl24_ena_ctrl : std_logic; - signal atari_vl16_ena_ctrl : std_logic; - signal atari_vl8_ena_ctrl : std_logic; - signal atari_vl0_ena_ctrl : std_logic; - signal vr_dout0_ena_ctrl : std_logic; - signal vr_frq0_ena_ctrl : std_logic; - signal border_color16_ena_ctrl : std_logic; - signal border_color8_ena_ctrl : std_logic; - signal border_color0_ena_ctrl : std_logic; - signal sys_ctr0_ena_ctrl : std_logic; - signal lof8_ena_ctrl : std_logic; - signal lof0_ena_ctrl : std_logic; - signal lwd8_ena_ctrl : std_logic; - signal lwd0_ena_ctrl : std_logic; - signal HHT8_ena_ctrl : std_logic; - signal HHT0_ena_ctrl : std_logic; - signal HBE8_ena_ctrl : std_logic; - signal HBE0_ena_ctrl : std_logic; - signal HDB8_ena_ctrl : std_logic; - signal HDB0_ena_ctrl : std_logic; - signal HDE8_ena_ctrl : std_logic; - signal hde0_ena_ctrl : std_logic; - signal HBB8_ena_ctrl : std_logic; - signal HBB0_ena_ctrl : std_logic; - signal HSS0_clk_ctrl : std_logic; - signal HSS8_ena_ctrl : std_logic; - signal HSS0_ena_ctrl : std_logic; - signal VBE8_ena_ctrl : std_logic; - signal VBE0_ena_ctrl : std_logic; - signal VDB8_ena_ctrl : std_logic; - signal VDB0_ena_ctrl : std_logic; - signal VDE8_ena_ctrl : std_logic; - signal vde0_ena_ctrl : std_logic; - signal VBB8_ena_ctrl : std_logic; - signal VBB0_ena_ctrl : std_logic; - signal VSS8_ena_ctrl : std_logic; - signal VSS0_ena_ctrl : std_logic; - signal VFT8_ena_ctrl : std_logic; - signal VFT0_ena_ctrl : std_logic; - signal VCO0_ena_ctrl : std_logic; - signal VCNTRL0_ena_ctrl : std_logic; - signal VVCNT0_ena_ctrl : std_logic; - signal vsync_I0_ena_ctrl : std_logic; - signal SUB_PIXEL_CNT0_ena_ctrl : std_logic; - signal color8_2 : std_logic; - signal color8_1 : std_logic; - signal color1_3 : std_logic; - signal color1_2 : std_logic; - signal color1_1 : std_logic; - signal COLOR4_2 : std_logic; - signal COLOR4_1 : std_logic; - signal color16_2 : std_logic; - signal color16_1 : std_logic; - signal gnd : std_logic; - signal u1_enabledt : std_logic; - signal u0_enabledt : std_logic; - signal vcntrl_cs : std_logic; - signal VCO_CS : std_logic; - signal VFT_CS : std_logic; - signal VSS_CS : std_logic; - signal VBB_CS : std_logic; - signal VDE_CS : std_logic; - signal VDB_CS : std_logic; - signal VBE_CS : std_logic; - signal dop_fifo_clr_q : std_logic; - signal dop_fifo_clr_d : std_logic; - signal DOP_ZEI_q : std_logic; - signal DOP_ZEI_d : std_logic; - signal DOP_ZEI : std_logic; - signal inter_zei_q : std_logic; - signal inter_zei_d : std_logic; - signal st_video : std_logic; - signal falcon_video : std_logic; - signal HSS_CS : std_logic; - signal HBB_CS : std_logic; - signal hde_CS : std_logic; - signal HDB_CS : std_logic; - signal HBE_CS : std_logic; - signal HHT_CS : std_logic; - signal atari_vl_cs : std_logic; - signal atari_hl_CS : std_logic; - signal atari_vh_CS : std_logic; - signal atari_hh_CS : std_logic; - signal ATARI_SYNC : std_logic; - signal color24 : std_logic; - signal color16 : std_logic; - signal SYNC_PIX2_q : std_logic; - signal SYNC_PIX2_d : std_logic; - signal SYNC_PIX2 : std_logic; - signal SYNC_PIX1_q : std_logic; - signal SYNC_PIX1_d : std_logic; - signal SYNC_PIX1 : std_logic; - signal SYNC_PIX_q : std_logic; - signal SYNC_PIX_d : std_logic; - signal SYNC_PIX : std_logic; - signal START_ZEILE_q : std_logic; - signal START_ZEILE_ena : std_logic; - signal START_ZEILE_d : std_logic; - signal START_ZEILE : std_logic; - signal clr_fifo_q : std_logic; - signal clr_fifo_ena : std_logic; - signal clr_fifo_d : std_logic; - signal fifo_rde_q : std_logic; - signal fifo_rde_d : std_logic; - signal RAND_ON : std_logic; - signal VCO_OFF_q : std_logic; - signal VCO_OFF_d : std_logic; - signal VCO_OFF : std_logic; - signal vco_on_q : std_logic; - signal vco_on_d : std_logic; - signal vco_on : std_logic; - signal VCO_ZL_q : std_logic; - signal VCO_ZL_ena : std_logic; - signal VCO_ZL_d : std_logic; - signal VCO_ZL : std_logic; - signal VDTRON_q : std_logic; - signal VDTRON_d : std_logic; - signal VDTRON : std_logic; - signal DPO_OFF_q : std_logic; - signal DPO_OFF_d : std_logic; - signal DPO_OFF : std_logic; - signal dpo_on_q : std_logic; - signal dpo_on_d : std_logic; - signal DPO_ON : std_logic; - signal dpo_zl_q : std_logic; - signal dpo_zl_ena : std_logic; - signal dpo_zl_d : std_logic; - signal DPO_ZL : std_logic; - signal disp_on_q : std_logic; - signal disp_on_d : std_logic; - signal DISP_ON : std_logic; - signal nBLANK_q : std_logic; - signal nBLANK_d : std_logic; - signal vsync_START_q : std_logic; - signal vsync_START_ena : std_logic; - signal vsync_START_d : std_logic; - signal vsync_START : std_logic; - signal vsync_q : std_logic; - signal vsync_d : std_logic; - signal LAST_q : std_logic; - signal LAST_d : std_logic; - signal LAST : std_logic; - signal hsync_START_q : std_logic; - signal hsync_START_d : std_logic; - signal hsync_START : std_logic; - signal hsync_q : std_logic; - signal hsync_d : std_logic; - signal CLUT_TA_q : std_logic; - signal CLUT_TA_d : std_logic; - signal CLUT_TA : std_logic; - signal lwd_CS : std_logic; - signal lof_CS : std_logic; - signal sys_ctr_CS : std_logic; - signal acp_video_on : std_logic; - signal border_color_CS : std_logic; - signal acp_vctr_cs : std_logic; - signal falcon_shift_mode_CS : std_logic; - signal st_shift_mode_CS : std_logic; - signal ST_CLUT : std_logic; - signal st_clut_cs : std_logic; - signal falcon_clut : std_logic; - signal falcon_clut_cs : std_logic; - signal video_reconfig_q : std_logic; - signal video_reconfig_d : std_logic; - signal video_pll_reconfig_cs : std_logic; - signal vr_wr_q : std_logic; - signal vr_wr_d : std_logic; - signal video_pll_config_cs : std_logic; - signal acp_clut : std_logic; - signal acp_clut_cs : std_logic; - signal CLK13M_q : std_logic; - signal CLK13M_d : std_logic; - signal CLK13M : std_logic; - signal CLK17M_q : std_logic; - signal CLK17M_d : std_logic; - signal CLK17M : std_logic; - signal color4_i : std_logic; - signal pixel_clk_i : std_logic; - - -- Sub Module Interface Section - - function to_std_logic(X : in boolean) return std_logic is - variable ret : std_logic; - begin - if x then - ret := '1'; - else - ret := '0'; - end if; - return ret; - end function to_std_logic; - - - -- sizeIt replicates a value to an array of specific length. - function sizeit(a : std_Logic; len : integer) return std_logic_vector is - variable rep : std_logic_vector(len - 1 downto 0); - begin - for i in rep'range loop - rep(i) := a; - end loop; - return rep; - end function sizeit; - -begin - -- Register Section - - clut_mux_adr <= clut_mux_adr_q; - - -- missing signals that seem to got lost during conversion - hsync <= hsync_q; - acp_vctr <= acp_vctr_q; - rand <= rand_q; - atari_hh <= atari_hh_q; - atari_hl <= atari_hl_q; - HBE <= HBE_q; - HSS <= HSS_q; - VCO <= VCO_q; - VCNTRL <= vcntrl_q; - - vsync <= vsync_q; - nBLANK <= nBLANK_q; - fifo_rde <= fifo_rde_q; - border_color(23 downto 16) <= border_color_q(23 downto 16); - border_color(15 downto 8) <= border_color_q(15 downto 8); - border_color(7 downto 0) <= border_color_q(7 downto 0); - ccsel <= ccsel_q; - inter_zei <= inter_zei_q; - dop_fifo_clr <= dop_fifo_clr_q; - HHT <= HHT_q; - - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then - clut_mux_adr_q <= clut_mux_adr_d; - hsync_q <= hsync_d; - vsync_q <= vsync_d; - nBLANK_q <= nBLANK_d; - fifo_rde_q <= fifo_rde_d; - if border_color16_ena_ctrl = '1' then - border_color_q(23 downto 16) <= border_color_d(23 downto 16); - end if; - if border_color8_ena_ctrl = '1' then - border_color_q(15 downto 8) <= border_color_d(15 downto 8); - end if; - if border_color0_ena_ctrl = '1' then - border_color_q(7 downto 0) <= border_color_d(7 downto 0); - end if; - ccsel_q <= ccsel_d; - inter_zei_q <= inter_zei_d; - dop_fifo_clr_q <= dop_fifo_clr_d; - end if; - end process; - - video_reconfig <= video_reconfig_q; - - vr_wr <= vr_wr_q; - - clr_fifo <= clr_fifo_q; - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then - if clr_fifo_ena = '1' then - clr_fifo_q <= clr_fifo_d; - end if; - end if; - end process; - - process (clk25m) - begin - if rising_edge(clk25m) then - CLK13M_q <= CLK13M_d; - end if; - end process; - - vr_frq <= unsigned(vr_frq_q); - - process (main_clk) - begin - if rising_edge(main_clk) then - vr_wr_q <= vr_wr_d; - - video_reconfig_q <= video_reconfig_d; - - CLK17M_q <= CLK17M_d; - - if vr_dout0_ena_ctrl = '1' then - vr_dout_q <= vr_dout_d; - end if; - - if vr_frq0_ena_ctrl = '1' then - vr_frq_q <= vr_frq_d; - end if; - - if st_shift_mode0_ena_ctrl = '1' then - st_shift_mode_q <= st_shift_mode_d; - end if; - - if falcon_shift_mode8_ena_ctrl = '1' then - falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); - end if; - - if falcon_shift_mode0_ena_ctrl = '1' then - falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); - end if; - if acp_vctr24_ena_ctrl = '1' then - acp_vctr_q(31 downto 24) <= acp_vctr_d(31 downto 24); - end if; - - if acp_vctr16_ena_ctrl = '1' then - acp_vctr_q(23 downto 16) <= acp_vctr_d(23 downto 16); - end if; - - if acp_vctr8_ena_ctrl = '1' then - acp_vctr_q(15 downto 8) <= acp_vctr_d(15 downto 8); - end if; - - if acp_vctr6_ena_ctrl = '1' then - acp_vctr_q(7 downto 6) <= acp_vctr_d(7 downto 6); - end if; - - if acp_vctr0_ena_ctrl = '1' then - acp_vctr_q(5 downto 0) <= acp_vctr_d(5 downto 0); - end if; - - if sys_ctr0_ena_ctrl='1' then - sys_ctr_q <= sys_ctr_d; - end if; - - if lof8_ena_ctrl = '1' then - lof_q(15 downto 8) <= lof_d(15 downto 8); - end if; - - if lof0_ena_ctrl = '1' then - lof_q(7 downto 0) <= lof_d(7 downto 0); - end if; - - if lwd8_ena_ctrl = '1' then - lwd_q(15 downto 8) <= lwd_d(15 downto 8); - end if; - - if lwd0_ena_ctrl = '1' then - lwd_q(7 downto 0) <= lwd_d(7 downto 0); - end if; - - if HDB8_ena_ctrl = '1' then - HDB_q(11 downto 8) <= HDB_d(11 downto 8); - end if; - - if HDB0_ena_ctrl = '1' then - HDB_q(7 downto 0) <= HDB_d(7 downto 0); - end if; - - if HDE8_ena_ctrl = '1' then - hde_q(11 downto 8) <= hde_d(11 downto 8); - end if; - - if hde0_ena_ctrl = '1' then - hde_q(7 downto 0) <= hde_d(7 downto 0); - end if; - - if HBB8_ena_ctrl = '1' then - HBB_q(11 downto 8) <= HBB_d(11 downto 8); - end if; - - if HBB0_ena_ctrl = '1' then - HBB_q(7 downto 0) <= HBB_d(7 downto 0); - end if; - - if HSS8_ena_ctrl = '1' then - HSS_q(11 downto 8) <= HSS_d(11 downto 8); - end if; - - if HSS0_ena_ctrl='1' then - HSS_q(7 downto 0) <= HSS_d(7 downto 0); - end if; - - dop_zei_q <= dop_zei_d; - - if VBE8_ena_ctrl = '1' then - VBE_q(10 downto 8) <= VBE_d(10 downto 8); - end if; - - if VBE0_ena_ctrl = '1' then - VBE_q(7 downto 0) <= VBE_d(7 downto 0); - end if; - - if VDB8_ena_ctrl = '1' then - VDB_q(10 downto 8) <= VDB_d(10 downto 8); - end if; - - if VDB0_ena_ctrl = '1' then - VDB_q(7 downto 0) <= VDB_d(7 downto 0); - end if; - - if VDE8_ena_ctrl = '1' then - VDE_q(10 downto 8) <= VDE_d(10 downto 8); - end if; - - if vde0_ena_ctrl = '1' then - VDE_q(7 downto 0) <= VDE_d(7 downto 0); - end if; - - if VBB8_ena_ctrl = '1' then - VBB_q(10 downto 8) <= VBB_d(10 downto 8); - end if; - - if VBB0_ena_ctrl = '1' then - VBB_q(7 downto 0) <= VBB_d(7 downto 0); - end if; - - if VSS8_ena_ctrl = '1' then - VSS_q(10 downto 8) <= VSS_d(10 downto 8); - end if; - - if VSS0_ena_ctrl = '1' then - VSS_q(7 downto 0) <= VSS_d(7 downto 0); - end if; - - if VFT8_ena_ctrl = '1' then - VFT_q(10 downto 8) <= VFT_d(10 downto 8); - end if; - - if VFT0_ena_ctrl = '1' then - VFT_q(7 downto 0) <= VFT_d(7 downto 0); - end if; - - if VCO_ena(8) = '1' then - VCO_q(8) <= VCO_d(8); - end if; - - if VCO0_ena_ctrl = '1' then - VCO_q(7 downto 0) <= VCO_d(7 downto 0); - end if; - - if vcntrl0_ena_ctrl = '1' then - vcntrl_q <= vcntrl_d; - end if; - end if; - end process; - - process (pixel_clk_i) - begin - if rising_edge(pixel_clk_i) then - clut_mux_av1_q <= clut_mux_av1_d; - clut_mux_av0_q <= clut_mux_av0_d; - CLUT_TA_q <= CLUT_TA_d; - hsync_I_q <= hsync_I_d; - HSY_LEN_q <= HSY_LEN_d; - hsync_START_q <= hsync_START_d; - LAST_q <= LAST_d; - - if vsync_START_ena = '1' then - vsync_START_q <= vsync_START_d; - end if; - - if vsync_I0_ena_ctrl='1' then - vsync_I_q <= vsync_I_d; - end if; - - disp_on_q <= disp_on_d; - - if dpo_zl_ena = '1' then - dpo_zl_q <= dpo_zl_d; - end if; - - dpo_on_q <= dpo_on_d; - DPO_OFF_q <= DPO_OFF_d; - VDTRON_q <= VDTRON_d; - - if VCO_ZL_ena = '1' then - VCO_ZL_q <= VCO_ZL_d; - end if; - - vco_on_q <= vco_on_d; - VCO_OFF_q <= VCO_OFF_d; - vhcnt_q <= vhcnt_d; - - if sub_pixel_cnt0_ena_ctrl = '1' then - sub_pixel_cnt_q <= sub_pixel_cnt_d; - end if; - - if vvcnt0_ena_ctrl='1' then - vvcnt_q <= vvcnt_d; - end if; - - verz2_q <= verz2_d; - verz1_q <= verz1_d; - VERZ0_q <= VERZ0_d; - rand_q <= rand_d; - - if START_ZEILE_ena = '1' then - START_ZEILE_q <= START_ZEILE_d; - end if; - - SYNC_PIX_q <= SYNC_PIX_d; - SYNC_PIX1_q <= SYNC_PIX1_d; - SYNC_PIX2_q <= SYNC_PIX2_d; - - if atari_hh24_ena_ctrl = '1' then - atari_hh_q(31 downto 24) <= atari_hh_d(31 downto 24); - end if; - - if atari_hh16_ena_ctrl = '1' then - atari_hh_q(23 downto 16) <= atari_hh_d(23 downto 16); - end if; - - if atari_hh8_ena_ctrl = '1' then - atari_hh_q(15 downto 8) <= atari_hh_d(15 downto 8); - end if; - - if atari_hh0_ena_ctrl = '1' then - atari_hh_q(7 downto 0) <= atari_hh_d(7 downto 0); - end if; - - if atari_vh24_ena_ctrl = '1' then - atari_vh_q(31 downto 24) <= atari_vh_d(31 downto 24); - end if; - - if atari_vh16_ena_ctrl = '1' then - atari_vh_q(23 downto 16) <= atari_vh_d(23 downto 16); - end if; - - if atari_vh8_ena_ctrl = '1' then - atari_vh_q(15 downto 8) <= atari_vh_d(15 downto 8); - end if; - - if atari_vh0_ena_ctrl='1' then - atari_vh_q(7 downto 0) <= atari_vh_d(7 downto 0); - end if; - - if atari_hl24_ena_ctrl = '1' then - atari_hl_q(31 downto 24) <= atari_hl_d(31 downto 24); - end if; - - if atari_hl16_ena_ctrl = '1' then - atari_hl_q(23 downto 16) <= atari_hl_d(23 downto 16); - end if; - - if atari_hl8_ena_ctrl = '1' then - atari_hl_q(15 downto 8) <= atari_hl_d(15 downto 8); - end if; - - if atari_hl0_ena_ctrl = '1' then - atari_hl_q(7 downto 0) <= atari_hl_d(7 downto 0); - end if; - - if atari_vl24_ena_ctrl = '1' then - atari_vl_q(31 downto 24) <= atari_vl_d(31 downto 24); - end if; - - if atari_vl16_ena_ctrl = '1' then - atari_vl_q(23 downto 16) <= atari_vl_d(23 downto 16); - end if; - - if atari_vl8_ena_ctrl = '1' then - atari_vl_q(15 downto 8) <= atari_vl_d(15 downto 8); - end if; - - if atari_vl0_ena_ctrl = '1' then - atari_vl_q(7 downto 0) <= atari_vl_d(7 downto 0); - end if; - - if HHT8_ena_ctrl = '1' then - HHT_q(11 downto 8) <= HHT_d(11 downto 8); - end if; - - if HHT0_ena_ctrl = '1' then - HHT_q(7 downto 0) <= HHT_d(7 downto 0); - end if; - - if HBE8_ena_ctrl = '1' then - HBE_q(11 downto 8) <= HBE_d(11 downto 8); - end if; - - if HBE0_ena_ctrl = '1' then - HBE_q(7 downto 0) <= HBE_d(7 downto 0); - end if; - end if; - end process; - - --- Start of original equations - - -- BYT SELECT 32 BIT - -- ADR==0 - -- fb_b(0) <= to_std_logic(fb_adr(1 downto 0) = "00"); - fb_b(0) <= '1' when fb_adr(1 downto 0) = "00" else '0'; - - -- ADR==1 - -- HIGH WORD - -- LONG UND LINE - fb_b(1) <= to_std_logic(fb_adr(1 downto 0) = "01") or - (fb_size1 and (not fb_size0) and (not fb_adr(1))) or (fb_size1 and fb_size0) or - ((not fb_size1) and (not fb_size0)); - - -- ADR==2 - -- LONG UND LINE - fb_b(2) <= to_std_logic(fb_adr(1 downto 0) = "10") or - (fb_size1 and fb_size0) or - ((not fb_size1) and (not fb_size0)); - - -- ADR==3 - -- LOW WORD - -- LONG UND LINE - fb_b(3) <= to_std_logic(fb_adr(1 downto 0) = "11") or - (fb_size1 and (not fb_size0) and fb_adr(1)) or - (fb_size1 and fb_size0) or - ((not fb_size1) and (not fb_size0)); - - -- BYT SELECT 16 BIT - -- ADR==0 - FB_16B(0) <= to_std_logic(fb_adr(0) = '0'); - - -- ADR==1 - -- NOT BYT - FB_16B(1) <= to_std_logic(fb_adr(0) = '1') or (not ((not fb_size1) and fb_size0)); - - -- ACP CLUT -- - -- 0-3FF/1024 - acp_clut_cs <= to_std_logic(((not nFB_CS2) = '1') and fb_adr(27 downto 10) = "000000000000000000"); - acp_clut_rd <= acp_clut_cs and (not nFB_OE); - acp_clut_wr <= fb_b and sizeIt(acp_clut_cs, 4) and sizeIt(not nFB_WR, 4); - CLUT_TA_d <= (acp_clut_cs or falcon_clut_cs or st_clut_cs) and (not video_mod_ta); - - -- FALCON CLUT -- - -- $F9800/$400 - falcon_clut_cs <= to_std_logic(((not nFB_CS1) = '1') and fb_adr(19 downto 10) = "1111100110"); - - -- HIGH WORD - falcon_clut_rdh <= falcon_clut_cs and (not nFB_OE) and (not fb_adr(1)); - - -- LOW WORD - falcon_clut_rdl <= falcon_clut_cs and (not nFB_OE) and fb_adr(1); - falcon_clut_wr(1 downto 0) <= FB_16B and std_logic_vector'((not fb_adr(1)) & - (not fb_adr(1))) and std_logic_vector'(falcon_clut_cs & falcon_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - falcon_clut_wr(3 downto 2) <= FB_16B and std_logic_vector'(fb_adr(1) & fb_adr(1)) and std_logic_vector'(falcon_clut_cs & falcon_clut_cs) and - std_logic_vector'((not nFB_WR) & (not nFB_WR)); - - -- ST CLUT -- - -- $F8240/$20 - st_clut_cs <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 5) = "111110000010010"); - st_clut_rd <= st_clut_cs and (not nFB_OE); - st_clut_wr <= FB_16B and std_logic_vector'(st_clut_cs & st_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); - - -- ST shift mode - - -- $F8260/2 - st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adr(19 downto 1) = 19x"7c130" else '0'; - -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100110000"); - st_shift_mode_d <= fb_ad_in(25 downto 24) when st_shift_mode_cs; - st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and fb_b(0); - - -- MONO - color1_1 <= to_std_logic(st_shift_mode_q = "10") and (not color8) and st_video and (not acp_video_on); - - -- 4 FARBEN - color2 <= to_std_logic(st_shift_mode_q = "01") and (not color8) and st_video and (not acp_video_on); - - -- 16 FARBEN - COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not color8) and st_video and (not acp_video_on); - - -- FALCON shift mode - - -- $F8266/2 - falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100110011"); - falcon_shift_mode_d <= fb_ad_in(26 downto 16) when falcon_shift_mode_cs; - falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and fb_b(2); - falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and fb_b(3); - - clut_off <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); - color1_2 <= falcon_shift_mode_q(10) and (not color16) and (not color8) and falcon_video and (not acp_video_on); - color8_1 <= falcon_shift_mode_q(4) and (not color16) and falcon_video and (not acp_video_on); - color16_1 <= falcon_shift_mode_q(8) and falcon_video and (not acp_video_on); - COLOR4_2 <= (not color1) and (not color16) and (not color8) and falcon_video and (not acp_video_on); - - -- ACP VIDEO CONTROL - -- BIT 0 = ACP VIDEO ON - -- BIT 1 = POWER ON VIDEO DAC - -- BIT 2 = ACP 24BIT - -- BIT 3 = ACP 16BIT - -- BIT 4 = ACP 8BIT - -- BIT 5 = ACP 1BIT - -- BIT 6 = FALCON SHifT MODE - -- BIT 7 = ST SHifT MODE - -- BIT 9..8 = VCLK FREQUENZ - -- BIT 15 =-SYNC ALLOWED - -- BIT 31..16 = video_ram_ctr - -- BIT 25 = RANDFARBE EINSCHALTEN - -- BIT 26 = STANDARD ATARI SYNCS - - -- $400/4 - acp_vctr_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000000"); - - acp_vctr_d(31 downto 8) <= fb_ad_in(31 downto 8) when acp_vctr_cs; - acp_vctr_d(5 downto 0) <= fb_ad_in(5 downto 0) when acp_vctr_cs; - - acp_vctr24_ena_ctrl <= acp_vctr_cs and fb_b(0) and (not nFB_WR); - acp_vctr16_ena_ctrl <= acp_vctr_cs and fb_b(1) and (not nFB_WR); - acp_vctr8_ena_ctrl <= acp_vctr_cs and fb_b(2) and (not nFB_WR); - acp_vctr0_ena_ctrl <= acp_vctr_cs and fb_b(3) and (not nFB_WR); - acp_video_on <= acp_vctr_q(0); - nPD_VGA <= acp_vctr_q(1); - - -- ATARI MODUS - -- WENN 1 AUTOMATISCHE AUFLÖSUNG - ATARI_SYNC <= acp_vctr_q(26); - - -- HORIZONTAL TIMING 640x480 - - -- $410/4 - atari_hh_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000100"); - atari_hh_d <= fb_ad_in when atari_hh_cs; - atari_hh24_ena_ctrl <= atari_hh_cs and fb_b(0) and (not nFB_WR); - atari_hh16_ena_ctrl <= atari_hh_cs and fb_b(1) and (not nFB_WR); - atari_hh8_ena_ctrl <= atari_hh_cs and fb_b(2) and (not nFB_WR); - atari_hh0_ena_ctrl <= atari_hh_cs and fb_b(3) and (not nFB_WR); - - -- VERTIKAL TIMING 640x480 - - -- $414/4 - atari_vh_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000101"); - atari_vh_d <= fb_ad_in when atari_vh_cs; - atari_vh24_ena_ctrl <= atari_vh_cs and fb_b(0) and (not nFB_WR); - atari_vh16_ena_ctrl <= atari_vh_cs and fb_b(1) and (not nFB_WR); - atari_vh8_ena_ctrl <= atari_vh_cs and fb_b(2) and (not nFB_WR); - atari_vh0_ena_ctrl <= atari_vh_cs and fb_b(3) and (not nFB_WR); - - -- HORIZONTAL TIMING 320x240 - - -- $418/4 - atari_hl_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000110"); - atari_hl_d <= fb_ad_in when atari_hl_cs; - atari_hl24_ena_ctrl <= atari_hl_cs and fb_b(0) and (not nFB_WR); - atari_hl16_ena_ctrl <= atari_hl_cs and fb_b(1) and (not nFB_WR); - atari_hl8_ena_ctrl <= atari_hl_cs and fb_b(2) and (not nFB_WR); - atari_hl0_ena_ctrl <= atari_hl_cs and fb_b(3) and (not nFB_WR); - - -- VERTIKAL TIMING 320x240 - - -- $41C/4 - atari_vl_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000111"); - atari_vl_d <= fb_ad_in when atari_vl_cs; - atari_vl24_ena_ctrl <= atari_vl_cs and fb_b(0) and (not nFB_WR); - atari_vl16_ena_ctrl <= atari_vl_cs and fb_b(1) and (not nFB_WR); - atari_vl8_ena_ctrl <= atari_vl_cs and fb_b(2) and (not nFB_WR); - atari_vl0_ena_ctrl <= atari_vl_cs and fb_b(3) and (not nFB_WR); - - -- VIDEO PLL CONFIG - -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - video_pll_config_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 9) = "0000000000000000011") and fb_b(0) and fb_b(1); - vr_wr_d <= video_pll_config_cs and (not nFB_WR) and (not vr_busy) and (not vr_wr_q); - vr_rd <= video_pll_config_cs and nFB_WR and (not vr_busy); - vr_dout0_ena_ctrl <= not vr_busy; - vr_dout_d <= vr_d; - vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adr(8 downto 0) = "000000100"); - vr_frq_d <= fb_ad_in(23 downto 16) when video_pll_config_cs; - - -- VIDEO PLL RECONFIG - -- $(F)000'0800 - video_pll_reconfig_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 0) = "0000000000000000100000000000") and fb_b(0); - video_reconfig_d <= video_pll_reconfig_cs and (not nFB_WR) and (not vr_busy) and (not video_reconfig_q); - - -- ---------------------------------------------------------------------------------------------------------------------- - video_ram_ctr <= acp_vctr_q(31 downto 16); - - -- ------------ COLOR MODE IM ACP SETZEN - color1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and acp_video_on; - color8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and acp_video_on; - color16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and acp_video_on; - color24 <= acp_vctr_q(2) and acp_video_on; - acp_clut <= (acp_video_on and (color1 or color8)) or (st_video and color1); - - -- ST ODER FALCON SHifT MODE SETZEN WENN WRITE X..SHifT REGISTER - acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not acp_video_on); - acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not acp_video_on); - - acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_cs and fb_b(3) and (not nFB_WR) and fb_ad_in(0)); - falcon_video <= acp_vctr_q(7); - falcon_clut <= falcon_video and (not acp_video_on) and (not color16); - st_video <= acp_vctr_q(6); - ST_CLUT <= st_video and (not acp_video_on) and (not falcon_clut) and (not color1); - pixel_clk_i <= pixel_clk; - - -- ONLY FOR INFORMATION - ccsel_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and - sizeIt(falcon_clut,3)) or ("100" and sizeIt(acp_clut,3)) or ("101" and - sizeIt(color16,3)) or ("110" and sizeIt(color24,3)) or ("111" and - sizeIt(RAND_ON,3)); - - -- DIVERSE (VIDEO)-REGISTER ---------------------------- - -- randFARBE - - -- $404/4 - border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adr(27 downto 2) = "00000000000000000100000001"); - border_color_d <= fb_ad_in(23 downto 0) when border_color_cs; - border_color16_ena_ctrl <= border_color_CS and fb_b(1) and (not nFB_WR); - border_color8_ena_ctrl <= border_color_CS and fb_b(2) and (not nFB_WR); - border_color0_ena_ctrl <= border_color_CS and fb_b(3) and (not nFB_WR); - - -- System Config Register - -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi - -- |||||||| - -- |||||||+- RAM Wait Status - -- ||||||| 0 = 1 Wait (default) - -- ||||||| 1 = 0 Wait - -- ||||||+-- Video Bus Width - -- |||||| 0 = 16 Bit - -- |||||| 1 = 32 Bit (default) - -- ||||++--- ROM Wait Status - -- |||| 00 = reserved - -- |||| 01 = 2 Wait (default) - -- |||| 10 = 1 Wait - -- |||| 11 = 0 Wait - -- ||++----- Main Memory Size - -- || 01 = 4 MB - -- || 10 = 16 MB - -- ++------- Monitor Type - -- 00 Monochrome - -- 01 RGB - -- 10 VGA - -- 11 TV - -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr, 20x"f8006") = '1' else '0'; - -- fb_adr(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; - - -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adr(19 downto 1) = "1111100000000000011"); - sys_ctr_d <= fb_ad_in(22 downto 16) when sys_ctr_cs; - sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and fb_b(3); - blitter_on <= not sys_ctr_q(3); - - -- lof - -- $820E/2 - lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000111"); - lof_d <= fb_ad_in(31 downto 16) when lof_cs; - lof8_ena_ctrl <= lof_CS and (not nFB_WR) and fb_b(2); - lof0_ena_ctrl <= lof_CS and (not nFB_WR) and fb_b(3); - lof <= lof_q; - - -- lwd - -- $8210/2 - lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100001000"); - lwd_d <= fb_ad_in(31 downto 16) when lwd_cs; - lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and fb_b(0); - lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and fb_b(1); - - -- HORIZONTAL - -- HHT - -- $8282/2 - HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000001"); - HHT_d <= fb_ad_in(27 downto 16) when hht_cs; - HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and fb_b(2); - HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and fb_b(3); - - -- HBE - -- $8286/2 - HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000011"); - HBE_d <= fb_ad_in(27 downto 16) when hbe_cs; - HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and fb_b(2); - HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and fb_b(3); - - -- HDB - -- $8288/2 - HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000100"); - HDB_d <= fb_ad_in(27 downto 16) when hdb_cs; - HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and fb_b(0); - HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and fb_b(1); - - -- HDE - -- $828A/2 - HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000101"); - HDE_d <= fb_ad_in(27 downto 16) when hde_cs; - HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and fb_b(2); - HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and fb_b(3); - - -- HBB - -- $8284/2 - HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000010"); - HBB_d <= fb_ad_in(27 downto 16) when hbb_cs; - HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and fb_b(0); - HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and fb_b(1); - - -- HSS - -- Videl hsync start register $828C / 2 - HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000110"); - HSS_d <= fb_ad_in(27 downto 16) when hss_cs; - HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and fb_b(0); - HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and fb_b(1); - - -- VERTIKAL - -- VBE - -- $82A6/2 - VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010011"); - VBE_d <= fb_ad_in(26 downto 16) when vbe_cs; - VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and fb_b(2); - VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and fb_b(3); - - -- VDB - -- $82A8/2 - VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010100"); - VDB_d <= fb_ad_in(26 downto 16) when vdb_cs; - VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and fb_b(0); - VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and fb_b(1); - - -- VDE - -- $82AA/2 - VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010101"); - VDE_d <= fb_ad_in(26 downto 16) when vde_cs; - VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and fb_b(2); - VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and fb_b(3); - - -- VBB - -- $82A4/2 - VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010010"); - VBB_d <= fb_ad_in(26 downto 16) when vbb_cs; - VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and fb_b(0); - VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and fb_b(1); - - -- VSS - -- $82AC/2 - VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010110"); - VSS_d <= fb_ad_in(26 downto 16) when vss_cs; - VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and fb_b(0); - VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and fb_b(1); - - -- VFT - -- $82A2/2 - -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010001"); - vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); - VFT_d <= fb_ad_in(26 downto 16) when vft_cs; - VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and fb_b(2); - VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and fb_b(3); - - -- VCO - -- $82C0 / 2 Falcon clock control register VCO - VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101100000"); - VCO_d <= fb_ad_in(24 downto 16) when vco_cs; - VCO_ena(8) <= VCO_CS and (not nFB_WR) and fb_b(0); - VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and fb_b(1); - - -- VCNTRL - -- $82C2 / 2 Falcon resolution control register VCNTRL - vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; - vcntrl_d <= fb_ad_in(19 downto 16) when vcntrl_cs; - VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and fb_b(3); - --- - REGISTER OUT --- low word register access --- u0_data <= (sizeIt(st_shift_mode_CS,16) and std_logic_vector'("000000" & st_shift_mode_q & "00000000")) or --- (sizeIt(falcon_shift_mode_CS,16) and std_logic_vector'("00000" & falcon_shift_mode_q)) or --- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0))) or --- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or --- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or --- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or --- (sizeIt(hde_CS,16) and std_logic_vector'("0000" & hde_q)) or --- (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or --- (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or --- (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or --- (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or --- (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or --- (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or --- (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or --- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or --- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or --- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or --- (sizeIt(vcntrl_cs,16) and std_logic_vector'("000000000000" & vcntrl_q)) or --- (sizeIt(acp_vctr_cs,16) and acp_vctr_q(31 downto 16)) or --- (sizeIt(atari_hh_CS,16) and atari_hh_q(31 downto 16)) or --- (sizeIt(atari_vh_CS,16) and atari_vh_q(31 downto 16)) or --- (sizeIt(atari_hl_CS,16) and atari_hl_q(31 downto 16)) or --- (sizeIt(atari_vl_cs,16) and atari_vl_q(31 downto 16)) or --- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or --- (sizeIt(video_pll_config_cs,16) and std_logic_vector'("0000000" & vr_dout_q)) or --- (sizeIt(video_pll_reconfig_cs,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); - - fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else - "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else - lwd_q when lof_cs = '1' and lwd_cs = '1' else - "0000" & hbe_q when hbe_cs = '1' else - "0000" & hdb_q when hdb_cs = '1' else - "0000" & hde_q when hde_cs = '1' else - "0000" & hbb_q when hbb_cs = '1' else - "0000" & hss_q when hss_cs = '1' else - "0000" & hht_q when hht_cs = '1' else - "00000" & vbe_q when vbe_cs = '1' else - "00000" & vdb_q when vdb_cs = '1' else - "00000" & vde_q when vde_cs = '1' else - "00000" & vbb_q when vbb_cs = '1' else - "00000" & vss_q when vss_cs = '1' else - "00000" & vft_q when vft_cs = '1' else - "0000000" & vco_q when vco_cs = '1' else - "000000000000" & vcntrl_q when vcntrl_cs = '1' else - acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else - atari_hh_q(31 downto 16) when atari_hh_cs = '1' else - atari_vh_q(31 downto 16) when atari_vh_cs = '1' else - atari_hl_q(31 downto 16) when atari_hl_cs = '1' else - atari_vl_q(31 downto 16) when atari_vl_cs = '1' else - "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else - "0000000" & vr_dout_q when video_pll_config_cs = '1' else - vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else - (others => 'Z'); - --- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_cs or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or --- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or atari_vl_cs or video_pll_config_cs or --- video_pll_reconfig_cs or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); --- fb_ad(31 downto 16) <= u0_tridata; - --- high word register access --- u1_data <= (sizeIt(acp_vctr_cs,16) and acp_vctr_q(15 downto 0)) or --- (sizeIt(atari_hh_CS,16) and atari_hh_q(15 downto 0)) or --- (sizeIt(atari_vh_CS,16) and atari_vh_q(15 downto 0)) or --- (sizeIt(atari_hl_CS,16) and atari_hl_q(15 downto 0)) or --- (sizeIt(atari_vl_cs,16) and atari_vl_q(15 downto 0)) or --- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); --- u1_enabledt <= (acp_vctr_cs or border_color_CS or atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs) and (not nFB_OE); --- fb_ad(15 downto 0) <= u1_tridata; - - fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else - atari_hh_q(15 downto 0) when atari_hh_cs = '1' else - atari_vh_q(15 downto 0) when atari_vh_cs = '1' else - atari_hl_q(15 downto 0) when atari_hl_cs = '1' else - atari_vl_q(15 downto 0) when atari_vl_cs = '1' else - border_color_q(15 downto 0) when border_color_cs = '1' else - (others => 'Z'); - - video_mod_ta <= clut_ta_q or - st_shift_mode_cs or - falcon_shift_mode_cs or - acp_vctr_cs or - sys_ctr_cs or - lof_cs or - lwd_cs or - hbe_cs or - hdb_cs or - hde_cs or - hbb_cs or - hss_cs or - hht_cs or - atari_hh_cs or - atari_vh_cs or - atari_hl_cs or - atari_vl_cs or - vbe_cs or - vdb_cs or - vde_cs or - vbb_cs or - vss_cs or - vft_cs or - vco_cs or - vcntrl_cs; - - -- VIDEO AUSGABE SETZEN - CLK17M_d <= not CLK17M_q; - CLK13M_d <= not CLK13M_q; - - -- 320 pixels, 32 MHz, - -- 320 pixels, 25.175 MHz, - -- 640 pixels, 32 MHz, VGA monitor - -- 640 pixels, 25.175 MHz, VGA monitor - pixel_clk <= (CLK13M_q and (not acp_video_on) and (falcon_video or st_video) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or - (CLK17M_q and (not acp_video_on) and (falcon_video or st_video) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or - (clk25m and (not acp_video_on) and (falcon_video or st_video) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or - (clk33m and (not acp_video_on) and (falcon_video or st_video) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or - (to_std_logic((clk25m and acp_video_on)='1' and acp_vctr_q(9 downto 8) = "00")) or - (to_std_logic((clk33m and acp_video_on)='1' and acp_vctr_q(9 downto 8) = "01")) or - (clk_video and acp_video_on and acp_vctr_q(9)); - - -- ------------------------------------------------------------ - -- HORIZONTALE SYNC LÄNGE in pixel_clk - -- -------------------------------------------------------------- - - -- 320 pixels, 32 MHz, RGB - -- 320 pixels, 25.175 MHz, VGA - -- 640 pixels, 32 MHz, RGB - -- 640 pixels, 25.175 MHz, VGA - -- hsync pulse length in pixeln = frequenz / = 500ns - - hsy_len_d <= std_logic_vector'(8d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else - std_logic_vector'(8d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else - std_logic_vector'(8d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else - std_logic_vector'(8d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else - std_logic_vector'(8d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else - std_logic_vector'(8d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else - std_logic_vector(8d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else - (others => '0'); - - -- ("00001110" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or - -- ("00010000" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or - -- ("00011100" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00100000" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or - -- ("00011100" and sizeIt(acp_video_on, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or - -- ("00100000" and sizeIt(acp_video_on, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or - -- ((std_logic_vector(to_unsigned(16, hsy_len_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(acp_video_on, 8) and sizeIt(acp_vctr_q(9), 8)); - --- MULTIPLIKATIONS FAKTOR - MULF <= ("000010" and sizeIt(not st_video,6) and sizeIt(vcntrl_q(2),6)) or - ("000100" and sizeIt(not st_video,6) and sizeIt(not vcntrl_q(2),6)) or - ("010000" and sizeIt(st_video,6) and sizeIt(vcntrl_q(2),6)) or - ("100000" and sizeIt(st_video,6) and sizeIt(not vcntrl_q(2),6)); - --- BREITE IN PIXELN - hdis_len <= ("000101000000" and sizeIt(vcntrl_q(2),12)) or ("001010000000" - and sizeIt(not vcntrl_q(2),12)); - --- DOPPELZEILENMODUS --- ZEILENVERDOPPELUNG EIN AUS - dop_zei_d <= vcntrl_q(0) and (falcon_video or st_video); - --- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC --- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC - inter_zei_d <= (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) /= VDIS_START(0) - and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) < unsigned(std_logic_vector(unsigned(HDIS_END) - 1))))) or (to_std_logic(DOP_ZEI_q='1' and - VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and - (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); - --- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - dop_fifo_clr_d <= (inter_zei_q and hsync_START_q) or SYNC_PIX_q; - --- rand_links[] = HBE[] & acp_video_on --- # 21 & !acp_video_on & ATARI_SYNC & VCNTRL2 --- # 42 & !acp_video_on & ATARI_SYNC & !VCNTRL2 --- # HBE[] * (0, MULF[5..1]) & !acp_video_on & !ATARI_SYNC; -- - rand_links <= HBE_q when acp_video_on else - 12d"21" when not acp_video_on and atari_sync and vcntrl(2) else - 12d"42" when not acp_video_on and atari_sync and not(vcntrl(2)) else - std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else - (others => '0'); - - /* rand_links <= (HBE_q and sizeit(acp_video_on, 12)) or - (std_logic_vector(to_unsigned(21, 12)) and sizeit(not acp_video_on and atari_sync and vcntrl(2), 12)) or - (std_logic_vector(to_unsigned(42, 12)) and sizeit(not acp_video_on and atari_sync and not vcntrl(2), 12)) or - (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 downto 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ - --- hdis_start[] = HDB[] & acp_video_on --- # rand_links[] + 1 & !acp_video_on; -- - hdis_start <= (HDB_q and sizeIt(acp_video_on, 12)) or ((std_logic_vector(unsigned(rand_links) + 1)) and sizeIt(not acp_video_on,12)); - hdis_end <= (hde_q and sizeIt(acp_video_on, 12)) or - ((std_logic_vector(unsigned(rand_links) + unsigned(hdis_len))) and sizeIt(not acp_video_on,12)); - rand_rechts <= (HBB_q and sizeIt(acp_video_on,12)) or - ((std_logic_vector(unsigned(hdis_end) + 1)) and sizeIt(not acp_video_on, 12)); - - hs_start <= hss_q when acp_video_on else - atari_hl(11 downto 0) when not(acp_video_on) and atari_sync and vcntrl(2) else - atari_hh(11 downto 0) when not(acp_video_on) and atari_sync and not vcntrl(2) else - std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else - (others => '0'); - --- hs_start[] = HSS[] & acp_video_on --- # atari_hl[11..0] & !acp_video_on & ATARI_SYNC & VCNTRL2 --- # atari_hh[11..0] & !acp_video_on & ATARI_SYNC & !VCNTRL2 --- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !acp_video_on & !ATARI_SYNC; -- --- - h_total <= hht_q when acp_video_on else - atari_hl(27 downto 16) when not acp_video_on and atari_sync and vcntrl(2) else - atari_hh(27 downto 16) when not acp_video_on and atari_sync and not vcntrl(2) else - std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync else - (others => '0'); - --- h_total[] = HHT[] & acp_video_on --- # atari_hl[27..16] & !acp_video_on & ATARI_SYNC & VCNTRL2 --- # atari_hh[27..16] & !acp_video_on & ATARI_SYNC & !VCNTRL2 --- # (HHT[] + 2) * (0, MULF[]) & !acp_video_on & !ATARI_SYNC; -- - rand_OBEN <= (VBE_q and sizeIt(acp_video_on,11)) or ("00000011111" and - sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or - (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not - acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - - - VDIS_START <= (VDB_q and sizeIt(acp_video_on,11)) or - ("00000100000" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - - VDIS_end <= (VDE_q and sizeIt(acp_video_on,11)) or - ("00110101111" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(st_video,11)) or - ("00111111111" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not st_video,11)) or - (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - - border_bottom <= (VBB_q and sizeIt(acp_video_on,11)) or - ((std_logic_vector(unsigned(VDIS_end) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or - ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - - VS_START <= (VSS_q and sizeIt(acp_video_on,11)) or (atari_vl_q(10 downto 0) - and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(vcntrl_q(2),11)) or (atari_vh_q(10 downto 0) and sizeIt(not - acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - vcntrl_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and - sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - V_TOTAL <= (VFT_q and sizeIt(acp_video_on,11)) or (atari_vl_q(26 downto 16) - and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and - sizeIt(vcntrl_q(2),11)) or (atari_vh_q(26 downto 16) and sizeIt(not - acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not - vcntrl_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and - sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); - - -- ZÄHLER - last_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(h_total) - 2))); - - vhcnt_d <= (std_logic_vector(unsigned(vhcnt_q) + 1)) and sizeIt(not last_q,12); - - vvcnt0_ena_ctrl <= last_q; - vvcnt_d <= (std_logic_vector(unsigned(vvcnt_q) + 1)) and sizeIt(to_std_logic(vvcnt_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); - - -- DISPLAY ON OFF - -- 1 ZEILE DAVOR ON OFF - dpo_zl_d <= to_std_logic((unsigned(vvcnt_q) > unsigned(std_logic_vector(unsigned(rand_OBEN) - 1))) and (unsigned(vvcnt_q) < unsigned(std_logic_vector(unsigned(border_bottom) - 1)))); - - -- AM ZEILENendE ÃœBERNEHMEN - dpo_zl_ena <= last_q; - - -- BESSER EINZELN WEGEN TIMING - dpo_on_d <= to_std_logic(vhcnt_q = rand_links); - DPO_OFF_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(rand_rechts) - 1))); - disp_on_d <= (disp_on_q and (not DPO_OFF_q)) or (dpo_on_q and dpo_zl_q); - - -- DATENTRANSFER ON OFF - - - -- BESSER EINZELN WEGEN TIMING - vco_on_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(hdis_start) - 1))); - VCO_OFF_d <= to_std_logic(vhcnt_q = hdis_end); - - - -- AM ZEILENendE ÃœBERNEHMEN - VCO_ZL_ena <= last_q; - - -- 1 ZEILE DAVOR ON OFF - VCO_ZL_d <= to_std_logic((unsigned(vvcnt_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(vvcnt_q) < unsigned(VDIS_end))); - - VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (vco_on_q and VCO_ZL_q); - - -- VERZÖGERUNG UND SYNC - - hsync_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); - - hsync_I_d <= (HSY_LEN_q and sizeIt(hsync_START_q,8)) or - ((std_logic_vector(unsigned(hsync_I_q) - 1)) and - sizeIt(not hsync_START_q,8) and sizeIt(to_std_logic(hsync_I_q /= - "00000000"),8)); - - vsync_START_ena <= LAST_q; - - -- start am ende der Zeile vor dem vsync - vsync_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); - - -- start am ende der Zeile vor dem vsync - vsync_I0_ena_ctrl <= LAST_q; - - -- 3 zeilen vsync length - -- runterzählen bis 0 - vsync_I_d <= 3x"3" when vsync_START_q = '1' else - std_logic_vector(unsigned(vsync_I_q) - 1) when vsync_START_q = '0' and vsync_I_q /= 3x"0" else - (others => '0'); - - -- vsync_I_d <= ("011" and sizeIt(vsync_START_q,3)) or - -- ((std_logic_vector(unsigned(vsync_I_q) - 1)) and sizeIt(not vsync_START_q,3) and sizeIt(to_std_logic(vsync_I_q /= "000"),3)); - - (verz2_d(1), verz1_d(1), VERZ0_d(1)) <= std_logic_vector'(verz2_q(0) & verz1_q(0) & VERZ0_q(0)); - (verz2_d(2), verz1_d(2), VERZ0_d(2)) <= std_logic_vector'(verz2_q(1) & verz1_q(1) & VERZ0_q(1)); - (verz2_d(3), verz1_d(3), VERZ0_d(3)) <= std_logic_vector'(verz2_q(2) & verz1_q(2) & VERZ0_q(2)); - (verz2_d(4), verz1_d(4), VERZ0_d(4)) <= std_logic_vector'(verz2_q(3) & verz1_q(3) & VERZ0_q(3)); - (verz2_d(5), verz1_d(5), VERZ0_d(5)) <= std_logic_vector'(verz2_q(4) & verz1_q(4) & VERZ0_q(4)); - (verz2_d(6), verz1_d(6), VERZ0_d(6)) <= std_logic_vector'(verz2_q(5) & verz1_q(5) & VERZ0_q(5)); - (verz2_d(7), verz1_d(7), VERZ0_d(7)) <= std_logic_vector'(verz2_q(6) & verz1_q(6) & VERZ0_q(6)); - (verz2_d(8), verz1_d(8), VERZ0_d(8)) <= std_logic_vector'(verz2_q(7) & verz1_q(7) & VERZ0_q(7)); - (verz2_d(9), verz1_d(9), VERZ0_d(9)) <= std_logic_vector'(verz2_q(8) & verz1_q(8) & VERZ0_q(8)); - VERZ0_d(0) <= disp_on_q; - - -- VERZ[1][0] = hsync_I[] != 0; - -- NUR MÖGLICH WENN BEIDE - VERZ1_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') - and hsync_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(6))='1' and hsync_I_q = "00000000")); - - -- NUR MÖGLICH WENN BEIDE - VERZ2_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') - and vsync_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(5))='1' and vsync_I_q = "000")); - - -- nBLANK = VERZ[0][8]; - nblank_d <= verz0_q(8); - - -- nBLANK_d <= disp_on_q; - - -- hsync = VERZ[1][9]; - -- NUR MÖGLICH WENN BEIDE - hsync_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and - hsync_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(6))='1' and hsync_I_q = "00000000")); - - -- vsync = VERZ[2][9]; - -- NUR MÖGLICH WENN BEIDE - vsync_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and - vsync_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and - VCO_q(5))='1' and vsync_I_q = "000")); - nSYNC <= gnd; - - -- randFARBE MACHEN ------------------------------------ - rand_d(0) <= disp_on_q and (not VDTRON_q) and acp_vctr_q(25); - rand_d(1) <= rand_q(0); - rand_d(2) <= rand_q(1); - rand_d(3) <= rand_q(2); - rand_d(4) <= rand_q(3); - rand_d(5) <= rand_q(4); - rand_d(6) <= rand_q(5); - - -- rand_ON = rand[6]; - rand_on <= rand(6); - -- rand_ON <= disp_on_q and (not VDTRON_q) and acp_vctr_q(25); - - -- -------------------------------------------------------- - clr_fifo_ena <= LAST_q; - - -- IN LETZTER ZEILE LÖSCHEN - clr_fifo_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); - START_ZEILE_ena <= LAST_q; - - -- ZEILE 1 - START_ZEILE_d <= to_std_logic(vvcnt_q = "00000000000"); - - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX_d <= to_std_logic(vhcnt_q = "000000000011") and START_ZEILE_q; - - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX1_d <= to_std_logic(vhcnt_q = "000000000101") and START_ZEILE_q; - - -- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX2_d <= to_std_logic(vhcnt_q = "000000000111") and START_ZEILE_q; - - sub_pixel_cnt0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; - - -- count up if display on sonst clear bei sync pix - sub_pixel_cnt_d <= (std_logic_vector(unsigned(sub_pixel_cnt_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - - -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - fifo_rde_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and color1) or - (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and color2) or - (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or - (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and color8) or - (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and color16) or - (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and color24)) and - VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - - clut_mux_av0_d <= sub_pixel_cnt_q(3 downto 0); - clut_mux_av1_d <= clut_mux_av0_q; - clut_mux_adr_d <= clut_mux_av1_q; - - - -- Assignments added to explicitly combine the - -- effects of multiple drivers in the source - color16 <= color16_1 or color16_2; - color4_i <= COLOR4_1 or COLOR4_2; - color4 <= color4_i; - color1 <= color1_1 or color1_2 or color1_3; - color8 <= color8_1 or color8_2; - - -- Define power signal(s) - gnd <= '0'; -end ARCHITECTURE rtl; +-- Xilinx XPort Language Converter, Version 4.1 (110) +-- +-- AHDL Design Source: .tdf +-- VHDL Design Output: .vhd +-- Created 13-Jan-2016 10:03 AM +-- +-- Copyright (c) 2016, Xilinx, Inc. All Rights Reserved. +-- Xilinx Inc makes no warranty, expressed or implied, with respect to +-- the operation and/or functionality of the converted output files. +-- + +-- VIDEO MODUSE UND CLUT CONTROL + + +-- Some names could not be written out to VHDL as they were +-- in the source, and have been changed: +-- +-- AHDL VHDL +-- ==== ==== +-- VERZ0_.q VERZ0_q +-- VERZ0_.prn VERZ0_prn +-- VERZ0_.clrn VERZ0_clrn +-- VERZ0_.clk VERZ0_clk +-- VERZ0_.d VERZ0_d +-- VERZ0_ VERZ0 +-- verz1_.q verz1_q +-- verz1_.prn verz1_prn +-- verz1_.clrn verz1_clrn +-- verz1_.clk verz1_clk +-- verz1_.d verz1_d +-- verz1_ verz1 +-- verz2_.q verz2_q +-- verz2_.prn verz2_prn +-- verz2_.clrn verz2_clrn +-- verz2_.clk verz2_clk +-- verz2_.d verz2_d +-- verz2_ verz2 +-- clut_mux_av0_.q clut_mux_av0_q +-- clut_mux_av0_.prn clut_mux_av0_prn +-- clut_mux_av0_.clrn clut_mux_av0_clrn +-- clut_mux_av0_.clk clut_mux_av0_clk +-- clut_mux_av0_.d clut_mux_av0_d +-- clut_mux_av0_ clut_mux_av0 +-- clut_mux_av1_.q clut_mux_av1_q +-- clut_mux_av1_.prn clut_mux_av1_prn +-- clut_mux_av1_.clrn clut_mux_av1_clrn +-- clut_mux_av1_.clk clut_mux_av1_clk +-- clut_mux_av1_.d clut_mux_av1_d +-- clut_mux_av1_ clut_mux_av1 + + +-- CREATED BY FREDI ASCHWANDEN +-- {{ALTERA_PARAMETERS_begin}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_end}} DO NOT REMOVE THIS LINE! + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.firebee_utils_pkg.all; + +entity video_mod_mux_clutctr is + port + ( + nRSTO : in std_logic; + main_clk : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_WR : in std_logic; + nFB_OE : in std_logic; + fb_size0 : in std_logic; + fb_size1 : in std_logic; + nFB_BURST : in std_logic; + fb_adr : in std_logic_vector(31 downto 0); + clk33m : in std_logic; + clk25m : in std_logic; + blitter_run : in std_logic; + clk_video : in std_logic; + vr_d : in std_logic_vector(8 downto 0); + vr_busy : in std_logic; + color8 : out std_logic; + acp_clut_rd : out std_logic; + color1 : out std_logic; + falcon_clut_rdh : out std_logic; + falcon_clut_rdl : out std_logic; + falcon_clut_wr : out std_logic_vector(3 downto 0); + st_clut_rd : out std_logic; + st_clut_wr : out std_logic_vector(1 downto 0); + clut_mux_adr : out std_logic_vector(3 downto 0); + hsync : out std_logic; + vsync : out std_logic; + nBLANK : out std_logic; + nSYNC : out std_logic; + nPD_VGA : out std_logic; + fifo_rde : out std_logic; + color2 : out std_logic; + color4 : out std_logic; + pixel_clk : out std_logic; + clut_off : out std_logic_vector(3 downto 0); + blitter_on : out std_logic; + video_ram_ctr : out std_logic_vector(15 downto 0); + video_mod_ta : out std_logic; + border_color : out std_logic_vector(23 downto 0); + ccsel : out std_logic_vector(2 downto 0); + acp_clut_wr : out std_logic_vector(3 downto 0); + inter_zei : out std_logic; + dop_fifo_clr : out std_logic; + video_reconfig : out std_logic; + vr_wr : out std_logic; + vr_rd : out std_logic; + clr_fifo : out std_logic; + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0) + ); +end video_mod_mux_clutctr; + + +architecture rtl of video_mod_mux_clutctr is + -- DIV. CONTROL REGISTER + -- BRAUCHT EIN WAITSTAT + -- LÄNGE hsync PULS IN pixel_clk + -- LETZTES PIXEL EINER ZEILE ERREICHT + -- ATARI RESOLUTION + -- HORIZONTAL TIMING 640x480 + -- VERTIKAL TIMING 640x480 + -- HORIZONTAL TIMING 320x240 + -- VERTIKAL TIMING 320x240 + -- HORIZONTAL + -- VERTIKAL + signal vr_dout : std_logic_vector(8 downto 0); + signal vr_dout_d : std_logic_vector(8 downto 0); + signal vr_dout_q : std_logic_vector(8 downto 0); + signal vr_frq : unsigned(7 downto 0); + signal vr_frq_d : std_logic_vector(7 downto 0); + signal vr_frq_q : std_logic_vector(7 downto 0); + signal fb_b : std_logic_vector(3 downto 0); + signal FB_16B : std_logic_vector(1 downto 0); + signal st_shift_mode : std_logic_vector(1 downto 0); + signal st_shift_mode_d : std_logic_vector(1 downto 0); + signal st_shift_mode_q : std_logic_vector(1 downto 0); + signal falcon_shift_mode : std_logic_vector(10 downto 0); + signal falcon_shift_mode_d : std_logic_vector(10 downto 0); + signal falcon_shift_mode_q : std_logic_vector(10 downto 0); + signal clut_mux_adr_d : std_logic_vector(3 downto 0); + signal clut_mux_adr_q : std_logic_vector(3 downto 0); + signal clut_mux_av1 : std_logic_vector(3 downto 0); + signal clut_mux_av1_d : std_logic_vector(3 downto 0); + signal clut_mux_av1_q : std_logic_vector(3 downto 0); + signal clut_mux_av0 : std_logic_vector(3 downto 0); + signal clut_mux_av0_d : std_logic_vector(3 downto 0); + signal clut_mux_av0_q : std_logic_vector(3 downto 0); + signal acp_vctr : std_logic_vector(31 downto 0); + signal acp_vctr_d : std_logic_vector(31 downto 0); + signal acp_vctr_q : std_logic_vector(31 downto 0); + signal border_color_d : std_logic_vector(23 downto 0); + signal border_color_q : std_logic_vector(23 downto 0); + signal sys_ctr : std_logic_vector(6 downto 0); + signal sys_ctr_d : std_logic_vector(6 downto 0); + signal sys_ctr_q : std_logic_vector(6 downto 0); + signal lof : std_logic_vector(15 downto 0); + signal lof_d : std_logic_vector(15 downto 0); + signal lof_q : std_logic_vector(15 downto 0); + signal lwd : std_logic_vector(15 downto 0); + signal lwd_d : std_logic_vector(15 downto 0); + signal lwd_q : std_logic_vector(15 downto 0); + signal hsync_I : std_logic_vector(7 downto 0); + signal hsync_I_d : std_logic_vector(7 downto 0); + signal hsync_I_q : std_logic_vector(7 downto 0); + signal HSY_LEN : std_logic_vector(7 downto 0); + signal HSY_LEN_d : std_logic_vector(7 downto 0); + signal HSY_LEN_q : std_logic_vector(7 downto 0); + signal vsync_I : std_logic_vector(2 downto 0); + signal vsync_I_d : std_logic_vector(2 downto 0); + signal vsync_I_q : std_logic_vector(2 downto 0); + signal VHCNT : std_logic_vector(11 downto 0); + signal VHCNT_d : std_logic_vector(11 downto 0); + signal VHCNT_q : std_logic_vector(11 downto 0); + signal SUB_PIXEL_CNT : std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_d : std_logic_vector(6 downto 0); + signal SUB_PIXEL_CNT_q : std_logic_vector(6 downto 0); + signal VVCNT : std_logic_vector(10 downto 0); + signal VVCNT_d : std_logic_vector(10 downto 0); + signal VVCNT_q : std_logic_vector(10 downto 0); + signal VERZ2 : std_logic_vector(9 downto 0); + signal VERZ2_d : std_logic_vector(9 downto 0); + signal VERZ2_q : std_logic_vector(9 downto 0); + signal VERZ1 : std_logic_vector(9 downto 0); + signal VERZ1_d : std_logic_vector(9 downto 0); + signal VERZ1_q : std_logic_vector(9 downto 0); + signal VERZ0 : std_logic_vector(9 downto 0); + signal VERZ0_d : std_logic_vector(9 downto 0); + signal VERZ0_q : std_logic_vector(9 downto 0); + signal RAND : std_logic_vector(6 downto 0) := (others => '0'); + signal RAND_d : std_logic_vector(6 downto 0); + signal RAND_q : std_logic_vector(6 downto 0); + signal ccsel_d : std_logic_vector(2 downto 0); + signal ccsel_q : std_logic_vector(2 downto 0); + signal atari_hh : std_logic_vector(31 downto 0) := (others => '0'); + signal atari_hh_d : std_logic_vector(31 downto 0); + signal atari_hh_q : std_logic_vector(31 downto 0); + signal atari_vh : std_logic_vector(31 downto 0); + signal atari_vh_d : std_logic_vector(31 downto 0); + signal atari_vh_q : std_logic_vector(31 downto 0); + signal atari_hl : std_logic_vector(31 downto 0) := (others => '0'); + signal atari_hl_d : std_logic_vector(31 downto 0); + signal atari_hl_q : std_logic_vector(31 downto 0); + signal atari_vl : std_logic_vector(31 downto 0); + signal atari_vl_d : std_logic_vector(31 downto 0); + signal atari_vl_q : std_logic_vector(31 downto 0); + signal rand_links : std_logic_vector(11 downto 0); + signal hdis_start : std_logic_vector(11 downto 0); + signal hdis_end : std_logic_vector(11 downto 0); + signal rand_rechts : std_logic_vector(11 downto 0); + signal hs_start : std_logic_vector(11 downto 0); + signal h_total : std_logic_vector(11 downto 0); + signal hdis_len : std_logic_vector(11 downto 0); + signal MULF : std_logic_vector(5 downto 0); + signal HHT : std_logic_vector(11 downto 0) := (others => '0'); + signal HHT_d : std_logic_vector(11 downto 0); + signal HHT_q : std_logic_vector(11 downto 0); + signal HBE : std_logic_vector(11 downto 0) := (others => '0'); + signal HBE_d : std_logic_vector(11 downto 0); + signal HBE_q : std_logic_vector(11 downto 0); + signal HDB : std_logic_vector(11 downto 0); + signal HDB_d : std_logic_vector(11 downto 0); + signal HDB_q : std_logic_vector(11 downto 0); + signal HDE : std_logic_vector(11 downto 0); + signal hde_d : std_logic_vector(11 downto 0); + signal hde_q : std_logic_vector(11 downto 0); + signal HBB : std_logic_vector(11 downto 0); + signal HBB_d : std_logic_vector(11 downto 0); + signal HBB_q : std_logic_vector(11 downto 0); + signal HSS : std_logic_vector(11 downto 0) := (others => '0'); + signal HSS_d : std_logic_vector(11 downto 0); + signal HSS_q : std_logic_vector(11 downto 0); + signal rand_OBEN : std_logic_vector(10 downto 0); + signal VDIS_START : std_logic_vector(10 downto 0); + signal VDIS_end : std_logic_vector(10 downto 0); + signal border_bottom : std_logic_vector(10 downto 0); + signal VS_START : std_logic_vector(10 downto 0); + signal V_TOTAL : std_logic_vector(10 downto 0); + signal VBE : std_logic_vector(10 downto 0); + signal VBE_d : std_logic_vector(10 downto 0); + signal VBE_q : std_logic_vector(10 downto 0); + signal VDB : std_logic_vector(10 downto 0); + signal VDB_d : std_logic_vector(10 downto 0); + signal VDB_q : std_logic_vector(10 downto 0); + signal VDE : std_logic_vector(10 downto 0); + signal VDE_d : std_logic_vector(10 downto 0); + signal VDE_q : std_logic_vector(10 downto 0); + signal VBB : std_logic_vector(10 downto 0); + signal VBB_d : std_logic_vector(10 downto 0); + signal VBB_q : std_logic_vector(10 downto 0); + signal VSS : std_logic_vector(10 downto 0); + signal VSS_d : std_logic_vector(10 downto 0); + signal VSS_q : std_logic_vector(10 downto 0); + signal VFT : std_logic_vector(10 downto 0); + signal VFT_d : std_logic_vector(10 downto 0); + signal VFT_q : std_logic_vector(10 downto 0); + signal VCO : std_logic_vector(8 downto 0); + signal VCO_d : std_logic_vector(8 downto 0); + signal VCO_ena : std_logic_vector(8 downto 0); + signal VCO_q : std_logic_vector(8 downto 0); + signal VCNTRL : std_logic_vector(3 downto 0) := (others => '0'); + signal vcntrl_d : std_logic_vector(3 downto 0); + signal vcntrl_q : std_logic_vector(3 downto 0); + signal u0_data : std_logic_vector(15 downto 0); + signal u0_tridata : std_logic_vector(15 downto 0); + signal u1_data : std_logic_vector(15 downto 0); + signal u1_tridata : std_logic_vector(15 downto 0); + -- signal st_shift_mode0_clk_ctrl : std_logic; + signal st_shift_mode0_ena_ctrl : std_logic; + -- signal falcon_shift_mode0_clk_ctrl : std_logic; + signal falcon_shift_mode8_ena_ctrl : std_logic; + signal falcon_shift_mode0_ena_ctrl : std_logic; + + signal acp_vctr24_ena_ctrl : std_logic; + signal acp_vctr16_ena_ctrl : std_logic; + signal acp_vctr8_ena_ctrl : std_logic; + signal acp_vctr6_ena_ctrl : std_logic; + signal acp_vctr0_ena_ctrl : std_logic; + + signal atari_hh24_ena_ctrl : std_logic; + signal atari_hh16_ena_ctrl : std_logic; + signal atari_hh8_ena_ctrl : std_logic; + signal atari_hh0_ena_ctrl : std_logic; + signal atari_vh24_ena_ctrl : std_logic; + signal atari_vh16_ena_ctrl : std_logic; + signal atari_vh8_ena_ctrl : std_logic; + signal atari_vh0_ena_ctrl : std_logic; + signal atari_hl24_ena_ctrl : std_logic; + signal atari_hl16_ena_ctrl : std_logic; + signal atari_hl8_ena_ctrl : std_logic; + signal atari_hl0_ena_ctrl : std_logic; + signal atari_vl0_clk_ctrl : std_logic; + signal atari_vl24_ena_ctrl : std_logic; + signal atari_vl16_ena_ctrl : std_logic; + signal atari_vl8_ena_ctrl : std_logic; + signal atari_vl0_ena_ctrl : std_logic; + signal vr_dout0_ena_ctrl : std_logic; + signal vr_frq0_ena_ctrl : std_logic; + signal border_color16_ena_ctrl : std_logic; + signal border_color8_ena_ctrl : std_logic; + signal border_color0_ena_ctrl : std_logic; + signal sys_ctr0_ena_ctrl : std_logic; + signal lof8_ena_ctrl : std_logic; + signal lof0_ena_ctrl : std_logic; + signal lwd8_ena_ctrl : std_logic; + signal lwd0_ena_ctrl : std_logic; + signal HHT8_ena_ctrl : std_logic; + signal HHT0_ena_ctrl : std_logic; + signal HBE8_ena_ctrl : std_logic; + signal HBE0_ena_ctrl : std_logic; + signal HDB8_ena_ctrl : std_logic; + signal HDB0_ena_ctrl : std_logic; + signal HDE8_ena_ctrl : std_logic; + signal hde0_ena_ctrl : std_logic; + signal HBB8_ena_ctrl : std_logic; + signal HBB0_ena_ctrl : std_logic; + signal HSS0_clk_ctrl : std_logic; + signal HSS8_ena_ctrl : std_logic; + signal HSS0_ena_ctrl : std_logic; + signal VBE8_ena_ctrl : std_logic; + signal VBE0_ena_ctrl : std_logic; + signal VDB8_ena_ctrl : std_logic; + signal VDB0_ena_ctrl : std_logic; + signal VDE8_ena_ctrl : std_logic; + signal vde0_ena_ctrl : std_logic; + signal VBB8_ena_ctrl : std_logic; + signal VBB0_ena_ctrl : std_logic; + signal VSS8_ena_ctrl : std_logic; + signal VSS0_ena_ctrl : std_logic; + signal VFT8_ena_ctrl : std_logic; + signal VFT0_ena_ctrl : std_logic; + signal VCO0_ena_ctrl : std_logic; + signal VCNTRL0_ena_ctrl : std_logic; + signal VVCNT0_ena_ctrl : std_logic; + signal vsync_I0_ena_ctrl : std_logic; + signal SUB_PIXEL_CNT0_ena_ctrl : std_logic; + signal color8_2 : std_logic; + signal color8_1 : std_logic; + signal color1_3 : std_logic; + signal color1_2 : std_logic; + signal color1_1 : std_logic; + signal COLOR4_2 : std_logic; + signal COLOR4_1 : std_logic; + signal color16_2 : std_logic; + signal color16_1 : std_logic; + signal gnd : std_logic; + signal u1_enabledt : std_logic; + signal u0_enabledt : std_logic; + signal vcntrl_cs : std_logic; + signal VCO_CS : std_logic; + signal VFT_CS : std_logic; + signal VSS_CS : std_logic; + signal VBB_CS : std_logic; + signal VDE_CS : std_logic; + signal VDB_CS : std_logic; + signal VBE_CS : std_logic; + signal dop_fifo_clr_q : std_logic; + signal dop_fifo_clr_d : std_logic; + signal DOP_ZEI_q : std_logic; + signal DOP_ZEI_d : std_logic; + signal DOP_ZEI : std_logic; + signal inter_zei_q : std_logic; + signal inter_zei_d : std_logic; + signal st_video : std_logic; + signal falcon_video : std_logic; + signal HSS_CS : std_logic; + signal HBB_CS : std_logic; + signal hde_CS : std_logic; + signal HDB_CS : std_logic; + signal HBE_CS : std_logic; + signal HHT_CS : std_logic; + signal atari_vl_cs : std_logic; + signal atari_hl_CS : std_logic; + signal atari_vh_CS : std_logic; + signal atari_hh_CS : std_logic; + signal ATARI_SYNC : std_logic; + signal color24 : std_logic; + signal color16 : std_logic; + signal SYNC_PIX2_q : std_logic; + signal SYNC_PIX2_d : std_logic; + signal SYNC_PIX2 : std_logic; + signal SYNC_PIX1_q : std_logic; + signal SYNC_PIX1_d : std_logic; + signal SYNC_PIX1 : std_logic; + signal SYNC_PIX_q : std_logic; + signal SYNC_PIX_d : std_logic; + signal SYNC_PIX : std_logic; + signal START_ZEILE_q : std_logic; + signal START_ZEILE_ena : std_logic; + signal START_ZEILE_d : std_logic; + signal START_ZEILE : std_logic; + signal clr_fifo_q : std_logic; + signal clr_fifo_ena : std_logic; + signal clr_fifo_d : std_logic; + signal fifo_rde_q : std_logic; + signal fifo_rde_d : std_logic; + signal RAND_ON : std_logic; + signal VCO_OFF_q : std_logic; + signal VCO_OFF_d : std_logic; + signal VCO_OFF : std_logic; + signal vco_on_q : std_logic; + signal vco_on_d : std_logic; + signal vco_on : std_logic; + signal VCO_ZL_q : std_logic; + signal VCO_ZL_ena : std_logic; + signal VCO_ZL_d : std_logic; + signal VCO_ZL : std_logic; + signal VDTRON_q : std_logic; + signal VDTRON_d : std_logic; + signal VDTRON : std_logic; + signal DPO_OFF_q : std_logic; + signal DPO_OFF_d : std_logic; + signal DPO_OFF : std_logic; + signal dpo_on_q : std_logic; + signal dpo_on_d : std_logic; + signal DPO_ON : std_logic; + signal dpo_zl_q : std_logic; + signal dpo_zl_ena : std_logic; + signal dpo_zl_d : std_logic; + signal DPO_ZL : std_logic; + signal disp_on_q : std_logic; + signal disp_on_d : std_logic; + signal DISP_ON : std_logic; + signal nBLANK_q : std_logic; + signal nBLANK_d : std_logic; + signal vsync_START_q : std_logic; + signal vsync_START_ena : std_logic; + signal vsync_START_d : std_logic; + signal vsync_START : std_logic; + signal vsync_q : std_logic; + signal vsync_d : std_logic; + signal LAST_q : std_logic; + signal LAST_d : std_logic; + signal LAST : std_logic; + signal hsync_START_q : std_logic; + signal hsync_START_d : std_logic; + signal hsync_START : std_logic; + signal hsync_q : std_logic; + signal hsync_d : std_logic; + signal CLUT_TA_q : std_logic; + signal CLUT_TA_d : std_logic; + signal CLUT_TA : std_logic; + signal lwd_CS : std_logic; + signal lof_CS : std_logic; + signal sys_ctr_CS : std_logic; + signal acp_video_on : std_logic; + signal border_color_CS : std_logic; + signal acp_vctr_cs : std_logic; + signal falcon_shift_mode_CS : std_logic; + signal st_shift_mode_CS : std_logic; + signal ST_CLUT : std_logic; + signal st_clut_cs : std_logic; + signal falcon_clut : std_logic; + signal falcon_clut_cs : std_logic; + signal video_reconfig_q : std_logic; + signal video_reconfig_d : std_logic; + signal video_pll_reconfig_cs : std_logic; + signal vr_wr_q : std_logic; + signal vr_wr_d : std_logic; + signal video_pll_config_cs : std_logic; + signal acp_clut : std_logic; + signal acp_clut_cs : std_logic; + signal CLK13M_q : std_logic; + signal CLK13M_d : std_logic; + signal CLK13M : std_logic; + signal CLK17M_q : std_logic; + signal CLK17M_d : std_logic; + signal CLK17M : std_logic; + signal color4_i : std_logic; + signal pixel_clk_i : std_logic; + + -- Sub Module Interface Section + + function to_std_logic(X : in boolean) return std_logic is + variable ret : std_logic; + begin + if x then + ret := '1'; + else + ret := '0'; + end if; + return ret; + end function to_std_logic; + + + -- sizeIt replicates a value to an array of specific length. + function sizeit(a : std_Logic; len : integer) return std_logic_vector is + variable rep : std_logic_vector(len - 1 downto 0); + begin + for i in rep'range loop + rep(i) := a; + end loop; + return rep; + end function sizeit; + +begin + -- Register Section + + clut_mux_adr <= clut_mux_adr_q; + + -- missing signals that seem to got lost during conversion + hsync <= hsync_q; + acp_vctr <= acp_vctr_q; + rand <= rand_q; + atari_hh <= atari_hh_q; + atari_hl <= atari_hl_q; + HBE <= HBE_q; + HSS <= HSS_q; + VCO <= VCO_q; + VCNTRL <= vcntrl_q; + + vsync <= vsync_q; + nBLANK <= nBLANK_q; + fifo_rde <= fifo_rde_q; + border_color(23 downto 16) <= border_color_q(23 downto 16); + border_color(15 downto 8) <= border_color_q(15 downto 8); + border_color(7 downto 0) <= border_color_q(7 downto 0); + ccsel <= ccsel_q; + inter_zei <= inter_zei_q; + dop_fifo_clr <= dop_fifo_clr_q; + HHT <= HHT_q; + + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then + clut_mux_adr_q <= clut_mux_adr_d; + hsync_q <= hsync_d; + vsync_q <= vsync_d; + nBLANK_q <= nBLANK_d; + fifo_rde_q <= fifo_rde_d; + if border_color16_ena_ctrl = '1' then + border_color_q(23 downto 16) <= border_color_d(23 downto 16); + end if; + if border_color8_ena_ctrl = '1' then + border_color_q(15 downto 8) <= border_color_d(15 downto 8); + end if; + if border_color0_ena_ctrl = '1' then + border_color_q(7 downto 0) <= border_color_d(7 downto 0); + end if; + ccsel_q <= ccsel_d; + inter_zei_q <= inter_zei_d; + dop_fifo_clr_q <= dop_fifo_clr_d; + end if; + end process; + + video_reconfig <= video_reconfig_q; + + vr_wr <= vr_wr_q; + + clr_fifo <= clr_fifo_q; + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then + if clr_fifo_ena = '1' then + clr_fifo_q <= clr_fifo_d; + end if; + end if; + end process; + + process (clk25m) + begin + if rising_edge(clk25m) then + CLK13M_q <= CLK13M_d; + end if; + end process; + + vr_frq <= unsigned(vr_frq_q); + + process (main_clk) + begin + if rising_edge(main_clk) then + vr_wr_q <= vr_wr_d; + + video_reconfig_q <= video_reconfig_d; + + CLK17M_q <= CLK17M_d; + + if vr_dout0_ena_ctrl = '1' then + vr_dout_q <= vr_dout_d; + end if; + + if vr_frq0_ena_ctrl = '1' then + vr_frq_q <= vr_frq_d; + end if; + + if st_shift_mode0_ena_ctrl = '1' then + st_shift_mode_q <= st_shift_mode_d; + end if; + + if falcon_shift_mode8_ena_ctrl = '1' then + falcon_shift_mode_q(10 downto 8) <= falcon_shift_mode_d(10 downto 8); + end if; + + if falcon_shift_mode0_ena_ctrl = '1' then + falcon_shift_mode_q(7 downto 0) <= falcon_shift_mode_d(7 downto 0); + end if; + if acp_vctr24_ena_ctrl = '1' then + acp_vctr_q(31 downto 24) <= acp_vctr_d(31 downto 24); + end if; + + if acp_vctr16_ena_ctrl = '1' then + acp_vctr_q(23 downto 16) <= acp_vctr_d(23 downto 16); + end if; + + if acp_vctr8_ena_ctrl = '1' then + acp_vctr_q(15 downto 8) <= acp_vctr_d(15 downto 8); + end if; + + if acp_vctr6_ena_ctrl = '1' then + acp_vctr_q(7 downto 6) <= acp_vctr_d(7 downto 6); + end if; + + if acp_vctr0_ena_ctrl = '1' then + acp_vctr_q(5 downto 0) <= acp_vctr_d(5 downto 0); + end if; + + if sys_ctr0_ena_ctrl='1' then + sys_ctr_q <= sys_ctr_d; + end if; + + if lof8_ena_ctrl = '1' then + lof_q(15 downto 8) <= lof_d(15 downto 8); + end if; + + if lof0_ena_ctrl = '1' then + lof_q(7 downto 0) <= lof_d(7 downto 0); + end if; + + if lwd8_ena_ctrl = '1' then + lwd_q(15 downto 8) <= lwd_d(15 downto 8); + end if; + + if lwd0_ena_ctrl = '1' then + lwd_q(7 downto 0) <= lwd_d(7 downto 0); + end if; + + if HDB8_ena_ctrl = '1' then + HDB_q(11 downto 8) <= HDB_d(11 downto 8); + end if; + + if HDB0_ena_ctrl = '1' then + HDB_q(7 downto 0) <= HDB_d(7 downto 0); + end if; + + if HDE8_ena_ctrl = '1' then + hde_q(11 downto 8) <= hde_d(11 downto 8); + end if; + + if hde0_ena_ctrl = '1' then + hde_q(7 downto 0) <= hde_d(7 downto 0); + end if; + + if HBB8_ena_ctrl = '1' then + HBB_q(11 downto 8) <= HBB_d(11 downto 8); + end if; + + if HBB0_ena_ctrl = '1' then + HBB_q(7 downto 0) <= HBB_d(7 downto 0); + end if; + + if HSS8_ena_ctrl = '1' then + HSS_q(11 downto 8) <= HSS_d(11 downto 8); + end if; + + if HSS0_ena_ctrl='1' then + HSS_q(7 downto 0) <= HSS_d(7 downto 0); + end if; + + dop_zei_q <= dop_zei_d; + + if VBE8_ena_ctrl = '1' then + VBE_q(10 downto 8) <= VBE_d(10 downto 8); + end if; + + if VBE0_ena_ctrl = '1' then + VBE_q(7 downto 0) <= VBE_d(7 downto 0); + end if; + + if VDB8_ena_ctrl = '1' then + VDB_q(10 downto 8) <= VDB_d(10 downto 8); + end if; + + if VDB0_ena_ctrl = '1' then + VDB_q(7 downto 0) <= VDB_d(7 downto 0); + end if; + + if VDE8_ena_ctrl = '1' then + VDE_q(10 downto 8) <= VDE_d(10 downto 8); + end if; + + if vde0_ena_ctrl = '1' then + VDE_q(7 downto 0) <= VDE_d(7 downto 0); + end if; + + if VBB8_ena_ctrl = '1' then + VBB_q(10 downto 8) <= VBB_d(10 downto 8); + end if; + + if VBB0_ena_ctrl = '1' then + VBB_q(7 downto 0) <= VBB_d(7 downto 0); + end if; + + if VSS8_ena_ctrl = '1' then + VSS_q(10 downto 8) <= VSS_d(10 downto 8); + end if; + + if VSS0_ena_ctrl = '1' then + VSS_q(7 downto 0) <= VSS_d(7 downto 0); + end if; + + if VFT8_ena_ctrl = '1' then + VFT_q(10 downto 8) <= VFT_d(10 downto 8); + end if; + + if VFT0_ena_ctrl = '1' then + VFT_q(7 downto 0) <= VFT_d(7 downto 0); + end if; + + if VCO_ena(8) = '1' then + VCO_q(8) <= VCO_d(8); + end if; + + if VCO0_ena_ctrl = '1' then + VCO_q(7 downto 0) <= VCO_d(7 downto 0); + end if; + + if vcntrl0_ena_ctrl = '1' then + vcntrl_q <= vcntrl_d; + end if; + end if; + end process; + + process (pixel_clk_i) + begin + if rising_edge(pixel_clk_i) then + clut_mux_av1_q <= clut_mux_av1_d; + clut_mux_av0_q <= clut_mux_av0_d; + CLUT_TA_q <= CLUT_TA_d; + hsync_I_q <= hsync_I_d; + HSY_LEN_q <= HSY_LEN_d; + hsync_START_q <= hsync_START_d; + LAST_q <= LAST_d; + + if vsync_START_ena = '1' then + vsync_START_q <= vsync_START_d; + end if; + + if vsync_I0_ena_ctrl='1' then + vsync_I_q <= vsync_I_d; + end if; + + disp_on_q <= disp_on_d; + + if dpo_zl_ena = '1' then + dpo_zl_q <= dpo_zl_d; + end if; + + dpo_on_q <= dpo_on_d; + DPO_OFF_q <= DPO_OFF_d; + VDTRON_q <= VDTRON_d; + + if VCO_ZL_ena = '1' then + VCO_ZL_q <= VCO_ZL_d; + end if; + + vco_on_q <= vco_on_d; + VCO_OFF_q <= VCO_OFF_d; + vhcnt_q <= vhcnt_d; + + if sub_pixel_cnt0_ena_ctrl = '1' then + sub_pixel_cnt_q <= sub_pixel_cnt_d; + end if; + + if vvcnt0_ena_ctrl='1' then + vvcnt_q <= vvcnt_d; + end if; + + verz2_q <= verz2_d; + verz1_q <= verz1_d; + VERZ0_q <= VERZ0_d; + rand_q <= rand_d; + + if START_ZEILE_ena = '1' then + START_ZEILE_q <= START_ZEILE_d; + end if; + + SYNC_PIX_q <= SYNC_PIX_d; + SYNC_PIX1_q <= SYNC_PIX1_d; + SYNC_PIX2_q <= SYNC_PIX2_d; + + if atari_hh24_ena_ctrl = '1' then + atari_hh_q(31 downto 24) <= atari_hh_d(31 downto 24); + end if; + + if atari_hh16_ena_ctrl = '1' then + atari_hh_q(23 downto 16) <= atari_hh_d(23 downto 16); + end if; + + if atari_hh8_ena_ctrl = '1' then + atari_hh_q(15 downto 8) <= atari_hh_d(15 downto 8); + end if; + + if atari_hh0_ena_ctrl = '1' then + atari_hh_q(7 downto 0) <= atari_hh_d(7 downto 0); + end if; + + if atari_vh24_ena_ctrl = '1' then + atari_vh_q(31 downto 24) <= atari_vh_d(31 downto 24); + end if; + + if atari_vh16_ena_ctrl = '1' then + atari_vh_q(23 downto 16) <= atari_vh_d(23 downto 16); + end if; + + if atari_vh8_ena_ctrl = '1' then + atari_vh_q(15 downto 8) <= atari_vh_d(15 downto 8); + end if; + + if atari_vh0_ena_ctrl='1' then + atari_vh_q(7 downto 0) <= atari_vh_d(7 downto 0); + end if; + + if atari_hl24_ena_ctrl = '1' then + atari_hl_q(31 downto 24) <= atari_hl_d(31 downto 24); + end if; + + if atari_hl16_ena_ctrl = '1' then + atari_hl_q(23 downto 16) <= atari_hl_d(23 downto 16); + end if; + + if atari_hl8_ena_ctrl = '1' then + atari_hl_q(15 downto 8) <= atari_hl_d(15 downto 8); + end if; + + if atari_hl0_ena_ctrl = '1' then + atari_hl_q(7 downto 0) <= atari_hl_d(7 downto 0); + end if; + + if atari_vl24_ena_ctrl = '1' then + atari_vl_q(31 downto 24) <= atari_vl_d(31 downto 24); + end if; + + if atari_vl16_ena_ctrl = '1' then + atari_vl_q(23 downto 16) <= atari_vl_d(23 downto 16); + end if; + + if atari_vl8_ena_ctrl = '1' then + atari_vl_q(15 downto 8) <= atari_vl_d(15 downto 8); + end if; + + if atari_vl0_ena_ctrl = '1' then + atari_vl_q(7 downto 0) <= atari_vl_d(7 downto 0); + end if; + + if HHT8_ena_ctrl = '1' then + HHT_q(11 downto 8) <= HHT_d(11 downto 8); + end if; + + if HHT0_ena_ctrl = '1' then + HHT_q(7 downto 0) <= HHT_d(7 downto 0); + end if; + + if HBE8_ena_ctrl = '1' then + HBE_q(11 downto 8) <= HBE_d(11 downto 8); + end if; + + if HBE0_ena_ctrl = '1' then + HBE_q(7 downto 0) <= HBE_d(7 downto 0); + end if; + end if; + end process; + + +-- Start of original equations + + -- BYT SELECT 32 BIT + -- ADR==0 + -- fb_b(0) <= to_std_logic(fb_adr(1 downto 0) = "00"); + fb_b(0) <= '1' when fb_adr(1 downto 0) = "00" else '0'; + + -- ADR==1 + -- HIGH WORD + -- LONG UND LINE + fb_b(1) <= to_std_logic(fb_adr(1 downto 0) = "01") or + (fb_size1 and (not fb_size0) and (not fb_adr(1))) or (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); + + -- ADR==2 + -- LONG UND LINE + fb_b(2) <= to_std_logic(fb_adr(1 downto 0) = "10") or + (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); + + -- ADR==3 + -- LOW WORD + -- LONG UND LINE + fb_b(3) <= to_std_logic(fb_adr(1 downto 0) = "11") or + (fb_size1 and (not fb_size0) and fb_adr(1)) or + (fb_size1 and fb_size0) or + ((not fb_size1) and (not fb_size0)); + + -- BYT SELECT 16 BIT + -- ADR==0 + FB_16B(0) <= to_std_logic(fb_adr(0) = '0'); + + -- ADR==1 + -- NOT BYT + FB_16B(1) <= to_std_logic(fb_adr(0) = '1') or (not ((not fb_size1) and fb_size0)); + + -- ACP CLUT -- + -- 0-3FF/1024 + acp_clut_cs <= to_std_logic(((not nFB_CS2) = '1') and fb_adr(27 downto 10) = "000000000000000000"); + acp_clut_rd <= acp_clut_cs and (not nFB_OE); + acp_clut_wr <= fb_b and sizeIt(acp_clut_cs, 4) and sizeIt(not nFB_WR, 4); + CLUT_TA_d <= (acp_clut_cs or falcon_clut_cs or st_clut_cs) and (not video_mod_ta); + + -- FALCON CLUT -- + -- $F9800/$400 + falcon_clut_cs <= to_std_logic(((not nFB_CS1) = '1') and fb_adr(19 downto 10) = "1111100110"); + + -- HIGH WORD + falcon_clut_rdh <= falcon_clut_cs and (not nFB_OE) and (not fb_adr(1)); + + -- LOW WORD + falcon_clut_rdl <= falcon_clut_cs and (not nFB_OE) and fb_adr(1); + falcon_clut_wr(1 downto 0) <= FB_16B and std_logic_vector'((not fb_adr(1)) & + (not fb_adr(1))) and std_logic_vector'(falcon_clut_cs & falcon_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + falcon_clut_wr(3 downto 2) <= FB_16B and std_logic_vector'(fb_adr(1) & fb_adr(1)) and std_logic_vector'(falcon_clut_cs & falcon_clut_cs) and + std_logic_vector'((not nFB_WR) & (not nFB_WR)); + + -- ST CLUT -- + -- $F8240/$20 + st_clut_cs <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 5) = "111110000010010"); + st_clut_rd <= st_clut_cs and (not nFB_OE); + st_clut_wr <= FB_16B and std_logic_vector'(st_clut_cs & st_clut_cs) and std_logic_vector'((not nFB_WR) & (not nFB_WR)); + + -- ST shift mode + + -- $F8260/2 + st_shift_mode_cs <= '1' when nFB_CS1 = '0' and fb_adr(19 downto 1) = 19x"7c130" else '0'; + -- st_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100110000"); + st_shift_mode_d <= fb_ad_in(25 downto 24) when st_shift_mode_cs; + st_shift_mode0_ena_ctrl <= st_shift_mode_CS and (not nFB_WR) and fb_b(0); + + -- MONO + color1_1 <= to_std_logic(st_shift_mode_q = "10") and (not color8) and st_video and (not acp_video_on); + + -- 4 FARBEN + color2 <= to_std_logic(st_shift_mode_q = "01") and (not color8) and st_video and (not acp_video_on); + + -- 16 FARBEN + COLOR4_1 <= to_std_logic(st_shift_mode_q = "00") and (not color8) and st_video and (not acp_video_on); + + -- FALCON shift mode + + -- $F8266/2 + falcon_shift_mode_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100110011"); + falcon_shift_mode_d <= fb_ad_in(26 downto 16) when falcon_shift_mode_cs; + falcon_shift_mode8_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and fb_b(2); + falcon_shift_mode0_ena_ctrl <= falcon_shift_mode_CS and (not nFB_WR) and fb_b(3); + + clut_off <= falcon_shift_mode_q(3 downto 0) and sizeIt(COLOR4_i, 4); + color1_2 <= falcon_shift_mode_q(10) and (not color16) and (not color8) and falcon_video and (not acp_video_on); + color8_1 <= falcon_shift_mode_q(4) and (not color16) and falcon_video and (not acp_video_on); + color16_1 <= falcon_shift_mode_q(8) and falcon_video and (not acp_video_on); + COLOR4_2 <= (not color1) and (not color16) and (not color8) and falcon_video and (not acp_video_on); + + -- ACP VIDEO CONTROL + -- BIT 0 = ACP VIDEO ON + -- BIT 1 = POWER ON VIDEO DAC + -- BIT 2 = ACP 24BIT + -- BIT 3 = ACP 16BIT + -- BIT 4 = ACP 8BIT + -- BIT 5 = ACP 1BIT + -- BIT 6 = FALCON SHifT MODE + -- BIT 7 = ST SHifT MODE + -- BIT 9..8 = VCLK FREQUENZ + -- BIT 15 =-SYNC ALLOWED + -- BIT 31..16 = video_ram_ctr + -- BIT 25 = RANDFARBE EINSCHALTEN + -- BIT 26 = STANDARD ATARI SYNCS + + -- $400/4 + acp_vctr_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000000"); + + acp_vctr_d(31 downto 8) <= fb_ad_in(31 downto 8) when acp_vctr_cs; + acp_vctr_d(5 downto 0) <= fb_ad_in(5 downto 0) when acp_vctr_cs; + + acp_vctr24_ena_ctrl <= acp_vctr_cs and fb_b(0) and (not nFB_WR); + acp_vctr16_ena_ctrl <= acp_vctr_cs and fb_b(1) and (not nFB_WR); + acp_vctr8_ena_ctrl <= acp_vctr_cs and fb_b(2) and (not nFB_WR); + acp_vctr0_ena_ctrl <= acp_vctr_cs and fb_b(3) and (not nFB_WR); + acp_video_on <= acp_vctr_q(0); + nPD_VGA <= acp_vctr_q(1); + + -- ATARI MODUS + -- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC <= acp_vctr_q(26); + + -- HORIZONTAL TIMING 640x480 + + -- $410/4 + atari_hh_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000100"); + atari_hh_d <= fb_ad_in when atari_hh_cs; + atari_hh24_ena_ctrl <= atari_hh_cs and fb_b(0) and (not nFB_WR); + atari_hh16_ena_ctrl <= atari_hh_cs and fb_b(1) and (not nFB_WR); + atari_hh8_ena_ctrl <= atari_hh_cs and fb_b(2) and (not nFB_WR); + atari_hh0_ena_ctrl <= atari_hh_cs and fb_b(3) and (not nFB_WR); + + -- VERTIKAL TIMING 640x480 + + -- $414/4 + atari_vh_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000101"); + atari_vh_d <= fb_ad_in when atari_vh_cs; + atari_vh24_ena_ctrl <= atari_vh_cs and fb_b(0) and (not nFB_WR); + atari_vh16_ena_ctrl <= atari_vh_cs and fb_b(1) and (not nFB_WR); + atari_vh8_ena_ctrl <= atari_vh_cs and fb_b(2) and (not nFB_WR); + atari_vh0_ena_ctrl <= atari_vh_cs and fb_b(3) and (not nFB_WR); + + -- HORIZONTAL TIMING 320x240 + + -- $418/4 + atari_hl_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000110"); + atari_hl_d <= fb_ad_in when atari_hl_cs; + atari_hl24_ena_ctrl <= atari_hl_cs and fb_b(0) and (not nFB_WR); + atari_hl16_ena_ctrl <= atari_hl_cs and fb_b(1) and (not nFB_WR); + atari_hl8_ena_ctrl <= atari_hl_cs and fb_b(2) and (not nFB_WR); + atari_hl0_ena_ctrl <= atari_hl_cs and fb_b(3) and (not nFB_WR); + + -- VERTIKAL TIMING 320x240 + + -- $41C/4 + atari_vl_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 2) = "00000000000000000100000111"); + atari_vl_d <= fb_ad_in when atari_vl_cs; + atari_vl24_ena_ctrl <= atari_vl_cs and fb_b(0) and (not nFB_WR); + atari_vl16_ena_ctrl <= atari_vl_cs and fb_b(1) and (not nFB_WR); + atari_vl8_ena_ctrl <= atari_vl_cs and fb_b(2) and (not nFB_WR); + atari_vl0_ena_ctrl <= atari_vl_cs and fb_b(3) and (not nFB_WR); + + -- VIDEO PLL CONFIG + -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + video_pll_config_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 9) = "0000000000000000011") and fb_b(0) and fb_b(1); + vr_wr_d <= video_pll_config_cs and (not nFB_WR) and (not vr_busy) and (not vr_wr_q); + vr_rd <= video_pll_config_cs and nFB_WR and (not vr_busy); + vr_dout0_ena_ctrl <= not vr_busy; + vr_dout_d <= vr_d; + vr_frq0_ena_ctrl <= to_std_logic(vr_wr_q='1' and fb_adr(8 downto 0) = "000000100"); + vr_frq_d <= fb_ad_in(23 downto 16) when video_pll_config_cs; + + -- VIDEO PLL RECONFIG + -- $(F)000'0800 + video_pll_reconfig_cs <= to_std_logic(((not nFB_CS2)='1') and fb_adr(27 downto 0) = "0000000000000000100000000000") and fb_b(0); + video_reconfig_d <= video_pll_reconfig_cs and (not nFB_WR) and (not vr_busy) and (not video_reconfig_q); + + -- ---------------------------------------------------------------------------------------------------------------------- + video_ram_ctr <= acp_vctr_q(31 downto 16); + + -- ------------ COLOR MODE IM ACP SETZEN + color1_3 <= acp_vctr_q(5) and (not acp_vctr_q(4)) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and acp_video_on; + color8_2 <= acp_vctr_q(4) and (not acp_vctr_q(3)) and (not acp_vctr_q(2)) and acp_video_on; + color16_2 <= acp_vctr_q(3) and (not acp_vctr_q(2)) and acp_video_on; + color24 <= acp_vctr_q(2) and acp_video_on; + acp_clut <= (acp_video_on and (color1 or color8)) or (st_video and color1); + + -- ST ODER FALCON SHifT MODE SETZEN WENN WRITE X..SHifT REGISTER + acp_vctr_d(7) <= falcon_shift_mode_CS and (not nFB_WR) and (not acp_video_on); + acp_vctr_d(6) <= st_shift_mode_CS and (not nFB_WR) and (not acp_video_on); + + acp_vctr6_ena_ctrl <= (falcon_shift_mode_CS and (not nFB_WR)) or (st_shift_mode_CS and (not nFB_WR)) or (acp_vctr_cs and fb_b(3) and (not nFB_WR) and fb_ad_in(0)); + falcon_video <= acp_vctr_q(7); + falcon_clut <= falcon_video and (not acp_video_on) and (not color16); + st_video <= acp_vctr_q(6); + ST_CLUT <= st_video and (not acp_video_on) and (not falcon_clut) and (not color1); + pixel_clk_i <= pixel_clk; + + -- ONLY FOR INFORMATION + ccsel_d <= ("000" and sizeIt(ST_CLUT,3)) or ("001" and + sizeIt(falcon_clut,3)) or ("100" and sizeIt(acp_clut,3)) or ("101" and + sizeIt(color16,3)) or ("110" and sizeIt(color24,3)) or ("111" and + sizeIt(RAND_ON,3)); + + -- DIVERSE (VIDEO)-REGISTER ---------------------------- + -- randFARBE + + -- $404/4 + border_color_CS <= to_std_logic(((not nFB_CS2) = '1') and fb_adr(27 downto 2) = "00000000000000000100000001"); + border_color_d <= fb_ad_in(23 downto 0) when border_color_cs; + border_color16_ena_ctrl <= border_color_CS and fb_b(1) and (not nFB_WR); + border_color8_ena_ctrl <= border_color_CS and fb_b(2) and (not nFB_WR); + border_color0_ena_ctrl <= border_color_CS and fb_b(3) and (not nFB_WR); + + -- System Config Register + -- $FFFF8006 [R/W] B 76543210 Monitor-Type Hi + -- |||||||| + -- |||||||+- RAM Wait Status + -- ||||||| 0 = 1 Wait (default) + -- ||||||| 1 = 0 Wait + -- ||||||+-- Video Bus Width + -- |||||| 0 = 16 Bit + -- |||||| 1 = 32 Bit (default) + -- ||||++--- ROM Wait Status + -- |||| 00 = reserved + -- |||| 01 = 2 Wait (default) + -- |||| 10 = 1 Wait + -- |||| 11 = 0 Wait + -- ||++----- Main Memory Size + -- || 01 = 4 MB + -- || 10 = 16 MB + -- ++------- Monitor Type + -- 00 Monochrome + -- 01 RGB + -- 10 VGA + -- 11 TV + -- $8006/2 + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr, 20x"f8006") = '1' else '0'; + -- fb_adr(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; + + -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adr(19 downto 1) = "1111100000000000011"); + sys_ctr_d <= fb_ad_in(22 downto 16) when sys_ctr_cs; + sys_ctr0_ena_ctrl <= sys_ctr_CS and (not nFB_WR) and fb_b(3); + blitter_on <= not sys_ctr_q(3); + + -- lof + -- $820E/2 + lof_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100000111"); + lof_d <= fb_ad_in(31 downto 16) when lof_cs; + lof8_ena_ctrl <= lof_CS and (not nFB_WR) and fb_b(2); + lof0_ena_ctrl <= lof_CS and (not nFB_WR) and fb_b(3); + lof <= lof_q; + + -- lwd + -- $8210/2 + lwd_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000100001000"); + lwd_d <= fb_ad_in(31 downto 16) when lwd_cs; + lwd8_ena_ctrl <= lwd_CS and (not nFB_WR) and fb_b(0); + lwd0_ena_ctrl <= lwd_CS and (not nFB_WR) and fb_b(1); + + -- HORIZONTAL + -- HHT + -- $8282/2 + HHT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000001"); + HHT_d <= fb_ad_in(27 downto 16) when hht_cs; + HHT8_ena_ctrl <= HHT_CS and (not nFB_WR) and fb_b(2); + HHT0_ena_ctrl <= HHT_CS and (not nFB_WR) and fb_b(3); + + -- HBE + -- $8286/2 + HBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000011"); + HBE_d <= fb_ad_in(27 downto 16) when hbe_cs; + HBE8_ena_ctrl <= HBE_CS and (not nFB_WR) and fb_b(2); + HBE0_ena_ctrl <= HBE_CS and (not nFB_WR) and fb_b(3); + + -- HDB + -- $8288/2 + HDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000100"); + HDB_d <= fb_ad_in(27 downto 16) when hdb_cs; + HDB8_ena_ctrl <= HDB_CS and (not nFB_WR) and fb_b(0); + HDB0_ena_ctrl <= HDB_CS and (not nFB_WR) and fb_b(1); + + -- HDE + -- $828A/2 + HDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000101"); + HDE_d <= fb_ad_in(27 downto 16) when hde_cs; + HDE8_ena_ctrl <= HDE_CS and (not nFB_WR) and fb_b(2); + HDE0_ena_ctrl <= HDE_CS and (not nFB_WR) and fb_b(3); + + -- HBB + -- $8284/2 + HBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000010"); + HBB_d <= fb_ad_in(27 downto 16) when hbb_cs; + HBB8_ena_ctrl <= HBB_CS and (not nFB_WR) and fb_b(0); + HBB0_ena_ctrl <= HBB_CS and (not nFB_WR) and fb_b(1); + + -- HSS + -- Videl hsync start register $828C / 2 + HSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101000110"); + HSS_d <= fb_ad_in(27 downto 16) when hss_cs; + HSS8_ena_ctrl <= HSS_CS and (not nFB_WR) and fb_b(0); + HSS0_ena_ctrl <= HSS_CS and (not nFB_WR) and fb_b(1); + + -- VERTIKAL + -- VBE + -- $82A6/2 + VBE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010011"); + VBE_d <= fb_ad_in(26 downto 16) when vbe_cs; + VBE8_ena_ctrl <= VBE_CS and (not nFB_WR) and fb_b(2); + VBE0_ena_ctrl <= VBE_CS and (not nFB_WR) and fb_b(3); + + -- VDB + -- $82A8/2 + VDB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010100"); + VDB_d <= fb_ad_in(26 downto 16) when vdb_cs; + VDB8_ena_ctrl <= VDB_CS and (not nFB_WR) and fb_b(0); + VDB0_ena_ctrl <= VDB_CS and (not nFB_WR) and fb_b(1); + + -- VDE + -- $82AA/2 + VDE_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010101"); + VDE_d <= fb_ad_in(26 downto 16) when vde_cs; + VDE8_ena_ctrl <= VDE_CS and (not nFB_WR) and fb_b(2); + VDE0_ena_ctrl <= VDE_CS and (not nFB_WR) and fb_b(3); + + -- VBB + -- $82A4/2 + VBB_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010010"); + VBB_d <= fb_ad_in(26 downto 16) when vbb_cs; + VBB8_ena_ctrl <= VBB_CS and (not nFB_WR) and fb_b(0); + VBB0_ena_ctrl <= VBB_CS and (not nFB_WR) and fb_b(1); + + -- VSS + -- $82AC/2 + VSS_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010110"); + VSS_d <= fb_ad_in(26 downto 16) when vss_cs; + VSS8_ena_ctrl <= VSS_CS and (not nFB_WR) and fb_b(0); + VSS0_ena_ctrl <= VSS_CS and (not nFB_WR) and fb_b(1); + + -- VFT + -- $82A2/2 + -- VFT_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101010001"); + vft_cs <= not nFB_CS1 and f_addr_cmp_w(fb_adr(19 downto 0), x"f82a2"); + VFT_d <= fb_ad_in(26 downto 16) when vft_cs; + VFT8_ena_ctrl <= VFT_CS and (not nFB_WR) and fb_b(2); + VFT0_ena_ctrl <= VFT_CS and (not nFB_WR) and fb_b(3); + + -- VCO + -- $82C0 / 2 Falcon clock control register VCO + VCO_CS <= to_std_logic(((not nFB_CS1)='1') and fb_adr(19 downto 1) = "1111100000101100000"); + VCO_d <= fb_ad_in(24 downto 16) when vco_cs; + VCO_ena(8) <= VCO_CS and (not nFB_WR) and fb_b(0); + VCO0_ena_ctrl <= VCO_CS and (not nFB_WR) and fb_b(1); + + -- VCNTRL + -- $82C2 / 2 Falcon resolution control register VCNTRL + vcntrl_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adr(19 downto 0), x"f82c2") = '1' else '0'; + vcntrl_d <= fb_ad_in(19 downto 16) when vcntrl_cs; + VCNTRL0_ena_ctrl <= vcntrl_cs and (not nFB_WR) and fb_b(3); + +-- - REGISTER OUT +-- low word register access +-- u0_data <= (sizeIt(st_shift_mode_CS,16) and std_logic_vector'("000000" & st_shift_mode_q & "00000000")) or +-- (sizeIt(falcon_shift_mode_CS,16) and std_logic_vector'("00000" & falcon_shift_mode_q)) or +-- (sizeIt(sys_ctr_CS,16) and std_logic_vector'("100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0))) or +-- (sizeIt(lof_CS,16) and lof_q) or (sizeIt(lwd_CS,16) and lwd_q) or +-- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or +-- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or +-- (sizeIt(hde_CS,16) and std_logic_vector'("0000" & hde_q)) or +-- (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or +-- (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or +-- (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or +-- (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or +-- (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or +-- (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or +-- (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or +-- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or +-- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or +-- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or +-- (sizeIt(vcntrl_cs,16) and std_logic_vector'("000000000000" & vcntrl_q)) or +-- (sizeIt(acp_vctr_cs,16) and acp_vctr_q(31 downto 16)) or +-- (sizeIt(atari_hh_CS,16) and atari_hh_q(31 downto 16)) or +-- (sizeIt(atari_vh_CS,16) and atari_vh_q(31 downto 16)) or +-- (sizeIt(atari_hl_CS,16) and atari_hl_q(31 downto 16)) or +-- (sizeIt(atari_vl_cs,16) and atari_vl_q(31 downto 16)) or +-- (sizeIt(border_color_CS,16) and std_logic_vector'("00000000" & border_color_q(23 downto 16))) or +-- (sizeIt(video_pll_config_cs,16) and std_logic_vector'("0000000" & vr_dout_q)) or +-- (sizeIt(video_pll_reconfig_cs,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); + + fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else + "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else + lwd_q when lof_cs = '1' and lwd_cs = '1' else + "0000" & hbe_q when hbe_cs = '1' else + "0000" & hdb_q when hdb_cs = '1' else + "0000" & hde_q when hde_cs = '1' else + "0000" & hbb_q when hbb_cs = '1' else + "0000" & hss_q when hss_cs = '1' else + "0000" & hht_q when hht_cs = '1' else + "00000" & vbe_q when vbe_cs = '1' else + "00000" & vdb_q when vdb_cs = '1' else + "00000" & vde_q when vde_cs = '1' else + "00000" & vbb_q when vbb_cs = '1' else + "00000" & vss_q when vss_cs = '1' else + "00000" & vft_q when vft_cs = '1' else + "0000000" & vco_q when vco_cs = '1' else + "000000000000" & vcntrl_q when vcntrl_cs = '1' else + acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else + atari_hh_q(31 downto 16) when atari_hh_cs = '1' else + atari_vh_q(31 downto 16) when atari_vh_cs = '1' else + atari_hl_q(31 downto 16) when atari_hl_cs = '1' else + atari_vl_q(31 downto 16) when atari_vl_cs = '1' else + "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else + "0000000" & vr_dout_q when video_pll_config_cs = '1' else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else + (others => 'Z'); + +-- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_cs or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or +-- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or atari_vl_cs or video_pll_config_cs or +-- video_pll_reconfig_cs or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); +-- fb_ad(31 downto 16) <= u0_tridata; + +-- high word register access +-- u1_data <= (sizeIt(acp_vctr_cs,16) and acp_vctr_q(15 downto 0)) or +-- (sizeIt(atari_hh_CS,16) and atari_hh_q(15 downto 0)) or +-- (sizeIt(atari_vh_CS,16) and atari_vh_q(15 downto 0)) or +-- (sizeIt(atari_hl_CS,16) and atari_hl_q(15 downto 0)) or +-- (sizeIt(atari_vl_cs,16) and atari_vl_q(15 downto 0)) or +-- (sizeIt(border_color_CS,16) and border_color_q(15 downto 0)); +-- u1_enabledt <= (acp_vctr_cs or border_color_CS or atari_hh_cs or atari_vh_cs or atari_hl_cs or atari_vl_cs) and (not nFB_OE); +-- fb_ad(15 downto 0) <= u1_tridata; + + fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else + atari_hh_q(15 downto 0) when atari_hh_cs = '1' else + atari_vh_q(15 downto 0) when atari_vh_cs = '1' else + atari_hl_q(15 downto 0) when atari_hl_cs = '1' else + atari_vl_q(15 downto 0) when atari_vl_cs = '1' else + border_color_q(15 downto 0) when border_color_cs = '1' else + (others => 'Z'); + + video_mod_ta <= clut_ta_q or + st_shift_mode_cs or + falcon_shift_mode_cs or + acp_vctr_cs or + sys_ctr_cs or + lof_cs or + lwd_cs or + hbe_cs or + hdb_cs or + hde_cs or + hbb_cs or + hss_cs or + hht_cs or + atari_hh_cs or + atari_vh_cs or + atari_hl_cs or + atari_vl_cs or + vbe_cs or + vdb_cs or + vde_cs or + vbb_cs or + vss_cs or + vft_cs or + vco_cs or + vcntrl_cs; + + -- VIDEO AUSGABE SETZEN + CLK17M_d <= not CLK17M_q; + CLK13M_d <= not CLK13M_q; + + -- 320 pixels, 32 MHz, + -- 320 pixels, 25.175 MHz, + -- 640 pixels, 32 MHz, VGA monitor + -- 640 pixels, 25.175 MHz, VGA monitor + pixel_clk <= (CLK13M_q and (not acp_video_on) and (falcon_video or st_video) and ((VCNTRL_q(2) and VCO_q(2)) or VCO_q(0))) or + (CLK17M_q and (not acp_video_on) and (falcon_video or st_video) and ((VCNTRL_q(2) and (not VCO_q(2))) or VCO_q(0))) or + (clk25m and (not acp_video_on) and (falcon_video or st_video) and (not VCNTRL_q(2)) and VCO_q(2) and (not VCO_q(0))) or + (clk33m and (not acp_video_on) and (falcon_video or st_video) and (not VCNTRL_q(2)) and (not VCO_q(2)) and (not VCO_q(0))) or + (to_std_logic((clk25m and acp_video_on)='1' and acp_vctr_q(9 downto 8) = "00")) or + (to_std_logic((clk33m and acp_video_on)='1' and acp_vctr_q(9 downto 8) = "01")) or + (clk_video and acp_video_on and acp_vctr_q(9)); + + -- ------------------------------------------------------------ + -- HORIZONTALE SYNC LÄNGE in pixel_clk + -- -------------------------------------------------------------- + + -- 320 pixels, 32 MHz, RGB + -- 320 pixels, 25.175 MHz, VGA + -- 640 pixels, 32 MHz, RGB + -- 640 pixels, 25.175 MHz, VGA + -- hsync pulse length in pixeln = frequenz / = 500ns + + hsy_len_d <= std_logic_vector'(8d"14") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '1' or vco(0) = '1') else + std_logic_vector'(8d"16") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '1' and (vco(2) = '0' or vco(0) = '1') else + std_logic_vector'(8d"28") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '1' and vco(0) = '0' else + std_logic_vector'(8d"32") when acp_video_on = '0' and (falcon_video = '1' or st_video = '1') and vcntrl(2) = '0' and vco(2) = '0' and vco(0) = '0' else + std_logic_vector'(8d"28") when acp_video_on = '1' and acp_vctr(9 downto 8) = "00" else + std_logic_vector'(8d"32") when acp_video_on = '1' and acp_vctr(9 downto 8) = "01" else + std_logic_vector(8d"16" + ("0" & vr_frq(7 downto 1))) when acp_video_on = '1' and acp_vctr(9) = '1' else + (others => '0'); + + -- ("00001110" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8)) or sizeIt(VCO_q(0), 8))) or + -- ("00010000" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and ((sizeIt(vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8)) or sizeIt(VCO_q(0),8))) or + -- ("00011100" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00100000" and sizeIt(not acp_video_on, 8) and (sizeIt(falcon_video, 8) or sizeIt(st_video, 8)) and sizeIt(not vcntrl_q(2), 8) and sizeIt(not VCO_q(2), 8) and sizeIt(not VCO_q(0), 8)) or + -- ("00011100" and sizeIt(acp_video_on, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "00"), 8)) or + -- ("00100000" and sizeIt(acp_video_on, 8) and sizeIt(to_std_logic(acp_vctr_q(9 downto 8) = "01"), 8)) or + -- ((std_logic_vector(to_unsigned(16, hsy_len_d'LENGTH) + unsigned(std_logic_vector('0' & vr_frq_q(7 downto 1))))) and sizeIt(acp_video_on, 8) and sizeIt(acp_vctr_q(9), 8)); + +-- MULTIPLIKATIONS FAKTOR + MULF <= ("000010" and sizeIt(not st_video,6) and sizeIt(vcntrl_q(2),6)) or + ("000100" and sizeIt(not st_video,6) and sizeIt(not vcntrl_q(2),6)) or + ("010000" and sizeIt(st_video,6) and sizeIt(vcntrl_q(2),6)) or + ("100000" and sizeIt(st_video,6) and sizeIt(not vcntrl_q(2),6)); + +-- BREITE IN PIXELN + hdis_len <= ("000101000000" and sizeIt(vcntrl_q(2),12)) or ("001010000000" + and sizeIt(not vcntrl_q(2),12)); + +-- DOPPELZEILENMODUS +-- ZEILENVERDOPPELUNG EIN AUS + dop_zei_d <= vcntrl_q(0) and (falcon_video or st_video); + +-- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC +-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + inter_zei_d <= (to_std_logic(DOP_ZEI_q='1' and VVCNT_q(0) /= VDIS_START(0) + and VVCNT_q /= "00000000000" and (unsigned(VHCNT_q) < unsigned(std_logic_vector(unsigned(HDIS_END) - 1))))) or (to_std_logic(DOP_ZEI_q='1' and + VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and + (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2))))); + +-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + dop_fifo_clr_d <= (inter_zei_q and hsync_START_q) or SYNC_PIX_q; + +-- rand_links[] = HBE[] & acp_video_on +-- # 21 & !acp_video_on & ATARI_SYNC & VCNTRL2 +-- # 42 & !acp_video_on & ATARI_SYNC & !VCNTRL2 +-- # HBE[] * (0, MULF[5..1]) & !acp_video_on & !ATARI_SYNC; -- + rand_links <= HBE_q when acp_video_on else + 12d"21" when not acp_video_on and atari_sync and vcntrl(2) else + 12d"42" when not acp_video_on and atari_sync and not(vcntrl(2)) else + std_logic_vector(resize(unsigned(hbe) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else + (others => '0'); + + /* rand_links <= (HBE_q and sizeit(acp_video_on, 12)) or + (std_logic_vector(to_unsigned(21, 12)) and sizeit(not acp_video_on and atari_sync and vcntrl(2), 12)) or + (std_logic_vector(to_unsigned(42, 12)) and sizeit(not acp_video_on and atari_sync and not vcntrl(2), 12)) or + (std_logic_vector(unsigned(hbe) * unsigned(mulf(5 downto 1))) and sizeit(not acp_video_on and not atari_sync, 12)); */ + +-- hdis_start[] = HDB[] & acp_video_on +-- # rand_links[] + 1 & !acp_video_on; -- + hdis_start <= (HDB_q and sizeIt(acp_video_on, 12)) or ((std_logic_vector(unsigned(rand_links) + 1)) and sizeIt(not acp_video_on,12)); + hdis_end <= (hde_q and sizeIt(acp_video_on, 12)) or + ((std_logic_vector(unsigned(rand_links) + unsigned(hdis_len))) and sizeIt(not acp_video_on,12)); + rand_rechts <= (HBB_q and sizeIt(acp_video_on,12)) or + ((std_logic_vector(unsigned(hdis_end) + 1)) and sizeIt(not acp_video_on, 12)); + + hs_start <= hss_q when acp_video_on else + atari_hl(11 downto 0) when not(acp_video_on) and atari_sync and vcntrl(2) else + atari_hh(11 downto 0) when not(acp_video_on) and atari_sync and not vcntrl(2) else + std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 downto 1)), 12)) when not acp_video_on and not atari_sync else + (others => '0'); + +-- hs_start[] = HSS[] & acp_video_on +-- # atari_hl[11..0] & !acp_video_on & ATARI_SYNC & VCNTRL2 +-- # atari_hh[11..0] & !acp_video_on & ATARI_SYNC & !VCNTRL2 +-- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !acp_video_on & !ATARI_SYNC; -- +-- + h_total <= hht_q when acp_video_on else + atari_hl(27 downto 16) when not acp_video_on and atari_sync and vcntrl(2) else + atari_hh(27 downto 16) when not acp_video_on and atari_sync and not vcntrl(2) else + std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) when not acp_video_on and not atari_sync else + (others => '0'); + +-- h_total[] = HHT[] & acp_video_on +-- # atari_hl[27..16] & !acp_video_on & ATARI_SYNC & VCNTRL2 +-- # atari_hh[27..16] & !acp_video_on & ATARI_SYNC & !VCNTRL2 +-- # (HHT[] + 2) * (0, MULF[]) & !acp_video_on & !ATARI_SYNC; -- + rand_OBEN <= (VBE_q and sizeIt(acp_video_on,11)) or ("00000011111" and + sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or + (std_logic_vector'('0' & VBE_q(10 downto 1)) and sizeIt(not + acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + + + VDIS_START <= (VDB_q and sizeIt(acp_video_on,11)) or + ("00000100000" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 downto 1))) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + + VDIS_end <= (VDE_q and sizeIt(acp_video_on,11)) or + ("00110101111" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC, 11) and sizeIt(st_video,11)) or + ("00111111111" and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not st_video,11)) or + (std_logic_vector'('0' & VDE_q(10 downto 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + + border_bottom <= (VBB_q and sizeIt(acp_video_on,11)) or + ((std_logic_vector(unsigned(VDIS_end) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11)) or + ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 downto 1))) + 1)) and sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + + VS_START <= (VSS_q and sizeIt(acp_video_on,11)) or (atari_vl_q(10 downto 0) + and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and + sizeIt(vcntrl_q(2),11)) or (atari_vh_q(10 downto 0) and sizeIt(not + acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not + vcntrl_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 downto 1)) and + sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + V_TOTAL <= (VFT_q and sizeIt(acp_video_on,11)) or (atari_vl_q(26 downto 16) + and sizeIt(not acp_video_on,11) and sizeIt(ATARI_SYNC,11) and + sizeIt(vcntrl_q(2),11)) or (atari_vh_q(26 downto 16) and sizeIt(not + acp_video_on,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not + vcntrl_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and + sizeIt(not acp_video_on,11) and sizeIt(not ATARI_SYNC,11)); + + -- ZÄHLER + last_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(h_total) - 2))); + + vhcnt_d <= (std_logic_vector(unsigned(vhcnt_q) + 1)) and sizeIt(not last_q,12); + + vvcnt0_ena_ctrl <= last_q; + vvcnt_d <= (std_logic_vector(unsigned(vvcnt_q) + 1)) and sizeIt(to_std_logic(vvcnt_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); + + -- DISPLAY ON OFF + -- 1 ZEILE DAVOR ON OFF + dpo_zl_d <= to_std_logic((unsigned(vvcnt_q) > unsigned(std_logic_vector(unsigned(rand_OBEN) - 1))) and (unsigned(vvcnt_q) < unsigned(std_logic_vector(unsigned(border_bottom) - 1)))); + + -- AM ZEILENendE ÃœBERNEHMEN + dpo_zl_ena <= last_q; + + -- BESSER EINZELN WEGEN TIMING + dpo_on_d <= to_std_logic(vhcnt_q = rand_links); + DPO_OFF_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(rand_rechts) - 1))); + disp_on_d <= (disp_on_q and (not DPO_OFF_q)) or (dpo_on_q and dpo_zl_q); + + -- DATENTRANSFER ON OFF + + + -- BESSER EINZELN WEGEN TIMING + vco_on_d <= to_std_logic(vhcnt_q = (std_logic_vector(unsigned(hdis_start) - 1))); + VCO_OFF_d <= to_std_logic(vhcnt_q = hdis_end); + + + -- AM ZEILENendE ÃœBERNEHMEN + VCO_ZL_ena <= last_q; + + -- 1 ZEILE DAVOR ON OFF + VCO_ZL_d <= to_std_logic((unsigned(vvcnt_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(vvcnt_q) < unsigned(VDIS_end))); + + VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (vco_on_q and VCO_ZL_q); + + -- VERZÖGERUNG UND SYNC + + hsync_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); + + hsync_I_d <= (HSY_LEN_q and sizeIt(hsync_START_q,8)) or + ((std_logic_vector(unsigned(hsync_I_q) - 1)) and + sizeIt(not hsync_START_q,8) and sizeIt(to_std_logic(hsync_I_q /= + "00000000"),8)); + + vsync_START_ena <= LAST_q; + + -- start am ende der Zeile vor dem vsync + vsync_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); + + -- start am ende der Zeile vor dem vsync + vsync_I0_ena_ctrl <= LAST_q; + + -- 3 zeilen vsync length + -- runterzählen bis 0 + vsync_I_d <= 3x"3" when vsync_START_q = '1' else + std_logic_vector(unsigned(vsync_I_q) - 1) when vsync_START_q = '0' and vsync_I_q /= 3x"0" else + (others => '0'); + + -- vsync_I_d <= ("011" and sizeIt(vsync_START_q,3)) or + -- ((std_logic_vector(unsigned(vsync_I_q) - 1)) and sizeIt(not vsync_START_q,3) and sizeIt(to_std_logic(vsync_I_q /= "000"),3)); + + (verz2_d(1), verz1_d(1), VERZ0_d(1)) <= std_logic_vector'(verz2_q(0) & verz1_q(0) & VERZ0_q(0)); + (verz2_d(2), verz1_d(2), VERZ0_d(2)) <= std_logic_vector'(verz2_q(1) & verz1_q(1) & VERZ0_q(1)); + (verz2_d(3), verz1_d(3), VERZ0_d(3)) <= std_logic_vector'(verz2_q(2) & verz1_q(2) & VERZ0_q(2)); + (verz2_d(4), verz1_d(4), VERZ0_d(4)) <= std_logic_vector'(verz2_q(3) & verz1_q(3) & VERZ0_q(3)); + (verz2_d(5), verz1_d(5), VERZ0_d(5)) <= std_logic_vector'(verz2_q(4) & verz1_q(4) & VERZ0_q(4)); + (verz2_d(6), verz1_d(6), VERZ0_d(6)) <= std_logic_vector'(verz2_q(5) & verz1_q(5) & VERZ0_q(5)); + (verz2_d(7), verz1_d(7), VERZ0_d(7)) <= std_logic_vector'(verz2_q(6) & verz1_q(6) & VERZ0_q(6)); + (verz2_d(8), verz1_d(8), VERZ0_d(8)) <= std_logic_vector'(verz2_q(7) & verz1_q(7) & VERZ0_q(7)); + (verz2_d(9), verz1_d(9), VERZ0_d(9)) <= std_logic_vector'(verz2_q(8) & verz1_q(8) & VERZ0_q(8)); + VERZ0_d(0) <= disp_on_q; + + -- VERZ[1][0] = hsync_I[] != 0; + -- NUR MÖGLICH WENN BEIDE + VERZ1_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') + and hsync_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(6))='1' and hsync_I_q = "00000000")); + + -- NUR MÖGLICH WENN BEIDE + VERZ2_d(0) <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') + and vsync_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(5))='1' and vsync_I_q = "000")); + + -- nBLANK = VERZ[0][8]; + nblank_d <= verz0_q(8); + + -- nBLANK_d <= disp_on_q; + + -- hsync = VERZ[1][9]; + -- NUR MÖGLICH WENN BEIDE + hsync_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(6)))='1') and + hsync_I_q /= "00000000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(6))='1' and hsync_I_q = "00000000")); + + -- vsync = VERZ[2][9]; + -- NUR MÖGLICH WENN BEIDE + vsync_d <= (to_std_logic((((not acp_vctr_q(15)) or (not VCO_q(5)))='1') and + vsync_I_q /= "000")) or (to_std_logic((acp_vctr_q(15) and + VCO_q(5))='1' and vsync_I_q = "000")); + nSYNC <= gnd; + + -- randFARBE MACHEN ------------------------------------ + rand_d(0) <= disp_on_q and (not VDTRON_q) and acp_vctr_q(25); + rand_d(1) <= rand_q(0); + rand_d(2) <= rand_q(1); + rand_d(3) <= rand_q(2); + rand_d(4) <= rand_q(3); + rand_d(5) <= rand_q(4); + rand_d(6) <= rand_q(5); + + -- rand_ON = rand[6]; + rand_on <= rand(6); + -- rand_ON <= disp_on_q and (not VDTRON_q) and acp_vctr_q(25); + + -- -------------------------------------------------------- + clr_fifo_ena <= LAST_q; + + -- IN LETZTER ZEILE LÖSCHEN + clr_fifo_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); + START_ZEILE_ena <= LAST_q; + + -- ZEILE 1 + START_ZEILE_d <= to_std_logic(vvcnt_q = "00000000000"); + + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX_d <= to_std_logic(vhcnt_q = "000000000011") and START_ZEILE_q; + + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX1_d <= to_std_logic(vhcnt_q = "000000000101") and START_ZEILE_q; + + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX2_d <= to_std_logic(vhcnt_q = "000000000111") and START_ZEILE_q; + + sub_pixel_cnt0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; + + -- count up if display on sonst clear bei sync pix + sub_pixel_cnt_d <= (std_logic_vector(unsigned(sub_pixel_cnt_q) + 1)) and sizeIt(not SYNC_PIX_q,7); + + -- 3 CLOCK ZUSÄTZLICH FÃœR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + fifo_rde_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and color1) or + (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and color2) or + (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or + (to_std_logic(SUB_PIXEL_CNT_q(3 downto 0) = "0001") and color8) or + (to_std_logic(SUB_PIXEL_CNT_q(2 downto 0) = "001") and color16) or + (to_std_logic(SUB_PIXEL_CNT_q(1 downto 0) = "01") and color24)) and + VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; + + clut_mux_av0_d <= sub_pixel_cnt_q(3 downto 0); + clut_mux_av1_d <= clut_mux_av0_q; + clut_mux_adr_d <= clut_mux_av1_q; + + + -- Assignments added to explicitly combine the + -- effects of multiple drivers in the source + color16 <= color16_1 or color16_2; + color4_i <= COLOR4_1 or COLOR4_2; + color4 <= color4_i; + color1 <= color1_1 or color1_2 or color1_3; + color8 <= color8_1 or color8_2; + + -- Define power signal(s) + gnd <= '0'; +end ARCHITECTURE rtl;

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z&ivBL;$AaWm!s)BK01PB+8#-XzlduP=Kt@Fr^OfFcmos7{E=(o@E@FsQDXV}8~5EW zCVz~H=G(tABbPy8!2j_TqMYFDnR^`S&t6DSj>`y+VDU`Qg{kYAd+ryv{>7M1%*6kC z;>b55v*LLpwk6cW5HHe$AA5@px}ftlB+I=+>Bmgwt`=*WPw>#q?l=V zf&yc#1gReHApt1zfJ=#ouARAGoc$vrt(aKCqD2LZ6m%(`C4fE(!|qCM-epD^9e}*B>bgqP1uDUK6uxXOKdNs%I53 z<^qDCYcwlZaVhFTmxJI%aaMog%*BU4@|!RH+>a>nTYqPKVfv(-Jn14tH{w{lA5Q5d&*4QlX9~@Z zdJZ4_DaB4JeG5XE|LJM8>_o1csmUxmT)Nykl!!!2Mmq1hwaj>GrbxHig>|S^Bw7BV zhN9U@DcdFV4{lGS(0Yt+wYONJaPeU=n=e0q@l^>DUVEYs!Erd6Ek>B$KL5_qd9epH z-i~C(G$+rA_!4>@#x!?pIPZT4Go?dWF2S@bGLS2bX*(*s;QblFbQYBSZ?@gnD z%Vq+yRnuBsv7nh2W0bKNrEsF4hqFa5jub%>KX-2m$Qk6HbwQ=PDAatKK1_r&C)gu From 8ec08da1fd74af3df34d7237112b88d79aa237d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 07:01:21 +0000 Subject: [PATCH 009/127] add TimeQuest Synopsis Design Constraint file --- FPGA_Quartus_13.1/firebee1.sdc | 512 +++++++++++++++++++++++++++++++++ 1 file changed, 512 insertions(+) create mode 100644 FPGA_Quartus_13.1/firebee1.sdc diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc new file mode 100644 index 0000000..4560656 --- /dev/null +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -0,0 +1,512 @@ +## Generated SDC file "firebee1.sdc" + +## Copyright (C) 1991-2014 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" + +## DATE "Sun Sep 20 08:38:08 2015" + +## +## DEVICE "EP3C40F484C6" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name {CLK33M} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK33M}] +create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}] +create_clock -name {E0_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {E0_INT}] +create_clock -name {nPCI_INTB} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTB}] +create_clock -name {nPCI_INTA} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTA}] +create_clock -name {DVI_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {DVI_INT}] +create_clock -name {nPCI_INTC} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTC}] +create_clock -name {nPCI_INTD} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTD}] +create_clock -name {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC} -period 1.000 -waveform { 0.000 0.500 } [get_registers {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] +create_clock -name {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC} -period 1.000 -waveform { 0.000 0.500 } [get_registers {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] +create_clock -name {PIC_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {PIC_INT}] + + +#************************************************************** +# Create Generated Clock +#************************************************************** + +create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 66 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[0]}] +create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 67 -divide_by 900 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[1]}] +create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 67 -divide_by 90 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[2]}] +create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 1800 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[0]}] +create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 225 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[1]}] +create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 144 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[2]}] +create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 75 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[3]}] +create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 240.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[0]}] +create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[1]}] +create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 180.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[2]}] +create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 105.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[3]}] +create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -phase 270.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[4]}] +create_generated_clock -name {inst22|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst22|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {inst13|altpll_component|auto_generated|pll1|clk[3]} [get_pins {inst22|altpll_component|auto_generated|pll1|clk[0]}] + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.110 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.110 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.110 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.110 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {PIC_INT}] -rise_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {PIC_INT}] -fall_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {PIC_INT}] -rise_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {PIC_INT}] -fall_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.140 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.140 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -setup 0.130 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -setup 0.130 +set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.140 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.140 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -setup 0.130 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -setup 0.130 +set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {PIC_INT}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {PIC_INT}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTD}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTD}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTC}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTC}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {DVI_INT}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {DVI_INT}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTA}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTA}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTB}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTB}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {E0_INT}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {E0_INT}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {CLK33M}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {CLK33M}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {PIC_INT}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {PIC_INT}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTD}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTD}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTC}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTC}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {DVI_INT}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {DVI_INT}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTA}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTA}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTB}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTB}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {E0_INT}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {E0_INT}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {CLK33M}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {CLK33M}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -hold 0.060 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -hold 0.060 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {MAIN_CLK}] 0.030 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {CLK33M}] 0.020 +set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK33M}] 0.020 + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -from [get_clocks {CLK33M}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] +set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] +set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] +set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + From 4f57571130e615d293303df5a7757e3ab65df411 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 08:06:12 +0000 Subject: [PATCH 010/127] renamed many instances to more meaningful names --- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 40 +- FPGA_Quartus_13.1/Video/Video.bdf | 21302 ++++++++-------- FPGA_Quartus_13.1/firebee1.bdf | 11674 ++++----- FPGA_Quartus_13.1/firebee1.qsf | 5 +- FPGA_Quartus_13.1/firebee1.qws | Bin 90 -> 4717 bytes 5 files changed, 16512 insertions(+), 16509 deletions(-) diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index 2c9adcc..2b777db 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -1,4 +1,4 @@ -TITLE "VIDEO MODUSE UND CLUT CONTROL"; +TITLE "VIDEO MODI AND CLUT CONTROL"; -- CREATED BY FREDI ASCHWANDEN @@ -101,7 +101,7 @@ VARIABLE CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK + HSY_LEN[7..0] :DFF; -- L�NGE HSYNC PULS IN PIXEL_CLK HSYNC_START :DFF; LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT VSYNC :DFF; @@ -191,6 +191,7 @@ VARIABLE VDL_VCT_CS :NODE; VDL_VMD[3..0] :DFFE; VDL_VMD_CS :NODE; + ACP_VCTR6_DUP : NODE; BEGIN -- BYT SELECT 32 BIT @@ -254,7 +255,7 @@ BEGIN ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL�SUNG -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 @@ -312,7 +313,10 @@ BEGIN ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + + -- duplicate ACP_VCTR6 according to TimeQuest reccomendations + ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ACP_VCTR6_DUP; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; FALCON_VIDEO = ACP_VCTR7; FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; @@ -497,7 +501,7 @@ BEGIN # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; -------------------------------------------------------------- --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +-- HORIZONTALE SYNC L�NGE in PIXEL_CLK ---------------------------------------------------------------- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) @@ -524,7 +528,7 @@ BEGIN INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L�SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 @@ -566,7 +570,7 @@ BEGIN # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- ZÄHLER +-- Z�HLER LAST.CLK = PIXEL_CLK; LAST = VHCNT[]==(H_TOTAL[]-2); VHCNT[].CLK = PIXEL_CLK; @@ -577,7 +581,7 @@ BEGIN -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[]1S=a` z8!Jtrf?#c-XeC%^VJiqWHvSDp6BAGfRCK7|GK=E$!h6ZB25 z^dxK8PTFM~pjFVjNXeT^YAqIIc{fJ`7`7>FNf?R9?i2Gyrd}8)bie@ntJsVk&>5b>SB3=UkloK8fwcVl~LNs z2GzDJ`H-TG*BXRpCh1~z#@N}T^?XT&Wn`~AHH~w>aFucETy3FA2KMt}Ihy0-pPT84 zy?guG4H?rhJ4BRk633U+FCj(rdGx2$!z2i19C}%ToI&z{EMtAv@4yQon2I2nUjb+u z=;ax$@fn9}U<)39rV;yu@s*|asMENM4?kOy7XM7P9S;MjR#aKh+!KgiENC4yVjIyE z#Y5~ex&wJr?WZJWtq&+~FX`==-e_l=2^_Nyj6m%qA9Y_=&9>f>7c_2yP62Ev=m_vv zOtus8CoIn^>e|wM=#SB#QxB6s*Uvhq;Jv^EJTY6E7M+t--m8Kx>%HQ<_7I3KBZLgfr(&x> zO@kKJ{RT%J8q;CxPX@+&f@9%-8 zwMdlj;hQHhW5kYrsqvd%BN?#CZ|qv6)sUuPlLtd^C~sySZ21`aDM*V4*Xq$M!kc6X z=F7rnMMON9<%sV^TYsqc*W|%ozYOSS=0E?%bI5bq+{j12?(%hWZwIGWU~~Sv^_zpg U@igrie$T~JG|lh8T3wj_2H)EuI{*Lx literal 90 zcmazJD9X=DO)d$~FUl@1NK8(R<>e|U$%}W+$jnJGv~?>=%uOxk<%&jErU#KhRSnhz G(*gk2B_Im` From 32cb8b020604685de260626822cf0a2ebac53960 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 08:23:00 +0000 Subject: [PATCH 011/127] reformatted --- .../Interrupt_Handler/interrupt_handler.tdf | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf index a455469..5131b0f 100644 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -91,7 +91,7 @@ BEGIN # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL�SEN, 1=INT7 AUSL�SEN INT_CTR[].CLK = MAIN_CLK; INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 INT_CTR[] = FB_AD[]; @@ -324,9 +324,12 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; - PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; + + PIC_INT_SYNC[].CLK = MAIN_CLK; + PIC_INT_SYNC[0] = PIC_INT; PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; WERTE[6][10].CLRN = GND; -- KEIN UIP UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF @@ -334,7 +337,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); @@ -345,36 +348,36 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- TRISTATE OUTPUT From 489fb04b1611b15834e8a871b4efcda225209705 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Sun, 20 Sep 2015 12:24:45 +0000 Subject: [PATCH 012/127] get rid of generated files --- FPGA_Quartus_13.1/DSP/DSP.vhd.bak | 79 -- .../FalconIO_SDCard_IDE_CF.vhd.bak | 971 ------------------ .../FalconIO_SDCard_IDE_CF_pgk.vhd.bak | 406 -------- .../WF_SDC_IF/sd-card-interface_soc.vhd.bak | 239 ----- .../wf6850ip_ctrl_status.vhd.bak | 244 ----- .../WF_UART6850_IP/wf6850ip_receive.vhd.bak | 415 -------- .../WF_UART6850_IP/wf6850ip_top_soc.vhd.bak | 252 ----- .../WF_UART6850_IP/wf6850ip_transmit.vhd.bak | 339 ------ .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak | 202 ---- .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak | 202 ---- .../interrupt_handler.tdf.bak | 478 --------- .../Video/BLITTER/BLITTER.vhd.bak | 75 -- FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak | 660 ------------ .../Video/DDR_CTR_BLITTER.tdf.bak | 352 ------- .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak | 675 ------------ FPGA_Quartus_13.1/Video/altdpram0_wave0.jpg | Bin 125146 -> 0 bytes FPGA_Quartus_13.1/Video/altdpram0_wave1.jpg | Bin 171723 -> 0 bytes .../Video/altdpram0_waveforms.html | 16 - FPGA_Quartus_13.1/Video/altdpram1_wave0.jpg | Bin 151954 -> 0 bytes FPGA_Quartus_13.1/Video/altdpram1_wave1.jpg | Bin 203609 -> 0 bytes .../Video/altdpram1_waveforms.html | 16 - FPGA_Quartus_13.1/Video/altdpram2_wave0.jpg | Bin 152433 -> 0 bytes FPGA_Quartus_13.1/Video/altdpram2_wave1.jpg | Bin 204342 -> 0 bytes .../Video/altdpram2_waveforms.html | 16 - .../Video/lpm_compare1_wave0.jpg | Bin 30655 -> 0 bytes .../Video/lpm_compare1_waveforms.html | 13 - FPGA_Quartus_13.1/Video/lpm_fifoDZ_wave0.jpg | Bin 86257 -> 0 bytes .../Video/lpm_fifoDZ_waveforms.html | 13 - .../Video/lpm_fifo_dc0_wave0.jpg | Bin 121926 -> 0 bytes .../Video/lpm_fifo_dc0_waveforms.html | 13 - FPGA_Quartus_13.1/lpm_counter0_wave0.jpg | Bin 56372 -> 0 bytes 31 files changed, 5676 deletions(-) delete mode 100644 FPGA_Quartus_13.1/DSP/DSP.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak delete mode 100644 FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak delete mode 100644 FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak delete mode 100644 FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak delete mode 100644 FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak delete mode 100644 FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak delete mode 100644 FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak delete mode 100644 FPGA_Quartus_13.1/Video/altdpram0_wave0.jpg delete mode 100644 FPGA_Quartus_13.1/Video/altdpram0_wave1.jpg delete mode 100644 FPGA_Quartus_13.1/Video/altdpram0_waveforms.html delete mode 100644 FPGA_Quartus_13.1/Video/altdpram1_wave0.jpg delete mode 100644 FPGA_Quartus_13.1/Video/altdpram1_wave1.jpg delete mode 100644 FPGA_Quartus_13.1/Video/altdpram1_waveforms.html delete mode 100644 FPGA_Quartus_13.1/Video/altdpram2_wave0.jpg delete mode 100644 FPGA_Quartus_13.1/Video/altdpram2_wave1.jpg delete mode 100644 FPGA_Quartus_13.1/Video/altdpram2_waveforms.html delete mode 100644 FPGA_Quartus_13.1/Video/lpm_compare1_wave0.jpg delete mode 100644 FPGA_Quartus_13.1/Video/lpm_compare1_waveforms.html delete mode 100644 FPGA_Quartus_13.1/Video/lpm_fifoDZ_wave0.jpg delete mode 100644 FPGA_Quartus_13.1/Video/lpm_fifoDZ_waveforms.html delete mode 100644 FPGA_Quartus_13.1/Video/lpm_fifo_dc0_wave0.jpg delete mode 100644 FPGA_Quartus_13.1/Video/lpm_fifo_dc0_waveforms.html delete mode 100644 FPGA_Quartus_13.1/lpm_counter0_wave0.jpg diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd.bak b/FPGA_Quartus_13.1/DSP/DSP.vhd.bak deleted file mode 100644 index 2d4811a..0000000 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd.bak +++ /dev/null @@ -1,79 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:57 2009 - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration - -ENTITY DSP IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nRSTO : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - nSRCS : OUT STD_LOGIC; - nSRBLE : OUT STD_LOGIC; - nSRBHE : OUT STD_LOGIC; - nSRWE : OUT STD_LOGIC; - nSROE : OUT STD_LOGIC; - DSP_INT : OUT STD_LOGIC; - DSP_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - IO : INOUT STD_LOGIC_VECTOR(17 downto 0); - SRD : INOUT STD_LOGIC_VECTOR(15 downto 0) - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END DSP; - - --- Architecture Body - -ARCHITECTURE DSP_architecture OF DSP IS - - -BEGIN - nSRCS <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --nFB_CS3; - nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1'; - nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; - nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1'; - nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1'; - DSP_INT <= '0'; - DSP_TA <= '0'; - IO(17 downto 0) <= FB_ADR(18 downto 1); - SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; - - -END DSP_architecture; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak deleted file mode 100644 index a339eda..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak +++ /dev/null @@ -1,971 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Tue Sep 08 16:24:20 2009 - -library work; -use work.FalconIO_SDCard_IDE_CF_pkg.all; - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - - --- Entity Declaration - - --- Entity Declaration - -ENTITY FalconIO_SDCard_IDE_CF IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - CLK33M : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - CLK2M : IN STD_LOGIC; - CLK500k : IN STD_LOGIC; - nFB_CS1 : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - nFB_BURST : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - LP_BUSY : IN STD_LOGIC; - nACSI_DRQ : IN STD_LOGIC; - nACSI_INT : IN STD_LOGIC; - nSCSI_DRQ : IN STD_LOGIC; - nSCSI_MSG : IN STD_LOGIC; - MIDI_IN : IN STD_LOGIC; - RxD : IN STD_LOGIC; - CTS : IN STD_LOGIC; - RI : IN STD_LOGIC; - DCD : IN STD_LOGIC; - AMKB_RX : IN STD_LOGIC; - PIC_AMKB_RX : IN STD_LOGIC; - IDE_RDY : IN STD_LOGIC; - IDE_INT : IN STD_LOGIC; - WP_CS_CARD : IN STD_LOGIC; - nINDEX : IN STD_LOGIC; - TRACK00 : IN STD_LOGIC; - nRD_DATA : IN STD_LOGIC; - nDCHG : IN STD_LOGIC; - SD_DATA0 : IN STD_LOGIC; - SD_DATA1 : IN STD_LOGIC; - SD_DATA2 : IN STD_LOGIC; - SD_CARD_DEDECT : IN STD_LOGIC; - SD_WP : IN STD_LOGIC; - nDACK0 : IN STD_LOGIC; - nFB_WR : INOUT STD_LOGIC; - WP_CF_CARD : IN STD_LOGIC; - nWP : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nRSTO : IN STD_LOGIC; - HD_DD : IN STD_LOGIC; - nSCSI_C_D : IN STD_LOGIC; - nSCSI_I_O : IN STD_LOGIC; - CLK2M4576 : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - VSYNC : IN STD_LOGIC; - HSYNC : IN STD_LOGIC; - DSP_INT : IN STD_LOGIC; - nBLANK : IN STD_LOGIC; - FDC_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24); - nIDE_CS1 : OUT STD_LOGIC; - nIDE_CS0 : OUT STD_LOGIC; - LP_STR : OUT STD_LOGIC; - LP_DIR : OUT STD_LOGIC; - nACSI_ACK : OUT STD_LOGIC; - nACSI_RESET : OUT STD_LOGIC; - nACSI_CS : OUT STD_LOGIC; - ACSI_DIR : OUT STD_LOGIC; - ACSI_A1 : OUT STD_LOGIC; - nSCSI_ACK : OUT STD_LOGIC; - nSCSI_ATN : OUT STD_LOGIC; - SCSI_DIR : OUT STD_LOGIC; - SD_CLK : OUT STD_LOGIC; - YM_QA : OUT STD_LOGIC; - YM_QC : OUT STD_LOGIC; - YM_QB : OUT STD_LOGIC; - nSDSEL : OUT STD_LOGIC; - STEP : OUT STD_LOGIC; - MOT_ON : OUT STD_LOGIC; - nRP_LDS : OUT STD_LOGIC; - nRP_UDS : OUT STD_LOGIC; - nROM4 : OUT STD_LOGIC; - nROM3 : OUT STD_LOGIC; - nCF_CS1 : OUT STD_LOGIC; - nCF_CS0 : OUT STD_LOGIC; - nIDE_RD : INOUT STD_LOGIC; - nIDE_WR : INOUT STD_LOGIC; - AMKB_TX : OUT STD_LOGIC; - IDE_RES : OUT STD_LOGIC; - DTR : OUT STD_LOGIC; - RTS : OUT STD_LOGIC; - TxD : OUT STD_LOGIC; - MIDI_OLR : OUT STD_LOGIC; - MIDI_TLR : OUT STD_LOGIC; - nDREQ0 : OUT STD_LOGIC; - DSA_D : OUT STD_LOGIC; - nMFP_INT : OUT STD_LOGIC; - FALCON_IO_TA : OUT STD_LOGIC; - STEP_DIR : OUT STD_LOGIC; - WR_DATA : OUT STD_LOGIC; - WR_GATE : OUT STD_LOGIC; - DMA_DRQ : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0); - LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0); - SCSI_PAR : INOUT STD_LOGIC; - nSCSI_SEL : INOUT STD_LOGIC; - nSCSI_BUSY : INOUT STD_LOGIC; - nSCSI_RST : INOUT STD_LOGIC; - SD_CD_DATA3 : INOUT STD_LOGIC; - SD_CDM_D1 : INOUT STD_LOGIC - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END FalconIO_SDCard_IDE_CF; - - --- Architecture Body - -ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS --- system -signal SYS_CLK : STD_LOGIC; -signal RESETn : STD_LOGIC; -signal FB_B0 : STD_LOGIC; -- UPPER BYT BEI 16BIT BUS -signal FB_B1 : STD_LOGIC; -- LOWER BYT BEI 16BIT BUS -signal BYT : STD_LOGIC; -- WENN BYT -> 1 -signal LONG : STD_LOGIC; -- WENN -> 1 --- KEYBOARD MIDI -signal ACIA_CS_I : STD_LOGIC; -signal IRQ_KEYBDn : STD_LOGIC; -signal IRQ_MIDIn : STD_LOGIC; -signal KEYB_RxD : STD_LOGIC; -signal AMKB_REG : STD_LOGIC_VECTOR(4 downto 0); -signal MIDI_OUT : STD_LOGIC; -signal DATA_OUT_ACIA_I : STD_LOGIC_VECTOR(7 downto 0); -signal DATA_OUT_ACIA_II : STD_LOGIC_VECTOR(7 downto 0); --- MFP -signal MFP_CS : STD_LOGIC; -signal MFP_INTACK : STD_LOGIC; -signal LDS : STD_LOGIC; -signal DTACK_OUT_MFPn : STD_LOGIC; -signal IRQ_ACIAn : STD_LOGIC; -signal DINTn : STD_LOGIC; -signal DATA_OUT_MFP : STD_LOGIC_VECTOR(7 downto 0); -signal TDO : STD_LOGIC; --- SOUND -signal SNDCS : STD_LOGIC; -signal SNDCS_I : STD_LOGIC; -signal SNDIR_I : STD_LOGIC; -signal LP_DIR_X : STD_LOGIC; -signal DA_OUT_X : STD_LOGIC_VECTOR(7 downto 0); -signal LP_D_X : STD_LOGIC_VECTOR(7 downto 0); --- DIV -signal SUB_BUS : STD_LOGIC; -- SUB BUS MIT ROM-PORT, CF UND IDE -signal ROM_CS : STD_LOGIC; --- DMA UND FLOPPY -signal DMA_DATEN_CS : STD_LOGIC; -signal DMA_MODUS_CS : STD_LOGIC; -signal DMA_MODUS : STD_LOGIC_VECTOR(15 downto 0); -signal WDC_BSL_CS : STD_LOGIC; -signal WDC_BSL : STD_LOGIC_VECTOR(1 DOWNTO 0); -signal HD_DD_OUT : STD_LOGIC; -signal FDCS_In : STD_LOGIC; -signal CA0 : STD_LOGIC; -signal CA1 : STD_LOGIC; -signal CA2 : STD_LOGIC; -signal FDINT : STD_LOGIC; -signal FDRQ : STD_LOGIC; -signal CD_OUT_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal CD_IN_FDC : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_TOP_CS : STD_LOGIC; -signal DMA_TOP : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_HIGH_CS : STD_LOGIC; -signal DMA_HIGH : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_MID_CS : STD_LOGIC; -signal DMA_MID : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_LOW_CS : STD_LOGIC; -signal DMA_LOW : STD_LOGIC_VECTOR(7 downto 0); -signal DMA_DIRM_CS : STD_LOGIC; -signal DMA_ADR_CS : STD_LOGIC; -signal DMA_STATUS : STD_LOGIC_VECTOR(2 downto 0); -signal DMA_DIR_OLD : STD_LOGIC; -signal DMA_BYT_CNT_CS : STD_LOGIC; -signal DMA_BYT_CNT : STD_LOGIC_VECTOR(31 downto 0); -signal CLR_FIFO : STD_LOGIC; -signal DMA_DRQ_I : STD_LOGIC; -signal DMA_DRQ_REG : STD_LOGIC_VECTOR(1 downto 0); -signal DMA_DRQQ : STD_LOGIC; -signal DMA_DRQ_Q : STD_LOGIC; -signal RDF_DOUT : STD_LOGIC_VECTOR(31 downto 0); -signal RDF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal RDF_RDE : STD_LOGIC; -signal RDF_WRE : STD_LOGIC; -signal RDF_DIN : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal WRF_AZ : STD_LOGIC_VECTOR(9 downto 0); -signal WRF_RDE : STD_LOGIC; -signal WRF_WRE : STD_LOGIC; -signal nFDC_WR : STD_LOGIC; -type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); -signal FCF_STATE : FCF_STATES; -signal NEXT_FCF_STATE : FCF_STATES; -signal DMA_REQ : STD_LOGIC; -signal FDC_CS : STD_LOGIC; -signal FCF_CS : STD_LOGIC; -signal FCF_APH : STD_LOGIC; -signal DMA_AZ_CS : STD_LOGIC; -signal DMA_ACTIV : STD_LOGIC; -signal DMA_ACTIV_NEW : STD_LOGIC; -signal FDC_OUT : STD_LOGIC_VECTOR(7 downto 0); --- SCSI -signal SCSI_CS : STD_LOGIC; -signal SCSI_CSn : STD_LOGIC; -signal SCSI_DOUT : STD_LOGIC_VECTOR(7 downto 0); -signal nSCSI_DACK : STD_LOGIC; -signal SCSI_DRQ : STD_LOGIC; -signal SCSI_INT : STD_LOGIC; -signal DB_OUTn : STD_LOGIC_VECTOR(7 downto 0); -signal DB_EN : STD_LOGIC; -signal DBP_OUTn : STD_LOGIC; -signal DBP_EN : STD_LOGIC; -signal RST_OUTn : STD_LOGIC; -signal RST_EN : STD_LOGIC; -signal BSY_OUTn : STD_LOGIC; -signal BSY_EN : STD_LOGIC; -signal SEL_OUTn : STD_LOGIC; -signal SEL_EN : STD_LOGIC; --- IDE -signal nnIDE_RES : STD_LOGIC; -signal IDE_CF_CS : STD_LOGIC; -signal IDE_CF_TA : STD_LOGIC; -signal NEXT_nIDE_RD : STD_LOGIC; -signal NEXT_nIDE_WR : STD_LOGIC; -type CMD_STATES is( IDLE, T1, T6, T7); -signal CMD_STATE : CMD_STATES; -signal NEXT_CMD_STATE : CMD_STATES; - - -BEGIN -LONG <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0'; -BYT <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; -FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0'; -FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0'; - -FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' - or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0'; -SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1' ELSE - '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE - '1' when nFB_WR = '0' and nIDE_WR = '0' ELSE '0'; -nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; -nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; -nDREQ0 <= '0'; ----------------------------------------------------------------------------- --- SD ----------------------------------------------------------------------------- -SD_CLK <= 'Z'; -SD_CD_DATA3 <= 'Z'; -SD_CDM_D1 <= 'Z'; ----------------------------------------------------------------------------- --- IDE ----------------------------------------------------------------------------- -CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE) - begin - if nRSTO = '0' then - CMD_STATE <= IDLE; - elsif rising_edge(MAIN_CLK) then - CMD_STATE <= NEXT_CMD_STATE; -- go to next - nIDE_RD <= NEXT_nIDE_RD; -- go to next - nIDE_WR <= NEXT_nIDE_WR; -- go to next - else - CMD_STATE <= CMD_STATE; -- halten - nIDE_RD <= nIDE_RD; -- halten - nIDE_WR <= nIDE_WR; -- halten - end if; - end process CMD_REG; - - CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA) - begin - case CMD_STATE is - when IDLE => - IDE_CF_TA <= '0'; - if IDE_CF_CS = '1' then - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T1; - else - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= IDLE; - end if; - when T1 => - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T6; - when T6 => - IF IDE_RDY = '1' then - IDE_CF_TA <= '1'; - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= T7; - else - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= not nFB_WR; - NEXT_nIDE_WR <= nFB_WR; - NEXT_CMD_STATE <= T6; - end if; - when T7 => - IDE_CF_TA <= '0'; - NEXT_nIDE_RD <= '1'; - NEXT_nIDE_WR <= '1'; - NEXT_CMD_STATE <= IDLE; - end case; - end process CMD_DECODER; - -IDE_RES <= not nnIDE_RES and nRSTO; -IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0'; -- FFF0'0000/80 -nCF_CS0 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else -- FFFO'0000-FFF0'001F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; -- FFFO'0040-FFF0'005F -nCF_CS1 <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else -- FFF0'0020-FFF0'003F - '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; -- FFFO'0060-FFF0'007F -nIDE_CS0 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else -- FFF0'0040-FFF0'005F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; -- FFFO'0000-FFF0'001F -nIDE_CS1 <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else -- FFF0'0060-FFF0'007F - '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; -- FFFO'0020-FFF0'003F ------------------------------------------------------------------------------------------------------------------------------------------ --- ACSI, SCSI UND FLOPPY WD1772 -------------------------------------------------------------------------------------------------------------------------------------------- --- daten read fifo - RDF: dcfifo0 - port map( - aclr => CLR_FIFO, - data => RDF_DIN, - rdclk => MAIN_CLK, - rdreq => RDF_RDE, - wrclk => FDC_CLK, - wrreq => RDF_WRE, - q => RDF_DOUT, - wrusedw => RDF_AZ - ); -FCF_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0'; -- F002'0110 LONG ONLY -FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0) = x"F0020110" and LONG = '1' else '0'; -- ADRESSPHASE F0020110 LONG ONLY -RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0'; -- AKTIVIEREN IN ADRESSPHASE -FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT; --- daten write fifo - WRF: dcfifo1 - port map( - aclr => CLR_FIFO, - data => FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24), - rdclk => FDC_CLK, - rdreq => WRF_RDE, - wrclk => MAIN_CLK, - wrreq => WRF_WRE, - q => WRF_DOUT, - rdusedw => WRF_AZ - ); -CD_IN_FDC <= WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); -- BEI DMA WRITE <-FIFO SONST <-FB -DMA_AZ_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0'; -- F002'010C LONG -FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) - begin - if nRSTO = '0' THEN - WRF_WRE <= '0'; - elsif rising_edge(MAIN_CLK) then - IF FCF_APH = '1' and nFB_WR = '0' then - WRF_WRE <= '1'; - else - WRF_WRE <= '0'; - end if; - else - WRF_WRE <= WRF_WRE; - end if; - END PROCESS; - -FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV) - begin - if nRSTO = '0' then - FCF_STATE <= FCF_IDLE; - DMA_ACTIV <= '0'; - elsif rising_edge(FDC_CLK) then - FCF_STATE <= NEXT_FCF_STATE; -- go to next - DMA_ACTIV <= DMA_ACTIV_NEW; - else - FCF_STATE <= FCF_STATE; -- halten - DMA_ACTIV <= DMA_ACTIV; - end if; - end process FCF_REG; - -FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC) - begin - if nRSTO = '0' then - FDC_OUT <= x"00"; - elsif rising_edge(FDC_CLK) and FDCS_In = '0' then - FDC_OUT <= CD_OUT_FDC; -- set - else - FDC_OUT <= FDC_OUT; -- halten - end if; - end process FDC_REG; - -DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0'; -FDC_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0'; -SCSI_CS <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0'; - - FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn) - begin - case FCF_STATE is - when FCF_IDLE => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - WRF_RDE <= '0'; - nSCSI_DACK <= '1'; - if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then - DMA_ACTIV_NEW <= DMA_REQ; - NEXT_FCF_STATE <= FCF_T0; - else - DMA_ACTIV_NEW <= '0'; - NEXT_FCF_STATE <= FCF_IDLE; - end if; - when FCF_T0 => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - nSCSI_DACK <= '1'; - DMA_ACTIV_NEW <= DMA_REQ; - WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO - if DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike? - NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start - else - NEXT_FCF_STATE <= FCF_T1; - end if; - when FCF_T1 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T2; - when FCF_T2 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T3; - when FCF_T3 => - RDF_WRE <= '0'; - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - NEXT_FCF_STATE <= FCF_T6; - when FCF_T6 => - WRF_RDE <= '0'; - DMA_ACTIV_NEW <= DMA_ACTIV; - SCSI_CSn <= not SCSI_CS; - FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3); - nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV; - RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO - NEXT_FCF_STATE <= FCF_T7; - when FCF_T7 => - SCSI_CSn <= '1'; - FDCS_In <= '1'; - RDF_WRE <= '0'; - WRF_RDE <= '0'; - nSCSI_DACK <= '1'; - DMA_ACTIV_NEW <= '0'; - if FDC_CS = '1' and DMA_REQ = '0' then - NEXT_FCF_STATE <= FCF_T7; - else - NEXT_FCF_STATE <= FCF_IDLE; - end if; - end case; - end process FCF_DECODER; - - I_FDC: WF1772IP_TOP_SOC - port map( - CLK => FDC_CLK, - RESETn => nRSTO, - CSn => FDCS_In, - RWn => nFDC_WR, - A1 => CA2, - A0 => CA1, - DATA_IN => CD_IN_FDC, - DATA_OUT => CD_OUT_FDC, --- DATA_EN => CD_EN_FDC, - RDn => nRD_DATA, - TR00n => TRACK00, - IPn => nINDEX, - WPRTn => nWP, - DDEn => '0', -- Fixed to MFM. - HDTYPE => HD_DD_OUT, - MO => MOT_ON, - WG => WR_GATE, - WD => WR_DATA, - STEP => STEP, - DIRC => STEP_DIR, - DRQ => DMA_DRQ_I, - INTRQ => FDINT - ); -DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0'; -- F8604/2 -DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0'; -- F8606/2 -WDC_BSL_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0'; -- F860E/2 -HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); -nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR; -CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0); -CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1); -CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2); -FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else - SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else - DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ---- WDC BSL REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN - WDC_BSL <= "00"; - elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then - IF FB_B0 = '1' THEN - WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); - else - WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); - end if; - end if; - END PROCESS; ---- DMA MODUS REGISTER ------------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) - begin - if nRSTO = '0' THEN - DMA_MODUS <= x"0000"; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then - IF FB_B0 = '1' THEN - DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24); - else - DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8); - end if; - IF FB_B1 = '1' THEN - DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16); - else - DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0); - end if; - else - DMA_MODUS <= DMA_MODUS; - end if; - END PROCESS; --- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- - process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) - begin - if nRSTO = '0' or CLR_FIFO = '1' THEN - DMA_BYT_CNT <= x"00000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then - DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16); - DMA_BYT_CNT(8 downto 0) <= "000000000"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then - DMA_BYT_CNT <= FB_AD; - else - DMA_BYT_CNT <= DMA_BYT_CNT; - end if; - END PROCESS; --------------------------------------------------------------------- -FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -DMA_STATUS(0) <= '1'; -- DMA OK -DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0'; -- WENN byts UND NICHT MINUS -DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; -DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' else - '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0'; -DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0'; --- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ - process(FDC_CLK, nRSTO, DMA_DRQ_REG) - begin - if nRSTO = '0' THEN - DMA_DRQ_REG <= "00"; - elsif rising_edge(FDC_CLK) then - DMA_DRQ_REG(0) <= DMA_DRQQ; - DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ; - else - DMA_DRQ_REG <= DMA_DRQ_REG; - end if; - END PROCESS; --- DMA ADRESSE ------------------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN - DMA_TOP <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then - DMA_TOP <= FB_AD(31 downto 24); - else - DMA_TOP <= DMA_TOP; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) - begin - if nRSTO = '0' THEN - DMA_HIGH <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then - DMA_HIGH <= FB_AD(23 downto 16); - else - DMA_HIGH <= DMA_HIGH; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) - begin - DMA_MID <= DMA_MID; - if nRSTO = '0' THEN - DMA_MID <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_MID_CS = '1' then - DMA_MID <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_MID <= FB_AD(15 downto 8); - end if; - end if; - END PROCESS; - process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) - begin - DMA_LOW <= DMA_LOW; - if nRSTO = '0' THEN - DMA_LOW <= x"00"; - elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then - if DMA_LOW_CS = '1'then - DMA_LOW <= FB_AD(23 downto 16); - elsif DMA_ADR_CS = '1' then - DMA_LOW <= FB_AD(7 downto 0); - end if; - end if; - END PROCESS; --------------------------------------------------------------------------------------------- -DMA_TOP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0'; -- F8608/2 -DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0'; -- F8609/2 -DMA_MID_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0'; -- F860B/2 -DMA_LOW_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0'; -- F860D/2 -FB_AD(31 downto 24) <= DMA_TOP when DMA_TOP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_MID when DMA_MID_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(23 downto 16) <= DMA_LOW when DMA_LOW_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- DIRECTZUGRIFF -DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20100" else '0'; -- F002'0100 WORD -DMA_ADR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20104" else '0'; -- F002'0104 LONG -DMA_BYT_CNT_CS <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0'; -- F002'0108 LONG -FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; -FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; --- DMA RW TOGGLE ------------------------------------------ - process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) - begin - if nRSTO = '0' THEN - DMA_DIR_OLD <= '0'; - elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' then - DMA_DIR_OLD <= DMA_MODUS(8); - else - DMA_DIR_OLD <= DMA_DIR_OLD; - end if; - END PROCESS; -CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD; --- SCSI ---------------------------------------------------------------------------------- - I_SCSI: WF5380_TOP_SOC - port map( - CLK => FDC_CLK, - RESETn => nRSTO, - ADR => CA2 & CA1 & CA0, - DATA_IN => CD_IN_FDC, - DATA_OUT => SCSI_DOUT, - --DATA_EN : out bit; - -- Bus and DMA controls: - CSn => '1', --SCSI_CSn, ABGESCHALTET - RDn => (not nFDC_WR) or (not SCSI_CS), - WRn => nFDC_WR or (not SCSI_CS), - EOPn => '1', - DACKn => nSCSI_DACK, - DRQ => SCSI_DRQ, - INT => SCSI_INT, --- READY => - -- SCSI bus: - DB_INn => SCSI_D, - DB_OUTn => DB_OUTn, - DB_EN => DB_EN, - DBP_INn => SCSI_PAR, - DBP_OUTn => DBP_OUTn, - DBP_EN => DBP_EN, -- wenn 1 dann output - RST_INn => nSCSI_RST, - RST_OUTn => RST_OUTn, - RST_EN => RST_EN, - BSY_INn => nSCSI_BUSY, - BSY_OUTn => BSY_OUTn, - BSY_EN => BSY_EN, - SEL_INn => nSCSI_SEL, - SEL_OUTn => SEL_OUTn, - SEL_EN => SEL_EN, - ACK_INn => '1', - ACK_OUTn => nSCSI_ACK, --- ACK_EN => ACK_EN, - ATN_INn => '1', - ATN_OUTn => nSCSI_ATN, --- ATN_EN => ATN_EN, - REQ_INn => nSCSI_DRQ, --- REQ_OUTn => REQ_OUTn, --- REQ_EN => REQ_EN, - IOn_IN => nSCSI_I_O, --- IOn_OUT => IOn_OUT, --- IO_EN => IO_EN, - CDn_IN => nSCSI_C_D, --- CDn_OUT => CDn_OUT, --- CD_EN => CD_EN, - MSG_INn => nSCSI_MSG --- MSG_OUTn => MSG_OUTn, --- MSG_EN => MSG_EN - ); --- SCSI ACSI --------------------------------------------------------------- -SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; -SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1'; --ABGESCHALTET -SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z'; -nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z'; -nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z'; -nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z'; -ACSI_DIR <= '0'; -ACSI_D <= "ZZZZZZZZ"; -nACSI_CS <= '1'; -ACSI_A1 <= CA1; -nACSI_RESET <= nRSTO; -nACSI_ACK <= '1'; ----------------------------------------------------------------------------- --- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ----------------------------------------------------------------------------- -ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0'; -- FFF A'0000/2'0000 -nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1'; -nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1'; ----------------------------------------------------------------------------- --- ACIA KEYBOARD ----------------------------------------------------------------------------- - I_ACIA_KEYBOARD: WF6850IP_TOP_SOC - port map( - CLK => MAIN_CLK, - RESETn => nRSTO, - - CS2n => FB_ADR(2), - CS1 => '1', - CS0 => ACIA_CS_I, - E => ACIA_CS_I, - RWn => nFB_WR, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_I, --- DATA_EN => DATA_EN_ACIA_I, - - TXCLK => CLK500k, - RXCLK => CLK500k, - RXDATA => KEYB_RxD, - - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_KEYBDn, - TXDATA => AMKB_TX - --RTSn => -- Not used. - ); -ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0'; -- FFC00-FFC07 FFC00/8 -KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL -FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ"; --- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ - process(CLK2M, AMKB_RX, AMKB_REG) - begin - if rising_edge(CLK2M) then - IF AMKB_RX = '0' THEN - IF AMKB_REG < 16 THEN - AMKB_REG <= "00000"; - ELSE - AMKB_REG <= AMKB_REG - 1; - END IF; - ELSE - IF AMKB_REG > 15 THEN - AMKB_REG <= "11111"; - ELSE - AMKB_REG <= AMKB_REG + 1; - END IF; - END IF; - ELSE - AMKB_REG <= AMKB_REG; - end if; - END PROCESS; ----------------------------------------------------------------------------- --- ACIA MIDI ----------------------------------------------------------------------------- - I_ACIA_MIDI: WF6850IP_TOP_SOC - port map( - CLK => MAIN_CLK, - RESETn => nRSTO, - - CS2n => '0', - CS1 => FB_ADR(2), - CS0 => ACIA_CS_I, - E => ACIA_CS_I, - RWn => nFB_WR, - RS => FB_ADR(1), - - DATA_IN => FB_AD(31 downto 24), - DATA_OUT => DATA_OUT_ACIA_II, --- DATA_EN => DATA_EN_ACIA_II, - - TXCLK => CLK500k, - RXCLK => CLK500k, - RXDATA => MIDI_IN, - CTSn => '0', - DCDn => '0', - - IRQn => IRQ_MIDIn, - TXDATA => MIDI_OUT - --RTSn => -- Not used. - ); -MIDI_TLR <= MIDI_OUT; -MIDI_OLR <= MIDI_OUT; -FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; ----------------------------------------------------------------------------- --- MFP ----------------------------------------------------------------------------- - I_MFP: WF68901IP_TOP_SOC - port map( - -- System control: - CLK => MAIN_CLK, - RESETn => nRSTO, - -- Asynchronous bus control: - DSn => not LDS, - CSn => not MFP_CS, - RWn => nFB_WR, - DTACKn => DTACK_OUT_MFPn, - -- Data and Adresses: - RS => FB_ADR(5 downto 1), - DATA_IN => FB_AD(23 downto 16), - DATA_OUT => DATA_OUT_MFP, --- DATA_EN => DATA_EN_MFP, - GPIP_IN(7) => not DMA_DRQ_Q, - GPIP_IN(6) => not RI, - GPIP_IN(5) => DINTn, - GPIP_IN(4) => IRQ_ACIAn, - GPIP_IN(3) => DSP_INT, - GPIP_IN(2) => not CTS, - GPIP_IN(1) => not DCD, - GPIP_IN(0) => LP_BUSY, - -- GPIP_OUT =>, -- Not used; all GPIPs are direction input. - -- GPIP_EN =>, -- Not used; all GPIPs are direction input. - -- Interrupt control: - IACKn => not MFP_INTACK, - IEIn => '0', - -- IEOn =>, -- Not used. - IRQn => nMFP_INT, - -- Timers and timer control: - XTAL1 => CLK2M4576, - TAI => '0', - TBI => nBLANK, - -- TAO =>, - -- TBO =>, - -- TCO =>, - TDO => TDO, - -- Serial I/O control: - RC => TDO, - TC => TDO, - SI => RxD, - SO => TxD - -- SO_EN => MFP_SO_EN - -- DMA control: - -- RRn =>, - -- TRn => - ); - -MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0'; -- FFA00/40 -MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; --F002'0000 -LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0'; -FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ"; -FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ"; -DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else - '0' when FDINT = '1' else - '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1'; --- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn) - begin - if nRSTO = '0' THEN - IRQ_ACIAn <= '1'; - elsif rising_edge(MAIN_CLK) then - IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn; - else - IRQ_ACIAn <= IRQ_ACIAn; - end if; - END PROCESS; ----------------------------------------------------------------------------- --- Sound ----------------------------------------------------------------------------- - I_SOUND: WF2149IP_TOP_SOC - port map( - SYS_CLK => MAIN_CLK, - RESETn => nRSTO, - - WAV_CLK => CLK2M, - SELn => '1', - - BDIR => SNDIR_I, - BC2 => '1', - BC1 => SNDCS_I, - - A9n => '0', - A8 => '1', - DA_IN => FB_AD(31 downto 24), - DA_OUT => DA_OUT_X, - - IO_A_IN => x"00", -- All port pins are dedicated outputs. - IO_A_OUT(7) => nnIDE_RES, - IO_A_OUT(6) => LP_DIR_X, - IO_A_OUT(5) => LP_STR, - IO_A_OUT(4) => DTR, - IO_A_OUT(3) => RTS, --- IO_A_OUT(2) => FDD_D1SEL, - IO_A_OUT(1) => DSA_D, - IO_A_OUT(0) => nSDSEL, - -- IO_A_EN =>, -- Not required. - IO_B_IN => LP_D, - IO_B_OUT => LP_D_X, - -- IO_B_EN => IO_B_EN, - - OUT_A => YM_QA, - OUT_B => YM_QB, - OUT_C => YM_QC - ); - -SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0'; -- 8800-8803 F8800/4 -SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0'; -SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0'; -FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ"; -LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ"; -LP_DIR <= LP_DIR_X; - -END FalconIO_SDCard_IDE_CF_architecture; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak deleted file mode 100644 index 4f42cf2..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak +++ /dev/null @@ -1,406 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- Atari Coldfire IP Core ---- ----- ---- ----- This file is part of the Atari Coldfire project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- ---- ----- ---- ----- ---- ----- ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2009 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- 1.0 Initial Release, 20090925. --- - -library ieee; -use ieee.std_logic_1164.all; - -package FalconIO_SDCard_IDE_CF_PKG is - component WF25915IP_TOP_V1_SOC -- GLUE. - port ( - -- Clock system: - GL_CLK : in std_logic; -- Originally 8MHz. - GL_CLK_016 : in std_logic; -- One sixteenth of GL_CLK. - - -- Core address select: - GL_ROMSEL_FC_E0n : in std_logic; - EN_RAM_14MB : in std_logic; - -- Adress decoder outputs: - GL_ROM_6n : out std_logic; -- STE. - GL_ROM_5n : out std_logic; -- STE. - GL_ROM_4n : out std_logic; -- ST. - GL_ROM_3n : out std_logic; -- ST. - GL_ROM_2n : out std_logic; - GL_ROM_1n : out std_logic; - GL_ROM_0n : out std_logic; - - GL_ACIACS : out std_logic; - GL_MFPCSn : out std_logic; - GL_SNDCSn : out std_logic; - GL_FCSn : out std_logic; - - GL_STE_SNDCS : out std_logic; -- STE: Sound chip select. - GL_STE_SNDIR : out std_logic; -- STE: Data flow direction control. - - GL_STE_RTCCSn : out std_logic; --STE only. - GL_STE_RTC_WRn : out std_logic; --STE only. - GL_STE_RTC_RDn : out std_logic; --STE only. - - -- 6800 peripheral control, - GL_VPAn : out std_logic; - GL_VMAn : in std_logic; - - GL_DMA_SYNC : in std_logic; - GL_DEVn : out std_logic; - GL_RAMn : out std_logic; - GL_DMAn : out std_logic; - - -- Interrupt system: - -- Comment out GL_AVECn for CPUs which do not provide the VMAn signal. - GL_AVECn : out std_logic; - GL_STE_FDINT : in std_logic; -- Floppy disk interrupt; STE only. - GL_STE_HDINTn : in std_logic; -- Hard disk interrupt; STE only. - GL_MFPINTn : in std_logic; -- ST. - GL_STE_EINT3n : in std_logic; --STE only. - GL_STE_EINT5n : in std_logic; --STE only. - GL_STE_EINT7n : in std_logic; --STE only. - GL_STE_DINTn : out std_logic; -- Disk interrupt (floppy or hard disk); STE only. - GL_IACKn : out std_logic; -- ST. - GL_STE_IPL2n : out std_logic; --STE only. - GL_STE_IPL1n : out std_logic; --STE only. - GL_STE_IPL0n : out std_logic; --STE only. - - -- Video timing: - GL_BLANKn : out std_logic; - GL_DE : out std_logic; - GL_MULTISYNC : in std_logic_vector(3 downto 2); - GL_VIDEO_HIMODE : out std_logic; - GL_HSYNC_INn : in std_logic; - GL_HSYNC_OUTn : out std_logic; - GL_VSYNC_INn : in std_logic; - GL_VSYNC_OUTn : out std_logic; - GL_SYNC_OUT_EN : out std_logic; - - -- Bus arstd_logicration control: - GL_RDY_INn : in std_logic; - GL_RDY_OUTn : out std_logic; - GL_BRn : out std_logic; - GL_BGIn : in std_logic; - GL_BGOn : out std_logic; - GL_BGACK_INn : in std_logic; - GL_BGACK_OUTn : out std_logic; - - -- Adress and data bus: - GL_ADDRESS : in std_logic_vector(23 downto 1); - -- ST: put the data bus to 1 downto 0. - -- STE: put the data out bus to 15 downto 0. - GL_DATA_IN : in std_logic_vector(7 downto 0); - GL_DATA_OUT : out std_logic_vector(15 downto 0); - GL_DATA_EN : out std_logic; - - -- Asynchronous bus control: - GL_RWn_IN : in std_logic; - GL_RWn_OUT : out std_logic; - GL_AS_INn : in std_logic; - GL_AS_OUTn : out std_logic; - GL_UDS_INn : in std_logic; - GL_UDS_OUTn : out std_logic; - GL_LDS_INn : in std_logic; - GL_LDS_OUTn : out std_logic; - GL_DTACK_INn : in std_logic; - GL_DTACK_OUTn : out std_logic; - GL_CTRL_EN : out std_logic; - - -- System control: - GL_RESETn : in std_logic; - GL_BERRn : out std_logic; - - -- Processor function codes: - GL_FC : in std_logic_vector(2 downto 0); - - -- STE enhancements: - GL_STE_FDDS : out std_logic; -- Floppy type select (HD or DD). - GL_STE_FCCLK : out std_logic; -- Floppy controller clock select. - GL_STE_JOY_RHn : out std_logic; -- Read only FF9202 high byte. - GL_STE_JOY_RLn : out std_logic; -- Read only FF9202 low byte. - GL_STE_JOY_WL : out std_logic; -- Write only FF9202 low byte. - GL_STE_JOY_WEn : out std_logic; -- Write only FF9202 output enable. - GL_STE_BUTTONn : out std_logic; -- Read only FF9000 low byte. - GL_STE_PAD0Xn : in std_logic; -- Counter input for the Paddle 0X. - GL_STE_PAD0Yn : in std_logic; -- Counter input for the Paddle 0Y. - GL_STE_PAD1Xn : in std_logic; -- Counter input for the Paddle 1X. - GL_STE_PAD1Yn : in std_logic; -- Counter input for the Paddle 1Y. - GL_STE_PADRSTn : out std_logic; -- Paddle monoflops reset. - GL_STE_PENn : in std_logic; -- Input of the light pen. - GL_STE_SCCn : out std_logic; -- Select signal for the STE or TT SCC chip. - GL_STE_CPROGn : out std_logic -- Select signal for the STE's cache processor. - ); - end component WF25915IP_TOP_V1_SOC; - - component WF5380_TOP_SOC - port ( - CLK : in std_logic; - RESETn : in std_logic; - ADR : in std_logic_vector(2 downto 0); - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - CSn : in std_logic; - RDn : in std_logic; - WRn : in std_logic; - EOPn : in std_logic; - DACKn : in std_logic; - DRQ : out std_logic; - INT : out std_logic; - READY : out std_logic; - DB_INn : in std_logic_vector(7 downto 0); - DB_OUTn : out std_logic_vector(7 downto 0); - DB_EN : out std_logic; - DBP_INn : in std_logic; - DBP_OUTn : out std_logic; - DBP_EN : out std_logic; - RST_INn : in std_logic; - RST_OUTn : out std_logic; - RST_EN : out std_logic; - BSY_INn : in std_logic; - BSY_OUTn : out std_logic; - BSY_EN : out std_logic; - SEL_INn : in std_logic; - SEL_OUTn : out std_logic; - SEL_EN : out std_logic; - ACK_INn : in std_logic; - ACK_OUTn : out std_logic; - ACK_EN : out std_logic; - ATN_INn : in std_logic; - ATN_OUTn : out std_logic; - ATN_EN : out std_logic; - REQ_INn : in std_logic; - REQ_OUTn : out std_logic; - REQ_EN : out std_logic; - IOn_IN : in std_logic; - IOn_OUT : out std_logic; - IO_EN : out std_logic; - CDn_IN : in std_logic; - CDn_OUT : out std_logic; - CD_EN : out std_logic; - MSG_INn : in std_logic; - MSG_OUTn : out std_logic; - MSG_EN : out std_logic - ); - end component WF5380_TOP_SOC; - - component WF1772IP_TOP_SOC -- FDC. - port ( - CLK : in std_logic; -- 16MHz clock! - RESETn : in std_logic; - CSn : in std_logic; - RWn : in std_logic; - A1, A0 : in std_logic; - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - RDn : in std_logic; - TR00n : in std_logic; - IPn : in std_logic; - WPRTn : in std_logic; - DDEn : in std_logic; - HDTYPE : in std_logic; -- '0' = DD disks, '1' = HD disks. - MO : out std_logic; - WG : out std_logic; - WD : out std_logic; - STEP : out std_logic; - DIRC : out std_logic; - DRQ : out std_logic; - INTRQ : out std_logic - ); - end component WF1772IP_TOP_SOC; - - component WF68901IP_TOP_SOC -- MFP. - port ( -- System control: - CLK : in std_logic; - RESETn : in std_logic; - - -- Asynchronous bus control: - DSn : in std_logic; - CSn : in std_logic; - RWn : in std_logic; - DTACKn : out std_logic; - - -- Data and Adresses: - RS : in std_logic_vector(5 downto 1); - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - GPIP_IN : in std_logic_vector(7 downto 0); - GPIP_OUT : out std_logic_vector(7 downto 0); - GPIP_EN : out std_logic_vector(7 downto 0); - - -- Interrupt control: - IACKn : in std_logic; - IEIn : in std_logic; - IEOn : out std_logic; - IRQn : out std_logic; - - -- Timers and timer control: - XTAL1 : in std_logic; -- Use an oszillator instead of a quartz. - TAI : in std_logic; - TBI : in std_logic; - TAO : out std_logic; - TBO : out std_logic; - TCO : out std_logic; - TDO : out std_logic; - - -- Serial I/O control: - RC : in std_logic; - TC : in std_logic; - SI : in std_logic; - SO : out std_logic; - SO_EN : out std_logic; - - -- DMA control: - RRn : out std_logic; - TRn : out std_logic - ); - end component WF68901IP_TOP_SOC; - - component WF2149IP_TOP_SOC -- Sound. - port( - - SYS_CLK : in std_logic; -- Read the inforation in the header! - RESETn : in std_logic; - - WAV_CLK : in std_logic; -- Read the inforation in the header! - SELn : in std_logic; - - BDIR : in std_logic; - BC2, BC1 : in std_logic; - - A9n, A8 : in std_logic; - DA_IN : in std_logic_vector(7 downto 0); - DA_OUT : out std_logic_vector(7 downto 0); - DA_EN : out std_logic; - - IO_A_IN : in std_logic_vector(7 downto 0); - IO_A_OUT : out std_logic_vector(7 downto 0); - IO_A_EN : out std_logic; - IO_B_IN : in std_logic_vector(7 downto 0); - IO_B_OUT : out std_logic_vector(7 downto 0); - IO_B_EN : out std_logic; - - OUT_A : out std_logic; -- Analog (PWM) outputs. - OUT_B : out std_logic; - OUT_C : out std_logic - ); - end component WF2149IP_TOP_SOC; - - component WF6850IP_TOP_SOC -- ACIA. - port ( - CLK : in std_logic; - RESETn : in std_logic; - - CS2n, CS1, CS0 : in std_logic; - E : in std_logic; - RWn : in std_logic; - RS : in std_logic; - - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out std_logic; - - TXCLK : in std_logic; - RXCLK : in std_logic; - RXDATA : in std_logic; - CTSn : in std_logic; - DCDn : in std_logic; - - IRQn : out std_logic; - TXDATA : out std_logic; - RTSn : out std_logic - ); - end component WF6850IP_TOP_SOC; - - component WF_SD_CARD - port ( - RESETn : in std_logic; - CLK : in std_logic; - ACSI_A1 : in std_logic; - ACSI_CSn : in std_logic; - ACSI_ACKn : in std_logic; - ACSI_INTn : out std_logic; - ACSI_DRQn : out std_logic; - ACSI_D_IN : in std_logic_vector(7 downto 0); - ACSI_D_OUT : out std_logic_vector(7 downto 0); - ACSI_D_EN : out std_logic; - MC_DO : in std_logic; - MC_PIO_DMAn : in std_logic; - MC_RWn : in std_logic; - MC_CLR_CMD : in std_logic; - MC_DONE : out std_logic; - MC_GOT_CMD : out std_logic; - MC_D_IN : in std_logic_vector(7 downto 0); - MC_D_OUT : out std_logic_vector(7 downto 0); - MC_D_EN : out std_logic - ); - end component WF_SD_CARD; - - component dcfifo0 - PORT ( - aclr : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) - ); - end component dcfifo0; - - component dcfifo1 - PORT ( - aclr : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - rdusedw : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) - ); - end component; - - -end FalconIO_SDCard_IDE_CF_PKG; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak deleted file mode 100644 index 0200dea..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak +++ /dev/null @@ -1,239 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- ATARI IP Core peripheral Add-On ---- ----- ---- ----- This file is part of the FPGA-ATARI project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- This hardware provides an interface to connect to a SD-Card. ---- ----- ---- ----- This interface is based on the project 'SatanDisk' of ---- ----- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- ----- the original code, written in VERILOG. It is provided for ---- ----- the use in a system on programmable chips (SOPC). ---- ----- ---- ----- Timing: Use a clock frequency of 16MHz for this component. ---- ----- Use the same clock frequency for the connected AVR ---- ----- microcontroller. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- ----- This hardware works with the original ATARI ---- ----- hard dik driver. ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K7A 2007/01/05 WF --- Initial Release. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF_SD_CARD is - port ( - -- System: - RESETn : in bit; - CLK : in bit; -- 16MHz, see above. - - -- ACSI section: - ACSI_A1 : in bit; - ACSI_CSn : in bit; - ACSI_ACKn : in bit; - ACSI_INTn : out bit; - ACSI_DRQn : out bit; - ACSI_D_IN : in std_logic_vector(7 downto 0); - ACSI_D_OUT : out std_logic_vector(7 downto 0); - ACSI_D_EN : out bit; - - -- Microcontroller interface: - MC_DO : in bit; - MC_PIO_DMAn : in bit; - MC_RWn : in bit; - MC_CLR_CMD : in bit; - MC_DONE : out bit; - MC_GOT_CMD : out bit; - MC_D_IN : in std_logic_vector(7 downto 0); - MC_D_OUT : out std_logic_vector(7 downto 0); - MC_D_EN : out bit - ); -end WF_SD_CARD; - -architecture BEHAVIOR of WF_SD_CARD is -signal DATA_REG : std_logic_vector(7 downto 0); -signal D0_REG : bit; -signal INT_REG : bit; -signal DRQ_REG : bit; -signal DONE_REG : bit; -signal GOT_CMD_REG : bit; -signal HOLD : bit; -signal PREV_CSn : bit; -signal PREV_ACKn : bit; -begin - MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); - MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; - ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); --- ???: ---ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; -ACSI_D_EN <= '0'; - ACSI_INTn <= INT_REG; - ACSI_DRQn <= DRQ_REG; - MC_DONE <= DONE_REG; - MC_GOT_CMD <= GOT_CMD_REG; - - P_DATA: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= (others => '0'); - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then - DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. - end if; - -- - if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then - DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. - elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then - DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. - end if; - end if; - end process P_DATA; - - P_SYNC: process - begin - wait until CLK = '1' and CLK' event; - PREV_CSn <= ACSI_CSn; - PREV_ACKn <= ACSI_ACKn; - end process P_SYNC; - - P_INT_DRQ: process(RESETn, CLK) - begin - if RESETn = '0' then - INT_REG <= '1'; -- No interrupt. - DRQ_REG <= '1'; -- No data request. - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. - INT_REG <= '0'; -- Release an interrupt. - DRQ_REG <= '1'; - elsif D0_REG = '0' and MC_DO = '1' then - INT_REG <= '1'; - DRQ_REG <= '0'; -- Release a data request. - end if; - -- - if MC_CLR_CMD = '1' then -- Clear done. - INT_REG <= '1'; -- Restore INT_REG. - DRQ_REG <= '1'; -- Restore DRQ_REG. - end if; - -- - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - if ACSI_CSn = '0' then - INT_REG <= '1'; - end if; - -- - if ACSI_ACKn = '0' then - DRQ_REG <= '1'; - end if; - end if; - end if; - end process P_INT_DRQ; - - P_HOLD: process(RESETn, CLK) - begin - if RESETn = '0' then - HOLD <= '0'; - elsif CLK = '1' and CLK' event then - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - HOLD <= '1'; - elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. - HOLD <= '0'; - elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. - HOLD <= '0'; - elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. - HOLD <= '1'; - elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. - HOLD <= '1'; - elsif MC_CLR_CMD = '1' then -- Clear done. - HOLD <= '0'; - end if; - end if; - end process P_HOLD; - - P_DONE: process(RESETn, CLK) - begin - if RESETn = '0' then - DONE_REG <= '0'; - elsif CLK = '1' and CLK' event then - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - DONE_REG <= '1'; - elsif MC_CLR_CMD = '1' then -- Clear done. - DONE_REG <= '0'; - elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. - DONE_REG <= '0'; - elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. - DONE_REG <= '0'; - end if; - end if; - end process P_DONE; - - P_DO_REG: process(RESETn, CLK) - begin - if RESETn = '0' then - D0_REG <= '0'; - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. - D0_REG <= MC_DO; - elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. - D0_REG <= MC_DO; - end if; - end if; - end process P_DO_REG; - - P_GOT_CMD: process(RESETn, CLK) - begin - if RESETn = '0' then - GOT_CMD_REG <= '0'; - elsif CLK = '1' and CLK' event then --- ?? ACSI_CSn doppelt! ---if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then - GOT_CMD_REG <= '1'; -- If command was received. - elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then - GOT_CMD_REG <= '1'; -- If command was received. - elsif MC_CLR_CMD = '1' then -- Clear done. - GOT_CMD_REG <= '0'; - end if; - end if; - end process P_GOT_CMD; -end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak deleted file mode 100644 index a0ea9e4..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak +++ /dev/null @@ -1,244 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- Control unit and status logic. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- Revision 2K9A 2009/06/20 WF --- CTRL_REG has now synchronous reset to meet preset requirements. --- Process P_DCD has now synchronous reset to meet preset requirements. --- IRQ_In has now synchronous reset to meet preset requirement. --- Revision 2K9B 2009/12/24 WF --- Fixed the interrupt logic. --- Introduced a minor RTSn correction. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_CTRL_STATUS is - port ( - CLK : in bit; - RESETn : in bit; - - CS : in bit_vector(2 downto 0); -- Active if "011". - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - -- Status register stuff: - RDRF : in bit; -- Receive data register full. - TDRE : in bit; -- Transmit data register empty. - DCDn : in bit; -- Data carrier detect. - CTSn : in bit; -- Clear to send. - FE : in bit; -- Framing error. - OVR : in bit; -- Overrun error. - PE : in bit; -- Parity error. - - -- Control register stuff: - MCLR : buffer bit; -- Master clear (high active). - RTSn : out bit; -- Request to send. - CDS : out bit_vector(1 downto 0); -- Clock control. - WS : out bit_vector(2 downto 0); -- Word select. - TC : out bit_vector(1 downto 0); -- Transmit control. - IRQn : out bit -- Interrupt request. - ); -end entity WF6850IP_CTRL_STATUS; - -architecture BEHAVIOR of WF6850IP_CTRL_STATUS is -signal CTRL_REG : bit_vector(7 downto 0); -signal STATUS_REG : bit_vector(7 downto 0); -signal RIE : bit; -signal IRQ_I : bit; -signal CTS_In : bit; -signal DCD_In : bit; -signal DCD_FLAGn : bit; -begin - P_SAMPLE: process - begin - wait until CLK = '0' and CLK' event; - CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. - DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. - end process P_SAMPLE; - - STATUS_REG(7) <= IRQ_I; - STATUS_REG(6) <= PE; - STATUS_REG(5) <= OVR; - STATUS_REG(4) <= FE; - STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. - STATUS_REG(2) <= DCD_FLAGn; - STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. - STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. - - DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; - - MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; - RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; - - CDS <= CTRL_REG(1 downto 0); - WS <= CTRL_REG(4 downto 2); - TC <= CTRL_REG(6 downto 5); - RIE <= CTRL_REG(7); - - P_IRQ: process - variable DCD_OVR_LOCK : boolean; - variable DCD_LOCK : boolean; - variable DCD_TRANS : boolean; - begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - DCD_OVR_LOCK := false; - IRQn <= '1'; - IRQ_I <= '0'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then - DCD_OVR_LOCK := false; -- Enable reset by reading the status. - end if; - --- Clear interrupts when disabled. -if CTRL_REG(7) = '0' then - IRQn <= '1'; - IRQ_I <= '0'; -elsif CTRL_REG(6 downto 5) /= "01" then - IRQn <= '1'; - IRQ_I <= '0'; -end if; - - -- Transmitter interrupt: - if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then - IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by writing to the transmit data register. - end if; - - -- Receiver interrupts: - if RDRF = '1' and RIE = '1' and DCD_In = '0' then - IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by reading the receive data register. - end if; - - if OVR = '1' and RIE = '1' then - IRQn <= '0'; - IRQ_I <= '1'; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. - end if; - - if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then - IRQn <= '0'; - IRQ_I <= '1'; - -- DCD_TRANS is used to detect a low to high transition of DCDn. - DCD_TRANS := true; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. - elsif DCD_In = '0' then - DCD_TRANS := false; - end if; - - -- The reset of the IRQ status flag: - -- Clear by writing to the transmit data register. - -- Clear by reading the receive data register. - if CS = "011" and RS = '1' and E = '1' then - IRQ_I <= '0'; - end if; - end process P_IRQ; - - CONTROL: process - begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - CTRL_REG <= "01000000"; - elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then - CTRL_REG <= DATA_IN; - end if; - end process CONTROL; - - P_DCD: process - -- This process is some kind of tricky. Refer to the MC6850 data - -- sheet for more information. - variable READ_LOCK : boolean; - variable DCD_RELEASE : boolean; - begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - DCD_FLAGn <= '0'; -- This interrupt source must initialise low. - READ_LOCK := true; - DCD_RELEASE := false; - elsif MCLR = '1' then - DCD_FLAGn <= DCD_In; - READ_LOCK := true; - elsif DCD_In = '1' then - DCD_FLAGn <= '1'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then - READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then - -- Clear if receiver status register read access. - -- After data register has ben read and READ_LOCK again. - DCD_RELEASE := true; - READ_LOCK := true; - DCD_FLAGn <= DCD_In; - elsif DCD_In = '0' and DCD_RELEASE = true then - DCD_FLAGn <= '0'; - DCD_RELEASE := false; - end if; - end process P_DCD; -end architecture BEHAVIOR; - diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak deleted file mode 100644 index e8c82b2..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak +++ /dev/null @@ -1,415 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's receiver unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_RECEIVE is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - RXCLK : in bit; - RXDATA : in bit; - - RDRF : buffer bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end entity WF6850IP_RECEIVE; - -architecture BEHAVIOR of WF6850IP_RECEIVE is -type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); -signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; -signal RXDATA_I : bit; -signal RXDATA_S : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal CLK_STRB : bit; -signal BITCNT : std_logic_vector(2 downto 0); -begin - P_SAMPLE: process - -- This filter provides a synchronisation to the system - -- clock, even for random baud rates of the received data - -- stream. - variable FLT_TMP : integer range 0 to 2; - begin - wait until CLK = '1' and CLK' event; - -- - RXDATA_I <= RXDATA; - -- - if RXDATA_I = '1' and FLT_TMP < 2 then - FLT_TMP := FLT_TMP + 1; - elsif RXDATA_I = '1' then - RXDATA_S <= '1'; - elsif RXDATA_I = '0' and FLT_TMP > 0 then - FLT_TMP := FLT_TMP - 1; - elsif RXDATA_I = '0' then - RXDATA_S <= '0'; - end if; - end process P_SAMPLE; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- Divider off. - if RXCLK = '1' and STRB_LOCK = false then - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif RXCLK = '0' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif RCV_STATE = IDLE then - -- Preset the CLKDIV with the start delays. - if CDS = "01" then - CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. - elsif CDS = "10" then - CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. - end if; - CLK_STRB <= '0'; - else - if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - -- - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif RXCLK = '0' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - DATA_REG <= x"00"; - elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= '0' & SHIFT_REG(7 downto 1); - elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= SHIFT_REG; - end if; - end if; - end process DATAREG; ---DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); ---DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; -DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0'); -DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0'; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - SHIFT_REG <= x"00"; - elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then - SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process - begin - wait until CLK = '1' and CLK' event; - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif RCV_STATE /= SAMPLE then - BITCNT <= (others => '0'); - end if; - end process P_BITCNT; - - FRAME_ERR: process(RESETn, CLK) - -- This module detects a framing error - -- during stop bit 1 and stop bit 2. - variable FE_I: bit; - begin - if RESETn = '0' then - FE_I := '0'; - FE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - FE_I := '0'; - FE <= '0'; - elsif CLK_STRB = '1' then - if RCV_STATE = STOP1 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP2 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then - FE_I := '0'; -- Error resets when correct data appears. - end if; - end if; - if RCV_STATE = SYNC then - FE <= FE_I; -- Update the FE every SYNC time. - end if; - end if; - end process FRAME_ERR; - - OVERRUN: process(RESETn, CLK) - variable OVR_I : bit; - variable FIRST_READ : boolean; - begin - if RESETn = '0' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK_STRB = '1' and RCV_STATE = STOP1 then - -- Overrun appears if RDRF is '1' in this state. - OVR_I := RDRF; - end if; - if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then - -- If an overrun was detected, the concerning flag is - -- set when the valid data word in the receiver data - -- register is read. Thereafter the RDRF flag is reset - -- and the overrun disappears (OVR_I goes low) after - -- a second read (in time) of the receiver data register. - if FIRST_READ = false then - OVR <= '1'; - FIRST_READ := true; - else - OVR <= '0'; - FIRST_READ := false; - end if; - end if; - end if; - end process OVERRUN; - - PARITY_TEST: process(RESETn, CLK) - variable PAR_TMP : bit; - variable PE_I : bit; - begin - if RESETn = '0' then - PE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - PE <= '0'; - elsif CLK_STRB = '1' then -- Sample parity on clock strobe. - PE_I := '0'; -- Initialise. - if RCV_STATE = PARITY then - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PE_I := PAR_TMP xor RXDATA_S; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PE_I := not PAR_TMP xor RXDATA_S; - else -- No parity for WS = "100" and WS = "101". - PE_I := '0'; - end if; - end if; - end if; - -- Transmit the parity flag together with the data - -- In other words: no parity to the status register - -- when RDRF inhibits the data transfer to the - -- receiver data register. - if RCV_STATE = SYNC and RDRF = '0' then - PE <= PE_I; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - PE <= '0'; -- Clear when reading the data register. - end if; - end if; - end process PARITY_TEST; - - P_RDRF: process(RESETn, CLK) - -- Receive data register full flag. - begin - if RESETn = '0' then - RDRF <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RDRF <= '0'; - elsif RCV_STATE = SYNC then - RDRF <= '1'; -- Data register is full until now! - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - RDRF <= '0'; -- After reading the data register ... - end if; - end if; - end process P_RDRF; - - RCV_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - RCV_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RCV_STATE <= IDLE; - else - RCV_STATE <= RCV_NEXT_STATE; - end if; - end if; - end process RCV_STATEREG; - - RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) - begin - case RCV_STATE is - when IDLE => - if RXDATA_S = '0' and CDS = "00" then - RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. - elsif RXDATA_S = '0' and CDS = "01" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. - elsif RXDATA_S = '0' and CDS = "10" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. - else - RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) - end if; - when WAIT_START => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. - else - RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. - end if; - else - RCV_NEXT_STATE <= WAIT_START; -- Stay. - end if; - when SAMPLE => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. - elsif WS = "100" or WS = "101" then - RCV_NEXT_STATE <= STOP1; -- No parity check enabled. - else - RCV_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. - end if; - when PARITY => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= STOP1; - else - RCV_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SYNC; -- Framing error detected. - elsif WS = "000" or WS = "001" or WS = "100" then - RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. - else - RCV_NEXT_STATE <= SYNC; -- One stop bit selected. - end if; - else - RCV_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= SYNC; - else - RCV_NEXT_STATE <= STOP2; - end if; - when SYNC => - RCV_NEXT_STATE <= IDLE; - end case; - end process RCV_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak deleted file mode 100644 index 6f80a67..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak +++ /dev/null @@ -1,252 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- This is the top level file. ---- ----- Top level file for use in systems on programmable chips. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Top level file provided for SOC (systems on programmable chips). --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_TOP_SOC is - port ( - CLK : in bit; - RESETn : in bit; - - CS2n, CS1, CS0 : in bit; - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out bit; - - TXCLK : in bit; - RXCLK : in bit; - RXDATA : in bit; - CTSn : in bit; - DCDn : in bit; - - IRQn : out bit; - TXDATA : out bit; - RTSn : out bit - ); -end entity WF6850IP_TOP_SOC; - -architecture STRUCTURE of WF6850IP_TOP_SOC is -component WF6850IP_CTRL_STATUS - port ( - CLK : in bit; - RESETn : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - RDRF : in bit; - TDRE : in bit; - DCDn : in bit; - CTSn : in bit; - FE : in bit; - OVR : in bit; - PE : in bit; - MCLR : out bit; - RTSn : out bit; - CDS : out bit_vector(1 downto 0); - WS : out bit_vector(2 downto 0); - TC : out bit_vector(1 downto 0); - IRQn : out bit - ); -end component; - -component WF6850IP_RECEIVE - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - RXCLK : in bit; - RXDATA : in bit; - RDRF : out bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end component; - -component WF6850IP_TRANSMIT - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - CTSn : in bit; - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - TXCLK : in bit; - TDRE : out bit; - TXDATA : out bit - ); -end component; -signal DATA_IN_I : bit_vector(7 downto 0); -signal DATA_RX : bit_vector(7 downto 0); -signal DATA_RX_EN : bit; -signal DATA_CTRL : bit_vector(7 downto 0); -signal DATA_CTRL_EN : bit; -signal RDRF_I : bit; -signal TDRE_I : bit; -signal FE_I : bit; -signal OVR_I : bit; -signal PE_I : bit; -signal MCLR_I : bit; -signal CDS_I : bit_vector(1 downto 0); -signal WS_I : bit_vector(2 downto 0); -signal TC_I : bit_vector(1 downto 0); -signal IRQ_In : bit; -begin - DATA_IN_I <= To_BitVector(DATA_IN); - DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; - DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else - To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); - - IRQn <= '0' when IRQ_In = '0' else '1'; - - I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS - port map( - CLK => CLK, - RESETn => RESETn, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_IN => DATA_IN_I, - DATA_OUT => DATA_CTRL, - DATA_EN => DATA_CTRL_EN, - RDRF => RDRF_I, - TDRE => TDRE_I, - DCDn => DCDn, - CTSn => CTSn, - FE => FE_I, - OVR => OVR_I, - PE => PE_I, - MCLR => MCLR_I, - RTSn => RTSn, - CDS => CDS_I, - WS => WS_I, - TC => TC_I, - IRQn => IRQ_In - ); - - I_UART_RECEIVE: WF6850IP_RECEIVE - port map ( - CLK => CLK, - RESETn => RESETn, - MCLR => MCLR_I, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_OUT => DATA_RX, - DATA_EN => DATA_RX_EN, - WS => WS_I, - CDS => CDS_I, - RXCLK => RXCLK, - RXDATA => RXDATA, - RDRF => RDRF_I, - OVR => OVR_I, - PE => PE_I, - FE => FE_I - ); - - I_UART_TRANSMIT: WF6850IP_TRANSMIT - port map ( - CLK => CLK, - RESETn => RESETn, - MCLR => MCLR_I, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_IN => DATA_IN_I, - CTSn => CTSn, - TC => TC_I, - WS => WS_I, - CDS => CDS_I, - TDRE => TDRE_I, - TXCLK => TXCLK, - TXDATA => TXDATA - ); -end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak deleted file mode 100644 index bcff094..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak +++ /dev/null @@ -1,339 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's transmitter unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- Revision 2K8B 2008/11/01 WF --- Fixed the T_DRE process concerning the TDRE <= '1' setting. --- Thanks to Lyndon Amsdon finding the bug. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_TRANSMIT is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in bit_vector(7 downto 0); - - CTSn : in bit; - - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - TXCLK : in bit; - - TDRE : buffer bit; - TXDATA : out bit - ); -end entity WF6850IP_TRANSMIT; - -architecture BEHAVIOR of WF6850IP_TRANSMIT is -type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); -signal TR_STATE, TR_NEXT_STATE : TR_STATES; -signal CLK_STRB : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal BITCNT : std_logic_vector(2 downto 0); -signal PARITY_I : bit; -begin - -- The default condition in this statement is to ensure - -- to cover all possibilities for example if there is a - -- one hot decoding of the state machine with wrong states - -- (e.g. not one of the given here). - TXDATA <= '1' when TR_STATE = IDLE else - '1' when TR_STATE = LOAD_SHFT else - '0' when TR_STATE = START else - SHIFT_REG(0) when TR_STATE = SHIFTOUT else - PARITY_I when TR_STATE = PARITY else - '1' when TR_STATE = STOP1 else - '1' when TR_STATE = STOP2 else '1'; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- divider off - if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif TXCLK = '1' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif TR_STATE = IDLE then - -- preset the CLKDIV with the start delays - if CDS = "01" then - CLK_DIVCNT := "0010000"; -- div by 16 mode - elsif CDS = "10" then - CLK_DIVCNT := "1000000"; -- div by 64 mode - end if; - CLK_STRB <= '0'; - else - -- Works on negative TXCLK edge: - if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif TXCLK = '1' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - DATA_REG <= x"00"; - elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then - DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. - elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then - DATA_REG <= DATA_IN; -- 8 bit data mode. - end if; - end if; - end process DATAREG; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - SHIFT_REG <= x"00"; - elsif TR_STATE = LOAD_SHFT and TDRE = '0' then - -- If during LOAD_SHIFT the transmitter data register - -- is empty (TDRE = '1') the shift register will not - -- be loaded. When additionally TC = "11", the break - -- character (zero data and no stop bits) is sent. - SHIFT_REG <= DATA_REG; - elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then - SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process - -- Counter for the data bits transmitted. - begin - wait until CLK = '1' and CLK' event; - if TR_STATE = SHIFTOUT and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif TR_STATE /= SHIFTOUT then - BITCNT <= "000"; - end if; - end process P_BITCNT; - - P_TDRE: process(RESETn, CLK) - -- Transmit data register empty flag. - variable LOCK : boolean; - begin - if RESETn = '0' then - TDRE <= '1'; - LOCK := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - TDRE <= '1'; - elsif TR_NEXT_STATE = START and TR_STATE /= START then - -- Data has been loaded to shift register, thus data register is free again. - -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once - -- entering the state now. - TDRE <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then - LOCK := true; - elsif E = '0' and LOCK = true and CS /= "011" then - -- This construction clears TDRE after the falling edge of E - -- and after the transmit data register has been written to. - TDRE <= '0'; - LOCK := false; - end if; - end if; - end process P_TDRE; - - PARITY_GEN: process - variable PAR_TMP : bit; - begin - wait until CLK = '1' and CLK' event; - if TR_STATE = START then -- Calculate the parity during the start phase. - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PARITY_I <= PAR_TMP; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PARITY_I <= not PAR_TMP; - else -- No parity for WS = "100" and WS = "101". - PARITY_I <= '0'; - end if; - end if; - end process PARITY_GEN; - - TR_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - TR_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - TR_STATE <= IDLE; - else - TR_STATE <= TR_NEXT_STATE; - end if; - end if; - end process TR_STATEREG; - - TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) - begin - case TR_STATE is - when IDLE => - if TDRE = '1' and TC = "11" then - TR_NEXT_STATE <= LOAD_SHFT; - elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. - TR_NEXT_STATE <= LOAD_SHFT; - else - TR_NEXT_STATE <= IDLE; - end if; - when LOAD_SHFT => - TR_NEXT_STATE <= START; - when START => - if CLK_STRB = '1' then - TR_NEXT_STATE <= SHIFTOUT; - else - TR_NEXT_STATE <= START; - end if; - when SHIFTOUT => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. - elsif WS = "100" or WS = "101" then - if TDRE = '1' and TC = "11" then - -- Break condition, do not send a stop bit. - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP1; -- No parity check enabled. - end if; - else - TR_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - TR_NEXT_STATE <= SHIFTOUT; - end if; - when PARITY => - if CLK_STRB = '1' then - if TDRE = '1' and TC = "11" then - -- Break condition, do not send a stop bit. - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP1; -- No parity check enabled. - end if; - else - TR_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then - TR_NEXT_STATE <= STOP2; -- Two stop bits selected. - elsif CLK_STRB = '1' then - TR_NEXT_STATE <= IDLE; -- One stop bits selected. - else - TR_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP2; - end if; - end case; - end process TR_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak deleted file mode 100644 index c3ca670..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak +++ /dev/null @@ -1,202 +0,0 @@ --- megafunction wizard: %LPM_FIFO+% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: dcfifo_mixed_widths - --- ============================================================ --- File Name: dcfifo0.vhd --- Megafunction Name(s): --- dcfifo_mixed_widths --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 222 10/21/2009 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dcfifo0 IS - PORT - ( - aclr : IN STD_LOGIC := '0'; - data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) - ); -END dcfifo0; - - -ARCHITECTURE SYN OF dcfifo0 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0); - - - - COMPONENT dcfifo_mixed_widths - GENERIC ( - intended_device_family : STRING; - lpm_numwords : NATURAL; - lpm_showahead : STRING; - lpm_type : STRING; - lpm_width : NATURAL; - lpm_widthu : NATURAL; - lpm_widthu_r : NATURAL; - lpm_width_r : NATURAL; - overflow_checking : STRING; - rdsync_delaypipe : NATURAL; - underflow_checking : STRING; - use_eab : STRING; - write_aclr_synch : STRING; - wrsync_delaypipe : NATURAL - ); - PORT ( - wrclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrusedw : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - aclr : IN STD_LOGIC ; - rdclk : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); - wrreq : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (7 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - wrusedw <= sub_wire0(4 DOWNTO 0); - q <= sub_wire1(15 DOWNTO 0); - - dcfifo_mixed_widths_component : dcfifo_mixed_widths - GENERIC MAP ( - intended_device_family => "Cyclone III", - lpm_numwords => 32, - lpm_showahead => "OFF", - lpm_type => "dcfifo", - lpm_width => 8, - lpm_widthu => 5, - lpm_widthu_r => 4, - lpm_width_r => 16, - overflow_checking => "ON", - rdsync_delaypipe => 5, - underflow_checking => "ON", - use_eab => "ON", - write_aclr_synch => "OFF", - wrsync_delaypipe => 5 - ) - PORT MAP ( - wrclk => wrclk, - rdreq => rdreq, - aclr => aclr, - rdclk => rdclk, - wrreq => wrreq, - data => data, - wrusedw => sub_wire0, - q => sub_wire1 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" --- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" --- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" --- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" --- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "4" --- Retrieval info: PRIVATE: Depth NUMERIC "32" --- Retrieval info: PRIVATE: Empty NUMERIC "1" --- Retrieval info: PRIVATE: Full NUMERIC "1" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" --- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" --- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" --- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: Optimize NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: UsedW NUMERIC "1" --- Retrieval info: PRIVATE: Width NUMERIC "8" --- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" --- Retrieval info: PRIVATE: diff_widths NUMERIC "1" --- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" --- Retrieval info: PRIVATE: output_width NUMERIC "16" --- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: rsFull NUMERIC "0" --- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" --- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" --- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" --- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: wsFull NUMERIC "0" --- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32" --- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" --- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" --- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5" --- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4" --- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16" --- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: USE_EAB STRING "ON" --- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" --- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr --- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] --- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0] --- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk --- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq --- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk --- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq --- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0] --- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 --- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0 --- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 --- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 --- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 --- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 --- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0 --- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak deleted file mode 100644 index e7c6ae6..0000000 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak +++ /dev/null @@ -1,202 +0,0 @@ --- megafunction wizard: %LPM_FIFO+% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: dcfifo_mixed_widths - --- ============================================================ --- File Name: dcfifo1.vhd --- Megafunction Name(s): --- dcfifo_mixed_widths --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 9.1 Build 222 10/21/2009 SJ Web Edition --- ************************************************************ - - ---Copyright (C) 1991-2009 Altera Corporation ---Your use of Altera Corporation's design tools, logic functions ---and other software and tools, and its AMPP partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Altera Program License ---Subscription Agreement, Altera MegaCore Function License ---Agreement, or other applicable license agreement, including, ---without limitation, that your use is for the sole purpose of ---programming logic devices manufactured by Altera and sold by ---Altera or its authorized distributors. Please refer to the ---applicable agreement for further details. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY dcfifo1 IS - PORT - ( - aclr : IN STD_LOGIC := '0'; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); - rdclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrclk : IN STD_LOGIC ; - wrreq : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) - ); -END dcfifo1; - - -ARCHITECTURE SYN OF dcfifo1 IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); - - - - COMPONENT dcfifo_mixed_widths - GENERIC ( - intended_device_family : STRING; - lpm_numwords : NATURAL; - lpm_showahead : STRING; - lpm_type : STRING; - lpm_width : NATURAL; - lpm_widthu : NATURAL; - lpm_widthu_r : NATURAL; - lpm_width_r : NATURAL; - overflow_checking : STRING; - rdsync_delaypipe : NATURAL; - underflow_checking : STRING; - use_eab : STRING; - write_aclr_synch : STRING; - wrsync_delaypipe : NATURAL - ); - PORT ( - wrclk : IN STD_LOGIC ; - rdreq : IN STD_LOGIC ; - wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); - aclr : IN STD_LOGIC ; - rdclk : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); - wrreq : IN STD_LOGIC ; - data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - wrusedw <= sub_wire0(3 DOWNTO 0); - q <= sub_wire1(7 DOWNTO 0); - - dcfifo_mixed_widths_component : dcfifo_mixed_widths - GENERIC MAP ( - intended_device_family => "Cyclone III", - lpm_numwords => 16, - lpm_showahead => "OFF", - lpm_type => "dcfifo", - lpm_width => 16, - lpm_widthu => 4, - lpm_widthu_r => 5, - lpm_width_r => 8, - overflow_checking => "ON", - rdsync_delaypipe => 5, - underflow_checking => "ON", - use_eab => "ON", - write_aclr_synch => "OFF", - wrsync_delaypipe => 5 - ) - PORT MAP ( - wrclk => wrclk, - rdreq => rdreq, - aclr => aclr, - rdclk => rdclk, - wrreq => wrreq, - data => data, - wrusedw => sub_wire0, - q => sub_wire1 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" --- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" --- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" --- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" --- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" --- Retrieval info: PRIVATE: Clock NUMERIC "4" --- Retrieval info: PRIVATE: Depth NUMERIC "16" --- Retrieval info: PRIVATE: Empty NUMERIC "1" --- Retrieval info: PRIVATE: Full NUMERIC "1" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" --- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" --- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" --- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: Optimize NUMERIC "1" --- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" --- Retrieval info: PRIVATE: UsedW NUMERIC "1" --- Retrieval info: PRIVATE: Width NUMERIC "16" --- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" --- Retrieval info: PRIVATE: diff_widths NUMERIC "1" --- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" --- Retrieval info: PRIVATE: output_width NUMERIC "8" --- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: rsFull NUMERIC "0" --- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" --- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" --- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" --- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" --- Retrieval info: PRIVATE: wsFull NUMERIC "0" --- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" --- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" --- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" --- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" --- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" --- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" --- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5" --- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" --- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" --- Retrieval info: CONSTANT: USE_EAB STRING "ON" --- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" --- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" --- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr --- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] --- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] --- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk --- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq --- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk --- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq --- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0] --- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 --- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 --- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 --- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 --- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 --- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 --- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 --- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE --- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak deleted file mode 100644 index e3e49eb..0000000 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf.bak +++ /dev/null @@ -1,478 +0,0 @@ -TITLE "INTERRUPT HANDLER UND C1287"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_LONG.inc"; -INCLUDE "lpm_bustri_BYT.inc"; - - --- Parameters Statement (optional) - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - - --- Subdesign Section - -SUBDESIGN interrupt_handler -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - MAIN_CLK : INPUT; - nFB_WR : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - FB_ADR[31..0] : INPUT; - PIC_INT : INPUT; - E0_INT : INPUT; - DVI_INT : INPUT; - nPCI_INTA : INPUT; - nPCI_INTB : INPUT; - nPCI_INTC : INPUT; - nPCI_INTD : INPUT; - nMFP_INT : INPUT; - nFB_OE : INPUT; - DSP_INT : INPUT; - VSYNC : INPUT; - HSYNC : INPUT; - DMA_DRQ : INPUT; - nIRQ[7..2] : OUTPUT; - INT_HANDLER_TA : OUTPUT; - ACP_CONF[31..0] : OUTPUT; - TIN0 : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_B[3..0] :NODE; - INT_CTR[31..0] :DFFE; - INT_CTR_CS :NODE; - INT_LATCH[31..0] :DFF; - INT_LATCH_CS :NODE; - INT_CLEAR[31..0] :DFF; - INT_CLEAR_CS :NODE; - INT_IN[31..0] :NODE; - INT_ENA[31..0] :DFFE; - INT_ENA_CS :NODE; - ACP_CONF[31..0] :DFFE; - ACP_CONF_CS :NODE; - PSEUDO_BUS_ERROR :NODE; - UHR_AS :NODE; - UHR_DS :NODE; - RTC_ADR[5..0] :DFFE; - ACHTELSEKUNDEN[2..0] :DFFE; - WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 - PIC_INT_SYNC[2..0] :DFF; - INC_SEC :NODE; - INC_MIN :NODE; - INC_STD :NODE; - INC_TAG :NODE; - ANZAHL_TAGE_DES_MONATS[7..0]:NODE; - WINTERZEIT :NODE; - SOMMERZEIT :NODE; - INC_MONAT :NODE; - INC_JAHR :NODE; - UPDATE_ON :NODE; - -BEGIN --- BYT SELECT - FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD - # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD - # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD - # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD - # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT - # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE - --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN - INT_CTR[].CLK = MAIN_CLK; - INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 - INT_CTR[] = FB_AD[]; - INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; - INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; - INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; - INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; --- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 - INT_ENA[].CLK = MAIN_CLK; - INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 - INT_ENA[] = FB_AD[]; - INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; - INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; - INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; - INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; --- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR - INT_CLEAR[].CLK = MAIN_CLK; - INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 - INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; - INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; - INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; - INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; --- INTERRUPT LATCH REGISTER READ ONLY - INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 --- INTERRUPT - !nIRQ2 = HSYNC & INT_ENA[26]; - !nIRQ3 = INT_CTR0 & INT_ENA[27]; - !nIRQ4 = VSYNC & INT_ENA[28]; - nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; - !nIRQ6 = !nMFP_INT & INT_ENA[30]; - !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; - -PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC - # FB_ADR[19..4]==H"F8E0" -- VME - # FB_ADR[19..4]==H"F920" -- PADDLE - # FB_ADR[19..4]==H"F921" -- PADDLE - # FB_ADR[19..4]==H"F922" -- PADDLE - # FB_ADR[19..4]==H"FFA8" -- MFP2 - # FB_ADR[19..4]==H"FFA9" -- MFP2 - # FB_ADR[19..4]==H"FFAA" -- MFP2 - # FB_ADR[19..4]==H"FFA8" -- MFP2 - # FB_ADR[19..8]==H"F87" -- TT SCSI - # FB_ADR[19..4]==H"FFC2" -- ST UHR - # FB_ADR[19..4]==H"FFC3" -- ST UHR - # FB_ADR[19..4]==H"F890" -- DMA SOUND - # FB_ADR[19..4]==H"F891" -- DMA SOUND - # FB_ADR[19..4]==H"F892"); -- DMA SOUND --- IF VIDEO ADR CHANGE -TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- VIDEO BASE ADR HIGH 0xFFFF8201/2 - --- INTERRUPT LATCH - INT_LATCH[] = H"FFFFFFFF"; - INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; - INT_LATCH1.CLK = E0_INT & INT_ENA[1]; - INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; - INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; - INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; - INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; - INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; - INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; - INT_LATCH8.CLK = VSYNC & INT_ENA[8]; - INT_LATCH9.CLK = HSYNC & INT_ENA[9]; - --- INTERRUPT CLEAR - INT_LATCH[].CLRN = !INT_CLEAR[]; - --- INT_IN - INT_IN0 = PIC_INT; - INT_IN1 = E0_INT; - INT_IN2 = DVI_INT; - INT_IN3 = !nPCI_INTA; - INT_IN4 = !nPCI_INTB; - INT_IN5 = !nPCI_INTC; - INT_IN6 = !nPCI_INTD; - INT_IN7 = DSP_INT; - INT_IN8 = VSYNC; - INT_IN9 = HSYNC; - INT_IN[25..10] = H"0"; - INT_IN26 = HSYNC; - INT_IN27 = INT_CTR0; - INT_IN28 = VSYNC; - INT_IN29 = INT_LATCH[]!=H"00000000"; - INT_IN30 = !nMFP_INT; - INT_IN31 = DMA_DRQ; ---*************************************************************************************** --- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE - ACP_CONF[].CLK = MAIN_CLK; - ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 - ACP_CONF[] = FB_AD[]; - ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; - ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; - ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; - ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; ---*************************************************************************************** - --------------------------------------------------------------- --- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR ----------------------------------------------------------- - RTC_ADR[].CLK = MAIN_CLK; - RTC_ADR[] = FB_AD[21..16]; - UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 - UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 - RTC_ADR[].ENA = UHR_AS & !nFB_WR; - WERTE[][].CLK = MAIN_CLK; - WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; - WERTE[7..0][1] = FB_AD[23..16]; - WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; - WERTE[7..0][3] = FB_AD[23..16]; - WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; - WERTE[7..0][5] = FB_AD[23..16]; - WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; - WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; - WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; - WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[7..0][10] = FB_AD[23..16]; - WERTE[7..0][11] = FB_AD[23..16]; - WERTE[7..0][12] = FB_AD[23..16]; - WERTE[7..0][13] = FB_AD[23..16]; - WERTE[7..0][14] = FB_AD[23..16]; - WERTE[7..0][15] = FB_AD[23..16]; - WERTE[7..0][16] = FB_AD[23..16]; - WERTE[7..0][17] = FB_AD[23..16]; - WERTE[7..0][18] = FB_AD[23..16]; - WERTE[7..0][19] = FB_AD[23..16]; - WERTE[7..0][20] = FB_AD[23..16]; - WERTE[7..0][21] = FB_AD[23..16]; - WERTE[7..0][22] = FB_AD[23..16]; - WERTE[7..0][23] = FB_AD[23..16]; - WERTE[7..0][24] = FB_AD[23..16]; - WERTE[7..0][25] = FB_AD[23..16]; - WERTE[7..0][26] = FB_AD[23..16]; - WERTE[7..0][27] = FB_AD[23..16]; - WERTE[7..0][28] = FB_AD[23..16]; - WERTE[7..0][29] = FB_AD[23..16]; - WERTE[7..0][30] = FB_AD[23..16]; - WERTE[7..0][31] = FB_AD[23..16]; - WERTE[7..0][32] = FB_AD[23..16]; - WERTE[7..0][33] = FB_AD[23..16]; - WERTE[7..0][34] = FB_AD[23..16]; - WERTE[7..0][35] = FB_AD[23..16]; - WERTE[7..0][36] = FB_AD[23..16]; - WERTE[7..0][37] = FB_AD[23..16]; - WERTE[7..0][38] = FB_AD[23..16]; - WERTE[7..0][39] = FB_AD[23..16]; - WERTE[7..0][40] = FB_AD[23..16]; - WERTE[7..0][41] = FB_AD[23..16]; - WERTE[7..0][42] = FB_AD[23..16]; - WERTE[7..0][43] = FB_AD[23..16]; - WERTE[7..0][44] = FB_AD[23..16]; - WERTE[7..0][45] = FB_AD[23..16]; - WERTE[7..0][46] = FB_AD[23..16]; - WERTE[7..0][47] = FB_AD[23..16]; - WERTE[7..0][48] = FB_AD[23..16]; - WERTE[7..0][49] = FB_AD[23..16]; - WERTE[7..0][50] = FB_AD[23..16]; - WERTE[7..0][51] = FB_AD[23..16]; - WERTE[7..0][52] = FB_AD[23..16]; - WERTE[7..0][53] = FB_AD[23..16]; - WERTE[7..0][54] = FB_AD[23..16]; - WERTE[7..0][55] = FB_AD[23..16]; - WERTE[7..0][56] = FB_AD[23..16]; - WERTE[7..0][57] = FB_AD[23..16]; - WERTE[7..0][58] = FB_AD[23..16]; - WERTE[7..0][59] = FB_AD[23..16]; - WERTE[7..0][60] = FB_AD[23..16]; - WERTE[7..0][61] = FB_AD[23..16]; - WERTE[7..0][62] = FB_AD[23..16]; - WERTE[7..0][63] = FB_AD[23..16]; - WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; - WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; - WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; - WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; - WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; - WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; - WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; - WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; - WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; - WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; - WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; - WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; - WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; - WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; - WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; - WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; - WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; - WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; - WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; - WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; - WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; - WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; - WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; - WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; - WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; - WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; - WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; - WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; - WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; - WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; - WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; - WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; - WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; - WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; - WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; - WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; - WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; - WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; - WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; - WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; - WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; - WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; - WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; - WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; - WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; - WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; - WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; - WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; - WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; - WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; - WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; - WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; - WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; - WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; - WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; - WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; - WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; - WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; - WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; - WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; - WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; - WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; - WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; - PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; - PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; - PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; - UPDATE_ON = !WERTE[7][11]; - WERTE[6][10].CLRN = GND; -- KEIN UIP - UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF - WERTE[2][11] = VCC; -- IMMER BINARY - WERTE[1][11] = VCC; -- IMMER 24H FORMAT - WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR - WERTE[7][13] = VCC; -- IMMER RICHTIG --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) - SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL - WERTE[0][13] = SOMMERZEIT; - WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); - WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER --- ACHTELSEKUNDEN - ACHTELSEKUNDEN[].CLK = MAIN_CLK; - ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; - ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; --- SEKUNDEN - INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 - WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); --- MINUTEN - INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 - WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- --- STUNDEN - INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 - WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT --- WOCHENTAG UND TAG - INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 - # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER - WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); - ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) - # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) - # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 - # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE - # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER - WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- --- MONATE - INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 - # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER - WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); --- JAHR - INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 - WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); --- TRISTATE OUTPUT - - FB_AD[31..24] = lpm_bustri_BYT( - INT_CTR_CS & INT_CTR[31..24] - # INT_ENA_CS & INT_ENA[31..24] - # INT_LATCH_CS & INT_LATCH[31..24] - # INT_CLEAR_CS & INT_IN[31..24] - # ACP_CONF_CS & ACP_CONF[31..24] - ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[23..16] = lpm_bustri_BYT( - WERTE[][0] & RTC_ADR[]==0 & UHR_DS - # WERTE[][1] & RTC_ADR[]==1 & UHR_DS - # WERTE[][2] & RTC_ADR[]==2 & UHR_DS - # WERTE[][3] & RTC_ADR[]==3 & UHR_DS - # WERTE[][4] & RTC_ADR[]==4 & UHR_DS - # WERTE[][5] & RTC_ADR[]==5 & UHR_DS - # WERTE[][6] & RTC_ADR[]==6 & UHR_DS - # WERTE[][7] & RTC_ADR[]==7 & UHR_DS - # WERTE[][8] & RTC_ADR[]==8 & UHR_DS - # WERTE[][9] & RTC_ADR[]==9 & UHR_DS - # WERTE[][10] & RTC_ADR[]==10 & UHR_DS - # WERTE[][11] & RTC_ADR[]==11 & UHR_DS - # WERTE[][12] & RTC_ADR[]==12 & UHR_DS - # WERTE[][13] & RTC_ADR[]==13 & UHR_DS - # WERTE[][14] & RTC_ADR[]==14 & UHR_DS - # WERTE[][15] & RTC_ADR[]==15 & UHR_DS - # WERTE[][16] & RTC_ADR[]==16 & UHR_DS - # WERTE[][17] & RTC_ADR[]==17 & UHR_DS - # WERTE[][18] & RTC_ADR[]==18 & UHR_DS - # WERTE[][19] & RTC_ADR[]==19 & UHR_DS - # WERTE[][20] & RTC_ADR[]==20 & UHR_DS - # WERTE[][21] & RTC_ADR[]==21 & UHR_DS - # WERTE[][22] & RTC_ADR[]==22 & UHR_DS - # WERTE[][23] & RTC_ADR[]==23 & UHR_DS - # WERTE[][24] & RTC_ADR[]==24 & UHR_DS - # WERTE[][25] & RTC_ADR[]==25 & UHR_DS - # WERTE[][26] & RTC_ADR[]==26 & UHR_DS - # WERTE[][27] & RTC_ADR[]==27 & UHR_DS - # WERTE[][28] & RTC_ADR[]==28 & UHR_DS - # WERTE[][29] & RTC_ADR[]==29 & UHR_DS - # WERTE[][30] & RTC_ADR[]==30 & UHR_DS - # WERTE[][31] & RTC_ADR[]==31 & UHR_DS - # WERTE[][32] & RTC_ADR[]==32 & UHR_DS - # WERTE[][33] & RTC_ADR[]==33 & UHR_DS - # WERTE[][34] & RTC_ADR[]==34 & UHR_DS - # WERTE[][35] & RTC_ADR[]==35 & UHR_DS - # WERTE[][36] & RTC_ADR[]==36 & UHR_DS - # WERTE[][37] & RTC_ADR[]==37 & UHR_DS - # WERTE[][38] & RTC_ADR[]==38 & UHR_DS - # WERTE[][39] & RTC_ADR[]==39 & UHR_DS - # WERTE[][40] & RTC_ADR[]==40 & UHR_DS - # WERTE[][41] & RTC_ADR[]==41 & UHR_DS - # WERTE[][42] & RTC_ADR[]==42 & UHR_DS - # WERTE[][43] & RTC_ADR[]==43 & UHR_DS - # WERTE[][44] & RTC_ADR[]==44 & UHR_DS - # WERTE[][45] & RTC_ADR[]==45 & UHR_DS - # WERTE[][46] & RTC_ADR[]==46 & UHR_DS - # WERTE[][47] & RTC_ADR[]==47 & UHR_DS - # WERTE[][48] & RTC_ADR[]==48 & UHR_DS - # WERTE[][49] & RTC_ADR[]==49 & UHR_DS - # WERTE[][50] & RTC_ADR[]==50 & UHR_DS - # WERTE[][51] & RTC_ADR[]==51 & UHR_DS - # WERTE[][52] & RTC_ADR[]==52 & UHR_DS - # WERTE[][53] & RTC_ADR[]==53 & UHR_DS - # WERTE[][54] & RTC_ADR[]==54 & UHR_DS - # WERTE[][55] & RTC_ADR[]==55 & UHR_DS - # WERTE[][56] & RTC_ADR[]==56 & UHR_DS - # WERTE[][57] & RTC_ADR[]==57 & UHR_DS - # WERTE[][58] & RTC_ADR[]==58 & UHR_DS - # WERTE[][59] & RTC_ADR[]==59 & UHR_DS - # WERTE[][60] & RTC_ADR[]==60 & UHR_DS - # WERTE[][61] & RTC_ADR[]==61 & UHR_DS - # WERTE[][62] & RTC_ADR[]==62 & UHR_DS - # WERTE[][63] & RTC_ADR[]==63 & UHR_DS - # (0,RTC_ADR[]) & UHR_AS - # INT_CTR_CS & INT_CTR[23..16] - # INT_ENA_CS & INT_ENA[23..16] - # INT_LATCH_CS & INT_LATCH[23..16] - # INT_CLEAR_CS & INT_IN[23..16] - # ACP_CONF_CS & ACP_CONF[23..16] - ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[15..8] = lpm_bustri_BYT( - INT_CTR_CS & INT_CTR[15..8] - # INT_ENA_CS & INT_ENA[15..8] - # INT_LATCH_CS & INT_LATCH[15..8] - # INT_CLEAR_CS & INT_IN[15..8] - # ACP_CONF_CS & ACP_CONF[15..8] - ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[7..0] = lpm_bustri_BYT( - INT_CTR_CS & INT_CTR[7..0] - # INT_ENA_CS & INT_ENA[7..0] - # INT_LATCH_CS & INT_LATCH[7..0] - # INT_CLEAR_CS & INT_IN[7..0] - # ACP_CONF_CS & ACP_CONF[7..0] - ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - - INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; -END; - - diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak deleted file mode 100644 index f674080..0000000 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd.bak +++ /dev/null @@ -1,75 +0,0 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Fri Oct 16 15:40:59 2009 - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - - --- Entity Declaration - -ENTITY BLITTER IS - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT - ( - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); - BLITTER_ON : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) - ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END BLITTER; - - --- Architecture Body - -ARCHITECTURE BLITTER_architecture OF BLITTER IS - - -BEGIN - BLITTER_RUN <= '0'; - BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; - BLITTER_ADR <= x"FEDCBA9876543210"; - BLITTER_SIG <= '0'; - BLITTER_WR <= '0'; - BLITTER_TA <= '0'; - -END BLITTER_architecture; diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak b/FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak deleted file mode 100644 index ead66e8..0000000 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.tdf.bak +++ /dev/null @@ -1,660 +0,0 @@ -TITLE "DDR_CTR"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_BYT.inc"; - --- FIFO WATER MARK -CONSTANT FIFO_LWM = 0; -CONSTANT FIFO_MWM = 200; -CONSTANT FIFO_HWM = 500; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN DDR_CTR -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - CLR_FIFO : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - BLITTER_ADR[31..0] : INPUT; - BLITTER_SIG : INPUT; - BLITTER_WR : INPUT; - DDRCLK0 : INPUT; - CLK33M : INPUT; - FIFO_MW[8..0] : INPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - CLEAR_FIFO_CNT : OUTPUT; - SR_FIFO_WRE : OUTPUT; - SR_DDR_FB : OUTPUT; - SR_DDR_WR : OUTPUT; - SR_DDRWR_D_SEL : OUTPUT; - SR_VDMP[7..0] : OUTPUT; - VIDEO_DDR_TA : OUTPUT; - SR_BLITTER_DACK : OUTPUT; - BA[1..0] : OUTPUT; - DDRWR_D_SEL1 : OUTPUT; - VDM_SEL[3..0] : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) - DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG - DS_T4R,DS_T5R, -- READ CPU UND BLITTER, - DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER - DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO - DS_CB6, DS_CB8, -- CLOSE FIFO BANK - DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS - LINE :NODE; - FB_B[3..0] :NODE; - VCAS :NODE; - VRAS :NODE; - VWE :NODE; - VA_P[12..0] :DFF; - BA_P[1..0] :DFF; - VA_S[12..0] :DFF; - BA_S[1..0] :DFF; - MCS[1..0] :DFF; - CPU_DDR_SYNC :DFF; - DDR_SEL :NODE; - DDR_CS :DFFE; - DDR_CONFIG :NODE; - SR_DDR_WR :DFF; - SR_DDRWR_D_SEL :DFF; - SR_VDMP[7..0] :DFF; - CPU_ROW_ADR[12..0] :NODE; - CPU_BA[1..0] :NODE; - CPU_COL_ADR[9..0] :NODE; - CPU_SIG :NODE; - CPU_REQ :DFF; - CPU_AC :DFF; - BUS_CYC :DFF; - BUS_CYC_END :NODE; - BLITTER_REQ :DFF; - BLITTER_AC :DFF; - BLITTER_ROW_ADR[12..0] :NODE; - BLITTER_BA[1..0] :NODE; - BLITTER_COL_ADR[9..0] :NODE; - FIFO_REQ :DFF; - FIFO_AC :DFF; - FIFO_ROW_ADR[12..0] :NODE; - FIFO_BA[1..0] :NODE; - FIFO_COL_ADR[9..0] :NODE; - FIFO_ACTIVE :NODE; - CLR_FIFO_SYNC :DFF; - CLEAR_FIFO_CNT :DFF; - STOP :DFF; - SR_FIFO_WRE :DFF; - FIFO_BANK_OK :DFF; - FIFO_BANK_NOT_OK :NODE; - DDR_REFRESH_ON :NODE; - DDR_REFRESH_CNT[10..0] :DFF; - DDR_REFRESH_REQ :DFF; - DDR_REFRESH_SIG[3..0] :DFFE; - REFRESH_TIME :DFF; - VIDEO_BASE_L_D[7..0] :DFFE; - VIDEO_BASE_L :NODE; - VIDEO_BASE_M_D[7..0] :DFFE; - VIDEO_BASE_M :NODE; - VIDEO_BASE_H_D[7..0] :DFFE; - VIDEO_BASE_H :NODE; - VIDEO_BASE_X_D[2..0] :DFFE; - VIDEO_ADR_CNT[22..0] :DFFE; - VIDEO_CNT_L :NODE; - VIDEO_CNT_M :NODE; - VIDEO_CNT_H :NODE; - VIDEO_BASE_ADR[22..0] :NODE; - VIDEO_ACT_ADR[26..0] :NODE; - -BEGIN - LINE = FB_SIZE0 & FB_SIZE1; --- BYT SELECT - FB_B0 = FB_ADR[1..0]==0 -- ADR==0 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR.CLK = MAIN_CLK; - CASE FB_REGDDR IS - WHEN FR_WAIT => - FB_LE0 = !nFB_WR; - IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE - FB_REGDDR = FR_S0; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S0 => - IF DDR_CS THEN - FB_LE0 = !nFB_WR; - VIDEO_DDR_TA = VCC; - IF LINE THEN - FB_VDOE0 = !nFB_OE & !DDR_CONFIG; - FB_REGDDR = FR_S1; - ELSE - BUS_CYC_END = VCC; - FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; - FB_REGDDR = FR_WAIT; - END IF; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S1 => - IF DDR_CS THEN - FB_VDOE1 = !nFB_OE & !DDR_CONFIG; - FB_LE1 = !nFB_WR; - VIDEO_DDR_TA = VCC; - FB_REGDDR = FR_S2; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S2 => - IF DDR_CS THEN - FB_VDOE2 = !nFB_OE & !DDR_CONFIG; - FB_LE2 = !nFB_WR; - IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN - FB_REGDDR = FR_S2; - ELSE - VIDEO_DDR_TA = VCC; - FB_REGDDR = FR_S3; - END IF; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S3 => - IF DDR_CS THEN - FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; - FB_LE3 = !nFB_WR; - VIDEO_DDR_TA = VCC; - BUS_CYC_END = VCC; - FB_REGDDR = FR_WAIT; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - END CASE; --- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; - VCKE = VIDEO_RAM_CTR0; - nVCS = !VIDEO_RAM_CTR1; - DDR_REFRESH_ON = VIDEO_RAM_CTR2; - DDR_CONFIG = VIDEO_RAM_CTR3; - FIFO_ACTIVE = VIDEO_RAM_CTR8; --------------------------------- - CPU_ROW_ADR[] = FB_ADR[26..14]; - CPU_BA[] = FB_ADR[13..12]; - CPU_COL_ADR[] = FB_ADR[11..2]; - nVRAS = !VRAS; - nVCAS = !VCAS; - nVWE = !VWE; - SR_DDR_WR.CLK = DDRCLK0; - SR_DDRWR_D_SEL.CLK = DDRCLK0; - SR_VDMP[7..0].CLK = DDRCLK0; - SR_FIFO_WRE.CLK = DDRCLK0; - CPU_AC.CLK = DDRCLK0; - FIFO_AC.CLK = DDRCLK0; - BLITTER_AC.CLK = DDRCLK0; - DDRWR_D_SEL1 = BLITTER_AC; --- SELECT LOGIC - DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; - DDR_CS.CLK = MAIN_CLK; - DDR_CS.ENA = FB_ALE; - DDR_CS = DDR_SEL; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER - CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG - # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS - # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER - CPU_REQ.CLK = DDR_SYNC_66M; - CPU_REQ = CPU_SIG - # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG - BUS_CYC.CLK = DDRCLK0; - BUS_CYC = BUS_CYC & !BUS_CYC_END; - -- STATE MACHINE SYNCHRONISIEREN ----------------- - MCS[].CLK = DDRCLK0; - MCS0 = MAIN_CLK; - MCS1 = MCS0; - CPU_DDR_SYNC.CLK = DDRCLK0; - CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN - --------------------------------------------------- - VA_S[].CLK = DDRCLK0; - BA_S[].CLK = DDRCLK0; - VA[] = VA_S[]; - BA[] = BA_S[]; - VA_P[].CLK = DDRCLK0; - BA_P[].CLK = DDRCLK0; --- DDR STATE MACHINE ----------------------------------------------- - DDR_SM.CLK = DDRCLK0; - CASE DDR_SM IS - WHEN DS_T1 => - IF DDR_REFRESH_REQ THEN - DDR_SM = DS_R2; - ELSE - IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? - IF DDR_CONFIG THEN -- JA - DDR_SM = DS_C2; - ELSE - IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE - VA_S[] = CPU_ROW_ADR[]; - BA_S[] = CPU_BA[]; - CPU_AC = VCC; - BUS_CYC = VCC; - DDR_SM = DS_T2B; - ELSE - IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT - VA_P[] = FIFO_ROW_ADR[]; - BA_P[] = FIFO_BA[]; - FIFO_AC = VCC; -- VORBESETZEN - ELSE - VA_P[] = BLITTER_ROW_ADR[]; - BA_P[] = BLITTER_BA[]; - BLITTER_AC = VCC; -- VORBESETZEN - END IF; - DDR_SM = DS_T2A; - END IF; - END IF; - ELSE - DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN - END IF; - END IF; - - WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** - IF DDR_SEL & (nFB_WR # !LINE) THEN - VRAS = VCC; - VA[] = FB_AD[26..14]; - BA[] = FB_AD[13..12]; - VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - ELSE - VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; - VA[] = VA_P[]; - BA[] = BA_P[]; - VA_S[10] = !(FIFO_AC & FIFO_REQ); - FIFO_BANK_OK = FIFO_AC & FIFO_REQ; - FIFO_AC = FIFO_AC & FIFO_REQ; - BLITTER_AC = BLITTER_AC & BLITTER_REQ; - END IF; - DDR_SM = DS_T3; - - WHEN DS_T2B => - VRAS = VCC; - FIFO_BANK_NOT_OK = VCC; - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - DDR_SM = DS_T3; - - WHEN DS_T3 => - CPU_AC = CPU_AC; - FIFO_AC = FIFO_AC; - BLITTER_AC = BLITTER_AC; - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN - DDR_SM = DS_T4W; - ELSE - IF CPU_AC THEN -- CPU? - VA_S[9..0] = CPU_COL_ADR[]; - BA_S[] = CPU_BA[]; - DDR_SM = DS_T4R; - ELSE - IF FIFO_AC THEN -- FIFO? - VA_S[9..0] = FIFO_COL_ADR[]; - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T4F; - ELSE - IF BLITTER_AC THEN - VA_S[9..0] = BLITTER_COL_ADR[]; - BA_S[] = BLITTER_BA[]; - DDR_SM = DS_T4R; - ELSE - DDR_SM = DS_N8; - END IF; - END IF; - END IF; - END IF; --- READ - WHEN DS_T4R => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VCAS = VCC; - SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU - SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN - DDR_SM = DS_T5R; - - WHEN DS_T5R => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK - VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- MANUEL PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; - END IF; --- WRITE - WHEN DS_T4W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - DDR_SM = DS_T5W; - - WHEN DS_T5W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VA_S[9..0] = CPU_AC & CPU_COL_ADR[] - # BLITTER_AC & BLITTER_COL_ADR[]; - VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE - BA_S[] = CPU_AC & CPU_BA[] - # BLITTER_AC & BLITTER_BA[]; - SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE - SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE - DDR_SM = DS_T6W; - - WHEN DS_T6W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - VCAS = VCC; - VWE = VCC; - SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV - DDR_SM = DS_T7W; - - WHEN DS_T7W => - CPU_AC = CPU_AC; - BLITTER_AC = BLITTER_AC; - SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE - SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN - DDR_SM = DS_T8W; - - WHEN DS_T8W => - DDR_SM = DS_T9W; - - WHEN DS_T9W => - IF FIFO_REQ & FIFO_BANK_OK THEN - VA_S[9..0] = FIFO_COL_ADR[]; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; - END IF; --- FIFO READ - WHEN DS_T4F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T5F; - - WHEN DS_T5F => - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - ELSE - VA_S[9..0] = FIFO_COL_ADR[]+4; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T6F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN - END IF; - - WHEN DS_T6F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T7F; - - WHEN DS_T7F => - IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN - VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - ELSE - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - ELSE - VA_S[9..0] = FIFO_COL_ADR[]+4; - VA_S[10] = GND; -- NON AUTO PRECHARGE - BA_S[] = FIFO_BA[]; - DDR_SM = DS_T8F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN - DDR_SM = DS_CB8; -- BANK SCHLIESSEN - END IF; - END IF; - - WHEN DS_T8F => - VCAS = VCC; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - IF FIFO_MW[] - ELSE - DDR_SM = DS_T9F; - END IF; - - WHEN DS_T9F => - IF FIFO_REQ THEN - IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? - VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - ELSE - VA_P[9..0] = FIFO_COL_ADR[]+4; - VA_P[10] = GND; -- NON AUTO PRECHARGE - BA_P[] = FIFO_BA[]; - DDR_SM = DS_T10F; - END IF; - ELSE - VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN - DDR_SM = DS_CB6; -- BANK SCHLIESSEN - END IF; - - WHEN DS_T10F => - IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN - VRAS = VCC; - VA[] = FB_AD[26..14]; - BA[] = FB_AD[13..12]; - CPU_AC = VCC; - BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN - VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK - DDR_SM = DS_T3; - ELSE - VCAS = VCC; - VA[] = VA_P[]; - BA[] = BA_P[]; - SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO - DDR_SM = DS_T7F; - END IF; - --- CONFIG CYCLUS - WHEN DS_C2 => - DDR_SM = DS_C3; - WHEN DS_C3 => - BUS_CYC = CPU_REQ; - DDR_SM = DS_C4; - WHEN DS_C4 => - IF CPU_REQ THEN - DDR_SM = DS_C5; - ELSE - DDR_SM = DS_T1; - END IF; - WHEN DS_C5 => - DDR_SM = DS_C6; - WHEN DS_C6 => - VA_S[] = FB_AD[12..0]; - BA_S[] = FB_AD[14..13]; - DDR_SM = DS_C7; - WHEN DS_C7 => - VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE - DDR_SM = DS_N8; --- CLOSE FIFO BANK - WHEN DS_CB6 => - FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN - VWE = VCC; - DDR_SM = DS_N7; - WHEN DS_CB8 => - FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK - VRAS = VCC; -- BÄNKE SCHLIESSEN - VWE = VCC; - DDR_SM = DS_T1; --- REFRESH 70NS = 10 ZYCLEN - WHEN DS_R2 => - IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN - VRAS = VCC; -- ALLE BANKS SCHLIESSEN - VWE = VCC; - VA[10] = VCC; - FIFO_BANK_NOT_OK = VCC; - DDR_SM = DS_R4; - ELSE - VCAS = VCC; - VRAS = VCC; - DDR_SM = DS_R3; - END IF; - WHEN DS_R3 => - DDR_SM = DS_R4; - WHEN DS_R4 => - DDR_SM = DS_R5; - WHEN DS_R5 => - DDR_SM = DS_R6; - WHEN DS_R6 => - DDR_SM = DS_N5; --- LEERSCHLAUFE - WHEN DS_N5 => - DDR_SM = DS_N6; - WHEN DS_N6 => - DDR_SM = DS_N7; - WHEN DS_N7 => - DDR_SM = DS_N8; - WHEN DS_N8 => - DDR_SM = DS_T1; - END CASE; - ---------------------------------------------------------------- --- BLITTER ---------------------- ------------------------------------------ - BLITTER_REQ.CLK = DDRCLK0; - BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; - BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; - BLITTER_BA1 = BLITTER_ADR13; - BLITTER_BA0 = BLITTER_ADR12; - BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; ------------------------------------------------------------------------------- --- FIFO --------------------------------- --------------------------------------------------------- - FIFO_REQ.CLK = DDRCLK0; - FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS ------------------------------------------------------------------------------------------ - DDR_REFRESH_CNT[].CLK = CLK33M; - DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 - REFRESH_TIME.CLK = DDRCLK0; - REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC - DDR_REFRESH_SIG[].CLK = DDRCLK0; - DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; - DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) - # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT - DDR_REFRESH_REQ.CLK = DDRCLK0; - DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; ------------------------------------------------------------ --- VIDEO REGISTER ----------------------- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D[].CLK = MAIN_CLK; - VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 - VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; - - VIDEO_BASE_M_D[].CLK = MAIN_CLK; - VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 - VIDEO_BASE_M_D[] = FB_AD[23..16]; - VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; - - VIDEO_BASE_H_D[].CLK = MAIN_CLK; - VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 - VIDEO_BASE_H_D[] = FB_AD[23..16]; - VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; - VIDEO_BASE_X_D[].CLK = MAIN_CLK; - VIDEO_BASE_X_D[] = FB_AD[26..24]; - VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; - - VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 - VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 - VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 - - FB_AD[31..24] = lpm_bustri_BYT( - VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) - # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) - ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - - FB_AD[23..16] = lpm_bustri_BYT( - VIDEO_BASE_L & VIDEO_BASE_L_D[] - # VIDEO_BASE_M & VIDEO_BASE_M_D[] - # VIDEO_BASE_H & VIDEO_BASE_H_D[] - # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] - # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] - # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] - ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); -END; - diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak deleted file mode 100644 index 03052b4..0000000 --- a/FPGA_Quartus_13.1/Video/DDR_CTR_BLITTER.tdf.bak +++ /dev/null @@ -1,352 +0,0 @@ -TITLE "DDR_CTR_BLITTER"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_BYT.inc"; - - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN DDR_CTR_BLITTER -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - FB_ADR[31..0] : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nRSTO : INPUT; - MAIN_CLK : INPUT; - FIFO_FULL : INPUT; - FB_ALE : INPUT; - nFB_WR : INPUT; - DDR_SYNC_66M : INPUT; - VSYNC : INPUT; - BLITTER_ON : INPUT; - VIDEO_RAM_CTR[15..0] : INPUT; - VDVZ[127..0] : INPUT; - DDRCLK[3..0] : INPUT; - BA0 : OUTPUT; - BA1 : OUTPUT; - VA[12..0] : OUTPUT; - nVWE : OUTPUT; - nVRAS : OUTPUT; - nVCS : OUTPUT; - VCKE : OUTPUT; - nVCAS : OUTPUT; - FIFO_WRE : OUTPUT; - FB_LE[3..0] : OUTPUT; - FB_VDOE[3..0] : OUTPUT; - START_CYC_RDWR : OUTPUT; - DDR_WR : OUTPUT; - CLEAR_FIFO_CNT : OUTPUT; - BLITTER_RUN : OUTPUT; - BLITTER_DOUT[127..0] : OUTPUT; - BLITTER_LE[3..0] : OUTPUT; - BLITTER_RDE : OUTPUT; - DDRWR_D_SEL[1..0] : OUTPUT; - VDMP[7..0] : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); - DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS); - LINE :NODE; - FB_B[3..0] :NODE; - VCAS :NODE; - VRAS :NODE; - VWE :NODE; - VA[12..0] :NODE; - BA0 :NODE; - BA1 :NODE; - DDR_WR :DFF; - DDR_SEL :NODE; - DDR_CONFIG :NODE; - DDRWR_D_SEL[1..0] :DFF; - CPU_ROW_ADR[12..0] :NODE; - CPU_BA0 :NODE; - CPU_BA1 :NODE; - CPU_COL_ADR[9..0] :NODE; - CPU_SIG :NODE; - CPU_REQ :DFF; - BLITTER_SIG :NODE; - BLITTER_REQ :DFF; - BLITTER_RUN :DFF; - BLITTER_WR :DFF; - BLITTER_ROW_ADR[12..0] :NODE; - BLITTER_BA0 :NODE; - BLITTER_BA1 :NODE; - BLITTER_COL_ADR[9..0] :NODE; - FIFO_SIG :NODE; - FIFO_REQ :DFF; - FIFO_ROW_ADR[12..0] :NODE; - FIFO_BA0 :NODE; - FIFO_BA1 :NODE; - FIFO_COL_ADR[9..0] :NODE; - FIFO_WRE :DFF; - FIFO_ACTIVE :NODE; - CLEAR_FIFO_CNT :DFF; - STOP :DFF; - DDR_REFRESH_ON :NODE; - VIDEO_BASE_L_D[3..0] :DFFE; - VIDEO_BASE_L :NODE; - VIDEO_BASE_M_D[7..0] :DFFE; - VIDEO_BASE_M :NODE; - VIDEO_BASE_H_D[7..0] :DFFE; - VIDEO_BASE_H :NODE; - VIDEO_BASE_X_D[7..0] :DFFE; - VIDEO_ADR_CNT[27..0] :DFFE; - VIDEO_CNT_L :NODE; - VIDEO_CNT_M :NODE; - VIDEO_CNT_H :NODE; - VIDEO_BASE_ADR[27..0] :NODE; - -BEGIN - LINE = FB_SIZE0 & FB_SIZE1; --- BYT SELECT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- - FB_REGDDR.CLK = MAIN_CLK; - CASE FB_REGDDR IS - WHEN FR_WAIT => - IF DDR_SEL THEN - FB_REGDDR = FR_S0; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S0 => - FB_VDOE0 = !nFB_OE & !DDR_CONFIG; - FB_LE0 = !nFB_WR; - IF LINE THEN - FB_REGDDR = FR_S1; - ELSE - FB_REGDDR = FR_WAIT; - END IF; - WHEN FR_S1 => - FB_VDOE1 = !nFB_OE & !DDR_CONFIG; - FB_LE1 = !nFB_WR; - FB_REGDDR = FR_S2; - WHEN FR_S2 => - FB_VDOE2 = !nFB_OE & !DDR_CONFIG; - FB_LE2 = !nFB_WR; - FB_REGDDR = FR_S3; - WHEN FR_S3 => - FB_VDOE3 = !nFB_OE & !DDR_CONFIG; - FB_LE3 = !nFB_WR; - FB_REGDDR = FR_WAIT; - END CASE; --- DDR STEUERUNG ----------------------------------------------------- --- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE - VCKE = VIDEO_RAM_CTR0; - nVCS = !VIDEO_RAM_CTR1; - FIFO_ACTIVE = VIDEO_RAM_CTR2; - DDR_CONFIG = VIDEO_RAM_CTR3; - DDR_REFRESH_ON = VIDEO_RAM_CTR4; --------------------------------- - CPU_ROW_ADR[] = FB_ADR[26..14]; - CPU_BA1 = FB_ADR13; - CPU_BA0 = FB_ADR12; - CPU_COL_ADR[] = FB_ADR[11..2]; - nVRAS = !VRAS; - nVCAS = !VCAS; - nVWE = !VWE; - DDR_WR.CLK = DDRCLK0; --- SELECT LOGIC - DDR_SEL = FB_ALE & FB_AD[31..29]==B"011"; --- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER - CPU_SIG = DDR_SEL & nFB_WR & !DDR_CONFIG -- READ SOFORT LOS - # FR_S0 & !nFB_WR -- WRITE SPÄTER AUCH CONFIG - # FR_S3 & !nFB_WR & LINE & !DDR_CONFIG; -- LINE WRITE - CPU_REQ = CPU_SIG; - CPU_REQ.CLK = DDR_SYNC_66M; - DDR_D_SEL[].CLK = DDRCLK3; --- DDR STATE MACHINE ----------------------------------------------- - DDR_SM.CLK = DDRCLK0; - CASE DDR_SM IS - WHEN DS_T1 => - IF MAIN_CLK THEN - DDR_WR = DDR_WR; -- WRITE HALTEN (VON T4) - DDR_SM = DS_T2; - ELSE - DDR_SM = DS_LS; -- SYNCHRONISIEREN - END IF; - WHEN DS_T2 => - IF !DDR_CONFIG THEN - VRAS = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON; - VA[] = CPU_SIG & CPU_ROW_ADR[] - # BLITTER_SIG & BLITTER_ROW_ADR[] - # FIFO_SIG & FIFO_ROW_ADR[]; - BA0 = CPU_SIG & CPU_BA0 - # BLITTER_SIG & BLITTER_BA0 - # FIFO_SIG & FIFO_BA0; - BA1 = CPU_SIG & CPU_BA1 - # BLITTER_SIG & BLITTER_BA1 - # FIFO_SIG & FIFO_BA1; - VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON; -- AUTO REFRESH WENN SONST NICHTS - BLITTER_REQ = BLITTER_SIG; - FIFO_REQ = FIFO_SIG; - END IF; - IF MAIN_CLK THEN - DDR_SM = DS_T3; - ELSE - DDR_SM = DS_LS; - END IF; - WHEN DS_T3 => - IF DDR_CONFIG & CPU_REQ THEN - VRAS = FB_AD18; - VCAS = FB_AD17; - VWE = FB_AD16; - BA1 = FB_AD14; - BA0 = FB_AD13; - VA[] = FB_AD[12..0]; - END IF; - IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN - DDR_SM = DS_LS; - ELSE - BLITTER_REQ = BLITTER_SIG; - FIFO_REQ = FIFO_SIG; - DDR_SM = DS_T4; - END IF; - WHEN DS_T4 => - FIFO_REQ = FIFO_SIG; - VCAS = VCC; - VWE = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; - VA[9..0] = CPU_REQ & CPU_COL_ADR[] - # BLITTER_REQ & BLITTER_COL_ADR[] - # FIFO_REQ & FIFO_COL_ADR[]; - VA10 = VCC; -- AUTO PRECHARGE - BA0 = CPU_REQ & CPU_BA0 - # BLITTER_REQ & BLITTER_BA0 - # FIFO_REQ & FIFO_BA0; - BA1 = CPU_REQ & CPU_BA1 - # BLITTER_REQ & BLITTER_BA1 - # FIFO_REQ & FIFO_BA1; - DDR_WR = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ; - FIFO_REQ = FIFO_SIG; - IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? - DDR_SM = DS_T5; -- JA-> - ELSE - DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN - END IF; - WHEN DS_T5 => - FIFO_REQ = FIFO_SIG; - DDR_SM = DS_T6; - WHEN DS_T6 => - IF CPU_SIG THEN -- SOFORT UMSCHALTEN WENN CPU REQ - VRAS = VCC; - VA[] = CPU_ROW_ADR[]; - BA1 = CPU_BA1; - BA0 = CPU_BA0; - DDR_SM = DS_T3; - ELSE - FIFO_REQ = FIFO_SIG; - VCAS = VCC; - VA[9..0] = FIFO_COL_ADR[]; - VA10 = VCC; -- AUTO PRECHARGE - BA0 = FIFO_BA0; - BA1 = FIFO_BA1; - FIFO_WRE = FIFO_REQ; -- ODER FIFO LATCH IN 5 CYC 133 - IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN -- GLEICHE PAGE? - DDR_SM = DS_T5; -- JA-> - ELSE - DDR_SM = DS_T1; -- SONST NEUE PAGE AUFMACHEN - END IF; - END IF; - WHEN DS_LS => - IF !MAIN_CLK THEN -- LEERSTATE UND SYNC - DDR_SM = DS_T1; - ELSE - DDR_SM = DS_LS; - END IF; - END CASE; ------------------------------------------------------------------------------- --- FIFO --------------------------------- - FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG; - FIFO_REQ.CLK = DDR_SYNC_66M; - FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12]; - FIFO_BA1 = VIDEO_ADR_CNT11; - FIFO_BA0 = VIDEO_ADR_CNT10; - FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0]; - -- ZÄHLER RÜCKSETZEN WENN VSYNC ---------------- - CLEAR_FIFO_CNT.CLK = DDRCLK0; - CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE; - STOP.CLK = DDRCLK0; - STOP = VSYNC # CLEAR_FIFO_CNT; - VIDEO_ADR_CNT[].CLK = DDRCLK0; - VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[] -- SET - # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1); -- NEXT 16 BYTS - VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE; - FIFO_WRE.CLK = DDRCLK0; ---------------------------------------------------------------- --- BLITTER BUS IST 128 BIT BREIT ------ - BLITTER_SIG = GND & !CPU_SIG; - BLITTER_REQ.CLK = DDR_SYNC_66M; - BLITTER_RUN.CLK = DDRCLK0; - BLITTER_RUN = GND; - BLITTER_WR.CLK = DDRCLK0; - BLITTER_WR = GND; - DDRWR_D_SEL1 = BLITTER_WR; - BLITTER_ROW_ADR[] = H"0"; - BLITTER_BA1 = GND; - BLITTER_BA0 = GND; - BLITTER_COL_ADR[] = H"0"; - BLITTER_DOUT[] = H"0"; - BLITTER_LE[] = H"0"; ------------------------------------------------------------ --- VIDEO REGISTER ----------------------- ---------------------------------------------------------------------------------------------------------------------- - VIDEO_BASE_L_D[].CLK = MAIN_CLK; - VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; -- 820D/2 - VIDEO_BASE_L_D[] = FB_AD[23..20]; -- SORRY, NUR 16 BYT GRENZEN - VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; - - VIDEO_BASE_M_D[].CLK = MAIN_CLK; - VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; -- 8203/2 - VIDEO_BASE_M_D[] = FB_AD[23..16]; - VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; - - VIDEO_BASE_H_D[].CLK = MAIN_CLK; - VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100"; -- 8200-1/2 - VIDEO_BASE_H_D[] = FB_AD[23..16]; - VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; - VIDEO_BASE_X_D[].CLK = MAIN_CLK; - VIDEO_BASE_X_D[] = FB_AD[31..24]; - VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; - - VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; -- 8209/2 - VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; -- 8207/2 - VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; -- 8205/2 - - FB_AD[31..24] = lpm_bustri_BYT( - VIDEO_BASE_H & VIDEO_BASE_X_D[] - # VIDEO_CNT_H & VIDEO_ADR_CNT[27..20] - ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); - - FB_AD[23..16] = lpm_bustri_BYT( - VIDEO_BASE_L & (VIDEO_BASE_L_D[],B"0000") - # VIDEO_BASE_M & VIDEO_BASE_M_D[] - # VIDEO_BASE_H & VIDEO_BASE_H_D[] - # VIDEO_CNT_L & (VIDEO_ADR_CNT[3..0],B"0000") - # VIDEO_CNT_M & VIDEO_ADR_CNT[11..4] - # VIDEO_CNT_H & VIDEO_ADR_CNT[19..12] - ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); - - VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[]; - VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[]; - VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[]; - VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[]; -END; - diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak deleted file mode 100644 index fda03c9..0000000 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak +++ /dev/null @@ -1,675 +0,0 @@ -TITLE "VIDEO MODUSE UND CLUT CONTROL"; - --- CREATED BY FREDI ASCHWANDEN - -INCLUDE "lpm_bustri_WORD.inc"; -INCLUDE "lpm_bustri_BYT.inc"; - --- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! --- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! - -SUBDESIGN VIDEO_MOD_MUX_CLUTCTR -( - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - nRSTO : INPUT; - MAIN_CLK : INPUT; - nFB_CS1 : INPUT; - nFB_CS2 : INPUT; - nFB_CS3 : INPUT; - nFB_WR : INPUT; - nFB_OE : INPUT; - FB_SIZE0 : INPUT; - FB_SIZE1 : INPUT; - nFB_BURST : INPUT; - FB_ADR[31..0] : INPUT; - CLK33M : INPUT; - CLK25M : INPUT; - BLITTER_RUN : INPUT; - CLK_VIDEO : INPUT; - VR_D[8..0] : INPUT; - VR_BUSY : INPUT; - COLOR8 : OUTPUT; - ACP_CLUT_RD : OUTPUT; - COLOR1 : OUTPUT; - FALCON_CLUT_RDH : OUTPUT; - FALCON_CLUT_RDL : OUTPUT; - FALCON_CLUT_WR[3..0] : OUTPUT; - ST_CLUT_RD : OUTPUT; - ST_CLUT_WR[1..0] : OUTPUT; - CLUT_MUX_ADR[3..0] : OUTPUT; - HSYNC : OUTPUT; - VSYNC : OUTPUT; - nBLANK : OUTPUT; - nSYNC : OUTPUT; - nPD_VGA : OUTPUT; - FIFO_RDE : OUTPUT; - COLOR2 : OUTPUT; - COLOR4 : OUTPUT; - PIXEL_CLK : OUTPUT; - CLUT_OFF[3..0] : OUTPUT; - BLITTER_ON : OUTPUT; - VIDEO_RAM_CTR[15..0] : OUTPUT; - VIDEO_MOD_TA : OUTPUT; - CCR[23..0] : OUTPUT; - CCSEL[2..0] : OUTPUT; - ACP_CLUT_WR[3..0] : OUTPUT; - INTER_ZEI : OUTPUT; - DOP_FIFO_CLR : OUTPUT; - VIDEO_RECONFIG : OUTPUT; - VR_WR : OUTPUT; - VR_RD : OUTPUT; - CLR_FIFO : OUTPUT; - FB_AD[31..0] : BIDIR; - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -) - -VARIABLE - CLK17M :DFF; - CLK13M :DFF; - ACP_CLUT_CS :NODE; - ACP_CLUT :NODE; - VIDEO_PLL_CONFIG_CS :NODE; - VR_WR :DFF; - VR_DOUT[8..0] :DFFE; - VR_FRQ[7..0] :DFFE; - VIDEO_PLL_RECONFIG_CS :NODE; - VIDEO_RECONFIG :DFF; - FALCON_CLUT_CS :NODE; - FALCON_CLUT :NODE; - ST_CLUT_CS :NODE; - ST_CLUT :NODE; - FB_B[3..0] :NODE; - FB_16B[1..0] :NODE; - ST_SHIFT_MODE[1..0] :DFFE; - ST_SHIFT_MODE_CS :NODE; - FALCON_SHIFT_MODE[10..0] :DFFE; - FALCON_SHIFT_MODE_CS :NODE; - CLUT_MUX_ADR[3..0] :DFF; - CLUT_MUX_AV[1..0][3..0] :DFF; - ACP_VCTR_CS :NODE; - ACP_VCTR[31..0] :DFFE; - CCR_CS :NODE; - CCR[23..0] :DFFE; - ACP_VIDEO_ON :NODE; - SYS_CTR[6..0] :DFFE; - SYS_CTR_CS :NODE; - VDL_LOF[15..0] :DFFE; - VDL_LOF_CS :NODE; - VDL_LWD[15..0] :DFFE; - VDL_LWD_CS :NODE; --- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT - HSYNC :DFF; - HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK - HSYNC_START :DFF; - LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT - VSYNC :DFF; - VSYNC_START :DFFE; - VSYNC_I[2..0] :DFFE; - nBLANK :DFF; - DISP_ON :DFF; - DPO_ZL :DFFE; - DPO_ON :DFF; - DPO_OFF :DFF; - VDTRON :DFF; - VDO_ZL :DFFE; - VDO_ON :DFF; - VDO_OFF :DFF; - VHCNT[11..0] :DFF; - SUB_PIXEL_CNT[6..0] :DFFE; - VVCNT[10..0] :DFFE; - VERZ[2..0][9..0] :DFF; - RAND[6..0] :DFF; - RAND_ON :NODE; - FIFO_RDE :DFF; - CLR_FIFO :DFFE; - START_ZEILE :DFFE; - SYNC_PIX :DFF; - SYNC_PIX1 :DFF; - SYNC_PIX2 :DFF; - CCSEL[2..0] :DFF; - COLOR16 :NODE; - COLOR24 :NODE; --- ATARI RESOLUTION - ATARI_SYNC :NODE; - ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 - ATARI_HH_CS :NODE; - ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480 - ATARI_VH_CS :NODE; - ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240 - ATARI_HL_CS :NODE; - ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240 - ATARI_VL_CS :NODE; --- HORIZONTAL - RAND_LINKS[11..0] :NODE; - HDIS_START[11..0] :NODE; - HDIS_END[11..0] :NODE; - RAND_RECHTS[11..0] :NODE; - HS_START[11..0] :NODE; - H_TOTAL[11..0] :NODE; - HDIS_LEN[11..0] :NODE; - MULF[5..0] :NODE; - VDL_HHT[11..0] :DFFE; - VDL_HHT_CS :NODE; - VDL_HBE[11..0] :DFFE; - VDL_HBE_CS :NODE; - VDL_HDB[11..0] :DFFE; - VDL_HDB_CS :NODE; - VDL_HDE[11..0] :DFFE; - VDL_HDE_CS :NODE; - VDL_HBB[11..0] :DFFE; - VDL_HBB_CS :NODE; - VDL_HSS[11..0] :DFFE; - VDL_HSS_CS :NODE; --- VERTIKAL - RAND_OBEN[10..0] :NODE; - VDIS_START[10..0] :NODE; - VDIS_END[10..0] :NODE; - RAND_UNTEN[10..0] :NODE; - VS_START[10..0] :NODE; - V_TOTAL[10..0] :NODE; - FALCON_VIDEO :NODE; - ST_VIDEO :NODE; - INTER_ZEI :DFF; - DOP_ZEI :DFF; - DOP_FIFO_CLR :DFF; - - VDL_VBE[10..0] :DFFE; - VDL_VBE_CS :NODE; - VDL_VDB[10..0] :DFFE; - VDL_VDB_CS :NODE; - VDL_VDE[10..0] :DFFE; - VDL_VDE_CS :NODE; - VDL_VBB[10..0] :DFFE; - VDL_VBB_CS :NODE; - VDL_VSS[10..0] :DFFE; - VDL_VSS_CS :NODE; - VDL_VFT[10..0] :DFFE; - VDL_VFT_CS :NODE; - VDL_VCT[8..0] :DFFE; - VDL_VCT_CS :NODE; - VDL_VMD[3..0] :DFFE; - VDL_VMD_CS :NODE; - -BEGIN --- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- ADR==1 - # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT --- ACP CLUT -- - ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 - ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; - ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; - CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; ---FALCON CLUT -- - FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 - FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD - FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD - FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; --- ST CLUT -- - ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 - ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; - ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; --- ST SHIFT MODE - ST_SHIFT_MODE[].CLK = MAIN_CLK; - ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 - ST_SHIFT_MODE[] = FB_AD[25..24]; - ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO - COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN - COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN --- FALCON SHIFT MODE - FALCON_SHIFT_MODE[].CLK = MAIN_CLK; - FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 - FALCON_SHIFT_MODE[] = FB_AD[26..16]; - FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; - FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; - COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; --- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS - ACP_VCTR[].CLK = MAIN_CLK; - ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 - ACP_VCTR[31..8] = FB_AD[31..8]; - ACP_VCTR[5..0] = FB_AD[5..0]; - ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; - ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; - ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; - ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; - ACP_VIDEO_ON = ACP_VCTR0; - nPD_VGA = ACP_VCTR1; - -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG - -- HORIZONTAL TIMING 640x480 - ATARI_HH[].CLK = MAIN_CLK; - ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 - ATARI_HH[] = FB_AD[]; - ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; - ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; - ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; - ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 - ATARI_VH[].CLK = MAIN_CLK; - ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 - ATARI_VH[] = FB_AD[]; - ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; - ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; - ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; - ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 - ATARI_HL[].CLK = MAIN_CLK; - ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 - ATARI_HL[] = FB_AD[]; - ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; - ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; - ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; - ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 - ATARI_VL[].CLK = MAIN_CLK; - ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 - ATARI_VL[] = FB_AD[]; - ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; - ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; - ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; - ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; --- VIDEO PLL CONFIG - VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY - VR_WR.CLK = MAIN_CLK; - VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; - VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; - VR_DOUT[].CLK = MAIN_CLK; - VR_DOUT[].ENA = !VR_BUSY; - VR_DOUT[] = VR_D[]; - VR_FRQ[].CLK = MAIN_CLK; - VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; - VR_FRQ[] = FB_AD[23..16]; --- VIDEO PLL RECONFIG - VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 - VIDEO_RECONFIG.CLK = MAIN_CLK; - VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; ------------------------------------------------------------------------------------------------------------------------- - VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; --------------- COLOR MODE IM ACP SETZEN - COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; - COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; - ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; --- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER - ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; - FALCON_VIDEO = ACP_VCTR7; - FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; - ST_VIDEO = ACP_VCTR6; - ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; - CCSEL[].CLK = PIXEL_CLK; - CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION - # B"001" & FALCON_CLUT - # B"100" & ACP_CLUT - # B"101" & COLOR16 - # B"110" & COLOR24 - # B"111" & RAND_ON; --- DIVERSE (VIDEO)-REGISTER ---------------------------- --- RANDFARBE - CCR[].CLK = MAIN_CLK; - CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 - CCR[] = FB_AD[23..0]; - CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; - CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; - CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; ---SYS CTR - SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 - SYS_CTR[].CLK = MAIN_CLK; - SYS_CTR[6..0] = FB_AD[22..16]; - SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; - BLITTER_ON = !SYS_CTR3; ---VDL_LOF - VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 - VDL_LOF[].CLK = MAIN_CLK; - VDL_LOF[] = FB_AD[31..16]; - VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; - VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; ---VDL_LWD - VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 - VDL_LWD[].CLK = MAIN_CLK; - VDL_LWD[] = FB_AD[31..16]; - VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; - VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; --- HORIZONTAL --- VDL_HHT - VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 - VDL_HHT[].CLK = MAIN_CLK; - VDL_HHT[] = FB_AD[27..16]; - VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; - VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; --- VDL_HBE - VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 - VDL_HBE[].CLK = MAIN_CLK; - VDL_HBE[] = FB_AD[27..16]; - VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; - VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; --- VDL_HDB - VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 - VDL_HDB[].CLK = MAIN_CLK; - VDL_HDB[] = FB_AD[27..16]; - VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; - VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; --- VDL_HDE - VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 - VDL_HDE[].CLK = MAIN_CLK; - VDL_HDE[] = FB_AD[27..16]; - VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; - VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; --- VDL_HBB - VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 - VDL_HBB[].CLK = MAIN_CLK; - VDL_HBB[] = FB_AD[27..16]; - VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; - VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; --- VDL_HSS - VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 - VDL_HSS[].CLK = MAIN_CLK; - VDL_HSS[] = FB_AD[27..16]; - VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; - VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; --- VERTIKAL --- VDL_VBE - VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 - VDL_VBE[].CLK = MAIN_CLK; - VDL_VBE[] = FB_AD[26..16]; - VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; - VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; --- VDL_VDB - VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 - VDL_VDB[].CLK = MAIN_CLK; - VDL_VDB[] = FB_AD[26..16]; - VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; - VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; --- VDL_VDE - VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 - VDL_VDE[].CLK = MAIN_CLK; - VDL_VDE[] = FB_AD[26..16]; - VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; - VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; --- VDL_VBB - VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 - VDL_VBB[].CLK = MAIN_CLK; - VDL_VBB[] = FB_AD[26..16]; - VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; - VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; --- VDL_VSS - VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 - VDL_VSS[].CLK = MAIN_CLK; - VDL_VSS[] = FB_AD[26..16]; - VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; - VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; --- VDL_VFT - VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 - VDL_VFT[].CLK = MAIN_CLK; - VDL_VFT[] = FB_AD[26..16]; - VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; - VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; --- VDL_VCT - VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 - VDL_VCT[].CLK = MAIN_CLK; - VDL_VCT[] = FB_AD[24..16]; - VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; - VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; --- VDL_VMD - VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 - VDL_VMD[].CLK = MAIN_CLK; - VDL_VMD[] = FB_AD[19..16]; - VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; ---- REGISTER OUT - FB_AD[31..16] = lpm_bustri_WORD( - ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") - # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) - # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0]) - # VDL_LOF_CS & VDL_LOF[] - # VDL_LWD_CS & VDL_LWD[] - # VDL_HBE_CS & (0,VDL_HBE[]) - # VDL_HDB_CS & (0,VDL_HDB[]) - # VDL_HDE_CS & (0,VDL_HDE[]) - # VDL_HBB_CS & (0,VDL_HBB[]) - # VDL_HSS_CS & (0,VDL_HSS[]) - # VDL_HHT_CS & (0,VDL_HHT[]) - # VDL_VBE_CS & (0,VDL_VBE[]) - # VDL_VDB_CS & (0,VDL_VDB[]) - # VDL_VDE_CS & (0,VDL_VDE[]) - # VDL_VBB_CS & (0,VDL_VBB[]) - # VDL_VSS_CS & (0,VDL_VSS[]) - # VDL_VFT_CS & (0,VDL_VFT[]) - # VDL_VCT_CS & (0,VDL_VCT[]) - # VDL_VMD_CS & (0,VDL_VMD[]) - # ACP_VCTR_CS & ACP_VCTR[31..16] - # ATARI_HH_CS & ATARI_HH[31..16] - # ATARI_VH_CS & ATARI_VH[31..16] - # ATARI_HL_CS & ATARI_HL[31..16] - # ATARI_VL_CS & ATARI_VL[31..16] - # CCR_CS & (0,CCR[23..16]) - # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) - # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") - ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS - # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS - # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS - # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); - - FB_AD[15..0] = lpm_bustri_WORD( - ACP_VCTR_CS & ACP_VCTR[15..0] - # ATARI_HH_CS & ATARI_HH[15..0] - # ATARI_VH_CS & ATARI_VH[15..0] - # ATARI_HL_CS & ATARI_HL[15..0] - # ATARI_VL_CS & ATARI_VL[15..0] - # CCR_CS & CCR[15..0] - ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); - - VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS - # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS - # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS - # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; - --- VIDEO AUSGABE SETZEN - CLK17M.CLK = CLK33M; - CLK17M = !CLK17M; - CLK13M.CLK = CLK25M; - CLK13M = !CLK13M; - PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) - # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) - # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 - # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 - # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; --------------------------------------------------------------- --- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ----------------------------------------------------------------- - HSY_LEN[].CLK = MAIN_CLK; - HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) - # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) - # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 - # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 - # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" - # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" - # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns - - MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR - # 4 & !ST_VIDEO & !VDL_VMD2 - # 16 & ST_VIDEO & VDL_VMD2 - # 32 & ST_VIDEO & !VDL_VMD2; - - - HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN - # 640 & !VDL_VMD2; - --- DOPPELZEILENMODUS - DOP_ZEI.CLK = MAIN_CLK; - DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS - INTER_ZEI.CLK = PIXEL_CLK; - INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC - # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC - DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START - - RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON - # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON - # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- - HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON - # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- - RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON - # HDIS_END[]+1 & !ACP_VIDEO_ON; -- - HS_START[] = VDL_HSS[] & ACP_VIDEO_ON - # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON - # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - - RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON - # 31 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON - # 32 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON - # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO - # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO - # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON - # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC - # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; - VS_START[] = VDL_VSS[] & ACP_VIDEO_ON - # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON - # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 - # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 - # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --- ZÄHLER - LAST.CLK = PIXEL_CLK; - LAST = VHCNT[]==(H_TOTAL[]-2); - VHCNT[].CLK = PIXEL_CLK; - VHCNT[] = (VHCNT[] + 1) & !LAST; - VVCNT[].CLK = PIXEL_CLK; - VVCNT[].ENA = LAST; - VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); --- DISPLAY ON OFF - DPO_ZL.CLK = PIXEL_CLK; - DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[]m*@$!j5s&~O*-GzQ5l{poQbG|T z(v%kIpCHm(P(s31q)DO>mk`2Te*Ztt9p9GoUC%xH+;RSK4~`%uthMHxZ+V{QedpYr z-kpc=nHifJL-y^1K=y(EAiJ{=L-4!*xsPub`JcN2_}9BHApD2+mHd>rf8TM)PyGA# z^Y7d3hCspRJn$dahWzKpzMuC0eBdC*Ax$#Q@(PMd>Kd9_ z+B&+1=Z%a_E|{9x*xK1UI666dUh(qw@%8f$4GX^!fsTxdjf+o6OiE6g{ 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